* RE: [PATCH V4] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
From: David Laight @ 2013-03-12 9:47 UTC (permalink / raw)
To: Jia Hongtao-B38951, Wood Scott-B07421; +Cc: linuxppc-dev, Stuart Yoder
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C15369@039-SN1MPN1-003.039d.mgd.msft.net>
> Is that OK if I use the following code?
...
> if (is_in_pci_mem_space(addr)) {
> if (!user_mode(regs)) {
> ret =3D probe_kernel_address(regs->nip, inst);
>=20
> if (!ret) {
> rd =3D get_rt(inst);
> regs->gpr[rd] =3D 0xffffffff;
> }
> }
Don't you need to check that the instruction is actually
a memory read?
I also know that there are people mapping PCIe addresses
directly into userspace for 'simple' access to things like
fpga devices.
I suspect that such devices are the ones likely to generate
the faulting cycles. So you probably do want to handle
faults from normal userspace addresses.
David
^ permalink raw reply
* [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Chen Yuanquan-B41889 @ 2013-03-12 10:12 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Kumar Gala, Zang Roy-R61911
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B102CFB@039-SN2MPN1-013.039d.mgd.msft.net>
>> -----Original Message-----
>> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
>> fei.zang=freescale.com@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
>> Sent: Tuesday, March 12, 2013 5:23 PM
>> To: Kumar Gala
>> Cc: linuxppc-dev@lists.ozlabs.org
>> Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe
>> controllers
>>
>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>> Rather than do it this way, we should do something like:
>>>
>>> fsl_indirect_read_config() {
>>> link check
>>> if (link)
>>> indirect_read_config()
>>> }
>>>
>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>>
>>> - k
>>>
>> Ok, how about this:
>>
Yeah, this patch can solve the problem of PCI-e bus rescan which a PCI-e
EP is added to RC
after RC booting up. If RC boots up without EP added, the original code
will set the PCI-e
bus as no link even if you add a EP to RC during RC's runtime.
Regards,
Yuanquan
>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
>> ---
>> arch/powerpc/sysdev/fsl_pci.c | 49
>> ++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 45 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c
>> b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -36,6 +36,8 @@
>>
>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>>
>> +static struct pci_ops *indirect_pci_ops;
>> +
>> static void quirk_fsl_pcie_header(struct pci_dev *dev) {
>> u8 hdr_type;
>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct
>> pci_controller
>> *hose)
>> return 0;
>> }
>>
>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
>> devfn,
>> + int offset, int len, u32 *val)
>> +{
>> + struct pci_controller *hose = pci_bus_to_host(bus);
>> +
>> + // check the link status
>> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
>> + u32 ltssm = 0;
>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
>> + if (ltssm < PCIE_LTSSM_L0) {
>> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + } else {
>> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + }
>> + }
>> + return indirect_pci_ops->read(bus, devfn, offset, len, val); }
>> +
>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int
>> devfn,
>> + int offset, int len, u32 val)
>> +{
>> + return indirect_pci_ops->write(bus, devfn, offset, len, val); }
>> +
>> +static struct pci_ops fsl_indirect_pci_ops = {
>> + .read = fsl_indirect_read_config,
>> + .write = fsl_indirect_write_config,
>> +};
>> +
>> +static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
>> + resource_size_t cfg_addr,
>> + resource_size_t cfg_data, u32 flags) {
>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
>> + indirect_pci_ops = hose->ops;
>> + hose->ops = &fsl_indirect_pci_ops;
>> +}
>> +
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>
>> #define MAX_PHYS_ADDR_BITS 40
>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device
>> *pdev, int is_primary)
>> hose->first_busno = bus_range ? bus_range[0] : 0x0;
>> hose->last_busno = bus_range ? bus_range[1] : 0xff;
>>
>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>
>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> /* For PCIE read HEADER_TYPE to identify controler mode */ @@
>> -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
>> if (ret)
>> goto err0;
>> } else {
>> - setup_indirect_pci(hose, rsrc_cfg.start,
>> - rsrc_cfg.start + 4, 0);
>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
>> + rsrc_cfg.start + 4, 0);
>> }
>>
>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>>
>>
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
>
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Rojhalat Ibrahim @ 2013-03-12 10:30 UTC (permalink / raw)
To: Chen Yuanquan-B41889; +Cc: linuxppc-dev, Zang Roy-R61911
In-Reply-To: <513EFF84.3090103@freescale.com>
On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
> >> -----Original Message-----
> >> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> >> fei.zang=freescale.com@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
> >> Sent: Tuesday, March 12, 2013 5:23 PM
> >> To: Kumar Gala
> >> Cc: linuxppc-dev@lists.ozlabs.org
> >> Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe
> >> controllers
> >>
> >> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
> >>> Rather than do it this way, we should do something like:
> >>>
> >>> fsl_indirect_read_config() {
> >>>
> >>> link check
> >>> if (link)
> >>>
> >>> indirect_read_config()
> >>>
> >>> }
> >>>
> >>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
> >>>
> >>> - k
> >>
> >> Ok, how about this:
> Yeah, this patch can solve the problem of PCI-e bus rescan which a PCI-e
> EP is added to RC
> after RC booting up. If RC boots up without EP added, the original code
> will set the PCI-e
> bus as no link even if you add a EP to RC during RC's runtime.
>
> Regards,
> Yuanquan
>
Right. The EP is only added if you first do "echo 1 > /sys/bus/pci/rescan".
Rojhalat
> >> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> >> ---
> >>
> >> arch/powerpc/sysdev/fsl_pci.c | 49
> >>
> >> ++++++++++++++++++++++++++++++++++++++----
> >>
> >> 1 file changed, 45 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/arch/powerpc/sysdev/fsl_pci.c
> >> b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644
> >> --- a/arch/powerpc/sysdev/fsl_pci.c
> >> +++ b/arch/powerpc/sysdev/fsl_pci.c
> >> @@ -36,6 +36,8 @@
> >>
> >> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
> >>
> >> +static struct pci_ops *indirect_pci_ops;
> >> +
> >>
> >> static void quirk_fsl_pcie_header(struct pci_dev *dev) {
> >>
> >> u8 hdr_type;
> >>
> >> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct
> >> pci_controller
> >> *hose)
> >>
> >> return 0;
> >>
> >> }
> >>
> >> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
> >> devfn,
> >> + int offset, int len, u32 *val)
> >> +{
> >> + struct pci_controller *hose = pci_bus_to_host(bus);
> >> +
> >> + // check the link status
> >> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
> >> + u32 ltssm = 0;
> >> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
> >> + if (ltssm < PCIE_LTSSM_L0) {
> >> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >> + } else {
> >> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >> + }
> >> + }
> >> + return indirect_pci_ops->read(bus, devfn, offset, len, val); }
> >> +
> >> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int
> >> devfn,
> >> + int offset, int len, u32 val)
> >> +{
> >> + return indirect_pci_ops->write(bus, devfn, offset, len, val); }
> >> +
> >> +static struct pci_ops fsl_indirect_pci_ops = {
> >> + .read = fsl_indirect_read_config,
> >> + .write = fsl_indirect_write_config,
> >> +};
> >> +
> >> +static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
> >> + resource_size_t cfg_addr,
> >> + resource_size_t cfg_data, u32 flags) {
> >> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
> >> + indirect_pci_ops = hose->ops;
> >> + hose->ops = &fsl_indirect_pci_ops;
> >> +}
> >> +
> >>
> >> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> >>
> >> #define MAX_PHYS_ADDR_BITS 40
> >>
> >> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device
> >> *pdev, int is_primary)
> >>
> >> hose->first_busno = bus_range ? bus_range[0] : 0x0;
> >> hose->last_busno = bus_range ? bus_range[1] : 0xff;
> >>
> >> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >>
> >> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> >>
> >> /* For PCIE read HEADER_TYPE to identify controler mode */ @@
> >>
> >> -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
> >>
> >> if (ret)
> >>
> >> goto err0;
> >>
> >> } else {
> >>
> >> - setup_indirect_pci(hose, rsrc_cfg.start,
> >> - rsrc_cfg.start + 4, 0);
> >> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
> >> + rsrc_cfg.start + 4, 0);
> >>
> >> }
> >>
> >> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
> >>
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Chen Yuanquan-B41889 @ 2013-03-12 11:03 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev, Zang Roy-R61911
In-Reply-To: <2837636.lhg2IyzI4d@pcimr>
On 03/12/2013 06:30 PM, Rojhalat Ibrahim wrote:
> On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
>>>> -----Original Message-----
>>>> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
>>>> fei.zang=freescale.com@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
>>>> Sent: Tuesday, March 12, 2013 5:23 PM
>>>> To: Kumar Gala
>>>> Cc: linuxppc-dev@lists.ozlabs.org
>>>> Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe
>>>> controllers
>>>>
>>>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>>>> Rather than do it this way, we should do something like:
>>>>>
>>>>> fsl_indirect_read_config() {
>>>>>
>>>>> link check
>>>>> if (link)
>>>>>
>>>>> indirect_read_config()
>>>>>
>>>>> }
>>>>>
>>>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>>>>
>>>>> - k
>>>> Ok, how about this:
>> Yeah, this patch can solve the problem of PCI-e bus rescan which a PCI-e
>> EP is added to RC
>> after RC booting up. If RC boots up without EP added, the original code
>> will set the PCI-e
>> bus as no link even if you add a EP to RC during RC's runtime.
>>
>> Regards,
>> Yuanquan
>>
> Right. The EP is only added if you first do "echo 1 > /sys/bus/pci/rescan".
>
> Rojhalat
>
The following patch can solve your issue of "only added if you first ...":
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 5b3771a..c1298d0 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -730,11 +730,12 @@ int __devinit pci_scan_bridge(struct pci_bus *bus,
struct
/* Prevent assigning a bus number that already exists.
* This can happen when a bridge is hot-plugged */
- if (pci_find_bus(pci_domain_nr(bus), max+1))
- goto out;
- child = pci_add_new_bus(bus, dev, ++max);
- if (!child)
- goto out;
+ child = pci_find_bus(pci_domain_nr(bus), max+1);
+ if (!child) {
+ child = pci_add_new_bus(bus, dev, ++max);
+ if (!child)
+ goto out;
+ }
buses = (buses & 0xff000000)
| ((unsigned int)(child->primary) << 0)
| ((unsigned int)(child->secondary) << 8)
There are still some issues about powerpc PCI-e rescan. For example, add
a Intel e1000e
ethernet card or silicon PCI-e_sata to powerpc PCI-e slot and boot the
board. The EP can
work well with their driver. But if you "echo 1 >
/sys/bus/pci/device/xxx/remove" which
corresponds to Intel e1000e ethernet card or silicon PCI-e_sata, then
"echo 1" to rescan,
the device can be rescanned, but it will fail to load the corresponded
driver due to hw_irq
and dma_set_mask error. The following patch can solve the problem, but
not a good method
to solve it.
diff --git a/arch/powerpc/kernel/pci-common.c
b/arch/powerpc/kernel/pci-common.c
index 2476a32..f9b7f0f 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1557,6 +1557,19 @@ int pcibios_enable_device(struct pci_dev *dev,
int mask)
if (ppc_md.pcibios_enable_device_hook(dev))
return -EINVAL;
+ if (!dev->is_added) {
+ set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
+
+ set_dma_ops(&dev->dev, pci_dma_ops);
+ set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
+
+ if (ppc_md.pci_dma_dev_setup)
+ ppc_md.pci_dma_dev_setup(dev);
+
+ pci_read_irq_line(dev);
+ if (ppc_md.pci_irq_fixup)
+ ppc_md.pci_irq_fixup(dev);
+ }
return pci_enable_resources(dev, mask);
}
Regards,
Yuanquan
>>>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
>>>> ---
>>>>
>>>> arch/powerpc/sysdev/fsl_pci.c | 49
>>>>
>>>> ++++++++++++++++++++++++++++++++++++++----
>>>>
>>>> 1 file changed, 45 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c
>>>> b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644
>>>> --- a/arch/powerpc/sysdev/fsl_pci.c
>>>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>>>> @@ -36,6 +36,8 @@
>>>>
>>>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>>>>
>>>> +static struct pci_ops *indirect_pci_ops;
>>>> +
>>>>
>>>> static void quirk_fsl_pcie_header(struct pci_dev *dev) {
>>>>
>>>> u8 hdr_type;
>>>>
>>>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct
>>>> pci_controller
>>>> *hose)
>>>>
>>>> return 0;
>>>>
>>>> }
>>>>
>>>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
>>>> devfn,
>>>> + int offset, int len, u32 *val)
>>>> +{
>>>> + struct pci_controller *hose = pci_bus_to_host(bus);
>>>> +
>>>> + // check the link status
>>>> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
>>>> + u32 ltssm = 0;
>>>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
>>>> + if (ltssm < PCIE_LTSSM_L0) {
>>>> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>>>> + } else {
>>>> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>>>> + }
>>>> + }
>>>> + return indirect_pci_ops->read(bus, devfn, offset, len, val); }
>>>> +
>>>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int
>>>> devfn,
>>>> + int offset, int len, u32 val)
>>>> +{
>>>> + return indirect_pci_ops->write(bus, devfn, offset, len, val); }
>>>> +
>>>> +static struct pci_ops fsl_indirect_pci_ops = {
>>>> + .read = fsl_indirect_read_config,
>>>> + .write = fsl_indirect_write_config,
>>>> +};
>>>> +
>>>> +static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
>>>> + resource_size_t cfg_addr,
>>>> + resource_size_t cfg_data, u32 flags) {
>>>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
>>>> + indirect_pci_ops = hose->ops;
>>>> + hose->ops = &fsl_indirect_pci_ops;
>>>> +}
>>>> +
>>>>
>>>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>>>
>>>> #define MAX_PHYS_ADDR_BITS 40
>>>>
>>>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device
>>>> *pdev, int is_primary)
>>>>
>>>> hose->first_busno = bus_range ? bus_range[0] : 0x0;
>>>> hose->last_busno = bus_range ? bus_range[1] : 0xff;
>>>>
>>>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>>>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>>>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>>>
>>>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>>>>
>>>> /* For PCIE read HEADER_TYPE to identify controler mode */ @@
>>>>
>>>> -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
>>>>
>>>> if (ret)
>>>>
>>>> goto err0;
>>>>
>>>> } else {
>>>>
>>>> - setup_indirect_pci(hose, rsrc_cfg.start,
>>>> - rsrc_cfg.start + 4, 0);
>>>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
>>>> + rsrc_cfg.start + 4, 0);
>>>>
>>>> }
>>>>
>>>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>>>>
>>>> _______________________________________________
>>>> Linuxppc-dev mailing list
>>>> Linuxppc-dev@lists.ozlabs.org
>>>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
>
^ permalink raw reply related
* [PATCH] powerpc: Fix -mcmodel=medium breakage in prom_init.c
From: Anton Blanchard @ 2013-03-12 11:51 UTC (permalink / raw)
To: agraf, benh, aaro.koskinen, amodra; +Cc: linuxppc-dev
Commit 5ac47f7a6efb (powerpc: Relocate prom_init.c on 64bit) made
prom_init.c position independent by manually relocating its entries
in the TOC.
We get the address of the TOC entries with the __prom_init_toc_start
linker symbol. If __prom_init_toc_start ends up as an entry in the
TOC then we need to add an offset to get the current address. This is
the case for older toolchains.
On the other hand, if we have a newer toolchain that supports
-mcmodel=medium then __prom_init_toc_start will be created by a
relative offset from r2 (the TOC pointer). Since r2 has already been
relocated, nothing more needs to be done. Adding an offset in this
case is wrong and Aaro Koskinen and Alexander Graf have noticed noticed
G5 and OpenBIOS breakage.
Alan Modra suggested we just use r2 to get at the TOC which is simpler
and works with both old and new toolchains.
Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Thanks Aaro for reporting this, and Alexander for an initial
fix. This tested ok for me with both a new and an old toolchain,
but would appreciate if you could double check it fixes your issues
too.
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 7f7fb7f..13f8d16 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2832,11 +2832,13 @@ static void unreloc_toc(void)
{
}
#else
-static void __reloc_toc(void *tocstart, unsigned long offset,
- unsigned long nr_entries)
+static void __reloc_toc(unsigned long offset, unsigned long nr_entries)
{
unsigned long i;
- unsigned long *toc_entry = (unsigned long *)tocstart;
+ unsigned long *toc_entry;
+
+ /* Get the start of the TOC by using r2 directly. */
+ asm volatile("addi %0,2,-0x8000" : "=b" (toc_entry));
for (i = 0; i < nr_entries; i++) {
*toc_entry = *toc_entry + offset;
@@ -2850,8 +2852,7 @@ static void reloc_toc(void)
unsigned long nr_entries =
(__prom_init_toc_end - __prom_init_toc_start) / sizeof(long);
- /* Need to add offset to get at __prom_init_toc_start */
- __reloc_toc(__prom_init_toc_start + offset, offset, nr_entries);
+ __reloc_toc(offset, nr_entries);
mb();
}
@@ -2864,8 +2865,7 @@ static void unreloc_toc(void)
mb();
- /* __prom_init_toc_start has been relocated, no need to add offset */
- __reloc_toc(__prom_init_toc_start, -offset, nr_entries);
+ __reloc_toc(-offset, nr_entries);
}
#endif
#endif
^ permalink raw reply related
* [PATCH -V3 1/3] powerpc: Make VSID_BITS* dependency explicit
From: Aneesh Kumar K.V @ 2013-03-12 12:08 UTC (permalink / raw)
To: benh, paulus, David Gibson; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
VSID_BITS and VSID_BITS_1T depends on the context bits and user esid
bits. Make the dependency explicit
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 2fdb47a..5f8c2bd 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -381,21 +381,22 @@ extern void slb_set_size(u16 size);
* hash collisions.
*/
+#define CONTEXT_BITS 19
+#define USER_ESID_BITS 18
+#define USER_ESID_BITS_1T 6
+
/*
* This should be computed such that protovosid * vsid_mulitplier
* doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
*/
#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_256M 38
+#define VSID_BITS_256M (CONTEXT_BITS + USER_ESID_BITS + 1)
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T 26
+#define VSID_BITS_1T (CONTEXT_BITS + USER_ESID_BITS_1T + 1)
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
-#define CONTEXT_BITS 19
-#define USER_ESID_BITS 18
-#define USER_ESID_BITS_1T 6
#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
--
1.7.10
^ permalink raw reply related
* [PATCH -V3 2/3] powerpc: Update kernel VSID range
From: Aneesh Kumar K.V @ 2013-03-12 12:08 UTC (permalink / raw)
To: benh, paulus, David Gibson; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1363090131-14545-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
This patch change the kernel VSID range so that we limit VSID_BITS to 37.
This enables us to support 64TB with 65 bit VA (37+28). Without this patch
we have boot hangs on platforms that only support 65 bit VA.
With this patch we now have proto vsid generated as below:
We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
from mmu context id and effective segment id of the address.
For user processes max context id is limited to ((1ul << 19) - 5)
for kernel space, we use the top 4 context ids to map address as below
0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 115 +++++++++++++++++----------------
arch/powerpc/kernel/exceptions-64s.S | 34 +++++++---
arch/powerpc/mm/hash_utils_64.c | 20 ++++--
arch/powerpc/mm/mmu_context_hash64.c | 11 +---
arch/powerpc/mm/slb_low.S | 49 +++++++-------
arch/powerpc/mm/tlb_hash64.c | 2 +-
6 files changed, 125 insertions(+), 106 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 5f8c2bd..90f0ab1 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -343,17 +343,16 @@ extern void slb_set_size(u16 size);
/*
* VSID allocation (256MB segment)
*
- * We first generate a 38-bit "proto-VSID". For kernel addresses this
- * is equal to the ESID | 1 << 37, for user addresses it is:
- * (context << USER_ESID_BITS) | (esid & ((1U << USER_ESID_BITS) - 1)
+ * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
+ * from mmu context id and effective segment id of the address.
*
- * This splits the proto-VSID into the below range
- * 0 - (2^(CONTEXT_BITS + USER_ESID_BITS) - 1) : User proto-VSID range
- * 2^(CONTEXT_BITS + USER_ESID_BITS) - 2^(VSID_BITS) : Kernel proto-VSID range
- *
- * We also have CONTEXT_BITS + USER_ESID_BITS = VSID_BITS - 1
- * That is, we assign half of the space to user processes and half
- * to the kernel.
+ * For user processes max context id is limited to ((1ul << 19) - 6)
+ * for kernel space, we use the top 4 context ids to map address as below
+ * NOTE: each context only support 64TB now.
+ * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
+ * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
+ * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
+ * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
*
* The proto-VSIDs are then scrambled into real VSIDs with the
* multiplicative hash:
@@ -363,22 +362,19 @@ extern void slb_set_size(u16 size);
* VSID_MULTIPLIER is prime, so in particular it is
* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
* Because the modulus is 2^n-1 we can compute it efficiently without
- * a divide or extra multiply (see below).
- *
- * This scheme has several advantages over older methods:
+ * a divide or extra multiply (see below). The scramble function gives
+ * robust scattering in the hash * table (at least based on some initial
+ * results).
*
- * - We have VSIDs allocated for every kernel address
- * (i.e. everything above 0xC000000000000000), except the very top
- * segment, which simplifies several things.
+ * We also consider VSID 0 special. We use VSID 0 for slb entries mapping
+ * bad address. This enables us to consolidate bad address handling in
+ * hash_page.
*
- * - We allow for USER_ESID_BITS significant bits of ESID and
- * CONTEXT_BITS bits of context for user addresses.
- * i.e. 64T (46 bits) of address space for up to half a million contexts.
- *
- * - The scramble function gives robust scattering in the hash
- * table (at least based on some initial results). The previous
- * method was more susceptible to pathological cases giving excessive
- * hash collisions.
+ * We also need to avoid the last segment of the last context, because that
+ * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
+ * because of the modulo operation in vsid scramble. But the vmemmap
+ * (which is what uses region 0xf) will never be close to 64TB in size
+ * (it's 56 bytes per page of system memory).
*/
#define CONTEXT_BITS 19
@@ -386,15 +382,25 @@ extern void slb_set_size(u16 size);
#define USER_ESID_BITS_1T 6
/*
+ * 256MB segment
+ * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments
+ * available for user + kernel mapping. The top 4 contexts are used for
+ * kernel mapping. Each segment contains 2^28 bytes. Each
+ * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
+ * (19 == 37 + 28 - 46).
+ */
+#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 5)
+
+/*
* This should be computed such that protovosid * vsid_mulitplier
* doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
*/
#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_256M (CONTEXT_BITS + USER_ESID_BITS + 1)
+#define VSID_BITS_256M (CONTEXT_BITS + USER_ESID_BITS)
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T (CONTEXT_BITS + USER_ESID_BITS_1T + 1)
+#define VSID_BITS_1T (CONTEXT_BITS + USER_ESID_BITS_1T)
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
@@ -422,7 +428,8 @@ extern void slb_set_size(u16 size);
srdi rx,rt,VSID_BITS_##size; \
clrldi rt,rt,(64-VSID_BITS_##size); \
add rt,rt,rx; /* add high and low bits */ \
- /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
+ /* NOTE: explanation based on VSID_BITS_##size = 36 \
+ * Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
* 2^36-1+2^28-1. That in particular means that if r3 >= \
* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
* the bit clear, r3 already has the answer we want, if it \
@@ -514,34 +521,6 @@ typedef struct {
})
#endif /* 1 */
-/*
- * This is only valid for addresses >= PAGE_OFFSET
- * The proto-VSID space is divided into two class
- * User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
- * kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
- *
- * With KERNEL_START at 0xc000000000000000, the proto vsid for
- * the kernel ends up with 0xc00000000 (36 bits). With 64TB
- * support we need to have kernel proto-VSID in the
- * [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
- */
-static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
-{
- unsigned long proto_vsid;
- /*
- * We need to make sure proto_vsid for the kernel is
- * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
- */
- if (ssize == MMU_SEGSIZE_256M) {
- proto_vsid = ea >> SID_SHIFT;
- proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
- return vsid_scramble(proto_vsid, 256M);
- }
- proto_vsid = ea >> SID_SHIFT_1T;
- proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
- return vsid_scramble(proto_vsid, 1T);
-}
-
/* Returns the segment size indicator for a user address */
static inline int user_segment_size(unsigned long addr)
{
@@ -551,10 +530,15 @@ static inline int user_segment_size(unsigned long addr)
return MMU_SEGSIZE_256M;
}
-/* This is only valid for user addresses (which are below 2^44) */
static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
int ssize)
{
+ /*
+ * Bad address. We return VSID 0 for that
+ */
+ if ((ea & ~REGION_MASK) >= PGTABLE_RANGE)
+ return 0;
+
if (ssize == MMU_SEGSIZE_256M)
return vsid_scramble((context << USER_ESID_BITS)
| (ea >> SID_SHIFT), 256M);
@@ -562,6 +546,25 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
| (ea >> SID_SHIFT_1T), 1T);
}
+/*
+ * This is only valid for addresses >= PAGE_OFFSET
+ *
+ * For kernel space, we use the top 4 context ids to map address as below
+ * 0x7fffc - [ 0xc000000000000000 - 0xc0003fffffffffff ]
+ * 0x7fffd - [ 0xd000000000000000 - 0xd0003fffffffffff ]
+ * 0x7fffe - [ 0xe000000000000000 - 0xe0003fffffffffff ]
+ * 0x7ffff - [ 0xf000000000000000 - 0xf0003fffffffffff ]
+ */
+static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
+{
+ unsigned long context;
+
+ /*
+ * kernel take the top 4 context from the available range
+ */
+ context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1;
+ return get_vsid(context, ea, ssize);
+}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_MMU_HASH64_H_ */
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 4665e82..c90dec0 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1268,20 +1268,36 @@ do_ste_alloc:
_GLOBAL(do_stab_bolted)
stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
+ mfspr r11,SPRN_DAR /* ea */
+ /*
+ * check for bad kernel/user address
+ * (ea & ~REGION_MASK) >= PGTABLE_RANGE
+ */
+ rldicr. r9,r11,4,(63 - 46 - 4)
+ li r9,0 /* VSID = 0 for bad address */
+ bne- 0f
+
+ /*
+ * Calculate VSID:
+ * This is the kernel vsid, we take the top for context from
+ * the range. context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
+ * Here we know that (ea >> 60) == 0xc
+ */
+ lis r9,8
+ subi r9,r9,4 /* context */
+
+ srdi r10,r11,SID_SHIFT
+ rldimi r10,r9,USER_ESID_BITS,0 /* proto vsid */
+ ASM_VSID_SCRAMBLE(r10, r9, 256M)
+ rldic r9,r10,12,16 /* r9 = vsid << 12 */
+
+0:
/* Hash to the primary group */
ld r10,PACASTABVIRT(r13)
- mfspr r11,SPRN_DAR
- srdi r11,r11,28
+ srdi r11,r11,SID_SHIFT
rldimi r10,r11,7,52 /* r10 = first ste of the group */
- /* Calculate VSID */
- /* This is a kernel address, so protovsid = ESID | 1 << 37 */
- li r9,0x1
- rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
- ASM_VSID_SCRAMBLE(r11, r9, 256M)
- rldic r9,r11,12,16 /* r9 = vsid << 12 */
-
/* Search the primary group for a free entry */
1: ld r11,0(r10) /* Test valid bit of the current ste */
andi. r11,r11,0x80
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 3a292be..bfeab83 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -194,6 +194,11 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
unsigned long tprot = prot;
+ /*
+ * If we hit a bad address return error.
+ */
+ if (!vsid)
+ return -1;
/* Make kernel text executable */
if (overlaps_kernel_text(vaddr, vaddr + step))
tprot &= ~HPTE_R_N;
@@ -921,11 +926,6 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
ea, access, trap);
- if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
- DBG_LOW(" out of pgtable range !\n");
- return 1;
- }
-
/* Get region & vsid */
switch (REGION_ID(ea)) {
case USER_REGION_ID:
@@ -956,6 +956,11 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
}
DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
+ /* Bad address. */
+ if (!vsid) {
+ DBG_LOW("Bad address!\n");
+ return 1;
+ }
/* Get pgdir */
pgdir = mm->pgd;
if (pgdir == NULL)
@@ -1125,6 +1130,8 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
/* Get VSID */
ssize = user_segment_size(ea);
vsid = get_vsid(mm->context.id, ea, ssize);
+ if (!vsid)
+ return;
/* Hash doesn't like irqs */
local_irq_save(flags);
@@ -1217,6 +1224,9 @@ static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
+ /* Don't create HPTE entries for bad address */
+ if (!vsid)
+ return;
ret = ppc_md.hpte_insert(hpteg, vpn, __pa(vaddr),
mode, HPTE_V_BOLTED,
mmu_linear_psize, mmu_kernel_ssize);
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 40bc5b0..f11630d 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -29,15 +29,6 @@
static DEFINE_SPINLOCK(mmu_context_lock);
static DEFINE_IDA(mmu_context_ida);
-/*
- * 256MB segment
- * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments
- * available for user mappings. Each segment contains 2^28 bytes. Each
- * context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
- * (19 == 37 + 28 - 46).
- */
-#define MAX_CONTEXT ((1UL << CONTEXT_BITS) - 1)
-
int __init_new_context(void)
{
int index;
@@ -56,7 +47,7 @@ again:
else if (err)
return err;
- if (index > MAX_CONTEXT) {
+ if (index > (MAX_USER_CONTEXT)) {
spin_lock(&mmu_context_lock);
ida_remove(&mmu_context_ida, index);
spin_unlock(&mmu_context_lock);
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 1a16ca2..946c617 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -31,10 +31,15 @@
* No other registers are examined or changed.
*/
_GLOBAL(slb_allocate_realmode)
- /* r3 = faulting address */
+ /*
+ * check for bad kernel/user address
+ * (ea & ~REGION_MASK) >= PGTABLE_RANGE
+ */
+ rldicr. r9,r3,4,(63 - 46 - 4)
+ bne- 8f
srdi r9,r3,60 /* get region */
- srdi r10,r3,28 /* get esid */
+ srdi r10,r3,SID_SHIFT /* get esid */
cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
@@ -56,12 +61,13 @@ _GLOBAL(slb_allocate_realmode)
*/
_GLOBAL(slb_miss_kernel_load_linear)
li r11,0
- li r9,0x1
/*
- * for 1T we shift 12 bits more. slb_finish_load_1T will do
- * the necessary adjustment
+ * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
*/
- rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
+ rldicl r9,r3,4,62
+ addis r9,r9,8
+ subi r9,r9,4
+
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
@@ -91,24 +97,19 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
_GLOBAL(slb_miss_kernel_load_io)
li r11,0
6:
- li r9,0x1
/*
- * for 1T we shift 12 bits more. slb_finish_load_1T will do
- * the necessary adjustment
+ * context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
*/
- rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
+ rldicl r9,r3,4,62
+ addis r9,r9,8
+ subi r9,r9,4
+
BEGIN_FTR_SECTION
b slb_finish_load
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
b slb_finish_load_1T
-0: /* user address: proto-VSID = context << 15 | ESID. First check
- * if the address is within the boundaries of the user region
- */
- srdi. r9,r10,USER_ESID_BITS
- bne- 8f /* invalid ea bits set */
-
-
+0:
/* when using slices, we extract the psize off the slice bitmaps
* and then we need to get the sllp encoding off the mmu_psize_defs
* array.
@@ -164,15 +165,13 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
ld r9,PACACONTEXTID(r13)
BEGIN_FTR_SECTION
cmpldi r10,0x1000
-END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
- rldimi r10,r9,USER_ESID_BITS,0
-BEGIN_FTR_SECTION
bge slb_finish_load_1T
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
b slb_finish_load
8: /* invalid EA */
li r10,0 /* BAD_VSID */
+ li r9,0 /* BAD_VSID */
li r11,SLB_VSID_USER /* flags don't much matter */
b slb_finish_load
@@ -221,8 +220,6 @@ _GLOBAL(slb_allocate_user)
/* get context to calculate proto-VSID */
ld r9,PACACONTEXTID(r13)
- rldimi r10,r9,USER_ESID_BITS,0
-
/* fall through slb_finish_load */
#endif /* __DISABLED__ */
@@ -231,9 +228,10 @@ _GLOBAL(slb_allocate_user)
/*
* Finish loading of an SLB entry and return
*
- * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
+ * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
*/
slb_finish_load:
+ rldimi r10,r9,USER_ESID_BITS,0
ASM_VSID_SCRAMBLE(r10,r9,256M)
/*
* bits above VSID_BITS_256M need to be ignored from r10
@@ -298,10 +296,11 @@ _GLOBAL(slb_compare_rr_to_size)
/*
* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
*
- * r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
+ * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
*/
slb_finish_load_1T:
- srdi r10,r10,40-28 /* get 1T ESID */
+ srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
+ rldimi r10,r9,USER_ESID_BITS_1T,0
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 0d82ef5..023ec8a 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -82,11 +82,11 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
if (!is_kernel_addr(addr)) {
ssize = user_segment_size(addr);
vsid = get_vsid(mm->context.id, addr, ssize);
- WARN_ON(vsid == 0);
} else {
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
+ WARN_ON(vsid == 0);
vpn = hpt_vpn(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
--
1.7.10
^ permalink raw reply related
* [PATCH -V3 3/3] powerpc: rename USER_ESID_BITS* to ESID_BITS*
From: Aneesh Kumar K.V @ 2013-03-12 12:08 UTC (permalink / raw)
To: benh, paulus, David Gibson; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <1363090131-14545-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Now we use ESID_BITS of kernel address to build proto vsid. So rename
USER_ESIT_BITS to ESID_BITS
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 16 ++++++++--------
arch/powerpc/kernel/exceptions-64s.S | 2 +-
arch/powerpc/kvm/book3s_64_mmu_host.c | 4 ++--
arch/powerpc/mm/pgtable_64.c | 2 +-
arch/powerpc/mm/slb_low.S | 4 ++--
5 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 90f0ab1..c322100 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -378,12 +378,12 @@ extern void slb_set_size(u16 size);
*/
#define CONTEXT_BITS 19
-#define USER_ESID_BITS 18
-#define USER_ESID_BITS_1T 6
+#define ESID_BITS 18
+#define ESID_BITS_1T 6
/*
* 256MB segment
- * The proto-VSID space has 2^(CONTEX_BITS + USER_ESID_BITS) - 1 segments
+ * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
* available for user + kernel mapping. The top 4 contexts are used for
* kernel mapping. Each segment contains 2^28 bytes. Each
* context maps 2^46 bytes (64TB) so we can support 2^19-1 contexts
@@ -396,15 +396,15 @@ extern void slb_set_size(u16 size);
* doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
*/
#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_256M (CONTEXT_BITS + USER_ESID_BITS)
+#define VSID_BITS_256M (CONTEXT_BITS + ESID_BITS)
#define VSID_MODULUS_256M ((1UL<<VSID_BITS_256M)-1)
#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
-#define VSID_BITS_1T (CONTEXT_BITS + USER_ESID_BITS_1T)
+#define VSID_BITS_1T (CONTEXT_BITS + ESID_BITS_1T)
#define VSID_MODULUS_1T ((1UL<<VSID_BITS_1T)-1)
-#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
+#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
/*
* This macro generates asm code to compute the VSID scramble
@@ -540,9 +540,9 @@ static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
return 0;
if (ssize == MMU_SEGSIZE_256M)
- return vsid_scramble((context << USER_ESID_BITS)
+ return vsid_scramble((context << ESID_BITS)
| (ea >> SID_SHIFT), 256M);
- return vsid_scramble((context << USER_ESID_BITS_1T)
+ return vsid_scramble((context << ESID_BITS_1T)
| (ea >> SID_SHIFT_1T), 1T);
}
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index c90dec0..1b7c73a 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1288,7 +1288,7 @@ _GLOBAL(do_stab_bolted)
subi r9,r9,4 /* context */
srdi r10,r11,SID_SHIFT
- rldimi r10,r9,USER_ESID_BITS,0 /* proto vsid */
+ rldimi r10,r9,ESID_BITS,0 /* proto vsid */
ASM_VSID_SCRAMBLE(r10, r9, 256M)
rldic r9,r10,12,16 /* r9 = vsid << 12 */
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index ead58e3..5d7d29a 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -326,8 +326,8 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
vcpu3s->context_id[0] = err;
vcpu3s->proto_vsid_max = ((vcpu3s->context_id[0] + 1)
- << USER_ESID_BITS) - 1;
- vcpu3s->proto_vsid_first = vcpu3s->context_id[0] << USER_ESID_BITS;
+ << ESID_BITS) - 1;
+ vcpu3s->proto_vsid_first = vcpu3s->context_id[0] << ESID_BITS;
vcpu3s->proto_vsid_next = vcpu3s->proto_vsid_first;
kvmppc_mmu_hpte_init(vcpu);
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index e212a27..654258f 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -61,7 +61,7 @@
#endif
#ifdef CONFIG_PPC_STD_MMU_64
-#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#if TASK_SIZE_USER64 > (1UL << (ESID_BITS + SID_SHIFT))
#error TASK_SIZE_USER64 exceeds user VSID range
#endif
#endif
diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 946c617..9e44b58 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S
@@ -231,7 +231,7 @@ _GLOBAL(slb_allocate_user)
* r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
*/
slb_finish_load:
- rldimi r10,r9,USER_ESID_BITS,0
+ rldimi r10,r9,ESID_BITS,0
ASM_VSID_SCRAMBLE(r10,r9,256M)
/*
* bits above VSID_BITS_256M need to be ignored from r10
@@ -300,7 +300,7 @@ _GLOBAL(slb_compare_rr_to_size)
*/
slb_finish_load_1T:
srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
- rldimi r10,r9,USER_ESID_BITS_1T,0
+ rldimi r10,r9,ESID_BITS_1T,0
ASM_VSID_SCRAMBLE(r10,r9,1T)
/*
* bits above VSID_BITS_1T need to be ignored from r10
--
1.7.10
^ permalink raw reply related
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Rojhalat Ibrahim @ 2013-03-12 12:12 UTC (permalink / raw)
To: Chen Yuanquan-B41889; +Cc: linuxppc-dev, Zang Roy-R61911
In-Reply-To: <513F0B8B.4090607@freescale.com>
On Tuesday 12 March 2013 19:03:39 Chen Yuanquan-B41889 wrote:
> On 03/12/2013 06:30 PM, Rojhalat Ibrahim wrote:
> > On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
> >>>> -----Original Message-----
> >>>> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> >>>> fei.zang=freescale.com@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
> >>>> Sent: Tuesday, March 12, 2013 5:23 PM
> >>>> To: Kumar Gala
> >>>> Cc: linuxppc-dev@lists.ozlabs.org
> >>>> Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe
> >>>> controllers
> >>>>
> >>>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
> >>>>> Rather than do it this way, we should do something like:
> >>>>>
> >>>>> fsl_indirect_read_config() {
> >>>>>
> >>>>> link check
> >>>>> if (link)
> >>>>>
> >>>>> indirect_read_config()
> >>>>>
> >>>>> }
> >>>>>
> >>>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
> >>>>>
> >>>>> - k
> >>>>
> >>>> Ok, how about this:
> >> Yeah, this patch can solve the problem of PCI-e bus rescan which a PCI-e
> >> EP is added to RC
> >> after RC booting up. If RC boots up without EP added, the original code
> >> will set the PCI-e
> >> bus as no link even if you add a EP to RC during RC's runtime.
> >>
> >> Regards,
> >> Yuanquan
> >
> > Right. The EP is only added if you first do "echo 1 >
> > /sys/bus/pci/rescan".
> >
> > Rojhalat
>
> The following patch can solve your issue of "only added if you first ...":
Actually I don't have a problem with having to do a rescan before the device
is added. In my case the device is a FPGA which is configured at runtime. So I
can simply trigger the rescan after configuration.
For my purposes the patch I proposed is sufficient for now.
The additional changes suggested by you should probably go into separate
patches.
Rojhalat
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 5b3771a..c1298d0 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -730,11 +730,12 @@ int __devinit pci_scan_bridge(struct pci_bus *bus,
> struct
>
> /* Prevent assigning a bus number that already exists.
> * This can happen when a bridge is hot-plugged */
> - if (pci_find_bus(pci_domain_nr(bus), max+1))
> - goto out;
> - child = pci_add_new_bus(bus, dev, ++max);
> - if (!child)
> - goto out;
> + child = pci_find_bus(pci_domain_nr(bus), max+1);
> + if (!child) {
> + child = pci_add_new_bus(bus, dev, ++max);
> + if (!child)
> + goto out;
> + }
> buses = (buses & 0xff000000)
>
> | ((unsigned int)(child->primary) << 0)
> | ((unsigned int)(child->secondary) << 8)
>
> There are still some issues about powerpc PCI-e rescan. For example, add
> a Intel e1000e
> ethernet card or silicon PCI-e_sata to powerpc PCI-e slot and boot the
> board. The EP can
> work well with their driver. But if you "echo 1 >
> /sys/bus/pci/device/xxx/remove" which
> corresponds to Intel e1000e ethernet card or silicon PCI-e_sata, then
> "echo 1" to rescan,
> the device can be rescanned, but it will fail to load the corresponded
> driver due to hw_irq
> and dma_set_mask error. The following patch can solve the problem, but
> not a good method
> to solve it.
>
> diff --git a/arch/powerpc/kernel/pci-common.c
> b/arch/powerpc/kernel/pci-common.c
> index 2476a32..f9b7f0f 100644
> --- a/arch/powerpc/kernel/pci-common.c
> +++ b/arch/powerpc/kernel/pci-common.c
> @@ -1557,6 +1557,19 @@ int pcibios_enable_device(struct pci_dev *dev,
> int mask)
> if (ppc_md.pcibios_enable_device_hook(dev))
> return -EINVAL;
>
> + if (!dev->is_added) {
> + set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
> +
> + set_dma_ops(&dev->dev, pci_dma_ops);
> + set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
> +
> + if (ppc_md.pci_dma_dev_setup)
> + ppc_md.pci_dma_dev_setup(dev);
> +
> + pci_read_irq_line(dev);
> + if (ppc_md.pci_irq_fixup)
> + ppc_md.pci_irq_fixup(dev);
> + }
> return pci_enable_resources(dev, mask);
> }
>
>
> Regards,
> Yuanquan
>
> >>>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> >>>> ---
> >>>>
> >>>> arch/powerpc/sysdev/fsl_pci.c | 49
> >>>>
> >>>> ++++++++++++++++++++++++++++++++++++++----
> >>>>
> >>>> 1 file changed, 45 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c
> >>>> b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644
> >>>> --- a/arch/powerpc/sysdev/fsl_pci.c
> >>>> +++ b/arch/powerpc/sysdev/fsl_pci.c
> >>>> @@ -36,6 +36,8 @@
> >>>>
> >>>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
> >>>>
> >>>> +static struct pci_ops *indirect_pci_ops;
> >>>> +
> >>>>
> >>>> static void quirk_fsl_pcie_header(struct pci_dev *dev) {
> >>>>
> >>>> u8 hdr_type;
> >>>>
> >>>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct
> >>>> pci_controller
> >>>> *hose)
> >>>>
> >>>> return 0;
> >>>>
> >>>> }
> >>>>
> >>>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
> >>>> devfn,
> >>>> + int offset, int len, u32 *val)
> >>>> +{
> >>>> + struct pci_controller *hose = pci_bus_to_host(bus);
> >>>> +
> >>>> + // check the link status
> >>>> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
> >>>> + u32 ltssm = 0;
> >>>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
> >>>> + if (ltssm < PCIE_LTSSM_L0) {
> >>>> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >>>> + } else {
> >>>> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >>>> + }
> >>>> + }
> >>>> + return indirect_pci_ops->read(bus, devfn, offset, len, val); }
> >>>> +
> >>>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int
> >>>> devfn,
> >>>> + int offset, int len, u32 val)
> >>>> +{
> >>>> + return indirect_pci_ops->write(bus, devfn, offset, len, val); }
> >>>> +
> >>>> +static struct pci_ops fsl_indirect_pci_ops = {
> >>>> + .read = fsl_indirect_read_config,
> >>>> + .write = fsl_indirect_write_config,
> >>>> +};
> >>>> +
> >>>> +static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
> >>>> + resource_size_t cfg_addr,
> >>>> + resource_size_t cfg_data, u32 flags) {
> >>>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
> >>>> + indirect_pci_ops = hose->ops;
> >>>> + hose->ops = &fsl_indirect_pci_ops;
> >>>> +}
> >>>> +
> >>>>
> >>>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> >>>>
> >>>> #define MAX_PHYS_ADDR_BITS 40
> >>>>
> >>>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device
> >>>> *pdev, int is_primary)
> >>>>
> >>>> hose->first_busno = bus_range ? bus_range[0] : 0x0;
> >>>> hose->last_busno = bus_range ? bus_range[1] : 0xff;
> >>>>
> >>>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >>>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >>>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >>>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >>>>
> >>>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> >>>>
> >>>> /* For PCIE read HEADER_TYPE to identify controler mode */ @@
> >>>>
> >>>> -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
> >>>>
> >>>> if (ret)
> >>>>
> >>>> goto err0;
> >>>>
> >>>> } else {
> >>>>
> >>>> - setup_indirect_pci(hose, rsrc_cfg.start,
> >>>> - rsrc_cfg.start + 4, 0);
> >>>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
> >>>> + rsrc_cfg.start + 4, 0);
> >>>>
> >>>> }
> >>>>
> >>>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
> >>>>
> >>>> _______________________________________________
> >>>> Linuxppc-dev mailing list
> >>>> Linuxppc-dev@lists.ozlabs.org
> >>>> https://lists.ozlabs.org/listinfo/linuxppc-dev
> >>
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] powerpc/85xx: add CONFIG_E1000E to corenet64_smp_defconfig
From: Scott Wood @ 2013-03-12 20:03 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
This is a commonly used ethernet card, especially with mainline kernels
which lack datapath support.o
Other changes are due to running savedefconfig.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/configs/corenet64_smp_defconfig | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 3d139fa..37363a3 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -1,14 +1,12 @@
CONFIG_PPC64=y
CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=2
-CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -78,6 +76,7 @@ CONFIG_SATA_FSL=y
CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
+CONFIG_E1000E=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
@@ -140,6 +139,5 @@ CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_FSL_CAAM=y
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH -V2 2/2] powerpc: Update kernel VSID range
From: Geoff Levand @ 2013-03-12 20:11 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: phileas-fogg, paulus, linuxppc-dev, David Gibson
In-Reply-To: <87vc8xrsp1.fsf@linux.vnet.ibm.com>
Hi Aneesh,
On Tue, 2013-03-12 at 12:49 +0530, Aneesh Kumar K.V wrote:
> Done. I added this as a patch on top of the series.
I tried to test this against v3.8, but applying it failed:
Applying: powerpc: Update kernel VSID range
error: patch failed: arch/powerpc/mm/slb_low.S:66
Could you please make a set that applies to 3.8? Thanks.
-Geoff
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Kumar Gala @ 2013-03-12 20:44 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev
In-Reply-To: <2399353.017i5G1tnZ@pcimr>
On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>=20
>> Rather than do it this way, we should do something like:
>>=20
>> fsl_indirect_read_config() {
>> link check
>> if (link)
>> indirect_read_config()
>> }
>>=20
>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>=20
>> - k
>>=20
>=20
> Ok, how about this:
>=20
I'd rather we just export indirect_read_config() & =
indirect_write_config() from indirect_pci.c and call the functions =
directly. Adding a global and call them via a function pointer seems =
wrong to me.
- k
>=20
> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 49=20
> ++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 45 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
> index 682084d..693db9f 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -36,6 +36,8 @@
>=20
> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>=20
> +static struct pci_ops *indirect_pci_ops;
> +
> static void quirk_fsl_pcie_header(struct pci_dev *dev)
> {
> u8 hdr_type;
> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct =
pci_controller=20
> *hose)
> return 0;
> }
>=20
> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int =
devfn,
> + int offset, int len, u32 *val)
> +{
> + struct pci_controller *hose =3D pci_bus_to_host(bus);
> +=09
> + // check the link status
> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) =
{
> + u32 ltssm =3D 0;
> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
> + if (ltssm < PCIE_LTSSM_L0) {
> + hose->indirect_type |=3D =
PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + } else {
> + hose->indirect_type &=3D =
~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + }
> + }
> + return indirect_pci_ops->read(bus, devfn, offset, len, val);
> +}
> +
> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned =
int devfn,
> + int offset, int len, u32 val)
> +{
> + return indirect_pci_ops->write(bus, devfn, offset, len, val);
> +}
> +
> +static struct pci_ops fsl_indirect_pci_ops =3D
> +{
> + .read =3D fsl_indirect_read_config,
> + .write =3D fsl_indirect_write_config,
> +};
> +
> +static void __init fsl_setup_indirect_pci(struct pci_controller* =
hose,
> + resource_size_t cfg_addr,
> + resource_size_t cfg_data, u32 =
flags)
> +{
> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
> + indirect_pci_ops =3D hose->ops;
> + hose->ops =3D &fsl_indirect_pci_ops;
> +}
> +
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>=20
> #define MAX_PHYS_ADDR_BITS 40
> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device =
*pdev,=20
> int is_primary)
> hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
> hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
>=20
> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>=20
> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> /* For PCIE read HEADER_TYPE to identify controler mode =
*/
> @@ -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node =
*dev)
> if (ret)
> goto err0;
> } else {
> - setup_indirect_pci(hose, rsrc_cfg.start,
> - rsrc_cfg.start + 4, 0);
> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
> + rsrc_cfg.start + 4, 0);
> }
>=20
> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>=20
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Add platform_device declaration to fsl_pci.h
From: Kumar Gala @ 2013-03-12 20:46 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Li Yang-R58472
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C11ED4@039-SN1MPN1-003.039d.mgd.msft.net>
On Mar 10, 2013, at 9:36 PM, Jia Hongtao-B38951 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Saturday, March 09, 2013 4:38 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
>> Subject: Re: [PATCH] powerpc/85xx: Add platform_device declaration to
>> fsl_pci.h
>>=20
>>=20
>> On Mar 4, 2013, at 2:40 AM, Jia Hongtao wrote:
>>=20
>>> mpc85xx_pci_err_probe(struct platform_device *op) need =
platform_device
>>> declaration for definition. Otherwise, it will cause compile error =
if
>>> any files including fsl_pci.h without declaration of =
platform_device.
>>>=20
>>> Signed-off-by: Jia Hongtao <B38951@freescale.com>
>>> ---
>>> arch/powerpc/sysdev/fsl_pci.h | 2 ++
>>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>>=20
>>=20
>> Where does the compile error show up?
>>=20
>> - k
>=20
> The function mpc85xx_pci_err_probe(struct platform_device *op) need
> *platform_device* declaration so <linux/platform_device.h> must be
> included.=20
>=20
> For now there is no compile error occurred just because the file that
> need fsl_pci.h happened to include <linux/platform_device.h> already.
>=20
> If not the compile error log will be like this:
> "
> In file included from arch/powerpc/kernel/traps.c:62:0:
> arch/powerpc/sysdev/fsl_pci.h:108:34: error: 'struct platform_device' =
declared inside parameter list
> arch/powerpc/sysdev/fsl_pci.h:108:34: error: its scope is only this =
definition or declaration, which is probably not what you want
> "
>=20
> You mean I have to show the compile error log in patch description?
Not necessarily, I'm just trying to decide if we should include =
<linux/platform_device.h> or just do:
struct platform_device;
near the top of fsl_pci.h.
>=20
> Thanks.
> -Hongtao.
>=20
>>=20
>>> diff --git a/arch/powerpc/sysdev/fsl_pci.h
>>> b/arch/powerpc/sysdev/fsl_pci.h index c495c00..df66721 100644
>>> --- a/arch/powerpc/sysdev/fsl_pci.h
>>> +++ b/arch/powerpc/sysdev/fsl_pci.h
>>> @@ -14,6 +14,8 @@
>>> #ifndef __POWERPC_FSL_PCI_H
>>> #define __POWERPC_FSL_PCI_H
>>>=20
>>> +#include <linux/platform_device.h>
>>> +
>>> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and
>> Status */
>>> #define PCIE_LTSSM_L0 0x16 /* L0 state */
>>> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block =
version
>> Rev2.2 */
>>> --
>>> 1.7.5.1
>>>=20
>>=20
>=20
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Kumar Gala @ 2013-03-12 20:48 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev
In-Reply-To: <92335390-A05A-4E1D-9D07-A69896768A57@kernel.crashing.org>
On Mar 12, 2013, at 3:44 PM, Kumar Gala wrote:
>=20
> On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
>=20
>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>>=20
>>> Rather than do it this way, we should do something like:
>>>=20
>>> fsl_indirect_read_config() {
>>> link check
>>> if (link)
>>> indirect_read_config()
>>> }
>>>=20
>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>>=20
>>> - k
>>>=20
>>=20
>> Ok, how about this:
>>=20
>=20
> I'd rather we just export indirect_read_config() & =
indirect_write_config() from indirect_pci.c and call the functions =
directly. Adding a global and call them via a function pointer seems =
wrong to me.
>=20
> - k
Also, can you base this patch on my powerpc.git next branch as =
fsl_pci.{c,h} have some changes in them.
- k
>=20
>>=20
>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
>> ---
>> arch/powerpc/sysdev/fsl_pci.c | 49=20
>> ++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 45 insertions(+), 4 deletions(-)
>>=20
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
>> index 682084d..693db9f 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -36,6 +36,8 @@
>>=20
>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>>=20
>> +static struct pci_ops *indirect_pci_ops;
>> +
>> static void quirk_fsl_pcie_header(struct pci_dev *dev)
>> {
>> u8 hdr_type;
>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct =
pci_controller=20
>> *hose)
>> return 0;
>> }
>>=20
>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned =
int devfn,
>> + int offset, int len, u32 *val)
>> +{
>> + struct pci_controller *hose =3D pci_bus_to_host(bus);
>> +=09
>> + // check the link status
>> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) =
{
>> + u32 ltssm =3D 0;
>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
>> + if (ltssm < PCIE_LTSSM_L0) {
>> + hose->indirect_type |=3D =
PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + } else {
>> + hose->indirect_type &=3D =
~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + }
>> + }
>> + return indirect_pci_ops->read(bus, devfn, offset, len, val);
>> +}
>> +
>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned =
int devfn,
>> + int offset, int len, u32 val)
>> +{
>> + return indirect_pci_ops->write(bus, devfn, offset, len, val);
>> +}
>> +
>> +static struct pci_ops fsl_indirect_pci_ops =3D
>> +{
>> + .read =3D fsl_indirect_read_config,
>> + .write =3D fsl_indirect_write_config,
>> +};
>> +
>> +static void __init fsl_setup_indirect_pci(struct pci_controller* =
hose,
>> + resource_size_t cfg_addr,
>> + resource_size_t cfg_data, u32 =
flags)
>> +{
>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
>> + indirect_pci_ops =3D hose->ops;
>> + hose->ops =3D &fsl_indirect_pci_ops;
>> +}
>> +
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>=20
>> #define MAX_PHYS_ADDR_BITS 40
>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device =
*pdev,=20
>> int is_primary)
>> hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
>> hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
>>=20
>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>=20
>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> /* For PCIE read HEADER_TYPE to identify controler mode =
*/
>> @@ -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node =
*dev)
>> if (ret)
>> goto err0;
>> } else {
>> - setup_indirect_pci(hose, rsrc_cfg.start,
>> - rsrc_cfg.start + 4, 0);
>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
>> + rsrc_cfg.start + 4, 0);
>> }
>>=20
>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH][v2] powerpc: add missing deo arch category to e500mc/e5500 dts
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev
In-Reply-To: <1362523149-19393-2-git-send-email-stuart.yoder@freescale.com>
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder <stuart.yoder@freescale.com>
>
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
>
> -v2
> -deo is EREF specific, changed name of property
>
> arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi | 1 +
> arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi | 1 +
> 2 files changed, 2 insertions(+)
applied to next
- k
^ permalink raw reply
* Re: [PATCH]qonverge/usb: Add first usb controller node
From: Gala Kumar-B11780 @ 2013-03-12 21:14 UTC (permalink / raw)
To: Mehresh Ramneek-B31383
Cc: <devicetree-discuss@lists.ozlabs.org>,
<linuxppc-dev@lists.ozlabs.org>
In-Reply-To: <1362041205-18171-1-git-send-email-ramneek.mehresh@freescale.com>
On Feb 28, 2013, at 2:46 AM, Ramneek Mehresh wrote:
> Add first usb controller node for qonverge qoriq platforms like
> B4860, etc
>=20
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> ---
> Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.gi=
t
> (branch next)
>=20
> arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi | 41 ++++++++++++++++++=
+++++
> 1 file changed, 41 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH][v3] powerpc/e6500: Add architecture categories for e6500 cores
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev
In-Reply-To: <1362523149-19393-1-git-send-email-stuart.yoder@freescale.com>
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder <stuart.yoder@freescale.com>
>=20
> -also define a binding for fsl,eref-* properties
>=20
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
>=20
> -v3
> -converted EREF specific properties to fsl,eref-*
>=20
> .../devicetree/bindings/powerpc/fsl/cpus.txt | 21 +++++++
> arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65 =
++++++++++++++++++++
> 2 files changed, 86 insertions(+)
> create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
> create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Reserve a partition of NOR flash for QE ucode firmware
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Jiucheng Xu; +Cc: linuxppc-dev
In-Reply-To: <1361846016-9023-1-git-send-email-Jiucheng.Xu@freescale.com>
On Feb 25, 2013, at 8:33 PM, Jiucheng Xu wrote:
> Due to the partition of JFFS2 overlaps with QE ucode firmware, So JFFS2
> will break QE ucode. Shrink JFFS2's partition to reserve the space of
> QE ucode firmware.
>
> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
> ---
> arch/powerpc/boot/dts/p1021rdb-pc.dtsi | 12 ++++++++++--
> 1 files changed, 10 insertions(+), 2 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: add CONFIG_E1000E to corenet64_smp_defconfig
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20130312200340.GA22145@home.buserror.net>
On Mar 12, 2013, at 3:03 PM, Scott Wood wrote:
> This is a commonly used ethernet card, especially with mainline kernels
> which lack datapath support.o
>
> Other changes are due to running savedefconfig.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>
> arch/powerpc/configs/corenet64_smp_defconfig | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
fixed up and applied to next
- k
^ permalink raw reply
* Re: [PATCH][V3] powerpc: remove the PPC_CLOCK dependency
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: <Yuantian.Tang@freescale.com>; +Cc: linuxppc-dev, R58472
In-Reply-To: <1363070583-23197-1-git-send-email-Yuantian.Tang@freescale.com>
On Mar 12, 2013, at 1:43 AM, <Yuantian.Tang@freescale.com> =
<Yuantian.Tang@freescale.com> wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
>=20
> Config FSL_SOC does not depend on PPC_CLOCK anymore since the =
following
> commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
> Config CPM does not use PPC_CLOCK either currently. So remove them.
>=20
> PPC_CLOCK also keeps Freescale PowerPC archtecture from supporting =
COMMON_CLK.
>=20
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
> v3: modified the description
> v2: correct the title
>=20
> arch/powerpc/Kconfig | 1 -
> arch/powerpc/platforms/Kconfig | 1 -
> 2 files changed, 0 insertions(+), 2 deletions(-)
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree.
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Vakul Garg
In-Reply-To: <1362525360-23136-1-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Vakul Garg <vakul@freescale.com>
>=20
> Add device tree for SEC (crypto engine) version 5.0 used on T4240.
>=20
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 =
+++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 5/8 v2] powerpc/fsl-booke: Add initial silicon device tree for
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362686336-5426-1-git-send-email-galak@kernel.crashing.org>
On Mar 7, 2013, at 1:58 PM, Kumar Gala wrote:
> Enable a baseline T4240 SoC to boot. There are several things missing
> from the device trees for T4240:
>=20
> * Proper PAMU topology information
> * DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
> * Prefetch Manager
> * Thermal monitor unit
> * Interlaken
>=20
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: York Sun <yorksun@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * Added thread ids to cpu nodes
> * removed clock-frequency from PCI nodes as we dont use it
>=20
> arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 307 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 127 +++++++++++
> 5 files changed, 557 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-3-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
> the Power Book-E Architecture. However there are some minor differences
> between it and other Book-E implementations.
>
> Add support to parse SPRN_TLB1PS for the variable page sizes supported.
> In the future this should be expanded for more page sizes supported on
> e6500 as well as other MMU features.
>
> This patch is based on code from Scott Wood.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/mm/tlb_nohash.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-2-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Roy ZANG <tie-fei.zang@freescale.com>
>
> The T4240 utilizes a new PCIe controller block that has some minor
> programming model differences from previous versions.
>
> The major one that impacts initialization is how we determine the link
> state. On the 3.x controllers we have a memory mapped SoC register
> instead of a PCI config register that reports the link state.
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 29 ++++++++++++++++++++++++++---
> arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++
> 2 files changed, 37 insertions(+), 3 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-6-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/t4240qds.dts | 220 =
++++++++++++++++++++++++++++++++++++
> 1 file changed, 220 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/t4240qds.dts
applied to next
- k=
^ permalink raw reply
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