* Re: [PATCH 5/6][v4]: perf: Create a sysfs entry for Power event format
From: Michael Ellerman @ 2013-03-13 0:15 UTC (permalink / raw)
To: Paul Mackerras
Cc: Andi Kleen, Peter Zijlstra, robert.richter, Anton Blanchard,
linux-kernel, Stephane Eranian, linuxppc-dev, Ingo Molnar,
Arnaldo Carvalho de Melo, Sukadev Bhattiprolu, Jiri Olsa
In-Reply-To: <20130312092740.GC30591@iris.ozlabs.ibm.com>
On Tue, Mar 12, 2013 at 08:27:40PM +1100, Paul Mackerras wrote:
> On Tue, Mar 05, 2013 at 09:48:26PM -0800, Sukadev Bhattiprolu wrote:
> > Michael Ellerman [michael@ellerman.id.au] wrote:
> > | I suspect Arnaldo was either waiting for an ACK from Ben, or was
> > | expecting Ben to take it?
> >
> > Arnaldo, here is an updated patch. If it is acked by Paul Mackerras,
> > Michael Ellerman or Ben, will you add it to your tree so the whole
> > patchset comes from one place ?
> >
> > Sukadev
> >
> > ---
> > >From 50c7a46f14083c0ed10d66b7aed66ba76e798550 Mon Sep 17 00:00:00 2001
> > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> > Date: Tue, 5 Mar 2013 21:20:56 -0800
> > Subject: [PATCH] [PATCH 5/6][v4]: perf Create a sysfs format entry for Power7 events
> >
> > Create a sysfs entry, '/sys/bus/event_source/devices/cpu/format/event'
> > which describes the format of the POWER7 PMU events.
> >
> > This code is based on corresponding code in x86.
> >
> > Changelog[v4]: [Michael Ellerman, Paul Mckerras] The event format is different
> > for other POWER cpus. So move the code to POWER7-specific,
> > power7-pmu.c Also, the POWER7 format uses bits 0-19 not 0-20.
> >
> > Changelog[v2]: [Jiri Osla] Use PMU_FORMAT_ATTR rather than duplicating code.
> >
> > Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>
> Acked-by: Paul Mackerras <paulus@samba.org>
Tested-by: Michael Ellerman <michael@ellerman.id.au>
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: Fix -mcmodel=medium breakage in prom_init.c
From: Aaro Koskinen @ 2013-03-12 22:11 UTC (permalink / raw)
To: Anton Blanchard; +Cc: linuxppc-dev, agraf, amodra
In-Reply-To: <20130312225151.2faeb395@kryten>
Hi,
On Tue, Mar 12, 2013 at 10:51:51PM +1100, Anton Blanchard wrote:
> Commit 5ac47f7a6efb (powerpc: Relocate prom_init.c on 64bit) made
> prom_init.c position independent by manually relocating its entries
> in the TOC.
>
> We get the address of the TOC entries with the __prom_init_toc_start
> linker symbol. If __prom_init_toc_start ends up as an entry in the
> TOC then we need to add an offset to get the current address. This is
> the case for older toolchains.
>
> On the other hand, if we have a newer toolchain that supports
> -mcmodel=medium then __prom_init_toc_start will be created by a
> relative offset from r2 (the TOC pointer). Since r2 has already been
> relocated, nothing more needs to be done. Adding an offset in this
> case is wrong and Aaro Koskinen and Alexander Graf have noticed noticed
> G5 and OpenBIOS breakage.
>
> Alan Modra suggested we just use r2 to get at the TOC which is simpler
> and works with both old and new toolchains.
>
> Reported-by: Alexander Graf <agraf@suse.de>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>
> Thanks Aaro for reporting this, and Alexander for an initial
> fix. This tested ok for me with both a new and an old toolchain,
> but would appreciate if you could double check it fixes your issues
> too.
This seems to fix the issue also for me, so:
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Thanks,
A.
> diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
> index 7f7fb7f..13f8d16 100644
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -2832,11 +2832,13 @@ static void unreloc_toc(void)
> {
> }
> #else
> -static void __reloc_toc(void *tocstart, unsigned long offset,
> - unsigned long nr_entries)
> +static void __reloc_toc(unsigned long offset, unsigned long nr_entries)
> {
> unsigned long i;
> - unsigned long *toc_entry = (unsigned long *)tocstart;
> + unsigned long *toc_entry;
> +
> + /* Get the start of the TOC by using r2 directly. */
> + asm volatile("addi %0,2,-0x8000" : "=b" (toc_entry));
>
> for (i = 0; i < nr_entries; i++) {
> *toc_entry = *toc_entry + offset;
> @@ -2850,8 +2852,7 @@ static void reloc_toc(void)
> unsigned long nr_entries =
> (__prom_init_toc_end - __prom_init_toc_start) / sizeof(long);
>
> - /* Need to add offset to get at __prom_init_toc_start */
> - __reloc_toc(__prom_init_toc_start + offset, offset, nr_entries);
> + __reloc_toc(offset, nr_entries);
>
> mb();
> }
> @@ -2864,8 +2865,7 @@ static void unreloc_toc(void)
>
> mb();
>
> - /* __prom_init_toc_start has been relocated, no need to add offset */
> - __reloc_toc(__prom_init_toc_start, -offset, nr_entries);
> + __reloc_toc(-offset, nr_entries);
> }
> #endif
> #endif
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] powerpc/qe: remove useless Kconfig default
From: Paul Bolle @ 2013-03-12 21:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev, linux-kernel
The Kconfig entry for QE_USB contains
default y if USB_GADGET_FSL_QE
But USB_GADGET_FSL_QE got removed in commit
193ab2a6070039e7ee2b9b9bebea754a7c52fd1b ("usb: gadget: allow multiple
gadgets to be built"). This default will therefor never be set and can
be removed.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
---
0) Tested with "make ARCH=powerpc menuconfig" and "make ARCH=powerpc
oldconfig" (before and after the patch). Enough to see this patch didn't
obviously break stuff.
1) I don't really understand commit
193ab2a6070039e7ee2b9b9bebea754a7c52fd1b. Was its point that we replace
USB_GADGET_FSL_QE with USB_FSL_QE? I couldn't tell and chose not to
actually change any behavior.
arch/powerpc/sysdev/qe_lib/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 41ac3df..33caf44 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,6 +22,5 @@ config UCC
config QE_USB
bool
- default y if USB_GADGET_FSL_QE
help
QE USB Controller support
--
1.7.11.7
^ permalink raw reply related
* Re: [PATCH 1/1] serial/mpc52xx_uart: fix psc clock name for mpc512x
From: Anatolij Gustschin @ 2013-03-12 21:29 UTC (permalink / raw)
To: Matteo Facchinetti; +Cc: Matteo Facchinetti, linuxppc-dev
In-Reply-To: <1363123037-4926-1-git-send-email-matteo.facchinetti@sirius-es.it>
Hi,
On Tue, 12 Mar 2013 22:17:17 +0100
Matteo Facchinetti <matteo.facchinetti@sirius-es.it> wrote:
> From: Matteo Facchinetti <engineering@sirius-es.it>
>
> On platform mpc512x, PSC clock name registered by clk_register()
> (clock.c:703) has _mclk suffix.
> In mpc512x uart device driver, PSC clock name has _clk suffix.
>
> So change PSC clock name in UART device driver using registered clock.
This bug is already fixed in the tty tree [1].
Thanks,
Anatolij
[1] https://git.kernel.org/cgit/linux/kernel/git/gregkh/tty.git/commit/?h=tty-linus&id=09081e5b47f6842669bb645e015deedf191244f4
^ permalink raw reply
* [PATCH 1/1] serial/mpc52xx_uart: fix psc clock name for mpc512x
From: Matteo Facchinetti @ 2013-03-12 21:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Matteo Facchinetti, Anatolij Gustschin
From: Matteo Facchinetti <engineering@sirius-es.it>
On platform mpc512x, PSC clock name registered by clk_register()
(clock.c:703) has _mclk suffix.
In mpc512x uart device driver, PSC clock name has _clk suffix.
So change PSC clock name in UART device driver using registered clock.
Signed-off-by: Matteo Facchinetti <engineering@sirius-es.it>
---
drivers/tty/serial/mpc52xx_uart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/mpc52xx_uart.c b/drivers/tty/serial/mpc52xx_uart.c
index c0e1fad..018bad9 100644
--- a/drivers/tty/serial/mpc52xx_uart.c
+++ b/drivers/tty/serial/mpc52xx_uart.c
@@ -550,7 +550,7 @@ static int mpc512x_psc_clock(struct uart_port *port, int enable)
return 0;
psc_num = (port->mapbase & 0xf00) >> 8;
- snprintf(clk_name, sizeof(clk_name), "psc%d_clk", psc_num);
+ snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num);
psc_clk = clk_get(port->dev, clk_name);
if (IS_ERR(psc_clk)) {
dev_err(port->dev, "Failed to get PSC clock entry!\n");
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH V4] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
From: Scott Wood @ 2013-03-12 21:24 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421, David Laight, linuxppc-dev@lists.ozlabs.org,
Stuart Yoder
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C15369@039-SN1MPN1-003.039d.mgd.msft.net>
On 03/12/2013 02:40:39 AM, Jia Hongtao-B38951 wrote:
>=20
>=20
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Saturday, March 09, 2013 8:49 AM
> > To: Jia Hongtao-B38951
> > Cc: Wood Scott-B07421; David Laight; linuxppc-dev@lists.ozlabs.org;
> > Stuart Yoder
> > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler to =20
> fix
> > PCIe erratum on mpc85xx
> >
> > On 03/08/2013 02:01:46 AM, Jia Hongtao-B38951 wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: Friday, March 08, 2013 12:38 AM
> > > > To: Jia Hongtao-B38951
> > > > Cc: David Laight; Wood Scott-B07421; =20
> linuxppc-dev@lists.ozlabs.org;
> > > > Stuart Yoder
> > > > Subject: Re: [PATCH V4] powerpc/85xx: Add machine check handler =20
> to
> > > fix
> > > > PCIe erratum on mpc85xx
> > > >
> > > > On 03/07/2013 02:06:05 AM, Jia Hongtao-B38951 wrote:
> > > > > Here is the ideas from Scott:
> > > > > "
> > > > > > + if (is_in_pci_mem_space(addr)) {
> > > > > > + inst =3D *(unsigned int *)regs->nip;
> > > > >
> > > > > Be careful about taking a fault here. A simple TLB miss =20
> should be
> > > > > safe given that we shouldn't be accessing PCIe in the middle =20
> of
> > > > > exception code, but what if the mapping has gone away (e.g. a
> > > > > userspace driver had its code munmap()ed or swapped out)? =20
> What if
> > > > > permissions allow execute but not read (not sure if Linux will
> > > allow
> > > > > this, but the hardware does)?
> > > > >
> > > > > What if it happened in a KVM guest? You can't access guest
> > > addresses
> > > > > directly.
> > > > > "
> > > >
> > > > That means you need to be careful about how you read the
> > > instruction, not
> > > > that you shouldn't do it at all.
> > > >
> > > > -Scott
> > >
> > > I agree.
> > >
> > > Do you have a more secure way to get the instruction?
> > > Or what should be done to avoid permission break issue?
> >
> > probe_kernel_address() should take care of userspace issues. As for
> > KVM, if you see MSR_GS set, bail out and don't apply the workaround.
> > Let KVM/QEMU deal with it as it wishes (e.g. reflect to the guest =20
> and
> > let its machine check handler do the skipping). On PR-mode KVM =20
> (e.g.
> > on e500v2-based chips) there is no MSR_GS and it just looks like
> > userspace code -- for now just pretend it is user mode.
> >
> > -Scott
>=20
> Hi Scott,
>=20
> Is that OK if I use the following code?
>=20
> u32 inst;
> int ret;
>=20
> if (is_in_pci_mem_space(addr)) {
> if (!user_mode(regs)) {
> ret =3D probe_kernel_address(regs->nip, inst);
Hmm, seems there's no probe_user_address() -- for userspace we =20
basically want the same thing minus the KERNEL_DS. See =20
arch/powerpc/perf/callchain.c for an example.
You also need to skip this if (regs->msr & MSR_GS) as I mentioned above.
> if (!ret) {
> rd =3D get_rt(inst);
> regs->gpr[rd] =3D 0xffffffff;
> }
Check whether the instruction is a load, as David pointed out. Also =20
check the size of the load, whether it was load with update =20
instruction, etc.
-Scott=
^ permalink raw reply
* Re: [PATCH 7/8] powerpc/fsl-booke: Add initial T4240QDS board support
From: Kumar Gala @ 2013-03-12 21:16 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-7-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> Some minor changes to the common corenet_ds.c code are needed to =
support
> the T4240QDS:
> * Add support for "fsl,qoriq-pcie-v3.0" controller
> * Bump max # of IRQs to 512 (T4240 supports more interrupts than
> previous SoCs).
>=20
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/platforms/85xx/Kconfig | 17 ++++++
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/corenet_ds.c | 5 +-
> arch/powerpc/platforms/85xx/t4240_qds.c | 98 =
++++++++++++++++++++++++++++++
> 4 files changed, 120 insertions(+), 1 deletion(-)
> create mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 8/8] powerpc/85xx: Update corenet64_smp_defconfig for T4240
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-8-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:16 PM, Kumar Gala wrote:
> * Add support for up to 24 cores on T4240 (includes threads)
> * Enable AltiVec support (on T4240)
> * Add T4240QDS board into build
> * Other changes are due to general kernel update of defconfig
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/configs/corenet64_smp_defconfig | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 6/8] powerpc/fsl-booke: Add initial T4240QDS board device
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-6-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/t4240qds.dts | 220 =
++++++++++++++++++++++++++++++++++++
> 1 file changed, 220 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/t4240qds.dts
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 2/8] powerpc/85xx: Add support for FSL PCIe controller v3.0
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-2-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Roy ZANG <tie-fei.zang@freescale.com>
>
> The T4240 utilizes a new PCIe controller block that has some minor
> programming model differences from previous versions.
>
> The major one that impacts initialization is how we determine the link
> state. On the 3.x controllers we have a memory mapped SoC register
> instead of a PCI config register that reports the link state.
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 29 ++++++++++++++++++++++++++---
> arch/powerpc/sysdev/fsl_pci.h | 11 +++++++++++
> 2 files changed, 37 insertions(+), 3 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 3/8] powerpc/fsl-booke: Support detection of page sizes on
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362525360-23136-3-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> The e6500 core used on T4240 and B4860 SoCs from FSL implements MMUv2 of
> the Power Book-E Architecture. However there are some minor differences
> between it and other Book-E implementations.
>
> Add support to parse SPRN_TLB1PS for the variable page sizes supported.
> In the future this should be expanded for more page sizes supported on
> e6500 as well as other MMU features.
>
> This patch is based on code from Scott Wood.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/mm/tlb_nohash.c | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH 5/8 v2] powerpc/fsl-booke: Add initial silicon device tree for
From: Kumar Gala @ 2013-03-12 21:15 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1362686336-5426-1-git-send-email-galak@kernel.crashing.org>
On Mar 7, 2013, at 1:58 PM, Kumar Gala wrote:
> Enable a baseline T4240 SoC to boot. There are several things missing
> from the device trees for T4240:
>=20
> * Proper PAMU topology information
> * DPAA related nodes (Qman, Bman, Fman, Rman, DCE)
> * Prefetch Manager
> * Thermal monitor unit
> * Interlaken
>=20
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: York Sun <yorksun@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> * Added thread ids to cpu nodes
> * removed clock-frequency from PCI nodes as we dont use it
>=20
> arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi | 41 ++++
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 307 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 127 +++++++++++
> 5 files changed, 557 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 1/8] powerpc/85xx: Added SEC-5.0 device tree.
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Vakul Garg
In-Reply-To: <1362525360-23136-1-git-send-email-galak@kernel.crashing.org>
On Mar 5, 2013, at 5:15 PM, Kumar Gala wrote:
> From: Vakul Garg <vakul@freescale.com>
>=20
> Add device tree for SEC (crypto engine) version 5.0 used on T4240.
>=20
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi | 109 =
+++++++++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH][V3] powerpc: remove the PPC_CLOCK dependency
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: <Yuantian.Tang@freescale.com>; +Cc: linuxppc-dev, R58472
In-Reply-To: <1363070583-23197-1-git-send-email-Yuantian.Tang@freescale.com>
On Mar 12, 2013, at 1:43 AM, <Yuantian.Tang@freescale.com> =
<Yuantian.Tang@freescale.com> wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
>=20
> Config FSL_SOC does not depend on PPC_CLOCK anymore since the =
following
> commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines)
> Config CPM does not use PPC_CLOCK either currently. So remove them.
>=20
> PPC_CLOCK also keeps Freescale PowerPC archtecture from supporting =
COMMON_CLK.
>=20
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
> v3: modified the description
> v2: correct the title
>=20
> arch/powerpc/Kconfig | 1 -
> arch/powerpc/platforms/Kconfig | 1 -
> 2 files changed, 0 insertions(+), 2 deletions(-)
applied to next
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: add CONFIG_E1000E to corenet64_smp_defconfig
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20130312200340.GA22145@home.buserror.net>
On Mar 12, 2013, at 3:03 PM, Scott Wood wrote:
> This is a commonly used ethernet card, especially with mainline kernels
> which lack datapath support.o
>
> Other changes are due to running savedefconfig.
>
> Signed-off-by: Scott Wood <scottwood@freescale.com>
> ---
>
> arch/powerpc/configs/corenet64_smp_defconfig | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
fixed up and applied to next
- k
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Reserve a partition of NOR flash for QE ucode firmware
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Jiucheng Xu; +Cc: linuxppc-dev
In-Reply-To: <1361846016-9023-1-git-send-email-Jiucheng.Xu@freescale.com>
On Feb 25, 2013, at 8:33 PM, Jiucheng Xu wrote:
> Due to the partition of JFFS2 overlaps with QE ucode firmware, So JFFS2
> will break QE ucode. Shrink JFFS2's partition to reserve the space of
> QE ucode firmware.
>
> Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
> ---
> arch/powerpc/boot/dts/p1021rdb-pc.dtsi | 12 ++++++++++--
> 1 files changed, 10 insertions(+), 2 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [PATCH][v3] powerpc/e6500: Add architecture categories for e6500 cores
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev
In-Reply-To: <1362523149-19393-1-git-send-email-stuart.yoder@freescale.com>
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder <stuart.yoder@freescale.com>
>=20
> -also define a binding for fsl,eref-* properties
>=20
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
>=20
> -v3
> -converted EREF specific properties to fsl,eref-*
>=20
> .../devicetree/bindings/powerpc/fsl/cpus.txt | 21 +++++++
> arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65 =
++++++++++++++++++++
> 2 files changed, 86 insertions(+)
> create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
> create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH]qonverge/usb: Add first usb controller node
From: Gala Kumar-B11780 @ 2013-03-12 21:14 UTC (permalink / raw)
To: Mehresh Ramneek-B31383
Cc: <devicetree-discuss@lists.ozlabs.org>,
<linuxppc-dev@lists.ozlabs.org>
In-Reply-To: <1362041205-18171-1-git-send-email-ramneek.mehresh@freescale.com>
On Feb 28, 2013, at 2:46 AM, Ramneek Mehresh wrote:
> Add first usb controller node for qonverge qoriq platforms like
> B4860, etc
>=20
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> ---
> Applies on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.gi=
t
> (branch next)
>=20
> arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi | 41 ++++++++++++++++++=
+++++
> 1 file changed, 41 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
applied to next
- k=
^ permalink raw reply
* Re: [PATCH][v2] powerpc: add missing deo arch category to e500mc/e5500 dts
From: Kumar Gala @ 2013-03-12 21:14 UTC (permalink / raw)
To: Stuart Yoder; +Cc: linuxppc-dev
In-Reply-To: <1362523149-19393-2-git-send-email-stuart.yoder@freescale.com>
On Mar 5, 2013, at 4:39 PM, Stuart Yoder wrote:
> From: Stuart Yoder <stuart.yoder@freescale.com>
>
> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
> ---
>
> -v2
> -deo is EREF specific, changed name of property
>
> arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi | 1 +
> arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi | 1 +
> 2 files changed, 2 insertions(+)
applied to next
- k
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Kumar Gala @ 2013-03-12 20:48 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev
In-Reply-To: <92335390-A05A-4E1D-9D07-A69896768A57@kernel.crashing.org>
On Mar 12, 2013, at 3:44 PM, Kumar Gala wrote:
>=20
> On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
>=20
>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>>=20
>>> Rather than do it this way, we should do something like:
>>>=20
>>> fsl_indirect_read_config() {
>>> link check
>>> if (link)
>>> indirect_read_config()
>>> }
>>>=20
>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>>=20
>>> - k
>>>=20
>>=20
>> Ok, how about this:
>>=20
>=20
> I'd rather we just export indirect_read_config() & =
indirect_write_config() from indirect_pci.c and call the functions =
directly. Adding a global and call them via a function pointer seems =
wrong to me.
>=20
> - k
Also, can you base this patch on my powerpc.git next branch as =
fsl_pci.{c,h} have some changes in them.
- k
>=20
>>=20
>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
>> ---
>> arch/powerpc/sysdev/fsl_pci.c | 49=20
>> ++++++++++++++++++++++++++++++++++++++----
>> 1 file changed, 45 insertions(+), 4 deletions(-)
>>=20
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
>> index 682084d..693db9f 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -36,6 +36,8 @@
>>=20
>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>>=20
>> +static struct pci_ops *indirect_pci_ops;
>> +
>> static void quirk_fsl_pcie_header(struct pci_dev *dev)
>> {
>> u8 hdr_type;
>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct =
pci_controller=20
>> *hose)
>> return 0;
>> }
>>=20
>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned =
int devfn,
>> + int offset, int len, u32 *val)
>> +{
>> + struct pci_controller *hose =3D pci_bus_to_host(bus);
>> +=09
>> + // check the link status
>> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) =
{
>> + u32 ltssm =3D 0;
>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
>> + if (ltssm < PCIE_LTSSM_L0) {
>> + hose->indirect_type |=3D =
PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + } else {
>> + hose->indirect_type &=3D =
~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> + }
>> + }
>> + return indirect_pci_ops->read(bus, devfn, offset, len, val);
>> +}
>> +
>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned =
int devfn,
>> + int offset, int len, u32 val)
>> +{
>> + return indirect_pci_ops->write(bus, devfn, offset, len, val);
>> +}
>> +
>> +static struct pci_ops fsl_indirect_pci_ops =3D
>> +{
>> + .read =3D fsl_indirect_read_config,
>> + .write =3D fsl_indirect_write_config,
>> +};
>> +
>> +static void __init fsl_setup_indirect_pci(struct pci_controller* =
hose,
>> + resource_size_t cfg_addr,
>> + resource_size_t cfg_data, u32 =
flags)
>> +{
>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
>> + indirect_pci_ops =3D hose->ops;
>> + hose->ops =3D &fsl_indirect_pci_ops;
>> +}
>> +
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>=20
>> #define MAX_PHYS_ADDR_BITS 40
>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device =
*pdev,=20
>> int is_primary)
>> hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
>> hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
>>=20
>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>>=20
>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> /* For PCIE read HEADER_TYPE to identify controler mode =
*/
>> @@ -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node =
*dev)
>> if (ret)
>> goto err0;
>> } else {
>> - setup_indirect_pci(hose, rsrc_cfg.start,
>> - rsrc_cfg.start + 4, 0);
>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
>> + rsrc_cfg.start + 4, 0);
>> }
>>=20
>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Add platform_device declaration to fsl_pci.h
From: Kumar Gala @ 2013-03-12 20:46 UTC (permalink / raw)
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org, Li Yang-R58472
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C11ED4@039-SN1MPN1-003.039d.mgd.msft.net>
On Mar 10, 2013, at 9:36 PM, Jia Hongtao-B38951 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Kumar Gala [mailto:galak@kernel.crashing.org]
>> Sent: Saturday, March 09, 2013 4:38 AM
>> To: Jia Hongtao-B38951
>> Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
>> Subject: Re: [PATCH] powerpc/85xx: Add platform_device declaration to
>> fsl_pci.h
>>=20
>>=20
>> On Mar 4, 2013, at 2:40 AM, Jia Hongtao wrote:
>>=20
>>> mpc85xx_pci_err_probe(struct platform_device *op) need =
platform_device
>>> declaration for definition. Otherwise, it will cause compile error =
if
>>> any files including fsl_pci.h without declaration of =
platform_device.
>>>=20
>>> Signed-off-by: Jia Hongtao <B38951@freescale.com>
>>> ---
>>> arch/powerpc/sysdev/fsl_pci.h | 2 ++
>>> 1 files changed, 2 insertions(+), 0 deletions(-)
>>>=20
>>=20
>> Where does the compile error show up?
>>=20
>> - k
>=20
> The function mpc85xx_pci_err_probe(struct platform_device *op) need
> *platform_device* declaration so <linux/platform_device.h> must be
> included.=20
>=20
> For now there is no compile error occurred just because the file that
> need fsl_pci.h happened to include <linux/platform_device.h> already.
>=20
> If not the compile error log will be like this:
> "
> In file included from arch/powerpc/kernel/traps.c:62:0:
> arch/powerpc/sysdev/fsl_pci.h:108:34: error: 'struct platform_device' =
declared inside parameter list
> arch/powerpc/sysdev/fsl_pci.h:108:34: error: its scope is only this =
definition or declaration, which is probably not what you want
> "
>=20
> You mean I have to show the compile error log in patch description?
Not necessarily, I'm just trying to decide if we should include =
<linux/platform_device.h> or just do:
struct platform_device;
near the top of fsl_pci.h.
>=20
> Thanks.
> -Hongtao.
>=20
>>=20
>>> diff --git a/arch/powerpc/sysdev/fsl_pci.h
>>> b/arch/powerpc/sysdev/fsl_pci.h index c495c00..df66721 100644
>>> --- a/arch/powerpc/sysdev/fsl_pci.h
>>> +++ b/arch/powerpc/sysdev/fsl_pci.h
>>> @@ -14,6 +14,8 @@
>>> #ifndef __POWERPC_FSL_PCI_H
>>> #define __POWERPC_FSL_PCI_H
>>>=20
>>> +#include <linux/platform_device.h>
>>> +
>>> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and
>> Status */
>>> #define PCIE_LTSSM_L0 0x16 /* L0 state */
>>> #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block =
version
>> Rev2.2 */
>>> --
>>> 1.7.5.1
>>>=20
>>=20
>=20
^ permalink raw reply
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Kumar Gala @ 2013-03-12 20:44 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev
In-Reply-To: <2399353.017i5G1tnZ@pcimr>
On Mar 12, 2013, at 4:23 AM, Rojhalat Ibrahim wrote:
> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
>>=20
>> Rather than do it this way, we should do something like:
>>=20
>> fsl_indirect_read_config() {
>> link check
>> if (link)
>> indirect_read_config()
>> }
>>=20
>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
>>=20
>> - k
>>=20
>=20
> Ok, how about this:
>=20
I'd rather we just export indirect_read_config() & =
indirect_write_config() from indirect_pci.c and call the functions =
directly. Adding a global and call them via a function pointer seems =
wrong to me.
- k
>=20
> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> ---
> arch/powerpc/sysdev/fsl_pci.c | 49=20
> ++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 45 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/fsl_pci.c =
b/arch/powerpc/sysdev/fsl_pci.c
> index 682084d..693db9f 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -36,6 +36,8 @@
>=20
> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>=20
> +static struct pci_ops *indirect_pci_ops;
> +
> static void quirk_fsl_pcie_header(struct pci_dev *dev)
> {
> u8 hdr_type;
> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct =
pci_controller=20
> *hose)
> return 0;
> }
>=20
> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int =
devfn,
> + int offset, int len, u32 *val)
> +{
> + struct pci_controller *hose =3D pci_bus_to_host(bus);
> +=09
> + // check the link status
> + if ((bus->number =3D=3D hose->first_busno) && (devfn =3D=3D 0)) =
{
> + u32 ltssm =3D 0;
> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
> + if (ltssm < PCIE_LTSSM_L0) {
> + hose->indirect_type |=3D =
PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + } else {
> + hose->indirect_type &=3D =
~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> + }
> + }
> + return indirect_pci_ops->read(bus, devfn, offset, len, val);
> +}
> +
> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned =
int devfn,
> + int offset, int len, u32 val)
> +{
> + return indirect_pci_ops->write(bus, devfn, offset, len, val);
> +}
> +
> +static struct pci_ops fsl_indirect_pci_ops =3D
> +{
> + .read =3D fsl_indirect_read_config,
> + .write =3D fsl_indirect_write_config,
> +};
> +
> +static void __init fsl_setup_indirect_pci(struct pci_controller* =
hose,
> + resource_size_t cfg_addr,
> + resource_size_t cfg_data, u32 =
flags)
> +{
> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
> + indirect_pci_ops =3D hose->ops;
> + hose->ops =3D &fsl_indirect_pci_ops;
> +}
> +
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>=20
> #define MAX_PHYS_ADDR_BITS 40
> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device =
*pdev,=20
> int is_primary)
> hose->first_busno =3D bus_range ? bus_range[0] : 0x0;
> hose->last_busno =3D bus_range ? bus_range[1] : 0xff;
>=20
> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
>=20
> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> /* For PCIE read HEADER_TYPE to identify controler mode =
*/
> @@ -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node =
*dev)
> if (ret)
> goto err0;
> } else {
> - setup_indirect_pci(hose, rsrc_cfg.start,
> - rsrc_cfg.start + 4, 0);
> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
> + rsrc_cfg.start + 4, 0);
> }
>=20
> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>=20
^ permalink raw reply
* Re: [PATCH -V2 2/2] powerpc: Update kernel VSID range
From: Geoff Levand @ 2013-03-12 20:11 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: phileas-fogg, paulus, linuxppc-dev, David Gibson
In-Reply-To: <87vc8xrsp1.fsf@linux.vnet.ibm.com>
Hi Aneesh,
On Tue, 2013-03-12 at 12:49 +0530, Aneesh Kumar K.V wrote:
> Done. I added this as a patch on top of the series.
I tried to test this against v3.8, but applying it failed:
Applying: powerpc: Update kernel VSID range
error: patch failed: arch/powerpc/mm/slb_low.S:66
Could you please make a set that applies to 3.8? Thanks.
-Geoff
^ permalink raw reply
* [PATCH] powerpc/85xx: add CONFIG_E1000E to corenet64_smp_defconfig
From: Scott Wood @ 2013-03-12 20:03 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
This is a commonly used ethernet card, especially with mainline kernels
which lack datapath support.o
Other changes are due to running savedefconfig.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/configs/corenet64_smp_defconfig | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 3d139fa..37363a3 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -1,14 +1,12 @@
CONFIG_PPC64=y
CONFIG_PPC_BOOK3E_64=y
-# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=2
-CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
@@ -78,6 +76,7 @@ CONFIG_SATA_FSL=y
CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
+CONFIG_E1000E=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
@@ -140,6 +139,5 @@ CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_DEV_FSL_CAAM=y
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH] Make PCIe hotplug work with Freescale PCIe controllers
From: Rojhalat Ibrahim @ 2013-03-12 12:12 UTC (permalink / raw)
To: Chen Yuanquan-B41889; +Cc: linuxppc-dev, Zang Roy-R61911
In-Reply-To: <513F0B8B.4090607@freescale.com>
On Tuesday 12 March 2013 19:03:39 Chen Yuanquan-B41889 wrote:
> On 03/12/2013 06:30 PM, Rojhalat Ibrahim wrote:
> > On Tuesday 12 March 2013 18:12:20 Chen Yuanquan-B41889 wrote:
> >>>> -----Original Message-----
> >>>> From: Linuxppc-dev [mailto:linuxppc-dev-bounces+tie-
> >>>> fei.zang=freescale.com@lists.ozlabs.org] On Behalf Of Rojhalat Ibrahim
> >>>> Sent: Tuesday, March 12, 2013 5:23 PM
> >>>> To: Kumar Gala
> >>>> Cc: linuxppc-dev@lists.ozlabs.org
> >>>> Subject: Re: [PATCH] Make PCIe hotplug work with Freescale PCIe
> >>>> controllers
> >>>>
> >>>> On Monday 11 March 2013 12:17:42 Kumar Gala wrote:
> >>>>> Rather than do it this way, we should do something like:
> >>>>>
> >>>>> fsl_indirect_read_config() {
> >>>>>
> >>>>> link check
> >>>>> if (link)
> >>>>>
> >>>>> indirect_read_config()
> >>>>>
> >>>>> }
> >>>>>
> >>>>> and just add fsl_indirect_{r,w}_config into fsl_pci.c
> >>>>>
> >>>>> - k
> >>>>
> >>>> Ok, how about this:
> >> Yeah, this patch can solve the problem of PCI-e bus rescan which a PCI-e
> >> EP is added to RC
> >> after RC booting up. If RC boots up without EP added, the original code
> >> will set the PCI-e
> >> bus as no link even if you add a EP to RC during RC's runtime.
> >>
> >> Regards,
> >> Yuanquan
> >
> > Right. The EP is only added if you first do "echo 1 >
> > /sys/bus/pci/rescan".
> >
> > Rojhalat
>
> The following patch can solve your issue of "only added if you first ...":
Actually I don't have a problem with having to do a rescan before the device
is added. In my case the device is a FPGA which is configured at runtime. So I
can simply trigger the rescan after configuration.
For my purposes the patch I proposed is sufficient for now.
The additional changes suggested by you should probably go into separate
patches.
Rojhalat
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 5b3771a..c1298d0 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -730,11 +730,12 @@ int __devinit pci_scan_bridge(struct pci_bus *bus,
> struct
>
> /* Prevent assigning a bus number that already exists.
> * This can happen when a bridge is hot-plugged */
> - if (pci_find_bus(pci_domain_nr(bus), max+1))
> - goto out;
> - child = pci_add_new_bus(bus, dev, ++max);
> - if (!child)
> - goto out;
> + child = pci_find_bus(pci_domain_nr(bus), max+1);
> + if (!child) {
> + child = pci_add_new_bus(bus, dev, ++max);
> + if (!child)
> + goto out;
> + }
> buses = (buses & 0xff000000)
>
> | ((unsigned int)(child->primary) << 0)
> | ((unsigned int)(child->secondary) << 8)
>
> There are still some issues about powerpc PCI-e rescan. For example, add
> a Intel e1000e
> ethernet card or silicon PCI-e_sata to powerpc PCI-e slot and boot the
> board. The EP can
> work well with their driver. But if you "echo 1 >
> /sys/bus/pci/device/xxx/remove" which
> corresponds to Intel e1000e ethernet card or silicon PCI-e_sata, then
> "echo 1" to rescan,
> the device can be rescanned, but it will fail to load the corresponded
> driver due to hw_irq
> and dma_set_mask error. The following patch can solve the problem, but
> not a good method
> to solve it.
>
> diff --git a/arch/powerpc/kernel/pci-common.c
> b/arch/powerpc/kernel/pci-common.c
> index 2476a32..f9b7f0f 100644
> --- a/arch/powerpc/kernel/pci-common.c
> +++ b/arch/powerpc/kernel/pci-common.c
> @@ -1557,6 +1557,19 @@ int pcibios_enable_device(struct pci_dev *dev,
> int mask)
> if (ppc_md.pcibios_enable_device_hook(dev))
> return -EINVAL;
>
> + if (!dev->is_added) {
> + set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
> +
> + set_dma_ops(&dev->dev, pci_dma_ops);
> + set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
> +
> + if (ppc_md.pci_dma_dev_setup)
> + ppc_md.pci_dma_dev_setup(dev);
> +
> + pci_read_irq_line(dev);
> + if (ppc_md.pci_irq_fixup)
> + ppc_md.pci_irq_fixup(dev);
> + }
> return pci_enable_resources(dev, mask);
> }
>
>
> Regards,
> Yuanquan
>
> >>>> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> >>>> ---
> >>>>
> >>>> arch/powerpc/sysdev/fsl_pci.c | 49
> >>>>
> >>>> ++++++++++++++++++++++++++++++++++++++----
> >>>>
> >>>> 1 file changed, 45 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c
> >>>> b/arch/powerpc/sysdev/fsl_pci.c index 682084d..693db9f 100644
> >>>> --- a/arch/powerpc/sysdev/fsl_pci.c
> >>>> +++ b/arch/powerpc/sysdev/fsl_pci.c
> >>>> @@ -36,6 +36,8 @@
> >>>>
> >>>> static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
> >>>>
> >>>> +static struct pci_ops *indirect_pci_ops;
> >>>> +
> >>>>
> >>>> static void quirk_fsl_pcie_header(struct pci_dev *dev) {
> >>>>
> >>>> u8 hdr_type;
> >>>>
> >>>> @@ -64,6 +66,45 @@ static int __init fsl_pcie_check_link(struct
> >>>> pci_controller
> >>>> *hose)
> >>>>
> >>>> return 0;
> >>>>
> >>>> }
> >>>>
> >>>> +static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int
> >>>> devfn,
> >>>> + int offset, int len, u32 *val)
> >>>> +{
> >>>> + struct pci_controller *hose = pci_bus_to_host(bus);
> >>>> +
> >>>> + // check the link status
> >>>> + if ((bus->number == hose->first_busno) && (devfn == 0)) {
> >>>> + u32 ltssm = 0;
> >>>> + indirect_pci_ops->read(bus, 0, PCIE_LTSSM, 4, <ssm);
> >>>> + if (ltssm < PCIE_LTSSM_L0) {
> >>>> + hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >>>> + } else {
> >>>> + hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> >>>> + }
> >>>> + }
> >>>> + return indirect_pci_ops->read(bus, devfn, offset, len, val); }
> >>>> +
> >>>> +static int fsl_indirect_write_config(struct pci_bus *bus, unsigned int
> >>>> devfn,
> >>>> + int offset, int len, u32 val)
> >>>> +{
> >>>> + return indirect_pci_ops->write(bus, devfn, offset, len, val); }
> >>>> +
> >>>> +static struct pci_ops fsl_indirect_pci_ops = {
> >>>> + .read = fsl_indirect_read_config,
> >>>> + .write = fsl_indirect_write_config,
> >>>> +};
> >>>> +
> >>>> +static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
> >>>> + resource_size_t cfg_addr,
> >>>> + resource_size_t cfg_data, u32 flags) {
> >>>> + setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
> >>>> + indirect_pci_ops = hose->ops;
> >>>> + hose->ops = &fsl_indirect_pci_ops;
> >>>> +}
> >>>> +
> >>>>
> >>>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> >>>>
> >>>> #define MAX_PHYS_ADDR_BITS 40
> >>>>
> >>>> @@ -461,8 +502,8 @@ int __init fsl_add_bridge(struct platform_device
> >>>> *pdev, int is_primary)
> >>>>
> >>>> hose->first_busno = bus_range ? bus_range[0] : 0x0;
> >>>> hose->last_busno = bus_range ? bus_range[1] : 0xff;
> >>>>
> >>>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >>>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >>>> + fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> >>>> + PPC_INDIRECT_TYPE_BIG_ENDIAN);
> >>>>
> >>>> if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> >>>>
> >>>> /* For PCIE read HEADER_TYPE to identify controler mode */ @@
> >>>>
> >>>> -766,8 +807,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
> >>>>
> >>>> if (ret)
> >>>>
> >>>> goto err0;
> >>>>
> >>>> } else {
> >>>>
> >>>> - setup_indirect_pci(hose, rsrc_cfg.start,
> >>>> - rsrc_cfg.start + 4, 0);
> >>>> + fsl_setup_indirect_pci(hose, rsrc_cfg.start,
> >>>> + rsrc_cfg.start + 4, 0);
> >>>>
> >>>> }
> >>>>
> >>>> printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
> >>>>
> >>>> _______________________________________________
> >>>> Linuxppc-dev mailing list
> >>>> Linuxppc-dev@lists.ozlabs.org
> >>>> https://lists.ozlabs.org/listinfo/linuxppc-dev
> >>
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
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