* [PATCH v2] powerpc: Add accounting for Doorbell interrupts
From: Ian Munsie @ 2013-03-22 5:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Michael Neuling, linuxppc-dev, Ian Munsie
In-Reply-To: <1363928529-sup-704@delenn.ozlabs.ibm.com>
From: Ian Munsie <imunsie@au1.ibm.com>
This patch adds a new line to /proc/interrupts to account for the
doorbell interrupts that each hardware thread has received. The total
interrupt count in /proc/stat will now also include doorbells.
# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
16: 551 1267 281 175 XICS Level IPI
LOC: 2037 1503 1688 1625 Local timer interrupts
SPU: 0 0 0 0 Spurious interrupts
CNT: 0 0 0 0 Performance monitoring interrupts
MCE: 0 0 0 0 Machine check exceptions
DBL: 42 550 20 91 Doorbell interrupts
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
---
Changes from v1:
- Added #ifdef CONFIG_PPC_DOORBELL as requested by Michael Ellerman to avoid
the extra per cpu variable in irq_stat when building for a system that does
not support doorbells.
arch/powerpc/include/asm/hardirq.h | 3 +++
arch/powerpc/kernel/dbell.c | 2 ++
arch/powerpc/kernel/irq.c | 12 ++++++++++++
3 files changed, 17 insertions(+)
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index 3147a29..3bdcfce 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -10,6 +10,9 @@ typedef struct {
unsigned int pmu_irqs;
unsigned int mce_exceptions;
unsigned int spurious_irqs;
+#ifdef CONFIG_PPC_DOORBELL
+ unsigned int doorbell_irqs;
+#endif
} ____cacheline_aligned irq_cpustat_t;
DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 9ebbc24..d55c76c 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -41,6 +41,8 @@ void doorbell_exception(struct pt_regs *regs)
may_hard_irq_enable();
+ __get_cpu_var(irq_stat).doorbell_irqs++;
+
smp_ipi_demux();
irq_exit();
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 4f97fe3..5cbcf4d 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -374,6 +374,15 @@ int arch_show_interrupts(struct seq_file *p, int prec)
seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
seq_printf(p, " Machine check exceptions\n");
+#ifdef CONFIG_PPC_DOORBELL
+ if (cpu_has_feature(CPU_FTR_DBELL)) {
+ seq_printf(p, "%*s: ", prec, "DBL");
+ for_each_online_cpu(j)
+ seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
+ seq_printf(p, " Doorbell interrupts\n");
+ }
+#endif
+
return 0;
}
@@ -387,6 +396,9 @@ u64 arch_irq_stat_cpu(unsigned int cpu)
sum += per_cpu(irq_stat, cpu).pmu_irqs;
sum += per_cpu(irq_stat, cpu).mce_exceptions;
sum += per_cpu(irq_stat, cpu).spurious_irqs;
+#ifdef CONFIG_PPC_DOORBELL
+ sum += per_cpu(irq_stat, cpu).doorbell_irqs;
+#endif
return sum;
}
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH] powerpc: Add accounting for Doorbell interrupts
From: Ian Munsie @ 2013-03-22 5:13 UTC (permalink / raw)
To: Michael Ellerman; +Cc: Michael Neuling, linuxppc-dev
In-Reply-To: <20130322041803.GB26908@concordia>
Excerpts from Michael Ellerman's message of 2013-03-22 15:18:03 +1100:
> On Wed, Mar 20, 2013 at 06:42:12PM +1100, Ian Munsie wrote:
> > From: Ian Munsie <imunsie@au1.ibm.com>
> >
> > This patch adds a new line to /proc/interrupts to account for the
> > doorbell interrupts that each hardware thread has received. The total
> > interrupt count in /proc/stat will now also include doorbells.
>
> Should it be inside CONFIG_PPC_DOORBELL ?
The doorbell line will only show up in /proc/interrupt if CPU_FTR_DBELL
is set and the total interrupt count in /proc/stat will be unaffected
if we don't have doorbells (+ 0 doorbells). It still builds fine without
CONFIG_PPC_DOORBELL.
Adding #ifdefs would save one per cpu integer in irq_stat. I can throw
together a v2 patch with them in place.
Cheers,
-Ian
^ permalink raw reply
* Re: [PATCH] powerpc/uprobes: teach uprobes to ignore gdb breakpoints
From: Ananth N Mavinakayanahalli @ 2013-03-22 4:47 UTC (permalink / raw)
To: Oleg Nesterov; +Cc: ppcdev, Srikar Dronamraju, stable
In-Reply-To: <20130321155809.GA20865@redhat.com>
On Thu, Mar 21, 2013 at 04:58:09PM +0100, Oleg Nesterov wrote:
> On 03/21, Ananth N Mavinakayanahalli wrote:
> >
> > On Wed, Mar 20, 2013 at 05:06:44PM +0100, Oleg Nesterov wrote:
> >
> > > > > But we did not install UPROBE_SWBP_INSN. Is it fine? I hope yes, just to
> > > > > verify. If not, we need 2 definitions. is_uprobe_insn() should still check
> > > > > insns == UPROBE_SWBP_INSN, and is_swbp_insn() should check is_trap().
> >
> > Its fine from gdb's perspective with my patch.
>
> Yes, but this doesn't look right from uprobe's perspective.
>
> > > > So, install_breakpoint()->prepare_uprobe()->is_swbp_insn() will return
> > > > ENOTSUPP. In fact, arch_uprobe_analyze_insn() will also do the same.
> > >
> > > Yes and the check in arch_uprobe_analyze_insn() should go away.
> > >
> > > But you missed my point. Please forget about prepare_uprobe(), it is
> > > wrong anyway. And, prepare_uprobe() inspects the _original_ insn from
> > > the file, this has nothing install_breakpoint/etc.
> > >
> > > I meant verify_opcode() called by install_breakpoint/etc.
> >
> > For the case where X already exists, verify_opcode() currently returns 0.
> > IMO, it should return -EEXIST,
>
> Oh, this is debatable. Currently we assume that uprobe should "win".
And there is that one case where gdb also uses an unconditional trap...
but that's besides the point if we don't care about gdb.
> See below...
>
> > unless you are proposing that uprobes
> > should ride on the existing trap (even if its a variant).
>
> Yes. And this is what the current implementation does.
>
> > If you are proposing that uprobes ride on X if it already exists, that's
> > not always possible and is a big can of worms... see below...
>
> Sure. Whatever we do uprobe and gdb can confuse each other. Unless we
> rework the vm code completely (not sure this is realistic).
Agreed.
> > > OK. So, if I understand correctly, gdb can use some conditional
> > > breakpoint, and it is possible that this insn won't generate the
> > > trap?
> >
> > Yes it is possible if the condition is not met. If the condition is
> > met, the instruction will generate a trap, and uprobes will do a
> > send_sig(SIGTRAP) from handle_swbp().
>
> Unless there is uprobe at the same address. Once again, uprobe wins.
In which case, we will need to replace the conditional trap with the
unconditional one when the uprobe register happens. That is doable.
> Your patch only fixes the case when the task hits a non-UPROBE_SWBP_INSN
> breakpoint and there is no uprobe at the same address.
Correct.
> > > Then this patch is not right, or at least we need another change
> > > on top?
> > >
> > > Once again. Suppose that gdb installs the TRAP_IF_R1_GT_R2.
> > >
> > > After that uprobe_register() is called, but it won't change this
> > > insn because verify_opcode() returns 0.
> > >
> > > Then the probed task hits this breakoint with "r1 < r2" and we do
> > > not report this event.
> >
> > At this time, the condition for the trap is not satisfied, so no
> > exception occurs.
>
> Yes, and thus uprobe->handler() is not called, this was my point.
>
> > If the expectation is that the trap always trigger,
> > then all such trap variants need to be replaced with the unconditional
> > trap
>
> Yes. that is why I suggested the patch which doesn't affect verify_opcode().
> uprobe_register() should replace the conditional trap with the unconditional
> UPROBE_SWBP_INSN. uprobes should win.
OK, I see your point.
...
> > But, unlike x86, we cannot
> > expect a uprobe with an underlying trap variant (X) to always trigger.
>
> And that is why I think write_opcode() should rewrite the conditional
> trap.
OK
> > IMHO, its not a good idea to do that for x86 either,
>
> This change has no effect fo x86.
>
> > IMHO, I really think we should not allow uprobe_register() to succeed if
> > the underlying instruction is a breakpoint (or a variant thereof).
>
> I disagree.
>
> Just for example. Suppose we change install_breakpoint() so that it fails
> if the underlying instruction is int3. (once again, "underlying" does not
> mean the original insn from vma->vm_file).
>
> First of all, this is very much nontrivial. I simply do not see how we
> can do this. If nothing else, uprobe_register() can race with uprobe_mmap()
> and install_breakpoint() can be called twice with the same vaddr. With
> this change register or mmap can fail.
>
> But suppose you can do this. Now you can write the trivial application
> which mmaps glibc and inserts int3 into, say, getpid()'s vaddr. Voila,
> this makes "perf probe -x /lib/libc.so.6" impossible, uprobe_register()
> will fail.
>
> Whatever you think about this logic, it was desidned to assume that
> install_breakpoint() should be "idempotent", and we ignore the races
> with gdb. We should only ensure that the kernel can't crash/etc.
>
> And uprobe can "steal" the trap from gdb if they race, again this is by
> design. and your patch can't prevent this but complicates the rules.
>
> I already said this many times, but let me repeat. is_swbp_isn() and
> its usage is confusing. Lets forget about prepare_uprobe(). Now,
>
> - verify_opcode()->is_swbp_insn() means:
>
> is this insn fine for uprobe? (we do not care about
> gdb, we simply ignore this problem)
I will write up a patch for this case.. So, IIUC we do not care to send
gdb a SIGTRAP if we have replaced a conditional trap from gdb with an
unconditional uprobes one, right?
> - is_swbp_at_addr()->is_swbp_insn() means:
>
> there is no uprobe, should we send SIGTRAP ?
This part is handled with my patch now...
Thanks for being patient. I'll write up the patches and send across for
review.
Ananth.
^ permalink raw reply
* Re: [PATCH] powerpc/uprobes: teach uprobes to ignore gdb breakpoints
From: Ananth N Mavinakayanahalli @ 2013-03-22 4:37 UTC (permalink / raw)
To: Oleg Nesterov; +Cc: ppcdev, Srikar Dronamraju, stable
In-Reply-To: <20130321160002.GB20865@redhat.com>
On Thu, Mar 21, 2013 at 05:00:02PM +0100, Oleg Nesterov wrote:
> On 03/21, Ananth N Mavinakayanahalli wrote:
> ?
> > On Wed, Mar 20, 2013 at 05:07:28PM +0100, Oleg Nesterov wrote:
> > > On 03/20, Ananth N Mavinakayanahalli wrote:
> > > >
> > > > On Wed, Mar 20, 2013 at 01:43:01PM +0100, Oleg Nesterov wrote:
> > > > > On 03/20, Oleg Nesterov wrote:
> > > > > >
> > > > > IOW, if I wasn't clear... Lets forget about gdb/etc for the moment.
> > > > > Suppose we apply the patch below. Will uprobes on powerpc work?
> > > > >
> > > > > If yes, then your patch should be fine. If not, we probably need more
> > > > > changes.
> > > >
> > > > Yes, it will work fine.
> > >
> > > Even if this new insn is conditional?
> >
> > Yes.
>
> But this can't be true. If it is conditional, it won't always generate a
> trap, this means uprobe won't actually work.
I meant to say, uprobes if we use a conditional trap instruction as long
as the condition is met.
Ananth
^ permalink raw reply
* Re: [PATCH] powerpc: drop even more unused Kconfig symbols
From: Michael Ellerman @ 2013-03-22 4:21 UTC (permalink / raw)
To: Paul Bolle; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <1363864206.1390.117.camel@x61.thuisdomein>
On Thu, Mar 21, 2013 at 12:10:06PM +0100, Paul Bolle wrote:
> When I submitted commit 6805ab6daa2b589fe3242d05ddc47a9dbb0c4eb1
> ("powerpc: drop unused Kconfig symbols") I apparently failed to notice
> that my patch also made PREP_RESIDUAL and PPC_A2_DD2 unused. Drop these
> now.
>
> Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
> ---
> 0) Untested.
>
> 1) I investigated these Kconfig files a bit and discovered that PPC_PREP
> is marked BROKEN since v2.6.15, see commit
> 5be396b00ca0f2f769c55cf69bbd7c77451c925e ("powerpc: Mark PREP and
> embedded as broken for now"). Though it's not my problem, this does
> suggest PReP support can be removed entirely.
It does, and the best code is deleted code.
Care to send a patch?
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: Add accounting for Doorbell interrupts
From: Michael Ellerman @ 2013-03-22 4:18 UTC (permalink / raw)
To: Ian Munsie; +Cc: Michael Neuling, linuxppc-dev
In-Reply-To: <1363765332-28461-1-git-send-email-imunsie@au1.ibm.com>
On Wed, Mar 20, 2013 at 06:42:12PM +1100, Ian Munsie wrote:
> From: Ian Munsie <imunsie@au1.ibm.com>
>
> This patch adds a new line to /proc/interrupts to account for the
> doorbell interrupts that each hardware thread has received. The total
> interrupt count in /proc/stat will now also include doorbells.
Should it be inside CONFIG_PPC_DOORBELL ?
cheers
^ permalink raw reply
* Re: [PATCH 4/11] Add platform_has_feature()
From: Michael Ellerman @ 2013-03-22 3:56 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <5148AB26.4060705@linux.vnet.ibm.com>
On Tue, Mar 19, 2013 at 01:15:02PM -0500, Nathan Fontenot wrote:
> On 03/14/2013 08:42 AM, Michael Ellerman wrote:
> > On Fri, Mar 08, 2013 at 10:02:31PM -0600, Nathan Fontenot wrote:
> >> The firmware_has_feature() function makes it easy to check for supported
> >> features of the hardware. There is not corresponding function to check for
> >> features supported by the client architecture.
> >
> > Actually it doesn't tell you about features of the hardware, it tells
> > you about features of the firmware, or the platform ..
> >
> > So I think you should really just be adding a new firmware feature flag,
> > and adding whatever glue code is required to set it based on what you
> > find in the device tree.
> >
> > Also notice where you end up using it:
> >
> > - if (firmware_has_feature(FW_FEATURE_OPAL))
> > + if (firmware_has_feature(FW_FEATURE_OPAL) ||
> > + platform_has_feature(OV5_TYPE1_AFFINITY)) {
> > + dbg("Using form 1 affinity\n");
> > form1_affinity = 1;
> >
> > Could be:
> >
> > + if (firmware_has_feature(FW_FEATURE_FORM1_AFFINITY) ||
> >
>
> To make sure I understand what you're suggesting...
>
> You think there should be a single firmware_has_feature() for all current
> uses and also for checking items such as FORM1_AFFINITY and PRRN
> features as reported by the device tree for vector 5 portions of the
> client architecture bits. I think this could be done by checking the
> device tree ibm,architecture-vec-5 node for a specified feature and
> setting a bit the appropriate bit in powerpc_firmware_features.
Yes that's right.
So you'd add a new FW_FEATURE_FORM1_AFFINITY, and set it depending on what
you find in "ibm,architecture-vec-5" on IBM pseries machines.
As a cleanup you'd also set it unconditionally on OPAL and then the
check above could be simply for FW_FEATURE_FORM1_AFFINITY.
cheers
^ permalink raw reply
* [PATCH] KVM: fix powerpc build error for !CONFIG_KVM
From: Stephen Rothwell @ 2013-03-22 3:35 UTC (permalink / raw)
To: Kevin Hilman
Cc: Phil Carmody, Gleb Natapov, Marcelo Tosatti, LKML, linux-next,
Paul Mackerras, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 2909 bytes --]
Fixes these build error when CONFIG_KVM is not defined:
In file included from arch/powerpc/include/asm/kvm_ppc.h:33:0,
from arch/powerpc/kernel/setup_64.c:67:
arch/powerpc/include/asm/kvm_book3s.h:65:20: error: field 'pte' has incomplete type
arch/powerpc/include/asm/kvm_book3s.h:69:18: error: field 'vcpu' has incomplete type
arch/powerpc/include/asm/kvm_book3s.h:98:34: error: 'HPTEG_HASH_NUM_PTE' undeclared here (not in a function)
arch/powerpc/include/asm/kvm_book3s.h:99:39: error: 'HPTEG_HASH_NUM_PTE_LONG' undeclared here (not in a function)
arch/powerpc/include/asm/kvm_book3s.h:100:35: error: 'HPTEG_HASH_NUM_VPTE' undeclared here (not in a function)
arch/powerpc/include/asm/kvm_book3s.h:101:40: error: 'HPTEG_HASH_NUM_VPTE_LONG' undeclared here (not in a function)
arch/powerpc/include/asm/kvm_book3s.h:129:4: error: 'struct kvm_run' declared inside parameter list [-Werror]
arch/powerpc/include/asm/kvm_book3s.h:129:4: error: its scope is only this definition or declaration, which is probably not what you want [-Werror]
... and so on ...
This was introduced by commit f445f11eb2cc265dd47da5b2e864df46cd6e5a82
"KVM: allow host header to be included even for !CONFIG_KVM"
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/linux/kvm_host.h | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
Kevin, does this still fix the error that commit
f445f11eb2cc265dd47da5b2e864df46cd6e5a82 was fixing?
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index a942863..90ebec0 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1,8 +1,6 @@
#ifndef __KVM_HOST_H
#define __KVM_HOST_H
-#if IS_ENABLED(CONFIG_KVM)
-
/*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
@@ -751,6 +749,7 @@ static inline int kvm_deassign_device(struct kvm *kvm,
}
#endif /* CONFIG_IOMMU_API */
+#if IS_ENABLED(CONFIG_KVM)
static inline void __guest_enter(void)
{
/*
@@ -770,6 +769,10 @@ static inline void __guest_exit(void)
vtime_account_system(current);
current->flags &= ~PF_VCPU;
}
+#else
+static inline void __guest_enter(void) { return; }
+static inline void __guest_exit(void) { return; }
+#endif /* IS_ENABLED(CONFIG_KVM) */
#ifdef CONFIG_CONTEXT_TRACKING
extern void guest_enter(void);
@@ -1057,8 +1060,4 @@ static inline bool kvm_vcpu_eligible_for_directed_yield(struct kvm_vcpu *vcpu)
}
#endif /* CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT */
-#else
-static inline void __guest_enter(void) { return; }
-static inline void __guest_exit(void) { return; }
-#endif /* IS_ENABLED(CONFIG_KVM) */
#endif
--
1.8.1
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply related
* [PATCH] kvm: (ppc) stub out more functions in order to permit kernel to build
From: Phil Carmody @ 2013-03-21 23:59 UTC (permalink / raw)
To: sfr; +Cc: Phil Carmody, khilman, Linuxppc-dev
Build failure mentioned by Stephen Rothwell here:
http://www.mail-archive.com/linuxppc-dev@lists.ozlabs.org/msg65408.html
Traced to:
commit f445f11eb2cc -"KVM: allow host header to be included even for !CONFIG_KVM"
This patch permits the build to progress by stubbing out the two functions
that it fell over on. I have no idea if that's even vaguely appropriate.
This has been .c->.o compile tested only, as g5_defconfig FTB elsewhere.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Phil Carmody <pc+lkml@asdf.org>
---
arch/powerpc/include/asm/kvm_ppc.h | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 44a657a..262d9b7 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -20,6 +20,8 @@
#ifndef __POWERPC_KVM_PPC_H__
#define __POWERPC_KVM_PPC_H__
+#if IS_ENABLED(CONFIG_KVM)
+
/* This file exists just so we can dereference kvm_vcpu, avoiding nested header
* dependencies. */
@@ -324,4 +326,9 @@ static inline ulong kvmppc_get_ea_indexed(struct kvm_vcpu *vcpu, int ra, int rb)
return ea;
}
+#else
+static inline void kvmppc_set_xics_phys(int cpu, unsigned long addr) { return; }
+static inline void kvm_linear_init(void) { return; }
+#endif /* IS_ENABLED(CONFIG_KVM) */
+
#endif /* __POWERPC_KVM_PPC_H__ */
--
1.7.2.5
^ permalink raw reply related
* Re: [Suggestion] PowerPC: kernel: cross compiling issue with allmodconfig
From: Michael Neuling @ 2013-03-21 23:21 UTC (permalink / raw)
To: Chen Gang F T, Stuart Yoder, Kumar Gala
Cc: sfr, matt, Chen Gang, linux-kernel@vger.kernel.org,
paulus@samba.org, imunsie, linuxppc-dev
In-Reply-To: <514AC418.1070806@gmail.com>
Chen Gang F T <chen.gang.flying.transformer@gmail.com> wrote:
>=20
> it seems:
> only move slb_miss_realmode to the end, can fix this issue without ne=
gative effect.
So this works but uncovers a new bug.
Stuart: if you apply this patch allmodconfig now gets this build error
on linux-next.
arch/powerpc/kernel/built-in.o: In function `restore_pblist_ptr':
ftrace.c:(.toc+0xd78): undefined reference to `epapr_ev_idle_start'
ftrace.c:(.toc+0xd88): undefined reference to `epapr_ev_idle'
make[1]: *** [vmlinux] Error 1
Reverting your patch below fixes this:
commit f070986a07e514e3b4fc4aef6551b8dffcb19287
Author: Stuart Yoder <stuart.yoder@freescale.com>
Date: Fri Feb 8 13:22:56 2013 -0600
powerpc: Add paravirt idle loop for 64-bit Book-E
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Should we revert your patch or can you send a fix? This is currently
broken in linux-next (at least next-20130321).
Mikey
>=20
>=20
>=20
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/e=
xceptions-64s.S
> index 200afa5..56bd923 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -1066,78 +1066,6 @@ unrecov_user_slb:
> #endif /* __DISABLED__ */
>=20=20
>=20=20
> -/*
> - * r13 points to the PACA, r9 contains the saved CR,
> - * r12 contain the saved SRR1, SRR0 is still ready for return
> - * r3 has the faulting address
> - * r9 - r13 are saved in paca->exslb.
> - * r3 is saved in paca->slb_r3
> - * We assume we aren't going to take any exceptions during this procedur=
e.
> - */
> -_GLOBAL(slb_miss_realmode)
> - mflr r10
> -#ifdef CONFIG_RELOCATABLE
> - mtctr r11
> -#endif
> -
> - stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
> - std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
> -
> - bl .slb_allocate_realmode
> -
> - /* All done -- return from exception. */
> -
> - ld r10,PACA_EXSLB+EX_LR(r13)
> - ld r3,PACA_EXSLB+EX_R3(r13)
> - lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
> -
> - mtlr r10
> -
> - andi. r10,r12,MSR_RI /* check for unrecoverable exception */
> - beq- 2f
> -
> -.machine push
> -.machine "power4"
> - mtcrf 0x80,r9
> - mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
> -.machine pop
> -
> - RESTORE_PPR_PACA(PACA_EXSLB, r9)
> - ld r9,PACA_EXSLB+EX_R9(r13)
> - ld r10,PACA_EXSLB+EX_R10(r13)
> - ld r11,PACA_EXSLB+EX_R11(r13)
> - ld r12,PACA_EXSLB+EX_R12(r13)
> - ld r13,PACA_EXSLB+EX_R13(r13)
> - rfid
> - b . /* prevent speculative execution */
> -
> -2: mfspr r11,SPRN_SRR0
> - ld r10,PACAKBASE(r13)
> - LOAD_HANDLER(r10,unrecov_slb)
> - mtspr SPRN_SRR0,r10
> - ld r10,PACAKMSR(r13)
> - mtspr SPRN_SRR1,r10
> - rfid
> - b .
> -
> -unrecov_slb:
> - EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
> - DISABLE_INTS
> - bl .save_nvgprs
> -1: addi r3,r1,STACK_FRAME_OVERHEAD
> - bl .unrecoverable_exception
> - b 1b
> -
> -
> -#ifdef CONFIG_PPC_970_NAP
> -power4_fixup_nap:
> - andc r9,r9,r10
> - std r9,TI_LOCAL_FLAGS(r11)
> - ld r10,_LINK(r1) /* make idle task do the */
> - std r10,_NIP(r1) /* equivalent of a blr */
> - blr
> -#endif
> -
> .align 7
> .globl alignment_common
> alignment_common:
> @@ -1336,6 +1264,78 @@ _GLOBAL(opal_mc_secondary_handler)
>=20=20
>=20=20
> /*
> + * r13 points to the PACA, r9 contains the saved CR,
> + * r12 contain the saved SRR1, SRR0 is still ready for return
> + * r3 has the faulting address
> + * r9 - r13 are saved in paca->exslb.
> + * r3 is saved in paca->slb_r3
> + * We assume we aren't going to take any exceptions during this procedur=
e.
> + */
> +_GLOBAL(slb_miss_realmode)
> + mflr r10
> +#ifdef CONFIG_RELOCATABLE
> + mtctr r11
> +#endif
> +
> + stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
> + std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
> +
> + bl .slb_allocate_realmode
> +
> + /* All done -- return from exception. */
> +
> + ld r10,PACA_EXSLB+EX_LR(r13)
> + ld r3,PACA_EXSLB+EX_R3(r13)
> + lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
> +
> + mtlr r10
> +
> + andi. r10,r12,MSR_RI /* check for unrecoverable exception */
> + beq- 2f
> +
> +.machine push
> +.machine "power4"
> + mtcrf 0x80,r9
> + mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
> +.machine pop
> +
> + RESTORE_PPR_PACA(PACA_EXSLB, r9)
> + ld r9,PACA_EXSLB+EX_R9(r13)
> + ld r10,PACA_EXSLB+EX_R10(r13)
> + ld r11,PACA_EXSLB+EX_R11(r13)
> + ld r12,PACA_EXSLB+EX_R12(r13)
> + ld r13,PACA_EXSLB+EX_R13(r13)
> + rfid
> + b . /* prevent speculative execution */
> +
> +2: mfspr r11,SPRN_SRR0
> + ld r10,PACAKBASE(r13)
> + LOAD_HANDLER(r10,unrecov_slb)
> + mtspr SPRN_SRR0,r10
> + ld r10,PACAKMSR(r13)
> + mtspr SPRN_SRR1,r10
> + rfid
> + b .
> +
> +unrecov_slb:
> + EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
> + DISABLE_INTS
> + bl .save_nvgprs
> +1: addi r3,r1,STACK_FRAME_OVERHEAD
> + bl .unrecoverable_exception
> + b 1b
> +
> +
> +#ifdef CONFIG_PPC_970_NAP
> +power4_fixup_nap:
> + andc r9,r9,r10
> + std r9,TI_LOCAL_FLAGS(r11)
> + ld r10,_LINK(r1) /* make idle task do the */
> + std r10,_NIP(r1) /* equivalent of a blr */
> + blr
> +#endif
> +
> +/*
> * Hash table stuff
> */
> .align 7
>=20
>=20
> On 2013=E5=B9=B403=E6=9C=8821=E6=97=A5 13:55, Chen Gang wrote:
> > Hello All:
> >=20
> > summary:
> > the root cause is no enough room in exception area (0x5500 -- 0x7000).
> >=20
> > it is caused by the patches "for saving/restre PPR":
> > they consumed much space of this area (0x5500 -- 0x7000).
> > for pseries_defconfig and ppc64_defconfig, it is still ok.
> > but for allmodconfig and "some additional config", it will cause is=
sue.
> >=20
> > the solving patch "Make room in exception vector area" can make room =
larger.
> > it can let "some additional config" ok.
> > but for allmodconfig, it is still not enough.
> >=20
> >=20
> > details
> > reason:
> > it is caused by:
> > commit number: 13e7a8e846c2ea38a552b986ea49332f965bbb7a
> > commit number: 44e9309f1f357794b7ae93d5f3e3e6f11d2b8a7f
> > they are "for saving/restore PPR"
> > by Haren Myneni <haren@linux.vnet.ibm.com> Thu, 6 Dec 2012
> > compiling result:
> > pseries_defconfig: pass (cpu for POWER7)
> > ppc64_defconfig: pass (cpu for POWER7)
> > allmodconfig: failed (cpu for POWER7)
> >=20
> > analysing:
> > solving patch:
> > ------------------------------------------------------------------
> > commit number: 61383407677aef05928541a00678591abea2d84c
> > Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Date: Thu Jan 10 17:44:19 2013 +1100
> >=20
> > powerpc: Make room in exception vector area
> >=20=20=20=20=20
> > The FWNMI region is fixed at 0x7000 and the vector are now
> > overflowing that with some configurations. Fix that by moving
> > some hash management code out of that region as it doesn't need
> > to be that close to the call sites (isn't accessed using
> > conditional branches).
> > ------------------------------------------------------------------
> >=20
> > but for allmodconfig (not only for "some configurations"):
> > it really can reduce much overflow bytes,
> > (maybe from hundreds bytes to dozens bytes)
> > but still not enough (still content overflow bytes)
> >=20
> > additional trying:
> > after del CONFIG_VSX and CONFIG_PPC_970_NAP in allmodconfig,
> > (will reduce dozens bytes in the region .0x5500 -- .0x7000)
> > it can pass compiling (not overflow).
> >=20
> >=20
> > next:
> > I am sorry:
> > I am not quite familiar with the detail features of powerpc.
> > it seems I am not the suitable member to continue trying.
> >=20
> > I prefer Benjamin to continue trying (just like what he has done).
> >=20
> > if Benjamin will not do it (e.g. maybe no time to do)
> > I should continue: "make additional room in exception vector area".
> > (if get no reply within a week: before 2013-03-28, I should conti=
nue)
> >=20
> >=20
> >=20
> > welcome any members' (especially Benjamin) suggestions or completions.
> >=20
> > thanks.
> >=20
> > :-)
> >=20
> >=20
> > On 2013=E5=B9=B403=E6=9C=8815=E6=97=A5 13:14, Chen Gang wrote:
> >> =E4=BA=8E 2013=E5=B9=B403=E6=9C=8815=E6=97=A5 12:52, Michael Neuling =
=E5=86=99=E9=81=93:
> >>> Yep it's a known problem but no one has bothered to fix it since it
> >>> doesn't happen in a config that anyone cares about like
> >>> pseries_defconfig and ppc64_defconfig. We've been moving code around=
in
> >>> this area a lot recently hence the breakage.
> >>>
> >>> It should be fixed though. Patches welcome. :-)
> >>
> >> thanks, and I should try, and very glad to try.
> >>
> >> :-) :-)
> >>
> >> excuse me, I try to provide related patch within this month (2013-03=
-31), is it ok ?
> >> the reason is:
> >> I am not familiar with ppc assembly code, neither ppc kernel,
> >> so need additional time resource.
> >> (originally, I worked for x86(_64) core dump analysing for kerne=
l and user programs)
> >>
> >> thanks.
> >>
> >=20
> >=20
>=20
>=20
> --=20
> Chen Gang
>=20
> Flying Transformer
>=20
^ permalink raw reply
* Re: [Suggestion] PowerPC: kernel: cross compiling issue with allmodconfig
From: Michael Neuling @ 2013-03-21 22:54 UTC (permalink / raw)
To: Chen Gang
Cc: sfr, matt, linux-kernel@vger.kernel.org, paulus@samba.org,
imunsie, linuxppc-dev
In-Reply-To: <514AA0D9.1090509@asianux.com>
Chen Gang <gang.chen@asianux.com> wrote:
> Hello All:
>=20
> summary:
> the root cause is no enough room in exception area (0x5500 -- 0x7000).
>=20
> it is caused by the patches "for saving/restre PPR":
> they consumed much space of this area (0x5500 -- 0x7000).
> for pseries_defconfig and ppc64_defconfig, it is still ok.
> but for allmodconfig and "some additional config", it will cause issu=
e.
>=20
> the solving patch "Make room in exception vector area" can make room la=
rger.
> it can let "some additional config" ok.
> but for allmodconfig, it is still not enough.
>=20
>=20
> details
> reason:
> it is caused by:
> commit number: 13e7a8e846c2ea38a552b986ea49332f965bbb7a
> commit number: 44e9309f1f357794b7ae93d5f3e3e6f11d2b8a7f
> they are "for saving/restore PPR"
> by Haren Myneni <haren@linux.vnet.ibm.com> Thu, 6 Dec 2012
> compiling result:
> pseries_defconfig: pass (cpu for POWER7)
> ppc64_defconfig: pass (cpu for POWER7)
> allmodconfig: failed (cpu for POWER7)
>=20
> analysing:
> solving patch:
> ------------------------------------------------------------------
> commit number: 61383407677aef05928541a00678591abea2d84c
> Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Date: Thu Jan 10 17:44:19 2013 +1100
>=20
> powerpc: Make room in exception vector area
>=20=20=20=20=20
> The FWNMI region is fixed at 0x7000 and the vector are now
> overflowing that with some configurations. Fix that by moving
> some hash management code out of that region as it doesn't need
> to be that close to the call sites (isn't accessed using
> conditional branches).
> ------------------------------------------------------------------
>=20
> but for allmodconfig (not only for "some configurations"):
> it really can reduce much overflow bytes,
> (maybe from hundreds bytes to dozens bytes)
> but still not enough (still content overflow bytes)
>=20
> additional trying:
> after del CONFIG_VSX and CONFIG_PPC_970_NAP in allmodconfig,
> (will reduce dozens bytes in the region .0x5500 -- .0x7000)
> it can pass compiling (not overflow).
>=20
>=20
> next:
> I am sorry:
> I am not quite familiar with the detail features of powerpc.
> it seems I am not the suitable member to continue trying.
>=20
> I prefer Benjamin to continue trying (just like what he has done).
>=20
> if Benjamin will not do it (e.g. maybe no time to do)
> I should continue: "make additional room in exception vector area".
> (if get no reply within a week: before 2013-03-28, I should continu=
e)
>=20
>=20
>=20
> welcome any members' (especially Benjamin) suggestions or completions.
This is great, thanks a lot.=20=20
If you want this to be picked up by the maintainer, you'll need to add
your signed-off-by.
The signed-off-by is to indicate that your happy for it to be included
and that you're legally allowed to do so. See
http://gerrit.googlecode.com/svn/documentation/2.0/user-signedoffby.html
for more info.
Mikey
>=20
> thanks.
>=20
> :-)
>=20
>=20
> On 2013=E5=B9=B403=E6=9C=8815=E6=97=A5 13:14, Chen Gang wrote:
> > =E4=BA=8E 2013=E5=B9=B403=E6=9C=8815=E6=97=A5 12:52, Michael Neuling =
=E5=86=99=E9=81=93:
> >> Yep it's a known problem but no one has bothered to fix it since it
> >> doesn't happen in a config that anyone cares about like
> >> pseries_defconfig and ppc64_defconfig. We've been moving code around =
in
> >> this area a lot recently hence the breakage.
> >>
> >> It should be fixed though. Patches welcome. :-)
> >=20
> > thanks, and I should try, and very glad to try.
> >=20
> > :-) :-)
> >=20
> > excuse me, I try to provide related patch within this month (2013-03-=
31), is it ok ?
> > the reason is:
> > I am not familiar with ppc assembly code, neither ppc kernel,
> > so need additional time resource.
> > (originally, I worked for x86(_64) core dump analysing for kernel=
and user programs)
> >=20
> > thanks.
> >=20
>=20
>=20
> --=20
> Chen Gang
>=20
> Asianux Corporation
>=20
^ permalink raw reply
* Re: [PATCH] powerpc/dts: Add qe support for 36bit
From: Timur Tabi @ 2013-03-21 18:42 UTC (permalink / raw)
To: Zhicheng Fan; +Cc: linuxppc-dev
In-Reply-To: <1363857961-23296-1-git-send-email-B32736@freescale.com>
On Thu, Mar 21, 2013 at 4:26 AM, Zhicheng Fan <B32736@freescale.com> wrote:
> + qe: qe@fffe80000 {
> + ranges = <0x0 0xf 0xffe80000 0x40000>;
Are you sure this works? The QE can't handle 36-bit addresses, and I
think the MURAM is located inside the QE address space.
^ permalink raw reply
* Re: [PATCH] powerpc/uprobes: teach uprobes to ignore gdb breakpoints
From: Oleg Nesterov @ 2013-03-21 16:00 UTC (permalink / raw)
To: Ananth N Mavinakayanahalli; +Cc: ppcdev, Srikar Dronamraju, stable
In-Reply-To: <20130321071707.GB5271@in.ibm.com>
On 03/21, Ananth N Mavinakayanahalli wrote:
?
> On Wed, Mar 20, 2013 at 05:07:28PM +0100, Oleg Nesterov wrote:
> > On 03/20, Ananth N Mavinakayanahalli wrote:
> > >
> > > On Wed, Mar 20, 2013 at 01:43:01PM +0100, Oleg Nesterov wrote:
> > > > On 03/20, Oleg Nesterov wrote:
> > > > >
> > > > IOW, if I wasn't clear... Lets forget about gdb/etc for the moment.
> > > > Suppose we apply the patch below. Will uprobes on powerpc work?
> > > >
> > > > If yes, then your patch should be fine. If not, we probably need more
> > > > changes.
> > >
> > > Yes, it will work fine.
> >
> > Even if this new insn is conditional?
>
> Yes.
But this can't be true. If it is conditional, it won't always generate a
trap, this means uprobe won't actually work.
Oleg.
^ permalink raw reply
* Re: [PATCH] powerpc/uprobes: teach uprobes to ignore gdb breakpoints
From: Oleg Nesterov @ 2013-03-21 15:58 UTC (permalink / raw)
To: Ananth N Mavinakayanahalli; +Cc: ppcdev, Srikar Dronamraju, stable
In-Reply-To: <20130321071545.GA5271@in.ibm.com>
On 03/21, Ananth N Mavinakayanahalli wrote:
>
> On Wed, Mar 20, 2013 at 05:06:44PM +0100, Oleg Nesterov wrote:
>
> > > > But we did not install UPROBE_SWBP_INSN. Is it fine? I hope yes, just to
> > > > verify. If not, we need 2 definitions. is_uprobe_insn() should still check
> > > > insns == UPROBE_SWBP_INSN, and is_swbp_insn() should check is_trap().
>
> Its fine from gdb's perspective with my patch.
Yes, but this doesn't look right from uprobe's perspective.
> > > So, install_breakpoint()->prepare_uprobe()->is_swbp_insn() will return
> > > ENOTSUPP. In fact, arch_uprobe_analyze_insn() will also do the same.
> >
> > Yes and the check in arch_uprobe_analyze_insn() should go away.
> >
> > But you missed my point. Please forget about prepare_uprobe(), it is
> > wrong anyway. And, prepare_uprobe() inspects the _original_ insn from
> > the file, this has nothing install_breakpoint/etc.
> >
> > I meant verify_opcode() called by install_breakpoint/etc.
>
> For the case where X already exists, verify_opcode() currently returns 0.
> IMO, it should return -EEXIST,
Oh, this is debatable. Currently we assume that uprobe should "win".
See below...
> unless you are proposing that uprobes
> should ride on the existing trap (even if its a variant).
Yes. And this is what the current implementation does.
> If you are proposing that uprobes ride on X if it already exists, that's
> not always possible and is a big can of worms... see below...
Sure. Whatever we do uprobe and gdb can confuse each other. Unless we
rework the vm code completely (not sure this is realistic).
> > OK. So, if I understand correctly, gdb can use some conditional
> > breakpoint, and it is possible that this insn won't generate the
> > trap?
>
> Yes it is possible if the condition is not met. If the condition is
> met, the instruction will generate a trap, and uprobes will do a
> send_sig(SIGTRAP) from handle_swbp().
Unless there is uprobe at the same address. Once again, uprobe wins.
Your patch only fixes the case when the task hits a non-UPROBE_SWBP_INSN
breakpoint and there is no uprobe at the same address.
> > Then this patch is not right, or at least we need another change
> > on top?
> >
> > Once again. Suppose that gdb installs the TRAP_IF_R1_GT_R2.
> >
> > After that uprobe_register() is called, but it won't change this
> > insn because verify_opcode() returns 0.
> >
> > Then the probed task hits this breakoint with "r1 < r2" and we do
> > not report this event.
>
> At this time, the condition for the trap is not satisfied, so no
> exception occurs.
Yes, and thus uprobe->handler() is not called, this was my point.
> If the expectation is that the trap always trigger,
> then all such trap variants need to be replaced with the unconditional
> trap
Yes. that is why I suggested the patch which doesn't affect verify_opcode().
uprobe_register() should replace the conditional trap with the unconditional
UPROBE_SWBP_INSN. uprobes should win.
> and we should either add logic to re-execute the condional trap
> after uprobe handling and send_sig() via handle_swbp() or emulate the
> condition in software and do a send_sig() if needed.
Unlikely this is possible. Or even desirable.
> > So. I still think that we actually need something like below, and
> > powerpc should reimplement is_trap_insn() to use is_trap(insn).
> >
> > No?
>
> I don't see how this will help,
Hmm. This should equally fix this particular problem? handle_swbp()
will send the trap if is_trap() == T?
Again, unless there is uprobe, but this was always true.
> especially since the gdb<->uprobes is
> fraught with races.
They can race anyway, whatever we do.
Unless we rework write_opcode/etc completely.
> With your proposed patch, we refuse to insert a uprobe if the underlying
> instruction is a UPROBE_SWBP_INSTRUCTION;
If "underlying" means the original insn in vma->file, this is already
true. My patch doesn't change this logic.
Otherwise - no, we do not refuse to insert a uprobe if this insn was
already changed by gdb.
> changing is_swbp_at_addr()
> will need changes in handle_swbp() too.
I don't think so. Why?
> But, unlike x86, we cannot
> expect a uprobe with an underlying trap variant (X) to always trigger.
And that is why I think write_opcode() should rewrite the conditional
trap.
> IMHO, its not a good idea to do that for x86 either,
This change has no effect fo x86.
> IMHO, I really think we should not allow uprobe_register() to succeed if
> the underlying instruction is a breakpoint (or a variant thereof).
I disagree.
Just for example. Suppose we change install_breakpoint() so that it fails
if the underlying instruction is int3. (once again, "underlying" does not
mean the original insn from vma->vm_file).
First of all, this is very much nontrivial. I simply do not see how we
can do this. If nothing else, uprobe_register() can race with uprobe_mmap()
and install_breakpoint() can be called twice with the same vaddr. With
this change register or mmap can fail.
But suppose you can do this. Now you can write the trivial application
which mmaps glibc and inserts int3 into, say, getpid()'s vaddr. Voila,
this makes "perf probe -x /lib/libc.so.6" impossible, uprobe_register()
will fail.
Whatever you think about this logic, it was desidned to assume that
install_breakpoint() should be "idempotent", and we ignore the races
with gdb. We should only ensure that the kernel can't crash/etc.
And uprobe can "steal" the trap from gdb if they race, again this is by
design. and your patch can't prevent this but complicates the rules.
I already said this many times, but let me repeat. is_swbp_isn() and
its usage is confusing. Lets forget about prepare_uprobe(). Now,
- verify_opcode()->is_swbp_insn() means:
is this insn fine for uprobe? (we do not care about
gdb, we simply ignore this problem)
- is_swbp_at_addr()->is_swbp_insn() means:
there is no uprobe, should we send SIGTRAP ?
And the patch I sent separates these 2 cases.
Finally. If we want to eliminate the gdb/uprobes races/confusions,
we can not simply use a PageAnon() page, we shuld rewrite this code
completely. I can quote the very old email I sent you:
The proper fix, I think, is to rework the whole idea about uprobe bps,
but this is really "in the long term". install_breakpoint() should
only unmap the page and mark its pte as "owned by kernel, FOLL_WRITE
should not work". Something like migration or PROT_NONE. The task
itself should install bp during the page fault. And we need the
"backing store" for the pages with uprobes. Yes, this all is very
vague and I can be wrong.
IOW, somehow we should ensure that once uprobe changes the page, nobody
else can change it until uprobe_unregister().
Oleg.
^ permalink raw reply
* Re: MPC5121e, Linux, simple IO ports
From: CF Studelec @ 2013-03-21 13:44 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <514ACAD6.6010909@studelec-sa.com>
Sorry to bump the post, i'm wondering if it was correctly sent.
Le 21/03/2013 09:54, CF Studelec a écrit :
> Hello,
>
> This is a simple board base on mpc5121e MCU.
>
>
> Gpio is detected: kernel is compiled with its support - i got
> gpiochip_find_base: found new base @224 in dmesg - on kernel 3.0.4.
>
>
> But i'm unable to access it through /sys/class/gpio. I can successfully
> export a pin (ie, if i type cat 224 > export, gpio224 is created), but i
> can't successfully control it:
>
>
>
> echo "out" > /sys/class/gpio/gpio224/direction
>
> cat /sys/class/gpio/gpio224/value
>
> 0
>
> echo 1 > /sys/class/gpio/gpio224/value
>
> cat /sys/class/gpio/gpio224/value
>
> 0
>
>
>
> My need is a simple chipselect (well, 3 chipselect exactly ), for a
> custom design. Running linux is mandatory. I suspect the MPC5121e to be
> in the bad function mode, so:
>
> - does anyone knows how to change mode ? What register can i acces and
> how ? does it worths a try ?
>
> - does anyone successfully performed simple IO control ?
>
>
>
> Last thing, i have tryed to access internal registers through /dev/mem,
> but no success. There are very few ressources available for this
> microcontroler, but i'm stick to it. Perhaps anybody knows how to access
> (read) internal registers with /proc or sys-fs ?
>
>
>
> Thank you for your help.
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH] [RFC] powerpc: Add VDSO version of time
From: Adhemerval Zanella @ 2013-03-21 13:40 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1363755620.18880.27.camel@pasglop>
On 20-03-2013 02:00, Benjamin Herrenschmidt wrote:
> On Tue, 2013-03-19 at 16:55 -0300, Adhemerval Zanella wrote:
>> I focused on 64 bit kernel, do I need to provide a scheme for 32 bits
>> as well?
> You did provide both 32 and 64-bit VDSO implementations so 32-bit
> kernels should be covered.
Indeed and thanks for the reply. Any objection or request about including it?
Thanks.
^ permalink raw reply
* Re: [Suggestion] PowerPC: kernel: cross compiling issue with allmodconfig
From: Benjamin Herrenschmidt @ 2013-03-21 12:38 UTC (permalink / raw)
To: Chen Gang F T
Cc: sfr, Michael Neuling, matt, Chen Gang,
linux-kernel@vger.kernel.org, paulus@samba.org, imunsie,
linuxppc-dev
In-Reply-To: <514AC418.1070806@gmail.com>
On Thu, 2013-03-21 at 16:26 +0800, Chen Gang F T wrote:
> it seems:
> only move slb_miss_realmode to the end, can fix this issue without negative effect.
Thanks. I'm currently on vacation, I'll have a closer look when I'm back
unless Stephen or Paulus wants to shoot that to Linus while I'm
away.
Cheers,
Ben.
>
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index 200afa5..56bd923 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -1066,78 +1066,6 @@ unrecov_user_slb:
> #endif /* __DISABLED__ */
>
>
> -/*
> - * r13 points to the PACA, r9 contains the saved CR,
> - * r12 contain the saved SRR1, SRR0 is still ready for return
> - * r3 has the faulting address
> - * r9 - r13 are saved in paca->exslb.
> - * r3 is saved in paca->slb_r3
> - * We assume we aren't going to take any exceptions during this procedure.
> - */
> -_GLOBAL(slb_miss_realmode)
> - mflr r10
> -#ifdef CONFIG_RELOCATABLE
> - mtctr r11
> -#endif
> -
> - stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
> - std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
> -
> - bl .slb_allocate_realmode
> -
> - /* All done -- return from exception. */
> -
> - ld r10,PACA_EXSLB+EX_LR(r13)
> - ld r3,PACA_EXSLB+EX_R3(r13)
> - lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
> -
> - mtlr r10
> -
> - andi. r10,r12,MSR_RI /* check for unrecoverable exception */
> - beq- 2f
> -
> -.machine push
> -.machine "power4"
> - mtcrf 0x80,r9
> - mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
> -.machine pop
> -
> - RESTORE_PPR_PACA(PACA_EXSLB, r9)
> - ld r9,PACA_EXSLB+EX_R9(r13)
> - ld r10,PACA_EXSLB+EX_R10(r13)
> - ld r11,PACA_EXSLB+EX_R11(r13)
> - ld r12,PACA_EXSLB+EX_R12(r13)
> - ld r13,PACA_EXSLB+EX_R13(r13)
> - rfid
> - b . /* prevent speculative execution */
> -
> -2: mfspr r11,SPRN_SRR0
> - ld r10,PACAKBASE(r13)
> - LOAD_HANDLER(r10,unrecov_slb)
> - mtspr SPRN_SRR0,r10
> - ld r10,PACAKMSR(r13)
> - mtspr SPRN_SRR1,r10
> - rfid
> - b .
> -
> -unrecov_slb:
> - EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
> - DISABLE_INTS
> - bl .save_nvgprs
> -1: addi r3,r1,STACK_FRAME_OVERHEAD
> - bl .unrecoverable_exception
> - b 1b
> -
> -
> -#ifdef CONFIG_PPC_970_NAP
> -power4_fixup_nap:
> - andc r9,r9,r10
> - std r9,TI_LOCAL_FLAGS(r11)
> - ld r10,_LINK(r1) /* make idle task do the */
> - std r10,_NIP(r1) /* equivalent of a blr */
> - blr
> -#endif
> -
> .align 7
> .globl alignment_common
> alignment_common:
> @@ -1336,6 +1264,78 @@ _GLOBAL(opal_mc_secondary_handler)
>
>
> /*
> + * r13 points to the PACA, r9 contains the saved CR,
> + * r12 contain the saved SRR1, SRR0 is still ready for return
> + * r3 has the faulting address
> + * r9 - r13 are saved in paca->exslb.
> + * r3 is saved in paca->slb_r3
> + * We assume we aren't going to take any exceptions during this procedure.
> + */
> +_GLOBAL(slb_miss_realmode)
> + mflr r10
> +#ifdef CONFIG_RELOCATABLE
> + mtctr r11
> +#endif
> +
> + stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
> + std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
> +
> + bl .slb_allocate_realmode
> +
> + /* All done -- return from exception. */
> +
> + ld r10,PACA_EXSLB+EX_LR(r13)
> + ld r3,PACA_EXSLB+EX_R3(r13)
> + lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
> +
> + mtlr r10
> +
> + andi. r10,r12,MSR_RI /* check for unrecoverable exception */
> + beq- 2f
> +
> +.machine push
> +.machine "power4"
> + mtcrf 0x80,r9
> + mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
> +.machine pop
> +
> + RESTORE_PPR_PACA(PACA_EXSLB, r9)
> + ld r9,PACA_EXSLB+EX_R9(r13)
> + ld r10,PACA_EXSLB+EX_R10(r13)
> + ld r11,PACA_EXSLB+EX_R11(r13)
> + ld r12,PACA_EXSLB+EX_R12(r13)
> + ld r13,PACA_EXSLB+EX_R13(r13)
> + rfid
> + b . /* prevent speculative execution */
> +
> +2: mfspr r11,SPRN_SRR0
> + ld r10,PACAKBASE(r13)
> + LOAD_HANDLER(r10,unrecov_slb)
> + mtspr SPRN_SRR0,r10
> + ld r10,PACAKMSR(r13)
> + mtspr SPRN_SRR1,r10
> + rfid
> + b .
> +
> +unrecov_slb:
> + EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
> + DISABLE_INTS
> + bl .save_nvgprs
> +1: addi r3,r1,STACK_FRAME_OVERHEAD
> + bl .unrecoverable_exception
> + b 1b
> +
> +
> +#ifdef CONFIG_PPC_970_NAP
> +power4_fixup_nap:
> + andc r9,r9,r10
> + std r9,TI_LOCAL_FLAGS(r11)
> + ld r10,_LINK(r1) /* make idle task do the */
> + std r10,_NIP(r1) /* equivalent of a blr */
> + blr
> +#endif
> +
> +/*
> * Hash table stuff
> */
> .align 7
>
>
> On 2013年03月21日 13:55, Chen Gang wrote:
> > Hello All:
> >
> > summary:
> > the root cause is no enough room in exception area (0x5500 -- 0x7000).
> >
> > it is caused by the patches "for saving/restre PPR":
> > they consumed much space of this area (0x5500 -- 0x7000).
> > for pseries_defconfig and ppc64_defconfig, it is still ok.
> > but for allmodconfig and "some additional config", it will cause issue.
> >
> > the solving patch "Make room in exception vector area" can make room larger.
> > it can let "some additional config" ok.
> > but for allmodconfig, it is still not enough.
> >
> >
> > details
> > reason:
> > it is caused by:
> > commit number: 13e7a8e846c2ea38a552b986ea49332f965bbb7a
> > commit number: 44e9309f1f357794b7ae93d5f3e3e6f11d2b8a7f
> > they are "for saving/restore PPR"
> > by Haren Myneni <haren@linux.vnet.ibm.com> Thu, 6 Dec 2012
> > compiling result:
> > pseries_defconfig: pass (cpu for POWER7)
> > ppc64_defconfig: pass (cpu for POWER7)
> > allmodconfig: failed (cpu for POWER7)
> >
> > analysing:
> > solving patch:
> > ------------------------------------------------------------------
> > commit number: 61383407677aef05928541a00678591abea2d84c
> > Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > Date: Thu Jan 10 17:44:19 2013 +1100
> >
> > powerpc: Make room in exception vector area
> >
> > The FWNMI region is fixed at 0x7000 and the vector are now
> > overflowing that with some configurations. Fix that by moving
> > some hash management code out of that region as it doesn't need
> > to be that close to the call sites (isn't accessed using
> > conditional branches).
> > ------------------------------------------------------------------
> >
> > but for allmodconfig (not only for "some configurations"):
> > it really can reduce much overflow bytes,
> > (maybe from hundreds bytes to dozens bytes)
> > but still not enough (still content overflow bytes)
> >
> > additional trying:
> > after del CONFIG_VSX and CONFIG_PPC_970_NAP in allmodconfig,
> > (will reduce dozens bytes in the region .0x5500 -- .0x7000)
> > it can pass compiling (not overflow).
> >
> >
> > next:
> > I am sorry:
> > I am not quite familiar with the detail features of powerpc.
> > it seems I am not the suitable member to continue trying.
> >
> > I prefer Benjamin to continue trying (just like what he has done).
> >
> > if Benjamin will not do it (e.g. maybe no time to do)
> > I should continue: "make additional room in exception vector area".
> > (if get no reply within a week: before 2013-03-28, I should continue)
> >
> >
> >
> > welcome any members' (especially Benjamin) suggestions or completions.
> >
> > thanks.
> >
> > :-)
> >
> >
> > On 2013年03月15日 13:14, Chen Gang wrote:
> >> 于 2013年03月15日 12:52, Michael Neuling 写道:
> >>> Yep it's a known problem but no one has bothered to fix it since it
> >>> doesn't happen in a config that anyone cares about like
> >>> pseries_defconfig and ppc64_defconfig. We've been moving code around in
> >>> this area a lot recently hence the breakage.
> >>>
> >>> It should be fixed though. Patches welcome. :-)
> >>
> >> thanks, and I should try, and very glad to try.
> >>
> >> :-) :-)
> >>
> >> excuse me, I try to provide related patch within this month (2013-03-31), is it ok ?
> >> the reason is:
> >> I am not familiar with ppc assembly code, neither ppc kernel,
> >> so need additional time resource.
> >> (originally, I worked for x86(_64) core dump analysing for kernel and user programs)
> >>
> >> thanks.
> >>
> >
> >
>
>
^ permalink raw reply
* Re: [PATCH] KVM: PPC: e500: Add separate functions for vcpu's MMU configuration
From: Alexander Graf @ 2013-03-21 11:48 UTC (permalink / raw)
To: Caraman Mihai Claudiu-B02008
Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org
In-Reply-To: <300B73AA675FCE4A93EB4FC1D42459FF373151@039-SN2MPN1-012.039d.mgd.msft.net>
On 21.03.2013, at 12:19, Caraman Mihai Claudiu-B02008 wrote:
>> -----Original Message-----
>> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
>> owner@vger.kernel.org] On Behalf Of Alexander Graf
>> Sent: Thursday, March 21, 2013 12:07 PM
>> To: Caraman Mihai Claudiu-B02008
>> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org
>> Subject: Re: [PATCH] KVM: PPC: e500: Add separate functions for =
vcpu's
>> MMU configuration
>>=20
>>=20
>> On 19.03.2013, at 18:16, Mihai Caraman wrote:
>>=20
>>> Move vcpu's MMU default configuration and geometry update into their
>> own
>>> functions.
>>=20
>> Mind to explain why?
>=20
> You requested a separate function for clearing TLBnCFG_IND bit (E.PT =
removal)
> to self-document the code. The existing logic (that TLBnCFG_IND relies =
on)
> was buried in a chunk of code and I thought this will add more =
clarity.
> If you don't agree I would document the code at least.
I guess I'll have to see the full picture then. Please just include this =
patch in the series when you change the IND bit and make the patch =
description a bit more obvious: Just indicate that you need this a =
cleanup to make the IND patch more readable.
Alex
^ permalink raw reply
* RE: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
From: Caraman Mihai Claudiu-B02008 @ 2013-03-21 11:42 UTC (permalink / raw)
To: Alexander Graf
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org,
kvm@vger.kernel.org, kvm-ppc@vger.kernel.org
In-Reply-To: <53B128A9-FE74-4C85-994B-6A8674270C8B@suse.de>
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Thursday, March 21, 2013 1:07 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: Wood Scott-B07421; kvm-ppc@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; kvm@vger.kernel.org
> Subject: Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
>=20
>=20
> On 21.03.2013, at 12:02, Caraman Mihai Claudiu-B02008 wrote:
>=20
> >
> >
> >> -----Original Message-----
> >> From: Alexander Graf [mailto:agraf@suse.de]
> >> Sent: Thursday, March 21, 2013 12:07 PM
> >> To: Wood Scott-B07421
> >> Cc: Caraman Mihai Claudiu-B02008; kvm-ppc@vger.kernel.org; linuxppc-
> >> dev@lists.ozlabs.org; kvm@vger.kernel.org
> >> Subject: Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
> >>
> >>
> >> On 19.03.2013, at 18:26, Scott Wood wrote:
> >>
> >>> On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:
> >>>> diff --git a/arch/powerpc/kvm/e500_mmu.c
> b/arch/powerpc/kvm/e500_mmu.c
> >>>> index 66b6e31..b77b855 100644
> >>>> --- a/arch/powerpc/kvm/e500_mmu.c
> >>>> +++ b/arch/powerpc/kvm/e500_mmu.c
> >>>> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu
> >> *vcpu, struct kvm_sregs *sregs)
> >>>> return 0;
> >>>> }
> >>>> +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> >>>> + union kvmppc_one_reg *val)
> >>>
> >>> s/500/e500/
> >>>
> >>>> +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> >>>> + union kvmppc_one_reg *val)
> >>>> +{
> >>>> + int r =3D 0;
> >>>> + long int i;
> >>>> +
> >>>> + switch (id) {
> >>>> + case KVM_REG_PPC_MAS0:
> >>>> + vcpu->arch.shared->mas0 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MAS1:
> >>>> + vcpu->arch.shared->mas1 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MAS2:
> >>>> + vcpu->arch.shared->mas2 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MAS7_3:
> >>>> + vcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MAS4:
> >>>> + vcpu->arch.shared->mas4 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MAS6:
> >>>> + vcpu->arch.shared->mas6 =3D set_reg_val(id, *val);
> >>>> + break;
> >>>> + case KVM_REG_PPC_MMUCFG: {
> >>>> + u32 mmucfg =3D set_reg_val(id, *val);
> >>>> + vcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE;
> >>>> + break;
> >>>> + }
> >>>
> >>> Do we really want to allow arbitrary MMUCFG changes? It won't
> >> magically make us able to support larger RAs, PIDs, different MAVN,
> etc.
> >
> > Not magically, some changes e.g TLBnCFG_IND or TLBnPS require just a
> kvm
> > check other changes e.g. TLBnCFG_MAVN require additional support and we
> > might not implement all of them. Until then this code should do the
> job:
> >
> > /* MMU registers can be set only to the configuration supported by
> KVM */
> > case KVM_REG_PPC_MMUCFG: {
> > if (set_reg_val(id, *val) !=3D vcpu->arch.mmucfg)
> > r =3D -EINVAL;
> > break;
> > }
>=20
> Yes :).
>=20
> >
> >>
> >> Only if we update the actual shadow mmu configuration as well.
> >
> > These registers (MMUCFG, EPTCFG, TLBnCFG, TLBnPS) are read-only (and
> shared
> > between e6500 threads), we can only emulate them.
>=20
> We need to change the behavior of the shadow mmu as well. It's not about
> the registers, but the actually exposed TLBs. If you configure 4 TLBs,
> and you announce to the guest that you can do 4 TLBs, you better emulate
> 4 TLBs :).
Right, like the rest of configs I was talking above:)
-Mike
^ permalink raw reply
* RE: [PATCH] KVM: PPC: e500: Add separate functions for vcpu's MMU configuration
From: Caraman Mihai Claudiu-B02008 @ 2013-03-21 11:19 UTC (permalink / raw)
To: Alexander Graf
Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org
In-Reply-To: <90E4FFA9-97C8-4D7D-910E-2E5DB273C88C@suse.de>
> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-
> owner@vger.kernel.org] On Behalf Of Alexander Graf
> Sent: Thursday, March 21, 2013 12:07 PM
> To: Caraman Mihai Claudiu-B02008
> Cc: kvm-ppc@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org
> Subject: Re: [PATCH] KVM: PPC: e500: Add separate functions for vcpu's
> MMU configuration
>=20
>=20
> On 19.03.2013, at 18:16, Mihai Caraman wrote:
>=20
> > Move vcpu's MMU default configuration and geometry update into their
> own
> > functions.
>=20
> Mind to explain why?
You requested a separate function for clearing TLBnCFG_IND bit (E.PT remova=
l)
to self-document the code. The existing logic (that TLBnCFG_IND relies on)
was buried in a chunk of code and I thought this will add more clarity.
If you don't agree I would document the code at least.
-Mike
>=20
>=20
> Alex
>=20
> >
> > Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> > ---
> > arch/powerpc/kvm/e500_mmu.c | 59 +++++++++++++++++++++++++++---------
> -------
> > 1 files changed, 37 insertions(+), 22 deletions(-)
> >
> > diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> > index 5c44759..66b6e31 100644
> > --- a/arch/powerpc/kvm/e500_mmu.c
> > +++ b/arch/powerpc/kvm/e500_mmu.c
> > @@ -596,6 +596,20 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu
> *vcpu, struct kvm_sregs *sregs)
> > return 0;
> > }
> >
> > +static int vcpu_mmu_geometry_update(struct kvm_vcpu *vcpu,
> > + struct kvm_book3e_206_tlb_params *params)
> > +{
> > + vcpu->arch.tlbcfg[0] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > + if (params->tlb_sizes[0] <=3D 2048)
> > + vcpu->arch.tlbcfg[0] |=3D params->tlb_sizes[0];
> > + vcpu->arch.tlbcfg[0] |=3D params->tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
> > +
> > + vcpu->arch.tlbcfg[1] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > + vcpu->arch.tlbcfg[1] |=3D params->tlb_sizes[1];
> > + vcpu->arch.tlbcfg[1] |=3D params->tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
> > + return 0;
> > +}
> > +
> > int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
> > struct kvm_config_tlb *cfg)
> > {
> > @@ -692,16 +706,8 @@ int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu
> *vcpu,
> > vcpu_e500->gtlb_offset[0] =3D 0;
> > vcpu_e500->gtlb_offset[1] =3D params.tlb_sizes[0];
> >
> > - vcpu->arch.mmucfg =3D mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
> > -
> > - vcpu->arch.tlbcfg[0] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > - if (params.tlb_sizes[0] <=3D 2048)
> > - vcpu->arch.tlbcfg[0] |=3D params.tlb_sizes[0];
> > - vcpu->arch.tlbcfg[0] |=3D params.tlb_ways[0] << TLBnCFG_ASSOC_SHIFT;
> > -
> > - vcpu->arch.tlbcfg[1] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > - vcpu->arch.tlbcfg[1] |=3D params.tlb_sizes[1];
> > - vcpu->arch.tlbcfg[1] |=3D params.tlb_ways[1] << TLBnCFG_ASSOC_SHIFT;
> > + /* Update vcpu's MMU geometry based on SW_TLB input */
> > + vcpu_mmu_geometry_update(vcpu, ¶ms);
> >
> > vcpu_e500->shared_tlb_pages =3D pages;
> > vcpu_e500->num_shared_tlb_pages =3D num_pages;
> > @@ -737,6 +743,26 @@ int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu
> *vcpu,
> > return 0;
> > }
> >
> > +/* vcpu's MMU default configuration */
> > +static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
> > + struct kvmppc_e500_tlb_params *params)
> > +{
> > + /* Initialize RASIZE, PIDSIZE, NTLBS and MAVN fields with host
> values*/
> > + vcpu->arch.mmucfg =3D mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
> > +
> > + /* Initialize IPROT field with host value*/
> > + vcpu->arch.tlbcfg[0] =3D mfspr(SPRN_TLB0CFG) &
> > + ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > + vcpu->arch.tlbcfg[0] |=3D params[0].entries;
> > + vcpu->arch.tlbcfg[0] |=3D params[0].ways << TLBnCFG_ASSOC_SHIFT;
> > +
> > + vcpu->arch.tlbcfg[1] =3D mfspr(SPRN_TLB1CFG) &
> > + ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > + vcpu->arch.tlbcfg[1] |=3D params[1].entries;
> > + vcpu->arch.tlbcfg[1] |=3D params[1].ways << TLBnCFG_ASSOC_SHIFT;
> > + return 0;
> > +}
> > +
> > int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
> > {
> > struct kvm_vcpu *vcpu =3D &vcpu_e500->vcpu;
> > @@ -781,18 +807,7 @@ int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500
> *vcpu_e500)
> > if (!vcpu_e500->g2h_tlb1_map)
> > goto err;
> >
> > - /* Init TLB configuration register */
> > - vcpu->arch.tlbcfg[0] =3D mfspr(SPRN_TLB0CFG) &
> > - ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > - vcpu->arch.tlbcfg[0] |=3D vcpu_e500->gtlb_params[0].entries;
> > - vcpu->arch.tlbcfg[0] |=3D
> > - vcpu_e500->gtlb_params[0].ways << TLBnCFG_ASSOC_SHIFT;
> > -
> > - vcpu->arch.tlbcfg[1] =3D mfspr(SPRN_TLB1CFG) &
> > - ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> > - vcpu->arch.tlbcfg[1] |=3D vcpu_e500->gtlb_params[1].entries;
> > - vcpu->arch.tlbcfg[1] |=3D
> > - vcpu_e500->gtlb_params[1].ways << TLBnCFG_ASSOC_SHIFT;
> > + vcpu_mmu_init(vcpu, vcpu_e500->gtlb_params);
> >
> > kvmppc_recalc_tlb1map_range(vcpu_e500);
> > return 0;
> > --
> > 1.7.4.1
> >
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
>=20
> --
> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] powerpc: drop even more unused Kconfig symbols
From: Paul Bolle @ 2013-03-21 11:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev, linux-kernel
When I submitted commit 6805ab6daa2b589fe3242d05ddc47a9dbb0c4eb1
("powerpc: drop unused Kconfig symbols") I apparently failed to notice
that my patch also made PREP_RESIDUAL and PPC_A2_DD2 unused. Drop these
now.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
---
0) Untested.
1) I investigated these Kconfig files a bit and discovered that PPC_PREP
is marked BROKEN since v2.6.15, see commit
5be396b00ca0f2f769c55cf69bbd7c77451c925e ("powerpc: Mark PREP and
embedded as broken for now"). Though it's not my problem, this does
suggest PReP support can be removed entirely.
arch/powerpc/platforms/prep/Kconfig | 13 -------------
arch/powerpc/platforms/wsp/Kconfig | 4 ----
2 files changed, 17 deletions(-)
diff --git a/arch/powerpc/platforms/prep/Kconfig b/arch/powerpc/platforms/prep/Kconfig
index 1547f66..2036e7e 100644
--- a/arch/powerpc/platforms/prep/Kconfig
+++ b/arch/powerpc/platforms/prep/Kconfig
@@ -8,16 +8,3 @@ config PPC_PREP
select PPC_UDBG_16550
select PPC_NATIVE
default n
-
-config PREP_RESIDUAL
- bool "Support for PReP Residual Data"
- depends on PPC_PREP
- help
- Some PReP systems have residual data passed to the kernel by the
- firmware. This allows detection of memory size, devices present and
- other useful pieces of information. Sometimes this information is
- not present or incorrect, in which case it could lead to the machine
- behaving incorrectly. If this happens, either disable PREP_RESIDUAL
- or pass the 'noresidual' option to the kernel.
-
- If you are running a PReP system, say Y here, otherwise say N.
diff --git a/arch/powerpc/platforms/wsp/Kconfig b/arch/powerpc/platforms/wsp/Kconfig
index 79d2225..9eea710 100644
--- a/arch/powerpc/platforms/wsp/Kconfig
+++ b/arch/powerpc/platforms/wsp/Kconfig
@@ -29,7 +29,3 @@ config PPC_CHROMA
default y
endmenu
-
-config PPC_A2_DD2
- bool "Support for DD2 based A2/WSP systems"
- depends on PPC_A2
--
1.7.11.7
^ permalink raw reply related
* Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
From: Alexander Graf @ 2013-03-21 11:06 UTC (permalink / raw)
To: Caraman Mihai Claudiu-B02008
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org,
kvm@vger.kernel.org, kvm-ppc@vger.kernel.org
In-Reply-To: <300B73AA675FCE4A93EB4FC1D42459FF37304B@039-SN2MPN1-012.039d.mgd.msft.net>
On 21.03.2013, at 12:02, Caraman Mihai Claudiu-B02008 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Alexander Graf [mailto:agraf@suse.de]
>> Sent: Thursday, March 21, 2013 12:07 PM
>> To: Wood Scott-B07421
>> Cc: Caraman Mihai Claudiu-B02008; kvm-ppc@vger.kernel.org; linuxppc-
>> dev@lists.ozlabs.org; kvm@vger.kernel.org
>> Subject: Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
>>=20
>>=20
>> On 19.03.2013, at 18:26, Scott Wood wrote:
>>=20
>>> On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:
>>>> diff --git a/arch/powerpc/kvm/e500_mmu.c =
b/arch/powerpc/kvm/e500_mmu.c
>>>> index 66b6e31..b77b855 100644
>>>> --- a/arch/powerpc/kvm/e500_mmu.c
>>>> +++ b/arch/powerpc/kvm/e500_mmu.c
>>>> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu
>> *vcpu, struct kvm_sregs *sregs)
>>>> return 0;
>>>> }
>>>> +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
>>>> + union kvmppc_one_reg *val)
>>>=20
>>> s/500/e500/
>>>=20
>>>> +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
>>>> + union kvmppc_one_reg *val)
>>>> +{
>>>> + int r =3D 0;
>>>> + long int i;
>>>> +
>>>> + switch (id) {
>>>> + case KVM_REG_PPC_MAS0:
>>>> + vcpu->arch.shared->mas0 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MAS1:
>>>> + vcpu->arch.shared->mas1 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MAS2:
>>>> + vcpu->arch.shared->mas2 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MAS7_3:
>>>> + vcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MAS4:
>>>> + vcpu->arch.shared->mas4 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MAS6:
>>>> + vcpu->arch.shared->mas6 =3D set_reg_val(id, *val);
>>>> + break;
>>>> + case KVM_REG_PPC_MMUCFG: {
>>>> + u32 mmucfg =3D set_reg_val(id, *val);
>>>> + vcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE;
>>>> + break;
>>>> + }
>>>=20
>>> Do we really want to allow arbitrary MMUCFG changes? It won't
>> magically make us able to support larger RAs, PIDs, different MAVN, =
etc.
>=20
> Not magically, some changes e.g TLBnCFG_IND or TLBnPS require just a =
kvm
> check other changes e.g. TLBnCFG_MAVN require additional support and =
we
> might not implement all of them. Until then this code should do the =
job:
>=20
> /* MMU registers can be set only to the configuration supported =
by KVM */
> case KVM_REG_PPC_MMUCFG: {
> if (set_reg_val(id, *val) !=3D vcpu->arch.mmucfg)
> r =3D -EINVAL;
> break;
> }
Yes :).
>=20
>>=20
>> Only if we update the actual shadow mmu configuration as well.
>=20
> These registers (MMUCFG, EPTCFG, TLBnCFG, TLBnPS) are read-only (and =
shared
> between e6500 threads), we can only emulate them.
We need to change the behavior of the shadow mmu as well. It's not about =
the registers, but the actually exposed TLBs. If you configure 4 TLBs, =
and you announce to the guest that you can do 4 TLBs, you better emulate =
4 TLBs :).
Alex
^ permalink raw reply
* RE: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
From: Caraman Mihai Claudiu-B02008 @ 2013-03-21 11:02 UTC (permalink / raw)
To: Alexander Graf, Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org,
kvm-ppc@vger.kernel.org
In-Reply-To: <5F65F205-3B81-4154-B9E0-43FA1100A3FD@suse.de>
> -----Original Message-----
> From: Alexander Graf [mailto:agraf@suse.de]
> Sent: Thursday, March 21, 2013 12:07 PM
> To: Wood Scott-B07421
> Cc: Caraman Mihai Claudiu-B02008; kvm-ppc@vger.kernel.org; linuxppc-
> dev@lists.ozlabs.org; kvm@vger.kernel.org
> Subject: Re: [PATCH] KVM: PPC: e500: Expose MMU registers via ONE_REG
>=20
>=20
> On 19.03.2013, at 18:26, Scott Wood wrote:
>=20
> > On 03/19/2013 12:17:11 PM, Mihai Caraman wrote:
> >> diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> >> index 66b6e31..b77b855 100644
> >> --- a/arch/powerpc/kvm/e500_mmu.c
> >> +++ b/arch/powerpc/kvm/e500_mmu.c
> >> @@ -596,6 +596,95 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu
> *vcpu, struct kvm_sregs *sregs)
> >> return 0;
> >> }
> >> +int kvmppc_get_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> >> + union kvmppc_one_reg *val)
> >
> > s/500/e500/
> >
> >> +int kvmppc_set_one_reg_500_tlb(struct kvm_vcpu *vcpu, u64 id,
> >> + union kvmppc_one_reg *val)
> >> +{
> >> + int r =3D 0;
> >> + long int i;
> >> +
> >> + switch (id) {
> >> + case KVM_REG_PPC_MAS0:
> >> + vcpu->arch.shared->mas0 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MAS1:
> >> + vcpu->arch.shared->mas1 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MAS2:
> >> + vcpu->arch.shared->mas2 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MAS7_3:
> >> + vcpu->arch.shared->mas7_3 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MAS4:
> >> + vcpu->arch.shared->mas4 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MAS6:
> >> + vcpu->arch.shared->mas6 =3D set_reg_val(id, *val);
> >> + break;
> >> + case KVM_REG_PPC_MMUCFG: {
> >> + u32 mmucfg =3D set_reg_val(id, *val);
> >> + vcpu->arch.mmucfg =3D mmucfg & ~MMUCFG_LPIDSIZE;
> >> + break;
> >> + }
> >
> > Do we really want to allow arbitrary MMUCFG changes? It won't
> magically make us able to support larger RAs, PIDs, different MAVN, etc.
Not magically, some changes e.g TLBnCFG_IND or TLBnPS require just a kvm
check other changes e.g. TLBnCFG_MAVN require additional support and we
might not implement all of them. Until then this code should do the job:
/* MMU registers can be set only to the configuration supported by KVM */
case KVM_REG_PPC_MMUCFG: {
if (set_reg_val(id, *val) !=3D vcpu->arch.mmucfg)
r =3D -EINVAL;
break;
}
>=20
> Only if we update the actual shadow mmu configuration as well.
These registers (MMUCFG, EPTCFG, TLBnCFG, TLBnPS) are read-only (and shared
between e6500 threads), we can only emulate them.
-Mike
^ permalink raw reply
* RE: [PATCH V2] powerpc/85xx: workaround for chips with MSI hardware errata
From: Jia Hongtao-B38951 @ 2013-03-21 10:22 UTC (permalink / raw)
To: Wood Scott-B07421, Kumar Gala
Cc: linuxppc-dev@lists.ozlabs.org, Li Yang-R58472
In-Reply-To: <1363710693.16671.7@snotra>
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, March 20, 2013 12:32 AM
> To: Jia Hongtao-B38951
> Cc: Kumar Gala; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
> michael@ellerman.id.au; Li Yang-R58472
> Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
> hardware errata
>=20
> ;On 03/19/2013 03:03:13 AM, Jia Hongtao-B38951 wrote:
> >
> >
> > > -----Original Message-----
> > > From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > > Sent: Friday, March 15, 2013 11:53 PM
> > > To: Jia Hongtao-B38951
> > > Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
> > > michael@ellerman.id.au; Li Yang-R58472
> > > Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with MSI
> > > hardware errata
> > >
> > >
> > > On Mar 14, 2013, at 9:00 PM, Jia Hongtao-B38951 wrote:
> > >
> > > >
> > > >
> > > >> -----Original Message-----
> > > >> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > > >> Sent: Friday, March 15, 2013 4:05 AM
> > > >> To: Jia Hongtao-B38951
> > > >> Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
> > > >> michael@ellerman.id.au; Li Yang-R58472; Jia Hongtao-B38951
> > > >> Subject: Re: [PATCH V2] powerpc/85xx: workaround for chips with
> > MSI
> > > >> hardware errata
> > > >>
> > > >>
> > > >> On Mar 14, 2013, at 5:35 AM, Jia Hongtao wrote:
> > > >>
> > > >>> The MPIC version 2.0 has a MSI errata (errata PIC1 of mpc8544),
> > It
> > > >>> causes that neither MSI nor MSI-X can work fine. This is a
> > > >>> workaround to allow MSI-X to function properly.
> > > >>>
> > > >>> Signed-off-by: Liu Shuo <soniccat.liu@gmail.com>
> > > >>> Signed-off-by: Li Yang <leoli@freescale.com>
> > > >>> Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
> > > >>> ---
> > > >>> Changes for V2:
> > > >>> - Address almost all the comments from Michael Ellerman for V1.
> > > >>> Here is the link:
> > > >>> http://patchwork.ozlabs.org/patch/226833/
> > > >>>
> > > >>> arch/powerpc/sysdev/fsl_msi.c | 65
> > > >>> +++++++++++++++++++++++++++++++++++++++++--
> > > >>> arch/powerpc/sysdev/fsl_msi.h | 2 ++
> > > >>> 2 files changed, 64 insertions(+), 3 deletions(-)
> > > >>>
> > > >>> diff --git a/arch/powerpc/sysdev/fsl_msi.c
> > > >>> b/arch/powerpc/sysdev/fsl_msi.c index 178c994..54cb83e 100644
> > > >>> --- a/arch/powerpc/sysdev/fsl_msi.c
> > > >>> +++ b/arch/powerpc/sysdev/fsl_msi.c
> > > >>> @@ -98,8 +98,18 @@ static int fsl_msi_init_allocator(struct
> > fsl_msi
> > > >>> *msi_data)
> > > >>>
> > > >>> static int fsl_msi_check_device(struct pci_dev *pdev, int nvec,
> > int
> > > >>> type) {
> > > >>> - if (type =3D=3D PCI_CAP_ID_MSIX)
> > > >>> - pr_debug("fslmsi: MSI-X untested, trying
> > anyway.\n");
> > > >>> + struct fsl_msi *msi;
> > > >>> +
> > > >>> + if (type =3D=3D PCI_CAP_ID_MSI) {
> > > >>> + /*
> > > >>> + * MPIC version 2.0 has erratum PIC1. For now
> > MSI
> > > >>> + * could not work. So check to prevent MSI from
> > > >>> + * being used on the board with this erratum.
> > > >>> + */
> > > >>> + list_for_each_entry(msi, &msi_head, list)
> > > >>> + if (msi->feature & MSI_HW_ERRATA_ENDIAN)
> > > >>> + return -EINVAL;
> > > >>> + }
> > > >>>
> > > >>> return 0;
> > > >>> }
> > > >>> @@ -142,7 +152,17 @@ static void fsl_compose_msi_msg(struct
> > pci_dev
> > > >> *pdev, int hwirq,
> > > >>> msg->address_lo =3D lower_32_bits(address);
> > > >>> msg->address_hi =3D upper_32_bits(address);
> > > >>>
> > > >>> - msg->data =3D hwirq;
> > > >>> + /*
> > > >>> + * MPIC version 2.0 has erratum PIC1. It causes
> > > >>> + * that neither MSI nor MSI-X can work fine.
> > > >>> + * This is a workaround to allow MSI-X to function
> > > >>> + * properly. It only works for MSI-X, we prevent
> > > >>> + * MSI on buggy chips in fsl_msi_check_device().
> > > >>> + */
> > > >>> + if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
> > > >>> + msg->data =3D __swab32(hwirq);
> > > >>> + else
> > > >>> + msg->data =3D hwirq;
> > > >>>
> > > >>> pr_debug("%s: allocated srs: %d, ibs: %d\n",
> > > >>> __func__, hwirq / IRQS_PER_MSI_REG, hwirq %
> > IRQS_PER_MSI_REG);
> > > >> @@
> > > >>> -361,6 +381,35 @@ static int fsl_msi_setup_hwirq(struct fsl_msi
> > > >>> *msi,
> > > >> struct platform_device *dev,
> > > >>> return 0;
> > > >>> }
> > > >>>
> > > >>> +/* MPIC version 2.0 has erratum PIC1 */ static int
> > > >>> +mpic_has_errata(struct platform_device *dev) {
> > > >>> + struct device_node *mpic_node;
> > > >>> +
> > > >>> + mpic_node =3D of_irq_find_parent(dev->dev.of_node);
> > > >>> + if (mpic_node) {
> > > >>> + u32 *reg_base, brr1 =3D 0;
> > > >>> + /* Get the PIC reg base */
> > > >>> + reg_base =3D of_iomap(mpic_node, 0);
> > > >>> + of_node_put(mpic_node);
> > > >>> + if (!reg_base) {
> > > >>> + dev_err(&dev->dev, "ioremap problem
> > failed.\n");
> > > >>> + return -EIO;
> > > >>> + }
> > > >>> +
> > > >>> + /* Get the mpic version from block revision
> > register 1 */
> > > >>> + brr1 =3D in_be32(reg_base + MPIC_FSL_BRR1);
> > > >>> + iounmap(reg_base);
> > > >>> + if ((brr1 & MPIC_FSL_BRR1_VER) =3D=3D 0x0200)
> > > >>> + return 1;
> > > >>> + } else {
> > > >>> + dev_err(&dev->dev, "MSI can't find his parent
> > mpic node.\n");
> > > >>> + return -ENODEV;
> > > >>> + }
> > > >>> +
> > > >>> + return 0;
> > > >>> +}
> > > >>> +
> > > >>> static const struct of_device_id fsl_of_msi_ids[]; static int
> > > >>> fsl_of_msi_probe(struct platform_device *dev) { @@ -423,6
> > +472,16 @@
> > > >>> static int fsl_of_msi_probe(struct platform_device *dev)
> > > >>>
> > > >>> msi->feature =3D features->fsl_pic_ip;
> > > >>>
> > > >>> + if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) =3D=3D
> > FSL_PIC_IP_MPIC) {
> > > >>> + rc =3D mpic_has_errata(dev);
> > > >>> + if (rc > 0) {
> > > >>> + msi->feature |=3D MSI_HW_ERRATA_ENDIAN;
> > > >>> + } else if (rc < 0) {
> > > >>> + err =3D rc;
> > > >>> + goto error_out;
> > > >>> + }
> > > >>> + }
> > > >>> +
> > > >>> /*
> > > >>> * Remember the phandle, so that we can match with any
> > PCI nodes
> > > >>> * that have an "fsl,msi" property.
> > > >>> diff --git a/arch/powerpc/sysdev/fsl_msi.h
> > > >>> b/arch/powerpc/sysdev/fsl_msi.h index 8225f86..7389e8e 100644
> > > >>> --- a/arch/powerpc/sysdev/fsl_msi.h
> > > >>> +++ b/arch/powerpc/sysdev/fsl_msi.h
> > > >>> @@ -25,6 +25,8 @@
> > > >>> #define FSL_PIC_IP_IPIC 0x00000002
> > > >>> #define FSL_PIC_IP_VMPIC 0x00000003
> > > >>>
> > > >>> +#define MSI_HW_ERRATA_ENDIAN 0x00000010
> > > >>> +
> > > >>
> > > >> Is there any reason to put this in fsl_msi.h rather than just in
> > > >> fsl_msi.c itself?
> > > >>
> > > >> - k
> > > >
> > > > Actually no. This micro is only used by fsl_msi.c.
> > > > Will move it to fsl_msi.c.
> > > >
> > > > Thanks.
> > > > -Hongtao.
> > >
> > > Also, wondering if we can do the mpic version detection in mpic.c
> > and not
> > > here. I'm not sure what means we'd have to get back to the mpic
> > struct
> > > so we could possible use mpic->flags.
> > >
> >
> > Use the MPIC version result in mpic.c was my plan.
> > But as you point out there seems no obvious way to get the mpic
> > struct.
> > mpic struct is defined as an automatic variable in platform files.
> > Also MSI driver is not so close to mpic driver under current
> > architecture.
> >
> > If you get some elegant way to do this please feel free to tell me.
>=20
> Declare a non-static function to retrieve the MPIC version.
>=20
> -Scott
The struct pointer "mpic" is for internal use only while the "mpic_primary"
could be used for external.
So I'd like to declare two functions something like:
mpic_get_version(struct *mpic);
mpic_primary_get_version(void);
The first function is for mpic.c internal use by mpic_alloc() and mpic_init=
().
The second function is for external use by fsl_msi.c.
There will be two patches:
1. Declare the two MPIC get-version APIs.
2. Fix the MSI errata.
Any comments for this plan?
Thanks.
-Hongtao.
^ permalink raw reply
* Re: [PATCH] KVM: PPC: e500: Add separate functions for vcpu's MMU configuration
From: Alexander Graf @ 2013-03-21 10:07 UTC (permalink / raw)
To: Mihai Caraman; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <1363713407-27886-1-git-send-email-mihai.caraman@freescale.com>
On 19.03.2013, at 18:16, Mihai Caraman wrote:
> Move vcpu's MMU default configuration and geometry update into their =
own
> functions.
Mind to explain why?
Alex
>=20
> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
> ---
> arch/powerpc/kvm/e500_mmu.c | 59 =
+++++++++++++++++++++++++++----------------
> 1 files changed, 37 insertions(+), 22 deletions(-)
>=20
> diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
> index 5c44759..66b6e31 100644
> --- a/arch/powerpc/kvm/e500_mmu.c
> +++ b/arch/powerpc/kvm/e500_mmu.c
> @@ -596,6 +596,20 @@ int kvmppc_set_sregs_e500_tlb(struct kvm_vcpu =
*vcpu, struct kvm_sregs *sregs)
> return 0;
> }
>=20
> +static int vcpu_mmu_geometry_update(struct kvm_vcpu *vcpu,
> + struct kvm_book3e_206_tlb_params *params)
> +{
> + vcpu->arch.tlbcfg[0] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> + if (params->tlb_sizes[0] <=3D 2048)
> + vcpu->arch.tlbcfg[0] |=3D params->tlb_sizes[0];
> + vcpu->arch.tlbcfg[0] |=3D params->tlb_ways[0] << =
TLBnCFG_ASSOC_SHIFT;
> +
> + vcpu->arch.tlbcfg[1] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> + vcpu->arch.tlbcfg[1] |=3D params->tlb_sizes[1];
> + vcpu->arch.tlbcfg[1] |=3D params->tlb_ways[1] << =
TLBnCFG_ASSOC_SHIFT;
> + return 0; =09
> +}
> +
> int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu *vcpu,
> struct kvm_config_tlb *cfg)
> {
> @@ -692,16 +706,8 @@ int kvm_vcpu_ioctl_config_tlb(struct kvm_vcpu =
*vcpu,
> vcpu_e500->gtlb_offset[0] =3D 0;
> vcpu_e500->gtlb_offset[1] =3D params.tlb_sizes[0];
>=20
> - vcpu->arch.mmucfg =3D mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
> -
> - vcpu->arch.tlbcfg[0] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> - if (params.tlb_sizes[0] <=3D 2048)
> - vcpu->arch.tlbcfg[0] |=3D params.tlb_sizes[0];
> - vcpu->arch.tlbcfg[0] |=3D params.tlb_ways[0] << =
TLBnCFG_ASSOC_SHIFT;
> -
> - vcpu->arch.tlbcfg[1] &=3D ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> - vcpu->arch.tlbcfg[1] |=3D params.tlb_sizes[1];
> - vcpu->arch.tlbcfg[1] |=3D params.tlb_ways[1] << =
TLBnCFG_ASSOC_SHIFT;
> + /* Update vcpu's MMU geometry based on SW_TLB input */
> + vcpu_mmu_geometry_update(vcpu, ¶ms);
>=20
> vcpu_e500->shared_tlb_pages =3D pages;
> vcpu_e500->num_shared_tlb_pages =3D num_pages;
> @@ -737,6 +743,26 @@ int kvm_vcpu_ioctl_dirty_tlb(struct kvm_vcpu =
*vcpu,
> return 0;
> }
>=20
> +/* vcpu's MMU default configuration */
> +static int vcpu_mmu_init(struct kvm_vcpu *vcpu,
> + struct kvmppc_e500_tlb_params *params)
> +{
> + /* Initialize RASIZE, PIDSIZE, NTLBS and MAVN fields with host =
values*/
> + vcpu->arch.mmucfg =3D mfspr(SPRN_MMUCFG) & ~MMUCFG_LPIDSIZE;
> +
> + /* Initialize IPROT field with host value*/
> + vcpu->arch.tlbcfg[0] =3D mfspr(SPRN_TLB0CFG) &
> + ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> + vcpu->arch.tlbcfg[0] |=3D params[0].entries;
> + vcpu->arch.tlbcfg[0] |=3D params[0].ways << TLBnCFG_ASSOC_SHIFT;
> +
> + vcpu->arch.tlbcfg[1] =3D mfspr(SPRN_TLB1CFG) &
> + ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> + vcpu->arch.tlbcfg[1] |=3D params[1].entries;
> + vcpu->arch.tlbcfg[1] |=3D params[1].ways << TLBnCFG_ASSOC_SHIFT;
> + return 0;
> +}
> +
> int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 *vcpu_e500)
> {
> struct kvm_vcpu *vcpu =3D &vcpu_e500->vcpu;
> @@ -781,18 +807,7 @@ int kvmppc_e500_tlb_init(struct kvmppc_vcpu_e500 =
*vcpu_e500)
> if (!vcpu_e500->g2h_tlb1_map)
> goto err;
>=20
> - /* Init TLB configuration register */
> - vcpu->arch.tlbcfg[0] =3D mfspr(SPRN_TLB0CFG) &
> - ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> - vcpu->arch.tlbcfg[0] |=3D vcpu_e500->gtlb_params[0].entries;
> - vcpu->arch.tlbcfg[0] |=3D
> - vcpu_e500->gtlb_params[0].ways << TLBnCFG_ASSOC_SHIFT;
> -
> - vcpu->arch.tlbcfg[1] =3D mfspr(SPRN_TLB1CFG) &
> - ~(TLBnCFG_N_ENTRY | TLBnCFG_ASSOC);
> - vcpu->arch.tlbcfg[1] |=3D vcpu_e500->gtlb_params[1].entries;
> - vcpu->arch.tlbcfg[1] |=3D
> - vcpu_e500->gtlb_params[1].ways << TLBnCFG_ASSOC_SHIFT;
> + vcpu_mmu_init(vcpu, vcpu_e500->gtlb_params);
>=20
> kvmppc_recalc_tlb1map_range(vcpu_e500);
> return 0;
> --=20
> 1.7.4.1
>=20
>=20
> --
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