* Re: [PATCH 3/3] powerpc: Set default VGA device
From: Brian King @ 2013-04-05 15:38 UTC (permalink / raw)
To: Michael Ellerman; +Cc: klebers, linux-pci, bhelgaas, linuxppc-dev, lucaskt
In-Reply-To: <20130405065238.GC5082@concordia>
On 04/05/2013 01:52 AM, Michael Ellerman wrote:
> Hi Brian,
>
>
> On Thu, Apr 04, 2013 at 04:58:17PM -0500, Brian King wrote:
>>
>> Add a PCI quirk for VGA devices on Power to set the default VGA device.
>> Ensures a default VGA is always set if a graphics adapter is present,
>> even if firmware did not initialize it. If more than one graphics
>> adapter is present, ensure the one initialized by firmware is set
>> as the default VGA device. This ensures that X autoconfiguration
>> will work.
>
> So a few things:
>
> - You are doing this on all power systems, not just pseries which is I
> assume what you're testing on - that seems OK to me, but just
> checking.
Correct. I've only tested on pseries, but figured it would make sense for
this to be more generic. I'm happy to make this pseries specific if that
is preferred.
> - What is the "initialized by firmware" test? Just that IO & MEM are
> enabled?
Correct. This is what the x86 code does. Alternatively, its possible
there is a chosen attribute in the device tree we could look at.
> - You potentially override an existing default, is that a problem? Can
> the user set the default? (no AFAICS).
I couldn't find anywhere that this could be set by the user and wanted to
be able to handle both the case of a single adapter that wasn't initialized
by firmware as well as the multi adapter case where only one of the adapters was
initialized by firmware. I could have made this smarter so that we only
override the default if the previous default was not initialized by firmware,
but opted for the simpler patch.
> - The x86 code is slightly different, they don't override an existing
> default, why do we?
I wanted to be able to handle the case of a single graphics adapter installed in a system
that has not been initialized by firmware, since I have a system like this. This generally
isn't something that x86 would need to do since all graphics adapters should have x86 boot
code in them, but very few current graphics adapters have fcode in them today.
Thanks,
Brian
--
Brian King
Power Linux I/O
IBM Linux Technology Center
^ permalink raw reply
* Re: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-05 14:22 UTC (permalink / raw)
To: Shaveta Leekha; +Cc: linuxppc-dev@lists.ozlabs.org list
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420
>=20
> There are several things missing from the device trees of B4860 and =
B4420:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information
> * serdes, sfp(security fuse processor), thermal,
> gpio, maple, cpri, quad timers nodes
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> v2:=20
> - incorporated review comments on commits message
> - change unit address of cpu nodes to match the reg property
>=20
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
> 6 files changed, 667 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
Is there a reason you didn't get rid of b4si-pre.dtsi and just merge it =
into b4860si-pre.dtsi & b4420-pre.dtsi?
- k=
^ permalink raw reply
* [PATCH] powerpc/fsl-booke: Fix cpu unit address to match reg on
From: Kumar Gala @ 2013-04-05 14:20 UTC (permalink / raw)
To: linuxppc-dev
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 9b39a43..a93c55a 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -69,57 +69,57 @@
reg = <0 1>;
next-level-cache = <&L2_1>;
};
- cpu1: PowerPC,e6500@1 {
+ cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
next-level-cache = <&L2_1>;
};
- cpu2: PowerPC,e6500@2 {
+ cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
next-level-cache = <&L2_1>;
};
- cpu3: PowerPC,e6500@3 {
+ cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
next-level-cache = <&L2_1>;
};
- cpu4: PowerPC,e6500@4 {
+ cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
next-level-cache = <&L2_2>;
};
- cpu5: PowerPC,e6500@5 {
+ cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
next-level-cache = <&L2_2>;
};
- cpu6: PowerPC,e6500@6 {
+ cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
next-level-cache = <&L2_2>;
};
- cpu7: PowerPC,e6500@7 {
+ cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
next-level-cache = <&L2_2>;
};
- cpu8: PowerPC,e6500@8 {
+ cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
next-level-cache = <&L2_3>;
};
- cpu9: PowerPC,e6500@9 {
+ cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
next-level-cache = <&L2_3>;
};
- cpu10: PowerPC,e6500@10 {
+ cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
next-level-cache = <&L2_3>;
};
- cpu11: PowerPC,e6500@11 {
+ cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
next-level-cache = <&L2_3>;
--
1.7.9.7
^ permalink raw reply related
* RE: [PATCH] bookehv: Handle debug exception on guest exit
From: Bhushan Bharat-R65777 @ 2013-04-05 7:53 UTC (permalink / raw)
To: Alexander Graf, Kumar Gala, Benjamin Herrenschmidt
Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D06FC04D4@039-SN2MPN1-013.039d.mgd.msft.net>
Hi Kumar/Benh,
After further looking into the code I think that if we correct the vector r=
ange below in DebugDebug handler then we do not need the change I provided =
in this patch.
Here is the snapshot for 32 bit (head_booke.h, same will be true for 64 bit=
):
#define DEBUG_DEBUG_EXCEPTION =
\
START_EXCEPTION(DebugDebug); =
\
DEBUG_EXCEPTION_PROLOG; =
\
=
\
/* =
\
* If there is a single step or branch-taken exception in an =
\
* exception entry sequence, it was probably meant to apply to =
\
* the code where the exception occurred (since exception entry =
\
* doesn't turn off DE automatically). We simulate the effect =
\
* of turning off DE on entry to an exception handler by turning =
\
* off DE in the DSRR1 value and clearing the debug status. =
\
*/ =
\
mfspr r10,SPRN_DBSR; /* check single-step/branch taken *=
/ \
andis. r10,r10,(DBSR_IC|DBSR_BT)@h; =
\
beq+ 2f; =
\
=
\
lis r10,KERNELBASE@h; /* check if exception in vectors */=
\
ori r10,r10,KERNELBASE@l; =
\
cmplw r12,r10; =
\
blt+ 2f; /* addr below exception vectors */ =
\
=
\
lis r10,DebugDebug@h; \
ori r10,r10,DebugDebug@l; =
\
^^^^
Here we assume all exception vector ends at DebugDebug, which is not corre=
ct.
We probably should get proper end by using some start_vector and end_vecto=
r lebels
or at least use end at Ehvpriv (which is last defined in head_fsl_booke.S =
for PowerPC. Is that correct?
=09
cmplw r12,r10; =
\
bgt+ 2f; /* addr above exception vectors */ =
\
Thanks
-Bharat
> -----Original Message-----
> From: kvm-ppc-owner@vger.kernel.org [mailto:kvm-ppc-owner@vger.kernel.org=
] On
> Behalf Of Bhushan Bharat-R65777
> Sent: Thursday, April 04, 2013 8:29 PM
> To: Alexander Graf
> Cc: linuxppc-dev@lists.ozlabs.org; kvm@vger.kernel.org; kvm-ppc@vger.kern=
el.org;
> Wood Scott-B07421
> Subject: RE: [PATCH] bookehv: Handle debug exception on guest exit
>=20
>=20
>=20
> > -----Original Message-----
> > From: Alexander Graf [mailto:agraf@suse.de]
> > Sent: Thursday, April 04, 2013 6:55 PM
> > To: Bhushan Bharat-R65777
> > Cc: linuxppc-dev@lists.ozlabs.org; kvm@vger.kernel.org;
> > kvm-ppc@vger.kernel.org; Wood Scott-B07421; Bhushan Bharat-R65777
> > Subject: Re: [PATCH] bookehv: Handle debug exception on guest exit
> >
> >
> > On 20.03.2013, at 18:45, Bharat Bhushan wrote:
> >
> > > EPCR.DUVD controls whether the debug events can come in hypervisor
> > > mode or not. When KVM guest is using the debug resource then we do
> > > not want debug events to be captured in guest entry/exit path. So we
> > > set EPCR.DUVD when entering and clears EPCR.DUVD when exiting from gu=
est.
> > >
> > > Debug instruction complete is a post-completion debug exception but
> > > debug event gets posted on the basis of MSR before the instruction
> > > is executed. Now if the instruction switches the context from guest
> > > mode (MSR.GS =3D 1) to hypervisor mode (MSR.GS =3D 0) then the xSRR0
> > > points to first instruction of KVM handler and xSRR1 points that
> > > MSR.GS is clear (hypervisor context). Now as xSRR1.GS is used to
> > > decide whether KVM handler will be invoked to handle the exception
> > > or host host kernel debug handler will be invoked to handle the excep=
tion.
> > > This leads to host kernel debug handler handling the exception which
> > > should either be handled by KVM.
> > >
> > > This is tested on e500mc in 32 bit mode
> > >
> > > Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> > > ---
> > > v0:
> > > - Do not apply this change for debug_crit as we do not know those
> > > chips have
> > issue or not.
> > > - corrected 64bit case branching
> > >
> > > arch/powerpc/kernel/exceptions-64e.S | 29 +++++++++++++++++++++++++=
+++-
> > > arch/powerpc/kernel/head_booke.h | 26 +++++++++++++++++++++++++=
+
> > > 2 files changed, 54 insertions(+), 1 deletions(-)
> > >
> > > diff --git a/arch/powerpc/kernel/exceptions-64e.S
> > > b/arch/powerpc/kernel/exceptions-64e.S
> > > index 4684e33..8b26294 100644
> > > --- a/arch/powerpc/kernel/exceptions-64e.S
> > > +++ b/arch/powerpc/kernel/exceptions-64e.S
> > > @@ -516,6 +516,33 @@ kernel_dbg_exc:
> > > andis. r15,r14,DBSR_IC@h
> > > beq+ 1f
> > >
> > > +#ifdef CONFIG_KVM_BOOKE_HV
> > > + /*
> > > + * EPCR.DUVD controls whether the debug events can come in
> > > + * hypervisor mode or not. When KVM guest is using the debug
> > > + * resource then we do not want debug events to be captured
> > > + * in guest entry/exit path. So we set EPCR.DUVD when entering
> > > + * and clears EPCR.DUVD when exiting from guest.
> > > + * Debug instruction complete is a post-completion debug
> > > + * exception but debug event gets posted on the basis of MSR
> > > + * before the instruction is executed. Now if the instruction
> > > + * switches the context from guest mode (MSR.GS =3D 1) to hyperviso=
r
> > > + * mode (MSR.GS =3D 0) then the xSRR0 points to first instruction o=
f
> >
> > Can't we just execute that code path with MSR.DE=3D0?
>=20
> Single stepping uses DBCR0.IC (instruction complete).
> Can you describe how MSR.DE =3D 0 will work?
>=20
> >
> >
> > Alex
> >
> > > + * KVM handler and xSRR1 points that MSR.GS is clear
> > > + * (hypervisor context). Now as xSRR1.GS is used to decide whether
> > > + * KVM handler will be invoked to handle the exception or host
> > > + * host kernel debug handler will be invoked to handle the exceptio=
n.
> > > + * This leads to host kernel debug handler handling the exception
> > > + * which should either be handled by KVM.
> > > + */
> > > + mfspr r10, SPRN_EPCR
> > > + andis. r10,r10,SPRN_EPCR_DUVD@h
> > > + beq+ 2f
> > > +
> > > + andis. r10,r9,MSR_GS@h
> > > + beq+ 3f
> > > +2:
> > > +#endif
> > > LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
> > > LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
> > > cmpld cr0,r10,r14
> > > @@ -523,7 +550,7 @@ kernel_dbg_exc:
> > > blt+ cr0,1f
> > > bge+ cr1,1f
> > >
> > > - /* here it looks like we got an inappropriate debug exception. */
> > > +3: /* here it looks like we got an inappropriate debug exception. */
> > > lis r14,DBSR_IC@h /* clear the IC event */
> > > rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
> > > mtspr SPRN_DBSR,r14
> > > diff --git a/arch/powerpc/kernel/head_booke.h
> > > b/arch/powerpc/kernel/head_booke.h
> > > index 5f051ee..edc6a3b 100644
> > > --- a/arch/powerpc/kernel/head_booke.h
> > > +++ b/arch/powerpc/kernel/head_booke.h
> > > @@ -285,7 +285,33 @@ label:
> > > mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
> > > andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
> > > beq+ 2f; \
> > > +#ifdef CONFIG_KVM_BOOKE_HV \
> > > + /* \
> > > + * EPCR.DUVD controls whether the debug events can come in \
> > > + * hypervisor mode or not. When KVM guest is using the debug =
\
> > > + * resource then we do not want debug events to be captured =
\
> > > + * in guest entry/exit path. So we set EPCR.DUVD when entering =
\
> > > + * and clears EPCR.DUVD when exiting from guest. \
> > > + * Debug instruction complete is a post-completion debug \
> > > + * exception but debug event gets posted on the basis of MSR =
\
> > > + * before the instruction is executed. Now if the instruction =
\
> > > + * switches the context from guest mode (MSR.GS =3D 1) to hyperviso=
r \
> > > + * mode (MSR.GS =3D 0) then the xSRR0 points to first instruction o=
f \
> > > + * KVM handler and xSRR1 points that MSR.GS is clear \
> > > + * (hypervisor context). Now as xSRR1.GS is used to decide whether =
\
> > > + * KVM handler will be invoked to handle the exception or host =
\
> > > + * host kernel debug handler will be invoked to handle the exceptio=
n. \
> > > + * This leads to host kernel debug handler handling the exception =
\
> > > + * which should either be handled by KVM. \
> > > + */ \
> > > + mfspr r10, SPRN_EPCR; \
> > > + andis. r10,r10,SPRN_EPCR_DUVD@h; \
> > > + beq+ 3f; \
> > > \
> > > + andis. r10,r9,MSR_GS@h; \
> > > + beq+ 1f; \
> > > +3: \
> > > +#endif \
> > > lis r10,KERNELBASE@h; /* check if exception in vectors */ \
> > > ori r10,r10,KERNELBASE@l; \
> > > cmplw r12,r10; \
> > > --
> > > 1.7.0.4
> > >
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe kvm-ppc"
> > > in the body of a message to majordomo@vger.kernel.org More majordomo
> > > info at http://vger.kernel.org/majordomo-info.html
> >
>=20
>=20
> --
> To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the=
body
> of a message to majordomo@vger.kernel.org More majordomo info at
> http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] powerpc: Add HWCAP2 aux entry
From: Michael Ellerman @ 2013-04-05 7:06 UTC (permalink / raw)
To: Nishanth Aravamudan
Cc: michaele, vda.linux, Steve Munroe, linux-kernel, paulus, viro,
Ryan Arnold, linuxppc-dev, akpm
In-Reply-To: <20130402212204.GA30438@linux.vnet.ibm.com>
Hi guys,
Added some folks to CC, blame scripts/get_maintainer.pl.
Comment below ..
On Tue, Apr 02, 2013 at 02:22:05PM -0700, Nishanth Aravamudan wrote:
> From: Michael Neuling <michael.neuling@au1.ibm.com>
>
> We are currently out of free bits in AT_HWCAP. With POWER8, we have
> several hardware features that we need to advertise. Tested on POWER and
> x86.
>
> Signed-off-by: Michael Neuling <michael.neuling@au1.ibm.com>
> Signed-off-by: Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
>
> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
> index fb3245e..ccadad6 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -52,6 +52,7 @@ struct cpu_spec {
> char *cpu_name;
> unsigned long cpu_features; /* Kernel features */
> unsigned int cpu_user_features; /* Userland features */
> + unsigned int cpu_user_features2; /* Userland features v2 */
> unsigned int mmu_features; /* MMU features */
>
> /* cache line sizes */
> diff --git a/arch/powerpc/include/asm/elf.h b/arch/powerpc/include/asm/elf.h
> index ac9790f..cc0655a 100644
> --- a/arch/powerpc/include/asm/elf.h
> +++ b/arch/powerpc/include/asm/elf.h
> @@ -61,6 +61,7 @@ typedef elf_vrregset_t elf_fpxregset_t;
> instruction set this cpu supports. This could be done in userspace,
> but it's not easy, and we've already done it here. */
> # define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
> +# define ELF_HWCAP2 (cur_cpu_spec->cpu_user_features2)
>
> /* This yields a string that ld.so will use to load implementation
> specific libraries for optimization. This is more specific in
> diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
> index 3939829..51adc23 100644
> --- a/fs/binfmt_elf.c
> +++ b/fs/binfmt_elf.c
> @@ -140,6 +140,13 @@ static int padzero(unsigned long elf_bss)
> #define ELF_BASE_PLATFORM NULL
> #endif
>
> +/*
> + * Most archs don't need this
> + */
> +#ifndef ELF_HWCAP2
> +#define ELF_HWCAP2 (0)
> +#endif
> +
> static int
> create_elf_tables(struct linux_binprm *bprm, struct elfhdr *exec,
> unsigned long load_addr, unsigned long interp_load_addr)
> @@ -240,6 +247,7 @@ create_elf_tables(struct linux_binprm *bprm, struct elfhdr *exec,
> NEW_AUX_ENT(AT_EGID, from_kgid_munged(cred->user_ns, cred->egid));
> NEW_AUX_ENT(AT_SECURE, security_bprm_secureexec(bprm));
> NEW_AUX_ENT(AT_RANDOM, (elf_addr_t)(unsigned long)u_rand_bytes);
> + NEW_AUX_ENT(AT_HWCAP2, ELF_HWCAP2);
Wouldn't it be safer to not emit AT_HWCAP2 unless it is defined by the arch?
That way the change would only impact powerpc.
cheers
> diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c
> index 9c13e02..0b553d3 100644
> --- a/fs/binfmt_elf_fdpic.c
> +++ b/fs/binfmt_elf_fdpic.c
> @@ -469,6 +469,13 @@ error_kill:
> #endif
>
> /*
> + * Most archs don't need this
> + */
> +#ifndef ELF_HWCAP2
> +#define ELF_HWCAP2 (0)
> +#endif
> +
> +/*
> * present useful information to the program by shovelling it onto the new
> * process's stack
> */
> @@ -483,7 +490,6 @@ static int create_elf_fdpic_tables(struct linux_binprm *bprm,
> size_t platform_len = 0, len;
> char *k_platform, *k_base_platform;
> char __user *u_platform, *u_base_platform, *p;
> - long hwcap;
> int loop;
> int nr; /* reset for each csp adjustment */
>
> @@ -502,8 +508,6 @@ static int create_elf_fdpic_tables(struct linux_binprm *bprm,
> return -EFAULT;
> #endif
>
> - hwcap = ELF_HWCAP;
> -
> /*
> * If this architecture has a platform capability string, copy it
> * to userspace. In some cases (Sparc), this info is impossible
> @@ -617,7 +621,8 @@ static int create_elf_fdpic_tables(struct linux_binprm *bprm,
>
> nr = 0;
> csp -= DLINFO_ITEMS * 2 * sizeof(unsigned long);
> - NEW_AUX_ENT(AT_HWCAP, hwcap);
> + NEW_AUX_ENT(AT_HWCAP, ELF_HWCAP);
> + NEW_AUX_ENT(AT_HWCAP2, ELF_HWCAP2);
> NEW_AUX_ENT(AT_PAGESZ, PAGE_SIZE);
> NEW_AUX_ENT(AT_CLKTCK, CLOCKS_PER_SEC);
> NEW_AUX_ENT(AT_PHDR, exec_params->ph_addr);
> diff --git a/include/uapi/linux/auxvec.h b/include/uapi/linux/auxvec.h
> index 61594d5..835c065 100644
> --- a/include/uapi/linux/auxvec.h
> +++ b/include/uapi/linux/auxvec.h
> @@ -28,6 +28,7 @@
> #define AT_BASE_PLATFORM 24 /* string identifying real platform, may
> * differ from AT_PLATFORM. */
> #define AT_RANDOM 25 /* address of 16 random bytes */
> +#define AT_HWCAP2 26 /* extension of AT_HWCAP */
>
> #define AT_EXECFN 31 /* filename of program */
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 1/3] pci: Export pci_dev_type
From: Michael Ellerman @ 2013-04-05 6:55 UTC (permalink / raw)
To: Brian King; +Cc: klebers, linux-pci, bhelgaas, linuxppc-dev, lucaskt
In-Reply-To: <201304042158.r34LwDHx010466@d03av02.boulder.ibm.com>
Hi Bjorn,
Should we take this series via the powerpc tree, assuming you're OK with
this patch?
cheers
On Thu, Apr 04, 2013 at 04:58:13PM -0500, Brian King wrote:
>
> Export pci_dev_type so that arch specific PCI probing code can
> initialize a new PCI device struct.
>
> Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
> ---
>
> drivers/pci/pci.h | 1 -
> include/linux/pci.h | 1 +
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff -puN drivers/pci/pci.h~pci_export_pci_dev_type drivers/pci/pci.h
> --- linux/drivers/pci/pci.h~pci_export_pci_dev_type 2013-04-02 17:01:25.000000000 -0500
> +++ linux-bjking1/drivers/pci/pci.h 2013-04-02 17:02:31.000000000 -0500
> @@ -153,7 +153,6 @@ static inline int pci_no_d1d2(struct pci
> }
> extern struct device_attribute pci_dev_attrs[];
> extern struct device_attribute pcibus_dev_attrs[];
> -extern struct device_type pci_dev_type;
> extern struct bus_attribute pci_bus_attrs[];
>
>
> diff -puN include/linux/pci.h~pci_export_pci_dev_type include/linux/pci.h
> --- linux/include/linux/pci.h~pci_export_pci_dev_type 2013-04-02 17:01:59.000000000 -0500
> +++ linux-bjking1/include/linux/pci.h 2013-04-02 17:02:29.000000000 -0500
> @@ -670,6 +670,7 @@ enum pcie_bus_config_types {
> extern enum pcie_bus_config_types pcie_bus_config;
>
> extern struct bus_type pci_bus_type;
> +extern struct device_type pci_dev_type;
>
> /* Do NOT directly access these two variables, unless you are arch specific pci
> * code, or pci core code. */
> _
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 3/3] powerpc: Set default VGA device
From: Michael Ellerman @ 2013-04-05 6:52 UTC (permalink / raw)
To: Brian King; +Cc: klebers, linux-pci, bhelgaas, linuxppc-dev, lucaskt
In-Reply-To: <201304042158.r34LwGPg010714@d03av02.boulder.ibm.com>
Hi Brian,
On Thu, Apr 04, 2013 at 04:58:17PM -0500, Brian King wrote:
>
> Add a PCI quirk for VGA devices on Power to set the default VGA device.
> Ensures a default VGA is always set if a graphics adapter is present,
> even if firmware did not initialize it. If more than one graphics
> adapter is present, ensure the one initialized by firmware is set
> as the default VGA device. This ensures that X autoconfiguration
> will work.
So a few things:
- You are doing this on all power systems, not just pseries which is I
assume what you're testing on - that seems OK to me, but just
checking.
- What is the "initialized by firmware" test? Just that IO & MEM are
enabled?
- You potentially override an existing default, is that a problem? Can
the user set the default? (no AFAICS).
- The x86 code is slightly different, they don't override an existing
default, why do we?
cheers
^ permalink raw reply
* Re: [PATCH 17/18] cpufreq: powerpc: move cpufreq driver to drivers/cpufreq
From: Viresh Kumar @ 2013-04-05 6:46 UTC (permalink / raw)
To: rjw, deepthi
Cc: robin.randhawa, linux-pm, Viresh Kumar, patches, Liviu.Dudau,
linux-kernel, cpufreq, Steve.Bannister, Paul Mackerras,
Olof Johansson, arvind.chauhan, linuxppc-dev, linaro-kernel,
charles.garcia-tobin
In-Reply-To: <027e8f1d4ac8de6351115f15a408431558510abb.1365079581.git.viresh.kumar@linaro.org>
On 4 April 2013 18:24, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> This patch moves cpufreq driver of powerpc platform to drivers/cpufreq.
>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: linuxppc-dev@lists.ozlabs.org
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> Compile Tested only.
>
> arch/powerpc/platforms/Kconfig | 31 ----------------------
> arch/powerpc/platforms/pasemi/Makefile | 1 -
> arch/powerpc/platforms/powermac/Makefile | 2 --
> drivers/cpufreq/Kconfig.powerpc | 26 ++++++++++++++++++
> drivers/cpufreq/Makefile | 3 +++
> .../cpufreq.c => drivers/cpufreq/pasemi-cpufreq.c | 0
> .../cpufreq/pmac32-cpufreq.c | 0
> .../cpufreq/pmac64-cpufreq.c | 0
> 8 files changed, 29 insertions(+), 34 deletions(-)
> rename arch/powerpc/platforms/pasemi/cpufreq.c => drivers/cpufreq/pasemi-cpufreq.c (100%)
> rename arch/powerpc/platforms/powermac/cpufreq_32.c => drivers/cpufreq/pmac32-cpufreq.c (100%)
> rename arch/powerpc/platforms/powermac/cpufreq_64.c => drivers/cpufreq/pmac64-cpufreq.c (100%)
Hi Deepthi,
Can you help testing this please?
^ permalink raw reply
* [PATCH 3/4][v2] powerpc/fsl-booke: Add B4_QDS board support
From: Shaveta Leekha @ 2013-04-05 6:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Shaveta Leekha
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
- Add support for B4 board in board file b4_qds.c,
It is common for B4860, B4420 and B4220QDS as they share same QDS board
- Add B4QDS support in Kconfig and Makefile
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor,
with following major features:
- Four dual-threaded e6500 Power Architecture processors
organized in one cluster-each core runs up to 1.8 GHz
- Two DDR3/3L controllers for high-speed memory interface each
runs at up to 1866.67 MHz
- CoreNet fabric that fully supports coherency using MESI protocol
between the e6500 cores, SC3900 FVP cores, memories and
external interfaces.
- Data Path Acceleration Architecture having FMAN, QMan, BMan,
SEC 5.3 and RMAN
- Large internal cache memory with snooping and stashing capabilities
- Sixteen 10-GHz SerDes lanes that serve:
- Two SRIO interfaces. Each supports up to 4 lanes and
a total of up to 8 lanes
- Up to 8-lanes Common Public Radio Interface (CPRI) controller
for glue-less antenna connection
- Two 10-Gbit Ethernet controllers (10GEC)
- Six 1G/2.5-Gbit Ethernet controllers for network communications
- PCI Express controller
- Debug (Aurora)
- Various system peripherals
B4420 and B4220 have some differences in comparison to B4860 with fewer
core/clusters(both SC3900 and e6500), fewer DDR controllers,
fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies.
Key differences between B4860 and B4420:
B4420 has:
- Fewer e6500 cores:
1 cluster with 2 e6500 cores
- Fewer SC3900 cores/clusters:
1 cluster with 2 SC3900 cores per cluster
- Single DDRC @ 1.6GHz
- 2 X 4 lane serdes
- 3 SGMII interfaces
- no sRIO
- no 10G
Key differences between B4860 and B4220:
B4220 has:
- Fewer e6500 cores:
1 cluster with 1 e6500 core
- Fewer SC3900 cores/clusters:
1 cluster with 2 SC3900 cores per cluster
- Single DDRC @ 1.33GHz
- 2 X 2 lane serdes
- 2 SGMII interfaces
- no sRIO
- no 10G
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
v2: lines of commit message wrapped at 75 chars max
arch/powerpc/platforms/85xx/Kconfig | 17 ++++++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/b4_qds.c | 102 ++++++++++++++++++++++++++++++++++
3 files changed, 120 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 31dc066..8f02b05 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -321,6 +321,23 @@ config T4240_QDS
help
This option enables support for the T4240 QDS board
+config B4_QDS
+ bool "Freescale B4 QDS"
+ select DEFAULT_UIMAGE
+ select E500
+ select PPC_E500MC
+ select PHYS_64BIT
+ select SWIOTLB
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ select HAS_RAPIDIO
+ select PPC_EPAPR_HV_PIC
+ help
+ This option enables support for the B4 QDS board
+ The B4 application development system B4 QDS is a complete
+ debugging environment intended for engineers developing
+ applications for the B4.
+
endif
endif # FSL_SOC_BOOKE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 712e233..2eab37e 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
+obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
new file mode 100644
index 0000000..0c6702f
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/b4_qds.c
@@ -0,0 +1,102 @@
+/*
+ * B4 QDS Setup
+ * Should apply for QDS platform of B4860 and it's personalities.
+ * viz B4860/B4420/B4220QDS
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/phy.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <linux/of_platform.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+
+#include "corenet_ds.h"
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init b4_qds_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+ extern struct smp_ops_t smp_85xx_ops;
+#endif
+
+ if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
+ (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
+ (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
+ return 1;
+
+ /* Check if we're running under the Freescale hypervisor */
+ if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
+ (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
+ (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
+ ppc_md.init_IRQ = ehv_pic_init;
+ ppc_md.get_irq = ehv_pic_get_irq;
+ ppc_md.restart = fsl_hv_restart;
+ ppc_md.power_off = fsl_hv_halt;
+ ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+ /*
+ * Disable the timebase sync operations because we can't write
+ * to the timebase registers under the hypervisor.
+ */
+ smp_85xx_ops.give_timebase = NULL;
+ smp_85xx_ops.take_timebase = NULL;
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+define_machine(b4_qds) {
+ .name = "B4 QDS",
+ .probe = b4_qds_probe,
+ .setup_arch = corenet_ds_setup_arch,
+ .init_IRQ = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+ .get_irq = mpic_get_irq,
+#else
+ .get_irq = mpic_get_coreint_irq,
+#endif
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PPC64
+ .power_save = book3e_idle,
+#else
+ .power_save = e500_idle,
+#endif
+};
+
+machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
+
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
+#endif
--
1.7.6.GIT
^ permalink raw reply related
* [PATCH 4/4][v2] powerpc/85xx: Update corenet64_smp_defconfig for B4_QDS
From: Shaveta Leekha @ 2013-04-05 6:33 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Shaveta Leekha
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
---
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 1c6eb66..6c8b020 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -21,6 +21,7 @@ CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
+CONFIG_B4_QDS=y
CONFIG_P5020_DS=y
CONFIG_P5040_DS=y
CONFIG_T4240_QDS=y
--
1.7.6.GIT
^ permalink raw reply related
* [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Shaveta Leekha @ 2013-04-05 6:33 UTC (permalink / raw)
To: linuxppc-dev
Cc: Zhao Chenhui, Minghuan Lian, Shaveta Leekha, Vakul Garg,
Tang Yuantian, Andy Fleming, Ramneek Mehresh, Varun Sethi
B4860 and B4420 are similar that share some commonalities
* common features have been added in b4si-pre.dtsi and b4si-post.dtsi
* differences are added in respective silicon files of B4860 and B4420
There are several things missing from the device trees of B4860 and B4420:
* DPAA related nodes (Qman, Bman, Fman, Rman)
* DSP related nodes/information
* serdes, sfp(security fuse processor), thermal,
gpio, maple, cpri, quad timers nodes
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Vakul Garg <vakul@freescale.com>
---
v2:
- incorporated review comments on commits message
- change unit address of cpu nodes to match the reg property
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 +++++++++++++++++++++++++++
arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
6 files changed, 667 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 0000000..bba0c03
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,94 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+ compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&dcsr {
+ dcsr-epu@0 {
+ compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
+ };
+ dcsr-npc {
+ compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
+ };
+ dcsr-snpc@30000 {
+ compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+ };
+ dcsr-snpc@31000 {
+ compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
+ };
+ dcsr-cpu-sb-proxy@108000 {
+ compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x108000 0x1000 0x109000 0x1000>;
+ };
+};
+
+&soc {
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,b4420-l3-cache-controller", "cache";
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,b4420-corenet-cf";
+ };
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2";
+ };
+
+ L2: l2-cache-controller@c20000 {
+ compatible = "fsl,b4420-l2-cache-controller";
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 0000000..8bd1495
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,49 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/include/ "b4si-pre.dtsi"
+
+/ {
+ compatible = "fsl,B4420";
+
+ cpus {
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 0000000..f43910f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,138 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "b4si-post.dtsi"
+
+/* controller at 0x200000 */
+&pci0 {
+ compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
+};
+
+&rio {
+ compatible = "fsl,srio";
+ interrupts = <16 2 1 11>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ fsl,iommu-parent = <&pamu0>;
+ ranges;
+
+ port1 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <1>;
+ fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
+ };
+
+ port2 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cell-index = <2>;
+ fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
+ };
+};
+
+&dcsr {
+ dcsr-epu@0 {
+ compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
+ };
+ dcsr-npc {
+ compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
+ };
+ dcsr-ddr@13000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr2>;
+ reg = <0x13000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
+ };
+ dcsr-snpc@30000 {
+ compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+ };
+ dcsr-snpc@31000 {
+ compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
+ };
+ dcsr-cpu-sb-proxy@108000 {
+ compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu1>;
+ reg = <0x108000 0x1000 0x109000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@110000 {
+ compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu2>;
+ reg = <0x110000 0x1000 0x111000 0x1000>;
+ };
+ dcsr-cpu-sb-proxy@118000 {
+ compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu3>;
+ reg = <0x118000 0x1000 0x119000 0x1000>;
+ };
+};
+
+&soc {
+ ddr2: memory-controller@9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 9>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,b4860-l3-cache-controller", "cache";
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,b4860-corenet-cf";
+ };
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2";
+ };
+
+ L2: l2-cache-controller@c20000 {
+ compatible = "fsl,b4860-l2-cache-controller";
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 0000000..9261cab
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,59 @@
+/*
+ * B4860 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "b4si-pre.dtsi"
+
+/ {
+ compatible = "fsl,B4860";
+
+ cpus {
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ next-level-cache = <&L2>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ next-level-cache = <&L2>;
+ };
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
new file mode 100644
index 0000000..06c97a2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -0,0 +1,262 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc", "simple-bus";
+ interrupts = <25 2 0 0>;
+};
+
+/* controller at 0x200000 */
+&pci0 {
+ compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
+ device_type = "pci";
+ #size-cells = <2>;
+ #address-cells = <3>;
+ bus-range = <0x0 0xff>;
+ interrupts = <20 2 0 0>;
+ fsl,iommu-parent = <&pamu0>;
+ pcie@0 {
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ interrupts = <20 2 0 0>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 40 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ };
+};
+
+&dcsr {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,dcsr", "simple-bus";
+
+ dcsr-epu@0 {
+ compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
+ interrupts = <52 2 0 0
+ 84 2 0 0
+ 85 2 0 0
+ 94 2 0 0
+ 95 2 0 0>;
+ reg = <0x0 0x1000>;
+ };
+ dcsr-npc {
+ compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
+ reg = <0x1000 0x1000 0x1002000 0x10000>;
+ };
+ dcsr-nxc@2000 {
+ compatible = "fsl,dcsr-nxc";
+ reg = <0x2000 0x1000>;
+ };
+ dcsr-corenet {
+ compatible = "fsl,dcsr-corenet";
+ reg = <0x8000 0x1000 0x1A000 0x1000>;
+ };
+ dcsr-dpaa@9000 {
+ compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
+ reg = <0x9000 0x1000>;
+ };
+ dcsr-ocn@11000 {
+ compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
+ reg = <0x11000 0x1000>;
+ };
+ dcsr-ddr@12000 {
+ compatible = "fsl,dcsr-ddr";
+ dev-handle = <&ddr1>;
+ reg = <0x12000 0x1000>;
+ };
+ dcsr-nal@18000 {
+ compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
+ reg = <0x18000 0x1000>;
+ };
+ dcsr-rcpm@22000 {
+ compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
+ reg = <0x22000 0x1000>;
+ };
+ dcsr-snpc@30000 {
+ compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x30000 0x1000 0x1022000 0x10000>;
+ };
+ dcsr-snpc@31000 {
+ compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
+ reg = <0x31000 0x1000 0x1042000 0x10000>;
+ };
+ dcsr-cpu-sb-proxy@100000 {
+ compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
+ cpu-handle = <&cpu0>;
+ reg = <0x100000 0x1000 0x101000 0x1000>;
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 2>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 8>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,b4-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000>;
+ interrupts = <16 2 1 4>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,b4-corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 0>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 1>;
+
+
+ /* PCIe, DMA, SRIO */
+ pamu0: pamu@0 {
+ reg = <0 0x1000>;
+ fsl,primary-cache-geometry = <8 1>;
+ fsl,secondary-cache-geometry = <32 2>;
+ };
+
+ /* AXI2, Maple */
+ pamu1: pamu@1000 {
+ reg = <0x1000 0x1000>;
+ fsl,primary-cache-geometry = <32 1>;
+ fsl,secondary-cache-geometry = <32 2>;
+ };
+
+ /* Q/BMan */
+ pamu2: pamu@2000 {
+ reg = <0x2000 0x1000>;
+ fsl,primary-cache-geometry = <32 1>;
+ fsl,secondary-cache-geometry = <32 2>;
+ };
+
+ /* AXI1, FMAN */
+ pamu3: pamu@3000 {
+ reg = <0x3000 0x1000>;
+ fsl,primary-cache-geometry = <32 1>;
+ fsl,secondary-cache-geometry = <32 2>;
+ };
+ };
+
+/include/ "qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,b4-device-config";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ fsl,liodn-bits = <12>;
+ };
+
+ rcpm: global-utilities@e2000 {
+ compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2";
+ reg = <0xe2000 0x1000>;
+ };
+
+/include/ "qoriq-dma-0.dtsi"
+ dma@100300 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
+ };
+
+/include/ "qoriq-dma-1.dtsi"
+ dma@101300 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
+ };
+
+/include/ "qonverge-usb2-dr-0.dtsi"
+ usb0: usb@210000 {
+ compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
+ fsl,iommu-parent = <&pamu1>;
+ fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
+ };
+
+/include/ "qoriq-espi-0.dtsi"
+ spi@110000 {
+ fsl,espi-num-chipselects = <4>;
+ };
+
+/include/ "qoriq-esdhc-0.dtsi"
+ sdhc@114000 {
+ sdhci,auto-cmd12;
+ fsl,iommu-parent = <&pamu1>;
+ fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
+ };
+
+/include/ "qoriq-i2c-0.dtsi"
+/include/ "qoriq-i2c-1.dtsi"
+/include/ "qoriq-duart-0.dtsi"
+/include/ "qoriq-duart-1.dtsi"
+/include/ "qoriq-sec5.3-0.dtsi"
+
+ L2: l2-cache-controller@c20000 {
+ compatible = "fsl,b4-l2-cache-controller";
+ reg = <0xc20000 0x1000>;
+ next-level-cache = <&cpc>;
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
new file mode 100644
index 0000000..b6161c8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
@@ -0,0 +1,65 @@
+/*
+ * B4420 Silicon/SoC Device Tree Source (pre include)
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/ {
+ compatible = "fsl,B4";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+ dcsr = &dcsr;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ pci0 = &pci0;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ sdhc = &sdhc;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ next-level-cache = <&L2>;
+ };
+ };
+};
--
1.7.6.GIT
^ permalink raw reply related
* [PATCH 2/4][v2] powerpc/fsl-booke: Add initial B4860QDS and B4420QDS board device tree
From: Shaveta Leekha @ 2013-04-05 6:33 UTC (permalink / raw)
To: linuxppc-dev
Cc: Poonam Aggrwal, Shaveta Leekha, Minghuan Lian, Andy Fleming,
Ramneek Mehresh
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
B4860QDS and B4420QDS share same QDS board
* common board features have been added in b4qds.dts
* various board differences are in respective files of B4860 and B4420
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/b4420qds.dts | 50 +++++++++++
arch/powerpc/boot/dts/b4860qds.dts | 61 +++++++++++++
arch/powerpc/boot/dts/b4qds.dts | 171 ++++++++++++++++++++++++++++++++++++
3 files changed, 282 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
create mode 100644 arch/powerpc/boot/dts/b4860qds.dts
create mode 100644 arch/powerpc/boot/dts/b4qds.dts
diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
new file mode 100644
index 0000000..923156d
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -0,0 +1,50 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4420si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+ model = "fsl,B4420QDS";
+ compatible = "fsl,B4420QDS";
+
+ ifc: localbus@ffe124000 {
+ board-control@3,0 {
+ compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
+ };
+ };
+
+};
+
+/include/ "fsl/b4420si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 0000000..78907f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,61 @@
+/*
+ * B4860DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/b4860si-pre.dtsi"
+/include/ "b4qds.dts"
+
+/ {
+ model = "fsl,B4860QDS";
+ compatible = "fsl,B4860QDS";
+
+ ifc: localbus@ffe124000 {
+ board-control@3,0 {
+ compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
+ };
+ };
+
+ rio: rapidio@ffe0c0000 {
+ reg = <0xf 0xfe0c0000 0 0x11000>;
+
+ port1 {
+ ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+ };
+ port2 {
+ ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+ };
+ };
+
+};
+
+/include/ "fsl/b4860si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4qds.dts b/arch/powerpc/boot/dts/b4qds.dts
new file mode 100644
index 0000000..f99aa3e
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4qds.dts
@@ -0,0 +1,171 @@
+/*
+ * B4420DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/include/ "fsl/b4si-pre.dtsi"
+
+/ {
+ model = "fsl,B4QDS";
+ compatible = "fsl,B4QDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xff800000 0x00010000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND U-Boot Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND DTB Image";
+ };
+
+ partition@200000 {
+ /* 10MB for Linux Kernel Image */
+ reg = <0x00200000 0x00A00000>;
+ label = "NAND Linux Kernel Image";
+ };
+
+ partition@c00000 {
+ /* 500MB for Root file System Image */
+ reg = <0x00c00000 0x1F400000>;
+ label = "NAND RFS Image";
+ };
+ };
+
+ board-control@3,0 {
+ compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
+ reg = <3 0 0x300>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01052000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ spi@110000 {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf040";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ };
+ };
+
+ sdhc@114000 {
+ /*Disabled as there is no sdhc connector on B4420QDS board*/
+ status = "disabled";
+ };
+
+ i2c@118000 {
+ eeprom@50 {
+ compatible = "at24,24c64";
+ reg = <0x50>;
+ };
+ eeprom@51 {
+ compatible = "at24,24c256";
+ reg = <0x51>;
+ };
+ eeprom@53 {
+ compatible = "at24,24c256";
+ reg = <0x53>;
+ };
+ eeprom@57 {
+ compatible = "at24,24c256";
+ reg = <0x57>;
+ };
+ rtc@68 {
+ compatible = "dallas,ds3232";
+ reg = <0x68>;
+ };
+ };
+
+ usb@210000 {
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+
+ };
+
+ pci0: pcie@ffe200000 {
+ reg = <0xf 0xfe200000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+};
+
+/include/ "fsl/b4si-post.dtsi"
--
1.7.6.GIT
^ permalink raw reply related
* Re: [PATCH] [RFC] powerpc: Add VDSO version of time
From: Michael Ellerman @ 2013-04-05 6:21 UTC (permalink / raw)
To: Adhemerval Zanella; +Cc: linuxppc-dev
In-Reply-To: <5148C2B3.6010408@linux.vnet.ibm.com>
On Tue, Mar 19, 2013 at 04:55:31PM -0300, Adhemerval Zanella wrote:
> Hi all,
>
> This patch implement the time syscall as vDSO. I have a glibc patch
> to use it as IFUNC (as latest gettimeofday patch). Below the perf
> numbers:
>
> Baseline PPC32: 380 nsec
> Baseline PPC64: 352 nsec
> vdso PPC32: 20 nsec
> vdso PPC64: 20 nsec
>
> I focused on 64 bit kernel, do I need to provide a scheme for 32 bits
> as well?
You did provide a 32-bit implementation. I take it you haven't tested
that though? Can you test it?
What happens if I don't have the glibc patch?
cheers
^ permalink raw reply
* RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Leekha Shaveta-B20052 @ 2013-04-05 5:26 UTC (permalink / raw)
To: Kumar Gala
Cc: Li Yang-R58472, Zhao Chenhui-B35336, Mehresh Ramneek-B31383,
Garg Vakul-B16394, Lian Minghuan-B31939, Tang Yuantian-B29983,
Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <E3681803-00AE-4FBD-8BEA-E32C18F71A7E@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, April 05, 2013 12:44 AM
To: Leekha Shaveta-B20052
Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li Yang-R58472; Tan=
g Yuantian-B29983; Sethi Varun-B16395; Lian Minghuan-B31939; Mehresh Ramnee=
k-B31383; Fleming Andy-AFLEMING; Garg Vakul-B16394
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
files for B4860 and B4420
On Apr 4, 2013, at 2:10 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li=20
> Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian=20
> Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg=20
> Vakul-B16394
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860 and B4420
>=20
>=20
> On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
>=20
>> B4860 and B4420 are similar that share some commonalities
>>=20
>> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
>> * differences are added in respective silicon files of B4860 and=20
>> B4420
>=20
> What are the differences between B4860 & B4420, beyond # of cores?
> [SL] have detailed the differences in board support patch sent in this pa=
tch set.
> Do I need to mention the differences here also?=20
>=20
>>=20
>> There are several things missing from the device trees of B4860 and B442=
0:
>>=20
>> * DPAA related nodes (Qman, Bman, Fman, Rman)
>> * DSP related nodes/information
>=20
> What about:
>=20
> serdes, sfp [security fuse processor], thermal, gpio, maple, cpri,=20
> quad timers, [SL] I would prefer to add, what have been added in=20
> device tree so far in patch description As that is clear to me.
> But as u suggested, I mentioned some of the nodes/things missing,=20
> though the list is not Exhaustive. Also I am not sure of, what would be a=
dded/required in future in these device tree files.
>=20
> Anyways, I can add all the things you have mentioned above.
> Please tell if anything else is missing.
I would add the trivial ones and just make sure the list is exhaustive for =
the ones missing in the commit message.
[SL] Adding " serdes, sfp [security fuse processor], thermal, gpio, maple, =
cpri, quad timers as missing things"
in my commit message. If I still miss some, Please add while applying the p=
atch.
Thanks,
Shaveta
>=20
> Regards,
> Shaveta
>=20
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Vakul Garg <vakul@freescale.com>
>> ---
>> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
>> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
>> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 +++++++++++++++++++++=
++++++
>> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
>=20
> Remove b4si-pre.dtsi, there isn't enough here to warrant not just=20
> merging it into b4420si-pre.dtsi & b4860si-pre.dtsi
>=20
- k
^ permalink raw reply
* RE: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Leekha Shaveta-B20052 @ 2013-04-05 5:23 UTC (permalink / raw)
To: Kumar Gala
Cc: Wood Scott-B07421, Mehresh Ramneek-B31383, Zhao Chenhui-B35336,
Garg Vakul-B16394, Lian Minghuan-B31939, Tang Yuantian-B29983,
Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <BF757FF6-067E-4A23-9A12-E510B5CE59A7@kernel.crashing.org>
-----Original Message-----
From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
Sent: Friday, April 05, 2013 12:44 AM
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421; Zhao Chenhui-B35336; Mehresh Ramneek-B31383; Garg Va=
kul-B16394; Lian Minghuan-B31939; Tang Yuantian-B29983; Fleming Andy-AFLEMI=
NG; Sethi Varun-B16395; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree=
files for B4860 and B4420
On Apr 4, 2013, at 2:03 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao=20
> Chenhui-B35336; Lian Minghuan-B31939; Garg Vakul-B16394; Tang=20
> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi=20
> Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device=20
> tree files for B4860 and B4420
>=20
> On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>>=20
>>=20
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, April 03, 2013 12:49 AM
>> To: Leekha Shaveta-B20052
>> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
>> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang=20
>> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
>> Varun-B16395
>> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon=20
>> device tree files for B4860 and B4420
>>=20
>> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
>>> +/ {
>>> + compatible =3D "fsl,B4860";
>>> +
>>> + cpus {
>>> + cpu1: PowerPC,e6500@1 {
>>> + device_type =3D "cpu";
>>> + reg =3D <2 3>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>> + cpu2: PowerPC,e6500@2 {
>>> + device_type =3D "cpu";
>>> + reg =3D <4 5>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>> + cpu3: PowerPC,e6500@3 {
>>> + device_type =3D "cpu";
>>> + reg =3D <6 7>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>=20
>> The unit addresses need to match "reg".
>> [SL] You mean "@1" should match to "reg =3D <2 3>" ?
>=20
> Yes, it should be "@2" for that node.
>=20
>> As each e6500 core in B4860 is dual- threaded, reg property here=20
>> represents the thread's identifier in that PA core.
>>=20
>> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
>> Core 1 having <2 3> and
>> so on....
>=20
> The convention used in device trees is that the unit address matches the =
reg.
>=20
> -Scott
> [SL] Ok, I can change that. Will make unit address as @2 for <2 3>, @4 fo=
r <4 5> and so on....
>=20
> Kumar, please respond here, as I have followed the convention used in=20
> T4 device tree files for Dual-threaded cores.
Scott is correct, we probably need to fix the T4 dts.
- k
[SL] ok, will do it for B4
Regards,
Shaveta=20
^ permalink raw reply
* powerpc userspace address space layout information
From: Chris Friesen @ 2013-04-05 4:53 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt, Paul Mackerras,
Segher Boessenkool
Hi,
I'm running with glibc 2.11 on a 2.6.34 kernel. 32-bit userspace on 64-bit kernel.
On a complicated process the memory map looks something like this:
<vdso, executable, heap, etc.>
5b2c000-f5b38000 r-xp 00000000 00:0f 3636 /lib/libnss_files-2.11.1.so
<lots of libraries snipped>
f6026000-f6035000 ---p 00096000 00:0f 3628 /lib/libkrb5.so.3.3
<lots of libraries snipped>
f7902000-f7905000 r-xp 00000000 00:0f 3607 /lib/libdl-2.11.1.so
f7905000-f7914000 ---p 00003000 00:0f 3607 /lib/libdl-2.11.1.so
f7914000-f7915000 r--p 00002000 00:0f 3607 /lib/libdl-2.11.1.so
f7915000-f7916000 rw-p 00003000 00:0f 3607 /lib/libdl-2.11.1.so
f7918000-f7919000 rw-p 00000000 00:00 0
f7919000-f791a000 r--p 0001a000 00:0f 3646 /lib/libpthread-2.11.1.so
f791a000-f791b000 r--p 00001000 00:0f 2306001 /path/to/binary
f791b000-f791c000 r--p 00001000 00:0f 2306001 /path/to/binary
f791c000-f791d000 r--p 00001000 00:0f 2306001 /path/to/binary
f791d000-f7923000 rw-p 00000000 00:00 0
f7923000-f7943000 r-xp 00000000 00:0f 13323 /lib/ld-2.11.1.so
f7943000-f7944000 r--p 00020000 00:0f 13323 /lib/ld-2.11.1.so
f7944000-f7945000 rw-p 00021000 00:0f 13323 /lib/ld-2.11.1.so
f9000000-fac01000 rw-p 00000000 00:00 0
fac06000-fac07000 rw-s 00000000 00:04 327690 /SYSV41050355 (deleted)
fad00000-fae00000 rw-s 00000000 00:04 98307 /SYSVee113d3f (deleted)
fae00000-fb000000 rw-s 00000000 00:04 7503872 /SYSVc5050355 (deleted)
fb000000-fb200000 rw-s 00000000 00:04 7536641 /SYSV5c050355 (deleted)
fb200000-fb600000 rw-s 00000000 00:0d 30647 /var/log/blah
ffa8e000-ffab0000 rwxp 00000000 00:00 0 [stack]
I have a few questions I'm hoping someone can help me with.
First, what determines where /lib/ld-2.11.1.so gets mapped? It seems like
it never goes above 0xf8000000 or so.
Second, what is the mapping at 0xf9000000-0xfac01000? Is this just empty
space or is it reserved for something in particular?
Third, what's the most reliable way to ensure a block of addresses around
0xf6000000 don't get used for shared libraries? (We want to preserve
those addresses for emulating hardware in a virtual machine.) We have
this working on an older system but after upgrading to new software the
libraries now extend further down the address space.
Any help is greatly appreciated.
Chris
--
Chris Friesen
Software Designer
500 Palladium Drive, Suite 2100
Ottawa, Ontario K2N 1C2, Canada
www.genband.com
office:+1.343.883.2717
chris.friesen@genband.com
^ permalink raw reply
* Re: [RFC PATCH v2 2/6] powerpc: Exception hooks for context tracking subsystem
From: Paul Mackerras @ 2013-04-05 2:50 UTC (permalink / raw)
To: Li Zhong; +Cc: fweisbec, paulmck, linuxppc-dev, linux-kernel
In-Reply-To: <1364551221-23177-3-git-send-email-zhong@linux.vnet.ibm.com>
On Fri, Mar 29, 2013 at 06:00:17PM +0800, Li Zhong wrote:
> This is the exception hooks for context tracking subsystem, including
> data access, program check, single step, instruction breakpoint, machine check,
> alignment, fp unavailable, altivec assist, unknown exception, whose handlers
> might use RCU.
>
> This patch corresponds to
> [PATCH] x86: Exception hooks for userspace RCU extended QS
> commit 6ba3c97a38803883c2eee489505796cb0a727122
>
> Signed-off-by: Li Zhong <zhong@linux.vnet.ibm.com>
Is there a reason why you didn't put the exception_exit() call in
ret_from_except_lite in entry_64.S, and the exception_entry() call in
EXCEPTION_PROLOG_COMMON? That would seem to catch all these cases in
a more centralized place.
Also, I notice that with the exception_exit calls where they are, we
can still deliver signals (thus possibly taking a page fault) or call
schedule() for preemption after the exception_exit() call. Is that
OK, or is it a potential problem?
Paul.
^ permalink raw reply
* RE: [PATCH 5/5 v11] iommu/fsl: Freescale PAMU driver and iommu implementation.
From: Sethi Varun-B16395 @ 2013-04-05 0:01 UTC (permalink / raw)
To: Alex Williamson
Cc: Wood Scott-B07421, Joerg Roedel, linux-kernel@vger.kernel.org,
Yoder Stuart-B08248, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1365093819.2882.301.camel@bling.home>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQWxleCBXaWxsaWFtc29u
IFttYWlsdG86YWxleC53aWxsaWFtc29uQHJlZGhhdC5jb21dDQo+IFNlbnQ6IFRodXJzZGF5LCBB
cHJpbCAwNCwgMjAxMyAxMDoxNCBQTQ0KPiBUbzogU2V0aGkgVmFydW4tQjE2Mzk1DQo+IENjOiBK
b2VyZyBSb2VkZWw7IFlvZGVyIFN0dWFydC1CMDgyNDg7IFdvb2QgU2NvdHQtQjA3NDIxOw0KPiBp
b21tdUBsaXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZzsgbGludXhwcGMtZGV2QGxpc3RzLm96bGFi
cy5vcmc7IGxpbnV4LQ0KPiBrZXJuZWxAdmdlci5rZXJuZWwub3JnOyBnYWxha0BrZXJuZWwuY3Jh
c2hpbmcub3JnOw0KPiBiZW5oQGtlcm5lbC5jcmFzaGluZy5vcmcNCj4gU3ViamVjdDogUmU6IFtQ
QVRDSCA1LzUgdjExXSBpb21tdS9mc2w6IEZyZWVzY2FsZSBQQU1VIGRyaXZlciBhbmQgaW9tbXUN
Cj4gaW1wbGVtZW50YXRpb24uDQo+IA0KPiBPbiBUaHUsIDIwMTMtMDQtMDQgYXQgMTY6MzUgKzAw
MDAsIFNldGhpIFZhcnVuLUIxNjM5NSB3cm90ZToNCj4gPg0KPiA+ID4gLS0tLS1PcmlnaW5hbCBN
ZXNzYWdlLS0tLS0NCj4gPiA+IEZyb206IEFsZXggV2lsbGlhbXNvbiBbbWFpbHRvOmFsZXgud2ls
bGlhbXNvbkByZWRoYXQuY29tXQ0KPiA+ID4gU2VudDogVGh1cnNkYXksIEFwcmlsIDA0LCAyMDEz
IDg6NTIgUE0NCj4gPiA+IFRvOiBTZXRoaSBWYXJ1bi1CMTYzOTUNCj4gPiA+IENjOiBKb2VyZyBS
b2VkZWw7IFlvZGVyIFN0dWFydC1CMDgyNDg7IFdvb2QgU2NvdHQtQjA3NDIxOw0KPiA+ID4gaW9t
bXVAbGlzdHMubGludXgtZm91bmRhdGlvbi5vcmc7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMu
b3JnOw0KPiA+ID4gbGludXgtIGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmc7IGdhbGFrQGtlcm5lbC5j
cmFzaGluZy5vcmc7DQo+ID4gPiBiZW5oQGtlcm5lbC5jcmFzaGluZy5vcmcNCj4gPiA+IFN1Ympl
Y3Q6IFJlOiBbUEFUQ0ggNS81IHYxMV0gaW9tbXUvZnNsOiBGcmVlc2NhbGUgUEFNVSBkcml2ZXIg
YW5kDQo+ID4gPiBpb21tdSBpbXBsZW1lbnRhdGlvbi4NCj4gPiA+DQo+ID4gPiBPbiBUaHUsIDIw
MTMtMDQtMDQgYXQgMTM6MDAgKzAwMDAsIFNldGhpIFZhcnVuLUIxNjM5NSB3cm90ZToNCj4gPiA+
ID4NCj4gPiA+ID4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4gPiA+IEZyb206
IEFsZXggV2lsbGlhbXNvbiBbbWFpbHRvOmFsZXgud2lsbGlhbXNvbkByZWRoYXQuY29tXQ0KPiA+
ID4gPiA+IFNlbnQ6IFdlZG5lc2RheSwgQXByaWwgMDMsIDIwMTMgMTE6MzIgUE0NCj4gPiA+ID4g
PiBUbzogSm9lcmcgUm9lZGVsDQo+ID4gPiA+ID4gQ2M6IFNldGhpIFZhcnVuLUIxNjM5NTsgWW9k
ZXIgU3R1YXJ0LUIwODI0ODsgV29vZCBTY290dC1CMDc0MjE7DQo+ID4gPiA+ID4gaW9tbXVAbGlz
dHMubGludXgtZm91bmRhdGlvbi5vcmc7IGxpbnV4cHBjLWRldkBsaXN0cy5vemxhYnMub3JnOw0K
PiA+ID4gPiA+IGxpbnV4LSBrZXJuZWxAdmdlci5rZXJuZWwub3JnOyBnYWxha0BrZXJuZWwuY3Jh
c2hpbmcub3JnOw0KPiA+ID4gPiA+IGJlbmhAa2VybmVsLmNyYXNoaW5nLm9yZw0KPiA+ID4gPiA+
IFN1YmplY3Q6IFJlOiBbUEFUQ0ggNS81IHYxMV0gaW9tbXUvZnNsOiBGcmVlc2NhbGUgUEFNVSBk
cml2ZXINCj4gPiA+ID4gPiBhbmQgaW9tbXUgaW1wbGVtZW50YXRpb24uDQo+ID4gPiA+ID4NCj4g
PiA+ID4gPiBPbiBUdWUsIDIwMTMtMDQtMDIgYXQgMTg6MTggKzAyMDAsIEpvZXJnIFJvZWRlbCB3
cm90ZToNCj4gPiA+ID4gPiA+IENjJ2luZyBBbGV4IFdpbGxpYW1zb24NCj4gPiA+ID4gPiA+DQo+
ID4gPiA+ID4gPiBBbGV4LCBjYW4geW91IHBsZWFzZSByZXZpZXcgdGhlIGlvbW11LWdyb3VwIHBh
cnQgb2YgdGhpcyBwYXRjaD8NCj4gPiA+ID4gPg0KPiA+ID4gPiA+IFN1cmUsIGl0IGxvb2tzIHBy
ZXR0eSByZWFzb25hYmxlLiAgQUlVSSwgYWxsIFBDSSBkZXZpY2VzIGFyZQ0KPiA+ID4gPiA+IGJl
bG93IHNvbWUga2luZCBvZiBob3N0IGJyaWRnZSB0aGF0IGlzIGVpdGhlciBuZXcgYW5kIHN1cHBv
cnRzDQo+ID4gPiA+ID4gcGFydGl0aW9uaW5nIG9yIG9sZCBhbmQgZG9lc24ndC4gIEkgZG9uJ3Qg
a25vdyBpZiB0aGF0J3MgYQ0KPiA+ID4gPiA+IHZpc2liaWxpdHkgb3IgaXNvbGF0aW9uIHJlcXVp
cmVtZW50LCBwZXJoYXBzIFBDSSBBQ1MtaXNoLiAgSW4NCj4gPiA+ID4gPiB0aGUgbmV3IGhvc3Qg
YnJpZGdlIGNhc2UsIGVhY2ggZGV2aWNlIGdldHMgYSBncm91cC4gIFRoaXMgc2VlbXMNCj4gPiA+
ID4gPiBub3QgdG8gaGF2ZSBhbnkgcXVpcmtzIGZvciBtdWx0aWZ1bmN0aW9uIGRldmljZXMgdGhv
dWdoLiAgT24gQU1EDQo+ID4gPiA+ID4gYW5kIEludGVsIElPTU1VcyB3ZSB0ZXN0IG11bHRpZnVu
Y3Rpb24gZGV2aWNlIEFDUyBzdXBwb3J0IHRvDQo+ID4gPiA+ID4gZGV0ZXJtaW5lIHdoZXRoZXIg
YWxsIHRoZSBmdW5jdGlvbnMgc2hvdWxkIGJlIGluIHRoZSBzYW1lIGdyb3VwLg0KPiA+ID4gPiA+
IElzIHRoZXJlIGFueSByZWFzb24NCj4gPiA+IHRvIHRydXN0IG11bHRpZnVuY3Rpb24gZGV2aWNl
cyBvbiBQQU1VPw0KPiA+ID4gPiA+DQo+ID4gPiA+IFtTZXRoaSBWYXJ1bi1CMTYzOTVdIEluIHRo
ZSBjYXNlIHdoZXJlIHdlIGNhbiBwYXJ0aXRpb24gZW5kcG9pbnRzDQo+ID4gPiA+IHdlIGNhbiBk
aXN0aW5ndWlzaCB0cmFuc2FjdGlvbnMgYmFzZWQgb24gdGhlIGJ1cyxkZXZpY2UsZnVuY3Rpb24N
Cj4gPiA+ID4gbnVtYmVyIGNvbWJpbmF0aW9uLiBUaGlzIHN1cHBvcnQgaXMgYXZhaWxhYmxlIGlu
IHRoZSBQQ0llDQo+ID4gPiA+IGNvbnRyb2xsZXIgKGhvc3QgYnJpZGdlKS4NCj4gPiA+DQo+ID4g
PiBTbyBjYW4geDg2IElPTU1VcywgdGhhdCdzIHRoZSB2aXNpYmlsaXR5IGFzcGVjdCBvZiBJT01N
VSBncm91cHMuDQo+ID4gPiBWaXNpYmlsaXR5IGFsb25lIGRvZXNuJ3QgbmVjZXNzYXJpbHkgaW1w
bHkgdGhhdCBhIGRldmljZSBpcyBpc29sYXRlZA0KPiA+ID4gdGhvdWdoLiAgQSBtdWx0aWZ1bmN0
aW9uIFBDSSBkZXZpY2UgdGhhdCBkb2Vzbid0IGV4cG9zZSBBQ1Mgc3VwcG9ydA0KPiA+ID4gbWF5
IG5vdCBpc29sYXRlIGZ1bmN0aW9ucyBmcm9tIGVhY2ggb3RoZXIuICBGb3IgZXhhbXBsZSBhDQo+
ID4gPiBwZWVyLXRvLXBlZXIgRE1BIGJldHdlZW4gZnVuY3Rpb25zIG1heSBub3QgYmUgdHJhbnNs
YXRlZCBieSB0aGUNCj4gPiA+IHVwc3RyZWFtIElPTU1VLiAgSU9NTVUgZ3JvdXBzIHNob3VsZCBl
bmNvbXBhc3MgYm90aCB2aXNpYmlsaXR5IGFuZA0KPiBpc29sYXRpb24uDQo+ID4gW1NldGhpIFZh
cnVuLUIxNjM5NV0gV2UgY2FuIGlzb2xhdGUgdGhlIERNQSBhY2Nlc3MgdG8gdGhlIGhvc3QgYmFz
ZWQNCj4gPiBvbiB0aGUgdG8gdGhlIHBjaSBidXMsZGV2aWNlLGZ1bmN0aW9uIG51bWJlci4NCj4g
DQo+IFRoZSBJT01NVSBjYW4gb25seSBpc29sYXRlIERNQSB0aGF0IGl0IGNhbiBzZWUuICBBIG11
bHRpZnVuY3Rpb24gZGV2aWNlDQo+IG1heSBuZXZlciBleHBvc2UgcGVlci10by1wZWVyIERNQSB0
byB0aGUgdXBzdHJlYW0gZGV2aWNlLCBpdCdzDQo+IGltcGxlbWVudGF0aW9uIHNwZWNpZmljLiAg
VGhlIEFDUyBmbGFncyBhbGxvdyB0aGF0IHBvc3NpYmlsaXR5IHRvIGJlDQo+IGNvbnRyb2xsZWQg
YW5kIHByZXZlbnRlZC4NCj4gDQo+ID4gSSB0aG91Z2h0IHRoYXQgd2FzIGVub3VnaCB0byBwdXQg
ZGV2aWNlcyBpbiB0byBzZXBhcmF0ZSBpb21tdSBncm91cHMuDQo+ID4gVGhpcyBpcyBhIFBDSWUg
Y29udHJvbGxlciBwcm9wZXJ0eSB3aGljaCBhbGxvd3MgdXMgdG8gcGFydGl0aW9uIFBDSWUNCj4g
PiBkZXZpY2VzLiBCdXQsIHdoYXQgSSBjYW4gdW5kZXJzdGFuZCBmcm9tIHlvdXIgcG9pbnQgaXMg
dGhhdCB3ZSBhbHNvDQo+ID4gbmVlZCB0byBjb25zaWRlciBpc29sYXRpb24gYXQgUENJZSBkZXZp
Y2UgbGV2ZWwgYXMgd2VsbC4gSSB3aWxsIGNoZWNrDQo+ID4gZm9yIHRoZSBjYXNlIG9mIG11bHRp
ZnVuY3Rpb24gZGV2aWNlcy4NCj4gPg0KPiA+ID4NCj4gPiA+ID4gPiBJIGFsc28gZmluZCBpdCBj
dXJpb3VzIHdoYXQgaGFwcGVucyB0byB0aGUgaW9tbXUgZ3JvdXAgb2YgdGhlDQo+ID4gPiA+ID4g
aG9zdCBicmlkZ2UuICBJbiB0aGUgcGFydGl0aW9uYWJsZSBjYXNlIHRoZSBob3N0IGJyaWRnZSBn
cm91cCBpcw0KPiA+ID4gPiA+IHJlbW92ZWQsIGluIHRoZSBub24tcGFydGl0aW9uYWJsZSBjYXNl
IHRoZSBob3N0IGJyaWRnZSBncm91cA0KPiA+ID4gPiA+IGJlY29tZXMgdGhlIGdyb3VwIGZvciB0
aGUgY2hpbGRyZW4sIHJlbW92aW5nIHRoZSBob3N0IGJyaWRnZS4NCj4gPiA+ID4gPiBJdCdzIHVu
aXF1ZSB0byBQQU1VIHNvIGZhciB0aGF0IHRoZXNlIGhvc3QgYnJpZGdlcyBhcmUgZXZlbiBpbg0K
PiA+ID4gPiA+IGFuIGlvbW11IGdyb3VwICh4ODYgb25seSBhZGRzIHBjaSBkZXZpY2VzKSwgYnV0
IEkgZG9uJ3Qgc2VlIGl0DQo+ID4gPiA+ID4gYXMgbmVjZXNzYXJpbHkgd3JvbmcgbGVhdmluZyBp
dCBpbiBlaXRoZXIgc2NlbmFyaW8uICBEb2VzIGl0DQo+ID4gPiA+ID4gc29sdmUgc29tZSBwcm9i
bGVtIHRvIHJlbW92ZQ0KPiA+ID4gdGhlbSBmcm9tIHRoZSBncm91cHM/DQo+ID4gPiA+ID4gVGhh
bmtzLA0KPiA+ID4gPiBbU2V0aGkgVmFydW4tQjE2Mzk1XSBUaGUgUENJZSBjb250cm9sbGVyIGlz
bid0IGEgcGFydGl0aW9uYWJsZQ0KPiA+ID4gPiBlbnRpdHksIGl0IHdvdWxkIGFsd2F5cyBiZSBv
d25lZCBieSB0aGUgaG9zdC4NCj4gPiA+DQo+ID4gPiBPd25lcnNoaXAgb2YgYSBkZXZpY2Ugc2hv
dWxkbid0IHBsYXkgaW50byB0aGUgZ3JvdXAgY29udGV4dC4gIEFuDQo+ID4gPiBJT01NVSBncm91
cCBzaG91bGQgYmUgZGVmaW5lZCBieSBpdCdzIHZpc2liaWxpdHkgYW5kIGlzb2xhdGlvbiBmcm9t
DQo+ID4gPiBvdGhlciBkZXZpY2VzLiAgV2hldGhlciB0aGUgUENJZSBjb250cm9sbGVyIGlzIGFs
bG93ZWQgdG8gYmUgaGFuZGVkDQo+ID4gPiB0byB1c2Vyc3BhY2UgaXMgYSBxdWVzdGlvbiBmb3Ig
VkZJTy4NCj4gPiBbU2V0aGkgVmFydW4tQjE2Mzk1XSBUaGUgcHJvYmxlbSBpcyBpbiB0aGUgY2Fz
ZSwgd2hlcmUgd2UgY2FuJ3QNCj4gPiBwYXJ0aXRpb24gUENJZSBkZXZpY2VzLiBQQ0llIGRldmlj
ZXMgc2hhcmUgdGhlIHNhbWUgZGV2aWNlIGdyb3VwIGFzDQo+ID4gdGhlIFBDSSBjb250cm9sbGVy
LiBUaGlzIGJlY29tZXMgYSBwcm9ibGVtIHdoaWxlIGFzc2lnbmluZyB0aGUgZGV2aWNlcw0KPiA+
IHRvIHRoZSBndWVzdCwgYXMgeW91IGFyZSByZXF1aXJlZCB0byB1bmJpbmQgYWxsIHRoZSBQQ0ll
IGRldmljZXMNCj4gPiBpbmNsdWRpbmcgdGhlIGNvbnRyb2xsZXIgZnJvbSB0aGUgaG9zdC4gUENJ
ZSBjb250cm9sbGVyIGNhbid0IGJlDQo+ID4gdW5ib3VuZCBmcm9tIHRoZSBob3N0LCBzbyB3ZSBz
aW1wbHkgZGVsZXRlIHRoZSBjb250cm9sbGVyIGlvbW11X2dyb3VwLg0KPiANCj4gVW5iaW5kaW5n
IGRldmljZXMgaXMgYSBWRklPIGltcGxlbWVudGF0aW9uLCBpdCBzaG91bGRuJ3QgbGVhayBpbnRv
IElPTU1VDQo+IGdyb3Vwcy4gIEFsc28gbm90ZSB0aGF0IFZGSU8gaGFzIGEgZHJpdmVyIHdoaXRl
IGxpc3Qgd2hlcmUgd2UgY2FuIGhhdmUNCj4gZXhjZXB0aW9ucyB0byB0aGUgcnVsZS4gIEkgcmVj
ZW50bHkgYWRkZWQgcGNpZWhwIHRvIHRoYXQgbGlzdCBiZWNhdXNlIHRoZQ0KPiBob3N0IGRyaXZl
ciBwcm92aWRlcyBmdW5jdGlvbmFsaXR5LiAgQmVpbmcgYXR0YWNoZWQgdG8gdGhlIGhvc3QgZHJp
dmVyDQo+IG1lYW5zIHRoZSBkZXZpY2UgaXMgbm90IGFjY2Vzc2libGUgdG8gdGhlIHVzZXIgdGhy
b3VnaCBWRklPLCBidXQgb3RoZXINCj4gZGV2aWNlcyBpbiB0aGUgZ3JvdXAgYXJlLiAgVGhhbmtz
LA0KPiANCkFsc28sIGFzIFN0dWFydCBwb2ludGVkIG91dCB0aGUgUENJZSBjb250cm9sbGVyIGFy
ZW4ndCB0aGUgYWN0dWFsIERNQSBkZXZpY2VzIChlbmRwb2ludHMgYXJlIHRoZSBhY3R1YWwgRE1B
IGRldmljZXMpLiBTbywgd2UgcmVtb3ZlIHRoZSBkZXZpY2UgZ3JvdXAgYWxsb2NhdGVkIGZvciB0
aGUgUENJZSBjb250cm9sbGVycy4NCg0KLVZhcnVuDQoNCg==
^ permalink raw reply
* Re: weird elf header issues, is it binutils or my linker script?
From: Chris Friesen @ 2013-04-04 22:24 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Paul Mackerras, linuxppc-dev
In-Reply-To: <BFFF4F77-FA45-40B6-8836-EFF3A23A9480@kernel.crashing.org>
On 04/02/2013 09:07 AM, Segher Boessenkool wrote:
>> What I don't understand is where the "/lib/ld.so.1" string is coming
>> from and how the length gets set to the invalid value.
>
> It comes from the .interp input sections, i.e. the .interp sections in
> the .o files you linked together. Perhaps you have more than one of
> those?
It turns out that the problem was in the linker script. The linker
script was originally written for an older binutils. With the newly
compiled object files there were some sections that were not explicitly
specified in the linker script so they were added automatically to the
interpreter section, bumping up the length.
A new linker script with explicit mention of those sections made the
interpreter section look as expected.
Chris
^ permalink raw reply
* [PATCH 3/3] powerpc: Set default VGA device
From: Brian King @ 2013-04-04 21:58 UTC (permalink / raw)
To: linux-pci; +Cc: klebers, brking, lucaskt, bhelgaas, linuxppc-dev
Add a PCI quirk for VGA devices on Power to set the default VGA device.
Ensures a default VGA is always set if a graphics adapter is present,
even if firmware did not initialize it. If more than one graphics
adapter is present, ensure the one initialized by firmware is set
as the default VGA device. This ensures that X autoconfiguration
will work.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
---
arch/powerpc/kernel/pci-common.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff -puN arch/powerpc/kernel/pci-common.c~powerpc_vga_default_device arch/powerpc/kernel/pci-common.c
--- linux/arch/powerpc/kernel/pci-common.c~powerpc_vga_default_device 2013-04-03 09:50:33.000000000 -0500
+++ linux-bjking1/arch/powerpc/kernel/pci-common.c 2013-04-03 09:50:33.000000000 -0500
@@ -30,6 +30,7 @@
#include <linux/irq.h>
#include <linux/vmalloc.h>
#include <linux/slab.h>
+#include <linux/vgaarb.h>
#include <asm/processor.h>
#include <asm/io.h>
@@ -1725,3 +1726,15 @@ static void fixup_hide_host_resource_fsl
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
+
+static void fixup_vga(struct pci_dev *pdev)
+{
+ u16 cmd;
+
+ pci_read_config_word(pdev, PCI_COMMAND, &cmd);
+ if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
+ vga_set_default_device(pdev);
+
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
+ PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);
_
^ permalink raw reply
* [PATCH 2/3] powerpc: Enable boot_vga sysfs attribute for graphics adapters on Power
From: Brian King @ 2013-04-04 21:58 UTC (permalink / raw)
To: linux-pci; +Cc: klebers, brking, lucaskt, bhelgaas, linuxppc-dev
Initialize dev->dev.type such that the PCI group attributes for boot_vga
and SR-IOV can be displayed if appropriate. This fixes an issue seen on
Power preventing X from auto initializing a graphics adapter when using KMS.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
---
arch/powerpc/kernel/pci_of_scan.c | 1 +
1 file changed, 1 insertion(+)
diff -puN arch/powerpc/kernel/pci_of_scan.c~powerpc_set_pci_dev_type arch/powerpc/kernel/pci_of_scan.c
--- linux/arch/powerpc/kernel/pci_of_scan.c~powerpc_set_pci_dev_type 2013-04-03 09:43:19.000000000 -0500
+++ linux-bjking1/arch/powerpc/kernel/pci_of_scan.c 2013-04-03 09:43:19.000000000 -0500
@@ -141,6 +141,7 @@ struct pci_dev *of_create_pci_dev(struct
dev->dev.of_node = of_node_get(node);
dev->dev.parent = bus->bridge;
dev->dev.bus = &pci_bus_type;
+ dev->dev.type = &pci_dev_type;
dev->devfn = devfn;
dev->multifunction = 0; /* maybe a lie? */
dev->needs_freset = 0; /* pcie fundamental reset required */
_
^ permalink raw reply
* [PATCH 1/3] pci: Export pci_dev_type
From: Brian King @ 2013-04-04 21:58 UTC (permalink / raw)
To: linux-pci; +Cc: klebers, brking, lucaskt, bhelgaas, linuxppc-dev
Export pci_dev_type so that arch specific PCI probing code can
initialize a new PCI device struct.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
---
drivers/pci/pci.h | 1 -
include/linux/pci.h | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff -puN drivers/pci/pci.h~pci_export_pci_dev_type drivers/pci/pci.h
--- linux/drivers/pci/pci.h~pci_export_pci_dev_type 2013-04-02 17:01:25.000000000 -0500
+++ linux-bjking1/drivers/pci/pci.h 2013-04-02 17:02:31.000000000 -0500
@@ -153,7 +153,6 @@ static inline int pci_no_d1d2(struct pci
}
extern struct device_attribute pci_dev_attrs[];
extern struct device_attribute pcibus_dev_attrs[];
-extern struct device_type pci_dev_type;
extern struct bus_attribute pci_bus_attrs[];
diff -puN include/linux/pci.h~pci_export_pci_dev_type include/linux/pci.h
--- linux/include/linux/pci.h~pci_export_pci_dev_type 2013-04-02 17:01:59.000000000 -0500
+++ linux-bjking1/include/linux/pci.h 2013-04-02 17:02:29.000000000 -0500
@@ -670,6 +670,7 @@ enum pcie_bus_config_types {
extern enum pcie_bus_config_types pcie_bus_config;
extern struct bus_type pci_bus_type;
+extern struct device_type pci_dev_type;
/* Do NOT directly access these two variables, unless you are arch specific pci
* code, or pci core code. */
_
^ permalink raw reply
* Re: [PATCH] [RFC] powerpc: Add VDSO version of time
From: Adhemerval Zanella @ 2013-04-04 19:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1363755620.18880.27.camel@pasglop>
Hi Benjamin,
Any objection or request about this patch?
On 20-03-2013 02:00, Benjamin Herrenschmidt wrote:
> On Tue, 2013-03-19 at 16:55 -0300, Adhemerval Zanella wrote:
>> I focused on 64 bit kernel, do I need to provide a scheme for 32 bits
>> as well?
> You did provide both 32 and 64-bit VDSO implementations so 32-bit
> kernels should be covered.
>
> Cheers,
> Ben.
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-04 19:13 UTC (permalink / raw)
To: Leekha Shaveta-B20052
Cc: Li Yang-R58472, Zhao Chenhui-B35336, Mehresh Ramneek-B31383,
Garg Vakul-B16394, Lian Minghuan-B31939, Tang Yuantian-B29983,
Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <E12D2F89F87F4A49B0320A4C2DE7E749151B18@039-SN2MPN1-011.039d.mgd.msft.net>
On Apr 4, 2013, at 2:10 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:galak@kernel.crashing.org]=20
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Li =
Yang-R58472; Tang Yuantian-B29983; Sethi Varun-B16395; Lian =
Minghuan-B31939; Mehresh Ramneek-B31383; Fleming Andy-AFLEMING; Garg =
Vakul-B16394
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device =
tree files for B4860 and B4420
>=20
>=20
> On Apr 2, 2013, at 2:16 AM, Shaveta Leekha wrote:
>=20
>> B4860 and B4420 are similar that share some commonalities
>>=20
>> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
>> * differences are added in respective silicon files of B4860 and =
B4420
>=20
> What are the differences between B4860 & B4420, beyond # of cores?
> [SL] have detailed the differences in board support patch sent in this =
patch set.
> Do I need to mention the differences here also?=20
>=20
>>=20
>> There are several things missing from the device trees of B4860 and =
B4420:
>>=20
>> * DPAA related nodes (Qman, Bman, Fman, Rman)
>> * DSP related nodes/information
>=20
> What about:
>=20
> serdes, sfp [security fuse processor], thermal, gpio, maple, cpri, =
quad timers,=20
> [SL] I would prefer to add, what have been added in device tree so far =
in patch description
> As that is clear to me.
> But as u suggested, I mentioned some of the nodes/things missing, =
though the list is not
> Exhaustive. Also I am not sure of, what would be added/required in =
future in these device tree files.
>=20
> Anyways, I can add all the things you have mentioned above.
> Please tell if anything else is missing.
I would add the trivial ones and just make sure the list is exhaustive =
for the ones missing in the commit message.
>=20
> Regards,
> Shaveta
>=20
>>=20
>> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
>> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
>> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>> Signed-off-by: Andy Fleming <afleming@freescale.com>
>> Signed-off-by: Vakul Garg <vakul@freescale.com>
>> ---
>> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
>> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
>> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
>> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 =
+++++++++++++++++++++++++++
>> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
>=20
> Remove b4si-pre.dtsi, there isn't enough here to warrant not just =
merging it into b4420si-pre.dtsi & b4860si-pre.dtsi
>=20
- k
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-04 19:13 UTC (permalink / raw)
To: Leekha Shaveta-B20052
Cc: Wood Scott-B07421, Mehresh Ramneek-B31383, Zhao Chenhui-B35336,
Garg Vakul-B16394, Lian Minghuan-B31939, Tang Yuantian-B29983,
Fleming Andy-AFLEMING, Sethi Varun-B16395,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <E12D2F89F87F4A49B0320A4C2DE7E749151B05@039-SN2MPN1-011.039d.mgd.msft.net>
On Apr 4, 2013, at 2:03 AM, Leekha Shaveta-B20052 wrote:
>=20
>=20
> -----Original Message-----
> From: Wood Scott-B07421=20
> Sent: Wednesday, April 03, 2013 10:10 PM
> To: Leekha Shaveta-B20052
> Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; Zhao =
Chenhui-B35336; Lian Minghuan-B31939; Garg Vakul-B16394; Tang =
Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi =
Varun-B16395
> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon device =
tree files for B4860 and B4420
>=20
> On 04/03/2013 01:42:14 AM, Leekha Shaveta-B20052 wrote:
>>=20
>>=20
>> -----Original Message-----
>> From: Wood Scott-B07421
>> Sent: Wednesday, April 03, 2013 12:49 AM
>> To: Leekha Shaveta-B20052
>> Cc: linuxppc-dev@lists.ozlabs.org; Zhao Chenhui-B35336; Lian=20
>> Minghuan-B31939; Leekha Shaveta-B20052; Garg Vakul-B16394; Tang=20
>> Yuantian-B29983; Fleming Andy-AFLEMING; Mehresh Ramneek-B31383; Sethi
>> Varun-B16395
>> Subject: Re: [PATCH 2/5] powerpc/fsl-booke: Add initial silicon =
device=20
>> tree files for B4860 and B4420
>>=20
>> On 04/02/2013 02:16:05 AM, Shaveta Leekha wrote:
>>> +/ {
>>> + compatible =3D "fsl,B4860";
>>> +
>>> + cpus {
>>> + cpu1: PowerPC,e6500@1 {
>>> + device_type =3D "cpu";
>>> + reg =3D <2 3>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>> + cpu2: PowerPC,e6500@2 {
>>> + device_type =3D "cpu";
>>> + reg =3D <4 5>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>> + cpu3: PowerPC,e6500@3 {
>>> + device_type =3D "cpu";
>>> + reg =3D <6 7>;
>>> + next-level-cache =3D <&L2>;
>>> + };
>>=20
>> The unit addresses need to match "reg".
>> [SL] You mean "@1" should match to "reg =3D <2 3>" ?
>=20
> Yes, it should be "@2" for that node.
>=20
>> As each e6500 core in B4860 is dual- threaded, reg property here=20
>> represents the thread's identifier in that PA core.
>>=20
>> So convention used in T4 and B4 is: core 0 having threads 0 and 1,
>> Core 1 having <2 3> and
>> so on....
>=20
> The convention used in device trees is that the unit address matches =
the reg.
>=20
> -Scott
> [SL] Ok, I can change that. Will make unit address as @2 for <2 3>, @4 =
for <4 5> and so on....
>=20
> Kumar, please respond here, as I have followed the convention used in =
T4 device tree files for
> Dual-threaded cores.
Scott is correct, we probably need to fix the T4 dts.
- k=
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