* Re: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-10 15:17 UTC (permalink / raw)
To: Shaveta Leekha
Cc: Zhao Chenhui, Minghuan Lian, Vakul Garg, Tang Yuantian,
Andy Fleming, Ramneek Mehresh, Varun Sethi, linuxppc-dev
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420
>=20
> There are several things missing from the device trees of B4860 and =
B4420:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information
> * serdes, sfp(security fuse processor), thermal,
> gpio, maple, cpri, quad timers nodes
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> v2:=20
> - incorporated review comments on commits message
> - change unit address of cpu nodes to match the reg property
>=20
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
> 6 files changed, 667 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
* merged b4si-pre.dtsi into b4860-pre.dtsi & b4420-pre.dtsi
* Make some fixes to GUTs related nodes
applied to next
- k
^ permalink raw reply
* Re: [PATCH 2/4][v2] powerpc/fsl-booke: Add initial B4860QDS and B4420QDS board device tree
From: Kumar Gala @ 2013-04-10 15:17 UTC (permalink / raw)
To: Shaveta Leekha
Cc: Minghuan Lian, linuxppc-dev, Andy Fleming, Poonam Aggrwal,
Ramneek Mehresh
In-Reply-To: <1365143632-19362-2-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> B4860QDS and B4420QDS share same QDS board
>=20
> * common board features have been added in b4qds.dts
> * various board differences are in respective files of B4860 and B4420
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
> arch/powerpc/boot/dts/b4420qds.dts | 50 +++++++++++
> arch/powerpc/boot/dts/b4860qds.dts | 61 +++++++++++++
> arch/powerpc/boot/dts/b4qds.dts | 171 =
++++++++++++++++++++++++++++++++++++
> 3 files changed, 282 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
> create mode 100644 arch/powerpc/boot/dts/b4860qds.dts
> create mode 100644 arch/powerpc/boot/dts/b4qds.dts
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 3/4][v2] powerpc/fsl-booke: Add B4_QDS board support
From: Kumar Gala @ 2013-04-10 15:17 UTC (permalink / raw)
To: Shaveta Leekha; +Cc: linuxppc-dev
In-Reply-To: <1365143632-19362-3-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> - Add support for B4 board in board file b4_qds.c,
> It is common for B4860, B4420 and B4220QDS as they share same QDS =
board
> - Add B4QDS support in Kconfig and Makefile
>=20
> B4860QDS is a high-performance computing evaluation, development and
> test platform supporting the B4860 QorIQ Power Architecture processor,
> with following major features:
>=20
> - Four dual-threaded e6500 Power Architecture processors
> organized in one cluster-each core runs up to 1.8 GHz
> - Two DDR3/3L controllers for high-speed memory interface each
> runs at up to 1866.67 MHz
> - CoreNet fabric that fully supports coherency using MESI protocol
> between the e6500 cores, SC3900 FVP cores, memories and
> external interfaces.
> - Data Path Acceleration Architecture having FMAN, QMan, BMan,
> SEC 5.3 and RMAN
> - Large internal cache memory with snooping and stashing =
capabilities
> - Sixteen 10-GHz SerDes lanes that serve:
> - Two SRIO interfaces. Each supports up to 4 lanes and
> a total of up to 8 lanes
> - Up to 8-lanes Common Public Radio Interface (CPRI) controller
> for glue-less antenna connection
> - Two 10-Gbit Ethernet controllers (10GEC)
> - Six 1G/2.5-Gbit Ethernet controllers for network =
communications
> - PCI Express controller
> - Debug (Aurora)
> - Various system peripherals
>=20
> B4420 and B4220 have some differences in comparison to B4860 with =
fewer
> core/clusters(both SC3900 and e6500), fewer DDR controllers,
> fewer serdes lanes, fewer SGMII interfaces and reduced target =
frequencies.
>=20
> Key differences between B4860 and B4420:
> B4420 has:
> - Fewer e6500 cores:
> 1 cluster with 2 e6500 cores
> - Fewer SC3900 cores/clusters:
> 1 cluster with 2 SC3900 cores per cluster
> - Single DDRC @ 1.6GHz
> - 2 X 4 lane serdes
> - 3 SGMII interfaces
> - no sRIO
> - no 10G
>=20
> Key differences between B4860 and B4220:
> B4220 has:
> - Fewer e6500 cores:
> 1 cluster with 1 e6500 core
> - Fewer SC3900 cores/clusters:
> 1 cluster with 2 SC3900 cores per cluster
> - Single DDRC @ 1.33GHz
> - 2 X 2 lane serdes
> - 2 SGMII interfaces
> - no sRIO
> - no 10G
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> v2: lines of commit message wrapped at 75 chars max
>=20
> arch/powerpc/platforms/85xx/Kconfig | 17 ++++++
> arch/powerpc/platforms/85xx/Makefile | 1 +
> arch/powerpc/platforms/85xx/b4_qds.c | 102 =
++++++++++++++++++++++++++++++++++
> 3 files changed, 120 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 4/4][v2] powerpc/85xx: Update corenet64_smp_defconfig for B4_QDS
From: Kumar Gala @ 2013-04-10 15:18 UTC (permalink / raw)
To: Shaveta Leekha; +Cc: linuxppc-dev
In-Reply-To: <1365143632-19362-4-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> ---
> arch/powerpc/configs/corenet64_smp_defconfig | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
applied to next
- k
^ permalink raw reply
* Re: [RFC][PATCH 2/2] powerpc/fsl-pci Make PCIe hotplug work with Freescale
From: Kumar Gala @ 2013-04-10 15:18 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev
In-Reply-To: <1636993.nIfPQTmF8g@pcimr>
On Apr 8, 2013, at 3:15 AM, Rojhalat Ibrahim wrote:
> Up to now the PCIe link status on Freescale PCIe controllers was only
> checked once at boot time. So hotplug did not work. With this patch =
the
> link status is checked on every config read. PCIe devices not present =
at
> boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'.
>=20
> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> ---
> arch/powerpc/include/asm/pci-bridge.h | 6 ++++
> arch/powerpc/sysdev/fsl_pci.c | 51 =
+++++++++++++++++++++++++++++-----
> arch/powerpc/sysdev/indirect_pci.c | 10 ++----
> 3 files changed, 54 insertions(+), 13 deletions(-)
>=20
> diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/pow
applied to next
- k=
^ permalink raw reply
* Re: [PATCH 1/4][v2] powerpc/fsl-booke: Add initial silicon device tree files for B4860 and B4420
From: Kumar Gala @ 2013-04-10 15:17 UTC (permalink / raw)
To: Shaveta Leekha
Cc: Zhao Chenhui, Minghuan Lian, Vakul Garg, Tang Yuantian,
Andy Fleming, Ramneek Mehresh, Varun Sethi, linuxppc-dev
In-Reply-To: <1365143632-19362-1-git-send-email-shaveta@freescale.com>
On Apr 5, 2013, at 1:33 AM, Shaveta Leekha wrote:
> B4860 and B4420 are similar that share some commonalities
>=20
> * common features have been added in b4si-pre.dtsi and b4si-post.dtsi
> * differences are added in respective silicon files of B4860 and B4420
>=20
> There are several things missing from the device trees of B4860 and =
B4420:
>=20
> * DPAA related nodes (Qman, Bman, Fman, Rman)
> * DSP related nodes/information
> * serdes, sfp(security fuse processor), thermal,
> gpio, maple, cpri, quad timers nodes
>=20
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> Signed-off-by: Vakul Garg <vakul@freescale.com>
> ---
> v2:=20
> - incorporated review comments on commits message
> - change unit address of cpu nodes to match the reg property
>=20
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 94 ++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 49 +++++
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 138 ++++++++++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 59 ++++++
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 262 =
+++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4si-pre.dtsi | 65 +++++++
> 6 files changed, 667 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/b4si-pre.dtsi
* merged b4si-pre.dtsi into b4860-pre.dtsi & b4420-pre.dtsi
* Make some fixes to GUTs related nodes
applied to next
- k
^ permalink raw reply
* Re: [PATCH -V5 06/25] powerpc: Reduce PTE table memory wastage
From: Aneesh Kumar K.V @ 2013-04-10 17:47 UTC (permalink / raw)
To: David Gibson; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <87r4iiom8a.fsf@linux.vnet.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> David Gibson <dwg@au1.ibm.com> writes:
>
>> On Wed, Apr 10, 2013 at 11:59:29AM +0530, Aneesh Kumar K.V wrote:
>>> David Gibson <dwg@au1.ibm.com> writes:
>>> > On Thu, Apr 04, 2013 at 11:27:44AM +0530, Aneesh Kumar K.V wrote:
>> [snip]
>>> >> @@ -97,13 +100,45 @@ void __destroy_context(int context_id)
>>> >> }
>>> >> EXPORT_SYMBOL_GPL(__destroy_context);
>>> >>
>>> >> +#ifdef CONFIG_PPC_64K_PAGES
>>> >> +static void destroy_pagetable_page(struct mm_struct *mm)
>>> >> +{
>>> >> + int count;
>>> >> + struct page *page;
>>> >> +
>>> >> + page = mm->context.pgtable_page;
>>> >> + if (!page)
>>> >> + return;
>>> >> +
>>> >> + /* drop all the pending references */
>>> >> + count = atomic_read(&page->_mapcount) + 1;
>>> >> + /* We allow PTE_FRAG_NR(16) fragments from a PTE page */
>>> >> + count = atomic_sub_return(16 - count, &page->_count);
>>> >
>>> > You should really move PTE_FRAG_NR to a header so you can actually use
>>> > it here rather than hard coding 16.
>>> >
>>> > It took me a fair while to convince myself that there is no race here
>>> > with something altering mapcount and count between the atomic_read()
>>> > and the atomic_sub_return(). It could do with a comment to explain
>>> > why that is safe.
>>> >
>>> > Re-using the mapcount field for your index also seems odd, and it took
>>> > me a while to convince myself that that's safe too. Wouldn't it be
>>> > simpler to store a pointer to the next sub-page in the mm_context
>>> > instead? You can get from that to the struct page easily enough with a
>>> > shift and pfn_to_page().
>>>
>>> I found using _mapcount simpler in this case. I was looking at it not
>>> as an index, but rather how may fragments are mapped/used already.
>>
>> Except that it's actually (#fragments - 1). Using subpage pointer
>> makes the fragments calculation (very slightly) harder, but the
>> calculation of the table address easier. More importantly it avoids
>> adding effectively an extra variable - which is then shoehorned into a
>> structure not really designed to hold it.
>
> Even with subpage pointer we would need mm->context.pgtable_page or
> something similar. We don't add any other extra variable right ?. Let me
> try what you are suggesting here and see if that make it simpler.
Here is what I ended up with. I will fold this in next update
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index affbd68..8bd560c 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -233,7 +233,7 @@ typedef struct {
#endif
#ifdef CONFIG_PPC_64K_PAGES
/* for 4K PTE fragment support */
- struct page *pgtable_page;
+ void *pte_frag;
#endif
} mm_context_t;
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index f51ed83..af73f06 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -511,7 +511,7 @@ typedef struct {
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_64K_PAGES
/* for 4K PTE fragment support */
- struct page *pgtable_page;
+ void *pte_frag;
#endif
} mm_context_t;
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 46c6ffa..7b7ac40 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -149,6 +149,16 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
}
#else /* if CONFIG_PPC_64K_PAGES */
+/*
+ * we support 16 fragments per PTE page.
+ */
+#define PTE_FRAG_NR 16
+/*
+ * We use a 2K PTE page fragment and another 2K for storing
+ * real_pte_t hash index
+ */
+#define PTE_FRAG_SIZE_SHIFT 12
+#define PTE_FRAG_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))
extern pte_t *page_table_alloc(struct mm_struct *, unsigned long, int);
extern void page_table_free(struct mm_struct *, unsigned long *, int);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 27432fe..e379d3f 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -584,7 +584,7 @@ void __init setup_arch(char **cmdline_p)
init_mm.end_data = (unsigned long) _edata;
init_mm.brk = klimit;
#ifdef CONFIG_PPC_64K_PAGES
- init_mm.context.pgtable_page = NULL;
+ init_mm.context.pte_frag = NULL;
#endif
irqstack_early_init();
exc_lvl_early_init();
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index 87d96e5..8fe4bc9 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -23,6 +23,7 @@
#include <linux/slab.h>
#include <asm/mmu_context.h>
+#include <asm/pgalloc.h>
#include "icswx.h"
@@ -86,7 +87,7 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
#endif /* CONFIG_PPC_ICSWX */
#ifdef CONFIG_PPC_64K_PAGES
- mm->context.pgtable_page = NULL;
+ mm->context.pte_frag = NULL;
#endif
return 0;
}
@@ -103,16 +104,19 @@ EXPORT_SYMBOL_GPL(__destroy_context);
static void destroy_pagetable_page(struct mm_struct *mm)
{
int count;
+ void *pte_frag;
struct page *page;
- page = mm->context.pgtable_page;
- if (!page)
+ pte_frag = mm->context.pte_frag;
+ if (!pte_frag)
return;
+ page = virt_to_page(pte_frag);
/* drop all the pending references */
- count = atomic_read(&page->_mapcount) + 1;
- /* We allow PTE_FRAG_NR(16) fragments from a PTE page */
- count = atomic_sub_return(16 - count, &page->_count);
+ count = ((unsigned long )pte_frag &
+ (PAGE_SIZE -1)) >> PTE_FRAG_SIZE_SHIFT;
+ /* We allow PTE_FRAG_NR fragments from a PTE page */
+ count = atomic_sub_return(PTE_FRAG_NR - count, &page->_count);
if (!count) {
pgtable_page_dtor(page);
page_mapcount_reset(page);
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 34bc11f..d776614 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -352,66 +352,50 @@ struct page *pmd_page(pmd_t pmd)
}
#ifdef CONFIG_PPC_64K_PAGES
-/*
- * we support 16 fragments per PTE page. This is limited by how many
- * bits we can pack in page->_mapcount. We use the first half for
- * tracking the usage for rcu page table free.
- */
-#define PTE_FRAG_NR 16
-/*
- * We use a 2K PTE page fragment and another 2K for storing
- * real_pte_t hash index
- */
-#define PTE_FRAG_SIZE (2 * PTRS_PER_PTE * sizeof(pte_t))
-
static pte_t *get_from_cache(struct mm_struct *mm)
{
- int index;
- pte_t *ret = NULL;
- struct page *page;
+ void *ret = NULL;
spin_lock(&mm->page_table_lock);
- page = mm->context.pgtable_page;
- if (page) {
- void *p = page_address(page);
- index = atomic_add_return(1, &page->_mapcount);
- ret = (pte_t *) (p + (index * PTE_FRAG_SIZE));
+ ret = mm->context.pte_frag;
+ if (ret) {
+ ret += PTE_FRAG_SIZE;
/*
* If we have taken up all the fragments mark PTE page NULL
*/
- if (index == PTE_FRAG_NR - 1)
- mm->context.pgtable_page = NULL;
+ if (((unsigned long )ret & (PAGE_SIZE - 1)) == 0)
+ ret = NULL;
+ mm->context.pte_frag = ret;
}
spin_unlock(&mm->page_table_lock);
- return ret;
+ return (pte_t *)ret;
}
static pte_t *__alloc_for_cache(struct mm_struct *mm, int kernel)
{
- pte_t *ret = NULL;
+ void *ret = NULL;
struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
__GFP_REPEAT | __GFP_ZERO);
if (!page)
return NULL;
+ ret = page_address(page);
spin_lock(&mm->page_table_lock);
/*
* If we find pgtable_page set, we return
* the allocated page with single fragement
* count.
*/
- if (likely(!mm->context.pgtable_page)) {
+ if (likely(!mm->context.pte_frag)) {
atomic_set(&page->_count, PTE_FRAG_NR);
- atomic_set(&page->_mapcount, 0);
- mm->context.pgtable_page = page;
+ mm->context.pte_frag = ret + PTE_FRAG_SIZE;
}
spin_unlock(&mm->page_table_lock);
- ret = (unsigned long *)page_address(page);
if (!kernel)
pgtable_page_ctor(page);
- return ret;
+ return (pte_t *)ret;
}
pte_t *page_table_alloc(struct mm_struct *mm, unsigned long vmaddr, int kernel)
^ permalink raw reply related
* Re: [PATCH -V5 08/25] powerpc: Decode the pte-lp-encoding bits correctly.
From: Aneesh Kumar K.V @ 2013-04-10 17:49 UTC (permalink / raw)
To: David Gibson; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <87li8qolej.fsf@linux.vnet.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
>>> static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
>>> - int *psize, int *ssize, unsigned long *vpn)
>>> + int *psize, int *apsize, int *ssize, unsigned long *vpn)
>>> {
>>> unsigned long avpn, pteg, vpi;
>>> unsigned long hpte_r = hpte->r;
>>> unsigned long hpte_v = hpte->v;
>>> unsigned long vsid, seg_off;
>>> - int i, size, shift, penc;
>>> + int i, size, a_size, shift, penc;
>>>
>>> - if (!(hpte_v & HPTE_V_LARGE))
>>> - size = MMU_PAGE_4K;
>>> - else {
>>> + if (!(hpte_v & HPTE_V_LARGE)) {
>>> + size = MMU_PAGE_4K;
>>> + a_size = MMU_PAGE_4K;
>>> + } else {
>>> for (i = 0; i < LP_BITS; i++) {
>>> if ((hpte_r & LP_MASK(i+1)) == LP_MASK(i+1))
>>> break;
>>> @@ -388,19 +444,26 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
>>> penc = LP_MASK(i+1) >> LP_SHIFT;
>>> for (size = 0; size < MMU_PAGE_COUNT; size++) {
>>
>>>
>>> - /* 4K pages are not represented by LP */
>>> - if (size == MMU_PAGE_4K)
>>> - continue;
>>> -
>>> /* valid entries have a shift value */
>>> if (!mmu_psize_defs[size].shift)
>>> continue;
>>> + for (a_size = 0; a_size < MMU_PAGE_COUNT; a_size++) {
>>
>> Can't you resize hpte_actual_psize() here instead of recoding the
>> lookup?
>
> I thought about that, but re-coding avoided some repeated check. But
> then, if I follow your review comments of avoiding hpte valid check etc, may
> be I can reuse the hpte_actual_psize. Will try this.
>
How about below ?
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 4427ca8..de235d5 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -271,19 +271,10 @@ static long native_hpte_remove(unsigned long hpte_group)
return i;
}
-static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
+static inline int __hpte_actual_psize(unsigned int lp, int psize)
{
int i, shift;
unsigned int mask;
- /* Look at the 8 bit LP value */
- unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
-
- if (!(hptep->v & HPTE_V_VALID))
- return -1;
-
- /* First check if it is large page */
- if (!(hptep->v & HPTE_V_LARGE))
- return MMU_PAGE_4K;
/* start from 1 ignoring MMU_PAGE_4K */
for (i = 1; i < MMU_PAGE_COUNT; i++) {
@@ -310,6 +301,21 @@ static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
return -1;
}
+static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
+{
+ /* Look at the 8 bit LP value */
+ unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
+
+ if (!(hptep->v & HPTE_V_VALID))
+ return -1;
+
+ /* First check if it is large page */
+ if (!(hptep->v & HPTE_V_LARGE))
+ return MMU_PAGE_4K;
+
+ return __hpte_actual_psize(lp, psize);
+}
+
static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
unsigned long vpn, int psize, int ssize,
int local)
@@ -530,7 +536,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
unsigned long avpn, pteg, vpi;
unsigned long hpte_v = hpte->v;
unsigned long vsid, seg_off;
- int size, a_size, shift, mask;
+ int size, a_size, shift;
/* Look at the 8 bit LP value */
unsigned int lp = (hpte->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
@@ -544,33 +550,11 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
if (!mmu_psize_defs[size].shift)
continue;
- /* start from 1 ignoring MMU_PAGE_4K */
- for (a_size = 1; a_size < MMU_PAGE_COUNT; a_size++) {
-
- /* invalid penc */
- if (mmu_psize_defs[size].penc[a_size] == -1)
- continue;
- /*
- * encoding bits per actual page size
- * PTE LP actual page size
- * rrrr rrrz >=8KB
- * rrrr rrzz >=16KB
- * rrrr rzzz >=32KB
- * rrrr zzzz >=64KB
- * .......
- */
- shift = mmu_psize_defs[a_size].shift - LP_SHIFT;
- if (shift > LP_BITS)
- shift = LP_BITS;
- mask = (1 << shift) - 1;
- if ((lp & mask) ==
- mmu_psize_defs[size].penc[a_size]) {
- goto out;
- }
- }
+ a_size = __hpte_actual_psize(lp, size);
+ if (a_size != -1)
+ break;
}
}
-out:
/* This works for all page sizes, and for 256M and 1T segments */
*ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
shift = mmu_psize_defs[size].shift;
^ permalink raw reply related
* Re: [patch] mm, hotplug: avoid compiling memory hotremove functions when disabled
From: Toshi Kani @ 2013-04-10 17:29 UTC (permalink / raw)
To: David Rientjes
Cc: Wen Congyang, linux-kernel, Tang Chen, linux-mm,
Yasuaki Ishimatsu, Paul Mackerras, Greg Kroah-Hartman,
Andrew Morton, linuxppc-dev
In-Reply-To: <alpine.DEB.2.02.1304092302540.3916@chino.kir.corp.google.com>
On Tue, 2013-04-09 at 23:07 -0700, David Rientjes wrote:
> __remove_pages() is only necessary for CONFIG_MEMORY_HOTREMOVE. PowerPC
> pseries will return -EOPNOTSUPP if unsupported.
>
> Adding an #ifdef causes several other functions it depends on to also
> become unnecessary, which saves in .text when disabled (it's disabled in
> most defconfigs besides powerpc, including x86). remove_memory_block()
> becomes static since it is not referenced outside of
> drivers/base/memory.c.
>
> Build tested on x86 and powerpc with CONFIG_MEMORY_HOTREMOVE both enabled
> and disabled.
>
> Signed-off-by: David Rientjes <rientjes@google.com>
Acked-by: Toshi Kani <toshi.kani@hp.com>
Thanks,
-Toshi
> ---
> arch/powerpc/platforms/pseries/hotplug-memory.c | 12 +++++
> drivers/base/memory.c | 44 +++++++--------
> include/linux/memory.h | 3 +-
> include/linux/memory_hotplug.h | 4 +-
> mm/memory_hotplug.c | 68 +++++++++++------------
> mm/sparse.c | 72 +++++++++++++------------
> 6 files changed, 113 insertions(+), 90 deletions(-)
>
> diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
> --- a/arch/powerpc/platforms/pseries/hotplug-memory.c
> +++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
> @@ -72,6 +72,7 @@ unsigned long memory_block_size_bytes(void)
> return get_memblock_size();
> }
>
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> static int pseries_remove_memblock(unsigned long base, unsigned int memblock_size)
> {
> unsigned long start, start_pfn;
> @@ -153,6 +154,17 @@ static int pseries_remove_memory(struct device_node *np)
> ret = pseries_remove_memblock(base, lmb_size);
> return ret;
> }
> +#else
> +static inline int pseries_remove_memblock(unsigned long base,
> + unsigned int memblock_size)
> +{
> + return -EOPNOTSUPP;
> +}
> +static inline int pseries_remove_memory(struct device_node *np)
> +{
> + return -EOPNOTSUPP;
> +}
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
>
> static int pseries_add_memory(struct device_node *np)
> {
> diff --git a/drivers/base/memory.c b/drivers/base/memory.c
> --- a/drivers/base/memory.c
> +++ b/drivers/base/memory.c
> @@ -93,16 +93,6 @@ int register_memory(struct memory_block *memory)
> return error;
> }
>
> -static void
> -unregister_memory(struct memory_block *memory)
> -{
> - BUG_ON(memory->dev.bus != &memory_subsys);
> -
> - /* drop the ref. we got in remove_memory_block() */
> - kobject_put(&memory->dev.kobj);
> - device_unregister(&memory->dev);
> -}
> -
> unsigned long __weak memory_block_size_bytes(void)
> {
> return MIN_MEMORY_BLOCK_SIZE;
> @@ -637,8 +627,28 @@ static int add_memory_section(int nid, struct mem_section *section,
> return ret;
> }
>
> -int remove_memory_block(unsigned long node_id, struct mem_section *section,
> - int phys_device)
> +/*
> + * need an interface for the VM to add new memory regions,
> + * but without onlining it.
> + */
> +int register_new_memory(int nid, struct mem_section *section)
> +{
> + return add_memory_section(nid, section, NULL, MEM_OFFLINE, HOTPLUG);
> +}
> +
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> +static void
> +unregister_memory(struct memory_block *memory)
> +{
> + BUG_ON(memory->dev.bus != &memory_subsys);
> +
> + /* drop the ref. we got in remove_memory_block() */
> + kobject_put(&memory->dev.kobj);
> + device_unregister(&memory->dev);
> +}
> +
> +static int remove_memory_block(unsigned long node_id,
> + struct mem_section *section, int phys_device)
> {
> struct memory_block *mem;
>
> @@ -661,15 +671,6 @@ int remove_memory_block(unsigned long node_id, struct mem_section *section,
> return 0;
> }
>
> -/*
> - * need an interface for the VM to add new memory regions,
> - * but without onlining it.
> - */
> -int register_new_memory(int nid, struct mem_section *section)
> -{
> - return add_memory_section(nid, section, NULL, MEM_OFFLINE, HOTPLUG);
> -}
> -
> int unregister_memory_section(struct mem_section *section)
> {
> if (!present_section(section))
> @@ -677,6 +678,7 @@ int unregister_memory_section(struct mem_section *section)
>
> return remove_memory_block(0, section, 0);
> }
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
>
> /*
> * offline one memory block. If the memory block has been offlined, do nothing.
> diff --git a/include/linux/memory.h b/include/linux/memory.h
> --- a/include/linux/memory.h
> +++ b/include/linux/memory.h
> @@ -114,9 +114,10 @@ extern void unregister_memory_notifier(struct notifier_block *nb);
> extern int register_memory_isolate_notifier(struct notifier_block *nb);
> extern void unregister_memory_isolate_notifier(struct notifier_block *nb);
> extern int register_new_memory(int, struct mem_section *);
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> extern int unregister_memory_section(struct mem_section *);
> +#endif
> extern int memory_dev_init(void);
> -extern int remove_memory_block(unsigned long, struct mem_section *, int);
> extern int memory_notify(unsigned long val, void *v);
> extern int memory_isolate_notify(unsigned long val, void *v);
> extern struct memory_block *find_memory_block_hinted(struct mem_section *,
> diff --git a/include/linux/memory_hotplug.h b/include/linux/memory_hotplug.h
> --- a/include/linux/memory_hotplug.h
> +++ b/include/linux/memory_hotplug.h
> @@ -97,13 +97,13 @@ extern void __online_page_free(struct page *page);
> #ifdef CONFIG_MEMORY_HOTREMOVE
> extern bool is_pageblock_removable_nolock(struct page *page);
> extern int arch_remove_memory(u64 start, u64 size);
> +extern int __remove_pages(struct zone *zone, unsigned long start_pfn,
> + unsigned long nr_pages);
> #endif /* CONFIG_MEMORY_HOTREMOVE */
>
> /* reasonably generic interface to expand the physical pages in a zone */
> extern int __add_pages(int nid, struct zone *zone, unsigned long start_pfn,
> unsigned long nr_pages);
> -extern int __remove_pages(struct zone *zone, unsigned long start_pfn,
> - unsigned long nr_pages);
>
> #ifdef CONFIG_NUMA
> extern int memory_add_physaddr_to_nid(u64 start);
> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
> --- a/mm/memory_hotplug.c
> +++ b/mm/memory_hotplug.c
> @@ -436,6 +436,40 @@ static int __meminit __add_section(int nid, struct zone *zone,
> return register_new_memory(nid, __pfn_to_section(phys_start_pfn));
> }
>
> +/*
> + * Reasonably generic function for adding memory. It is
> + * expected that archs that support memory hotplug will
> + * call this function after deciding the zone to which to
> + * add the new pages.
> + */
> +int __ref __add_pages(int nid, struct zone *zone, unsigned long phys_start_pfn,
> + unsigned long nr_pages)
> +{
> + unsigned long i;
> + int err = 0;
> + int start_sec, end_sec;
> + /* during initialize mem_map, align hot-added range to section */
> + start_sec = pfn_to_section_nr(phys_start_pfn);
> + end_sec = pfn_to_section_nr(phys_start_pfn + nr_pages - 1);
> +
> + for (i = start_sec; i <= end_sec; i++) {
> + err = __add_section(nid, zone, i << PFN_SECTION_SHIFT);
> +
> + /*
> + * EEXIST is finally dealt with by ioresource collision
> + * check. see add_memory() => register_memory_resource()
> + * Warning will be printed if there is collision.
> + */
> + if (err && (err != -EEXIST))
> + break;
> + err = 0;
> + }
> +
> + return err;
> +}
> +EXPORT_SYMBOL_GPL(__add_pages);
> +
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> /* find the smallest valid pfn in the range [start_pfn, end_pfn) */
> static int find_smallest_section_pfn(int nid, struct zone *zone,
> unsigned long start_pfn,
> @@ -658,39 +692,6 @@ static int __remove_section(struct zone *zone, struct mem_section *ms)
> return 0;
> }
>
> -/*
> - * Reasonably generic function for adding memory. It is
> - * expected that archs that support memory hotplug will
> - * call this function after deciding the zone to which to
> - * add the new pages.
> - */
> -int __ref __add_pages(int nid, struct zone *zone, unsigned long phys_start_pfn,
> - unsigned long nr_pages)
> -{
> - unsigned long i;
> - int err = 0;
> - int start_sec, end_sec;
> - /* during initialize mem_map, align hot-added range to section */
> - start_sec = pfn_to_section_nr(phys_start_pfn);
> - end_sec = pfn_to_section_nr(phys_start_pfn + nr_pages - 1);
> -
> - for (i = start_sec; i <= end_sec; i++) {
> - err = __add_section(nid, zone, i << PFN_SECTION_SHIFT);
> -
> - /*
> - * EEXIST is finally dealt with by ioresource collision
> - * check. see add_memory() => register_memory_resource()
> - * Warning will be printed if there is collision.
> - */
> - if (err && (err != -EEXIST))
> - break;
> - err = 0;
> - }
> -
> - return err;
> -}
> -EXPORT_SYMBOL_GPL(__add_pages);
> -
> /**
> * __remove_pages() - remove sections of pages from a zone
> * @zone: zone from which pages need to be removed
> @@ -726,6 +727,7 @@ int __remove_pages(struct zone *zone, unsigned long phys_start_pfn,
> return ret;
> }
> EXPORT_SYMBOL_GPL(__remove_pages);
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
>
> int set_online_page_callback(online_page_callback_t callback)
> {
> diff --git a/mm/sparse.c b/mm/sparse.c
> --- a/mm/sparse.c
> +++ b/mm/sparse.c
> @@ -620,6 +620,7 @@ static void __kfree_section_memmap(struct page *memmap, unsigned long nr_pages)
>
> vmemmap_free(start, end);
> }
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> static void free_map_bootmem(struct page *memmap, unsigned long nr_pages)
> {
> unsigned long start = (unsigned long)memmap;
> @@ -627,6 +628,7 @@ static void free_map_bootmem(struct page *memmap, unsigned long nr_pages)
>
> vmemmap_free(start, end);
> }
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
> #else
> static struct page *__kmalloc_section_memmap(unsigned long nr_pages)
> {
> @@ -664,6 +666,7 @@ static void __kfree_section_memmap(struct page *memmap, unsigned long nr_pages)
> get_order(sizeof(struct page) * nr_pages));
> }
>
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> static void free_map_bootmem(struct page *memmap, unsigned long nr_pages)
> {
> unsigned long maps_section_nr, removing_section_nr, i;
> @@ -690,40 +693,9 @@ static void free_map_bootmem(struct page *memmap, unsigned long nr_pages)
> put_page_bootmem(page);
> }
> }
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
> #endif /* CONFIG_SPARSEMEM_VMEMMAP */
>
> -static void free_section_usemap(struct page *memmap, unsigned long *usemap)
> -{
> - struct page *usemap_page;
> - unsigned long nr_pages;
> -
> - if (!usemap)
> - return;
> -
> - usemap_page = virt_to_page(usemap);
> - /*
> - * Check to see if allocation came from hot-plug-add
> - */
> - if (PageSlab(usemap_page) || PageCompound(usemap_page)) {
> - kfree(usemap);
> - if (memmap)
> - __kfree_section_memmap(memmap, PAGES_PER_SECTION);
> - return;
> - }
> -
> - /*
> - * The usemap came from bootmem. This is packed with other usemaps
> - * on the section which has pgdat at boot time. Just keep it as is now.
> - */
> -
> - if (memmap) {
> - nr_pages = PAGE_ALIGN(PAGES_PER_SECTION * sizeof(struct page))
> - >> PAGE_SHIFT;
> -
> - free_map_bootmem(memmap, nr_pages);
> - }
> -}
> -
> /*
> * returns the number of sections whose mem_maps were properly
> * set. If this is <=0, then that means that the passed-in
> @@ -800,6 +772,39 @@ static inline void clear_hwpoisoned_pages(struct page *memmap, int nr_pages)
> }
> #endif
>
> +#ifdef CONFIG_MEMORY_HOTREMOVE
> +static void free_section_usemap(struct page *memmap, unsigned long *usemap)
> +{
> + struct page *usemap_page;
> + unsigned long nr_pages;
> +
> + if (!usemap)
> + return;
> +
> + usemap_page = virt_to_page(usemap);
> + /*
> + * Check to see if allocation came from hot-plug-add
> + */
> + if (PageSlab(usemap_page) || PageCompound(usemap_page)) {
> + kfree(usemap);
> + if (memmap)
> + __kfree_section_memmap(memmap, PAGES_PER_SECTION);
> + return;
> + }
> +
> + /*
> + * The usemap came from bootmem. This is packed with other usemaps
> + * on the section which has pgdat at boot time. Just keep it as is now.
> + */
> +
> + if (memmap) {
> + nr_pages = PAGE_ALIGN(PAGES_PER_SECTION * sizeof(struct page))
> + >> PAGE_SHIFT;
> +
> + free_map_bootmem(memmap, nr_pages);
> + }
> +}
> +
> void sparse_remove_one_section(struct zone *zone, struct mem_section *ms)
> {
> struct page *memmap = NULL;
> @@ -819,4 +824,5 @@ void sparse_remove_one_section(struct zone *zone, struct mem_section *ms)
> clear_hwpoisoned_pages(memmap, PAGES_PER_SECTION);
> free_section_usemap(memmap, usemap);
> }
> -#endif
> +#endif /* CONFIG_MEMORY_HOTREMOVE */
> +#endif /* CONFIG_MEMORY_HOTPLUG */
^ permalink raw reply
* Re: [PATCH 3/4] powerpc: Optimise 64bit syscall auditing entry path
From: Eric Paris @ 2013-04-10 16:56 UTC (permalink / raw)
To: Anton Blanchard; +Cc: linuxppc-dev, paulus, viro, linux-kernel
In-Reply-To: <20130109104815.2b85895a@kryten>
Patches 1 and 2 I applied for 3.10, but I'd really like to have someone who knows PPC ack 3 and 4. Especially if there is a hope that it goes through my tree...
Link to original messages for your ease of review...
http://marc.info/?l=linux-kernel&m=135768892320439&w=2
http://marc.info/?l=linux-kernel&m=135768895320472&w=2
-Eric
----- Original Message -----
>
> Add an assembly fast path for the syscall audit entry path on
> 64bit. Some distros enable auditing by default which forces us
> through the syscall auditing path even if there are no rules.
>
> I wrote some test cases to validate the patch:
>
> http://ozlabs.org/~anton/junkcode/audit_tests.tar.gz
>
> And to test the performance I ran a simple null syscall
> microbenchmark on a POWER7 box:
>
> http://ozlabs.org/~anton/junkcode/null_syscall.c
>
> Baseline: 949.2 cycles
> Patched: 920.6 cycles
>
> An improvement of 3%. Most of the potential gains are masked by
> the syscall audit exit path which will be fixed in a
> subsequent patch.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
>
> Index: b/arch/powerpc/kernel/entry_64.S
> ===================================================================
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -34,6 +34,12 @@
> #include <asm/ftrace.h>
> #include <asm/hw_irq.h>
>
> +/* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */
> +#include <linux/elf-em.h>
> +#define AUDIT_ARCH_PPC (EM_PPC)
> +#define AUDIT_ARCH_PPC64 (EM_PPC64|__AUDIT_ARCH_64BIT)
> +#define __AUDIT_ARCH_64BIT 0x80000000
> +
> /*
> * System calls.
> */
> @@ -244,6 +250,10 @@ syscall_error:
>
> /* Traced system call support */
> syscall_dotrace:
> +#ifdef CONFIG_AUDITSYSCALL
> + andi. r11,r10,(_TIF_SYSCALL_T_OR_A & ~_TIF_SYSCALL_AUDIT)
> + beq audit_entry
> +#endif
> bl .save_nvgprs
> addi r3,r1,STACK_FRAME_OVERHEAD
> bl .do_syscall_trace_enter
> @@ -253,6 +263,7 @@ syscall_dotrace:
> * for the call number to look up in the table (r0).
> */
> mr r0,r3
> +.Laudit_entry_return:
> ld r3,GPR3(r1)
> ld r4,GPR4(r1)
> ld r5,GPR5(r1)
> @@ -264,6 +275,34 @@ syscall_dotrace:
> ld r10,TI_FLAGS(r10)
> b .Lsyscall_dotrace_cont
>
> +#ifdef CONFIG_AUDITSYSCALL
> +audit_entry:
> + ld r4,GPR0(r1)
> + ld r5,GPR3(r1)
> + ld r6,GPR4(r1)
> + ld r7,GPR5(r1)
> + ld r8,GPR6(r1)
> +
> + andi. r11,r10,_TIF_32BIT
> + beq 1f
> +
> + lis r3,AUDIT_ARCH_PPC@h
> + ori r3,r3,AUDIT_ARCH_PPC@l
> + clrldi r5,r5,32
> + clrldi r6,r6,32
> + clrldi r7,r7,32
> + clrldi r8,r8,32
> + bl .__audit_syscall_entry
> + ld r0,GPR0(r1)
> + b .Laudit_entry_return
> +
> +1: lis r3,AUDIT_ARCH_PPC64@h
> + ori r3,r3,AUDIT_ARCH_PPC64@l
> + bl .__audit_syscall_entry
> + ld r0,GPR0(r1)
> + b .Laudit_entry_return
> +#endif
> +
> syscall_enosys:
> li r3,-ENOSYS
> b syscall_exit
>
^ permalink raw reply
* Re: [PATCH -V5 19/25] powerpc/THP: Differentiate THP PMD entries from HUGETLB PMD entries
From: Aneesh Kumar K.V @ 2013-04-10 18:26 UTC (permalink / raw)
To: Michael Ellerman; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <20130410072122.GC24786@concordia>
Michael Ellerman <michael@ellerman.id.au> writes:
> On Thu, Apr 04, 2013 at 11:27:57AM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> HUGETLB clear the top bit of PMD entries and use that to indicate
>> a HUGETLB page directory. Since we store pfns in PMDs for THP,
>> we would have the top bit cleared by default. Add the top bit mask
>> for THP PMD entries and clear that when we are looking for pmd_pfn.
>>
>> @@ -44,6 +44,14 @@ struct mm_struct;
>> #define PMD_HUGE_RPN_SHIFT PTE_RPN_SHIFT
>> #define HUGE_PAGE_SIZE (ASM_CONST(1) << 24)
>> #define HUGE_PAGE_MASK (~(HUGE_PAGE_SIZE - 1))
>> +/*
>> + * HugeTLB looks at the top bit of the Linux page table entries to
>> + * decide whether it is a huge page directory or not. Mark HUGE
>> + * PMD to differentiate
>> + */
>> +#define PMD_HUGE_NOT_HUGETLB (ASM_CONST(1) << 63)
>> +#define PMD_ISHUGE (_PMD_ISHUGE | PMD_HUGE_NOT_HUGETLB)
>> +#define PMD_HUGE_PROTBITS (0xfff | PMD_HUGE_NOT_HUGETLB)
>>
>> #ifndef __ASSEMBLY__
>> extern void hpte_need_hugepage_flush(struct mm_struct *mm, unsigned long addr,
>> @@ -84,7 +93,8 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
>> /*
>> * Only called for hugepage pmd
>> */
>> - return pmd_val(pmd) >> PMD_HUGE_RPN_SHIFT;
>> + unsigned long val = pmd_val(pmd) & ~PMD_HUGE_PROTBITS;
>> + return val >> PMD_HUGE_RPN_SHIFT;
>> }
>
> This is breaking the 32-bit build for me (pmac32_defconfig):
>
> arch/powerpc/include/asm/pgtable.h:123:2: error: left shift count >= width of type [-Werror]
>
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 5617dee..30c765a 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -110,11 +110,6 @@ static inline int has_transparent_hugepage(void)
return 1;
}
-#else
-#define pmd_large(pmd) 0
-#define has_transparent_hugepage() 0
-#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
-
static inline unsigned long pmd_pfn(pmd_t pmd)
{
/*
@@ -124,6 +119,11 @@ static inline unsigned long pmd_pfn(pmd_t pmd)
return val >> PMD_HUGE_RPN_SHIFT;
}
+#else
+#define pmd_large(pmd) 0
+#define has_transparent_hugepage() 0
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
static inline int pmd_young(pmd_t pmd)
{
return pmd_val(pmd) & PMD_HUGE_ACCESSED;
^ permalink raw reply related
* [PATCH] powerpc/512x: add ifm ac14xx board
From: Anatolij Gustschin @ 2013-04-10 19:10 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Anatolij Gustschin
Add dts file for ac14xx board and its board compatible
string to the generic mpc512x board match list.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
arch/powerpc/boot/dts/ac14xx.dts | 392 +++++++++++++++++++++++++
arch/powerpc/platforms/512x/mpc512x_generic.c | 1 +
2 files changed, 393 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/ac14xx.dts
diff --git a/arch/powerpc/boot/dts/ac14xx.dts b/arch/powerpc/boot/dts/ac14xx.dts
new file mode 100644
index 0000000..a27a460
--- /dev/null
+++ b/arch/powerpc/boot/dts/ac14xx.dts
@@ -0,0 +1,392 @@
+/*
+ * Device Tree Source for the MPC5121e based ac14xx board
+ *
+ * Copyright 2012 Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+/include/ "mpc5121.dtsi"
+
+/ {
+ model = "ac14xx";
+ compatible = "ifm,ac14xx", "fsl,mpc5121";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial7;
+ spi4 = &spi4;
+ spi5 = &spi5;
+ };
+
+ cpus {
+ PowerPC,5121@0 {
+ timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
+ bus-frequency = <160000000>; /* 160 MHz csb bus */
+ clock-frequency = <400000000>; /* 400 MHz ppc core */
+ };
+ };
+
+ memory {
+ reg = <0x00000000 0x10000000>; /* 256MB at 0 */
+ };
+
+ nfc@40000000 {
+ status = "disabled";
+ };
+
+ localbus@80000020 {
+ ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
+ 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
+ 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
+ 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
+ 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
+ 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
+
+ flash@0,0 {
+ compatible = "cfi-flash";
+ reg = <0 0x00000000 0x04000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ device-width = <2>;
+
+ partition@0 {
+ label = "dtb-kernel-production";
+ reg = <0x00000000 0x00400000>;
+ };
+ partition@1 {
+ label = "filesystem-production";
+ reg = <0x00400000 0x03400000>;
+ };
+
+ partition@2 {
+ label = "recovery";
+ reg = <0x03800000 0x00700000>;
+ };
+
+ partition@3 {
+ label = "uboot-code";
+ reg = <0x03f00000 0x00040000>;
+ };
+ partition@4 {
+ label = "uboot-env1";
+ reg = <0x03f40000 0x00020000>;
+ };
+ partition@5 {
+ label = "uboot-env2";
+ reg = <0x03f60000 0x00020000>;
+ };
+ };
+
+ fram@1,0 {
+ compatible = "ifm,ac14xx-fram", "linux,uio-pdrv-genirq";
+ reg = <1 0x00000000 0x00010000>;
+ };
+
+ asi@2,0 {
+ /* masters mapping: CS, CS offset, size */
+ reg = <2 0x00000000 0x00080000
+ 6 0x00000000 0x00080000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ifm,ac14xx-asi-fpga";
+ gpios = <
+ &gpio_pic 26 0 /* prog */
+ &gpio_pic 27 0 /* done */
+ &gpio_pic 10 0 /* reset */
+ >;
+
+ master@1 {
+ interrupts = <20 0x2>;
+ interrupt-parent = <&gpio_pic>;
+ chipselect = <2 0x00009000 0x00009100>;
+ label = "AS-i master 1";
+ };
+
+ master@2 {
+ interrupts = <21 0x2>;
+ interrupt-parent = <&gpio_pic>;
+ chipselect = <6 0x00009000 0x00009100>;
+ label = "AS-i master 2";
+ };
+ };
+
+ netx@3,0 {
+ compatible = "ifm,netx";
+ reg = <0x3 0x00000000 0x00020000>;
+ chipselect = <3 0x00101140 0x00203100>;
+ interrupts = <17 0x8>;
+ gpios = <&gpio_pic 15 0>;
+ };
+
+ safety@5,0 {
+ compatible = "ifm,safety";
+ reg = <0x5 0x00000000 0x00010000>;
+ chipselect = <5 0x00009000 0x00009100>;
+ interrupts = <22 0x2>;
+ interrupt-parent = <&gpio_pic>;
+ gpios = <
+ &gpio_pic 12 0 /* prog */
+ &gpio_pic 11 0 /* done */
+ >;
+ };
+ };
+
+ soc@80000000 {
+
+ clock@f00 {
+ compatible = "fsl,mpc5121rev2-clock", "fsl,mpc5121-clock";
+ };
+
+ /*
+ * GPIO PIC:
+ * interrupts cell = <pin nr, sense>
+ * sense == 8: Level, low assertion
+ * sense == 2: Edge, high-to-low change
+ */
+ gpio_pic: gpio@1100 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sdhc@1500 {
+ cd-gpios = <&gpio_pic 23 0>; /* card detect */
+ wp-gpios = <&gpio_pic 24 0>; /* write protect */
+ wp-inverted; /* WP active high */
+ };
+
+ i2c@1700 {
+ /* use Fast-mode */
+ clock-frequency = <400000>;
+
+ at24@30 {
+ compatible = "at24,24c01";
+ reg = <0x30>;
+ };
+
+ at24@31 {
+ compatible = "at24,24c01";
+ reg = <0x31>;
+ };
+
+ temp@48 {
+ compatible = "ad,ad7414";
+ reg = <0x48>;
+ };
+
+ at24@50 {
+ compatible = "at24,24c01";
+ reg = <0x50>;
+ };
+
+ at24@51 {
+ compatible = "at24,24c01";
+ reg = <0x51>;
+ };
+
+ at24@52 {
+ compatible = "at24,24c01";
+ reg = <0x52>;
+ };
+
+ at24@53 {
+ compatible = "at24,24c01";
+ reg = <0x53>;
+ };
+
+ at24@54 {
+ compatible = "at24,24c01";
+ reg = <0x54>;
+ };
+
+ at24@55 {
+ compatible = "at24,24c01";
+ reg = <0x55>;
+ };
+
+ at24@56 {
+ compatible = "at24,24c01";
+ reg = <0x56>;
+ };
+
+ at24@57 {
+ compatible = "at24,24c01";
+ reg = <0x57>;
+ };
+
+ rtc@68 {
+ compatible = "stm,m41t00";
+ reg = <0x68>;
+ };
+ };
+
+ axe_pic: axe-base@2000 {
+ compatible = "fsl,mpc5121-axe-base";
+ reg = <0x2000 0x100>;
+ interrupts = <42 0x8>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ axe-app {
+ compatible = "fsl,mpc5121-axe-app";
+ interrupt-parent = <&axe_pic>;
+ interrupts = <
+ /* soft interrupts */
+ 0 0x0 1 0x0 2 0x0 3 0x0
+ 4 0x0 5 0x0 6 0x0 7 0x0
+ /* fifo interrupts */
+ 8 0x0 9 0x0 10 0x0 11 0x0
+ >;
+ };
+
+ display@2100 {
+ edid = [00 FF FF FF FF FF FF 00 14 94 00 00 00 00 00 00
+ 0A 12 01 03 80 1C 23 78 CA 88 FF 94 52 54 8E 27
+ 1E 4C 50 00 00 00 01 01 01 01 01 01 01 01 01 01
+ 01 01 01 01 01 01 FB 00 B0 14 00 DC 05 00 08 04
+ 21 00 1C 23 00 00 00 18 00 00 00 FD 00 38 3C 1F
+ 3C 01 0A 20 20 20 20 20 20 20 00 00 00 FC 00 45
+ 54 30 31 38 30 30 33 44 4D 55 0A 0A 00 00 00 10
+ 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D5];
+ };
+
+ can@2300 {
+ status = "disabled";
+ };
+
+ can@2380 {
+ status = "disabled";
+ };
+
+ viu@2400 {
+ status = "disabled";
+ };
+
+ mdio@2800 {
+ phy0: ethernet-phy@1f {
+ compatible = "smsc,lan8700";
+ reg = <0x1f>;
+ };
+ };
+
+ enet: ethernet@2800 {
+ phy-handle = <&phy0>;
+ };
+
+ usb@3000 {
+ status = "disabled";
+ };
+
+ usb@4000 {
+ status = "disabled";
+ };
+
+ /* PSC3 serial port A, aka ttyPSC0 */
+ serial0: psc@11300 {
+ compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+ fsl,rx-fifo-size = <512>;
+ fsl,tx-fifo-size = <512>;
+ };
+
+ /* PSC4 in SPI mode */
+ spi4: psc@11400 {
+ compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+ fsl,rx-fifo-size = <768>;
+ fsl,tx-fifo-size = <768>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ cs-gpios = <&gpio_pic 25 0>;
+
+ flash: m25p128@0 {
+ compatible = "st,m25p128";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "spi-flash0";
+ reg = <0x00000000 0x01000000>;
+ };
+ };
+ };
+
+ /* PSC5 in SPI mode */
+ spi5: psc@11500 {
+ compatible = "fsl,mpc5121-psc-spi", "fsl,mpc5121-psc";
+ fsl,mode = "spi-master";
+ fsl,rx-fifo-size = <128>;
+ fsl,tx-fifo-size = <128>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lcd@0 {
+ compatible = "ilitek,ili922x";
+ reg = <0>;
+ spi-max-frequency = <100000>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+
+ /* PSC7 serial port C, aka ttyPSC2 */
+ serial7: psc@11700 {
+ compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
+ fsl,rx-fifo-size = <512>;
+ fsl,tx-fifo-size = <512>;
+ };
+
+ matrix_keypad@0 {
+ compatible = "gpio-matrix-keypad";
+ debounce-delay-ms = <5>;
+ col-scan-delay-us = <1>;
+ gpio-activelow;
+ col-gpios-binary;
+ col-switch-delay-ms = <200>;
+
+ col-gpios = <&gpio_pic 1 0>; /* pin1 */
+
+ row-gpios = <&gpio_pic 2 0 /* pin2 */
+ &gpio_pic 3 0 /* pin3 */
+ &gpio_pic 4 0>; /* pin4 */
+
+ linux,keymap = <0x0000006e /* FN LEFT */
+ 0x01000067 /* UP */
+ 0x02000066 /* FN RIGHT */
+ 0x00010069 /* LEFT */
+ 0x0101006a /* DOWN */
+ 0x0201006c>; /* RIGHT */
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ backlight {
+ label = "backlight";
+ gpios = <&gpio_pic 0 0>;
+ default-state = "keep";
+ };
+ green {
+ label = "green";
+ gpios = <&gpio_pic 18 0>;
+ default-state = "keep";
+ };
+ red {
+ label = "red";
+ gpios = <&gpio_pic 19 0>;
+ default-state = "keep";
+ };
+ };
+};
diff --git a/arch/powerpc/platforms/512x/mpc512x_generic.c b/arch/powerpc/platforms/512x/mpc512x_generic.c
index 6dfcb51..5fb919b 100644
--- a/arch/powerpc/platforms/512x/mpc512x_generic.c
+++ b/arch/powerpc/platforms/512x/mpc512x_generic.c
@@ -29,6 +29,7 @@
static const char * const board[] __initconst = {
"prt,prtlvt",
"fsl,mpc5125ads",
+ "ifm,ac14xx",
NULL
};
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH V5] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
From: Scott Wood @ 2013-04-10 21:51 UTC (permalink / raw)
To: Jia Hongtao; +Cc: hongtao.jia, B07421, linuxppc-dev
In-Reply-To: <1365409614-2634-1-git-send-email-hongtao.jia@freescale.com>
On 04/08/2013 03:26:54 AM, Jia Hongtao wrote:
> @@ -826,6 +829,124 @@ u64 fsl_pci_immrbar_base(struct pci_controller =20
> *hose)
> return 0;
> }
>=20
> +#ifdef CONFIG_E500
> +
> +#define OP_LWZ 32
> +#define OP_LWZU 33
> +#define OP_LBZ 34
> +#define OP_LBZU 35
> +#define OP_LHZ 40
> +#define OP_LHZU 41
> +#define OP_LHA 42
> +#define OP_LHAU 43
Can you move these to asm/ppc-opcode.h (or possibly =20
asm/ppc-disassemble.h if we don't want to mix the two methods of =20
describing instructions)?
> +static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
> +{
> + unsigned int rd, ra, d;
> +
> + rd =3D get_rt(inst);
> + ra =3D get_ra(inst);
> + d =3D get_d(inst);
> +
> + switch (get_op(inst)) {
> + case OP_LWZ:
> + regs->gpr[rd] =3D 0xffffffff;
> + break;
> +
> + case OP_LWZU:
> + regs->gpr[rd] =3D 0xffffffff;
> + regs->gpr[ra] +=3D (s16)d;
> + break;
> +
> + case OP_LBZ:
> + regs->gpr[rd] =3D 0xff;
> + break;
> +
> + case OP_LBZU:
> + regs->gpr[rd] =3D 0xff;
> + regs->gpr[ra] +=3D (s16)d;
> + break;
> +
> + case OP_LHZ:
> + regs->gpr[rd] =3D 0xffff;
> + break;
> +
> + case OP_LHZU:
> + regs->gpr[rd] =3D 0xffff;
> + regs->gpr[ra] +=3D (s16)d;
> + break;
> +
> + case OP_LHA:
> + regs->gpr[rd] =3D 0xffff;
> + break;
> +
> + case OP_LHAU:
> + regs->gpr[rd] =3D 0xffff;
> + regs->gpr[ra] +=3D (s16)d;
> + break;
The X and (especially for PCI) BRX versions are important -- probably =20
more so than the U versions. I doubt we need the A variant.
If you do support the A variant, why are you not sign-extending the =20
value?
Is this erratum present on any 64-bit chips?
-Scott=
^ permalink raw reply
* [PATCH] powerpc/85xx: Fix MPC8536DS 36-bit device tree
From: Kim Phillips @ 2013-04-10 21:58 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
From: Kumar Gala <galak@kernel.crashing.org>
The localbus node should be in at 0xfffe05000 not 0xffe05000. Also
fixed the names of the localbus and pci nodes to reflect the addresses
they are actually at.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
note: this upstream submission extended to fix pci1.
arch/powerpc/boot/dts/mpc8536ds_36b.dts | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index f8a3b34..6c723ee 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -32,7 +32,7 @@
reg = <0 0 0 0>; // Filled by U-Boot
};
- lbc: localbus@ffe05000 {
+ lbc: localbus@fffe05000 {
reg = <0xf 0xffe05000 0 0x1000>;
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
@@ -44,7 +44,7 @@
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
- pci0: pci@ffe08000 {
+ pci0: pci@fffe08000 {
reg = <0xf 0xffe08000 0 0x1000>;
ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
@@ -59,7 +59,7 @@
0x8800 0 0 4 &mpic 4 1 0 0>;
};
- pci1: pcie@ffe09000 {
+ pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
--
1.8.1.5
^ permalink raw reply related
* [PATCH] powerpc/85xx: enable Silicon image 3132 PCIe to SATA controller
From: Scott Wood @ 2013-04-10 22:40 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev
From: Roy ZANG <tie-fei.zang@freescale.com>
Some 85xx board, for example, P1020RDB-PC has on board silicon image
PCIe to SATA controller and when booting up, the filesystem will auto mount
to the SATA disk. So enable silicon image 3132 pcie to sata controller
by default
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cf815e8..75f17cf 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -106,6 +106,7 @@ CONFIG_SCSI_LOGGING=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
CONFIG_PATA_ALI=y
CONFIG_PATA_VIA=y
CONFIG_NETDEVICES=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 8d00ea5b..64ae227 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -108,6 +108,7 @@ CONFIG_SCSI_LOGGING=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
CONFIG_PATA_ALI=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/2] enable the coreint for the mpc85xx 64bit boards
From: Kevin Hao @ 2013-04-11 1:32 UTC (permalink / raw)
To: Kumar Gala, Benjamin Herrenschmidt; +Cc: linuxppc
Hi,
With the rework of the lazy EE, it seems that 64bit kernel works pretty
well on mpc85xx 64bit boards with lazy EE enabled. So this patch series
tries to enable the coreint for these boards by default. This passed
the ltp test on a t4240qds board and is based on Kumar's next branch.
---
Kevin Hao (2):
powerpc/irq: remove the unneeded flag PACA_IRQ_EE_EDGE
powerpc/85xx: enable coreint for all the 64bit boards
arch/powerpc/include/asm/hw_irq.h | 1 -
arch/powerpc/kernel/exceptions-64e.S | 1 -
arch/powerpc/kernel/irq.c | 8 --------
arch/powerpc/platforms/85xx/p5020_ds.c | 5 -----
arch/powerpc/platforms/85xx/p5040_ds.c | 5 -----
arch/powerpc/platforms/85xx/t4240_qds.c | 5 -----
6 files changed, 25 deletions(-)
--
1.8.1.4
Thanks,
Kevin
^ permalink raw reply
* [PATCH 2/2] powerpc/85xx: enable coreint for all the 64bit boards
From: Kevin Hao @ 2013-04-11 1:32 UTC (permalink / raw)
To: Kumar Gala, Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <1365643954-20798-1-git-send-email-haokexin@gmail.com>
With the patch 7230c564 (powerpc: Rework lazy-interrupt handling),
it seems that the coreint works pretty well on the 85xx 64bit kernel.
So use the coreint by default for these boards.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/platforms/85xx/p5020_ds.c | 5 -----
arch/powerpc/platforms/85xx/p5040_ds.c | 5 -----
arch/powerpc/platforms/85xx/t4240_qds.c | 5 -----
3 files changed, 15 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
index 753a42c..39cfa40 100644
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -75,12 +75,7 @@ define_machine(p5020_ds) {
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
- .get_irq = mpic_get_irq,
-#else
.get_irq = mpic_get_coreint_irq,
-#endif
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
index 1138185..f70e74c 100644
--- a/arch/powerpc/platforms/85xx/p5040_ds.c
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -66,12 +66,7 @@ define_machine(p5040_ds) {
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
- .get_irq = mpic_get_irq,
-#else
.get_irq = mpic_get_coreint_irq,
-#endif
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
index 5998e9f..91ead6b 100644
--- a/arch/powerpc/platforms/85xx/t4240_qds.c
+++ b/arch/powerpc/platforms/85xx/t4240_qds.c
@@ -75,12 +75,7 @@ define_machine(t4240_qds) {
#ifdef CONFIG_PCI
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
- .get_irq = mpic_get_irq,
-#else
.get_irq = mpic_get_coreint_irq,
-#endif
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
--
1.8.1.4
^ permalink raw reply related
* [PATCH 1/2] powerpc/irq: remove the unneeded flag PACA_IRQ_EE_EDGE
From: Kevin Hao @ 2013-04-11 1:32 UTC (permalink / raw)
To: Kumar Gala, Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <1365643954-20798-1-git-send-email-haokexin@gmail.com>
In order to support the Book3E external proxy, the flag
PACA_IRQ_EE_EDGE was introduced in patch 7230c564 (powerpc: Rework
lazy-interrupt handling). But it turns out that this is not needed.
And it is also not used by any code in the current kernel. According
to the PowerISA 2.0.6, the content of EPR (External Proxy Register)
is valid until MSR[EE] is set to 1. Since we never enable the hard irq
before replaying a external interrupt. That means we still can get
the valid interrupt vector from EPR when replaying irq.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/include/asm/hw_irq.h | 1 -
arch/powerpc/kernel/exceptions-64e.S | 1 -
arch/powerpc/kernel/irq.c | 8 --------
3 files changed, 10 deletions(-)
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index e45c494..8bf0789 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -24,7 +24,6 @@
#define PACA_IRQ_DBELL 0x02
#define PACA_IRQ_EE 0x04
#define PACA_IRQ_DEC 0x08 /* Or FIT */
-#define PACA_IRQ_EE_EDGE 0x10 /* BookE only */
#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 42a756e..64f2fbd 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -701,7 +701,6 @@ kernel_dbg_exc:
.endm
masked_interrupt_book3e_0x500:
- // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
masked_interrupt_book3e PACA_IRQ_EE 1
masked_interrupt_book3e_0x900:
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 4f97fe3..dbc1c05 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -171,14 +171,6 @@ notrace unsigned int __check_irq_replay(void)
return 0x500;
#ifdef CONFIG_PPC_BOOK3E
- /* Finally check if an EPR external interrupt happened
- * this bit is typically set if we need to handle another
- * "edge" interrupt from within the MPIC "EPR" handler
- */
- local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE;
- if (happened & PACA_IRQ_EE_EDGE)
- return 0x500;
-
local_paca->irq_happened &= ~PACA_IRQ_DBELL;
if (happened & PACA_IRQ_DBELL)
return 0x280;
--
1.8.1.4
^ permalink raw reply related
* Re: [PATCH -V5 08/25] powerpc: Decode the pte-lp-encoding bits correctly.
From: David Gibson @ 2013-04-11 1:28 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, paulus, linux-mm
In-Reply-To: <87li8qolej.fsf@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 5036 bytes --]
On Wed, Apr 10, 2013 at 01:41:16PM +0530, Aneesh Kumar K.V wrote:
> David Gibson <dwg@au1.ibm.com> writes:
>
> > On Thu, Apr 04, 2013 at 11:27:46AM +0530, Aneesh Kumar K.V wrote:
> >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> >>
> >> We look at both the segment base page size and actual page size and store
> >> the pte-lp-encodings in an array per base page size.
> >>
> >> We also update all relevant functions to take actual page size argument
> >> so that we can use the correct PTE LP encoding in HPTE. This should also
> >> get the basic Multiple Page Size per Segment (MPSS) support. This is needed
> >> to enable THP on ppc64.
> >>
>
> ....
>
> >> +static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
> >> +{
> >> + int i, shift;
> >> + unsigned int mask;
> >> + /* Look at the 8 bit LP value */
> >> + unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
> >> +
> >> + if (!(hptep->v & HPTE_V_VALID))
> >> + return -1;
> >
> > Folding the validity check into the size check seems confusing to me.
>
> We do end up with invalid hpte with which we call
> hpte_actual_psize. So that check is needed. I can either move to caller,
> but then i will have to replicate it in all the call sites.
>
>
> >> + /* First check if it is large page */
> >> + if (!(hptep->v & HPTE_V_LARGE))
> >> + return MMU_PAGE_4K;
> >> +
> >> + /* start from 1 ignoring MMU_PAGE_4K */
> >> + for (i = 1; i < MMU_PAGE_COUNT; i++) {
> >> + /* valid entries have a shift value */
> >> + if (!mmu_psize_defs[i].shift)
> >> + continue;
> >
> > Isn't this check redundant with the one below?
>
> Yes. I guess we can safely assume that if penc is valid then we do
> support that specific large page.
>
> I will drop this and keep the penc check. That is more correct check
>
> >> + /* invalid penc */
> >> + if (mmu_psize_defs[psize].penc[i] == -1)
> >> + continue;
> >> + /*
> >> + * encoding bits per actual page size
> >> + * PTE LP actual page size
> >> + * rrrr rrrz >=8KB
> >> + * rrrr rrzz >=16KB
> >> + * rrrr rzzz >=32KB
> >> + * rrrr zzzz >=64KB
> >> + * .......
> >> + */
> >> + shift = mmu_psize_defs[i].shift - LP_SHIFT;
> >> + if (shift > LP_BITS)
> >> + shift = LP_BITS;
> >> + mask = (1 << shift) - 1;
> >> + if ((lp & mask) == mmu_psize_defs[psize].penc[i])
> >> + return i;
> >> + }
> >
> > Shouldn't we have a BUG() or something here. If we get here we've
> > somehow created a PTE with LP bits we can't interpret, yes?
>
> I don't know. Is BUG() the right thing to do ?
Well, it's a situation that should never occur, and it's not clear
what we can do to fix it if it does, so, yeah, I think BUG() is appropriate.
> >> + return -1;
> >> +}
> >> +
> >> static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
> >> unsigned long vpn, int psize, int ssize,
> >> int local)
> >> @@ -251,6 +294,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
> >> struct hash_pte *hptep = htab_address + slot;
> >> unsigned long hpte_v, want_v;
> >> int ret = 0;
> >> + int actual_psize;
> >>
> >> want_v = hpte_encode_avpn(vpn, psize, ssize);
> >>
> >> @@ -260,9 +304,13 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
> >> native_lock_hpte(hptep);
> >>
> >> hpte_v = hptep->v;
> >> -
> >> + actual_psize = hpte_actual_psize(hptep, psize);
> >> + if (actual_psize < 0) {
> >> + native_unlock_hpte(hptep);
> >> + return -1;
> >> + }
> >
> > Wouldn't it make more sense to only do the psize lookup once you've
> > found a matching hpte?
>
> But we need to do psize lookup even if V_COMPARE fail, because we want
> to do tlbie in both the case.
Ah, yes. Sorry, misunderstood what this code was doing.
[snip]
> >> @@ -388,19 +444,26 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
> >> penc = LP_MASK(i+1) >> LP_SHIFT;
> >> for (size = 0; size < MMU_PAGE_COUNT; size++) {
> >
> >>
> >> - /* 4K pages are not represented by LP */
> >> - if (size == MMU_PAGE_4K)
> >> - continue;
> >> -
> >> /* valid entries have a shift value */
> >> if (!mmu_psize_defs[size].shift)
> >> continue;
> >> + for (a_size = 0; a_size < MMU_PAGE_COUNT; a_size++) {
> >
> > Can't you resize hpte_actual_psize() here instead of recoding the
> > lookup?
>
> I thought about that, but re-coding avoided some repeated check. But
> then, if I follow your review comments of avoiding hpte valid check etc, may
> be I can reuse the hpte_actual_psize. Will try this.
hpte_decode() is only used in the kexec() path so some repeated simple
tests don't really matter.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 06/25] powerpc: Reduce PTE table memory wastage
From: David Gibson @ 2013-04-11 1:20 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, paulus, linux-mm
In-Reply-To: <87eheinuq5.fsf@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2935 bytes --]
On Wed, Apr 10, 2013 at 11:17:30PM +0530, Aneesh Kumar K.V wrote:
> "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
>
> > David Gibson <dwg@au1.ibm.com> writes:
> >
> >> On Wed, Apr 10, 2013 at 11:59:29AM +0530, Aneesh Kumar K.V wrote:
> >>> David Gibson <dwg@au1.ibm.com> writes:
> >>> > On Thu, Apr 04, 2013 at 11:27:44AM +0530, Aneesh Kumar K.V wrote:
> >> [snip]
> >>> >> @@ -97,13 +100,45 @@ void __destroy_context(int context_id)
> >>> >> }
> >>> >> EXPORT_SYMBOL_GPL(__destroy_context);
> >>> >>
> >>> >> +#ifdef CONFIG_PPC_64K_PAGES
> >>> >> +static void destroy_pagetable_page(struct mm_struct *mm)
> >>> >> +{
> >>> >> + int count;
> >>> >> + struct page *page;
> >>> >> +
> >>> >> + page = mm->context.pgtable_page;
> >>> >> + if (!page)
> >>> >> + return;
> >>> >> +
> >>> >> + /* drop all the pending references */
> >>> >> + count = atomic_read(&page->_mapcount) + 1;
> >>> >> + /* We allow PTE_FRAG_NR(16) fragments from a PTE page */
> >>> >> + count = atomic_sub_return(16 - count, &page->_count);
> >>> >
> >>> > You should really move PTE_FRAG_NR to a header so you can actually use
> >>> > it here rather than hard coding 16.
> >>> >
> >>> > It took me a fair while to convince myself that there is no race here
> >>> > with something altering mapcount and count between the atomic_read()
> >>> > and the atomic_sub_return(). It could do with a comment to explain
> >>> > why that is safe.
> >>> >
> >>> > Re-using the mapcount field for your index also seems odd, and it took
> >>> > me a while to convince myself that that's safe too. Wouldn't it be
> >>> > simpler to store a pointer to the next sub-page in the mm_context
> >>> > instead? You can get from that to the struct page easily enough with a
> >>> > shift and pfn_to_page().
> >>>
> >>> I found using _mapcount simpler in this case. I was looking at it not
> >>> as an index, but rather how may fragments are mapped/used already.
> >>
> >> Except that it's actually (#fragments - 1). Using subpage pointer
> >> makes the fragments calculation (very slightly) harder, but the
> >> calculation of the table address easier. More importantly it avoids
> >> adding effectively an extra variable - which is then shoehorned into a
> >> structure not really designed to hold it.
> >
> > Even with subpage pointer we would need mm->context.pgtable_page or
> > something similar. We don't add any other extra variable right ?. Let me
> > try what you are suggesting here and see if that make it simpler.
>
>
> Here is what I ended up with. I will fold this in next update
Yeah, that looks better to me. Note that ~PAGE_MASK is the more usual
idiom, rather than (PAGE_SIZE - 1).
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 06/25] powerpc: Reduce PTE table memory wastage
From: David Gibson @ 2013-04-11 1:12 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <87r4iiom8a.fsf@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2041 bytes --]
On Wed, Apr 10, 2013 at 01:23:25PM +0530, Aneesh Kumar K.V wrote:
> David Gibson <dwg@au1.ibm.com> writes:
> > On Wed, Apr 10, 2013 at 11:59:29AM +0530, Aneesh Kumar K.V wrote:
> >> David Gibson <dwg@au1.ibm.com> writes:
> >> > On Thu, Apr 04, 2013 at 11:27:44AM +0530, Aneesh Kumar K.V wrote:
[snip]
> >> > You should really move PTE_FRAG_NR to a header so you can actually use
> >> > it here rather than hard coding 16.
> >> >
> >> > It took me a fair while to convince myself that there is no race here
> >> > with something altering mapcount and count between the atomic_read()
> >> > and the atomic_sub_return(). It could do with a comment to explain
> >> > why that is safe.
> >> >
> >> > Re-using the mapcount field for your index also seems odd, and it took
> >> > me a while to convince myself that that's safe too. Wouldn't it be
> >> > simpler to store a pointer to the next sub-page in the mm_context
> >> > instead? You can get from that to the struct page easily enough with a
> >> > shift and pfn_to_page().
> >>
> >> I found using _mapcount simpler in this case. I was looking at it not
> >> as an index, but rather how may fragments are mapped/used already.
> >
> > Except that it's actually (#fragments - 1). Using subpage pointer
> > makes the fragments calculation (very slightly) harder, but the
> > calculation of the table address easier. More importantly it avoids
> > adding effectively an extra variable - which is then shoehorned into a
> > structure not really designed to hold it.
>
> Even with subpage pointer we would need mm->context.pgtable_page or
> something similar. We don't add any other extra variable right ?. Let me
> try what you are suggesting here and see if that make it simpler.
No, because the struct page * can be easily derived from the subpage
pointer.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 09/25] powerpc: Fix hpte_decode to use the correct decoding for page sizes
From: David Gibson @ 2013-04-11 3:20 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1365055083-31956-10-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1210 bytes --]
On Thu, Apr 04, 2013 at 11:27:47AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> As per ISA doc, we encode base and actual page size in the LP bits of
> PTE. The number of bit used to encode the page sizes depend on actual
> page size. ISA doc lists this as
>
> PTE LP actual page size
> rrrr rrrz >=8KB
> rrrr rrzz >=16KB
> rrrr rzzz >=32KB
> rrrr zzzz >=64KB
> rrrz zzzz >=128KB
> rrzz zzzz >=256KB
> rzzz zzzz >=512KB
> zzzz zzzz >=1MB
>
> ISA doc also says
> "The values of the “z” bits used to specify each size, along with all possible
> values of “r” bits in the LP field, must result in LP values distinct from
> other LP values for other sizes."
>
> based on the above update hpte_decode to use the correct decoding for LP bits.
>
> Acked-by: Paul Mackerras <paulus@samba.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 15/25] mm/THP: Add pmd args to pgtable deposit and withdraw APIs
From: David Gibson @ 2013-04-11 3:40 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: Andrea Arcangeli, paulus, linuxppc-dev, linux-mm
In-Reply-To: <1365055083-31956-16-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 754 bytes --]
On Thu, Apr 04, 2013 at 11:27:53AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> This will be later used by powerpc THP support. In powerpc we want to use
> pgtable for storing the hash index values. So instead of adding them to
> mm_context list, we would like to store them in the second half of pmd
>
> Cc: Andrea Arcangeli <aarcange@redhat.com>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Looks ok, afaict.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 13/25] powerpc: Update tlbie/tlbiel as per ISA doc
From: David Gibson @ 2013-04-11 3:30 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1365055083-31956-14-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2239 bytes --]
On Thu, Apr 04, 2013 at 11:27:51AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> This make sure we handle multiple page size segment correctly.
This needs a much more detailed message. In what way was the existing
code not matching the ISA documentation? What consequences did that
have?
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_native_64.c | 30 ++++++++++++++++++++++++++++--
> 1 file changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index b461b2d..ac84fa6 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -61,7 +61,10 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
>
> switch (psize) {
> case MMU_PAGE_4K:
> + /* clear out bits after (52) [0....52.....63] */
> + va &= ~((1ul << (64 - 52)) - 1);
> va |= ssize << 8;
> + va |= mmu_psize_defs[apsize].sllp << 6;
sllp is the per-segment encoding, so it sure must be looked up via
psize, not apsize.
> asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> : "memory");
> @@ -69,9 +72,19 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
> default:
> /* We need 14 to 14 + i bits of va */
> penc = mmu_psize_defs[psize].penc[apsize];
> - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
> + va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> + /* Add AVAL part */
> + if (psize != apsize) {
> + /*
> + * MPSS, 64K base page size and 16MB parge page size
> + * We don't need all the bits, but this seems to work.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
"seems to work" is not a comment I like to see in core MMU code...
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V5 12/25] powerpc: Return all the valid pte ecndoing in KVM_PPC_GET_SMMU_INFO ioctl
From: David Gibson @ 2013-04-11 3:24 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1365055083-31956-13-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
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On Thu, Apr 04, 2013 at 11:27:50AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Surely this can't be correct until the KVM H_ENTER implementation is
updated to cope with the MPSS page sizes.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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