* [PATCH v2 10/15] powerpc/85xx: fix 64-bit support for cpu hotplug
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
* The paca[cpu].cpu_start is used as a signal to indicate if the cpu
should start. So it should be cleard in .cpu_die().
* The limit memory routine only needs to be ran once at boot time
by the boot cpu. Prevent other cpus running it again.
* Rearrange the code segment in smp_85xx_kick_cpu() to share codes
between PPC64 and PPC32 as far as possible.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/smp.c | 3 +++
arch/powerpc/mm/tlb_nohash.c | 6 ++++--
arch/powerpc/platforms/85xx/smp.c | 23 +++++++++++------------
4 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0ad6e30..aa5794b 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -347,7 +347,7 @@ config SWIOTLB
config HOTPLUG_CPU
bool "Support for enabling/disabling CPUs"
depends on SMP && HOTPLUG && (PPC_PSERIES || \
- PPC_PMAC || PPC_POWERNV || PPC_85xx)
+ PPC_PMAC || PPC_POWERNV || FSL_SOC_BOOKE)
---help---
Say Y here to be able to disable and re-enable individual
CPUs at runtime on SMP machines.
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 386c7ea..c8aa739 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -401,6 +401,9 @@ void generic_cpu_die(unsigned int cpu)
smp_rmb();
if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
platform_cpu_die(cpu);
+#ifdef CONFIG_PPC64
+ paca[cpu].cpu_start = 0;
+#endif
return;
}
msleep(100);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 6888cad..de7bf06 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -627,8 +627,10 @@ static void __early_init_mmu(int boot_cpu)
num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
- /* limit memory so we dont have linear faults */
- memblock_enforce_memory_limit(linear_map_top);
+ if (boot_cpu) {
+ /* limit memory so we dont have linear faults */
+ memblock_enforce_memory_limit(linear_map_top);
+ }
patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 6eae2e0..74d8cde 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -251,10 +251,6 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
spin_table = phys_to_virt(*cpu_rel_addr);
local_irq_save(flags);
-#ifdef CONFIG_PPC32
-#ifdef CONFIG_HOTPLUG_CPU
- /* Corresponding to generic_set_cpu_dead() */
- generic_set_cpu_up(nr);
if (system_state == SYSTEM_RUNNING) {
/*
@@ -298,12 +294,19 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
/* clear the acknowledge status */
__secondary_hold_acknowledge = -1;
}
-#endif
flush_spin_table(spin_table);
out_be32(&spin_table->pir, hw_cpu);
+#ifdef CONFIG_PPC32
out_be32(&spin_table->addr_l, __pa(__early_start));
+#else
+ out_be32(&spin_table->addr_h,
+ __pa(*(u64 *)generic_secondary_smp_init) >> 32);
+ out_be32(&spin_table->addr_l,
+ __pa(*(u64 *)generic_secondary_smp_init) & 0xffffffff);
+#endif
flush_spin_table(spin_table);
+#ifdef CONFIG_PPC32
/* Wait a bit for the CPU to ack. */
if (!spin_event_timeout(__secondary_hold_acknowledge == hw_cpu,
10000, 100)) {
@@ -312,18 +315,14 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
ret = -ENOENT;
goto out;
}
-out:
#else
smp_generic_kick_cpu(nr);
-
- flush_spin_table(spin_table);
- out_be32(&spin_table->pir, hw_cpu);
- out_be64((u64 *)(&spin_table->addr_h),
- __pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
- flush_spin_table(spin_table);
#endif
+ /* Corresponding to generic_set_cpu_dead() */
+ generic_set_cpu_up(nr);
cur_booting_core = hw_cpu;
+out:
local_irq_restore(flags);
if (ioremappable)
--
1.7.3
^ permalink raw reply related
* [PATCH v2 07/15] powerpc/85xx: add time base sync for SoCs based on e500mc/e5500
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
In the case of SMP, during the time base sync period, all time bases of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet based SoCs.
Define a struct ccsr_rcpm to describe the register map.
This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,
etc.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/include/asm/fsl_guts.h | 38 +++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/smp.c | 32 +++++++++++++++++++++++++++++
2 files changed, 70 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index 77ced0b..4eac1cf 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -106,6 +106,44 @@ struct ccsr_guts {
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
+struct ccsr_rcpm {
+ u8 res0000[4];
+ __be32 cdozsr; /* 0x0004 - Core Doze Status Register */
+ u8 res0008[4];
+ __be32 cdozcr; /* 0x000c - Core Doze Control Register */
+ u8 res0010[4];
+ __be32 cnapsr; /* 0x0014 - Core Nap Status Register */
+ u8 res0018[4];
+ __be32 cnapcr; /* 0x001c - Core Nap Control Register */
+ u8 res0020[4];
+ __be32 cdozpsr; /* 0x0024 - Core Doze Previous Status Register */
+ u8 res0028[4];
+ __be32 cnappsr; /* 0x002c - Core Nap Previous Status Register */
+ u8 res0030[4];
+ __be32 cwaitsr; /* 0x0034 - Core Wait Status Register */
+ u8 res0038[4];
+ __be32 cwdtdsr; /* 0x003c - Core watchdog detect status register */
+ __be32 powmgtcsr; /* 0x0040 - Power Mangement Control & Status Register */
+ u8 res0044[12];
+ __be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception Control Register */
+ u8 res0054[16];
+ __be32 cpmimr; /* 0x0064 - Core PM IRQ Mask Register */
+ u8 res0068[4];
+ __be32 cpmcimr; /* 0x006c - Core PM Critical IRQ Mask Register */
+ u8 res0070[4];
+ __be32 cpmmcmr; /* 0x0074 - Core PM Machine Check Mask Register */
+ u8 res0078[4];
+ __be32 cpmnmimr; /* 0x007c - Core PM NMI Mask Register */
+ u8 res0080[4];
+ __be32 ctbenr; /* 0x0084 - Core Time Base Enable Register */
+ u8 res0088[4];
+ __be32 ctbckselr; /* 0x008c - Core Time Base Clock Select Register */
+ u8 res0090[4];
+ __be32 ctbhltcr; /* 0x0094 - Core Time Base Halt Control Register */
+ u8 res0098[4];
+ __be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask control register */
+};
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 6a17599..6c2fe6b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -44,7 +44,36 @@ static struct ccsr_guts __iomem *guts;
static u64 timebase;
static int tb_req;
static int tb_valid;
+static u32 cur_booting_core;
+#ifdef CONFIG_PPC_E500MC
+/* get a physical mask of online cores and booting core */
+static inline u32 get_phy_cpu_mask(void)
+{
+ u32 mask;
+ int cpu;
+
+ mask = 1 << cur_booting_core;
+ for_each_online_cpu(cpu)
+ mask |= 1 << get_hard_smp_processor_id(cpu);
+
+ return mask;
+}
+
+static void mpc85xx_timebase_freeze(int freeze)
+{
+ struct ccsr_rcpm __iomem *rcpm = (typeof(rcpm))guts;
+ u32 mask = get_phy_cpu_mask();
+
+ if (freeze)
+ clrbits32(&rcpm->ctbenr, mask);
+ else
+ setbits32(&rcpm->ctbenr, mask);
+
+ /* read back to push the previos write */
+ in_be32(&rcpm->ctbenr);
+}
+#else
static void mpc85xx_timebase_freeze(int freeze)
{
uint32_t mask;
@@ -57,6 +86,7 @@ static void mpc85xx_timebase_freeze(int freeze)
in_be32(&guts->devdisr);
}
+#endif
static void mpc85xx_give_timebase(void)
{
@@ -244,6 +274,7 @@ out:
__pa((u64)*((unsigned long long *)generic_secondary_smp_init)));
flush_spin_table(spin_table);
#endif
+ cur_booting_core = hw_cpu;
local_irq_restore(flags);
@@ -378,6 +409,7 @@ static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = "fsl,p1022-guts", },
{ .compatible = "fsl,p1023-guts", },
{ .compatible = "fsl,p2020-guts", },
+ { .compatible = "fsl,qoriq-rcpm-1.0", },
{},
};
--
1.7.3
^ permalink raw reply related
* [PATCH v2 11/15] powerpc/rcpm: add struct ccsr_rcpm_v2
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/include/asm/fsl_guts.h | 66 +++++++++++++++++++++++++++++++++++
1 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index b8a08d5..193d1f1 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -145,6 +145,72 @@ struct ccsr_rcpm {
__be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask control register */
};
+struct ccsr_rcpm_v2 {
+ u8 res_00[12];
+ u32 tph10sr0; /* Thread PH10 Status Register */
+ u8 res_10[12];
+ u32 tph10setr0; /* Thread PH10 Set Control Register */
+ u8 res_20[12];
+ u32 tph10clrr0; /* Thread PH10 Clear Control Register */
+ u8 res_30[12];
+ u32 tph10psr0; /* Thread PH10 Previous Status Register */
+ u8 res_40[12];
+ u32 twaitsr0; /* Thread Wait Status Register */
+ u8 res_50[96];
+ u32 pcph15sr; /* Physical Core PH15 Status Register */
+ u32 pcph15setr; /* Physical Core PH15 Set Control Register */
+ u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
+ u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
+ u8 res_c0[16];
+ u32 pcph20sr; /* Physical Core PH20 Status Register */
+ u32 pcph20setr; /* Physical Core PH20 Set Control Register */
+ u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
+ u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
+ u32 pcpw20sr; /* Physical Core PW20 Status Register */
+ u8 res_e0[12];
+ u32 pcph30sr; /* Physical Core PH30 Status Register */
+ u32 pcph30setr; /* Physical Core PH30 Set Control Register */
+ u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
+ u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
+ u8 res_100[32];
+ u32 ippwrgatecr; /* IP Power Gating Control Register */
+ u8 res_124[12];
+ u32 powmgtcsr; /* Power Management Control & Status Reg */
+#define RCPM_POWMGTCSR_LPM20_RQ 0x00100000
+#define RCPM_POWMGTCSR_LPM20_ST 0x00000200
+#define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
+ u8 res_134[12];
+ u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
+ u8 res_150[12];
+ u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
+ u8 res_160[12];
+ u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
+ u8 res_170[12];
+ u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
+ u8 res_180[12];
+ u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
+ u8 res_190[12];
+ u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
+ u32 pctbenr; /* Physical Core Time Base Enable Reg */
+ u32 pctbclkselr; /* Physical Core Time Base Clock Select */
+ u32 tbclkdivr; /* Time Base Clock Divider Register */
+ u8 res_1ac[4];
+ u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
+ u32 clpcl10sr; /* Cluster PCL10 Status Register */
+ u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
+ u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
+ u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
+ u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
+ u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
+ u32 cdpwroksetr; /* Core Domain Power OK Set Register */
+ u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
+ u32 cdpwrensr; /* Core Domain Power Enable Status Register */
+ u32 cddslsr; /* Core Domain Deep Sleep Status Register */
+ u8 res_1e8[8];
+ u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
+ u8 res_300[3568];
+};
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
--
1.7.3
^ permalink raw reply related
* [PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cache operation
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/kernel/fsl_booke_cache.S | 11 ++++++++++-
1 files changed, 10 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/fsl_booke_cache.S b/arch/powerpc/kernel/fsl_booke_cache.S
index 232c47b..24a52bb 100644
--- a/arch/powerpc/kernel/fsl_booke_cache.S
+++ b/arch/powerpc/kernel/fsl_booke_cache.S
@@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1)
blr
+#define PVR_E6500 0x8040
+
/* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
_GLOBAL(__flush_disable_L1)
+/* L1 Data Cache of e6500 contains no modified data, no flush is required */
+ mfspr r3, SPRN_PVR
+ rlwinm r4, r3, 16, 0xffff
+ lis r5, 0
+ ori r5, r5, PVR_E6500@l
+ cmpw r4, r5
+ beq 2f
mflr r10
bl flush_dcache_L1 /* Flush L1 d-cache */
mtlr r10
- msync
+2: msync
mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
li r5, 2
rlwimi r4, r5, 0, 3
--
1.7.3
^ permalink raw reply related
* [PATCH v2 14/15] powerpc/smp: add cpu hotplug support for e6500
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
* Only if two threads of one core are offline, the core can
enter PH20 state.
* Clear PH20 bits before core reset, or core will not restart.
* Introduced a variable l2cache_type in the struce cpu_spec to
indentify the type of L2 cache.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/include/asm/cputable.h | 10 ++++++++
arch/powerpc/kernel/cputable.c | 5 ++++
arch/powerpc/platforms/85xx/smp.c | 40 +++++++++++++++++++++++++++++-----
3 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index f326444..3715def 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -33,6 +33,13 @@ enum powerpc_pmc_type {
PPC_PMC_G4 = 3,
};
+enum powerpc_l2cache_type {
+ PPC_L2_CACHE_DEFAULT = 0,
+ PPC_L2_CACHE_CORE = 1, /* L2 cache used exclusively by one core */
+ PPC_L2_CACHE_CLUSTER = 2, /* L2 cache shared by a core cluster */
+ PPC_L2_CACHE_SOC = 3, /* L2 cache shared by all cores */
+};
+
struct pt_regs;
extern int machine_check_generic(struct pt_regs *regs);
@@ -58,6 +65,9 @@ struct cpu_spec {
unsigned int icache_bsize;
unsigned int dcache_bsize;
+ /* L2 cache type */
+ enum powerpc_l2cache_type l2cache_type;
+
/* number of performance monitor counters */
unsigned int num_pmcs;
enum powerpc_pmc_type pmc_type;
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index cc39139..a7329c1 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2004,6 +2004,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500v1,
.machine_check = machine_check_e500,
.platform = "ppc8540",
+ .l2cache_type = PPC_L2_CACHE_SOC,
},
{ /* e500v2 */
.pvr_mask = 0xffff0000,
@@ -2023,6 +2024,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500v2,
.machine_check = machine_check_e500,
.platform = "ppc8548",
+ .l2cache_type = PPC_L2_CACHE_SOC,
},
{ /* e500mc */
.pvr_mask = 0xffff0000,
@@ -2040,6 +2042,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_setup = __setup_cpu_e500mc,
.machine_check = machine_check_e500mc,
.platform = "ppce500mc",
+ .l2cache_type = PPC_L2_CACHE_CORE,
},
#endif /* CONFIG_PPC32 */
{ /* e5500 */
@@ -2061,6 +2064,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif
.machine_check = machine_check_e500mc,
.platform = "ppce5500",
+ .l2cache_type = PPC_L2_CACHE_CORE,
},
{ /* e6500 */
.pvr_mask = 0xffff0000,
@@ -2082,6 +2086,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
#endif
.machine_check = machine_check_e500mc,
.platform = "ppce6500",
+ .l2cache_type = PPC_L2_CACHE_CLUSTER,
},
#ifdef CONFIG_PPC32
{ /* default match */
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 5f3eee3..a8b4df7 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -166,13 +166,31 @@ static void core_reset_erratum(int hw_cpu)
{
#ifdef CONFIG_PPC_E500MC
struct ccsr_rcpm __iomem *rcpm = guts_regs;
+ struct ccsr_rcpm_v2 __iomem *rcpm_v2 = guts_regs;
- clrbits32(&rcpm->cnapcr, 1 << hw_cpu);
+ if (rcpmv2)
+ setbits32(&rcpm_v2->pcph20clrr,
+ 1 << cpu_core_index_of_thread(hw_cpu));
+ else
+ clrbits32(&rcpm->cnapcr, 1 << hw_cpu);
#endif
}
#ifdef CONFIG_HOTPLUG_CPU
#ifdef CONFIG_PPC_E500MC
+static inline bool is_core_down(unsigned int thread)
+{
+ cpumask_t thd_mask;
+
+ if (!smt_capable())
+ return true;
+
+ cpumask_shift_left(&thd_mask, &threads_core_mask,
+ cpu_core_index_of_thread(thread) * threads_per_core);
+
+ return !cpumask_intersects(&thd_mask, cpu_online_mask);
+}
+
static void __cpuinit smp_85xx_mach_cpu_die(void)
{
unsigned int cpu = smp_processor_id();
@@ -183,8 +201,11 @@ static void __cpuinit smp_85xx_mach_cpu_die(void)
mtspr(SPRN_TCR, 0);
- __flush_disable_L1();
- disable_backside_L2_cache();
+ if (is_core_down(cpu))
+ __flush_disable_L1();
+
+ if (cur_cpu_spec->l2cache_type == PPC_L2_CACHE_CORE)
+ disable_backside_L2_cache();
generic_set_cpu_dead(cpu);
@@ -195,9 +216,16 @@ void platform_cpu_die(unsigned int cpu)
{
unsigned int hw_cpu = get_hard_smp_processor_id(cpu);
struct ccsr_rcpm __iomem *rcpm = guts_regs;
-
- /* Core Nap Operation */
- setbits32(&rcpm->cnapcr, 1 << hw_cpu);
+ struct ccsr_rcpm_v2 __iomem *rcpm_v2 = guts_regs;
+
+ if (rcpmv2 && is_core_down(cpu)) {
+ /* enter PH20 status */
+ setbits32(&rcpm_v2->pcph20setr,
+ 1 << cpu_core_index_of_thread(hw_cpu));
+ } else if (!rcpmv2) {
+ /* Core Nap Operation */
+ setbits32(&rcpm->cnapcr, 1 << hw_cpu);
+ }
}
#else
/* for e500v1 and e500v2 */
--
1.7.3
^ permalink raw reply related
* [PATCH v2 15/15] powerpc/rcpm: add sleep support for T4/B4 chips
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
RCPM unit controls the power managment of T4/B4 chips. Software can
access RCPM registers to put specific thread/core in PH10/PH15/PH20/PH30
state or put the device in LPM10/LPM20/LPM40 mode.
The RCPM unit supports several wake up sources through internal timers
and internal and external interrupts.
When the device enter sleep state, it will be put in LPM20 mode.
The command is "echo standby > /sys/power/state".
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/sysdev/fsl_rcpm.c | 54 +++++++++++++++++++++++++++++++++++++---
1 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
index fd789da..10e5cb3 100644
--- a/arch/powerpc/sysdev/fsl_rcpm.c
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -20,6 +20,7 @@
#include <asm/fsl_guts.h>
static struct ccsr_rcpm __iomem *rcpm_regs;
+static struct ccsr_rcpm_v2 __iomem *rcpm2_regs;
static int rcpm_suspend_enter(suspend_state_t state)
{
@@ -53,6 +54,41 @@ static int rcpm_suspend_enter(suspend_state_t state)
return ret;
}
+static int rcpm_v2_suspend_enter(suspend_state_t state)
+{
+ int ret = 0;
+
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+
+ /* clear previous LPM20 status */
+ setbits32(&rcpm2_regs->powmgtcsr, RCPM_POWMGTCSR_P_LPM20_ST);
+ /* enter LPM20 status */
+ setbits32(&rcpm2_regs->powmgtcsr, RCPM_POWMGTCSR_LPM20_RQ);
+
+ /* At this point, the device is in LPM20 status. */
+
+ /* resume ... */
+ ret = spin_event_timeout(
+ (in_be32(&rcpm2_regs->powmgtcsr) & RCPM_POWMGTCSR_LPM20_ST)
+ == 0, 10000, 10);
+ if (!ret) {
+ pr_err("%s: timeout waiting for LPM20 bit to be cleared\n",
+ __func__);
+ ret = -EINVAL;
+ }
+
+ break;
+
+ default:
+ ret = -EINVAL;
+
+ }
+
+ return ret;
+
+}
+
static int rcpm_suspend_valid(suspend_state_t state)
{
if (state == PM_SUSPEND_STANDBY)
@@ -63,16 +99,25 @@ static int rcpm_suspend_valid(suspend_state_t state)
static const struct platform_suspend_ops rcpm_suspend_ops = {
.valid = rcpm_suspend_valid,
- .enter = rcpm_suspend_enter,
};
static int rcpm_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
- rcpm_regs = of_iomap(np, 0);
- if (!rcpm_regs)
- return -ENOMEM;
+ if (of_device_is_compatible(np, "fsl,qoriq-rcpm-2.0")) {
+ rcpm2_regs = of_iomap(np, 0);
+ if (!rcpm2_regs)
+ return -ENOMEM;
+
+ rcpm_suspend_ops.enter = rcpm_v2_suspend_enter;
+ } else {
+ rcpm_regs = of_iomap(np, 0);
+ if (!rcpm_regs)
+ return -ENOMEM;
+
+ rcpm_suspend_ops.enter = rcpm_suspend_enter;
+ }
suspend_set_ops(&rcpm_suspend_ops);
@@ -82,6 +127,7 @@ static int rcpm_probe(struct platform_device *pdev)
static const struct of_device_id rcpm_ids[] = {
{ .compatible = "fsl,qoriq-rcpm-1.0", },
+ { .compatible = "fsl,qoriq-rcpm-2.0", },
{ },
};
--
1.7.3
^ permalink raw reply related
* [PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500
From: Zhao Chenhui @ 2013-04-19 10:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
---
arch/powerpc/platforms/85xx/smp.c | 52 +++++++++++++++++++++++++++++++-----
1 files changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 74d8cde..5f3eee3 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -26,6 +26,7 @@
#include <asm/cacheflush.h>
#include <asm/dbell.h>
#include <asm/fsl_guts.h>
+#include <asm/cputhreads.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/mpic.h>
@@ -45,6 +46,7 @@ static u64 timebase;
static int tb_req;
static int tb_valid;
static u32 cur_booting_core;
+static bool rcpmv2;
#ifdef CONFIG_PPC_E500MC
/* get a physical mask of online cores and booting core */
@@ -53,26 +55,40 @@ static inline u32 get_phy_cpu_mask(void)
u32 mask;
int cpu;
- mask = 1 << cur_booting_core;
- for_each_online_cpu(cpu)
- mask |= 1 << get_hard_smp_processor_id(cpu);
+ if (smt_capable()) {
+ /* two threads in one core share one time base */
+ mask = 1 << cpu_core_index_of_thread(cur_booting_core);
+ for_each_online_cpu(cpu)
+ mask |= 1 << cpu_core_index_of_thread(
+ get_hard_smp_processor_id(cpu));
+ } else {
+ mask = 1 << cur_booting_core;
+ for_each_online_cpu(cpu)
+ mask |= 1 << get_hard_smp_processor_id(cpu);
+ }
return mask;
}
static void mpc85xx_timebase_freeze(int freeze)
{
- struct ccsr_rcpm __iomem *rcpm = guts_regs;
+ u32 *addr;
u32 mask = get_phy_cpu_mask();
+ if (rcpmv2)
+ addr = &((struct ccsr_rcpm_v2 *)guts_regs)->pctbenr;
+ else
+ addr = &((struct ccsr_rcpm *)guts_regs)->ctbenr;
+
if (freeze)
- clrbits32(&rcpm->ctbenr, mask);
+ clrbits32(addr, mask);
else
- setbits32(&rcpm->ctbenr, mask);
+ setbits32(addr, mask);
- /* read back to push the previos write */
- in_be32(&rcpm->ctbenr);
+ /* read back to push the previous write */
+ in_be32(addr);
}
+
#else
static void mpc85xx_timebase_freeze(int freeze)
{
@@ -94,6 +110,16 @@ static void mpc85xx_give_timebase(void)
{
unsigned long flags;
+#ifdef CONFIG_PPC_E500MC
+ /*
+ * If the booting thread is not the first thread of the core,
+ * skip time base sync.
+ */
+ if (smt_capable() &&
+ cur_booting_core != cpu_first_thread_sibling(cur_booting_core))
+ return;
+#endif
+
local_irq_save(flags);
while (!tb_req)
@@ -117,6 +143,12 @@ static void mpc85xx_take_timebase(void)
{
unsigned long flags;
+#ifdef CONFIG_PPC_E500MC
+ if (smt_capable() &&
+ cur_booting_core != cpu_first_thread_sibling(cur_booting_core))
+ return;
+#endif
+
local_irq_save(flags);
tb_req = 1;
@@ -457,6 +489,7 @@ static const struct of_device_id mpc85xx_smp_guts_ids[] = {
{ .compatible = "fsl,p1023-guts", },
{ .compatible = "fsl,p2020-guts", },
{ .compatible = "fsl,qoriq-rcpm-1.0", },
+ { .compatible = "fsl,qoriq-rcpm-2.0", },
{},
};
@@ -483,6 +516,9 @@ void __init mpc85xx_smp_init(void)
np = of_find_matching_node(NULL, mpc85xx_smp_guts_ids);
if (np) {
+ if (of_device_is_compatible(np, "fsl,qoriq-rcpm-2.0"))
+ rcpmv2 = true;
+
guts_regs = of_iomap(np, 0);
of_node_put(np);
if (!guts_regs) {
--
1.7.3
^ permalink raw reply related
* [PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
From: Roy Zang @ 2013-04-19 18:55 UTC (permalink / raw)
To: linuxppc-dev
setup_pci_atmu() only has one parameter and remove the extra one, or
build will fail due to un-match.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
---
arch/powerpc/sysdev/fsl_pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 40ffe29..f823304 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -978,7 +978,7 @@ static int fsl_pci_resume(struct device *dev)
return -ENODEV;
}
- setup_pci_atmu(hose, &pci_rsrc);
+ setup_pci_atmu(hose);
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH] powerpc/fsl-pci: fix setup_pci_atmu() parameter issue
From: Roy Zang @ 2013-04-19 18:58 UTC (permalink / raw)
To: Roy Zang; +Cc: linuxppc-dev
In-Reply-To: <1366397734-1416-1-git-send-email-tie-fei.zang@freescale.com>
On 04/20/2013 02:55 AM, Roy Zang wrote:
> setup_pci_atmu() only has one parameter and remove the extra one, or
> build will fail due to un-match.
>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> ---
>
based on Kumar's next branch.
Roy
^ permalink raw reply
* [PATCH] powerpc/rtas_flash: New return code to indicate FW entitlement expiry
From: Vasant Hegde @ 2013-04-19 11:44 UTC (permalink / raw)
To: benh, linuxppc-dev, paulus
Add new return code to rtas_flash to indicate firmware entitlement
expiry. This will be used by the update_flash script to return
appropriate message to the user.
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
arch/powerpc/kernel/rtas_flash.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index a7020d2..0a12c16 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -64,6 +64,7 @@
#define VALIDATE_TMP_COMMIT_DL 4 /* Validate Return Status */
#define VALIDATE_TMP_COMMIT 5 /* Validate Return Status */
#define VALIDATE_TMP_UPDATE_DL 6 /* Validate Return Status */
+#define VALIDATE_OUT_OF_WRNTY 7 /* Validate Return Status */
/* ibm,manage-flash-image operation tokens */
#define RTAS_REJECT_TMP_IMG 0
^ permalink raw reply related
* [PATCH RESEND] powerpc/rtas_flash: Free kmem upon module exit
From: Vasant Hegde @ 2013-04-19 11:48 UTC (permalink / raw)
To: benh, linuxppc-dev, paulus
Memory allocated to flash_block_list in rtas_flash_write
is not freed during module exit. We hit below call trace
if we unload rtas_flash module after loading new firmware
image and before rebooting the system.
Feb 6 08:42:10 eagle3 kernel: kmem_cache_destroy rtas_flash_cache: Slab cache still has objects
Feb 6 08:42:10 eagle3 kernel: Call Trace:
Feb 6 08:42:10 eagle3 kernel: [c00000001c303b40] [c000000000014940] .show_stack+0x70/0x1c0 (unreliable)
Feb 6 08:42:10 eagle3 kernel: [c00000001c303bf0] [c000000000199bec] .kmem_cache_destroy+0x15c/0x170
Feb 6 08:42:10 eagle3 kernel: [c00000001c303c90] [d000000006fa1208] .rtas_flash_cleanup+0x3c/0x80 [rtas_flash]
Feb 6 08:42:10 eagle3 kernel: [c00000001c303e30] [c000000000009954] syscall_exit+0x0/0x94
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
arch/powerpc/kernel/rtas_flash.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index c642f01..a7020d2 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -790,6 +790,11 @@ static void __exit rtas_flash_cleanup(void)
{
rtas_flash_term_hook = NULL;
+ if (rtas_firmware_flash_list) {
+ free_flash_list(rtas_firmware_flash_list);
+ rtas_firmware_flash_list = NULL;
+ }
+
if (flash_block_cache)
kmem_cache_destroy(flash_block_cache);
^ permalink raw reply related
* Re: [PATCH v7 3/3] of/pci: mips: convert to common of_pci_range_parser
From: Jason Cooper @ 2013-04-20 22:33 UTC (permalink / raw)
To: Gabor Juhos
Cc: linux-mips@linux-mips.org, siva.kallam@samsung.com,
linux-pci@vger.kernel.org, Linus Walleij, Thierry Reding,
Liviu Dudau, Paul Mackerras, linux-samsung-soc,
Russell King - ARM Linux, Jingoo Han, Jason Gunthorpe,
Thomas Abraham, Arnd Bergmann,
devicetree-discuss@lists.ozlabs.org, rob.herring@calxeda.com,
Kukjin Kim, bhelgaas@google.com,
linux-arm-kernel@lists.infradead.org, Thomas Petazzoni,
Michal Simek, linux-kernel@vger.kernel.org,
suren.reddy@samsung.com, Andrew Murray,
linuxppc-dev@lists.ozlabs.org list
In-Reply-To: <5170F016.6050502@openwrt.org>
On Fri, Apr 19, 2013 at 09:19:50AM +0200, Gabor Juhos wrote:
> 2013.04.18. 15:09 keltez=E9ssel, Jason Cooper =EDrta:
> > On Thu, Apr 18, 2013 at 01:59:10PM +0100, Andrew Murray wrote:
> >> On Wed, Apr 17, 2013 at 04:42:48PM +0100, Linus Walleij wrote:
> >>> On Tue, Apr 16, 2013 at 12:18 PM, Andrew Murray <Andrew.Murray@arm.=
com> wrote:
> >>>
> >>>> This patch converts the pci_load_of_ranges function to use the new=
common
> >>>> of_pci_range_parser.
> >>>>
> >>>> Signed-off-by: Andrew Murray <Andrew.Murray@arm.com>
> >>>> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
> >>>> Reviewed-by: Rob Herring <rob.herring@calxeda.com>
> >>>
> >>> Tested-by: Linus Walleij <linus.walleij@linaro.org>
> >>
> >> Jason - you may not have seen this, but here (Linus Walleij) is anot=
her Tested-by
> >> to add to this patch in your tree (if you can).
> >=20
> > Thanks, I saw it. Unfortunately, the PR was already sent, and the br=
anch
> > is now pulled into arm-soc.
>=20
> Sorry I had no time earlier, but I have tested this now on MIPS. The pa=
tch
> causes build errors unfortunately. Given the fact that this has been me=
rged
> already, I will send a fixup patch.
Olof has dropped this branch from arm-soc, plase post the build error
and fix here so that it can be included in this series.
thx,
Jason.
^ permalink raw reply
* Re: [PATCH v7 3/3] of/pci: mips: convert to common of_pci_range_parser
From: Gabor Juhos @ 2013-04-21 7:27 UTC (permalink / raw)
To: Jason Cooper
Cc: linux-mips@linux-mips.org, siva.kallam@samsung.com,
linux-pci@vger.kernel.org, Linus Walleij, Thierry Reding,
Liviu Dudau, Paul Mackerras, linux-samsung-soc,
Russell King - ARM Linux, Jingoo Han, Jason Gunthorpe,
Thomas Abraham, Arnd Bergmann,
devicetree-discuss@lists.ozlabs.org, rob.herring@calxeda.com,
Kukjin Kim, bhelgaas@google.com,
linux-arm-kernel@lists.infradead.org, Thomas Petazzoni,
Michal Simek, linux-kernel@vger.kernel.org,
suren.reddy@samsung.com, Andrew Murray,
linuxppc-dev@lists.ozlabs.org list
In-Reply-To: <20130420223343.GB25724@titan.lakedaemon.net>
Hi Jason,
>> Sorry I had no time earlier, but I have tested this now on MIPS. The patch
>> causes build errors unfortunately. Given the fact that this has been merged
>> already, I will send a fixup patch.
>
> Olof has dropped this branch from arm-soc, plase post the build error
> and fix here so that it can be included in this series.
I have posted the patch to Olof two days ago. It has been CC'd to you as well
but In case that it does not exists in your mailbox the patch can be found here:
https://patchwork.linux-mips.org/patch/5196/
However I can re-post the patch as a reply to this thread if you prefer that.
-Gabor
^ permalink raw reply
* Re: PROBLEM: Linux 3.6.2 fails to boot on IBM Cell
From: Dennis Schridde @ 2013-04-21 12:31 UTC (permalink / raw)
To: Grant Likely; +Cc: Thomas Gleixner, linuxppc-dev
In-Reply-To: <20121115175835.652C43E197F@localhost>
[-- Attachment #1.1: Type: text/plain, Size: 836 bytes --]
Hello all of you!
Am Donnerstag, 15. November 2012, 17:58:35 schrieb Grant Likely:
> Umm, no. Some suggestions were made so I assumed you'd try those.
>
> Anyway, here is a real patch. Try this:
>
> - for_each_node(node) {
> + for_each_online_node(node) {
I am running my 3.8.6 kernel with your patch now (will this be merged anytime
soon?), but I still get a bunch of irq mapping failed messages.
Examples:
[ 0.490734] irq: irq-93==>hwirq-0x5d mapping failed: -22
[ 22.016469] irq: no irq domain found for /axon@10000000000/plb5/pciex-
utl@a00000a000004000 !
Please see attached log.
In addition I see a weird issue: All programs run on CPU 0 (cores 0+1) only,
while CPU 1 (cores 2+3) is always idle. Could this have anything to do with
the IRQ issue, or shall I start a new thread/report for that?
Best regards,
Dennis
[-- Attachment #1.2: blade00-dmesg.log --]
[-- Type: text/x-log, Size: 60051 bytes --]
[ 0.000000] Allocated 20480 bytes for 32 pacas at c00000000fffb000
[ 0.000000] Using Cell machine description
[ 0.000000] Page orders: linear mapping = 24, virtual = 12, io = 12, vmemmap = 24
[ 0.000000] Found initrd at 0xc000000004265000:0xc000000004c22964
[ 0.000000] Found legacy serial port 0 for /axon@10000000000/plb5/plb4/opb/serial@40000200
[ 0.000000] mem=14540000200, taddr=14540000200, irq=0, clk=14745600, speed=19200
[ 0.000000] Found legacy serial port 1 for /axon@10000000000/plb5/plb4/opb/serial@40000300
[ 0.000000] mem=14540000300, taddr=14540000300, irq=0, clk=14745600, speed=115200
[ 0.000000] Found legacy serial port 2 for /axon@30000000000/plb5/plb4/opb/serial@40000200
[ 0.000000] mem=34540000200, taddr=34540000200, irq=0, clk=14745600, speed=-1
[ 0.000000] Found legacy serial port 3 for /axon@30000000000/plb5/plb4/opb/serial@40000300
[ 0.000000] mem=34540000300, taddr=34540000300, irq=0, clk=14745600, speed=-1
[ 0.000000] bootconsole [udbg0] enabled
[ 0.000000] CPU maps initialized for 2 threads per core
[ 0.000000] (thread shift is 1)
[ 0.000000] Freed 16384 bytes for unused pacas
[ 0.000000] Starting Linux PPC64 #1 SMP Tue Apr 16 10:08:12 CEST 2013
[ 0.000000] -----------------------------------------------------
[ 0.000000] ppc64_pft_size = 0x0
[ 0.000000] physicalMemorySize = 0x200000000
[ 0.000000] htab_address = 0xc000000078000000
[ 0.000000] htab_hash_mask = 0xfffff
[ 0.000000] -----------------------------------------------------
[ 0.000000] Linux version 3.8.6-aufs (root@blade00) (gcc version 4.7.2 (Gentoo 4.7.2-r1 p1.5, pie-0.5.5) ) #1 SMP Tue Apr 16 10:08:12 CEST 2013
[ 0.000000] *** 0000 : CF000012
[ 0.000000] *** 0000 : Setup Arch
[ 0.000000] [boot]0012 Setup Arch
[ 0.000000] Node 0 Memory: 0x0-0x100000000
[ 0.000000] Node 1 Memory: 0x100000000-0x200000000
[ 0.000000] mmio NVRAM, 1020k at 0x14502000000 mapped to d000080080008000
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x00000000-0x1ffffffff]
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x00000000-0xffffffff]
[ 0.000000] node 1: [mem 0x100000000-0x1ffffffff]
[ 0.000000] On node 0 totalpages: 1048576
[ 0.000000] DMA zone: 14336 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 1034240 pages, LIFO batch:31
[ 0.000000] On node 1 totalpages: 1048576
[ 0.000000] DMA zone: 14336 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 1034240 pages, LIFO batch:31
[ 0.000000] *** 0000 : CF000015
[ 0.000000] *** 0000 : Setup Done
[ 0.000000] [boot]0015 Setup Done
[ 0.000000] PERCPU: Embedded 11 pages/cpu @c000000000800000 s14848 r0 d30208 u262144
[ 0.000000] pcpu-alloc: s14848 r0 d30208 u262144 alloc=1*1048576
[ 0.000000] pcpu-alloc: [0] 0 1 2 3
[ 0.000000] Built 2 zonelists in Node order, mobility grouping on. Total pages: 2068480
[ 0.000000] Policy zone: DMA
[ 0.000000] Kernel command line: ksdevice=bootif lang= ip=eth0:dhcp root=nfs:192.168.100.1:/export/gentoo/root-ppc64 text
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] freeing bootmem node 0
[ 0.000000] freeing bootmem node 1
[ 0.000000] Memory: 8058732k/8388608k available (6164k kernel code, 329876k reserved, 676k data, 398k bss, 2072k init)
[ 0.000000] SLUB: Genslabs=15, HWalign=128, Order=0-3, MinObjects=0, CPUs=4, Nodes=256
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] RCU restricting CPUs from NR_CPUS=32 to nr_cpu_ids=4.
[ 0.000000] NR_IRQS:512 nr_irqs:512 16
[ 0.000000] IIC for CPU 0 target id 0xe : /be@20000000000/interrupt-controller@508400
[ 0.000000] IIC for CPU 1 target id 0xf : /be@20000000000/interrupt-controller@508400
[ 0.000000] IIC for CPU 2 target id 0x1e : /be@20100000000/interrupt-controller@508400
[ 0.000000] IIC for CPU 3 target id 0x1f : /be@20100000000/interrupt-controller@508400
[ 0.000000] mpic: Setting up MPIC " MPIC " version 1.2 at 0, max 4 CPUs
[ 0.000000] mpic: ISU size: 128, shift: 7, mask: 7f
[ 0.000000] mpic: Initializing for 128 sources
[ 0.000000] /axon@10000000000/interrupt-controller: hooking up to IRQ 43
[ 0.000000] mpic: Setting up MPIC " MPIC " version 1.2 at 0, max 4 CPUs
[ 0.000000] mpic: ISU size: 128, shift: 7, mask: 7f
[ 0.000000] mpic: Initializing for 128 sources
[ 0.000000] /axon@30000000000/interrupt-controller: hooking up to IRQ 299
[ 0.000000] time_init: decrementer frequency = 26.664333 MHz
[ 0.000000] time_init: processor frequency = 3200.000000 MHz
[ 0.000000] clocksource: timebase mult[2580d717] shift[24] registered
[ 0.000000] clockevent: decrementer mult[6d37946] shift[32] cpu[0]
[ 0.000000] Console: colour dummy device 80x25
[ 0.065086] pid_max: default: 32768 minimum: 301
[ 0.095333] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
[ 0.151126] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.198839] Mount-cache hash table entries: 256
[ 0.227727] Brought up 4 CPUs
[ 0.245016] Node 0 CPUs: 0-1
[ 0.245025] Node 1 CPUs: 2-3
[ 0.245668] devtmpfs: initialized
[ 0.316341] NET: Registered protocol family 16
[ 0.342793] iommu: node 0, dynamic window 0x0-0x80000000 fixed window 0x80000000-0x280000000
[ 0.344192] IOMMU: Using strong ordering for fixed mapping
[ 0.378559] IOMMU table initialized, virtual merging enabled
[ 0.412058] iommu: node 1, dynamic window 0x0-0x80000000 fixed window 0x80000000-0x280000000
[ 0.414287] IOMMU: Using strong ordering for fixed mapping
[ 0.468866] PCI: Probing PCI hardware
[ 0.490341] PCI: Probing PCI hardware done
[ 0.490734] irq: irq-93==>hwirq-0x5d mapping failed: -22
[ 0.522130] ------------[ cut here ]------------
[ 0.549706] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 0.591895] Modules linked in:
[ 0.610126] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 0.652317] REGS: c0000000fe667190 TRAP: 0700 Not tainted (3.8.6-aufs)
[ 0.692940] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 44000024 XER: 00000000
[ 0.739817] SOFTE: 1
[ 0.752840] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667410 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 0000000078e26d37 0000000000000008 0000000000000000
GPR08: 0000000078eef1c4 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 000000000000005e
GPR24: 0000000000000174 000000000000005d 000000000000005d c0000000fe65fc00
GPR28: c0000000fe006060 000000000000005d c000000000643be0 000000000000005d
[ 1.119009] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 1.159628] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 1.199731] Call Trace:
[ 1.214318] [c0000000fe667410] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 1.269528] [c0000000fe6674e0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 1.313801] [c0000000fe667580] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 1.359639] [c0000000fe667630] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 1.404429] [c0000000fe6676c0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 1.445057] [c0000000fe667750] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 1.488287] [c0000000fe667850] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 1.538810] [c0000000fe6678f0] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 1.585687] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 1.632564] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 1.678404] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 1.736219] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 1.779445] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 1.825281] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 1.865907] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 1.911738] Instruction dump:
[ 1.929448] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 1.975803] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 2.023213] ---[ end trace 093b23e74665976f ]---
[ 2.051302] irq: irq-59==>hwirq-0x3b mapping failed: -22
[ 2.082642] ------------[ cut here ]------------
[ 2.110236] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 2.152425] Modules linked in:
[ 2.170657] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 2.212846] REGS: c0000000fe666fb0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 2.259200] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 44000024 XER: 00000000
[ 2.306076] SOFTE: 1
[ 2.319100] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667230 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 000000007b5d549f 0000000000000008 0000000000000000
GPR08: 000000007b69dec9 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 000000000000003c
GPR24: 00000000000000ec 000000000000003b 000000000000003b c0000000fe803100
GPR28: c0000000fe006060 000000000000003b c000000000643be0 000000000000003b
[ 2.685263] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 2.725888] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 2.765991] Call Trace:
[ 2.780579] [c0000000fe667230] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 2.835789] [c0000000fe667300] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 2.880062] [c0000000fe6673a0] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 2.925896] [c0000000fe667450] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 2.970690] [c0000000fe6674e0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 3.011315] [c0000000fe667570] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 3.054548] [c0000000fe667670] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 3.105070] [c0000000fe667710] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 3.151946] [c0000000fe667800] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 3.198824] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 3.245701] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 3.292577] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 3.338414] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 3.396228] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 3.439457] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 3.485294] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 3.525921] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 3.571752] Instruction dump:
[ 3.589461] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 3.635817] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 3.683216] ---[ end trace 093b23e746659770 ]---
[ 3.711776] irq: irq-18==>hwirq-0x2 mapping failed: -22
[ 3.742608] ------------[ cut here ]------------
[ 3.770199] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 3.812387] Modules linked in:
[ 3.830618] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 3.872808] REGS: c0000000fe666ec0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 3.919162] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 44000024 XER: 00000000
[ 3.966038] SOFTE: 1
[ 3.979061] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667140 c000000000699cb0 000000000000002b
GPR04: 0000000000000000 000000007e00bb99 0000000000000008 0000000000000000
GPR08: 000000007e0d404e 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 0000000000000013
GPR24: 0000000000000008 0000000000000002 0000000000000012 c0000000fe803500
GPR28: c0000000fe006060 0000000000000012 c000000000643be0 0000000000000002
[ 4.345224] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 4.385850] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 4.425953] Call Trace:
[ 4.440540] [c0000000fe667140] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 4.495750] [c0000000fe667210] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 4.540023] [c0000000fe6672b0] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 4.585858] [c0000000fe667360] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 4.630651] [c0000000fe6673f0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 4.671277] [c0000000fe667480] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 4.714509] [c0000000fe667580] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 4.765032] [c0000000fe667620] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 4.811908] [c0000000fe667710] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 4.858786] [c0000000fe667800] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 4.905662] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 4.952539] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 4.999415] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 5.045253] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 5.103067] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 5.146297] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 5.192132] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 5.232760] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 5.278590] Instruction dump:
[ 5.296299] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 5.342655] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 5.390054] ---[ end trace 093b23e746659771 ]---
[ 5.419401] irq: irq-102==>hwirq-0x66 mapping failed: -22
[ 5.451267] ------------[ cut here ]------------
[ 5.478859] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 5.521048] Modules linked in:
[ 5.539279] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 5.581470] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 5.627823] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 5.674700] SOFTE: 1
[ 5.687723] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002d
GPR04: 0000000000000000 0000000080b79860 0000000000000008 0000000000000000
GPR08: 0000000080c47261 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 0000000000000067
GPR24: 0000000000000198 0000000000000066 0000000000000066 c0000000fe806f00
GPR28: c0000000fe006060 0000000000000066 c000000000643be0 0000000000000066
[ 6.053885] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 6.094512] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 6.134614] Call Trace:
[ 6.149201] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 6.204412] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 6.248684] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 6.294520] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 6.339313] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 6.379940] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 6.423171] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 6.473693] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 6.520570] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 6.567447] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 6.614324] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 6.660160] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 6.717975] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 6.761204] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 6.807039] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 6.847667] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 6.893498] Instruction dump:
[ 6.911208] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 6.957563] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 7.004962] ---[ end trace 093b23e746659772 ]---
[ 7.032744] irq: irq-110==>hwirq-0x6e mapping failed: -22
[ 7.064870] ------------[ cut here ]------------
[ 7.092465] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 7.134654] Modules linked in:
[ 7.152885] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 7.195074] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 7.241429] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 7.288306] SOFTE: 1
[ 7.301328] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002d
GPR04: 0000000000000000 0000000083483c8a 0000000000000008 0000000000000000
GPR08: 000000008354f799 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 000000000000006f
GPR24: 00000000000001b8 000000000000006e 000000000000006e c0000000fe806f00
GPR28: c0000000fe006060 000000000000006e c000000000643be0 000000000000006e
[ 7.667491] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 7.708117] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 7.748219] Call Trace:
[ 7.762807] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 7.818018] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 7.862290] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 7.908125] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 7.952918] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 7.993545] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 8.036776] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 8.087299] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 8.134175] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 8.181053] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 8.227929] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 8.273765] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 8.331580] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 8.374810] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 8.420646] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 8.461272] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 8.507103] Instruction dump:
[ 8.524813] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 8.571169] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 8.618568] ---[ end trace 093b23e746659773 ]---
[ 8.646369] irq: irq-39==>hwirq-0x27 mapping failed: -22
[ 8.677955] ------------[ cut here ]------------
[ 8.705551] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 8.747738] Modules linked in:
[ 8.765970] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 8.808160] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 8.854513] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 8.901390] SOFTE: 1
[ 8.914413] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 0000000085d8c1ca 0000000000000008 0000000000000000
GPR08: 0000000085e54682 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000000fe006078 0000000000000028
GPR24: 000000000000009c 0000000000000027 0000000000000027 c0000000fe807000
GPR28: c0000000fe006060 0000000000000027 c000000000643be0 0000000000000027
[ 9.280577] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 9.321202] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 9.361304] Call Trace:
[ 9.375891] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 9.431102] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 9.475374] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 9.521210] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 9.566002] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 9.606630] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 9.649861] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 9.700383] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 9.747260] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 9.794137] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 9.841014] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 9.886851] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 9.944665] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 9.987895] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 10.033731] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 10.074357] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 10.120188] Instruction dump:
[ 10.137898] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 10.184254] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 10.231652] ---[ end trace 093b23e746659774 ]---
[ 10.259697] irq: irq-93==>hwirq-0x5d mapping failed: -22
[ 10.291040] ------------[ cut here ]------------
[ 10.318635] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 10.360823] Modules linked in:
[ 10.379055] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 10.421245] REGS: c0000000fe667190 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 10.467599] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 10.514475] SOFTE: 1
[ 10.527498] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667410 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 00000000886910b7 0000000000000008 0000000000000000
GPR08: 0000000088759576 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 000000000000005e
GPR24: 0000000000000174 000000000000005d 000000000000005d c0000001fe743100
GPR28: c0000001fe001000 000000000000005d c000000000643be0 000000000000005d
[ 10.893662] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 10.934287] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 10.974389] Call Trace:
[ 10.988976] [c0000000fe667410] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 11.044187] [c0000000fe6674e0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 11.088460] [c0000000fe667580] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 11.134294] [c0000000fe667630] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 11.179088] [c0000000fe6676c0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 11.219715] [c0000000fe667750] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 11.262946] [c0000000fe667850] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 11.313468] [c0000000fe6678f0] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 11.360346] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 11.407222] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 11.453058] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 11.510873] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 11.554103] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 11.599938] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 11.640565] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 11.686396] Instruction dump:
[ 11.704106] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 11.750461] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 11.797861] ---[ end trace 093b23e746659775 ]---
[ 11.825985] irq: irq-59==>hwirq-0x3b mapping failed: -22
[ 11.857353] ------------[ cut here ]------------
[ 11.884947] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 11.927135] Modules linked in:
[ 11.945367] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 11.987557] REGS: c0000000fe666fb0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 12.033911] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 12.080787] SOFTE: 1
[ 12.093810] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667230 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 000000008ae64d23 0000000000000008 0000000000000000
GPR08: 000000008af2dcbb 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 000000000000003c
GPR24: 00000000000000ec 000000000000003b 000000000000003b c0000001fe743600
GPR28: c0000001fe001000 000000000000003b c000000000643be0 000000000000003b
[ 12.459974] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 12.500599] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 12.540701] Call Trace:
[ 12.555288] [c0000000fe667230] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 12.610499] [c0000000fe667300] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 12.654772] [c0000000fe6673a0] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 12.700607] [c0000000fe667450] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 12.745400] [c0000000fe6674e0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 12.786027] [c0000000fe667570] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 12.829258] [c0000000fe667670] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 12.879780] [c0000000fe667710] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 12.926658] [c0000000fe667800] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 12.973534] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 13.020411] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 13.067288] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 13.113125] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 13.170939] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 13.214169] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 13.260005] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 13.300631] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 13.346462] Instruction dump:
[ 13.364172] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 13.410527] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 13.457926] ---[ end trace 093b23e746659776 ]---
[ 13.486091] irq: irq-20==>hwirq-0x2 mapping failed: -22
[ 13.516898] ------------[ cut here ]------------
[ 13.544492] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 13.586680] Modules linked in:
[ 13.604912] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 13.647101] REGS: c0000000fe666ec0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 13.693456] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 13.740333] SOFTE: 1
[ 13.753356] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667140 c000000000699cb0 000000000000002b
GPR04: 0000000000000000 000000008d89b97c 0000000000000008 0000000000000000
GPR08: 000000008d9612d7 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 0000000000000015
GPR24: 0000000000000008 0000000000000002 0000000000000014 c0000001fe743900
GPR28: c0000001fe001000 0000000000000014 c000000000643be0 0000000000000002
[ 14.119519] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 14.160144] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 14.200246] Call Trace:
[ 14.214833] [c0000000fe667140] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 14.270044] [c0000000fe667210] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 14.314317] [c0000000fe6672b0] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 14.360152] [c0000000fe667360] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 14.404945] [c0000000fe6673f0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 14.445571] [c0000000fe667480] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 14.488802] [c0000000fe667580] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 14.539325] [c0000000fe667620] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 14.586202] [c0000000fe667710] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 14.633079] [c0000000fe667800] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 14.679956] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 14.726833] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 14.773710] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 14.819546] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 14.877361] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 14.920591] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 14.966426] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 15.007053] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 15.052885] Instruction dump:
[ 15.070594] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 15.116950] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 15.164348] ---[ end trace 093b23e746659777 ]---
[ 15.193877] irq: irq-108==>hwirq-0x66 mapping failed: -22
[ 15.225769] ------------[ cut here ]------------
[ 15.253363] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 15.295550] Modules linked in:
[ 15.313782] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 15.355972] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 15.402326] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 15.449202] SOFTE: 1
[ 15.462226] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002d
GPR04: 0000000000000000 0000000090406ac4 0000000000000008 0000000000000000
GPR08: 00000000904d5a9f 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 000000000000006d
GPR24: 0000000000000198 0000000000000066 000000000000006c c0000001fe74c400
GPR28: c0000001fe001000 000000000000006c c000000000643be0 0000000000000066
[ 15.828389] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 15.869013] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 15.909117] Call Trace:
[ 15.923704] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 15.978914] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 16.023187] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 16.069022] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 16.113814] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 16.154441] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 16.197673] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 16.248196] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 16.295072] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 16.341949] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 16.388826] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 16.434662] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 16.492476] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 16.535707] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 16.581542] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 16.622168] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 16.668000] Instruction dump:
[ 16.685710] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 16.732066] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 16.779464] ---[ end trace 093b23e746659778 ]---
[ 16.807242] irq: irq-110==>hwirq-0x6e mapping failed: -22
[ 16.839373] ------------[ cut here ]------------
[ 16.866968] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 16.909155] Modules linked in:
[ 16.927387] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 16.969576] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 17.015931] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 17.062808] SOFTE: 1
[ 17.075831] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002d
GPR04: 0000000000000000 0000000092d124ca 0000000000000008 0000000000000000
GPR08: 0000000092dddfc6 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 000000000000006f
GPR24: 00000000000001b8 000000000000006e 000000000000006e c0000001fe74c400
GPR28: c0000001fe001000 000000000000006e c000000000643be0 000000000000006e
[ 17.441994] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 17.482619] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 17.522722] Call Trace:
[ 17.537310] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 17.592520] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 17.636792] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 17.682627] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 17.727421] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 17.768047] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 17.811278] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 17.861801] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 17.908678] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 17.955555] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 18.002431] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 18.048268] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 18.106082] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 18.149312] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 18.195148] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 18.235775] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 18.281606] Instruction dump:
[ 18.299315] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 18.345671] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 18.393070] ---[ end trace 093b23e746659779 ]---
[ 18.420872] irq: irq-42==>hwirq-0x27 mapping failed: -22
[ 18.452457] ------------[ cut here ]------------
[ 18.480052] WARNING: at /usr/src/linux-3.8.6-aufs/kernel/irq/irqdomain.c:467
[ 18.522241] Modules linked in:
[ 18.540472] NIP: c0000000000bdeac LR: c0000000000bdea8 CTR: c000000000025670
[ 18.582662] REGS: c0000000fe6670a0 TRAP: 0700 Tainted: G W (3.8.6-aufs)
[ 18.629016] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 84000024 XER: 00000000
[ 18.675893] SOFTE: 1
[ 18.688916] TASK = c0000000fe668000[1] 'swapper/0' THREAD: c0000000fe664000 CPU: 0
GPR00: c0000000000bdea8 c0000000fe667320 c000000000699cb0 000000000000002c
GPR04: 0000000000000000 000000009561a9f3 0000000000000008 0000000000000000
GPR08: 00000000956e2ec4 0000000000000000 0000000000000000 0000000000000000
GPR12: d000070000000000 c00000000fffb000 c00000000000a460 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 c0000001fe001018 000000000000002b
GPR24: 000000000000009c 0000000000000027 000000000000002a c0000001fe74c500
GPR28: c0000001fe001000 000000000000002a c000000000643be0 0000000000000027
[ 19.055078] NIP [c0000000000bdeac] .irq_domain_associate_many+0x264/0x290
[ 19.095704] LR [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290
[ 19.135807] Call Trace:
[ 19.150394] [c0000000fe667320] [c0000000000bdea8] .irq_domain_associate_many+0x260/0x290 (unreliable)
[ 19.205604] [c0000000fe6673f0] [c0000000000be928] .irq_create_mapping+0xc8/0x1d0
[ 19.249876] [c0000000fe667490] [c0000000000bead8] .irq_create_of_mapping+0xa8/0x170
[ 19.295712] [c0000000fe667540] [c000000000290c30] .irq_of_parse_and_map+0x40/0x58
[ 19.340505] [c0000000fe6675d0] [c000000000290df0] .of_irq_count+0x30/0x58
[ 19.381131] [c0000000fe667660] [c00000000029182c] .of_device_alloc+0x1ec/0x288
[ 19.424363] [c0000000fe667760] [c00000000029191c] .of_platform_device_create_pdata+0x54/0xf8
[ 19.474886] [c0000000fe667800] [c000000000291b04] .of_platform_bus_create+0x144/0x1e0
[ 19.521763] [c0000000fe6678f0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 19.568640] [c0000000fe6679e0] [c000000000291b60] .of_platform_bus_create+0x1a0/0x1e0
[ 19.615516] [c0000000fe667ad0] [c000000000291d50] .of_platform_bus_probe+0xd0/0x140
[ 19.661353] [c0000000fe667b70] [c0000000004109e4] .__machine_initcall_cell_cell_publish_devices+0x54/0x1b0
[ 19.719167] [c0000000fe667c40] [c000000000009e70] .do_one_initcall+0x168/0x1d0
[ 19.762397] [c0000000fe667d00] [c0000000003ffb6c] .kernel_init_freeable+0x14c/0x21c
[ 19.808233] [c0000000fe667db0] [c00000000000a47c] .kernel_init+0x1c/0x108
[ 19.848859] [c0000000fe667e30] [c000000000008cd8] .ret_from_kernel_thread+0x64/0x8c
[ 19.894691] Instruction dump:
[ 19.912401] 7fa4eb78 7ca507b4 4828c965 60000000 0fe00000 3860ffea 4bffff80 e87e8020
[ 19.958756] 7fa4eb78 7fe5fb78 4828c945 60000000 <0fe00000> 39200000 7f83e378 7f44d378
[ 20.006154] ---[ end trace 093b23e74665977a ]---
[ 20.033998] iommu: missing iommu for <no-node> (node -1)
[ 20.065580] iommu: missing iommu for <no-node> (node -1)
[ 20.097448] axon_msi: setup MSIC on /axon@10000000000/plb5/msic@4000004400003000
[ 20.097647] axon_msi: setup MSIC on /axon@30000000000/plb5/msic@4000004400003000
[ 20.098925] bio: create slab <bio-0> at 0
[ 20.122808] vgaarb: loaded
[ 20.138920] Switching to clocksource timebase
[ 20.171194] NET: Registered protocol family 2
[ 20.197448] TCP established hash table entries: 65536 (order: 8, 1048576 bytes)
[ 20.242041] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[ 20.284006] TCP: Hash tables configured (established 65536 bind 65536)
[ 20.322737] TCP: reno registered
[ 20.341968] UDP hash table entries: 4096 (order: 5, 131072 bytes)
[ 20.378547] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
[ 20.417767] PCI: CLS 0 bytes, default 128
[ 20.417908] Unpacking initramfs...
[ 20.998378] Freeing initrd memory: 9976k freed
[ 21.026844] iommu: missing iommu for <no-node> (node -1)
[ 21.058400] Setting up PCI bus /axon@10000000000/plb5/plb4/pcix@4000004600000000
[ 21.102499] PCI host bridge /axon@10000000000/plb5/plb4/pcix@4000004600000000 ranges:
[ 21.149865] IO 0x0000014608000000..0x000001460800ffff -> 0x0000000000000000
[ 21.192573] MEM 0x0000014780000000..0x00000147bfffffff -> 0x0000000080000000
[ 21.235804] MEM 0x00000147c0000000..0x00000147ffffffff -> 0x00000000c0000000 Prefetch
[ 21.283303] of-pci 14600000000.pcix: PCI host bridge to bus 0000:00
[ 21.320704] pci_bus 0000:00: root bus resource [io 0x10000-0x1ffff] (bus address [0x0000-0xffff])
[ 21.374351] pci_bus 0000:00: root bus resource [mem 0x14780000000-0x147bfffffff] (bus address [0x80000000-0xbfffffff])
[ 21.438415] pci_bus 0000:00: root bus resource [mem 0x147c0000000-0x147ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 21.505081] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 21.537895] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to ff
[ 21.537995] pci 0000:00:01.0: [14e4:16a8] type 00 class 0x020000
[ 21.538100] pci 0000:00:01.0: reg 10: [mem 0x14780000000-0x1478000ffff 64bit]
[ 21.538535] pci 0000:00:01.0: PME# supported from D3hot D3cold
[ 21.538676] pci 0000:00:01.1: [14e4:16a8] type 00 class 0x020000
[ 21.538785] pci 0000:00:01.1: reg 10: [mem 0x14780010000-0x1478001ffff 64bit]
[ 21.539213] pci 0000:00:01.1: PME# supported from D3hot D3cold
[ 21.539379] pci_bus 0000:00: busn_res: [bus 00-ff] end is updated to 00
[ 21.539606] Setting up PCI bus /axon@10000000000/plb5/pciex@a00000a000000000
[ 21.581406] PCI host bridge /axon@10000000000/plb5/pciex@a00000a000000000 ranges:
[ 21.626704] IO 0x000001a100000000..0x000001a10000ffff -> 0x0000000000000000
[ 21.669416] MEM 0x000001c080000000..0x000001c0bfffffff -> 0x0000000080000000
[ 21.712642] MEM 0x000001c0c0000000..0x000001c0ffffffff -> 0x00000000c0000000 Prefetch
[ 21.760128] of-pci D18000002400.pciex: PCI host bridge to bus 0001:00
[ 21.798585] pci_bus 0001:00: root bus resource [io 0x21000-0x30fff] (bus address [0x0000-0xffff])
[ 21.852232] pci_bus 0001:00: root bus resource [mem 0x1c080000000-0x1c0bfffffff] (bus address [0x80000000-0xbfffffff])
[ 21.916296] pci_bus 0001:00: root bus resource [mem 0x1c0c0000000-0x1c0ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 21.982968] pci_bus 0001:00: root bus resource [bus 00-ff]
[ 22.015778] pci_bus 0001:00: busn_res: [bus 00-ff] end is updated to ff
[ 22.015874] pci 0001:00:00.0: [1014:032c] type 01 class 0x060400
[ 22.015969] pci 0001:00:00.0: reg 10: [mem 0x00000000-0x7fffffff 64bit pref]
[ 22.016023] pci 0001:00:00.0: reg 38: [mem 0x1c0ffff8000-0x1c0ffffffff pref]
[ 22.016091] PCI: Hiding resources on Axon PCIE RC 0001:00:00.0
[ 22.016322] pci 0001:00:00.0: supports D1 D2
[ 22.016329] pci 0001:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 22.016469] irq: no irq domain found for /axon@10000000000/plb5/pciex-utl@a00000a000004000 !
[ 22.066811] pci 0001:00:00.0: PCI bridge to [bus 01]
[ 22.096348] pci_bus 0001:00: busn_res: [bus 00-ff] end is updated to 01
[ 22.096492] Setting up PCI bus /axon@10000000000/plb5/pciex@a00000a200000000
[ 22.138454] PCI host bridge /axon@10000000000/plb5/pciex@a00000a200000000 ranges:
[ 22.183757] IO 0x000001a300000000..0x000001a30000ffff -> 0x0000000000000000
[ 22.226467] MEM 0x000001d080000000..0x000001d0bfffffff -> 0x0000000080000000
[ 22.269700] MEM 0x000001d0c0000000..0x000001d0ffffffff -> 0x00000000c0000000 Prefetch
[ 22.317183] of-pci D18000002800.pciex: PCI host bridge to bus 0002:00
[ 22.355637] pci_bus 0002:00: root bus resource [io 0x32000-0x41fff] (bus address [0x0000-0xffff])
[ 22.409286] pci_bus 0002:00: root bus resource [mem 0x1d080000000-0x1d0bfffffff] (bus address [0x80000000-0xbfffffff])
[ 22.473351] pci_bus 0002:00: root bus resource [mem 0x1d0c0000000-0x1d0ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 22.540019] pci_bus 0002:00: root bus resource [bus 00-ff]
[ 22.572831] pci_bus 0002:00: busn_res: [bus 00-ff] end is updated to ff
[ 22.572925] pci 0002:00:00.0: [1014:032c] type 01 class 0x060400
[ 22.573019] pci 0002:00:00.0: reg 10: [mem 0x00000000-0x7fffffff 64bit pref]
[ 22.573072] pci 0002:00:00.0: reg 38: [mem 0x1d0ffff8000-0x1d0ffffffff pref]
[ 22.573139] PCI: Hiding resources on Axon PCIE RC 0002:00:00.0
[ 22.573370] pci 0002:00:00.0: supports D1 D2
[ 22.573377] pci 0002:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 22.573513] irq: no irq domain found for /axon@10000000000/plb5/pciex-utl@a00000a200004000 !
[ 22.623873] pci 0002:00:00.0: PCI bridge to [bus 01]
[ 22.653403] pci_bus 0002:00: busn_res: [bus 00-ff] end is updated to 01
[ 22.653571] Setting up PCI bus /axon@30000000000/plb5/plb4/pcix@4000004600000000
[ 22.697598] PCI host bridge /axon@30000000000/plb5/plb4/pcix@4000004600000000 ranges:
[ 22.744978] IO 0x0000034608000000..0x000003460800ffff -> 0x0000000000000000
[ 22.787688] MEM 0x0000034780000000..0x00000347bfffffff -> 0x0000000080000000
[ 22.830920] MEM 0x00000347c0000000..0x00000347ffffffff -> 0x00000000c0000000 Prefetch
[ 22.878412] of-pci 34600000000.pcix: PCI host bridge to bus 0003:00
[ 22.915816] pci_bus 0003:00: root bus resource [io 0x43000-0x52fff] (bus address [0x0000-0xffff])
[ 22.969462] pci_bus 0003:00: root bus resource [mem 0x34780000000-0x347bfffffff] (bus address [0x80000000-0xbfffffff])
[ 23.033529] pci_bus 0003:00: root bus resource [mem 0x347c0000000-0x347ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 23.100200] pci_bus 0003:00: root bus resource [bus 00-ff]
[ 23.133010] pci_bus 0003:00: busn_res: [bus 00-ff] end is updated to ff
[ 23.133069] pci 0003:00:01.0: [1033:0035] type 00 class 0x0c0310
[ 23.133151] pci 0003:00:01.0: reg 10: [mem 0x34780000000-0x34780000fff]
[ 23.133512] pci 0003:00:01.0: supports D1 D2
[ 23.133520] pci 0003:00:01.0: PME# supported from D0 D1 D2 D3hot
[ 23.133611] pci 0003:00:01.1: [1033:0035] type 00 class 0x0c0310
[ 23.133691] pci 0003:00:01.1: reg 10: [mem 0x34780001000-0x34780001fff]
[ 23.134068] pci 0003:00:01.1: supports D1 D2
[ 23.134076] pci 0003:00:01.1: PME# supported from D0 D1 D2 D3hot
[ 23.134167] pci 0003:00:01.2: [1033:00e0] type 00 class 0x0c0320
[ 23.134247] pci 0003:00:01.2: reg 10: [mem 0x34780002000-0x347800020ff]
[ 23.134605] pci 0003:00:01.2: supports D1 D2
[ 23.134612] pci 0003:00:01.2: PME# supported from D0 D1 D2 D3hot
[ 23.134776] pci_bus 0003:00: busn_res: [bus 00-ff] end is updated to 00
[ 23.236836] pci 0003:00:01.2: enabling device (0140 -> 0142)
[ 23.270411] Setting up PCI bus /axon@30000000000/plb5/pciex@a00000a000000000
[ 23.312464] PCI host bridge /axon@30000000000/plb5/pciex@a00000a000000000 ranges:
[ 23.357765] IO 0x000003a100000000..0x000003a10000ffff -> 0x0000000000000000
[ 23.400470] MEM 0x000003c080000000..0x000003c0bfffffff -> 0x0000000080000000
[ 23.443702] MEM 0x000003c0c0000000..0x000003c0ffffffff -> 0x00000000c0000000 Prefetch
[ 23.491188] of-pci D38000002400.pciex: PCI host bridge to bus 0004:00
[ 23.529643] pci_bus 0004:00: root bus resource [io 0x54000-0x63fff] (bus address [0x0000-0xffff])
[ 23.583289] pci_bus 0004:00: root bus resource [mem 0x3c080000000-0x3c0bfffffff] (bus address [0x80000000-0xbfffffff])
[ 23.647356] pci_bus 0004:00: root bus resource [mem 0x3c0c0000000-0x3c0ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 23.714024] pci_bus 0004:00: root bus resource [bus 00-ff]
[ 23.746836] pci_bus 0004:00: busn_res: [bus 00-ff] end is updated to ff
[ 23.746935] pci 0004:00:00.0: [1014:032c] type 01 class 0x060400
[ 23.747035] pci 0004:00:00.0: reg 10: [mem 0x00000000-0x7fffffff 64bit pref]
[ 23.747093] pci 0004:00:00.0: reg 38: [mem 0x3c0ffff8000-0x3c0ffffffff pref]
[ 23.747163] PCI: Hiding resources on Axon PCIE RC 0004:00:00.0
[ 23.747409] pci 0004:00:00.0: supports D1 D2
[ 23.747416] pci 0004:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 23.747563] irq: no irq domain found for /axon@30000000000/plb5/pciex-utl@a00000a000004000 !
[ 23.797937] pci 0004:00:00.0: PCI bridge to [bus 01]
[ 23.827465] pci_bus 0004:00: busn_res: [bus 00-ff] end is updated to 01
[ 23.827605] Setting up PCI bus /axon@30000000000/plb5/pciex@a00000a200000000
[ 23.869564] PCI host bridge /axon@30000000000/plb5/pciex@a00000a200000000 ranges:
[ 23.914870] IO 0x000003a300000000..0x000003a30000ffff -> 0x0000000000000000
[ 23.957576] MEM 0x000003d080000000..0x000003d0bfffffff -> 0x0000000080000000
[ 24.000807] MEM 0x000003d0c0000000..0x000003d0ffffffff -> 0x00000000c0000000 Prefetch
[ 24.048303] of-pci D38000002800.pciex: PCI host bridge to bus 0005:00
[ 24.086747] pci_bus 0005:00: root bus resource [io 0x65000-0x74fff] (bus address [0x0000-0xffff])
[ 24.140395] pci_bus 0005:00: root bus resource [mem 0x3d080000000-0x3d0bfffffff] (bus address [0x80000000-0xbfffffff])
[ 24.204462] pci_bus 0005:00: root bus resource [mem 0x3d0c0000000-0x3d0ffffffff pref] (bus address [0xc0000000-0xffffffff])
[ 24.271129] pci_bus 0005:00: root bus resource [bus 00-ff]
[ 24.303941] pci_bus 0005:00: busn_res: [bus 00-ff] end is updated to ff
[ 24.304047] pci 0005:00:00.0: [1014:032c] type 01 class 0x060400
[ 24.304146] pci 0005:00:00.0: reg 10: [mem 0x00000000-0x7fffffff 64bit pref]
[ 24.304203] pci 0005:00:00.0: reg 38: [mem 0x3d0ffff8000-0x3d0ffffffff pref]
[ 24.304272] PCI: Hiding resources on Axon PCIE RC 0005:00:00.0
[ 24.304517] pci 0005:00:00.0: supports D1 D2
[ 24.304524] pci 0005:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 24.304664] irq: no irq domain found for /axon@30000000000/plb5/pciex-utl@a00000a200004000 !
[ 24.355200] pci 0005:01:00.0: [15b3:634a] type 00 class 0x0c0600
[ 24.355378] pci 0005:01:00.0: reg 10: [mem 0x3d080000000-0x3d0800fffff 64bit]
[ 24.355524] pci 0005:01:00.0: reg 18: [mem 0x3d0c0000000-0x3d0c1ffffff 64bit pref]
[ 24.356526] pci 0005:00:00.0: PCI bridge to [bus 01]
[ 24.385809] pci 0005:00:00.0: bridge window [mem 0x3d080000000-0x3d0800fffff]
[ 24.385844] pci 0005:00:00.0: bridge window [mem 0x3d0c0000000-0x3d0c1ffffff 64bit pref]
[ 24.385934] pci_bus 0005:00: busn_res: [bus 00-ff] end is updated to 01
[ 24.386274] iommu: missing iommu for <no-node> (node -1)
[ 24.423030] iommu: missing iommu for <no-node> (node -1)
[ 24.463050] msgmni has been set to 15888
[ 24.500072] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[ 24.543980] io scheduler noop registered
[ 24.567417] io scheduler deadline registered
[ 24.593225] io scheduler cfq registered (default)
[ 24.664957] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 24.702646] iommu: missing iommu for <no-node> (node -1)
[ 24.756219] serial8250.0: ttyS0 at MMIO 0x14540000200 (irq = 16) is a U6_16550A
[ 24.799650] console [ttyS0] enabled, bootconsole disabled
[ 24.885615] serial8250.0: ttyS1 at MMIO 0x14540000300 (irq = 17) is a U6_16550A
[ 24.950843] serial8250.0: ttyS2 at MMIO 0x34540000200 (irq = 18) is a U6_16550A
[ 25.016425] serial8250.0: ttyS3 at MMIO 0x34540000300 (irq = 19) is a U6_16550A
[ 25.061120] mousedev: PS/2 mouse device common for all mice
[ 25.094572] cpuidle: using governor ladder
[ 25.119166] cpuidle: using governor menu
[ 25.143019] TCP: cubic registered
[ 25.162962] Key type dns_resolver registered
[ 25.191007] /usr/src/linux-3.8.6-aufs/drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
[ 25.246286] Freeing unused kernel memory: 2072k freed
[ 25.598515] dracut: dracut-027-ebfd8cd
[ 25.870831] RPC: Registered named UNIX socket transport module.
[ 25.906410] RPC: Registered udp transport module.
[ 25.934647] RPC: Registered tcp transport module.
[ 25.962878] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 26.060180] NET: Registered protocol family 1
[ 26.128272] NET: Registered protocol family 10
[ 26.288658] systemd-udevd[143]: starting version 200
[ 26.565854] pps_core: LinuxPPS API ver. 1 registered
[ 26.595737] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 26.657618] PTP clock support registered
[ 26.720952] tg3.c:v3.128 (December 03, 2012)
[ 26.746875] tg3 0000:00:01.0: enabling device (0140 -> 0142)
[ 26.812886] tg3 0000:00:01.0 eth0: Tigon3 [partno(none) rev 2100] (PCIX:100MHz:64-bit) MAC address 00:1a:64:b8:08:18
[ 26.876142] tg3 0000:00:01.0 eth0: attached PHY is serdes (1000Base-SX Ethernet) (WireSpeed[0], EEE[0])
[ 26.932674] tg3 0000:00:01.0 eth0: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[1] TSOcap[0]
[ 26.942744] usbcore: registered new interface driver usbfs
[ 26.942899] usbcore: registered new interface driver hub
[ 27.044642] tg3 0000:00:01.0 eth0: dma_rwctrl[769f4000] dma_mask[64-bit]
[ 27.085684] usbcore: registered new device driver usb
[ 27.101276] tg3 0000:00:01.1: enabling device (0140 -> 0142)
[ 27.110440] tg3 0000:00:01.1 eth1: Tigon3 [partno(none) rev 2100] (PCIX:100MHz:64-bit) MAC address 00:1a:64:b8:08:19
[ 27.110454] tg3 0000:00:01.1 eth1: attached PHY is serdes (1000Base-SX Ethernet) (WireSpeed[0], EEE[0])
[ 27.110467] tg3 0000:00:01.1 eth1: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
[ 27.110479] tg3 0000:00:01.1 eth1: dma_rwctrl[769f4000] dma_mask[64-bit]
[ 27.371083] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 27.413388] ehci-pci: EHCI PCI platform driver
[ 27.444298] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 27.483890] ehci-pci 0003:00:01.2: EHCI Host Controller
[ 27.515594] ehci-pci 0003:00:01.2: new USB bus registered, assigned bus number 1
[ 27.561329] ehci-pci 0003:00:01.2: irq 21, io mem 0x34780002000
[ 27.602979] ehci-pci 0003:00:01.2: USB 2.0 started, EHCI 1.00
[ 27.639547] hub 1-0:1.0: USB hub found
[ 27.662086] hub 1-0:1.0: 5 ports detected
[ 27.687335] ohci_hcd 0003:00:01.0: OHCI Host Controller
[ 27.718695] ohci_hcd 0003:00:01.0: new USB bus registered, assigned bus number 2
[ 27.763128] ohci_hcd 0003:00:01.0: irq 21, io mem 0x34780000000
[ 27.879080] hub 2-0:1.0: USB hub found
[ 27.901608] hub 2-0:1.0: 3 ports detected
[ 27.926261] ohci_hcd 0003:00:01.1: OHCI Host Controller
[ 27.957619] ohci_hcd 0003:00:01.1: new USB bus registered, assigned bus number 3
[ 27.957668] ohci_hcd 0003:00:01.1: irq 21, io mem 0x34780001000
[ 28.037674] hub 3-0:1.0: USB hub found
[ 28.037699] hub 3-0:1.0: 2 ports detected
[ 28.932303] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 28.995421] NET: Registered protocol family 17
[ 29.935487] tg3 0000:00:01.0 eth0: Link is up at 1000 Mbps, full duplex
[ 29.975345] tg3 0000:00:01.0 eth0: Flow control is on for TX and on for RX
[ 30.017138] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[ 33.536157] FS-Cache: Loaded
[ 33.579120] FS-Cache: Netfs 'nfs' registered for caching
[ 33.644356] NFS: Registering the id_resolver key type
[ 33.674914] Key type id_resolver registered
[ 33.700043] Key type id_legacy registered
[ 34.603362] dracut: Mounted root filesystem 192.168.100.1:/export/gentoo/root-ppc64
[ 35.043969] dracut: Switching root
[ 36.916516] systemd-udevd[375]: starting version 200
[ 37.676340] systemd-udevd[387]: renamed network interface eth1 to enp0s1f1
[ 37.906905] rtc-generic rtc-generic: rtc core: registered rtc-generic as rtc0
[ 37.980118] mlx4_core: Mellanox ConnectX core driver v1.1 (Dec, 2011)
[ 37.980232] mlx4_core: Initializing 0005:01:00.0
[ 37.980484] mlx4_core 0005:01:00.0: enabling device (0140 -> 0142)
[ 43.360940] mlx4_core 0005:01:00.0: command 0xc failed: fw status = 0x40
[ 43.361874] mlx4_core 0005:01:00.0: command 0xc failed: fw status = 0x40
[ 45.330025] <mlx4_ib> mlx4_ib_add: mlx4_ib: Mellanox ConnectX InfiniBand driver v1.0 (April 4, 2008)
[ 54.036776] mlx4_core 0005:01:00.0: command 0x5a failed: fw status = 0x2
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply
* [PATCH] ptrace/powerpc: dont flush_ptrace_hw_breakpoint() on fork()
From: Oleg Nesterov @ 2013-04-21 16:47 UTC (permalink / raw)
To: Michael Neuling, Benjamin Herrenschmidt, Paul Mackerras
Cc: linuxppc-dev, linux-kernel
arch_dup_task_struct() does flush_ptrace_hw_breakpoint(src), this
destroys the parent's breakpoints for no reason. We should clear
child->thread.ptrace_bps[] copied by dup_task_struct() instead.
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
Acked-by: Michael Neuling <mikey@neuling.org>
--- x/arch/powerpc/kernel/process.c
+++ x/arch/powerpc/kernel/process.c
@@ -910,10 +910,6 @@ int arch_dup_task_struct(struct task_str
flush_altivec_to_thread(src);
flush_vsx_to_thread(src);
flush_spe_to_thread(src);
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
- flush_ptrace_hw_breakpoint(src);
-#endif /* CONFIG_HAVE_HW_BREAKPOINT */
-
*dst = *src;
return 0;
}
@@ -984,6 +980,10 @@ int copy_thread(unsigned long clone_flag
p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
_ALIGN_UP(sizeof(struct thread_info), 16);
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+ p->thread.ptrace_bps[0] = NULL;
+#endif
+
#ifdef CONFIG_PPC_STD_MMU_64
if (mmu_has_feature(MMU_FTR_SLB)) {
unsigned long sp_vsid;
^ permalink raw reply
* Re: [PATCH RESEND] powerpc/rtas_flash: Free kmem upon module exit
From: Michael Ellerman @ 2013-04-21 23:27 UTC (permalink / raw)
To: Vasant Hegde; +Cc: linuxppc-dev, paulus
In-Reply-To: <20130419114737.20439.54937.stgit@hegdevasant>
On Fri, Apr 19, 2013 at 05:18:09PM +0530, Vasant Hegde wrote:
> Memory allocated to flash_block_list in rtas_flash_write
> is not freed during module exit. We hit below call trace
> if we unload rtas_flash module after loading new firmware
> image and before rebooting the system.
Why the resend? Did anything change?
cheers
^ permalink raw reply
* Re: [PATCH 3/3] powerpc/powernv: Patch MSI EOI handler on P8
From: Michael Ellerman @ 2013-04-21 23:34 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <1366363965-23281-3-git-send-email-shangw@linux.vnet.ibm.com>
On Fri, Apr 19, 2013 at 05:32:45PM +0800, Gavin Shan wrote:
> The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
> steps to handle the P/Q bits in IVE before EOIing the corresponding
> interrupt. The patch changes the EOI handler to cover that.
> diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
> index 48861d3..289355e 100644
> --- a/arch/powerpc/sysdev/xics/icp-native.c
> +++ b/arch/powerpc/sysdev/xics/icp-native.c
> @@ -27,6 +27,10 @@
> #include <asm/xics.h>
> #include <asm/kvm_ppc.h>
>
> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
> +extern int pnv_pci_msi_eoi(unsigned int hw_irq);
> +#endif
You don't need to #ifdef the extern. But it should be in a header, not
here.
> @@ -89,6 +93,24 @@ static void icp_native_eoi(struct irq_data *d)
> icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
> }
>
> +static void icp_p8_native_eoi(struct irq_data *d)
> +{
> + unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
> + int ret;
> +
> + /* Let firmware handle P/Q bits */
> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
> + if (hw_irq != XICS_IPI) {
> + ret = pnv_pci_msi_eoi(hw_irq);
> + WARN_ON_ONCE(ret);
> + }
> +#endif
Why the ifdef in here? You only ever hook this function up if those are
true, so why do you need to check them again?
> @@ -296,6 +318,15 @@ int __init icp_native_init(void)
> if (found == 0)
> return -ENODEV;
>
> + /* Change the EOI handler for P8 */
> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
This would be neater if you created CONFIG_POWERNV_MSI, like we have
CONFIG_PSERIES_MSI.
cheers
^ permalink raw reply
* Re: [PATCH v2 06/15] powerpc/85xx: add support to JOG feature using cpufreq interface
From: Rafael J. Wysocki @ 2013-04-21 23:43 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, cpufreq, linux-pm
In-Reply-To: <20130419110057.GC29421@localhost.localdomain>
On Friday, April 19, 2013 07:00:57 PM Zhao Chenhui wrote:
> ----- Forwarded message from Zhao Chenhui <chenhui.zhao@freescale.com> -----
>
> Date: Fri, 19 Apr 2013 18:47:39 +0800
> From: Zhao Chenhui <chenhui.zhao@freescale.com>
> To: linuxppc-dev@lists.ozlabs.org
> CC: linux-kernel@vger.kernel.org
> Subject: [linuxppc-release] [PATCH v2 06/15] powerpc/85xx: add support to JOG feature using cpufreq interface
> X-Mailer: git-send-email 1.7.3
>
> From: chenhui zhao <chenhui.zhao@freescale.com>
>
> Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
> a dynamic mechanism to lower or raise the CPU core clock at runtime.
>
> This patch adds the support to change CPU frequency using the standard
> cpufreq interface. The ratio CORE to CCB can be 1:1(except MPC8536), 3:2,
> 2:1, 5:2, 3:1, 7:2 and 4:1.
>
> Two CPU cores on P1022 must not in the low power state during the frequency
> transition. The driver uses a atomic counter to meet the requirement.
>
> The jog mode frequency transition process on the MPC8536 is similar to
> the deep sleep process. The driver need save the CPU state and restore
> it after CPU warm reset.
>
> Note:
> * The I/O peripherals such as PCIe and eTSEC may lose packets during
> the jog mode frequency transition.
> * The driver doesn't support MPC8536 Rev 1.0 due to a JOG erratum.
> Subsequent revisions of MPC8536 have corrected the erratum.
>
> Signed-off-by: Dave Liu <daveliu@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> CC: Scott Wood <scottwood@freescale.com>
Well, I'd like someone from the PowerPC camp to comment on this before I take it.
Thanks,
Rafael
> ---
> arch/powerpc/platforms/85xx/Makefile | 1 +
> drivers/cpufreq/Kconfig.powerpc | 10 +
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/mpc85xx-cpufreq.c | 390 ++++++++++++++++++++++++++++++++++
> 4 files changed, 402 insertions(+), 0 deletions(-)
> create mode 100644 drivers/cpufreq/mpc85xx-cpufreq.c
>
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
> index a35bab7..da53bde 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -3,6 +3,7 @@
> #
> obj-$(CONFIG_SMP) += smp.o
> obj-$(CONFIG_FSL_PMC) += sleep.o
> +obj-$(CONFIG_CPU_FREQ_MPC85xx) += sleep.o
>
> obj-y += common.o
>
> diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc
> index e76992f..ba06a00 100644
> --- a/drivers/cpufreq/Kconfig.powerpc
> +++ b/drivers/cpufreq/Kconfig.powerpc
> @@ -5,3 +5,13 @@ config CPU_FREQ_MAPLE
> help
> This adds support for frequency switching on Maple 970FX
> Evaluation Board and compatible boards (IBM JS2x blades).
> +
> +config CPU_FREQ_MPC85xx
> + bool "Support for Freescale MPC85xx CPU freq"
> + depends on PPC_85xx && PPC32 && !PPC_E500MC
> + select CPU_FREQ_TABLE
> + help
> + This adds support for dynamic frequency switching on
> + Freescale MPC85xx by cpufreq interface. MPC8536 and P1022
> + have a JOG feature, which provides a dynamic mechanism
> + to lower or raise the CPU core clock at runtime.
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 863fd18..e7aecc5 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -61,3 +61,4 @@ obj-$(CONFIG_ARM_IMX6Q_CPUFREQ) += imx6q-cpufreq.o
> ##################################################################################
> # PowerPC platform drivers
> obj-$(CONFIG_CPU_FREQ_MAPLE) += maple-cpufreq.o
> +obj-$(CONFIG_CPU_FREQ_MPC85xx) += mpc85xx-cpufreq.o
> diff --git a/drivers/cpufreq/mpc85xx-cpufreq.c b/drivers/cpufreq/mpc85xx-cpufreq.c
> new file mode 100644
> index 0000000..f56c826
> --- /dev/null
> +++ b/drivers/cpufreq/mpc85xx-cpufreq.c
> @@ -0,0 +1,390 @@
> +/*
> + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc.
> + * Author: Dave Liu <daveliu@freescale.com>
> + * Modifier: Chenhui Zhao <chenhui.zhao@freescale.com>
> + *
> + * The cpufreq driver is for Freescale 85xx processor,
> + * based on arch/powerpc/platforms/cell/cbe_cpufreq.c
> + * (C) Copyright IBM Deutschland Entwicklung GmbH 2005-2007
> + * Christian Krafft <krafft@de.ibm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/cpufreq.h>
> +#include <linux/of_platform.h>
> +#include <linux/suspend.h>
> +#include <linux/cpu.h>
> +#include <linux/time.h>
> +#include <linux/io.h>
> +#include <linux/smp.h>
> +
> +#include <asm/prom.h>
> +#include <asm/reg.h>
> +#include <asm/machdep.h>
> +
> +#include <sysdev/fsl_soc.h>
> +
> +static DEFINE_MUTEX(mpc85xx_switch_mutex);
> +static void __iomem *guts;
> +
> +static u32 sysfreq;
> +static unsigned int max_pll[2];
> +static atomic_t in_jog_process;
> +static struct cpufreq_frequency_table *mpc85xx_freqs;
> +static int (*set_pll)(unsigned int cpu, unsigned int pll);
> +
> +static struct cpufreq_frequency_table mpc8536_freqs_table[] = {
> + {3, 0},
> + {4, 0},
> + {5, 0},
> + {6, 0},
> + {7, 0},
> + {8, 0},
> + {0, CPUFREQ_TABLE_END},
> +};
> +
> +static struct cpufreq_frequency_table p1022_freqs_table[] = {
> + {2, 0},
> + {3, 0},
> + {4, 0},
> + {5, 0},
> + {6, 0},
> + {7, 0},
> + {8, 0},
> + {0, CPUFREQ_TABLE_END},
> +};
> +
> +#define FREQ_500MHz 500000000
> +#define FREQ_800MHz 800000000
> +
> +#define CORE_RATIO_STRIDE 8
> +#define CORE_RATIO_MASK 0x3f
> +#define CORE_RATIO_SHIFT 16
> +
> +#define PORPLLSR 0x0 /* Power-On Reset PLL ratio status register */
> +
> +#define PMJCR 0x7c /* Power Management Jog Control Register */
> +#define PMJCR_CORE0_SPD 0x00001000
> +#define PMJCR_CORE_SPD 0x00002000
> +
> +#define POWMGTCSR 0x80 /* Power management control and status register */
> +#define POWMGTCSR_JOG 0x00200000
> +#define POWMGTCSR_INT_MASK 0x00000f00
> +
> +static void spin_while_jogging(void *dummy)
> +{
> + unsigned long flags;
> +
> + local_irq_save(flags);
> +
> + atomic_inc(&in_jog_process);
> +
> + while (atomic_read(&in_jog_process) != 0)
> + barrier();
> +
> + local_irq_restore(flags);
> +}
> +
> +static int get_pll(int hw_cpu)
> +{
> + int shift;
> + u32 val = in_be32(guts + PORPLLSR);
> +
> + shift = hw_cpu * CORE_RATIO_STRIDE + CORE_RATIO_SHIFT;
> +
> + return (val >> shift) & CORE_RATIO_MASK;
> +}
> +
> +static int mpc8536_set_pll(unsigned int cpu, unsigned int pll)
> +{
> + u32 corefreq, val, mask;
> + unsigned int cur_pll = get_pll(0);
> + unsigned long flags;
> +
> + if (pll == cur_pll)
> + return 0;
> +
> + val = (pll & CORE_RATIO_MASK) << CORE_RATIO_SHIFT;
> +
> + corefreq = sysfreq * pll / 2;
> + /*
> + * Set the COREx_SPD bit if the requested core frequency
> + * is larger than the threshold frequency.
> + */
> + if (corefreq > FREQ_800MHz)
> + val |= PMJCR_CORE_SPD;
> +
> + mask = (CORE_RATIO_MASK << CORE_RATIO_SHIFT) | PMJCR_CORE_SPD;
> + clrsetbits_be32(guts + PMJCR, mask, val);
> +
> + /* readback to sync write */
> + in_be32(guts + PMJCR);
> +
> + local_irq_save(flags);
> + mpc85xx_enter_deep_sleep(get_immrbase(), POWMGTCSR_JOG);
> + local_irq_restore(flags);
> +
> + /* verify */
> + cur_pll = get_pll(0);
> + if (cur_pll != pll) {
> + pr_err("%s: error. The current PLL is %d instead of %d.\n",
> + __func__, cur_pll, pll);
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> +static int p1022_set_pll(unsigned int cpu, unsigned int pll)
> +{
> + int index, hw_cpu = get_hard_smp_processor_id(cpu);
> + int shift;
> + u32 corefreq, val, mask = 0;
> + unsigned int cur_pll = get_pll(hw_cpu);
> + unsigned long flags;
> + int ret = 0;
> +
> + if (pll == cur_pll)
> + return 0;
> +
> + shift = hw_cpu * CORE_RATIO_STRIDE + CORE_RATIO_SHIFT;
> + val = (pll & CORE_RATIO_MASK) << shift;
> +
> + corefreq = sysfreq * pll / 2;
> + /*
> + * Set the COREx_SPD bit if the requested core frequency
> + * is larger than the threshold frequency.
> + */
> + if (corefreq > FREQ_500MHz)
> + val |= PMJCR_CORE0_SPD << hw_cpu;
> +
> + mask = (CORE_RATIO_MASK << shift) | (PMJCR_CORE0_SPD << hw_cpu);
> + clrsetbits_be32(guts + PMJCR, mask, val);
> +
> + /* readback to sync write */
> + in_be32(guts + PMJCR);
> +
> + get_online_cpus();
> + /*
> + * A Jog request can not be asserted when any core is in a low
> + * power state on P1022. Before executing a jog request, any
> + * core which is in a low power state must be waked by a
> + * interrupt, and keep waking up until the sequence is
> + * finished.
> + */
> + for_each_present_cpu(index) {
> + if (!cpu_online(index)) {
> + put_online_cpus();
> + pr_err("%s: error, core%d is down.\n", __func__, index);
> + return -1;
> + }
> + }
> +
> + atomic_set(&in_jog_process, 0);
> + smp_call_function(spin_while_jogging, NULL, 0);
> +
> + local_irq_save(flags);
> +
> + /* Wait for the other core to wake. */
> + if (!spin_event_timeout(atomic_read(&in_jog_process) == 1, 1000, 100)) {
> + pr_err("%s: timeout, the other core is not at running state.\n",
> + __func__);
> + ret = -1;
> + goto err;
> + }
> +
> + out_be32(guts + POWMGTCSR, POWMGTCSR_JOG | POWMGTCSR_INT_MASK);
> +
> + if (!spin_event_timeout(
> + (in_be32(guts + POWMGTCSR) & POWMGTCSR_JOG) == 0, 1000, 100)) {
> + pr_err("%s: timeout, fail to switch the core frequency.\n",
> + __func__);
> + ret = -1;
> + goto err;
> + }
> +
> + clrbits32(guts + POWMGTCSR, POWMGTCSR_INT_MASK);
> + in_be32(guts + POWMGTCSR);
> +
> + atomic_set(&in_jog_process, 0);
> +err:
> + local_irq_restore(flags);
> + put_online_cpus();
> +
> + /* verify */
> + cur_pll = get_pll(hw_cpu);
> + if (cur_pll != pll) {
> + pr_err("%s: error, the current PLL of core %d is %d instead of %d.\n",
> + __func__, hw_cpu, cur_pll, pll);
> + return -1;
> + }
> +
> + return ret;
> +}
> +
> +/*
> + * cpufreq functions
> + */
> +static int mpc85xx_cpufreq_cpu_init(struct cpufreq_policy *policy)
> +{
> + unsigned int i, cur_pll;
> + int hw_cpu = get_hard_smp_processor_id(policy->cpu);
> +
> + if (!cpu_present(policy->cpu))
> + return -ENODEV;
> +
> + /* the latency of a transition, the unit is ns */
> + policy->cpuinfo.transition_latency = 2000;
> +
> + cur_pll = get_pll(hw_cpu);
> +
> + /* initialize frequency table */
> + pr_debug("core%d frequency table:\n", hw_cpu);
> + for (i = 0; mpc85xx_freqs[i].frequency != CPUFREQ_TABLE_END; i++) {
> + if (mpc85xx_freqs[i].index <= max_pll[hw_cpu]) {
> + /* The frequency unit is kHz. */
> + mpc85xx_freqs[i].frequency =
> + (sysfreq * mpc85xx_freqs[i].index / 2) / 1000;
> + } else {
> + mpc85xx_freqs[i].frequency = CPUFREQ_ENTRY_INVALID;
> + }
> +
> + pr_debug("%d: %dkHz\n", i, mpc85xx_freqs[i].frequency);
> +
> + if (mpc85xx_freqs[i].index == cur_pll)
> + policy->cur = mpc85xx_freqs[i].frequency;
> + }
> + pr_debug("current pll is at %d, and core freq is%d\n",
> + cur_pll, policy->cur);
> +
> + cpufreq_frequency_table_get_attr(mpc85xx_freqs, policy->cpu);
> +
> + /*
> + * This ensures that policy->cpuinfo_min
> + * and policy->cpuinfo_max are set correctly.
> + */
> + return cpufreq_frequency_table_cpuinfo(policy, mpc85xx_freqs);
> +}
> +
> +static int mpc85xx_cpufreq_cpu_exit(struct cpufreq_policy *policy)
> +{
> + cpufreq_frequency_table_put_attr(policy->cpu);
> +
> + return 0;
> +}
> +
> +static int mpc85xx_cpufreq_verify(struct cpufreq_policy *policy)
> +{
> + return cpufreq_frequency_table_verify(policy, mpc85xx_freqs);
> +}
> +
> +static int mpc85xx_cpufreq_target(struct cpufreq_policy *policy,
> + unsigned int target_freq,
> + unsigned int relation)
> +{
> + struct cpufreq_freqs freqs;
> + unsigned int new;
> + int ret = 0;
> +
> + if (!set_pll)
> + return -ENODEV;
> +
> + cpufreq_frequency_table_target(policy,
> + mpc85xx_freqs,
> + target_freq,
> + relation,
> + &new);
> +
> + freqs.old = policy->cur;
> + freqs.new = mpc85xx_freqs[new].frequency;
> + freqs.cpu = policy->cpu;
> +
> + mutex_lock(&mpc85xx_switch_mutex);
> + cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
> +
> + ret = set_pll(policy->cpu, mpc85xx_freqs[new].index);
> + if (!ret) {
> + pr_info("cpufreq: Setting core%d frequency to %d kHz and PLL ratio to %d:2\n",
> + policy->cpu, mpc85xx_freqs[new].frequency,
> + mpc85xx_freqs[new].index);
> +
> + ppc_proc_freq = freqs.new * 1000ul;
> + }
> + cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
> + mutex_unlock(&mpc85xx_switch_mutex);
> +
> + return ret;
> +}
> +
> +static struct cpufreq_driver mpc85xx_cpufreq_driver = {
> + .verify = mpc85xx_cpufreq_verify,
> + .target = mpc85xx_cpufreq_target,
> + .init = mpc85xx_cpufreq_cpu_init,
> + .exit = mpc85xx_cpufreq_cpu_exit,
> + .name = "mpc85xx-JOG",
> + .owner = THIS_MODULE,
> + .flags = CPUFREQ_CONST_LOOPS,
> +};
> +
> +static struct of_device_id mpc85xx_jog_ids[] = {
> + { .compatible = "fsl,mpc8536-guts", },
> + { .compatible = "fsl,p1022-guts", },
> + {}
> +};
> +
> +static int __init mpc85xx_jog_init(void)
> +{
> + struct device_node *np;
> + unsigned int svr;
> +
> + np = of_find_matching_node(NULL, mpc85xx_jog_ids);
> + if (!np)
> + return -ENODEV;
> +
> + guts = of_iomap(np, 0);
> + if (!guts) {
> + of_node_put(np);
> + return -ENODEV;
> + }
> +
> + sysfreq = fsl_get_sys_freq();
> +
> + if (of_device_is_compatible(np, "fsl,mpc8536-guts")) {
> + svr = mfspr(SPRN_SVR);
> + if ((svr & 0x7fff) == 0x10) {
> + pr_err("MPC8536 Rev 1.0 does not support cpufreq(JOG).\n");
> + of_node_put(np);
> + return -ENODEV;
> + }
> + mpc85xx_freqs = mpc8536_freqs_table;
> + set_pll = mpc8536_set_pll;
> + max_pll[0] = get_pll(0);
> +
> + } else if (of_device_is_compatible(np, "fsl,p1022-guts")) {
> + mpc85xx_freqs = p1022_freqs_table;
> + set_pll = p1022_set_pll;
> + max_pll[0] = get_pll(0);
> + max_pll[1] = get_pll(1);
> + }
> +
> + pr_info("Freescale MPC85xx cpufreq(JOG) driver\n");
> +
> + of_node_put(np);
> + return cpufreq_register_driver(&mpc85xx_cpufreq_driver);
> +}
> +
> +device_initcall(mpc85xx_jog_init);
>
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
^ permalink raw reply
* Re: [PATCH V3 1/5] powerpc, perf: Add new BHRB related instructions for POWER8
From: Michael Ellerman @ 2013-04-21 23:41 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linuxppc-dev, mikey, linux-kernel
In-Reply-To: <1366287976-3900-2-git-send-email-khandual@linux.vnet.ibm.com>
On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> This patch adds new POWER8 instruction encoding for reading
> the BHRB buffer entries and also clearing it. Encoding for
> "clrbhrb" instruction is straight forward.
Which is "clear branch history rolling buffer" ?
> But "mfbhrbe"
> encoding involves reading a certain index of BHRB buffer
> into a particular GPR register.
And "Move from branch history rolling buffer entry" ?
> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> index 8752bc8..93ae5a1 100644
> --- a/arch/powerpc/include/asm/ppc-opcode.h
> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> @@ -82,6 +82,7 @@
> #define __REGA0_R31 31
>
> /* sorted alphabetically */
> +#define PPC_INST_BHRBE 0x7c00025c
I don't think you really need this, just use the literal value below.
> @@ -297,6 +298,12 @@
> #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
> #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
>
> +/* BHRB instructions */
> +#define PPC_CLRBHRB stringify_in_c(.long 0x7c00035c)
> +#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
> + __PPC_RS(r) | \
> + (((n) & 0x1f) << 11))
Why are you not using ___PPC_RB(n) here ?
cheers
^ permalink raw reply
* Re: [PATCH V3 1/5] powerpc, perf: Add new BHRB related instructions for POWER8
From: Michael Neuling @ 2013-04-22 1:13 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, linux-kernel, Anshuman Khandual
In-Reply-To: <20130421234109.GC22246@concordia>
Michael Ellerman <michael@ellerman.id.au> wrote:
> On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> > This patch adds new POWER8 instruction encoding for reading
> > the BHRB buffer entries and also clearing it. Encoding for
> > "clrbhrb" instruction is straight forward.
>
> Which is "clear branch history rolling buffer" ?
>
> > But "mfbhrbe"
> > encoding involves reading a certain index of BHRB buffer
> > into a particular GPR register.
>
> And "Move from branch history rolling buffer entry" ?
>
> > diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> > index 8752bc8..93ae5a1 100644
> > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > @@ -82,6 +82,7 @@
> > #define __REGA0_R31 31
> >
> > /* sorted alphabetically */
> > +#define PPC_INST_BHRBE 0x7c00025c
>
> I don't think you really need this, just use the literal value below.
The rest of the defines in this file do this, so Anshuman's right.
> > @@ -297,6 +298,12 @@
> > #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
> > #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
> >
> > +/* BHRB instructions */
> > +#define PPC_CLRBHRB stringify_in_c(.long 0x7c00035c)
> > +#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
> > + __PPC_RS(r) | \
> > + (((n) & 0x1f) << 11))
>
> Why are you not using ___PPC_RB(n) here ?
Actually, this is wrong. The number field should be 10 bits (0x3ff),
not 5 (0x1f) Anshuman please fix.
Mikey
^ permalink raw reply
* Re: [PATCH 3/3] powerpc/powernv: Patch MSI EOI handler on P8
From: Gavin Shan @ 2013-04-22 1:45 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <20130421233436.GB22246@concordia>
On Mon, Apr 22, 2013 at 09:34:36AM +1000, Michael Ellerman wrote:
>On Fri, Apr 19, 2013 at 05:32:45PM +0800, Gavin Shan wrote:
>> The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
>> steps to handle the P/Q bits in IVE before EOIing the corresponding
>> interrupt. The patch changes the EOI handler to cover that.
Thanks for your time to review it, Michael. By the way, I think I need
rebase the patch since the patch fb1b55d654a7038ca6337fbf55839a308c9bc1a7
("Using bitmap to manage MSI") has been merged to linux-next.
>> diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
>> index 48861d3..289355e 100644
>> --- a/arch/powerpc/sysdev/xics/icp-native.c
>> +++ b/arch/powerpc/sysdev/xics/icp-native.c
>> @@ -27,6 +27,10 @@
>> #include <asm/xics.h>
>> #include <asm/kvm_ppc.h>
>>
>> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
>> +extern int pnv_pci_msi_eoi(unsigned int hw_irq);
>> +#endif
>
>You don't need to #ifdef the extern. But it should be in a header, not
>here.
>
Ok. I'll put it into asm/xics.h, but I want to confirm we needn't
#ifdef when moving it to asm/xics.h?
>> @@ -89,6 +93,24 @@ static void icp_native_eoi(struct irq_data *d)
>> icp_native_set_xirr((xics_pop_cppr() << 24) | hw_irq);
>> }
>>
>> +static void icp_p8_native_eoi(struct irq_data *d)
>> +{
>> + unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
>> + int ret;
>> +
>> + /* Let firmware handle P/Q bits */
>> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
>> + if (hw_irq != XICS_IPI) {
>> + ret = pnv_pci_msi_eoi(hw_irq);
>> + WARN_ON_ONCE(ret);
>> + }
>> +#endif
>
>Why the ifdef in here? You only ever hook this function up if those are
>true, so why do you need to check them again?
>
Right. I will remove #ifdef here in next version.
>> @@ -296,6 +318,15 @@ int __init icp_native_init(void)
>> if (found == 0)
>> return -ENODEV;
>>
>> + /* Change the EOI handler for P8 */
>> +#if defined(CONFIG_PPC_POWERNV) && defined(CONFIG_PCI_MSI)
>
>This would be neater if you created CONFIG_POWERNV_MSI, like we have
>CONFIG_PSERIES_MSI.
>
Sure. I'll introduce CONFIG_PSERIES_MSI in next version.
Thanks,
Gavin
^ permalink raw reply
* [PATCH 0/5] of_platform_driver and OF_DEVICE removal
From: Rob Herring @ 2013-04-22 2:13 UTC (permalink / raw)
To: linux-kernel, devicetree-discuss
Cc: Roland Dreier, Sean Hefty, Arnd Bergmann, Alexander Shishkin,
linux-usb, Rob Herring, linux-rdma, Christoph Raisch,
Hoang-Nam Nguyen, Thadeu Lima de Souza Cascardo,
Greg Kroah-Hartman, Grant Likely, Paul Mackerras, netdev,
linuxppc-dev, Hal Rosenstock
From: Rob Herring <rob.herring@calxeda.com>
This series is a relatively straight-forward removal of the last remaining
user of of_platform_driver (ibmebus) and removal of CONFIG_OF_DEVICE which
is always enabled when CONFIG_OF is enabled.
Compile tested on powerpc and sparc.
Rob
Rob Herring (5):
ibmebus: convert of_platform_driver to platform_driver
driver core: move to_platform_driver to platform_device.h
of: remove of_platform_driver
usb: chipidea: depend on CONFIG_OF instead of CONFIG_OF_DEVICE
of: remove CONFIG_OF_DEVICE
arch/powerpc/include/asm/ibmebus.h | 4 ++--
arch/powerpc/kernel/ibmebus.c | 22 ++++++++++-----------
drivers/base/platform.c | 3 ---
drivers/infiniband/hw/ehca/ehca_main.c | 5 ++---
drivers/net/ethernet/ibm/ehea/ehea_main.c | 8 +++-----
drivers/of/Kconfig | 3 ---
drivers/of/Makefile | 3 +--
drivers/usb/chipidea/Makefile | 2 +-
include/linux/of_device.h | 6 +++---
include/linux/of_platform.h | 30 +----------------------------
include/linux/platform_device.h | 3 +++
11 files changed, 26 insertions(+), 63 deletions(-)
--
1.7.10.4
^ permalink raw reply
* [PATCH 1/5] ibmebus: convert of_platform_driver to platform_driver
From: Rob Herring @ 2013-04-22 2:13 UTC (permalink / raw)
To: linux-kernel, devicetree-discuss
Cc: Roland Dreier, Arnd Bergmann, linux-rdma, Rob Herring,
Christoph Raisch, Hoang-Nam Nguyen, Thadeu Lima de Souza Cascardo,
netdev, Grant Likely, Paul Mackerras, Sean Hefty, linuxppc-dev,
Hal Rosenstock
In-Reply-To: <1366596798-9457-1-git-send-email-robherring2@gmail.com>
From: Rob Herring <rob.herring@calxeda.com>
ibmebus is the last remaining user of of_platform_driver and the
conversion to a regular platform driver is trivial.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Hoang-Nam Nguyen <hnguyen@de.ibm.com>
Cc: Christoph Raisch <raisch@de.ibm.com>
Cc: Roland Dreier <roland@kernel.org>
Cc: Sean Hefty <sean.hefty@intel.com>
Cc: Hal Rosenstock <hal.rosenstock@gmail.com>
Cc: Thadeu Lima de Souza Cascardo <cascardo@linux.vnet.ibm.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-rdma@vger.kernel.org
Cc: netdev@vger.kernel.org
---
arch/powerpc/include/asm/ibmebus.h | 4 ++--
arch/powerpc/kernel/ibmebus.c | 22 ++++++++++------------
drivers/infiniband/hw/ehca/ehca_main.c | 5 ++---
drivers/net/ethernet/ibm/ehea/ehea_main.c | 8 +++-----
4 files changed, 17 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/include/asm/ibmebus.h b/arch/powerpc/include/asm/ibmebus.h
index 1a9d9ae..088f95b 100644
--- a/arch/powerpc/include/asm/ibmebus.h
+++ b/arch/powerpc/include/asm/ibmebus.h
@@ -48,8 +48,8 @@
extern struct bus_type ibmebus_bus_type;
-int ibmebus_register_driver(struct of_platform_driver *drv);
-void ibmebus_unregister_driver(struct of_platform_driver *drv);
+int ibmebus_register_driver(struct platform_driver *drv);
+void ibmebus_unregister_driver(struct platform_driver *drv);
int ibmebus_request_irq(u32 ist, irq_handler_t handler,
unsigned long irq_flags, const char *devname,
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index 8220baa..16a7c23 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -205,7 +205,7 @@ static int ibmebus_create_devices(const struct of_device_id *matches)
return ret;
}
-int ibmebus_register_driver(struct of_platform_driver *drv)
+int ibmebus_register_driver(struct platform_driver *drv)
{
/* If the driver uses devices that ibmebus doesn't know, add them */
ibmebus_create_devices(drv->driver.of_match_table);
@@ -215,7 +215,7 @@ int ibmebus_register_driver(struct of_platform_driver *drv)
}
EXPORT_SYMBOL(ibmebus_register_driver);
-void ibmebus_unregister_driver(struct of_platform_driver *drv)
+void ibmebus_unregister_driver(struct platform_driver *drv)
{
driver_unregister(&drv->driver);
}
@@ -338,11 +338,10 @@ static int ibmebus_bus_bus_match(struct device *dev, struct device_driver *drv)
static int ibmebus_bus_device_probe(struct device *dev)
{
int error = -ENODEV;
- struct of_platform_driver *drv;
+ struct platform_driver *drv;
struct platform_device *of_dev;
- const struct of_device_id *match;
- drv = to_of_platform_driver(dev->driver);
+ drv = to_platform_driver(dev->driver);
of_dev = to_platform_device(dev);
if (!drv->probe)
@@ -350,9 +349,8 @@ static int ibmebus_bus_device_probe(struct device *dev)
of_dev_get(of_dev);
- match = of_match_device(drv->driver.of_match_table, dev);
- if (match)
- error = drv->probe(of_dev, match);
+ if (of_driver_match_device(dev, dev->driver))
+ error = drv->probe(of_dev);
if (error)
of_dev_put(of_dev);
@@ -362,7 +360,7 @@ static int ibmebus_bus_device_probe(struct device *dev)
static int ibmebus_bus_device_remove(struct device *dev)
{
struct platform_device *of_dev = to_platform_device(dev);
- struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+ struct platform_driver *drv = to_platform_driver(dev->driver);
if (dev->driver && drv->remove)
drv->remove(of_dev);
@@ -372,7 +370,7 @@ static int ibmebus_bus_device_remove(struct device *dev)
static void ibmebus_bus_device_shutdown(struct device *dev)
{
struct platform_device *of_dev = to_platform_device(dev);
- struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+ struct platform_driver *drv = to_platform_driver(dev->driver);
if (dev->driver && drv->shutdown)
drv->shutdown(of_dev);
@@ -419,7 +417,7 @@ struct device_attribute ibmebus_bus_device_attrs[] = {
static int ibmebus_bus_legacy_suspend(struct device *dev, pm_message_t mesg)
{
struct platform_device *of_dev = to_platform_device(dev);
- struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+ struct platform_driver *drv = to_platform_driver(dev->driver);
int ret = 0;
if (dev->driver && drv->suspend)
@@ -430,7 +428,7 @@ static int ibmebus_bus_legacy_suspend(struct device *dev, pm_message_t mesg)
static int ibmebus_bus_legacy_resume(struct device *dev)
{
struct platform_device *of_dev = to_platform_device(dev);
- struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+ struct platform_driver *drv = to_platform_driver(dev->driver);
int ret = 0;
if (dev->driver && drv->resume)
diff --git a/drivers/infiniband/hw/ehca/ehca_main.c b/drivers/infiniband/hw/ehca/ehca_main.c
index f8a6291..982e3ef 100644
--- a/drivers/infiniband/hw/ehca/ehca_main.c
+++ b/drivers/infiniband/hw/ehca/ehca_main.c
@@ -713,8 +713,7 @@ static struct attribute_group ehca_dev_attr_grp = {
.attrs = ehca_dev_attrs
};
-static int ehca_probe(struct platform_device *dev,
- const struct of_device_id *id)
+static int ehca_probe(struct platform_device *dev)
{
struct ehca_shca *shca;
const u64 *handle;
@@ -937,7 +936,7 @@ static struct of_device_id ehca_device_table[] =
};
MODULE_DEVICE_TABLE(of, ehca_device_table);
-static struct of_platform_driver ehca_driver = {
+static struct platform_driver ehca_driver = {
.probe = ehca_probe,
.remove = ehca_remove,
.driver = {
diff --git a/drivers/net/ethernet/ibm/ehea/ehea_main.c b/drivers/net/ethernet/ibm/ehea/ehea_main.c
index 328f47c..c6ecf70 100644
--- a/drivers/net/ethernet/ibm/ehea/ehea_main.c
+++ b/drivers/net/ethernet/ibm/ehea/ehea_main.c
@@ -98,8 +98,7 @@ static struct ehea_fw_handle_array ehea_fw_handles;
static struct ehea_bcmc_reg_array ehea_bcmc_regs;
-static int ehea_probe_adapter(struct platform_device *dev,
- const struct of_device_id *id);
+static int ehea_probe_adapter(struct platform_device *dev);
static int ehea_remove(struct platform_device *dev);
@@ -112,7 +111,7 @@ static struct of_device_id ehea_device_table[] = {
};
MODULE_DEVICE_TABLE(of, ehea_device_table);
-static struct of_platform_driver ehea_driver = {
+static struct platform_driver ehea_driver = {
.driver = {
.name = "ehea",
.owner = THIS_MODULE,
@@ -3255,8 +3254,7 @@ static void ehea_remove_device_sysfs(struct platform_device *dev)
device_remove_file(&dev->dev, &dev_attr_remove_port);
}
-static int ehea_probe_adapter(struct platform_device *dev,
- const struct of_device_id *id)
+static int ehea_probe_adapter(struct platform_device *dev)
{
struct ehea_adapter *adapter;
const u64 *adapter_handle;
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH V3 1/5] powerpc, perf: Add new BHRB related instructions for POWER8
From: Michael Ellerman @ 2013-04-22 2:45 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, linux-kernel, Anshuman Khandual
In-Reply-To: <14010.1366593223@ale.ozlabs.ibm.com>
On Mon, Apr 22, 2013 at 11:13:43AM +1000, Michael Neuling wrote:
> Michael Ellerman <michael@ellerman.id.au> wrote:
>
> > On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> > > This patch adds new POWER8 instruction encoding for reading
> > > the BHRB buffer entries and also clearing it. Encoding for
> > > "clrbhrb" instruction is straight forward.
> >
> > Which is "clear branch history rolling buffer" ?
> >
> > > But "mfbhrbe"
> > > encoding involves reading a certain index of BHRB buffer
> > > into a particular GPR register.
> >
> > And "Move from branch history rolling buffer entry" ?
> >
> > > diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> > > index 8752bc8..93ae5a1 100644
> > > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > > @@ -82,6 +82,7 @@
> > > #define __REGA0_R31 31
> > >
> > > /* sorted alphabetically */
> > > +#define PPC_INST_BHRBE 0x7c00025c
> >
> > I don't think you really need this, just use the literal value below.
>
> The rest of the defines in this file do this, so Anshuman's right.
I don't see the point, but sure let's be consistent. Though in that case
he should do the same for PPC_CLRBHRB below.
> > > @@ -297,6 +298,12 @@
> > > #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
> > > #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
> > >
> > > +/* BHRB instructions */
> > > +#define PPC_CLRBHRB stringify_in_c(.long 0x7c00035c)
> > > +#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
> > > + __PPC_RS(r) | \
> > > + (((n) & 0x1f) << 11))
> >
> > Why are you not using ___PPC_RB(n) here ?
>
> Actually, this is wrong. The number field should be 10 bits (0x3ff),
> not 5 (0x1f) Anshuman please fix.
ACK.
cheers
^ permalink raw reply
* Re: [PATCH V3 1/5] powerpc, perf: Add new BHRB related instructions for POWER8
From: Michael Neuling @ 2013-04-22 2:50 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, linux-kernel, Anshuman Khandual
In-Reply-To: <20130422024546.GA24739@concordia>
Michael Ellerman <michael@ellerman.id.au> wrote:
> On Mon, Apr 22, 2013 at 11:13:43AM +1000, Michael Neuling wrote:
> > Michael Ellerman <michael@ellerman.id.au> wrote:
> >
> > > On Thu, Apr 18, 2013 at 05:56:12PM +0530, Anshuman Khandual wrote:
> > > > This patch adds new POWER8 instruction encoding for reading
> > > > the BHRB buffer entries and also clearing it. Encoding for
> > > > "clrbhrb" instruction is straight forward.
> > >
> > > Which is "clear branch history rolling buffer" ?
> > >
> > > > But "mfbhrbe"
> > > > encoding involves reading a certain index of BHRB buffer
> > > > into a particular GPR register.
> > >
> > > And "Move from branch history rolling buffer entry" ?
> > >
> > > > diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> > > > index 8752bc8..93ae5a1 100644
> > > > --- a/arch/powerpc/include/asm/ppc-opcode.h
> > > > +++ b/arch/powerpc/include/asm/ppc-opcode.h
> > > > @@ -82,6 +82,7 @@
> > > > #define __REGA0_R31 31
> > > >
> > > > /* sorted alphabetically */
> > > > +#define PPC_INST_BHRBE 0x7c00025c
> > >
> > > I don't think you really need this, just use the literal value below.
> >
> > The rest of the defines in this file do this, so Anshuman's right.
>
> I don't see the point, but sure let's be consistent. Though in that case
> he should do the same for PPC_CLRBHRB below.
Agreed.
Mikey
>
> > > > @@ -297,6 +298,12 @@
> > > > #define PPC_NAP stringify_in_c(.long PPC_INST_NAP)
> > > > #define PPC_SLEEP stringify_in_c(.long PPC_INST_SLEEP)
> > > >
> > > > +/* BHRB instructions */
> > > > +#define PPC_CLRBHRB stringify_in_c(.long 0x7c00035c)
> > > > +#define PPC_MFBHRBE(r, n) stringify_in_c(.long PPC_INST_BHRBE | \
> > > > + __PPC_RS(r) | \
> > > > + (((n) & 0x1f) << 11))
> > >
> > > Why are you not using ___PPC_RB(n) here ?
> >
> > Actually, this is wrong. The number field should be 10 bits (0x3ff),
> > not 5 (0x1f) Anshuman please fix.
>
> ACK.
>
> cheers
>
^ permalink raw reply
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