* [PATCH v2 2/8] powerpc/pseries: Add version and timestamp to oops header
From: Aruna Balakrishnaiah @ 2013-04-24 6:20 UTC (permalink / raw)
To: linuxppc-dev, paulus, linux-kernel, benh
Cc: jkenisto, tony.luck, mahesh, cbouatmailru, anton, ccross,
keescook
In-Reply-To: <20130424061807.7341.909.stgit@aruna-ThinkPad-T420>
Introduce version and timestamp information in the oops header.
oops_log_info (oops header) holds version (to distinguish between old
and new format oops header), length of the oops text
(compressed or uncompressed) and timestamp.
The version field will sit in the same place as the length in old
headers. version is assigned 5000 (greater than oops partition size)
so that existing tools will refuse to dump new style partitions as
the length is too large. The updated tools will work with both
old and new format headers.
Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
Reviewed-by: Jim Keniston <jkenisto@us.ibm.com>
---
arch/powerpc/platforms/pseries/nvram.c | 57 +++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index e54a8b7..742735a 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -29,6 +29,13 @@
/* Max bytes to read/write in one go */
#define NVRW_CNT 0x20
+/*
+ * Set oops header version to distingush between old and new format header.
+ * lnx,oops-log partition max size is 4000, header version > 4000 will
+ * help in identifying new header.
+ */
+#define OOPS_HDR_VERSION 5000
+
static unsigned int nvram_size;
static int nvram_fetch, nvram_store;
static char nvram_buf[NVRW_CNT]; /* assume this is in the first 4GB */
@@ -67,6 +74,12 @@ static const char *pseries_nvram_os_partitions[] = {
NULL
};
+struct oops_log_info {
+ u16 version;
+ u16 report_length;
+ u64 timestamp;
+} __attribute__((packed));
+
static void oops_to_nvram(struct kmsg_dumper *dumper,
enum kmsg_dump_reason reason);
@@ -83,28 +96,28 @@ static unsigned long last_unread_rtas_event; /* timestamp */
* big_oops_buf[] holds the uncompressed text we're capturing.
*
- * oops_buf[] holds the compressed text, preceded by a prefix.
- * The prefix is just a u16 holding the length of the compressed* text.
- * (*Or uncompressed, if compression fails.) oops_buf[] gets written
- * to NVRAM.
+ * oops_buf[] holds the compressed text, preceded by a oops header.
+ * oops header has u16 holding the version of oops header (to differentiate
+ * between old and new format header) followed by u16 holding the length of
+ * the compressed* text (*Or uncompressed, if compression fails.) and u64
+ * holding the timestamp. oops_buf[] gets written to NVRAM.
*
- * oops_len points to the prefix. oops_data points to the compressed text.
+ * oops_log_info points to the header. oops_data points to the compressed text.
*
* +- oops_buf
- * | +- oops_data
- * v v
- * +------------+-----------------------------------------------+
- * | length | text |
- * | (2 bytes) | (oops_data_sz bytes) |
- * +------------+-----------------------------------------------+
+ * | +- oops_data
+ * v v
+ * +-----------+-----------+-----------+------------------------+
+ * | version | length | timestamp | text |
+ * | (2 bytes) | (2 bytes) | (8 bytes) | (oops_data_sz bytes) |
+ * +-----------+-----------+-----------+------------------------+
* ^
- * +- oops_len
+ * +- oops_log_info
*
* We preallocate these buffers during init to avoid kmalloc during oops/panic.
*/
static size_t big_oops_buf_sz;
static char *big_oops_buf, *oops_buf;
-static u16 *oops_len;
static char *oops_data;
static size_t oops_data_sz;
@@ -425,9 +438,8 @@ static void __init nvram_init_oops_partition(int rtas_partition_exists)
oops_log_partition.name);
return;
}
- oops_len = (u16*) oops_buf;
- oops_data = oops_buf + sizeof(u16);
- oops_data_sz = oops_log_partition.size - sizeof(u16);
+ oops_data = oops_buf + sizeof(struct oops_log_info);
+ oops_data_sz = oops_log_partition.size - sizeof(struct oops_log_info);
/*
* Figure compression (preceded by elimination of each line's <n>
@@ -555,6 +567,7 @@ error:
/* Compress the text from big_oops_buf into oops_buf. */
static int zip_oops(size_t text_len)
{
+ struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
int zipped_len = nvram_compress(big_oops_buf, oops_data, text_len,
oops_data_sz);
if (zipped_len < 0) {
@@ -562,7 +575,9 @@ static int zip_oops(size_t text_len)
pr_err("nvram: logging uncompressed oops/panic report\n");
return -1;
}
- *oops_len = (u16) zipped_len;
+ oops_hdr->version = OOPS_HDR_VERSION;
+ oops_hdr->report_length = (u16) zipped_len;
+ oops_hdr->timestamp = get_seconds();
return 0;
}
@@ -576,6 +591,7 @@ static int zip_oops(size_t text_len)
static void oops_to_nvram(struct kmsg_dumper *dumper,
enum kmsg_dump_reason reason)
{
+ struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
static unsigned int oops_count = 0;
static bool panicking = false;
static DEFINE_SPINLOCK(lock);
@@ -622,11 +638,14 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
kmsg_dump_get_buffer(dumper, false,
oops_data, oops_data_sz, &text_len);
err_type = ERR_TYPE_KERNEL_PANIC;
- *oops_len = (u16) text_len;
+ oops_hdr->version = OOPS_HDR_VERSION;
+ oops_hdr->report_length = (u16) text_len;
+ oops_hdr->timestamp = get_seconds();
}
(void) nvram_write_os_partition(&oops_log_partition, oops_buf,
- (int) (sizeof(*oops_len) + *oops_len), err_type, ++oops_count);
+ (int) (sizeof(*oops_hdr) + oops_hdr->report_length), err_type,
+ ++oops_count);
spin_unlock_irqrestore(&lock, flags);
}
^ permalink raw reply related
* [PATCH v2 1/8] powerpc/pseries: Remove syslog prefix in uncompressed oops text
From: Aruna Balakrishnaiah @ 2013-04-24 6:20 UTC (permalink / raw)
To: linuxppc-dev, paulus, linux-kernel, benh
Cc: jkenisto, tony.luck, mahesh, cbouatmailru, anton, ccross,
keescook
In-Reply-To: <20130424061807.7341.909.stgit@aruna-ThinkPad-T420>
Removal of syslog prefix in the uncompressed oops text will
help in capturing more oops data.
Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
Reviewed-by: Jim Keniston <jkenisto@us.ibm.com>
---
arch/powerpc/platforms/pseries/nvram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index 8733a86..e54a8b7 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -619,7 +619,7 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
}
if (rc != 0) {
kmsg_dump_rewind(dumper);
- kmsg_dump_get_buffer(dumper, true,
+ kmsg_dump_get_buffer(dumper, false,
oops_data, oops_data_sz, &text_len);
err_type = ERR_TYPE_KERNEL_PANIC;
*oops_len = (u16) text_len;
^ permalink raw reply related
* [PATCH v2 0/8] powerpc/pseries: Nvram-to-pstore
From: Aruna Balakrishnaiah @ 2013-04-24 6:19 UTC (permalink / raw)
To: linuxppc-dev, paulus, linux-kernel, benh
Cc: jkenisto, tony.luck, mahesh, cbouatmailru, anton, ccross,
keescook
Currently the kernel provides the contents of p-series NVRAM only as a
simple stream of bytes via /dev/nvram, which must be interpreted in user
space by the nvram command in the powerpc-utils package. This patch set
exploits the pstore subsystem to expose each partition in NVRAM as a
separate file in /dev/pstore. For instance Oops messages will stored in a
file named [dmesg-nvram-2].
Changes from v1:
- Reduce #ifdefs by and remove forward declarations of pstore callbacks
- Handle return value of nvram_write_os_partition
- Remove empty pstore callbacks and register pstore only when pstore
is configured
---
Aruna Balakrishnaiah (8):
powerpc/pseries: Remove syslog prefix in uncompressed oops text
powerpc/pseries: Add version and timestamp to oops header
powerpc/pseries: Introduce generic read function to read nvram-partitions
powerpc/pseries: Read/Write oops nvram partition via pstore
powerpc/pseries: Read rtas partition via pstore
powerpc/pseries: Distinguish between a os-partition and non-os partition
powerpc/pseries: Read of-config partition via pstore
powerpc/pseries: Read common partition via pstore
arch/powerpc/platforms/pseries/nvram.c | 353 +++++++++++++++++++++++++++-----
fs/pstore/inode.c | 9 +
include/linux/pstore.h | 4
3 files changed, 313 insertions(+), 53 deletions(-)
--
^ permalink raw reply
* Re: [PATCH 1/1] usb: ehci-fsl: set INCR8 mode only on MPC512x
From: Anatolij Gustschin @ 2013-04-24 5:55 UTC (permalink / raw)
To: Tiejun Chen; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366772110-9620-1-git-send-email-tiejun.chen@windriver.com>
On Wed, 24 Apr 2013 10:55:10 +0800
Tiejun Chen <tiejun.chen@windriver.com> wrote:
> commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
> on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
> INCR8 mode for system bus interface on MPC512x, but we should make sure
> this is only valid for MPC512x like other parts of this commit. Otherwise
NAK. It is already only valid for MPC512x.
> this would issue other platforms as abnormal without this similar Errata.
This setting is in the ehci_fsl_mpc512x_drv_resume() function which is
not called on other platforms.
Thanks,
Anatolij
^ permalink raw reply
* Re: [PATCH -V6 05/27] powerpc: New hugepage directory format
From: Paul Mackerras @ 2013-04-24 5:47 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1366624861-24948-6-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Mon, Apr 22, 2013 at 03:30:39PM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
[snip]
> /*
> - * Use the top bit of the higher-level page table entries to indicate whether
> - * the entries we point to contain hugepages. This works because we know that
> - * the page tables live in kernel space. If we ever decide to support having
> - * page tables at arbitrary addresses, this breaks and will have to change.
> - */
> -#ifdef CONFIG_PPC64
> -#define PD_HUGE 0x8000000000000000
> -#else
> -#define PD_HUGE 0x80000000
> -#endif
I think this is a good thing to do ultimately, but if you do this you
also need to fix arch/powerpc/kernel/head_fsl_booke.S:
#ifdef CONFIG_PTE_64BIT
#ifdef CONFIG_HUGETLB_PAGE
#define FIND_PTE \
rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
blt 1000f; /* Normal non-huge page */ \
beq 2f; /* Bail if no table */ \
oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
xor r12, r10, r11; /* drop size bits from pointer */ \
b 1001f; \
and this, from arch/powerpc/mm/tlb_low_64e.S:
cmpdi cr0,r14,0
bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
(of which there are several similar instances in that file).
If you want to avoid fixing these bits of assembly code (and any
others I missed in my quick scan), you'll need to keep the definition
of PD_HUGE, at least on anything not 64-bit Book3S.
Paul.
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: Move opcode definitions from kvm/emulate.c to asm/ppc-opcode.h
From: Benjamin Herrenschmidt @ 2013-04-24 4:19 UTC (permalink / raw)
To: Jia Hongtao-B38951; +Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C4A4B0@039-SN1MPN1-002.039d.mgd.msft.net>
On Tue, 2013-04-23 at 06:36 +0000, Jia Hongtao-B38951 wrote:
> These definitions are firstly used by KVM defined like OP_31_XOP_TRAP.
> Two ways to extract these definitions for public use:
>
> 1. Like this patch did. For keeping the KVM code that using these
> definitions unchanged we do not update them to match.
>
> 2. Move these definitions to another .h file like my last patch did:
> http://patchwork.ozlabs.org/patch/235646/
> You can see the comments there.
There's a better way ... but it's more work.
All opcodes are based on a primary opcode and a potential secondary
opcode. You could/should rework ppc-opcodes.h to in fact define them
all that way as well, which would "reconcile" the KVM way and the
existing stuff.
Cheers,
Ben.
> Thanks.
> -Hongtao
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [RFC, PATCH v2] powerpc/prom: Scan reserved-ranges node for memory reservations
From: Jeremy Kerr @ 2013-04-24 3:34 UTC (permalink / raw)
To: linuxppc-dev
Based on benh's proposal at
https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-September/101237.html,
this change provides support for reserving memory from the
reserved-ranges node at the root of the device tree.
We just call memblock_reserve on these ranges for now.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
---
v2: fix range property iteration
---
arch/powerpc/kernel/prom.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 8b6f7a9..c77307e 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -559,6 +559,34 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start,
}
#endif
+static bool __init early_reserve_mem_dt(void)
+{
+ unsigned long i, len, dt_root;
+ const __be32 *prop;
+
+ dt_root = ((unsigned long)initial_boot_params) +
+ be32_to_cpu(initial_boot_params->off_dt_struct);
+
+ prop = of_get_flat_dt_prop(dt_root, "reserved-ranges", &len);
+
+ if (!prop)
+ return false;
+
+ /* Each reserved range is an (address,size) pair, 2 cells each,
+ * totalling 4 cells per range. */
+ for (i = 0; i < len / (sizeof(*prop) * 4); i++) {
+ u64 base, size;
+
+ base = of_read_number(prop + (i * 4) + 0, 2);
+ size = of_read_number(prop + (i * 4) + 2, 2);
+
+ if (size)
+ memblock_reserve(base, size);
+ }
+
+ return true;
+}
+
static void __init early_reserve_mem(void)
{
u64 base, size;
@@ -574,6 +602,14 @@ static void __init early_reserve_mem(void)
self_size = initial_boot_params->totalsize;
memblock_reserve(self_base, self_size);
+ /*
+ * Try looking for reserved-regions property in the DT first; if
+ * it's present, it'll contain all of the necessary reservation
+ * info
+ */
+ if (early_reserve_mem_dt())
+ return;
+
#ifdef CONFIG_BLK_DEV_INITRD
/* then reserve the initrd, if any */
if (initrd_start && (initrd_end > initrd_start))
^ permalink raw reply related
* Re: [PATCH 1/1] usb: ehci-fsl: set INCR8 mode only on MPC512x
From: tiejun.chen @ 2013-04-24 3:13 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366772110-9620-1-git-send-email-tiejun.chen@windriver.com>
Sorry, please ignore this temporarily since looks this is already covered in tree.
I will look further into this to send another version.
Tiejun
On 04/24/2013 10:55 AM, Tiejun Chen wrote:
> commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
> on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
> INCR8 mode for system bus interface on MPC512x, but we should make sure
> this is only valid for MPC512x like other parts of this commit. Otherwise
> this would issue other platforms as abnormal without this similar Errata.
>
> Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
> ---
> drivers/usb/host/ehci-fsl.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
> index d81d2fc..f4f2a7b 100644
> --- a/drivers/usb/host/ehci-fsl.c
> +++ b/drivers/usb/host/ehci-fsl.c
> @@ -509,7 +509,15 @@ static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
> ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
> hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
>
> - ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
> + if (of_device_is_compatible(dev->parent->of_node,
> + "fsl,mpc5121-usb2-dr")) {
> + /*
> + * set SBUSCFG:AHBBRST so that control msgs don't
> + * fail when doing heavy PATA writes.
> + */
> + ehci_writel(ehci, SBUSCFG_INCR8,
> + hcd->regs + FSL_SOC_USB_SBUSCFG);
> + }
>
> /* restore EHCI registers */
> ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
>
^ permalink raw reply
* [PATCH 1/1] usb: ehci-fsl: set INCR8 mode only on MPC512x
From: Tiejun Chen @ 2013-04-24 2:55 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev, linux-kernel
commit 761bbcb7, "usb: ehci-fsl: set INCR8 mode for system bus interface
on MPC512x", introduced to fix one MPC5121e (M36P) Errata by setting
INCR8 mode for system bus interface on MPC512x, but we should make sure
this is only valid for MPC512x like other parts of this commit. Otherwise
this would issue other platforms as abnormal without this similar Errata.
Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
---
drivers/usb/host/ehci-fsl.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index d81d2fc..f4f2a7b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -509,7 +509,15 @@ static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
- ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
+ if (of_device_is_compatible(dev->parent->of_node,
+ "fsl,mpc5121-usb2-dr")) {
+ /*
+ * set SBUSCFG:AHBBRST so that control msgs don't
+ * fail when doing heavy PATA writes.
+ */
+ ehci_writel(ehci, SBUSCFG_INCR8,
+ hcd->regs + FSL_SOC_USB_SBUSCFG);
+ }
/* restore EHCI registers */
ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
--
1.7.9.5
^ permalink raw reply related
* [PATCH] Make CONFIG_BOOTX an exclusive early debug option
From: Alistair Popple @ 2013-04-24 2:16 UTC (permalink / raw)
To: linuxppc-dev
This patch makes the kernel configuration option "Support for early boot text
console (BootX or OpenFirmware only)" an exclusive choice under the "Early
debugging" menu. This prevents selection of two early debug consoles
simultaneously which does not appear to be supported by the code in
arch/powerpc/kernel/udbg.c.
Currently if two consoles are enabled the code in udbg.c selects one based on
the order in which initialisation functions are called which seems fairly
arbitrary.
For example if both CONFIG_BOOTX_TEXT and CONFIG_PPC_EARLY_DEBUG_LPAR are
enabled then the BootX console will be used. However if both CONFIG_BOOTX_TEXT
and CONFIG_PPC_EARLY_DEBUG_PS3GELIC are selected then the latter will be used.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 5416e28..659120c 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -122,13 +122,6 @@ config BDI_SWITCH
Unless you are intending to debug the kernel with one of these
machines, say N here.
-config BOOTX_TEXT
- bool "Support for early boot text console (BootX or OpenFirmware only)"
- depends on PPC_OF && PPC_BOOK3S
- help
- Say Y here to see progress messages from the boot firmware in text
- mode. Requires either BootX or Open Firmware.
-
config PPC_EARLY_DEBUG
bool "Early debugging (dangerous)"
help
@@ -147,6 +140,13 @@ choice
enable debugging for the wrong type of machine your kernel
_will not boot_.
+config BOOTX_TEXT
+ bool "Support for early boot text console (BootX or OpenFirmware only)"
+ depends on PPC_OF && PPC_BOOK3S
+ help
+ Say Y here to see progress messages from the boot firmware in text
+ mode. Requires either BootX or Open Firmware.
+
config PPC_EARLY_DEBUG_LPAR
bool "LPAR HV Console"
depends on PPC_PSERIES
^ permalink raw reply related
* Re: [PATCH] powerpc/spufs: Initialise inode->i_ino in spufs_new_inode()
From: Christoph Hellwig @ 2013-04-24 1:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Arnd Bergmann, linuxppc-dev, viro, dchinner, Christoph Hellwig,
Jeremy Kerr
In-Reply-To: <1366766214.12131.27.camel@pasglop>
Looks good.
^ permalink raw reply
* Re: [PATCH 5/5] powerpc/powernv: TCE invalidation for PHB3
From: Gavin Shan @ 2013-04-24 1:32 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1366730708.12131.7.camel@pasglop>
On Wed, Apr 24, 2013 at 01:25:08AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>> * of flags if that becomes the case
>> */
>> if (tbl->it_type & TCE_PCI_SWINV_CREATE)
>> - pnv_tce_invalidate(tbl, tces, tcep - 1);
>> + phb->dma_tce_invalidate(tbl, tces, tcep - 1);
>>
>> return 0;
>> }
>
>TCE invalidate is very performance sensitive, we might be better off
>doing the if (ioda_type == PNV_PHB_IODA1) ... else ... here (which
>the CPU can generally predict) rather than a function pointer call
>which can be more tricky.
>
Ok. I'll change it in next version ;-)
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH 4/5] powerpc/powernv: Patch MSI EOI handler on P8
From: Gavin Shan @ 2013-04-24 1:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1366730513.12131.5.camel@pasglop>
On Wed, Apr 24, 2013 at 01:21:53AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>>
>> +static int pnv_pci_ioda_msi_eoi(struct pnv_phb *phb, unsigned int hw_irq)
>> +{
>> + u8 p_bit = 1, q_bit = 1;
>> + long rc;
>> +
>> + while (p_bit || q_bit) {
>> + rc = opal_pci_get_xive_reissue(phb->opal_id,
>> + hw_irq - phb->msi_base, &p_bit, &q_bit);
>> + if (rc) {
>> + pr_warning("%s: Failed to get P/Q bits of IRQ#%d "
>> + "on PHB#%d, rc=%ld\n", __func__, hw_irq,
>> + phb->hose->global_number, rc);
>> + return -EIO;
>> + }
>> + if (!p_bit && !q_bit)
>> + break;
>> +
>> + rc = opal_pci_set_xive_reissue(phb->opal_id,
>> + hw_irq - phb->msi_base, p_bit, q_bit);
>> + if (rc) {
>> + pr_warning("%s: Failed to clear P/Q (%01d/%01d) of "
>> + "IRQ#%d on PHB#%d, rc=%ld\n", __func__,
>> + p_bit, q_bit, hw_irq,
>> + phb->hose->global_number, rc);
>> + return -EIO;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>
>Can you turn that into a single opal_pci_msi_eoi() ? This means that a
>single MSI will trigger only one OPAL call rather than two which is
>better for performances.
>
Ok. I will add new OPAL API opal_pci_msi_eoi() and use that in next version.
>We will later implement an "optimized" variant using direct MMIO based
>on knowing specifically the HW type but not now.
>
Ok :-)
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/powernv: Supports PHB3
From: Gavin Shan @ 2013-04-24 1:29 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1366730340.12131.3.camel@pasglop>
On Wed, Apr 24, 2013 at 01:19:00AM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-04-23 at 19:03 +0800, Gavin Shan wrote:
>> -/* Fixup wrong class code in p7ioc root complex */
>> +/* Fixup wrong class code in p7ioc and p8 root complex */
>> static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
>> {
>> dev->class = PCI_CLASS_BRIDGE_PCI << 8;
>> }
>> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
>> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x2da, pnv_p7ioc_rc_quirk);
>>
>This can go away from the normal patch, it is only necessary to work
>around a problem in the simulator. The real PHB3 doesn't need the
>workaround (p7ioc still does).
>
Ok. I'll remove it in next version ;-)
Thanks,
Gavin
^ permalink raw reply
* Re: [PATCH] powerpc/spufs: Initialise inode->i_ino in spufs_new_inode()
From: Benjamin Herrenschmidt @ 2013-04-24 1:16 UTC (permalink / raw)
To: Michael Ellerman
Cc: Arnd Bergmann, linuxppc-dev, viro, dchinner, Christoph Hellwig,
Jeremy Kerr
In-Reply-To: <1366765994-13486-1-git-send-email-michael@ellerman.id.au>
On Wed, 2013-04-24 at 11:13 +1000, Michael Ellerman wrote:
> In commit 85fe402 (fs: do not assign default i_ino in new_inode), the
> initialisation of i_ino was removed from new_inode() and pushed down
> into the callers. However spufs_new_inode() was not updated.
>
> This exhibits as no files appearing in /spu, because all our dirents
> have a zero inode, which readdir() seems to dislike.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Christoph/Al, can I have an Ack for this before I shoot it to Linus ?
Thanks !
Cheers,
Ben.
---
> arch/powerpc/platforms/cell/spufs/inode.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/powerpc/platforms/cell/spufs/inode.c
b/arch/powerpc/platforms/cell/spufs/inode.c
> index 3f3bb4c..35f77a4 100644
> --- a/arch/powerpc/platforms/cell/spufs/inode.c
> +++ b/arch/powerpc/platforms/cell/spufs/inode.c
> @@ -99,6 +99,7 @@ spufs_new_inode(struct super_block *sb, umode_t
mode)
> if (!inode)
> goto out;
>
> + inode->i_ino = get_next_ino();
> inode->i_mode = mode;
> inode->i_uid = current_fsuid();
> inode->i_gid = current_fsgid();
>
^ permalink raw reply
* [PATCH] powerpc/spufs: Initialise inode->i_ino in spufs_new_inode()
From: Michael Ellerman @ 2013-04-24 1:13 UTC (permalink / raw)
To: linuxppc-dev
Cc: Arnd Bergmann, viro, dchinner, Christoph Hellwig, Jeremy Kerr
In commit 85fe402 (fs: do not assign default i_ino in new_inode), the
initialisation of i_ino was removed from new_inode() and pushed down
into the callers. However spufs_new_inode() was not updated.
This exhibits as no files appearing in /spu, because all our dirents
have a zero inode, which readdir() seems to dislike.
Cc: stable@vger.kernel.org
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/platforms/cell/spufs/inode.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 3f3bb4c..35f77a4 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -99,6 +99,7 @@ spufs_new_inode(struct super_block *sb, umode_t mode)
if (!inode)
goto out;
+ inode->i_ino = get_next_ino();
inode->i_mode = mode;
inode->i_uid = current_fsuid();
inode->i_gid = current_fsgid();
--
1.7.10.4
^ permalink raw reply related
* [PATCH] arch: powerpc: mm: make mmap_64.c compile on 32bit powerpc
From: Daniel Walker @ 2013-04-24 0:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Paul Mackerras
There appears to be no good reason to keep this as 64bit only. It works
on 32bit also, and has checks so that it can work correctly with 32bit
binaries on 64bit hardware which is why I think this works.
I tested this on qemu using the virtex-ml507 machine type.
Before,
/bin2 # ./test & cat /proc/${!}/maps
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
48000000-48020000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
48021000-48023000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bfd03000-bfd24000 rw-p 00000000 00:00 0 [stack]
/bin2 # ./test & cat /proc/${!}/maps
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
0fe6e000-0ffd8000 r-xp 00000000 00:01 214 /lib/libc-2.11.3.so
0ffd8000-0ffe8000 ---p 0016a000 00:01 214 /lib/libc-2.11.3.so
0ffe8000-0ffed000 rw-p 0016a000 00:01 214 /lib/libc-2.11.3.so
0ffed000-0fff0000 rw-p 00000000 00:00 0
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
48000000-48020000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
48020000-48021000 rw-p 00000000 00:00 0
48021000-48023000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bf98a000-bf9ab000 rw-p 00000000 00:00 0 [stack]
/bin2 # ./test & cat /proc/${!}/maps
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
0fe6e000-0ffd8000 r-xp 00000000 00:01 214 /lib/libc-2.11.3.so
0ffd8000-0ffe8000 ---p 0016a000 00:01 214 /lib/libc-2.11.3.so
0ffe8000-0ffed000 rw-p 0016a000 00:01 214 /lib/libc-2.11.3.so
0ffed000-0fff0000 rw-p 00000000 00:00 0
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
48000000-48020000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
48020000-48021000 rw-p 00000000 00:00 0
48021000-48023000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bfa54000-bfa75000 rw-p 00000000 00:00 0 [stack]
After,
bash-4.1# ./test & cat /proc/${!}/maps
[7] 803
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
b7eb0000-b7ed0000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
b7ed1000-b7ed3000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bfbc0000-bfbe1000 rw-p 00000000 00:00 0 [stack]
bash-4.1# ./test & cat /proc/${!}/maps
[8] 805
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
b7b03000-b7b23000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
b7b24000-b7b26000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bfc27000-bfc48000 rw-p 00000000 00:00 0 [stack]
bash-4.1# ./test & cat /proc/${!}/maps
[9] 807
00100000-00103000 r-xp 00000000 00:00 0 [vdso]
10000000-10007000 r-xp 00000000 00:01 454 /bin2/test
10017000-10018000 rw-p 00007000 00:01 454 /bin2/test
b7f37000-b7f57000 r-xp 00000000 00:01 224 /lib/ld-2.11.3.so
b7f58000-b7f5a000 rw-p 00021000 00:01 224 /lib/ld-2.11.3.so
bff96000-bffb7000 rw-p 00000000 00:00 0 [stack]
Signed-off-by: Daniel Walker <dwalker@fifo90.com>
---
arch/powerpc/include/asm/processor.h | 2 -
arch/powerpc/mm/Makefile | 5 +-
arch/powerpc/mm/mmap.c | 101 ++++++++++++++++++++++++++++++++++
arch/powerpc/mm/mmap_64.c | 101 ----------------------------------
4 files changed, 103 insertions(+), 106 deletions(-)
create mode 100644 arch/powerpc/mm/mmap.c
delete mode 100644 arch/powerpc/mm/mmap_64.c
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 7ff9eaa..6ef17bd 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -402,9 +402,7 @@ static inline void prefetchw(const void *x)
#define spin_lock_prefetch(x) prefetchw(x)
-#ifdef CONFIG_PPC64
#define HAVE_ARCH_PICK_MMAP_LAYOUT
-#endif
#ifdef CONFIG_PPC64
static inline unsigned long get_clean_sp(struct pt_regs *regs, int is_32)
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index cf16b57..26f29a7 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -6,17 +6,16 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
-obj-y := fault.o mem.o pgtable.o gup.o \
+obj-y := fault.o mem.o pgtable.o gup.o mmap.o \
init_$(CONFIG_WORD_SIZE).o \
pgtable_$(CONFIG_WORD_SIZE).o
obj-$(CONFIG_PPC_MMU_NOHASH) += mmu_context_nohash.o tlb_nohash.o \
tlb_nohash_low.o
obj-$(CONFIG_PPC_BOOK3E) += tlb_low_$(CONFIG_WORD_SIZE)e.o
-obj-$(CONFIG_PPC64) += mmap_64.o
hash64-$(CONFIG_PPC_NATIVE) := hash_native_64.o
obj-$(CONFIG_PPC_STD_MMU_64) += hash_utils_64.o \
slb_low.o slb.o stab.o \
- mmap_64.o $(hash64-y)
+ $(hash64-y)
obj-$(CONFIG_PPC_STD_MMU_32) += ppc_mmu_32.o
obj-$(CONFIG_PPC_STD_MMU) += hash_low_$(CONFIG_WORD_SIZE).o \
tlb_hash$(CONFIG_WORD_SIZE).o \
diff --git a/arch/powerpc/mm/mmap.c b/arch/powerpc/mm/mmap.c
new file mode 100644
index 0000000..67a42ed
--- /dev/null
+++ b/arch/powerpc/mm/mmap.c
@@ -0,0 +1,101 @@
+/*
+ * flexible mmap layout support
+ *
+ * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
+ * All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ *
+ * Started by Ingo Molnar <mingo@elte.hu>
+ */
+
+#include <linux/personality.h>
+#include <linux/mm.h>
+#include <linux/random.h>
+#include <linux/sched.h>
+
+/*
+ * Top of mmap area (just below the process stack).
+ *
+ * Leave at least a ~128 MB hole on 32bit applications.
+ *
+ * On 64bit applications we randomise the stack by 1GB so we need to
+ * space our mmap start address by a further 1GB, otherwise there is a
+ * chance the mmap area will end up closer to the stack than our ulimit
+ * requires.
+ */
+#define MIN_GAP32 (128*1024*1024)
+#define MIN_GAP64 ((128 + 1024)*1024*1024UL)
+#define MIN_GAP ((is_32bit_task()) ? MIN_GAP32 : MIN_GAP64)
+#define MAX_GAP (TASK_SIZE/6*5)
+
+static inline int mmap_is_legacy(void)
+{
+ if (current->personality & ADDR_COMPAT_LAYOUT)
+ return 1;
+
+ if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
+ return 1;
+
+ return sysctl_legacy_va_layout;
+}
+
+static unsigned long mmap_rnd(void)
+{
+ unsigned long rnd = 0;
+
+ if (current->flags & PF_RANDOMIZE) {
+ /* 8MB for 32bit, 1GB for 64bit */
+ if (is_32bit_task())
+ rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
+ else
+ rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
+ }
+ return rnd << PAGE_SHIFT;
+}
+
+static inline unsigned long mmap_base(void)
+{
+ unsigned long gap = rlimit(RLIMIT_STACK);
+
+ if (gap < MIN_GAP)
+ gap = MIN_GAP;
+ else if (gap > MAX_GAP)
+ gap = MAX_GAP;
+
+ return PAGE_ALIGN(TASK_SIZE - gap - mmap_rnd());
+}
+
+/*
+ * This function, called very early during the creation of a new
+ * process VM image, sets up which VM layout function to use:
+ */
+void arch_pick_mmap_layout(struct mm_struct *mm)
+{
+ /*
+ * Fall back to the standard layout if the personality
+ * bit is set, or if the expected stack growth is unlimited:
+ */
+ if (mmap_is_legacy()) {
+ mm->mmap_base = TASK_UNMAPPED_BASE;
+ mm->get_unmapped_area = arch_get_unmapped_area;
+ mm->unmap_area = arch_unmap_area;
+ } else {
+ mm->mmap_base = mmap_base();
+ mm->get_unmapped_area = arch_get_unmapped_area_topdown;
+ mm->unmap_area = arch_unmap_area_topdown;
+ }
+}
diff --git a/arch/powerpc/mm/mmap_64.c b/arch/powerpc/mm/mmap_64.c
deleted file mode 100644
index 67a42ed..0000000
--- a/arch/powerpc/mm/mmap_64.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * flexible mmap layout support
- *
- * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- *
- * Started by Ingo Molnar <mingo@elte.hu>
- */
-
-#include <linux/personality.h>
-#include <linux/mm.h>
-#include <linux/random.h>
-#include <linux/sched.h>
-
-/*
- * Top of mmap area (just below the process stack).
- *
- * Leave at least a ~128 MB hole on 32bit applications.
- *
- * On 64bit applications we randomise the stack by 1GB so we need to
- * space our mmap start address by a further 1GB, otherwise there is a
- * chance the mmap area will end up closer to the stack than our ulimit
- * requires.
- */
-#define MIN_GAP32 (128*1024*1024)
-#define MIN_GAP64 ((128 + 1024)*1024*1024UL)
-#define MIN_GAP ((is_32bit_task()) ? MIN_GAP32 : MIN_GAP64)
-#define MAX_GAP (TASK_SIZE/6*5)
-
-static inline int mmap_is_legacy(void)
-{
- if (current->personality & ADDR_COMPAT_LAYOUT)
- return 1;
-
- if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
- return 1;
-
- return sysctl_legacy_va_layout;
-}
-
-static unsigned long mmap_rnd(void)
-{
- unsigned long rnd = 0;
-
- if (current->flags & PF_RANDOMIZE) {
- /* 8MB for 32bit, 1GB for 64bit */
- if (is_32bit_task())
- rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
- else
- rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
- }
- return rnd << PAGE_SHIFT;
-}
-
-static inline unsigned long mmap_base(void)
-{
- unsigned long gap = rlimit(RLIMIT_STACK);
-
- if (gap < MIN_GAP)
- gap = MIN_GAP;
- else if (gap > MAX_GAP)
- gap = MAX_GAP;
-
- return PAGE_ALIGN(TASK_SIZE - gap - mmap_rnd());
-}
-
-/*
- * This function, called very early during the creation of a new
- * process VM image, sets up which VM layout function to use:
- */
-void arch_pick_mmap_layout(struct mm_struct *mm)
-{
- /*
- * Fall back to the standard layout if the personality
- * bit is set, or if the expected stack growth is unlimited:
- */
- if (mmap_is_legacy()) {
- mm->mmap_base = TASK_UNMAPPED_BASE;
- mm->get_unmapped_area = arch_get_unmapped_area;
- mm->unmap_area = arch_unmap_area;
- } else {
- mm->mmap_base = mmap_base();
- mm->get_unmapped_area = arch_get_unmapped_area_topdown;
- mm->unmap_area = arch_unmap_area_topdown;
- }
-}
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500
From: Scott Wood @ 2013-04-24 0:04 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366368468-29143-12-git-send-email-chenhui.zhao@freescale.com>
On 04/19/2013 05:47:45 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
>=20
> For e6500, two threads in one core share one time base. Just need
> to do time base sync on first thread of one core, and skip it on
> the other thread.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/platforms/85xx/smp.c | 52 =20
> +++++++++++++++++++++++++++++++-----
> 1 files changed, 44 insertions(+), 8 deletions(-)
>=20
> diff --git a/arch/powerpc/platforms/85xx/smp.c =20
> b/arch/powerpc/platforms/85xx/smp.c
> index 74d8cde..5f3eee3 100644
> --- a/arch/powerpc/platforms/85xx/smp.c
> +++ b/arch/powerpc/platforms/85xx/smp.c
> @@ -26,6 +26,7 @@
> #include <asm/cacheflush.h>
> #include <asm/dbell.h>
> #include <asm/fsl_guts.h>
> +#include <asm/cputhreads.h>
>=20
> #include <sysdev/fsl_soc.h>
> #include <sysdev/mpic.h>
> @@ -45,6 +46,7 @@ static u64 timebase;
> static int tb_req;
> static int tb_valid;
> static u32 cur_booting_core;
> +static bool rcpmv2;
>=20
> #ifdef CONFIG_PPC_E500MC
> /* get a physical mask of online cores and booting core */
> @@ -53,26 +55,40 @@ static inline u32 get_phy_cpu_mask(void)
> u32 mask;
> int cpu;
>=20
> - mask =3D 1 << cur_booting_core;
> - for_each_online_cpu(cpu)
> - mask |=3D 1 << get_hard_smp_processor_id(cpu);
> + if (smt_capable()) {
> + /* two threads in one core share one time base */
> + mask =3D 1 << cpu_core_index_of_thread(cur_booting_core);
> + for_each_online_cpu(cpu)
> + mask |=3D 1 << cpu_core_index_of_thread(
> + get_hard_smp_processor_id(cpu));
> + } else {
> + mask =3D 1 << cur_booting_core;
> + for_each_online_cpu(cpu)
> + mask |=3D 1 << get_hard_smp_processor_id(cpu);
> + }
Where is smt_capable defined()? I assume somewhere in the patchset but =20
it's a pain to search 12 patches...
Is this really about whether we're SMT-capable or whether we have rcpm =20
v2?
-Scott=
^ permalink raw reply
* Re: [PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cache operation
From: Scott Wood @ 2013-04-24 0:00 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366368468-29143-13-git-send-email-chenhui.zhao@freescale.com>
On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
>=20
> The L1 Data Cache of e6500 contains no modified data, no flush
> is required.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
> ---
> arch/powerpc/kernel/fsl_booke_cache.S | 11 ++++++++++-
> 1 files changed, 10 insertions(+), 1 deletions(-)
>=20
> diff --git a/arch/powerpc/kernel/fsl_booke_cache.S =20
> b/arch/powerpc/kernel/fsl_booke_cache.S
> index 232c47b..24a52bb 100644
> --- a/arch/powerpc/kernel/fsl_booke_cache.S
> +++ b/arch/powerpc/kernel/fsl_booke_cache.S
> @@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1)
>=20
> blr
>=20
> +#define PVR_E6500 0x8040
> +
> /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
> _GLOBAL(__flush_disable_L1)
> +/* L1 Data Cache of e6500 contains no modified data, no flush is =20
> required */
> + mfspr r3, SPRN_PVR
> + rlwinm r4, r3, 16, 0xffff
> + lis r5, 0
> + ori r5, r5, PVR_E6500@l
> + cmpw r4, r5
> + beq 2f
> mflr r10
> bl flush_dcache_L1 /* Flush L1 d-cache */
> mtlr r10
>=20
> - msync
> +2: msync
> mfspr r4, SPRN_L1CSR0 /* Invalidate and disable d-cache */
> li r5, 2
> rlwimi r4, r5, 0, 3
Note that disabling the cache is a core operation, rather than a thread =20
operation. Is this only called when the second thread is disabled?
-Scott=
^ permalink raw reply
* Re: [PATCH v2 07/15] powerpc/85xx: add time base sync for SoCs based on e500mc/e5500
From: Scott Wood @ 2013-04-23 23:58 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366368468-29143-7-git-send-email-chenhui.zhao@freescale.com>
On 04/19/2013 05:47:40 AM, Zhao Chenhui wrote:
> From: Chen-Hui Zhao <chenhui.zhao@freescale.com>
>=20
> In the case of SMP, during the time base sync period, all time bases =20
> of
> online cores must stop, then start simultaneously.
>=20
> There is a RCPM (Run Control/Power Management) module in CoreNet =20
> based SoCs.
> Define a struct ccsr_rcpm to describe the register map.
>=20
> This patch supports SoCs based on e500mc/e5500, such as P4080, P5020,
> etc.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/include/asm/fsl_guts.h | 38 =20
> +++++++++++++++++++++++++++++++++++
> arch/powerpc/platforms/85xx/smp.c | 32 =20
> +++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/include/asm/fsl_guts.h =20
> b/arch/powerpc/include/asm/fsl_guts.h
> index 77ced0b..4eac1cf 100644
> --- a/arch/powerpc/include/asm/fsl_guts.h
> +++ b/arch/powerpc/include/asm/fsl_guts.h
> @@ -106,6 +106,44 @@ struct ccsr_guts {
> /* Alternate function signal multiplex control */
> #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
>=20
> +struct ccsr_rcpm {
> + u8 res0000[4];
> + __be32 cdozsr; /* 0x0004 - Core Doze Status Register */
> + u8 res0008[4];
> + __be32 cdozcr; /* 0x000c - Core Doze Control Register =20
> */
> + u8 res0010[4];
> + __be32 cnapsr; /* 0x0014 - Core Nap Status Register */
> + u8 res0018[4];
> + __be32 cnapcr; /* 0x001c - Core Nap Control Register */
> + u8 res0020[4];
> + __be32 cdozpsr; /* 0x0024 - Core Doze Previous Status =20
> Register */
> + u8 res0028[4];
> + __be32 cnappsr; /* 0x002c - Core Nap Previous Status =20
> Register */
> + u8 res0030[4];
> + __be32 cwaitsr; /* 0x0034 - Core Wait Status Register */
> + u8 res0038[4];
> + __be32 cwdtdsr; /* 0x003c - Core watchdog detect status =20
> register */
> + __be32 powmgtcsr; /* 0x0040 - Power Mangement Control & =20
> Status Register */
> + u8 res0044[12];
> + __be32 ippdexpcr; /* 0x0050 - IP Powerdown Exception =20
> Control Register */
> + u8 res0054[16];
> + __be32 cpmimr; /* 0x0064 - Core PM IRQ Mask Register */
> + u8 res0068[4];
> + __be32 cpmcimr; /* 0x006c - Core PM Critical IRQ Mask =20
> Register */
> + u8 res0070[4];
> + __be32 cpmmcmr; /* 0x0074 - Core PM Machine Check Mask =20
> Register */
> + u8 res0078[4];
> + __be32 cpmnmimr; /* 0x007c - Core PM NMI Mask Register */
> + u8 res0080[4];
> + __be32 ctbenr; /* 0x0084 - Core Time Base Enable =20
> Register */
> + u8 res0088[4];
> + __be32 ctbckselr; /* 0x008c - Core Time Base Clock Select =20
> Register */
> + u8 res0090[4];
> + __be32 ctbhltcr; /* 0x0094 - Core Time Base Halt Control =20
> Register */
> + u8 res0098[4];
> + __be32 cmcpmaskcr; /* 0x00a4 - Core machine check mask =20
> control register */
> +};
> +
> #ifdef CONFIG_PPC_86xx
>=20
> #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA =20
> controller/channel set to SSI */
> diff --git a/arch/powerpc/platforms/85xx/smp.c =20
> b/arch/powerpc/platforms/85xx/smp.c
> index 6a17599..6c2fe6b 100644
> --- a/arch/powerpc/platforms/85xx/smp.c
> +++ b/arch/powerpc/platforms/85xx/smp.c
> @@ -44,7 +44,36 @@ static struct ccsr_guts __iomem *guts;
> static u64 timebase;
> static int tb_req;
> static int tb_valid;
> +static u32 cur_booting_core;
>=20
> +#ifdef CONFIG_PPC_E500MC
> +/* get a physical mask of online cores and booting core */
> +static inline u32 get_phy_cpu_mask(void)
> +{
> + u32 mask;
> + int cpu;
> +
> + mask =3D 1 << cur_booting_core;
> + for_each_online_cpu(cpu)
> + mask |=3D 1 << get_hard_smp_processor_id(cpu);
> +
> + return mask;
> +}
> +
> +static void mpc85xx_timebase_freeze(int freeze)
> +{
> + struct ccsr_rcpm __iomem *rcpm =3D (typeof(rcpm))guts;
> + u32 mask =3D get_phy_cpu_mask();
> +
> + if (freeze)
> + clrbits32(&rcpm->ctbenr, mask);
> + else
> + setbits32(&rcpm->ctbenr, mask);
> +
> + /* read back to push the previos write */
> + in_be32(&rcpm->ctbenr);
> +}
> +#else
Please determine the timebase sync implementation at runtime, rather =20
than relying on our current inability to have e500v2 and e500mc in the =20
same kernel. e6500 will be different from e5500, but both can be in =20
the same kernel image.
-Scott=
^ permalink raw reply
* Re: [PATCH v2 02/15] powerpc/85xx: add sleep and deep sleep support
From: Scott Wood @ 2013-04-23 23:53 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366368468-29143-2-git-send-email-chenhui.zhao@freescale.com>
On 04/19/2013 05:47:35 AM, Zhao Chenhui wrote:
> static int pmc_suspend_enter(suspend_state_t state)
> {
> - int ret;
> + int ret =3D 0;
> +
> + switch (state) {
> +#ifdef CONFIG_PPC_85xx
> + case PM_SUSPEND_MEM:
> +#ifdef CONFIG_SPE
> + enable_kernel_spe();
> +#endif
> + enable_kernel_fp();
Why does enable_kernel_spe() need an ifdef but enable_kernel_fp() =20
doesn't?
> + case PM_SUSPEND_STANDBY:
> +#ifdef CONFIG_FSL_SOC_BOOKE
> + flush_dcache_L1();
> +#endif
> + setbits32(&pmc_regs->powmgtcsr, POWMGTCSR_SLP);
Only L1, even on e500mc?
-Scott=
^ permalink raw reply
* Re: [PATCH v2 01/15] powerpc/85xx: cache operations for Freescale SoCs based on BOOK3E
From: Scott Wood @ 2013-04-23 23:46 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1366368468-29143-1-git-send-email-chenhui.zhao@freescale.com>
On 04/19/2013 05:47:34 AM, Zhao Chenhui wrote:
> These cache operations support Freescale SoCs based on BOOK3E.
> Move L1 cache operations to fsl_booke_cache.S in order to maintain
> easily. And, add cache operations for backside L2 cache and platform =20
> cache.
>=20
> The backside L2 cache appears on e500mc and e5500 core. The platform =20
> cache
> supported by this patch is L2 Look-Aside Cache, which appears on SoCs
> with e500v1/e500v2 core, such as MPC8572, P1020, etc.
>=20
> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> arch/powerpc/include/asm/cacheflush.h | 8 ++
> arch/powerpc/kernel/Makefile | 1 +
> arch/powerpc/kernel/fsl_booke_cache.S | 210 =20
> +++++++++++++++++++++++++++++++++
> arch/powerpc/kernel/head_fsl_booke.S | 74 ------------
> 4 files changed, 219 insertions(+), 74 deletions(-)
> create mode 100644 arch/powerpc/kernel/fsl_booke_cache.S
>=20
> diff --git a/arch/powerpc/include/asm/cacheflush.h =20
> b/arch/powerpc/include/asm/cacheflush.h
> index b843e35..bc3f937 100644
> --- a/arch/powerpc/include/asm/cacheflush.h
> +++ b/arch/powerpc/include/asm/cacheflush.h
> @@ -32,6 +32,14 @@ extern void flush_dcache_page(struct page *page);
>=20
> extern void __flush_disable_L1(void);
>=20
> +#ifdef CONFIG_FSL_SOC_BOOKE
> +void flush_dcache_L1(void);
> +void flush_backside_L2_cache(void);
> +void disable_backside_L2_cache(void);
> +void flush_disable_L2(void);
> +void invalidate_enable_L2(void);
> +#endif
Don't ifdef prototypes unless there's a good reason, such as providing =20
an inline alternative.
Why do you have "flush_backside_L2_cache" and =20
"disable_backside_L2_cache" as something different from =20
"flush_disable_L2"? The latter should flush whatever L2 is present. =20
Don't treat pre-corenet as the default.
Why do we even need to distinguish L1 from L2 at all? Shouldn't the =20
function that gets exposed just be "flush and disable data caches that =20
are specific to this cpu"? What should happen on e6500?
-Scott=
^ permalink raw reply
* Re: [PATCH v3 1/12] Create a powerpc update_devicetree interface
From: Benjamin Herrenschmidt @ 2013-04-23 20:54 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <5176D715.4060606@linux.vnet.ibm.com>
On Tue, 2013-04-23 at 13:46 -0500, Nathan Fontenot wrote:
> ok, good. I was not crazy about using ppc_md to do this and if you're fine
> with putting the pseries specific stuff in ifdef CONFIG_PPC_PSERIES I'll
> update the code to do that.
>
> Question concerning rtas code. There is quite a bit of pseries specific
> pieces in the general powerpc/kernel directory. Has there been, or should
> there be, any effort to move that to the pseries directory?
It's a good question ... it's shared in part with CHRP, it might make
sense to split it but only if the split can be done cleanly, which I
haven't looked into.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH v3 12/12] Add /proc interface to control topology updates
From: Nathan Fontenot @ 2013-04-23 18:59 UTC (permalink / raw)
To: Michael Ellerman; +Cc: Stephen Rothwell, linuxppc-dev
In-Reply-To: <20130423024951.GA20902@concordia>
On 04/22/2013 09:49 PM, Michael Ellerman wrote:
> On Tue, Apr 23, 2013 at 12:00:26PM +1000, Stephen Rothwell wrote:
>> Hi Nathan,
>>
>> On Mon, 22 Apr 2013 13:47:55 -0500 Nathan Fontenot <nfont@linux.vnet.ibm.com> wrote:
>>>
>>> #if defined(CONFIG_NUMA) && defined(CONFIG_PPC_SPLPAR)
>>> extern int start_topology_update(void);
>>> extern int stop_topology_update(void);
>>> +extern inline int prrn_is_enabled(void);
>>
>> You really can't do "extern inline" with no body ...
>
> No you can't, and at least with my compiler it causes a build error.
>
Easy enough, no more inline for this.
This for looking,
-Nathan
^ permalink raw reply
* Re: [PATCH v3 7/12] Use stop machine to update cpu maps
From: Nathan Fontenot @ 2013-04-23 18:58 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1366676688.2886.5.camel@pasglop>
On 04/22/2013 07:24 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2013-04-22 at 13:41 -0500, Nathan Fontenot wrote:
>> From: Jesse Larrew <jlarrew@linux.vnet.ibm.com>
>>
>> Platform events such as partition migration or the new PRRN firmware
>> feature can cause the NUMA characteristics of a CPU to change, and these
>> changes will be reflected in the device tree nodes for the affected
>> CPUs.
>>
>> This patch registers a handler for Open Firmware device tree updates
>> and reconfigures the CPU and node maps whenever the associativity
>> changes. Currently, this is accomplished by marking the affected CPUs in
>> the cpu_associativity_changes_mask and allowing
>> arch_update_cpu_topology() to retrieve the new associativity information
>> using hcall_vphn().
>>
>> Protecting the NUMA cpu maps from concurrent access during an update
>> operation will be addressed in a subsequent patch in this series.
>
> I see no more mention of stop_machine() ... is the patch subject stale ?
>
Nope, just me mistakenly putting the wrong subject for this patch. I'll
correct it in the next version.
-Nathan
^ permalink raw reply
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