* RE: [PATCH 1/2 v15] iommu/fsl: Add additional iommu attributes required by the PAMU driver.
From: Sethi Varun-B16395 @ 2013-04-30 17:09 UTC (permalink / raw)
To: joro@8bytes.org, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
galak@kernel.crashing.org, benh@kernel.crashing.org,
Yoder Stuart-B08248, Wood Scott-B07421
In-Reply-To: <1366803351-17429-1-git-send-email-Varun.Sethi@freescale.com>
Hi Joerg,
Would you take this patchset for 3.10 merge?
Regards
Varun
> -----Original Message-----
> From: Sethi Varun-B16395
> Sent: Wednesday, April 24, 2013 5:06 PM
> To: joro@8bytes.org; iommu@lists.linux-foundation.org; linuxppc-
> dev@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> galak@kernel.crashing.org; benh@kernel.crashing.org; Yoder Stuart-B08248;
> Wood Scott-B07421
> Cc: Sethi Varun-B16395
> Subject: [PATCH 1/2 v15] iommu/fsl: Add additional iommu attributes
> required by the PAMU driver.
>=20
> Added the following domain attributes for the FSL PAMU driver:
> 1. Added new iommu stash attribute, which allows setting of the
> LIODN specific stash id parameter through IOMMU API.
> 2. Added an attribute for enabling/disabling DMA to a particular
> memory window.
> 3. Added domain attribute to check for PAMUV1 specific constraints.
>=20
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> ---
> v15 changes:
> - Moved fsl_pamu_stash.h under arch/powerpc/include/asm.
> v14 changes:
> - Add FSL prefix to PAMU attributes.
> v13 changes:
> - created a new file include/linux/fsl_pamu_stash.h for stash attributes.
> v12 changes:
> - Moved PAMU specifc stash ids and structures to PAMU header file.
> - no change in v11.
> - no change in v10.
> arch/powerpc/include/asm/fsl_pamu_stash.h | 39
> +++++++++++++++++++++++++++++
> include/linux/iommu.h | 16 ++++++++++++
> 2 files changed, 55 insertions(+), 0 deletions(-) create mode 100644
> arch/powerpc/include/asm/fsl_pamu_stash.h
>=20
> diff --git a/arch/powerpc/include/asm/fsl_pamu_stash.h
> b/arch/powerpc/include/asm/fsl_pamu_stash.h
> new file mode 100644
> index 0000000..caa1b21
> --- /dev/null
> +++ b/arch/powerpc/include/asm/fsl_pamu_stash.h
> @@ -0,0 +1,39 @@
> +/*
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License, version 2, as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
> USA.
> + *
> + * Copyright (C) 2013 Freescale Semiconductor, Inc.
> + *
> + */
> +
> +#ifndef __FSL_PAMU_STASH_H
> +#define __FSL_PAMU_STASH_H
> +
> +/* cache stash targets */
> +enum pamu_stash_target {
> + PAMU_ATTR_CACHE_L1 =3D 1,
> + PAMU_ATTR_CACHE_L2,
> + PAMU_ATTR_CACHE_L3,
> +};
> +
> +/*
> + * This attribute allows configuring stashig specific parameters
> + * in the PAMU hardware.
> + */
> +
> +struct pamu_stash_attribute {
> + u32 cpu; /* cpu number */
> + u32 cache; /* cache to stash to: L1,L2,L3 */
> +};
> +
> +#endif /* __FSL_PAMU_STASH_H */
> diff --git a/include/linux/iommu.h b/include/linux/iommu.h index
> 2727810..313d17a 100644
> --- a/include/linux/iommu.h
> +++ b/include/linux/iommu.h
> @@ -57,10 +57,26 @@ struct iommu_domain {
> #define IOMMU_CAP_CACHE_COHERENCY 0x1
> #define IOMMU_CAP_INTR_REMAP 0x2 /* isolates device intrs */
>=20
> +/*
> + * Following constraints are specifc to FSL_PAMUV1:
> + * -aperture must be power of 2, and naturally aligned
> + * -number of windows must be power of 2, and address space size
> + * of each window is determined by aperture size / # of windows
> + * -the actual size of the mapped region of a window must be power
> + * of 2 starting with 4KB and physical address must be naturally
> + * aligned.
> + * DOMAIN_ATTR_FSL_PAMUV1 corresponds to the above mentioned contraints.
> + * The caller can invoke iommu_domain_get_attr to check if the
> +underlying
> + * iommu implementation supports these constraints.
> + */
> +
> enum iommu_attr {
> DOMAIN_ATTR_GEOMETRY,
> DOMAIN_ATTR_PAGING,
> DOMAIN_ATTR_WINDOWS,
> + DOMAIN_ATTR_FSL_PAMU_STASH,
> + DOMAIN_ATTR_FSL_PAMU_ENABLE,
> + DOMAIN_ATTR_FSL_PAMUV1,
> DOMAIN_ATTR_MAX,
> };
>=20
> --
> 1.7.4.1
^ permalink raw reply
* flush_icache_range on AMCC 44x targets
From: Mike @ 2013-04-30 12:17 UTC (permalink / raw)
To: linuxppc-dev
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Hi,
i was reading trough arch/powerpc/kernel/misc32.S looking at the icbi and
iccci instructions, from whats on print in
http://s.eeweb.com/members/kvks_kumar/answers/1356585717-PPC440_UM2013.pdf(page
272) iccci should be used once in the power-on / reset routine, and
as far as flush_icache_range goes presumably before icbi is called?
So should not flush_icache_range go
#ifdef CONFIG_44x
iccci 0, r0
#endif
icbi 0,r6
arch/powerpc/kernel/misc32.S:
/*
* Write any modified data cache blocks out to memory
* and invalidate the corresponding instruction cache blocks.
* This is a no-op on the 601.
*
* flush_icache_range(unsigned long start, unsigned long stop)
*/
_KPROBE(__flush_icache_range)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
li r5,L1_CACHE_BYTES-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,L1_CACHE_SHIFT
beqlr
mtctr r4
mr r6,r3
1: dcbst 0,r3
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
sync /* wait for dcbst's to get to ram */
#ifndef CONFIG_44x
mtctr r4
2: icbi 0,r6
addi r6,r6,L1_CACHE_BYTES
bdnz 2b
#else
/* Flash invalidate on 44x because we are passed kmapped addresses and
this doesn't work for userspace pages due to the virtually tagged
icache. Sigh. */
iccci 0, r0
#endif
sync /* additional sync needed on g4 */
isync
blr
Best regards
-Mike
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^ permalink raw reply
* [PATCH] powerpc: Fix interrupt range check on debug exception
From: Bharat Bhushan @ 2013-04-30 8:18 UTC (permalink / raw)
To: galak, linuxppc-dev, benh, agraf, scottwood, stuart.yoder; +Cc: Bharat Bhushan
We do not want to take single step and branch-taken debug exception
in kernel exception code. But the address range check was not covering
all kernel exception handlers address range.
With this patch we defined the interrupt_end label which defines the
end on kernel exception code. So now we check interrupt_base to
interrupt_end range for not handling debug exception in kernel
exception entry.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kernel/head_44x.S | 2 ++
arch/powerpc/kernel/head_booke.h | 16 ++++++++--------
arch/powerpc/kernel/head_fsl_booke.S | 2 ++
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index 7a2e5e4..97e2671 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -769,6 +769,8 @@ finish_tlb_load_47x:
*/
DEBUG_CRIT_EXCEPTION
+interrupt_end:
+
/*
* Global functions
*/
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 5f051ee..df564e9 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -286,13 +286,13 @@ label:
andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
beq+ 2f; \
\
- lis r10,KERNELBASE@h; /* check if exception in vectors */ \
- ori r10,r10,KERNELBASE@l; \
+ lis r10,interrupt_base@h; /* check if exception in vectors */ \
+ ori r10,r10,interrupt_base@l; \
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
- lis r10,DebugDebug@h; \
- ori r10,r10,DebugDebug@l; \
+ lis r10,interrupt_end@h; \
+ ori r10,r10,interrupt_end@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
@@ -339,13 +339,13 @@ label:
andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
beq+ 2f; \
\
- lis r10,KERNELBASE@h; /* check if exception in vectors */ \
- ori r10,r10,KERNELBASE@l; \
+ lis r10,interrupt_base@h; /* check if exception in vectors */ \
+ ori r10,r10,interrupt_base@l; \
cmplw r12,r10; \
blt+ 2f; /* addr below exception vectors */ \
\
- lis r10,DebugCrit@h; \
- ori r10,r10,DebugCrit@l; \
+ lis r10,interrupt_end@h; \
+ ori r10,r10,interrupt_end@l; \
cmplw r12,r10; \
bgt+ 2f; /* addr above exception vectors */ \
\
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 6f62a73..d10a7ca 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -605,6 +605,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
/* Embedded Hypervisor Privilege */
EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
+interrupt_end:
+
/*
* Local functions
*/
--
1.5.6.5
^ permalink raw reply related
* Re: ppc/sata-fsl: orphan config value: CONFIG_MPC8315_DS
From: Anthony Foiani @ 2013-04-30 6:41 UTC (permalink / raw)
To: Anthony Foiani
Cc: Li Yang-R58472, Jeff Garzik, Adrian Bunk, Scott Wood,
Robert P.J.Day, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <gd35lbf55.fsf@dworkin.scrye.com>
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Apologies for resurrecting a very old thread, but...
On 05/30/2012 02:14 PM, Anthony Foiani wrote:
>
> Maybe someone who knows devtree really well could crank that out in a
> few minutes... but I'm not that person. :)
Well, I wasn't last year, but this year I decided that I didn't care.
Took me about an hour, not a minute, but...
Having been bitten by this config symbol disappearing one more time,
please find attached my attempt at using information out of the device
tree to enable this hack.
Patch is against 3.4.36 or so; hopefully upstream hasn't diverged very much.
Tested by me, so feel free to add that tag if required.
Thanks,
Anthony Foiani
[-- Attachment #2: 0001-sata-fsl-allow-device-tree-to-limit-sata-speed.patch --]
[-- Type: text/x-patch, Size: 4114 bytes --]
>From c0a85758a669b430c0a6af825e71d18a54ef88d0 Mon Sep 17 00:00:00 2001
From: Anthony Foiani <anthony.foiani@gmail.com>
Date: Mon, 29 Apr 2013 23:44:14 -0600
Subject: [PATCH] sata: fsl: allow device tree to limit sata speed.
There used to be an "orphan" config symbol (CONFIG_MPC8315_DS) that
would artificially limit SATA speed to generation 1 (1.5Gbps).
Since that config symbol got lost whenever any sort of configuration
was done, we instead extract the limitation from the device tree.
Signed-off-by: Anthony Foiani <anthony.foiani@gmail.com>
---
.../devicetree/bindings/powerpc/fsl/board.txt | 23 +++++++++++
drivers/ata/sata_fsl.c | 44 ++++++++++++++++++----
2 files changed, 59 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/board.txt b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
index 380914e..6a30398 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/board.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/board.txt
@@ -67,3 +67,26 @@ Example:
gpio-controller;
};
};
+
+* Maximum SATA Generation workaround
+
+Some boards advertise SATA speeds that they cannot actually achieve.
+Previously, this was dealt with via the orphaned config symbol
+CONFIG_MPC8315_DS. We now have a device tree property
+"fsl,sata-max-gen" to control this. It should live within the "sata"
+block.
+
+Example:
+
+ sata@18000 {
+ compatible = "fsl,mpc8315-sata", "fsl,pq-sata";
+ reg = <0x18000 0x1000>;
+ cell-index = <1>;
+ interrupts = <44 0x8>;
+ interrupt-parent = <&ipic>;
+ fsl,sata-max-gen = <1>;
+ };
+
+By default, there is no limitation; if a value is given, it indicates
+the maximum "generation" that should be negotiated. Gen 1 is 1.5Gbps,
+Gen 2 is 3.0Gbps.
diff --git a/drivers/ata/sata_fsl.c b/drivers/ata/sata_fsl.c
index d6577b9..6d3ec47 100644
--- a/drivers/ata/sata_fsl.c
+++ b/drivers/ata/sata_fsl.c
@@ -274,6 +274,17 @@ struct sata_fsl_port_priv {
};
/*
+ * speed negotiation.
+ */
+
+enum {
+ SCR_SPEED_NEG_MASK = 0xf0,
+ SCR_SPEED_NEG_UNLIMITED = 0x00,
+ SCR_SPEED_NEG_GEN_1 = 0x10, /* 1.5Gbps max */
+ SCR_SPEED_NEG_GEN_2 = 0x20 /* 3.0Gbps max */
+};
+
+/*
* ata_port->host_set private data
*/
struct sata_fsl_host_priv {
@@ -282,6 +293,7 @@ struct sata_fsl_host_priv {
void __iomem *csr_base;
int irq;
int data_snoop;
+ u32 speed_neg;
struct device_attribute intr_coalescing;
};
@@ -726,19 +738,23 @@ static int sata_fsl_port_start(struct ata_port *ap)
VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
-#ifdef CONFIG_MPC8315_DS
/*
* Workaround for 8315DS board 3gbps link-up issue,
* currently limit SATA port to GEN1 speed
*/
- sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
- temp &= ~(0xF << 4);
- temp |= (0x1 << 4);
- sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
+ if ( host_priv->speed_neg != SCR_SPEED_NEG_UNLIMITED )
+ {
- sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
- dev_warn(dev, "scr_control, speed limited to %x\n", temp);
-#endif
+ u32 orig;
+ sata_fsl_scr_read(&ap->link, SCR_CONTROL, &orig);
+ temp = ( ( orig & ~SCR_SPEED_NEG_MASK ) |
+ ( host_priv->speed_neg & SCR_SPEED_NEG_MASK ) );
+ sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
+
+ sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
+ dev_warn(dev, "speed limited, scr_control 0x%x -> 0x%x\n",
+ orig, temp);
+ }
return 0;
}
@@ -1437,6 +1453,18 @@ static int sata_fsl_probe(struct platform_device *ofdev)
else
host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
+ if (!of_property_read_u32(ofdev->dev.of_node, "fsl,sata-max-gen",
+ &temp))
+ {
+ switch (temp)
+ {
+ case 1: host_priv->speed_neg = SCR_SPEED_NEG_GEN_1; break;
+ case 2: host_priv->speed_neg = SCR_SPEED_NEG_GEN_2; break;
+ }
+ dev_warn(&ofdev->dev, "speed limit set to gen %u (0x%x)\n",
+ temp, host_priv->speed_neg);
+ }
+
/* allocate host structure */
host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
if (!host) {
--
1.8.1.4
^ permalink raw reply related
* Re: [PATCH -V7 18/18] powerpc: Update tlbie/tlbiel as per ISA doc
From: David Gibson @ 2013-04-30 6:15 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1367177859-7893-19-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
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On Mon, Apr 29, 2013 at 01:07:39AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Encode the actual page correctly in tlbie/tlbiel. This make sure we handle
> multiple page size segment correctly.
As mentioned in previous comments, this commit message needs to give
much more detail about what precisely the existing implementation is
doing wrong.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_native_64.c | 32 ++++++++++++++++++++++++++++++--
> 1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index bb920ee..6a2aead 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -61,7 +61,10 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
>
> switch (psize) {
> case MMU_PAGE_4K:
> + /* clear out bits after (52) [0....52.....63] */
> + va &= ~((1ul << (64 - 52)) - 1);
> va |= ssize << 8;
> + va |= mmu_psize_defs[apsize].sllp << 6;
> asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> : "memory");
> @@ -69,9 +72,20 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
> default:
> /* We need 14 to 14 + i bits of va */
> penc = mmu_psize_defs[psize].penc[apsize];
> - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
> + va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> + /* Add AVAL part */
> + if (psize != apsize) {
> + /*
> + * MPSS, 64K base page size and 16MB parge page size
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
I can't understand what this comment is saying. Why do we need to do
something different in the psize != apsize case?
> + */
> + va |= (vpn & 0xfe);
> + }
> va |= 1; /* L */
> asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> @@ -96,16 +110,30 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
>
> switch (psize) {
> case MMU_PAGE_4K:
> + /* clear out bits after(52) [0....52.....63] */
> + va &= ~((1ul << (64 - 52)) - 1);
> va |= ssize << 8;
> + va |= mmu_psize_defs[apsize].sllp << 6;
> asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
> : : "r"(va) : "memory");
> break;
> default:
> /* We need 14 to 14 + i bits of va */
> penc = mmu_psize_defs[psize].penc[apsize];
> - va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
> + va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> + /* Add AVAL part */
> + if (psize != apsize) {
> + /*
> + * MPSS, 64K base page size and 16MB parge page size
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
> + */
> + va |= (vpn & 0xfe);
> + }
> va |= 1; /* L */
> asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
> : : "r"(va) : "memory");
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: [PATCH -V7 08/18] powerpc: New hugepage directory format
From: David Gibson @ 2013-04-30 5:16 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1367177859-7893-9-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1005 bytes --]
On Mon, Apr 29, 2013 at 01:07:29AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> Change the hugepage directory format so that we can have leaf ptes directly
> at page directory avoiding the allocation of hugepage directory.
>
> With the new table format we have 3 cases for pgds and pmds:
> (1) invalid (all zeroes)
> (2) pointer to next table, as normal; bottom 6 bits == 0
> (4) hugepd pointer, bottom two bits == 00, next 4 bits indicate size of table
>
> Instead of storing shift value in hugepd pointer we use mmu_psize_def index
> so that we can fit all the supported hugepage size in 4 bits
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Looks ok.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: [PATCH -V7 09/18] powerpc: Switch 16GB and 16MB explicit hugepages to a different page table format
From: David Gibson @ 2013-04-30 5:17 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1367177859-7893-10-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
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On Mon, Apr 29, 2013 at 01:07:30AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> We will be switching PMD_SHIFT to 24 bits to facilitate THP impmenetation.
> With PMD_SHIFT set to 24, we now have 16MB huge pages allocated at PGD level.
> That means with 32 bit process we cannot allocate normal pages at
> all, because we cover the entire address space with one pgd entry. Fix this
> by switching to a new page table format for hugepages. With the new page table
> format for 16GB and 16MB hugepages we won't allocate hugepage directory. Instead
> we encode the PTE information directly at the directory level. This forces 16MB
> hugepage at PMD level. This will also make the page take walk much simpler later
> when we add the THP support.
>
> With the new table format we have 4 cases for pgds and pmds:
> (1) invalid (all zeroes)
> (2) pointer to next table, as normal; bottom 6 bits == 0
> (3) leaf pte for huge page, bottom two bits != 00
> (4) hugepd pointer, bottom two bits == 00, next 4 bits indicate size
> of table
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Mostly ok, except that in several pages your comments imply you have
16M and 16M page directory levels, but you haven't actually made that
change yet.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V7 01/18] mm/THP: HPAGE_SHIFT is not a #define on some arch
From: David Gibson @ 2013-04-30 5:01 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, paulus, linux-mm
In-Reply-To: <871u9sfzvy.fsf@linux.vnet.ibm.com>
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On Tue, Apr 30, 2013 at 09:12:09AM +0530, Aneesh Kumar K.V wrote:
> David Gibson <dwg@au1.ibm.com> writes:
>
> > On Mon, Apr 29, 2013 at 01:07:22AM +0530, Aneesh Kumar K.V wrote:
> >> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> >>
> >> On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
> >> and other derived values like HPAGE_PMD_ORDER are not constants. So move
> >> that to hugepage_init
> >
> > These seems to miss the point. Those variables may be defined in
> > terms of HPAGE_SHIFT right now, but that is of itself kind of broken.
> > The transparent hugepage mechanism only works if the hugepage size is
> > equal to the PMD size - and PMD_SHIFT remains a compile time constant.
> >
> > There's no reason having transparent hugepage should force the PMD
> > size of hugepage to be the default for other purposes - it should be
> > possible to do THP as long as PMD-sized is a possible hugepage size.
> >
>
> THP code does
>
> #define HPAGE_PMD_SHIFT HPAGE_SHIFT
> #define HPAGE_PMD_MASK HPAGE_MASK
> #define HPAGE_PMD_SIZE HPAGE_SIZE
>
> I had two options, one to move all those in terms of PMD_SHIFT
This is a much better option that you've taken now, and really
shouldn't be that hard. The THP code is much more strongly tied to
the fact that it is a PMD than the fact that it's the same size as
explicit huge pages.
> or switch
> ppc64 to not use HPAGE_SHIFT the way it use now. Both would involve large
> code changes. Hence I end up moving some of the checks to runtime
> checks. Actual HPAGE_SHIFT == PMD_SHIFT check happens in the has_transparent_hugepage()
>
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-April/106002.html
And my other point is that this is also wrong. All you should need to
check is that HPAGE_PMD_SHIFT (== PMD_SHIFT) is a supported hugepage
size, not that it is equal to HPAGE_SHIFT the default explicit
hugepage size.
> IMHO what the patch is checking is that, HPAGE_SHIFT
> value is not resulting in a page order higher than MAX_ORDER.
Which you don't actually care about in THP - you only care that
HPAGE_PMD_SHIFT doesn't exceed MAX_ORDER.
> Related to Reviewed-by: that came from V5 patchset
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-April/105299.html
>
> Your review suggestion to move that runtime check back to macro happened
> in V6. I missed dropping reviewed-by after that.
Ok.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* [PATCH v2] powerpc: Add an in memory udbg console
From: Alistair Popple @ 2013-04-30 4:07 UTC (permalink / raw)
To: linuxppc-dev
This patch adds a new udbg early debug console which utilises
statically defined input and output buffers stored within the kernel
BSS. It is primarily designed to assist with bring up of new hardware
which may not have a working console but which has a method of
reading/writing kernel memory.
This version incorporates comments made by Ben H (thanks!).
Changes from v1:
- Add memory barriers.
- Ensure updating of read/write positions is atomic.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
arch/powerpc/Kconfig.debug | 23 ++++++++
arch/powerpc/include/asm/udbg.h | 1 +
arch/powerpc/kernel/udbg.c | 3 ++
arch/powerpc/sysdev/Makefile | 2 +
arch/powerpc/sysdev/udbg_memcons.c | 105 ++++++++++++++++++++++++++++++++++++
5 files changed, 134 insertions(+)
create mode 100644 arch/powerpc/sysdev/udbg_memcons.c
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 5416e28..863d877 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -262,8 +262,31 @@ config PPC_EARLY_DEBUG_OPAL_HVSI
Select this to enable early debugging for the PowerNV platform
using an "hvsi" console
+config PPC_EARLY_DEBUG_MEMCONS
+ bool "In memory console"
+ help
+ Select this to enable early debugging using an in memory console.
+ This console provides input and output buffers stored within the
+ kernel BSS and should be safe to select on any system. A debugger
+ can then be used to read kernel output or send input to the console.
endchoice
+config PPC_MEMCONS_OUTPUT_SIZE
+ int "In memory console output buffer size"
+ depends on PPC_EARLY_DEBUG_MEMCONS
+ default 4096
+ help
+ Selects the size of the output buffer (in bytes) of the in memory
+ console.
+
+config PPC_MEMCONS_INPUT_SIZE
+ int "In memory console input buffer size"
+ depends on PPC_EARLY_DEBUG_MEMCONS
+ default 128
+ help
+ Selects the size of the input buffer (in bytes) of the in memory
+ console.
+
config PPC_EARLY_DEBUG_OPAL
def_bool y
depends on PPC_EARLY_DEBUG_OPAL_RAW || PPC_EARLY_DEBUG_OPAL_HVSI
diff --git a/arch/powerpc/include/asm/udbg.h b/arch/powerpc/include/asm/udbg.h
index 5a7510e..dc59091 100644
--- a/arch/powerpc/include/asm/udbg.h
+++ b/arch/powerpc/include/asm/udbg.h
@@ -52,6 +52,7 @@ extern void __init udbg_init_40x_realmode(void);
extern void __init udbg_init_cpm(void);
extern void __init udbg_init_usbgecko(void);
extern void __init udbg_init_wsp(void);
+extern void __init udbg_init_memcons(void);
extern void __init udbg_init_ehv_bc(void);
extern void __init udbg_init_ps3gelic(void);
extern void __init udbg_init_debug_opal_raw(void);
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index f974849..efa5c93 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -64,6 +64,9 @@ void __init udbg_early_init(void)
udbg_init_usbgecko();
#elif defined(CONFIG_PPC_EARLY_DEBUG_WSP)
udbg_init_wsp();
+#elif defined(CONFIG_PPC_EARLY_DEBUG_MEMCONS)
+ /* In memory console */
+ udbg_init_memcons();
#elif defined(CONFIG_PPC_EARLY_DEBUG_EHV_BC)
udbg_init_ehv_bc();
#elif defined(CONFIG_PPC_EARLY_DEBUG_PS3GELIC)
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index b0a518e..99464a7 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -64,6 +64,8 @@ endif
obj-$(CONFIG_PPC_SCOM) += scom.o
+obj-$(CONFIG_PPC_EARLY_DEBUG_MEMCONS) += udbg_memcons.o
+
subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
obj-$(CONFIG_PPC_XICS) += xics/
diff --git a/arch/powerpc/sysdev/udbg_memcons.c b/arch/powerpc/sysdev/udbg_memcons.c
new file mode 100644
index 0000000..ce5a7b4
--- /dev/null
+++ b/arch/powerpc/sysdev/udbg_memcons.c
@@ -0,0 +1,105 @@
+/*
+ * A udbg backend which logs messages and reads input from in memory
+ * buffers.
+ *
+ * The console output can be read from memcons_output which is a
+ * circular buffer whose next write position is stored in memcons.output_pos.
+ *
+ * Input may be passed by writing into the memcons_input buffer when it is
+ * empty. The input buffer is empty when both input_pos == input_start and
+ * *input_start == '\0'.
+ *
+ * Copyright (C) 2003-2005 Anton Blanchard and Milton Miller, IBM Corp
+ * Copyright (C) 2013 Alistair Popple, IBM Corp
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/barrier.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/udbg.h>
+
+struct memcons {
+ char *output_start;
+ char *output_pos;
+ char *output_end;
+ char *input_start;
+ char *input_pos;
+ char *input_end;
+};
+
+static char memcons_output[CONFIG_PPC_MEMCONS_OUTPUT_SIZE];
+static char memcons_input[CONFIG_PPC_MEMCONS_INPUT_SIZE];
+
+struct memcons memcons = {
+ .output_start = memcons_output,
+ .output_pos = memcons_output,
+ .output_end = &memcons_output[CONFIG_PPC_MEMCONS_OUTPUT_SIZE],
+ .input_start = memcons_input,
+ .input_pos = memcons_input,
+ .input_end = &memcons_input[CONFIG_PPC_MEMCONS_INPUT_SIZE],
+};
+
+void memcons_putc(char c)
+{
+ char *new_output_pos;
+
+ *memcons.output_pos = c;
+ wmb();
+ new_output_pos = memcons.output_pos + 1;
+ if (new_output_pos >= memcons.output_end)
+ new_output_pos = memcons.output_start;
+
+ memcons.output_pos = new_output_pos;
+}
+
+int memcons_getc_poll(void)
+{
+ char c;
+ char *new_input_pos;
+
+ if (*memcons.input_pos) {
+ c = *memcons.input_pos;
+
+ new_input_pos = memcons.input_pos + 1;
+ if (new_input_pos >= memcons.input_end)
+ new_input_pos = memcons.input_start;
+ else if (*new_input_pos == '\0')
+ new_input_pos = memcons.input_start;
+
+ *memcons.input_pos = '\0';
+ wmb();
+ memcons.input_pos = new_input_pos;
+ return c;
+ }
+
+ return -1;
+}
+
+int memcons_getc(void)
+{
+ int c;
+
+ while (1) {
+ c = memcons_getc_poll();
+ if (c == -1)
+ cpu_relax();
+ else
+ break;
+ }
+
+ return c;
+}
+
+void udbg_init_memcons(void)
+{
+ udbg_putc = memcons_putc;
+ udbg_getc = memcons_getc;
+ udbg_getc_poll = memcons_getc_poll;
+}
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH -V7 01/18] mm/THP: HPAGE_SHIFT is not a #define on some arch
From: Aneesh Kumar K.V @ 2013-04-30 3:42 UTC (permalink / raw)
To: David Gibson; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <20130430022149.GU20202@truffula.fritz.box>
David Gibson <dwg@au1.ibm.com> writes:
> On Mon, Apr 29, 2013 at 01:07:22AM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>>
>> On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
>> and other derived values like HPAGE_PMD_ORDER are not constants. So move
>> that to hugepage_init
>
> These seems to miss the point. Those variables may be defined in
> terms of HPAGE_SHIFT right now, but that is of itself kind of broken.
> The transparent hugepage mechanism only works if the hugepage size is
> equal to the PMD size - and PMD_SHIFT remains a compile time constant.
>
> There's no reason having transparent hugepage should force the PMD
> size of hugepage to be the default for other purposes - it should be
> possible to do THP as long as PMD-sized is a possible hugepage size.
>
THP code does
#define HPAGE_PMD_SHIFT HPAGE_SHIFT
#define HPAGE_PMD_MASK HPAGE_MASK
#define HPAGE_PMD_SIZE HPAGE_SIZE
I had two options, one to move all those in terms of PMD_SHIFT or switch
ppc64 to not use HPAGE_SHIFT the way it use now. Both would involve large
code changes. Hence I end up moving some of the checks to runtime
checks. Actual HPAGE_SHIFT == PMD_SHIFT check happens in the has_transparent_hugepage()
https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-April/106002.html
IMHO what the patch is checking is that, HPAGE_SHIFT
value is not resulting in a page order higher than MAX_ORDER.
Related to Reviewed-by: that came from V5 patchset
https://lists.ozlabs.org/pipermail/linuxppc-dev/2013-April/105299.html
Your review suggestion to move that runtime check back to macro happened
in V6. I missed dropping reviewed-by after that.
-aneesh
^ permalink raw reply
* Re: [PATCH -V7 01/18] mm/THP: HPAGE_SHIFT is not a #define on some arch
From: David Gibson @ 2013-04-30 2:24 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <20130430022149.GU20202@truffula.fritz.box>
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On Tue, Apr 30, 2013 at 12:21:49PM +1000, David Gibson wrote:
> On Mon, Apr 29, 2013 at 01:07:22AM +0530, Aneesh Kumar K.V wrote:
> > From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
> >
> > On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
> > and other derived values like HPAGE_PMD_ORDER are not constants. So move
> > that to hugepage_init
>
> These seems to miss the point. Those variables may be defined in
> terms of HPAGE_SHIFT right now, but that is of itself kind of broken.
> The transparent hugepage mechanism only works if the hugepage size is
> equal to the PMD size - and PMD_SHIFT remains a compile time constant.
>
> There's no reason having transparent hugepage should force the PMD
> size of hugepage to be the default for other purposes - it should be
> possible to do THP as long as PMD-sized is a possible hugepage size.
Oh, also, I'm pretty sure I said something similar on the last
posting. Receiving review comments and then ignoring them does not
count as "Reviewed-by"...
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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* Re: [PATCH -V7 01/18] mm/THP: HPAGE_SHIFT is not a #define on some arch
From: David Gibson @ 2013-04-30 2:21 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: paulus, linuxppc-dev, linux-mm
In-Reply-To: <1367177859-7893-2-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 999 bytes --]
On Mon, Apr 29, 2013 at 01:07:22AM +0530, Aneesh Kumar K.V wrote:
> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> On archs like powerpc that support different hugepage sizes, HPAGE_SHIFT
> and other derived values like HPAGE_PMD_ORDER are not constants. So move
> that to hugepage_init
These seems to miss the point. Those variables may be defined in
terms of HPAGE_SHIFT right now, but that is of itself kind of broken.
The transparent hugepage mechanism only works if the hugepage size is
equal to the PMD size - and PMD_SHIFT remains a compile time constant.
There's no reason having transparent hugepage should force the PMD
size of hugepage to be the default for other purposes - it should be
possible to do THP as long as PMD-sized is a possible hugepage size.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply
* Re: linux-next: build failure after merge of the cgroup tree
From: Benjamin Herrenschmidt @ 2013-04-30 1:51 UTC (permalink / raw)
To: Tejun Heo
Cc: Stephen Rothwell, linux-kernel, Li Zefan, linux-next,
Nathan Fontenot, linuxppc-dev
In-Reply-To: <20130429225513.GG2395@htj.dyndns.org>
On Mon, 2013-04-29 at 15:55 -0700, Tejun Heo wrote:
> Benjamin, can you please pick this up?
>
> Thanks a lot and sorry about the trouble.
Done.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: fix usage of setup_pci_atmu()
From: Benjamin Herrenschmidt @ 2013-04-30 1:08 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: linuxppc-dev, Michael Neuling, linux-next
In-Reply-To: <20130430090636.5e06bbfc6db472e1e677cb0b@canb.auug.org.au>
On Tue, 2013-04-30 at 09:06 +1000, Stephen Rothwell wrote:
>
> This is still not in your tree ...
I'll apply it after I merge kumar stuff.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: fix usage of setup_pci_atmu()
From: Stephen Rothwell @ 2013-04-29 23:06 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Michael Neuling, linux-next
In-Reply-To: <5881.1366004521@ale.ozlabs.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 1209 bytes --]
Hi Kumar,
On Mon, 15 Apr 2013 15:42:01 +1000 Michael Neuling <mikey@neuling.org> wrote:
>
> Linux next is currently failing to compile mpc85xx_defconfig with:
> arch/powerpc/sysdev/fsl_pci.c:944:2: error: too many arguments to function 'setup_pci_atmu'
>
> This is caused by (from Kumar's next branch):
> commit 34642bbb3d12121333efcf4ea7dfe66685e403a1
> Author: Kumar Gala <galak@kernel.crashing.org>
> powerpc/fsl-pci: Keep PCI SoC controller registers in pci_controller
>
> Which changed definition of setup_pci_atmu() but didn't update one of
> the callers. Below fixes this.
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> ---
> Kumar: this is for your next tree
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index 83918c3..a10a036 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -941,7 +941,7 @@ static int fsl_pci_resume(struct device *dev)
> return -ENODEV;
> }
>
> - setup_pci_atmu(hose, &pci_rsrc);
> + setup_pci_atmu(hose);
>
> return 0;
> }
>
This is still not in your tree ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
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^ permalink raw reply
* Re: linux-next: build failure after merge of the cgroup tree
From: Tejun Heo @ 2013-04-29 22:55 UTC (permalink / raw)
To: Stephen Rothwell
Cc: linux-kernel, Li Zefan, linux-next, Nathan Fontenot, linuxppc-dev
In-Reply-To: <20130429140433.92d05cd48b66ac323616d572@canb.auug.org.au>
Hello,
On Mon, Apr 29, 2013 at 02:04:33PM +1000, Stephen Rothwell wrote:
> I have added the following merge fix patch for today (but it should be
> applied to the powerpc tree ASAP).
>
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Mon, 29 Apr 2013 14:01:44 +1000
> Subject: [PATCH] powerpc: numa.c: using kzalloc/kfree requires including
> slab.h
>
> fixes these build errors:
>
> arch/powerpc/mm/numa.c: In function 'arch_update_cpu_topology':
> arch/powerpc/mm/numa.c:1465:2: error: implicit declaration of function 'kzalloc' [-Werror=implicit-function-declaration]
> arch/powerpc/mm/numa.c:1465:10: error: assignment makes pointer from integer without a cast [-Werror]
> arch/powerpc/mm/numa.c:1497:2: error: implicit declaration of function 'kfree' [-Werror=implicit-function-declaration]
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Tejun Heo <tj@kernel.org>
Benjamin, can you please pick this up?
Thanks a lot and sorry about the trouble.
--
tejun
^ permalink raw reply
* Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xx
From: Scott Wood @ 2013-04-29 20:29 UTC (permalink / raw)
To: Jia Hongtao-B38951; +Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <412C8208B4A0464FA894C5F0C278CD5D01C4C76D@039-SN1MPN1-002.039d.mgd.msft.net>
On 04/26/2013 09:26:26 PM, Jia Hongtao-B38951 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, April 26, 2013 12:58 AM
> > To: Segher Boessenkool
> > Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org;
> > galak@kernel.crashing.org; Wood Scott-B07421
> > Subject: Re: [PATCH 2/2 V7] powerpc/85xx: Add machine check handler =20
> to
> > fix PCIe erratum on mpc85xx
> >
> > On 04/25/2013 10:31:51 AM, Segher Boessenkool wrote:
> > >> * Remove A variant of load instruction emulation
> > >
> > > Why is this? You handle all other simple load insns, there is =20
> nothing
> > > special about LHA. (I reviewed the V4 email thread, no reason =20
> for the
> > > chance is given there).
> >
> > The LHA implementation in V5 was incorrect (didn't sign-extend).
> >
> > -Scott
>=20
> In former email you doubt whether we need A variant or not.
> Any particular reason for that?
> If not should I emulate all the A ARX AU AUX and AX variant?
I was just noting that the variants you left out from the earlier =20
revisions (e.g. BRX) were much more likely to be used for I/O than some =20
of the ones you included (e.g. "A"). Implementing all the normal =20
load/store instructions would be better, if they're done correctly.
-Scott=
^ permalink raw reply
* Re: [PATCH v2 12/15] powerpc/85xx: add time base sync support for e6500
From: Scott Wood @ 2013-04-29 20:18 UTC (permalink / raw)
To: Zhao Chenhui; +Cc: linuxppc-dev, linux-kernel, r58472
In-Reply-To: <20130428095634.GA27100@localhost.localdomain>
On 04/28/2013 04:56:34 AM, Zhao Chenhui wrote:
> On Thu, Apr 25, 2013 at 07:07:24PM -0500, Scott Wood wrote:
> > On 04/24/2013 07:28:18 PM, Zhao Chenhui wrote:
> > >On Wed, Apr 24, 2013 at 05:38:16PM -0500, Scott Wood wrote:
> > >> We shouldn't base it on CPU_FTR_SMT. For example, e6500 doesn't
> > >> claim that feature yet, except in our SDK kernel. That doesn't
> > >> change the topology of CPU numbering.
> > >>
> > >
> > >Then, where can I get the thread information? dts?
> > >Or, wait for upstream of the thread suppport of e6500.
> >
> > It's an inherent property of e6500 (outside of some virtualization
> > scenarios, but you wouldn't run this code under a hypervisor) that
> > you have two threads per core (whether Linux uses them or not). Or
> > you could read TMCFG0[NTHRD] if you know you're on a chip that has
> > TMRs but aren't positive it's an e6500, but I wouldn't bother. If
> > we do ever have such a chip, there are probably other things that
> > will need updating.
> >
>=20
> But how to know that there are TMRs on a chip except by CPU_FTR_SMT.
I don't know. I said I wouldn't bother. :-)
Just assume there are 2 threads per core on e6500. Then you won't have =20
a dependency on the threading patches, and you won't break if =20
CPU_FTR_SMT gets disabled for some other reason, or if the threads are =20
missing from the device tree for some reason (I've seen some people =20
remove them manually in an attempt to disable threading -- I tell them =20
not to when I see it, but eventually others will do it again).
-Scott=
^ permalink raw reply
* [git pull] Please pull powerpc.git next branch
From: Kumar Gala @ 2013-04-29 19:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc list
Ben,
Add support for T4 and B4 SoC families from Freescale, e6500 altivec =
support, some various board fixes and other minor cleanups.
- k
The following changes since commit =
54c9b2253d34e8998e4bff9ac2d7a3ba0b861d52:
powerpc: Set DSCR bit in FSCR setup (2013-03-05 16:56:30 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git next
for you to fetch changes up to 9e2ecdbba3b0745f9ed454ab86961e3ccf9dc224:
powerpc/fsl-booke: add the reg prop for pci bridge device node for =
T4/B4 (2013-04-29 14:47:25 -0500)
----------------------------------------------------------------
Ben Collins (1):
powerpc/85xx: sgy-cts1000 - Remove __dev* attributes
Chen-Hui Zhao (1):
powerpc/85xx: fix a bug with the parameter of mpic_reset_core()
Jia Hongtao (1):
powerpc/85xx: Add platform_device declaration to fsl_pci.h
Jiucheng Xu (1):
powerpc/85xx: Reserve a partition of NOR flash for QE ucode =
firmware
Kevin Hao (2):
powerpc/fsl-pci: don't unmap the PCI SoC controller registers in =
setup_pci_atmu
powerpc/fsl-booke: add the reg prop for pci bridge device node for =
T4/B4
Kumar Gala (11):
powerpc/fsl-booke: Support detection of page sizes on e6500
powerpc/85xx: Add AltiVec support for e6500
powerpc/fsl-booke: Add initial silicon device tree for T4240
powerpc/fsl-booke: Add initial T4240QDS board device tree
powerpc/fsl-booke: Add initial T4240QDS board support
powerpc/85xx: Update corenet64_smp_defconfig for T4240
powerpc/qe: Fix Kconfig enablement of QE_USB support
powerpc/fsl-booke: Update T4240 device config node in device tree
powerpc/fsl-booke: Minor fixes to T4240 Si device tree
powerpc/fsl-pci: Keep PCI SoC controller registers in =
pci_controller
powerpc/85xx: Fix MPC8536DS 36-bit device tree
Paul Bolle (2):
powerpc: remove "config 8260_PCI9"
powerpc: remove "config MPC10X_OPENPIC"
Prabhakar Kushwaha (1):
powerpc: add CONFIG(s) require for using flash controller
Ramneek Mehresh (1):
powerpc/85xx: Add first usb controller node for Qonverge platforms
Rojhalat Ibrahim (1):
powerpc/fsl-pci Make PCIe hotplug work with Freescale PCIe =
controllers
Roy ZANG (2):
powerpc/85xx: Add support for FSL PCIe controller v3.0
powerpc/85xx: enable Silicon image 3132 PCIe to SATA controller
Roy Zang (2):
powerpc/85xx: enable E1000 NIC to mpc85xx_defconfig
powerpc/fsl_pci: fix 64 bit pci size issue
Scott Wood (1):
powerpc/85xx: add CONFIG_E1000E to corenet64_smp_defconfig
Sebastian Andrzej Siewior (1):
powerpc/fsl-msi: use a different lockclass for the cascade =
interrupt
Shaveta Leekha (5):
powerpc/85xx: add SEC-5.3 device tree
powerpc/fsl-booke: Add initial silicon device tree files for B4860 =
and B4420
powerpc/fsl-booke: Add initial B4860QDS and B4420QDS board device =
tree
powerpc/fsl-booke: Add B4_QDS board support
powerpc/85xx: Update corenet64_smp_defconfig for B4_QDS
Stephen George (2):
powerpc/fsl-booke: Added device tree DCSR entries for T4240 =
Chassis v2 Debug IP
powerpc/fsl-booke: Update DCSR EPU device tree entries for =
existing SoCs
Stuart Yoder (3):
powerpc/e6500: Add architecture categories for e6500 cores
powerpc: add missing deo arch category to e500mc/e5500 dts
powerpc: Add paravirt idle loop for 64-bit Book-E
Tang Yuantian (1):
powerpc/fsl: remove the PPC_CLOCK dependency
Vakul Garg (3):
powerpc/85xx: Added SEC-5.0 device tree.
powerpc/fsl: removed qoriq-sec4.1-0.dtsi.
powerpc/fsl: Add property for 'era' in SEC dts crypto node
Zhicheng Fan (1):
powerpc/dts: Fix the dts for p1025rdb 36bit
.../devicetree/bindings/powerpc/fsl/cpus.txt | 22 +
arch/powerpc/Kconfig | 6 -
arch/powerpc/boot/dts/b4420qds.dts | 50 +++
arch/powerpc/boot/dts/b4860qds.dts | 61 +++
arch/powerpc/boot/dts/b4qds.dts | 169 ++++++++
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 98 +++++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 73 ++++
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 142 +++++++
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 83 ++++
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 268 +++++++++++++
arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi | 1 +
arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi | 1 +
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi | 65 +++
arch/powerpc/boot/dts/fsl/p1023si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi | 1 +
arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi | 41 ++
arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi | 41 ++
arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi | 41 ++
arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi | 41 ++
arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi | 1 +
arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi | 1 +
.../{qoriq-sec4.1-0.dtsi =3D> qoriq-sec5.0-0.dtsi} | 27 +-
arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi | 1 +
arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi | 119 ++++++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 442 =
+++++++++++++++++++++
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 128 ++++++
arch/powerpc/boot/dts/mpc8536ds_36b.dts | 6 +-
arch/powerpc/boot/dts/p1021rdb-pc.dtsi | 12 +-
arch/powerpc/boot/dts/p1025rdb_36b.dts | 5 +
arch/powerpc/boot/dts/t4240qds.dts | 224 +++++++++++
arch/powerpc/configs/corenet64_smp_defconfig | 46 ++-
arch/powerpc/configs/mpc85xx_defconfig | 40 +-
arch/powerpc/configs/mpc85xx_smp_defconfig | 32 ++
arch/powerpc/include/asm/cputable.h | 2 +-
arch/powerpc/include/asm/kvm_asm.h | 4 +
arch/powerpc/include/asm/pci-bridge.h | 11 +-
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 16 +
arch/powerpc/kernel/cputable.c | 9 +-
arch/powerpc/kernel/epapr_hcalls.S | 2 +
arch/powerpc/kernel/exceptions-64e.S | 47 +++
arch/powerpc/kernel/idle_book3e.S | 32 +-
arch/powerpc/mm/tlb_nohash.c | 18 +-
arch/powerpc/platforms/85xx/Kconfig | 34 ++
arch/powerpc/platforms/85xx/Makefile | 2 +
arch/powerpc/platforms/85xx/b4_qds.c | 102 +++++
arch/powerpc/platforms/85xx/corenet_ds.c | 5 +-
arch/powerpc/platforms/85xx/sgy_cts1000.c | 6 +-
arch/powerpc/platforms/85xx/smp.c | 2 +-
arch/powerpc/platforms/85xx/t4240_qds.c | 98 +++++
arch/powerpc/platforms/Kconfig | 1 -
arch/powerpc/platforms/Kconfig.cputype | 2 +-
arch/powerpc/platforms/embedded6xx/Kconfig | 5 -
arch/powerpc/sysdev/fsl_msi.c | 4 +-
arch/powerpc/sysdev/fsl_pci.c | 112 ++++--
arch/powerpc/sysdev/fsl_pci.h | 13 +
arch/powerpc/sysdev/indirect_pci.c | 10 +-
arch/powerpc/sysdev/qe_lib/Kconfig | 2 +-
62 files changed, 2738 insertions(+), 100 deletions(-)
create mode 100644 =
Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
create mode 100644 arch/powerpc/boot/dts/b4420qds.dts
create mode 100644 arch/powerpc/boot/dts/b4860qds.dts
create mode 100644 arch/powerpc/boot/dts/b4qds.dts
create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/b4si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
rename arch/powerpc/boot/dts/fsl/{qoriq-sec4.1-0.dtsi =3D> =
qoriq-sec5.0-0.dtsi} (83%)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
create mode 100644 arch/powerpc/boot/dts/t4240qds.dts
create mode 100644 arch/powerpc/platforms/85xx/b4_qds.c
create mode 100644 arch/powerpc/platforms/85xx/t4240_qds.c=
^ permalink raw reply
* Re: [PATCH v2] powerpc/dts: Fix the dts for p1025rdb 36bit
From: Kumar Gala @ 2013-04-29 19:51 UTC (permalink / raw)
To: Zhicheng Fan; +Cc: linuxppc-dev
In-Reply-To: <1364174586-26158-1-git-send-email-B32736@freescale.com>
On Mar 24, 2013, at 8:23 PM, Zhicheng Fan wrote:
> fix the following errors:
> Error: arch/powerpc/boot/dts/p1025rdb.dtsi:326.2-3 label or =
path, 'qe', not found
> Error: arch/powerpc/boot/dts/fsl/p1021si-post.dtsi:242.2-3 label =
or path, 'qe', not found
> FATAL ERROR: Syntax error parsing input tree
>=20
> Signed-off-by: Zhicheng Fan <B32736@freescale.com>
> ---
> arch/powerpc/boot/dts/p1025rdb_36b.dts | 5 +++++
> 1 files changed, 5 insertions(+), 0 deletions(-)
applied to next
- k=
^ permalink raw reply
* Re: [PATCH] powerpc/fsl-booke: add the reg property for pci bridge device node for t4/b4xx boards
From: Kumar Gala @ 2013-04-29 19:50 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1365918013-12190-1-git-send-email-haokexin@gmail.com>
On Apr 14, 2013, at 12:40 AM, Kevin Hao wrote:
> The reg property in the pci bridge device node is used to bind this
> device node to the pci bridge device. Then all the pci devices under
> this bridge could use the interrupt maps defined in this device node
> to do the irq translation. So if this property is missed, the pci
> traditional irq mechanism will not work.
>
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 1 +
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 4 ++++
> 2 files changed, 5 insertions(+)
applied to next
- k
^ permalink raw reply
* Re: [PATCH] powerpc/fsl-pci: don't unmap the PCI SoC controller registers in setup_pci_atmu
From: Kumar Gala @ 2013-04-29 19:46 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1365837281-27002-1-git-send-email-haokexin@gmail.com>
On Apr 13, 2013, at 2:14 AM, Kevin Hao wrote:
> In patch 34642bbb (powerpc/fsl-pci: Keep PCI SoC controller registers =
in
> pci_controller) we choose to keep the map of the PCI SoC controller
> registers. But we missed to delete the unmap in setup_pci_atmu
> function. This will cause the following call trace once we access
> the PCI SoC controller registers later.
>=20
> Unable to handle kernel paging request for data at address =
0x8000080080040f14
> Faulting instruction address: 0xc00000000002ea58
> Oops: Kernel access of bad area, sig: 11 [#1]
> SMP NR_CPUS=3D24 T4240 QDS
> Modules linked in:
> NIP: c00000000002ea58 LR: c00000000002eaf4 CTR: c00000000002eac0
> REGS: c00000017e10b4a0 TRAP: 0300 Not tainted =
(3.9.0-rc1-00052-gfa3529f-dirty)
> MSR: 0000000080029000 <CE,EE,ME> CR: 28adbe22 XER: 00000000
> SOFTE: 0
> DEAR: 8000080080040f14, ESR: 0000000000000000
> TASK =3D c00000017e100000[1] 'swapper/0' THREAD: c00000017e108000 CPU: =
2
> GPR00: 0000000000000000 c00000017e10b720 c0000000009928d8 =
c00000017e578e00
> GPR04: 0000000000000000 000000000000000c 0000000000000001 =
c00000017e10bb40
> GPR08: 0000000000000000 8000080080040000 0000000000000000 =
0000000000000016
> GPR12: 0000000088adbe22 c00000000fffa800 c000000000001ba0 =
0000000000000000
> GPR16: 0000000000000000 0000000000000000 0000000000000000 =
0000000000000000
> GPR20: 0000000000000000 0000000000000000 0000000000000000 =
c0000000008a5b70
> GPR24: c0000000008af938 c0000000009a28d8 c0000000009bb5dc =
c00000017e10bb40
> GPR28: c00000017e32a400 c00000017e10bc00 c00000017e32a400 =
c00000017e578e00
> NIP [c00000000002ea58] .fsl_pcie_check_link+0x88/0xf0
> LR [c00000000002eaf4] .fsl_indirect_read_config+0x34/0xb0
> Call Trace:
> [c00000017e10b720] [c00000017e10b7a0] 0xc00000017e10b7a0 (unreliable)
> [c00000017e10ba30] [c00000000002eaf4] =
.fsl_indirect_read_config+0x34/0xb0
> [c00000017e10bad0] [c00000000033aa08] =
.pci_bus_read_config_byte+0x88/0xd0
> [c00000017e10bb90] [c00000000088d708] =
.pci_apply_final_quirks+0x9c/0x18c
> [c00000017e10bc40] [c0000000000013dc] .do_one_initcall+0x5c/0x1f0
> [c00000017e10bcf0] [c00000000086ebac] =
.kernel_init_freeable+0x180/0x26c
> [c00000017e10bdb0] [c000000000001bbc] .kernel_init+0x1c/0x460
> [c00000017e10be30] [c000000000000880] =
.ret_from_kernel_thread+0x64/0xe4
> Instruction dump:
> 38210310 2b800015 4fdde842 7c600026 5463fffe e8010010 7c0803a6 =
4e800020
> 60000000 60000000 e92301d0 7c0004ac <80690f14> 0c030000 4c00012c =
38210310
> ---[ end trace 7a8fe0cbccb7d992 ]---
>=20
> Kernel panic - not syncing: Attempted to kill init! =
exitcode=3D0x0000000b
>=20
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> This is based on Kumar's next branch.
>=20
> arch/powerpc/sysdev/fsl_pci.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
applied to next
- k=
^ permalink raw reply
* Re: [PATCH] powerpc: Fix missing doorbell IPIs during nap power saving
From: Greg KH @ 2013-04-29 14:06 UTC (permalink / raw)
To: Ian Munsie; +Cc: Michael Neuling, linuxppc-dev, stable
In-Reply-To: <1367223460-4931-1-git-send-email-imunsie@au1.ibm.com>
On Mon, Apr 29, 2013 at 06:17:40PM +1000, Ian Munsie wrote:
> From: Ian Munsie <imunsie@au1.ibm.com>
>
> If a doorbell IPI comes in while a thread is in nap power saving, the
> doorbell interrupt won't be replayed by the hardware since it is edge
> sensitive. Currently we are not replaying these interrupts in software,
> which can cause threads to miss IPIs that come in during power saving
> and eventually will result in an RCU warning from rcu_sched that it has
> detected a stalled CPU.
>
> This patch fixes the issue by testing if a doorbell caused the thread to
> come out of power saving and sets the corresponding bit in the paca to
> indicate a doorbell happened, which will then be handled by the existing
> interrupt replay code.
>
> This is not an issue with other interrupts that can wake a thread
> (external, decrementer) as they are level sensitive and will continue to
> be asserted by the hardware.
>
> Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
<formletter>
This is not the correct way to submit patches for inclusion in the
stable kernel tree. Please read Documentation/stable_kernel_rules.txt
for how to do this properly.
</formletter>
^ permalink raw reply
* [PATCH] powerpc/pseries: correct builds break when CONFIG_SMP not defined
From: Nathan Fontenot @ 2013-04-29 13:45 UTC (permalink / raw)
To: linuxppc-dev
Correct build failure for powerpc/pseries builds with CONFIG_SMP not defined.
The function cpu_sibling_mask has no meaning (or definition) when CONFIG_SMP
is not defined. Additionally, the updating of NUMA affinity for a CPU in a UP
system doesn't really make sense.
This patch ifdef's out the code making the affinity updates for PRRN events to
fix the following build break.
arch/powerpc/mm/numa.c: In function ‘stage_topology_update’:
arch/powerpc/mm/numa.c:1535: error: implicit declaration of function ‘cpu_sibling_mask’
arch/powerpc/mm/numa.c:1535: warning: passing argument 3 of ‘cpumask_or’ makes pointer from integer without a cast
make[1]: *** [arch/powerpc/mm/numa.o] Error 1
Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
---
arch/powerpc/mm/numa.c | 8 ++++++++
1 file changed, 8 insertions(+)
Index: ppc-next/arch/powerpc/mm/numa.c
===================================================================
--- ppc-next.orig/arch/powerpc/mm/numa.c 2013-04-29 07:16:00.000000000 -0500
+++ ppc-next/arch/powerpc/mm/numa.c 2013-04-29 07:21:35.000000000 -0500
@@ -1529,6 +1529,8 @@
mod_timer(&topology_timer, topology_timer.expires);
}
+#ifdef CONFIG_SMP
+
static void stage_topology_update(int core_id)
{
cpumask_or(&cpu_associativity_changes_mask,
@@ -1562,6 +1564,8 @@
.notifier_call = dt_update_callback,
};
+#endif
+
/*
* Start polling for associativity changes.
*/
@@ -1573,7 +1577,9 @@
if (!prrn_enabled) {
prrn_enabled = 1;
vphn_enabled = 0;
+#ifdef CONFIG_SMP
rc = of_reconfig_notifier_register(&dt_update_nb);
+#endif
}
} else if (firmware_has_feature(FW_FEATURE_VPHN) &&
get_lppaca()->shared_proc) {
@@ -1598,7 +1604,9 @@
if (prrn_enabled) {
prrn_enabled = 0;
+#ifdef CONFIG_SMP
rc = of_reconfig_notifier_unregister(&dt_update_nb);
+#endif
} else if (vphn_enabled) {
vphn_enabled = 0;
rc = del_timer_sync(&topology_timer);
^ permalink raw reply
* RE: [PATCH 1/3] rapidio: make enumeration/discovery configurable
From: Bounine, Alexandre @ 2013-04-29 12:08 UTC (permalink / raw)
To: Andrew Morton
Cc: Micha Nelissen, linux-kernel@vger.kernel.org, Andre van Herk,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20130426155325.09fbad8c382dc8c549d503d0@linux-foundation.org>
On Fri, 26 Apr 2013 6:53 PM Andrew Morton <akpm@linux-foundation.org> wrote=
:
> Subject: Re: [PATCH 1/3] rapidio: make enumeration/discovery
> configurable
>=20
> This Kconfig change makes my kbuild do Weird Things.
>=20
> make mrproper ; yes "" | make allmodconfig ; make 2>/tmp/x
... skip ...=20
> : DMA Engine support for RapidIO (RAPIDIO_DMA_ENGINE) [Y/n/?] y
> : RapidIO subsystem debug messages (RAPIDIO_DEBUG) [Y/n/?] y
> : Enumeration method [M/y/?] (NEW) aborted!
> :
> : Console input/output is redirected. Run 'make oldconfig' to update conf=
iguration.
> :
> : SYSHDR arch/x86/syscalls/../include/generated/uapi/asm/unistd_32.h
> : SYSHDR arch/x86/syscalls/../include/generated/uapi/asm/unistd_64.h
> : SYSHDR
> arch/x86/syscalls/../include/generated/uapi/asm/unistd_x32.h
>=20
>=20
> See the "Enumeration method [M/y/?] (NEW) aborted!"
>=20
> Note that this only happens when make's stderr is redirected.
>=20
> I've no idea what's going on here. This appears to fix things:
>=20
> --- a/drivers/rapidio/Kconfig~rapidio-make-enumeration-discovery-
> configurable-fix
> +++ a/drivers/rapidio/Kconfig
> @@ -59,7 +59,7 @@ choice
> If unsure, select Basic built-in.
>=20
> config RAPIDIO_ENUM_BASIC
> - tristate "Basic"
> + bool "Basic"
> help
> This option includes basic RapidIO fabric enumeration and
> discovery
> mechanism similar to one described in RapidIO specification
> Annex 1.
>=20
> but doesn't appear to be what you intended.
Goal is to build enumerator as a module or built-in.
I will retest v2 of patches for this issue.
There are some changes to Kconfig (removed AUTO_ENUM option).
^ permalink raw reply
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