* RE: SATA FSL and upstreaming
From: Bhushan Bharat-R65777 @ 2013-05-16 7:13 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Zang Roy-R61911
Cc: tiejun.chen, Fleming Andy-AFLEMING, linuxppc-dev@lists.ozlabs.org,
Xie Shaohui-B21989, Liu Qiang-B32616
In-Reply-To: <1368687941.9603.56.camel@pasglop>
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^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 7:05 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, tiejun.chen,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E05BC@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-05-16 at 07:01 +0000, Zang Roy-R61911 wrote:
> I just tried your RCW. one e1000 card works in slot7.
> we may need to check others ...
Tried 4 and 7 ...
Note that this *used* to work. Last year I had this machine up with 2
cards doing things. Not sure what changed, it's possible that the DIP
got inadvertently changed. Or somebody stole a jumper from it in the
lab :-)
> U-Boot 2013.01-00078-g2741c99 (May 03 2013 - 00:20:41)
>
> CPU0: P5020E, Version: 2.0, (0x82280020)
> Core: E5500, Version: 1.2, (0x80240012)
> Clock Configuration:
> CPU0:2000 MHz, CPU1:2000 MHz,
> CCB:800 MHz,
> DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100 MHz
> FMAN1: 600 MHz
> QMAN: 400 MHz
> PME: 400 MHz
> L1: D-cache 32 kB enabled
> I-cache 32 kB enabled
> Reset Configuration Word (RCW):
> 00000000: 0c540000 00000000 1e120000 00000000
> 00000010: d8984a01 03002000 de800000 41000000
> 00000020: 00000000 00000000 00000000 10070000
> 00000030: 00000000 00000000 00000000 00000000
My RCW is identical
> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x02, FPGA Ver: 0x04, vBank: 4
Mine is:
Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 4
> SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
Same.
> I2C: ready
> SPI: ready
> DRAM: Initializing....using SPD
> Detected UDIMM i-DIMM
> Detected UDIMM i-DIMM
> 2 GiB left unmapped
> 4 GiB (DDR3, 64-bit, CL=9, ECC on)
> DDR Controller Interleaving Mode: cache line
> DDR Chip-Select Interleaving Mode: CS0+CS1
> Testing 0x00000000 - 0x7fffffff
> Testing 0x80000000 - 0xffffffff
> Remap DDR 2 GiB left unmapped
>
> POST memory PASSED
> Flash: 128 MiB
> L2: 512 KB enabled
> Corenet Platform Cache: 2048 KB enabled
> SRIO1: disabled
> SRIO2: disabled
> NAND: 1024 MiB
> MMC: FSL_SDHC: 0
> EEPROM: Invalid ID (ff ff ff ff)
> PCIe1: Root Complex, x2, regs @ 0xfe200000
> 01:00.0 - 8086:105e - Network controller
> 01:00.1 - 8086:105e - Network controller
> PCIe1: Bus 00 - 01
> PCIe2: disabled
> PCIe3: Root Complex, no link, regs @ 0xfe202000
> PCIe3: Bus 02 - 02
> PCIe4: disabled
And I never see anything here anymore...
> In: serial
> Out: serial
> Err: serial
> Net: Initializing Fman
> Fman1: Uploading microcode version 106.1.6
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> PHY reset timed out
> e1000: 00:15:17:16:ce:b8
> e1000: 00:15:17:16:ce:b9
> FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4 [PRIME], FM1@DTSEC5, FM1@TGEC1, e1000#0
> Warning: e1000#0 MAC addresses don't match:
> Address in SROM is 00:15:17:16:ce:b8
> Address in environment is 00:1b:21:68:5e:d4
> , e1000#1
> Warning: e1000#1 using MAC address from net device
>
> =>
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Zang Roy-R61911 @ 2013-05-16 7:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, tiejun.chen,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368687218.9603.52.camel@pasglop>
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^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:59 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, tiejun.chen,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E056D@039-SN2MPN1-011.039d.mgd.msft.net>
Ok, so I found this one on the SDK ISO: rcw_15g_2000mhz.bin
I flashed that, did pix altbank, I'm now booted from Bank 4 ... and PCIe
is still showing nothing. I have cards in slots 4 and 7 (assuming that's
the right numbering, ie, 7 is the top one).
Are we sure we don't have a problem with some DIP ? I saw some of them
control some SERDES stuff (SW5 iirc)
Cheers,
Ben.
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: tiejun.chen @ 2013-05-16 6:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368687218.9603.52.camel@pasglop>
On 05/16/2013 02:53 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:49 +0000, Zang Roy-R61911 wrote:
>>
>
>> Please also provide a RCW binary to Ben, if your guys insist updating the RCW.
>
> right, I just noticed it's ascii :-) That isn't going to work well...
Ben,
I already send my workable combination of u-boot and RCW privately to you,
please take a try.
Tiejun
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:53 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, tiejun.chen,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E056D@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:49 +0000, Zang Roy-R61911 wrote:
>
> Please also provide a RCW binary to Ben, if your guys insist updating the RCW.
right, I just noticed it's ascii :-) That isn't going to work well...
Cheers,
Ben.
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:52 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
tiejun.chen, Fleming Andy-AFLEMING, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C498@039-SN2MPN1-012.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:48 +0000, Bhushan Bharat-R65777 wrote:
> 1) Load RCW as Tiejun on some address in DDR.
>
> 2) Brun RCW at 0xec000000:
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b 0x1000000 0xec000000 $filesize
Done.
> 3) run " pix altbak" command
>
> 4) check you are on bank4
It stays on bank 0
Also, before I flashed the rcw, I tried messing with SW7[1:4] and got it
to book to bank 4 once (I think I changed DIP 2 or 3). Now, after the
new RCW is in, it won't boot with any other setting than bank 0 however.
Cheers,
Ben.
> 5) If you are luckier then networking will work for you.
>
> Thanks
> -Bharat
>
> >
> > Tiejun
>
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Zang Roy-R61911 @ 2013-05-16 6:49 UTC (permalink / raw)
To: Bhushan Bharat-R65777, tiejun.chen, Benjamin Herrenschmidt
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C498@039-SN2MPN1-012.039d.mgd.msft.net>
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^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Bhushan Bharat-R65777 @ 2013-05-16 6:48 UTC (permalink / raw)
To: tiejun.chen, Benjamin Herrenschmidt
Cc: Liu Qiang-B32616, linuxppc-dev@lists.ozlabs.org,
Fleming Andy-AFLEMING, Zang Roy-R61911, Xie Shaohui-B21989
In-Reply-To: <5194800D.3010606@windriver.com>
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^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Zang Roy-R61911 @ 2013-05-16 6:48 UTC (permalink / raw)
To: Bhushan Bharat-R65777, Benjamin Herrenschmidt
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C409@039-SN2MPN1-012.039d.mgd.msft.net>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmh1c2hhbiBCaGFyYXQt
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aWQgYnJlYWtpbmcgYmFuazAuDQpUaGFua3MuDQpSb3kNCg==
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: tiejun.chen @ 2013-05-16 6:43 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368686426.9603.49.camel@pasglop>
On 05/16/2013 02:40 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
>> On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
>>> On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
>>>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>>>> please take
>>>> a look at this:
>>>
>>> Ok, how do I update my RCW to bse Bharat's ?
>>
>>
>> Firstly please check which flash bank is used since we have to know where should
>> be updated RCW.
>>
>> What is SW7[1:4]?
>>
>> Or we have another simple way in u-boot prompt:
>>
>> => md.b ffdf002c
>> ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00 O...9...........
>> ...
>
> ffdf002c: 0f 00 fe 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
>
>> This means we're on bank4.
>
> I assume that means bank0 ?
Yes, RCW should be burned to 0xec000000.
In u-boot prompt:
=> loady
## Ready for binary (ymodem) download to 0x01000000 at 115200 bps...
C
Then send that RCW with ymodem in your terminal client.
Tiejun
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: tiejun.chen @ 2013-05-16 6:41 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368686221.9603.48.camel@pasglop>
On 05/16/2013 02:37 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
>> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
>> 0x1000000 0xec000000 $filesize
>
> BTW, is it normal that the network in uboot is *extremely* unreliable ?
We can use serial port:
loadb - load binary file over serial line (kermit mode)
loads - load S-Record file over serial line
loady - load binary file over serial line (ymodem mode)
Then please send the RCW with appropriate mode above in your terminal client.
Tiejun
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:40 UTC (permalink / raw)
To: tiejun.chen
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <51947E35.30808@windriver.com>
On Thu, 2013-05-16 at 14:35 +0800, tiejun.chen wrote:
> On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
> > On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
> >> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
> >> please take
> >> a look at this:
> >
> > Ok, how do I update my RCW to bse Bharat's ?
>
>
> Firstly please check which flash bank is used since we have to know where should
> be updated RCW.
>
> What is SW7[1:4]?
>
> Or we have another simple way in u-boot prompt:
>
> => md.b ffdf002c
> ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00 O...9...........
> ...
ffdf002c: 0f 00 fe 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
> This means we're on bank4.
I assume that means bank0 ?
> >
> > Any DIP switch setting I need to be aware of ?
>
> No.
>
> Tiejun
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Zang Roy-R61911 @ 2013-05-16 6:37 UTC (permalink / raw)
To: tiejun.chen, Benjamin Herrenschmidt
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989,
Bhushan Bharat-R65777
In-Reply-To: <51947E35.30808@windriver.com>
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^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:37 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Liu Qiang-B32616, linuxppc-dev@lists.ozlabs.org,
Fleming Andy-AFLEMING, Zang Roy-R61911, Xie Shaohui-B21989
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C409@039-SN2MPN1-012.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
> 0x1000000 0xec000000 $filesize
BTW, is it normal that the network in uboot is *extremely* unreliable ?
It takes dozens of tries if not more for it to "kick in", then it
eventually works.
I've given on dhcp and using fixed IPs but that doesn't help, tftp fails
several times until it eventually work ... if I'm in a lucky day.
Cheers,
Ben.
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: tiejun.chen @ 2013-05-16 6:35 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, Zang Roy-R61911,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368685307.9603.39.camel@pasglop>
On 05/16/2013 02:21 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2013-05-16 at 14:17 +0800, tiejun.chen wrote:
>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>> please take
>> a look at this:
>
> Ok, how do I update my RCW to bse Bharat's ?
Firstly please check which flash bank is used since we have to know where should
be updated RCW.
What is SW7[1:4]?
Or we have another simple way in u-boot prompt:
=> md.b ffdf002c
ffdf002c: 4f 00 fe 00 39 00 00 00 00 00 00 00 00 00 00 00 O...9...........
...
This means we're on bank4.
>
> Any DIP switch setting I need to be aware of ?
No.
Tiejun
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Zang Roy-R61911 @ 2013-05-16 6:35 UTC (permalink / raw)
To: Bhushan Bharat-R65777, Benjamin Herrenschmidt
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C409@039-SN2MPN1-012.039d.mgd.msft.net>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogQmh1c2hhbiBCaGFyYXQt
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amFtaW4gSGVycmVuc2NobWlkdDsgWmFuZyBSb3ktUjYxOTExDQo+IENjOiBMaXUgUWlhbmctQjMy
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azQuDQpSb3kNCg==
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:34 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Liu Qiang-B32616, linuxppc-dev@lists.ozlabs.org,
Fleming Andy-AFLEMING, Zang Roy-R61911, Xie Shaohui-B21989
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0701C409@039-SN2MPN1-012.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:33 +0000, Bhushan Bharat-R65777 wrote:
> From bank 0
> ------------
>
> tftp 0x1000000 rcw_2sgmii_1500mhz.bin
> protect off 0xec000000 +$filesize; erase 0xec000000 +$filesize; cp.b
> 0x1000000 0xec000000 $filesize
Before I do something irreparable, what do you specifically mean by
"from bank 0" ? :-)
Cheers,
Ben.
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Bhushan Bharat-R65777 @ 2013-05-16 6:33 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Zang Roy-R61911
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989
In-Reply-To: <1368685428.9603.41.camel@pasglop>
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^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:31 UTC (permalink / raw)
To: Xie Shaohui-B21989; +Cc: linuxppc-dev@lists.ozlabs.org, Fleming Andy-AFLEMING
In-Reply-To: <ED492CCEAF882048BC2237DE806547C90B1B1801@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:24 +0000, Xie Shaohui-B21989 wrote:
> Hi, Ben,
>
> Since the p5020ds you tested is a rev1 chip, I think the most possibility that SATA not work
> is due to a SATA erratum, which is fixed in rev1.1, we have a policy that patches for errata that
> are present only on early silicon revisions, typically only rev1 silicon will not send upstream.
> You can find the patch at below link:
> http://git.freescale.com/git/cgit.cgi/ppc/sdk/linux.git/commit/?id=b79a8a0528b8a0008cb76f339806b1200b5d8f63
Well, the chip I have is rev1... since I'm the maintainer I might pull a
"Linus" and just apply the damn patch to make it work for me :-) Though
I'm being told that a rev2 chip is on its way to me ... I'll wait a few
more days see if that arrives.
Cheers,
Ben.
> Since it is not sent to upstream, it may need to be rebased if apply it to latest tree.
>
> Also there might be another issue(SATA & USB) if you test 64 bit kernel on p5020ds with DRR > 4G, we have a patch
> Sent to upstream, but not accepted yet. Link as below:
> http://patchwork.ozlabs.org/patch/179828/
>
> There are online documents of SDK, for the p5020ds hardware please see the link:
> http://www.freescale.com/infocenter/index.jsp?topic=%2FQORIQSDK%2F2989554.html
>
>
> Best Regards,
> Shaohui Xie
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > Sent: Thursday, May 16, 2013 12:48 PM
> > To: Liu Qiang-B32616; Xie Shaohui-B21989; Fleming Andy-AFLEMING
> > Cc: linuxppc-dev@lists.ozlabs.org; Kumar Gala
> > Subject: SATA FSL and upstreaming
> >
> > Hi folks !
> >
> > So I was trying to use my 5020ds to test some stuff today. Since I hadn't
> > used it in a while, I decided to "upgrade" it to the latest NOR etc...
> >
> > Interestingly I discovered that the SATA (which was supposedly dead on
> > the rev1 chip) was actually working with the SDK kernel, while it's still
> > completely busted upstream.
> >
> > A quick git compare shows about 5 or 6 commits in the SDK tree, some as
> > old as 2011, fixing various erratas in that chip, that never made their
> > way upstream.
> >
> > Any reason for that ? Being GPL, I can submit them to Tejun myself but it
> > would be better form if you guys did :-)
> >
> > BTW. Also what's the status with getting the network working upstream ?
> > Even if sub-standard the code could at least go into staging...
> >
> > Cheers,
> > Ben.
> >
> >
>
^ permalink raw reply
* [PATCH] powerpc/mpc85xx: match with the pci bus address used by u-boot for all p1_p2_rdb_pc boards
From: Kevin Hao @ 2013-05-16 6:29 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc
All these boards use the same configuration file p1_p2_rdb_pc.h in
u-boot. So they have the same pci bus address set by the u-boot.
But in some of these boards the bus address set in dtb don't match
the one used by u-boot. And this will trigger a kernel bug in 32bit
kernel and cause the pci device malfunction. For example, on a
p2020rdb-pc board the u-boot use the 0xa0000000 as both bus address
and cpu address for one pci controller and then assign bus address
such as 0xa00004000 to some pci device. But in the kernel, the dtb
set the bus address to 0xe0000000 and the cpu address to 0xa0000000.
The kernel assumes mistakenly the assigned bus address 0xa0004000
in pci device is correct and keep it unchanged. This will definitely
cause the pci device malfunction. I have made two patches to fix
this in the pci subsystem.
http://patchwork.ozlabs.org/patch/243702/
http://patchwork.ozlabs.org/patch/243703/
But I still think it makes sense to set these bus address to match
with the u-boot. This issue can't be reproduced on 36bit kernel.
But I also tweak the 36bit dtb for the above reason.
The cpu address for the pci controller seems also not right in
p1025rdb_32b/36b.dts. So fix it at the same time.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
I just tested this on a p2020rdb-pca board. All others just passed build test.
arch/powerpc/boot/dts/p1020mbg-pc_32b.dts | 4 ++--
arch/powerpc/boot/dts/p1020mbg-pc_36b.dts | 4 ++--
arch/powerpc/boot/dts/p1020utm-pc_32b.dts | 4 ++--
arch/powerpc/boot/dts/p1020utm-pc_36b.dts | 4 ++--
arch/powerpc/boot/dts/p1024rdb_32b.dts | 4 ++--
arch/powerpc/boot/dts/p1024rdb_36b.dts | 4 ++--
arch/powerpc/boot/dts/p1025rdb_32b.dts | 4 ++--
arch/powerpc/boot/dts/p1025rdb_36b.dts | 4 ++--
arch/powerpc/boot/dts/p2020rdb-pc_32b.dts | 4 ++--
arch/powerpc/boot/dts/p2020rdb-pc_36b.dts | 4 ++--
10 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
index ab8f076..042bda5 100644
--- a/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p1020mbg-pc_32b.dts
@@ -56,7 +56,7 @@
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -71,7 +71,7 @@
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts b/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts
index 9e9f401..3afbd1f 100644
--- a/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p1020mbg-pc_36b.dts
@@ -56,7 +56,7 @@
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -71,7 +71,7 @@
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p1020utm-pc_32b.dts b/arch/powerpc/boot/dts/p1020utm-pc_32b.dts
index 4bfdd89..27576eb 100644
--- a/arch/powerpc/boot/dts/p1020utm-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p1020utm-pc_32b.dts
@@ -56,7 +56,7 @@
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -71,7 +71,7 @@
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p1020utm-pc_36b.dts b/arch/powerpc/boot/dts/p1020utm-pc_36b.dts
index abec535..52eabf9c 100644
--- a/arch/powerpc/boot/dts/p1020utm-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p1020utm-pc_36b.dts
@@ -56,7 +56,7 @@
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -71,7 +71,7 @@
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p1024rdb_32b.dts b/arch/powerpc/boot/dts/p1024rdb_32b.dts
index 90e803e..ede1af6 100644
--- a/arch/powerpc/boot/dts/p1024rdb_32b.dts
+++ b/arch/powerpc/boot/dts/p1024rdb_32b.dts
@@ -53,7 +53,7 @@
pci0: pcie@ffe09000 {
reg = <0x0 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -68,7 +68,7 @@
pci1: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
diff --git a/arch/powerpc/boot/dts/p1024rdb_36b.dts b/arch/powerpc/boot/dts/p1024rdb_36b.dts
index 3656825..7642783 100644
--- a/arch/powerpc/boot/dts/p1024rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1024rdb_36b.dts
@@ -53,7 +53,7 @@
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -68,7 +68,7 @@
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
diff --git a/arch/powerpc/boot/dts/p1025rdb_32b.dts b/arch/powerpc/boot/dts/p1025rdb_32b.dts
index ac5729c..6ba7ddd 100644
--- a/arch/powerpc/boot/dts/p1025rdb_32b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_32b.dts
@@ -54,7 +54,7 @@
};
pci0: pcie@ffe09000 {
- ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
pcie@0 {
@@ -70,7 +70,7 @@
pci1: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 06deb6f..4659e2d 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -55,7 +55,7 @@
pci0: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -70,7 +70,7 @@
pci1: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 57573bd..4ab21f8 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -63,7 +63,7 @@
pci1: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -78,7 +78,7 @@
pci0: pcie@ffe0a000 {
reg = <0 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
index 470247e..488f1ad 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -63,7 +63,7 @@
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
@@ -78,7 +78,7 @@
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
pcie@0 {
ranges = <0x2000000 0x0 0xe0000000
--
1.8.1.4
^ permalink raw reply related
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:26 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Xie Shaohui-B21989, Liu Qiang-B32616, tiejun.chen,
Fleming Andy-AFLEMING, Bhushan Bharat-R65777,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E0461@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:20 +0000, Zang Roy-R61911 wrote:
> Why?
> Ben's on board RCW protocol is 0x36, which should work for PCIe1 (slot 7) and PCIe3 (slot4).
> Roy
I've put a card in slot 7 and a card in slot 4 and I still get:
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
PCIe4: disabled
And nothing in Linux... Could there be another issue (DIP ? jumpers ?)
Cheers,
Ben.
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: tiejun.chen @ 2013-05-16 6:25 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Liu Qiang-B32616, Xie Shaohui-B21989, Fleming Andy-AFLEMING,
Bhushan Bharat-R65777, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E0461@039-SN2MPN1-011.039d.mgd.msft.net>
On 05/16/2013 02:20 PM, Zang Roy-R61911 wrote:
>
>
>> -----Original Message-----
>> From: tiejun.chen [mailto:tiejun.chen@windriver.com]
>> Sent: Thursday, May 16, 2013 2:18 PM
>> To: Benjamin Herrenschmidt
>> Cc: Zang Roy-R61911; Liu Qiang-B32616; Fleming Andy-AFLEMING; linuxppc-
>> dev@lists.ozlabs.org; Xie Shaohui-B21989; Bhushan Bharat-R65777
>> Subject: Re: SATA FSL and upstreaming
>>
>> On 05/16/2013 02:09 PM, Benjamin Herrenschmidt wrote:
>>> On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
>>>> I do not suggest changing the RCW. If the RCW is broken on Ben's
>>>> side, it is not easy to recover for him.
>>>> Let's check the U-boot output first.
>>>
>>> U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
>>>
>>> CPU0: P5020E, Version: 1.0, (0x82280010)
>>> Core: E5500, Version: 1.0, (0x80240010) Clock Configuration:
>>> CPU0:2000 MHz, CPU1:2000 MHz,
>>> CCB:800 MHz,
>>> DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous),
>> LBC:100 MHz
>>> FMAN1: 600 MHz
>>> QMAN: 400 MHz
>>> PME: 400 MHz
>>> L1: D-cache 32 kB enabled
>>> I-cache 32 kB enabled
>>> Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
>>> Reset Configuration Word (RCW):
>>> 00000000: 0c540000 00000000 1e120000 00000000
>>> 00000010: d8984a01 03002000 de800000 41000000
>>> 00000020: 00000000 00000000 00000000 10070000
>>> 00000030: 00000000 00000000 00000000 00000000
>>
>> I think you can use Bharat's RCW, which seems RR_HXAPNSP_0x36, then
>> please take a look at this:
> Why?
I just believe Bharat should pick a proper RCW from SDK.
> Ben's on board RCW protocol is 0x36, which should work for PCIe1 (slot 7) and PCIe3 (slot4).
Didn't you see I'm also saying to use slot 7 and slot 4?
Tiejun
^ permalink raw reply
* RE: SATA FSL and upstreaming
From: Xie Shaohui-B21989 @ 2013-05-16 6:24 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Fleming Andy-AFLEMING
Cc: linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1368679657.9603.32.camel@pasglop>
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IENoZWVycywNCj4gQmVuLg0KPiANCj4gDQoNCg==
^ permalink raw reply
* Re: SATA FSL and upstreaming
From: Benjamin Herrenschmidt @ 2013-05-16 6:23 UTC (permalink / raw)
To: Zang Roy-R61911
Cc: Liu Qiang-B32616, Fleming Andy-AFLEMING,
linuxppc-dev@lists.ozlabs.org, Xie Shaohui-B21989,
Bhushan Bharat-R65777
In-Reply-To: <3E027F8168735B46AC006B1D0C7BB0020B1E0442@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-05-16 at 06:17 +0000, Zang Roy-R61911 wrote:
> Do you try slot7?
> PCIe1 connects to slot7 directly.
I tried all slots. None of them sees any card. The card also doesn't
seem to be powered up (none of the LEDs blink, it's an e1000 since I
don't have networking with upstream).
I also tried a different card and uboot is pretty adamant at saying "no
link" :-)
I'll try to update the RCW when I know how to do it :-)
Cheers,
Ben.
> Roy
>
> > -----Original Message-----
> > From: Benjamin Herrenschmidt [mailto:benh@kernel.crashing.org]
> > Sent: Thursday, May 16, 2013 2:09 PM
> > To: Zang Roy-R61911
> > Cc: Bhushan Bharat-R65777; Liu Qiang-B32616; Fleming Andy-AFLEMING;
> > linuxppc-dev@lists.ozlabs.org; Xie Shaohui-B21989
> > Subject: Re: SATA FSL and upstreaming
> >
> > On Thu, 2013-05-16 at 06:05 +0000, Zang Roy-R61911 wrote:
> > > I do not suggest changing the RCW. If the RCW is broken on Ben's side,
> > > it is not easy to recover for him.
> > > Let's check the U-boot output first.
> >
> > U-Boot 2013.01-00009-g7bcd7f4 (Mar 14 2013 - 14:23:16)
> >
> > CPU0: P5020E, Version: 1.0, (0x82280010)
> > Core: E5500, Version: 1.0, (0x80240010)
> > Clock Configuration:
> > CPU0:2000 MHz, CPU1:2000 MHz,
> > CCB:800 MHz,
> > DDR:666.667 MHz (1333.333 MT/s data rate) (Asynchronous), LBC:100
> > MHz
> > FMAN1: 600 MHz
> > QMAN: 400 MHz
> > PME: 400 MHz
> > L1: D-cache 32 kB enabled
> > I-cache 32 kB enabled
> > Board: P5020DS, Sys ID: 0x1c, Sys Ver: 0x12, FPGA Ver: 0x05, vBank: 0
> > Reset Configuration Word (RCW):
> > 00000000: 0c540000 00000000 1e120000 00000000
> > 00000010: d8984a01 03002000 de800000 41000000
> > 00000020: 00000000 00000000 00000000 10070000
> > 00000030: 00000000 00000000 00000000 00000000
> > SERDES Reference Clocks: Bank1=100Mhz Bank2=125Mhz Bank3=125Mhz
> > I2C: ready
> > SPI: ready
> > DRAM: Initializing....using SPD
> > Detected UDIMM i-DIMM
> > Detected UDIMM i-DIMM
> > 2 GiB left unmapped
> > 4 GiB (DDR3, 64-bit, CL=9, ECC on)
> > DDR Controller Interleaving Mode: cache line
> > DDR Chip-Select Interleaving Mode: CS0+CS1
> > Testing 0x00000000 - 0x7fffffff
> > Testing 0x80000000 - 0xffffffff
> > Remap DDR 2 GiB left unmapped
> >
> > POST memory PASSED
> > Flash: 128 MiB
> > L2: 512 KB enabled
> > Corenet Platform Cache: 2048 KB enabled
> > SRIO1: disabled
> > SRIO2: disabled
> > NAND: 1024 MiB
> > MMC: FSL_SDHC: 0
> > EEPROM: NXID v1
> > PCIe1: Root Complex, no link, regs @ 0xfe200000
> > PCIe1: Bus 00 - 00
> > PCIe2: disabled
> > PCIe3: Root Complex, no link, regs @ 0xfe202000
> > PCIe3: Bus 01 - 01
> > PCIe4: disabled
> > In: serial
> > Out: serial
> > Err: serial
> > Net: Initializing Fman
> > Fman1: Uploading microcode version 106.1.7
> > PHY reset timed out
> > PHY reset timed out
> > PHY reset timed out
> > PHY reset timed out
> > FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, FM1@TGEC1
> > Hit any key to stop autoboot: 0
> > =>
> >
> > Cheers,
> > Ben.
> >
> >
>
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