* Re: [PATCH 4/5] powerpc/dts: remove msi-available-ranges property
From: Scott Wood @ 2013-06-14 22:10 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371194159-17332-4-git-send-email-Minghuan.Lian@freescale.com>
On 06/14/2013 02:15:58 AM, Minghuan Lian wrote:
> For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
> 16 MSI registers, but uses different IBS and SRS shift. For the
> first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
> ...0x1f, but when using MSIIR1, the irqs are 0x0 0x10 0x20 ... 0x1f0
> It is hard to describe the available irqs using property
> 'msi-available-ranges'. The patch removes this property.
Only remove it from mpic 4.3. And since you introduced =20
qoriq-mpic4.3.dtsi earlier in the patchset, why didn't you just avoid =20
adding it then?
-Scott=
^ permalink raw reply
* Re: [PATCH 5/5] powerpc/fsl_msi: add 'msiregs' kernel parameter
From: Scott Wood @ 2013-06-14 22:13 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371194159-17332-5-git-send-email-Minghuan.Lian@freescale.com>
On 06/14/2013 02:15:59 AM, Minghuan Lian wrote:
> 1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1
> the IRQs of a register are not continuous. for example, the first
> register irq values are 0x0, 0x10, 0x20, 0x30 ... 0x1f0. So it
> is hard to use 'msi-available-ranges' property to indicate the
> available ranges and 'msi-available-ranges' property has been
> removed from dts node, so this patch removes the related code.
>=20
> 2. Add 'msiregs' kernel parameter instead of 'msi-available-ranges'
> functionality.
The reason we used a device tree property was because this is for =20
virtualization and AMP scenarios where this instance of Linux does not =20
own all of the MSI registers.
I don't see any reasonable way to partition an MPIC v4.3 MSI group -- =20
but there are more groups, so it's not that bad. What's the use case =20
for this patch?
-Scott=
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
From: Scott Wood @ 2013-06-14 22:09 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371194159-17332-2-git-send-email-Minghuan.Lian@freescale.com>
On 06/14/2013 02:15:56 AM, Minghuan Lian wrote:
> @@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct =20
> platform_device *dev)
> }
> msi->msiir_offset =3D
> features->msiir_offset + (res.start & 0xfffff);
> +
> + /*
> + * First read the MSIIR/MSIIR1 offset from dts
> + * If failure use the hardcode MSIIR offset
"On failure"
> + */
> + if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
> + msi->msiir_offset =3D features->msiir_offset +
> + (res.start & =20
> MSIIR_OFFSET_MASK);
> + else
> + msi->msiir_offset =3D msiir.start & =20
> MSIIR_OFFSET_MASK;
> }
>=20
> msi->feature =3D features->fsl_pic_ip;
>=20
> + if (of_device_is_compatible(dev->dev.of_node, =20
> "fsl,mpic-msi-v4.3")) {
> + msi->srs_shift =3D MSIIR1_SRS_SHIFT;
> + msi->ibs_shift =3D MSIIR1_IBS_SHIFT;
> +
> + } else {
> + msi->srs_shift =3D MSIIR_SRS_SHIFT;
> + msi->ibs_shift =3D MSIIR_IBS_SHIFT;
> + }
Remove the blank line just before the "} else {".
> diff --git a/arch/powerpc/sysdev/fsl_msi.h =20
> b/arch/powerpc/sysdev/fsl_msi.h
> index 8225f86..43a9d99 100644
> --- a/arch/powerpc/sysdev/fsl_msi.h
> +++ b/arch/powerpc/sysdev/fsl_msi.h
> @@ -16,7 +16,7 @@
> #include <linux/of.h>
> #include <asm/msi_bitmap.h>
>=20
> -#define NR_MSI_REG 8
> +#define NR_MSI_REG 16
> #define IRQS_PER_MSI_REG 32
> #define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
I don't see where you update all_avail in fsl_of_msi_probe.
We should also be bounds-checking the contents of msi-available-ranges.
Currently it looks like we just silently overrun the bitmap if we get =20
bad
input from the device tree.
-Scott=
^ permalink raw reply
* Re: [PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3
From: Scott Wood @ 2013-06-14 22:06 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371194159-17332-3-git-send-email-Minghuan.Lian@freescale.com>
On 06/14/2013 02:15:57 AM, Minghuan Lian wrote:
> Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
> MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
> 16 MSI registers, but uses different IBS and SRS shift. When using
> MSIR1, the interrupt number is not consecutive. It is hard to use
> 'msi-available-ranges' to describe the ranges of the available
> interrupt and the ranges are related to the application, rather than
> the description of the hardware. this patch also removes
> 'msi-available-ranges' property.
>=20
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> .../devicetree/bindings/powerpc/fsl/msi-pic.txt | 49 =20
> ++++++++++------------
> 1 file changed, 22 insertions(+), 27 deletions(-)
>=20
> diff --git =20
> a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt =20
> b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
> index 5693877..e851e93 100644
> --- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
> @@ -1,26 +1,23 @@
> * Freescale MSI interrupt controller
>=20
> Required properties:
> -- compatible : compatible list, contains 2 entries,
> +- compatible : compatible list, may contains one or two entries,
> first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, =20
> mpc8572,
> - etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending =20
> on
> - the parent type.
> + etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
> + "fsl,mpic-msi-v4.3" depending on the parent type and version. If =20
> mpic
> + version is 4.3, the number of MSI registers is increased to 16, =20
> MSIIR1 is
> + provided to access these 16 registers, compatible =20
> "fsl,mpic-msi-v4.3"
> + should be used.
Why "one or two"? What does it look like in the case where there's =20
just one?
> - reg : It may contain one or two regions. The first region should =20
> contain
> the address and the length of the shared message interrupt =20
> register set.
> - The second region should contain the address of aliased MSIIR =20
> register for
> - platforms that have such an alias.
> -
> -- msi-available-ranges: use <start count> style section to define =20
> which
> - msi interrupt can be used in the 256 msi interrupts. This property =20
> is
> - optional, without this, all the 256 MSI interrupts can be used.
> - Each available range must begin and end on a multiple of 32 (i.e.
> - no splitting an individual MSI register or the associated PIC =20
> interrupt).
> + The second region should contain the address of aliased MSIIR or =20
> MSIIR1
> + register for platforms that have such an alias, if using MSIIR1, =20
> the second
> + region must be added because different MSI group has different =20
> MSIRR1 offset.
Why are you removing msi-available-ranges? It's not valid for MPIC =20
v4.3, but it's still valid for older MPICs. It should move to the =20
optional section, though.
> - interrupts : each one of the interrupts here is one entry per 32 =20
> MSIs,
> and routed to the host interrupt controller. the interrupts should
> - be set as edge sensitive. If msi-available-ranges is present, only
> - the interrupts that correspond to available ranges shall be =20
> present.
> + be set as edge sensitive.
>=20
> - interrupt-parent: the phandle for the interrupt controller
> that services interrupts for this device. for 83xx cpu, the =20
> interrupts
> @@ -39,20 +36,18 @@ Optional properties:
>=20
> Example:
> msi@41600 {
> - compatible =3D "fsl,mpc8610-msi", "fsl,mpic-msi";
> - reg =3D <0x41600 0x80>;
> - msi-available-ranges =3D <0 0x100>;
> - interrupts =3D <
> - 0xe0 0
> - 0xe1 0
> - 0xe2 0
> - 0xe3 0
> - 0xe4 0
> - 0xe5 0
> - 0xe6 0
> - 0xe7 0>;
> - interrupt-parent =3D <&mpic>;
> - };
> + compatible =3D "fsl,mpic-msi";
> + reg =3D <0x41600 0x200 0x44140 4>;
Why 0x200?
-Scott=
^ permalink raw reply
* Re: [PATCH] dtc: ensure #line directives don't consume data from the next line
From: Grant Likely @ 2013-06-14 22:01 UTC (permalink / raw)
To: Stephen Warren, Rob Herring
Cc: Michal Marek, jdl, Stephen Warren, Ian Campbell, linux-kbuild,
devicetree-discuss, linux-kernel, linuxppc-dev
In-Reply-To: <51AF6C3A.5020609@wwwdotorg.org>
On Wed, 05 Jun 2013 10:50:02 -0600, Stephen Warren <swarren@wwwdotorg.org> wrote:
> On 06/03/2013 09:36 AM, Stephen Warren wrote:
> > From: Stephen Warren <swarren@nvidia.com>
> >
> > Previously, the #line parsing regex ended with ({WS}+[0-9]+)?. The {WS}
> > could match line-break characters. If the #line directive did not contain
> > the optional flags field at the end, this could cause any integer data on
> > the next line to be consumed as part of the #line directive parsing. This
> > could cause syntax errors (i.e. #line parsing consuming the leading 0
> > from a hex literal 0x1234, leaving x1234 to be parsed as cell data,
> > which is a syntax error), or invalid compilation results (i.e. simply
> > consuming literal 1234 as part of the #line processing, thus removing it
> > from the cell data).
> >
> > Fix this by replacing {WS} with [ \t] so that it can't match line-breaks.
> >
> > Convert all instances of {WS}, even though the other instances should be
> > irrelevant for any well-formed #line directive. This is done for
> > consistency and ultimate safety.
> >
> > This is a port of upstream dtc commit a1ee6f0 (with same subject) to the
> > kernel's copy of dtc.
>
> Rob, Grant, does this look OK to apply for v3.10-rc*?
The fix is in mainline now. Please check to make sure it is working for you.
g.
--
email sent from notmuch.vim plugin
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
From: Scott Wood @ 2013-06-14 21:53 UTC (permalink / raw)
To: Scott Wood; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371242366.2996.10@snotra>
On 06/14/2013 03:39:26 PM, Scott Wood wrote:
> On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
>> +msi0: msi@41600 {
>> + compatible =3D "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
>=20
> More specific compatibles come first -- and I don't think this is =20
> 100% backwards compatible with "fsl,mpic-msi" anyway.
Also please update the binding.
-Scott=
^ permalink raw reply
* Re: Regression in RCU subsystem in latest mainline kernel
From: Steven Rostedt @ 2013-06-14 21:06 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: paulmck, linuxppc-dev, linux-kernel
In-Reply-To: <1645938.As0LR1yeVd@pcimr>
On Fri, 2013-06-14 at 14:46 +0200, Rojhalat Ibrahim wrote:
> On Friday 14 June 2013 05:28:00 Paul E. McKenney wrote:
> > On Fri, Jun 14, 2013 at 01:47:00PM +0200, Rojhalat Ibrahim wrote:
> > > Hi,
> > >
> > > the current mainline kernel from git reproducibly hangs on my Freescale
> > > PowerPC P5020DS development system. Most of the time the hang occurs
> > > during
> > > boot (kernel just stops booting, system hangs), sometimes shortly after
> > > booting (system hangs, no message). Very often booting stops at the
> > > initialization of the Intel PRO 1000 PCIe network device (e1000e).
I was pretty much able to reproduce this on my PA Semi PPC box. Funny
thing is, when I type on the console, it makes progress. Anyway, it
seems that powerpc has an issue with irq_work(). I'll try to get some
time either tonight or next week to figure it out.
Thanks!
-- Steve
> > >
> > > I used git bisect and arrived at this commit:
> > >
> > > 016a8d5be6ddcc72ef0432d82d9f6fa34f61b907
> > > rcu: Don't call wakeup() with rcu_node structure ->lock held
> > >
> > > With versions before that commit the system runs normally.
> >
> > Odd, given that this fix was intended to prevent hangs. Could you
> > please send your .config?
> >
> > Thanx, Paul
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
From: Scott Wood @ 2013-06-14 20:39 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1371194159-17332-1-git-send-email-Minghuan.Lian@freescale.com>
On 06/14/2013 02:15:55 AM, Minghuan Lian wrote:
> +msi0: msi@41600 {
> + compatible =3D "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
More specific compatibles come first -- and I don't think this is 100% =20
backwards compatible with "fsl,mpic-msi" anyway.
-Scott=
^ permalink raw reply
* Re: [PATCH v2] powerpc/pci: Fix setup of Freescale PCI / PCIe controllers
From: Scott Wood @ 2013-06-14 20:18 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev, linux-kernel, Michael Guntsche
In-Reply-To: <2819373.IXRuYOYOkX@pcimr>
On 06/14/2013 04:05:34 AM, Rojhalat Ibrahim wrote:
> Commit 50d8f87d2b3 (powerpc/fsl-pci Make PCIe hotplug work with =20
> Freescale
> PCIe controllers) does not handle non-PCIe controllers properly, =20
> which causes
> a panic during boot for certain configurations.
> This patch fixes the issue by calling setup_indirect_pci for all =20
> device types.
> fsl_indirect_read_config is now only used for booke/86xx PCIe =20
> controllers.
>=20
> Reported-by: Michael Guntsche <mike@it-loops.com>
> Cc: Scott Wood <scottwood@freescale.com>
> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
> ---
> v2: Make it more consistent.
>=20
> arch/powerpc/sysdev/fsl_pci.c | 20 +++++++-------------
> 1 file changed, 7 insertions(+), 13 deletions(-)
>=20
> diff --git a/arch/powerpc/sysdev/fsl_pci.c =20
> b/arch/powerpc/sysdev/fsl_pci.c
> index 028ac1f..5682c8a 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -97,20 +97,12 @@ static int fsl_indirect_read_config(struct =20
> pci_bus *bus,
> unsigned int devfn,
> return indirect_read_config(bus, devfn, offset, len, val);
> }
>=20
> -static struct pci_ops fsl_indirect_pci_ops =3D
> +static struct pci_ops fsl_indirect_pcie_ops =3D
> {
> .read =3D fsl_indirect_read_config,
> .write =3D indirect_write_config,
> };
On 83xx:
cc1: warnings being treated as errors
/home/scott/fsl/git/linux/upstream/arch/powerpc/sysdev/fsl_pci.c:100:23: =20
error: 'fsl_indirect_pcie_ops' defined but not used
make[2]: *** [arch/powerpc/sysdev/fsl_pci.o] Error 1
make[2]: *** Waiting for unfinished jobs....
I can fix this when applying, but this makes me wonder how you tested =20
it, given that the whole point is to fix 83xx... Did you fix this and =20
then accidentally sent a stale version?
Also, please be careful that the patch doesn't get line wrapped -- I =20
had to manually unwrap a couple places. Use git send-email if you =20
can't get KMail to cooperate.
-Scott=
^ permalink raw reply
* [PATCH] trivial: powerpc: fix typo in ioei_interrupt() description
From: Sebastien Bessiere @ 2013-06-14 15:57 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Sebastien Bessiere
Signed-off-by: Sebastien Bessiere <sebastien.bessiere@gmail.com>
---
arch/powerpc/platforms/pseries/io_event_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/pseries/io_event_irq.c b/arch/powerpc/platforms/pseries/io_event_irq.c
index ef9d9d8..5ea88d1 100644
--- a/arch/powerpc/platforms/pseries/io_event_irq.c
+++ b/arch/powerpc/platforms/pseries/io_event_irq.c
@@ -115,7 +115,7 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
* by scope or event type alone. For example, Torrent ISR route change
* event is reported with scope 0x00 (Not Applicatable) rather than
* 0x3B (Torrent-hub). It is better to let the clients to identify
- * who owns the the event.
+ * who owns the event.
*/
static irqreturn_t ioei_interrupt(int irq, void *dev_id)
--
1.7.9.5
^ permalink raw reply related
* [PATCH] powerpc: Fix emulation of illegal instructions on PowerNV platform
From: Paul Mackerras @ 2013-06-14 10:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
Normally, the kernel emulates a few instructions that are unimplemented
on some processors (e.g. the old dcba instruction), or privileged (e.g.
mfpvr). The emulation of unimplemented instructions is currently not
working on the PowerNV platform. The reason is that on these machines,
unimplemented and illegal instructions cause a hypervisor emulation
assist interrupt, rather than a program interrupt as on older CPUs.
Our vector for the emulation assist interrupt just calls
program_check_exception() directly, without setting the bit in SRR1
that indicates an illegal instruction interrupt. This fixes it by
making the emulation assist interrupt set that bit before calling
program_check_interrupt(). With this, old programs that use no-longer
implemented instructions such as dcba now work again.
Signed-off-by: Paul Mackerras <paulus@samba.org>
---
arch/powerpc/kernel/exceptions-64s.S | 2 +-
arch/powerpc/kernel/traps.c | 10 ++++++++++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index e783453..40e4a17 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -683,7 +683,7 @@ machine_check_common:
STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
- STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
+ STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
#ifdef CONFIG_PPC_DOORBELL
STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f18c79c..c0e5caf 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1165,6 +1165,16 @@ bail:
exception_exit(prev_state);
}
+/*
+ * This occurs when running in hypervisor mode on POWER6 or later
+ * and an illegal instruction is encountered.
+ */
+void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
+{
+ regs->msr |= REASON_ILLEGAL;
+ program_check_exception(regs);
+}
+
void alignment_exception(struct pt_regs *regs)
{
enum ctx_state prev_state = exception_enter();
--
1.7.10.4
^ permalink raw reply related
* [PATCH v2] powerpc/pci: Fix setup of Freescale PCI / PCIe controllers
From: Rojhalat Ibrahim @ 2013-06-14 9:05 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, linux-kernel, Michael Guntsche
Commit 50d8f87d2b3 (powerpc/fsl-pci Make PCIe hotplug work with Freescale
PCIe controllers) does not handle non-PCIe controllers properly, which causes
a panic during boot for certain configurations.
This patch fixes the issue by calling setup_indirect_pci for all device types.
fsl_indirect_read_config is now only used for booke/86xx PCIe controllers.
Reported-by: Michael Guntsche <mike@it-loops.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de>
---
v2: Make it more consistent.
arch/powerpc/sysdev/fsl_pci.c | 20 +++++++-------------
1 file changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 028ac1f..5682c8a 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -97,20 +97,12 @@ static int fsl_indirect_read_config(struct pci_bus *bus,
unsigned int devfn,
return indirect_read_config(bus, devfn, offset, len, val);
}
-static struct pci_ops fsl_indirect_pci_ops =
+static struct pci_ops fsl_indirect_pcie_ops =
{
.read = fsl_indirect_read_config,
.write = indirect_write_config,
};
-static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
- resource_size_t cfg_addr,
- resource_size_t cfg_data, u32 flags)
-{
- setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
- hose->ops = &fsl_indirect_pci_ops;
-}
-
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
#define MAX_PHYS_ADDR_BITS 40
@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev,
int is_primary)
if (!hose->private_data)
goto no_bridge;
- fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
- PPC_INDIRECT_TYPE_BIG_ENDIAN);
+ setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+ PPC_INDIRECT_TYPE_BIG_ENDIAN);
if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+ /* use fsl_indirect_read_config for PCIe */
+ hose->ops = &fsl_indirect_pcie_ops;
/* For PCIE read HEADER_TYPE to identify controler mode */
early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
if (ret)
goto err0;
} else {
- fsl_setup_indirect_pci(hose, rsrc_cfg.start,
- rsrc_cfg.start + 4, 0);
+ setup_indirect_pci(hose, rsrc_cfg.start,
+ rsrc_cfg.start + 4, 0);
}
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
--
1.8.1.5
^ permalink raw reply related
* [PATCH] powerpc/85xx: Add P1023RDB board support
From: Chunhe Lan @ 2013-06-14 8:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Chunhe Lan
P1023RDB Specification:
-----------------------
Memory subsystem:
512MB DDR3 (Fixed DDR on board)
64MB NOR flash
128MB NAND flash
Ethernet:
eTSEC1: Connected to Atheros AR8035 GETH PHY
eTSEC2: Connected to Atheros AR8035 GETH PHY
PCIe:
Three mini-PCIe slots
USB:
Two USB2.0 Type A ports
I2C:
AT24C08 8K Board EEPROM (8 bit address)
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
---
arch/powerpc/boot/dts/p1023rdb.dts | 191 ++++++++++++++++++++++++++
arch/powerpc/configs/85xx/p1023rds_defconfig | 4 +
arch/powerpc/platforms/85xx/Kconfig | 6 +
arch/powerpc/platforms/85xx/p1023_rds.c | 24 +++-
4 files changed, 224 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p1023rdb.dts
diff --git a/arch/powerpc/boot/dts/p1023rdb.dts b/arch/powerpc/boot/dts/p1023rdb.dts
new file mode 100644
index 0000000..4ce1cc9
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1023rdb.dts
@@ -0,0 +1,191 @@
+/*
+ * P1023 RDB Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Author: Roy Zang <tie-fei.zang@freescale.com>
+ * Chunhe Lan <Chunhe.Lan@freescale.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1023si-pre.dtsi"
+
+/ {
+ model = "fsl,P1023";
+ compatible = "fsl,P1023RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ff600000 {
+ ranges = <0x0 0x0 0xff600000 0x200000>;
+
+ i2c@3000 {
+ eeprom@53 {
+ compatible = "at24,24c04";
+ reg = <0x53>;
+ };
+
+ rtc@6f {
+ compatible = "microchip,mcp7941x";
+ reg = <0x6f>;
+ };
+ };
+
+ usb@22000 {
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+ };
+
+ lbc: localbus@ff605000 {
+ reg = <0 0xff605000 0 0x1000>;
+
+ /* NOR Flash */
+ ranges = <0x0 0x0 0x0 0xec000000 0x04000000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x04000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ label = "ramdisk";
+ reg = <0x00000000 0x03000000>;
+ };
+ partition@3000000 {
+ label = "kernel";
+ reg = <0x03000000 0x00ee0000>;
+ };
+ partiton@3ee0000 {
+ label = "dtb";
+ reg = <0x03ee0000 0x00020000>;
+ };
+ partition@3f00000 {
+ label = "firmware";
+ reg = <0x03f00000 0x00080000>;
+ read-only;
+ };
+ partition@3f80000 {
+ label = "u-boot";
+ reg = <0x03f80000 0x00080000>;
+ read-only;
+ };
+ };
+ };
+
+ pci0: pcie@ff60a000 {
+ reg = <0 0xff60a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ pcie@0 {
+ /* IRQ[0:3] are pulled up on board, set to active-low */
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 0 1 0 0
+ 0000 0 0 2 &mpic 1 1 0 0
+ 0000 0 0 3 &mpic 2 1 0 0
+ 0000 0 0 4 &mpic 3 1 0 0
+ >;
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ board_pci1: pci1: pcie@ff609000 {
+ reg = <0 0xff609000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ pcie@0 {
+ /*
+ * IRQ[4:6] only for PCIe, set to active-high,
+ * IRQ[7] is pulled up on board, set to active-low
+ */
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 4 2 0 0
+ 0000 0 0 2 &mpic 5 2 0 0
+ 0000 0 0 3 &mpic 6 2 0 0
+ 0000 0 0 4 &mpic 7 1 0 0
+ >;
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci2: pcie@ff60b000 {
+ reg = <0 0xff60b000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ /*
+ * IRQ[8:10] are pulled up on board, set to active-low
+ * IRQ[11] only for PCIe, set to active-high,
+ */
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0 0 1 &mpic 8 1 0 0
+ 0000 0 0 2 &mpic 9 1 0 0
+ 0000 0 0 3 &mpic 10 1 0 0
+ 0000 0 0 4 &mpic 11 2 0 0
+ >;
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+};
+
+/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig
index b80bcc6..092a746 100644
--- a/arch/powerpc/configs/85xx/p1023rds_defconfig
+++ b/arch/powerpc/configs/85xx/p1023rds_defconfig
@@ -22,6 +22,7 @@ CONFIG_MODVERSIONS=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
+CONFIG_P1023_RDB=y
CONFIG_P1023_RDS=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
@@ -67,6 +68,7 @@ CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_EEPROM_AT24=y
CONFIG_EEPROM_LEGACY=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_ST=y
@@ -102,6 +104,7 @@ CONFIG_SERIAL_8250_RSA=y
CONFIG_SERIAL_QE=m
CONFIG_NVRAM=y
CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
CONFIG_I2C_CPM=m
CONFIG_I2C_MPC=y
CONFIG_GPIO_MPC8XXX=y
@@ -121,6 +124,7 @@ CONFIG_USB_STORAGE=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index efdd37c..d0e8ff9 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -111,6 +111,12 @@ config P1022_RDK
This option enables support for the Freescale / iVeia P1022RDK
reference board.
+config P1023_RDB
+ bool "Freescale P1023 RDB"
+ select P1023_RDS
+ help
+ This option enables support for the P1023 RDB board
+
config P1023_RDS
bool "Freescale P1023 RDS"
select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rds.c
index 9cc60a7..2ae9d49 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
*
* Author: Roy Zang <tie-fei.zang@freescale.com>
*
@@ -86,6 +86,7 @@ static void __init mpc85xx_rds_setup_arch(void)
}
machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
+machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
static void __init mpc85xx_rds_pic_init(void)
{
@@ -106,6 +107,14 @@ static int __init p1023_rds_probe(void)
}
+static int __init p1023_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,P1023RDB");
+
+}
+
define_machine(p1023_rds) {
.name = "P1023 RDS",
.probe = p1023_rds_probe,
@@ -120,3 +129,16 @@ define_machine(p1023_rds) {
#endif
};
+define_machine(p1023_rdb) {
+ .name = "P1023 RDB",
+ .probe = p1023_rdb_probe,
+ .setup_arch = mpc85xx_rds_setup_arch,
+ .init_IRQ = mpc85xx_rds_pic_init,
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+};
--
1.7.6.5
^ permalink raw reply related
* Re: [BUG] PCI related panic on powerpc based board with 3.10-rcX
From: Rojhalat Ibrahim @ 2013-06-14 7:55 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, linux-kernel, Michael Guntsche
In-Reply-To: <1371142157.2028.9@snotra>
On Thursday 13 June 2013 11:49:17 Scott Wood wrote:
> On 06/13/2013 02:21:24 AM, Rojhalat Ibrahim wrote:
> > On Wednesday 12 June 2013 16:50:26 Scott Wood wrote:
> > > On 06/12/2013 03:19:30 AM, Rojhalat Ibrahim wrote:
> > > > On Tuesday 11 June 2013 12:28:59 Scott Wood wrote:
> > > > > Yes, I figured it was non-PCIe because the code change that you
> >
> > said
> >
> > > > > helped was on the non-PCIe branch of the if/else. Generally
> >
> > it's
> >
> > > > good
> > > >
> > > > > to explicitly mention the chip you're using, though.
> > > > >
> > > > > fsl_setup_indirect_pci should be renamed to
> >
> > fsl_setup_indirect_pcie.
> >
> > > > > Your patch above should be applied, and fsl_setup_indirect_pcie
> > > >
> > > > should
> > > >
> > > > > be moved into the booke/86xx ifdef to avoid an unused function
> > > >
> > > > warning.
> > > >
> > > > > -Scott
> > > >
> > > > How about this patch? It uses setup_indirect_pci for the PCI case
> >
> > in
> >
> > > > mpc83xx_add_bridge. Additionally it adds a check in
> > > > fsl_setup_indirect_pci
> > > > to only use the modified read function in case of PCIe.
> > >
> > > If we're adding the check to fsl_setup_indirect_pci, there's no
> >
> > need to
> >
> > > change the 83xx call back to setup_indirect_pci. I see that 85xx is
> > > also callirng fsl_setup_indirect_pci for both; it'd be good to be
> > > consistent.
> > >
> > > In any case, can you send a proper patch with a signoff and commit
> > > message?
> > >
> > > -Scott
> >
> > Where is it called for 85xx? As far as I can tell
> > fsl_setup_indirect_pci is
> > called exactly once in fsl_add_bridge and nowhere else (after
> > applying the
> > proposed patch).
>
> fsl_add_bridge() is where it's called for 85xx.
>
> > For 83xx the decision between PCI and PCIe has already been made at
> > the point where the setup function is called. So IMO it doesn't make
> > sense
> > to call fsl_setup_indirect_pci and do the check again. Moreover PCIe
> > on 83xx
> > uses a completely different set of functions.
>
> My concern is consistency. E.g. if 85xx is using
> fsl_setup_indirect_pci for both, but 83xx isn't, then a developer using
> 83xx could end up breaking 85xx by introducing another PCIe dependency
> in fsl_setup_indirect_pci. Or an 85xx developer could put something
> non-PCIe-related in fsl_setup_indirect_pci that 83xx would benefit from.
>
> Alternatively, you could call it fsl_setup_indirect_pcie, and move the
> PCIe check into fsl_add_bridge().
>
> -Scott
Ok. I'll post a v2 of the patch.
Rojhalat
^ permalink raw reply
* [PATCH 4/5] powerpc/dts: remove msi-available-ranges property
From: Minghuan Lian @ 2013-06-14 7:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
In-Reply-To: <1371194159-17332-1-git-send-email-Minghuan.Lian@freescale.com>
For MPIC v4.3 MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. For the
first register, when using MSIIR we will get the irqs 0x0 0x1 0x2
...0x1f, but when using MSIIR1, the irqs are 0x0 0x10 0x20 ... 0x1f0
It is hard to describe the available irqs using property
'msi-available-ranges'. The patch removes this property.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 1 -
arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi | 3 ---
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi | 4 ----
3 files changed, 8 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index 71c30eb..1ac4f23 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -66,7 +66,6 @@ message@41400 {
msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index 08f4227..cf7355c 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -54,7 +54,6 @@ timer@41100 {
msi0: msi@41600 {
compatible = "fsl,mpic-msi";
reg = <0x41600 0x200 0x44140 4>;
- msi-available-ranges = <0 0x100>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
@@ -69,7 +68,6 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = "fsl,mpic-msi";
reg = <0x41800 0x200 0x45140 4>;
- msi-available-ranges = <0 0x100>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
@@ -84,7 +82,6 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = "fsl,mpic-msi";
reg = <0x41a00 0x200 0x46140 4>;
- msi-available-ranges = <0 0x100>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
index e2665b8..8a997ea 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
@@ -54,7 +54,6 @@ timer@41100 {
msi0: msi@41600 {
compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
reg = <0x41600 0x200 0x44148 4>;
- msi-available-ranges = <0 0x200>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
@@ -77,7 +76,6 @@ msi0: msi@41600 {
msi1: msi@41800 {
compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
reg = <0x41800 0x200 0x45148 4>;
- msi-available-ranges = <0 0x200>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
@@ -100,7 +98,6 @@ msi1: msi@41800 {
msi2: msi@41a00 {
compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
reg = <0x41a00 0x200 0x46148 4>;
- msi-available-ranges = <0 0x200>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
@@ -123,7 +120,6 @@ msi2: msi@41a00 {
msi3: msi@41c00 {
compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
reg = <0x41c00 0x200 0x47148 4>;
- msi-available-ranges = <0 0x200>;
interrupts = <
0xf8 0 0 0
0xf9 0 0 0
--
1.8.1.2
^ permalink raw reply related
* [PATCH 5/5] powerpc/fsl_msi: add 'msiregs' kernel parameter
From: Minghuan Lian @ 2013-06-14 7:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
In-Reply-To: <1371194159-17332-1-git-send-email-Minghuan.Lian@freescale.com>
1. Only MSIIR1 can index 16 MSI registers, but when using MSIIR1
the IRQs of a register are not continuous. for example, the first
register irq values are 0x0, 0x10, 0x20, 0x30 ... 0x1f0. So it
is hard to use 'msi-available-ranges' property to indicate the
available ranges and 'msi-available-ranges' property has been
removed from dts node, so this patch removes the related code.
2. Add 'msiregs' kernel parameter instead of 'msi-available-ranges'
functionality. 'msiregs' is used to indicate the available MSI
registers ranges and uses a colon ':' to separate the multiple
banks. The range representation format is 'start-end', 'start'
and 'end' are integers describe the start and end register index,
the available registers lies between start and end and not include
end. For example, the available register x satisfying
start <= x < end.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
arch/powerpc/sysdev/fsl_msi.c | 118 ++++++++++++++++++++++++++++--------------
arch/powerpc/sysdev/fsl_msi.h | 1 +
2 files changed, 80 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 34510b7..db382ef9b 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -52,6 +52,60 @@ struct fsl_msi_cascade_data {
int index;
};
+struct msi_reg_range {
+ u32 start;
+ u32 end;
+};
+
+static struct msi_reg_range msiregs[NR_MSI_BANK] = {
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+ {.start = 0, .end = NR_MSI_REG },
+};
+
+/*
+ * Handle 'msiregs' parameter.
+ * msiregs is used to indicate the available MSI registers range and
+ * uses colon ':' to separate the multiple banks ranges.
+ * For each bank, the registers range format is 'start-end'
+ * start and end are integers, used to the indicate the start and end
+ * register index. The range is a set of real numbers that lies between
+ * start and end but not include end. For example, the set of all numbers
+ * x satisfying start <= x < end.
+ * if no range specified, driver will use the default range including all
+ * the registers.
+ * if you do no want to use this bank, you can set range as '0-0'
+ * For example msiregs=0-16:0-0::0-2
+ */
+static int msi_regs_setup(char *s)
+{
+ int bank = 0;
+ char *p;
+ struct msi_reg_range *range;
+
+ while ((p = strsep(&s, ":")) != NULL) {
+ int start = 0, end = NR_MSI_REG;
+
+ if (bank >= NR_MSI_BANK)
+ break;
+ range = &msiregs[bank];
+
+ if ((*p != '\0') && (sscanf(p, "%d-%d", &start, &end) < 1))
+ pr_err("msiregs correct format is: start-end\n");
+
+ /* Ok, gets the specified value */
+ range->start = start;
+ range->end = end;
+ pr_info("MSI bank%d available regs range is %d-%d\n",
+ bank, range->start, range->end);
+ bank++;
+ }
+ return 1;
+}
+
+__setup("msiregs=", msi_regs_setup);
+
static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
@@ -350,7 +404,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
static struct lock_class_key fsl_msi_irq_class;
static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
- int offset, int irq_index)
+ int irq_index)
{
struct fsl_msi_cascade_data *cascade_data = NULL;
int virt_msir, i;
@@ -369,7 +423,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
}
irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
msi->msi_virqs[irq_index] = virt_msir;
- cascade_data->index = offset;
+ cascade_data->index = irq_index;
cascade_data->msi_data = msi;
irq_set_handler_data(virt_msir, cascade_data);
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
@@ -377,7 +431,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
/* Release the hwirqs corresponding to this MSI register */
for (i = 0; i < IRQS_PER_MSI_REG; i++)
msi_bitmap_free_hwirqs(&msi->bitmap,
- msi_hwirq(msi, offset, i), 1);
+ msi_hwirq(msi, irq_index, i), 1);
return 0;
}
@@ -387,21 +441,29 @@ static int fsl_of_msi_probe(struct platform_device *dev)
{
const struct of_device_id *match;
struct fsl_msi *msi;
+ static int bank;
+ struct msi_reg_range *range;
struct resource res, msiir;
- int err, i, j, irq_index, count;
+ int err, irq_index, count;
int rc;
- const u32 *p;
const struct fsl_msi_feature *features;
- int len;
- u32 offset;
- static const u32 all_avail[] = { 0, NR_MSI_IRQS };
match = of_match_device(fsl_of_msi_ids, &dev->dev);
if (!match)
return -EINVAL;
features = match->data;
- printk(KERN_DEBUG "Setting up Freescale MSI support\n");
+ if (bank >= NR_MSI_BANK)
+ return -EINVAL;
+ range = &msiregs[bank];
+ pr_debug("Setting up Freescale MSI bank%d support\n", bank);
+
+ count = of_irq_count(dev->dev.of_node);
+ if (!count)
+ return -ENODEV;
+
+ if (count > NR_MSI_REG)
+ count = NR_MSI_REG;
msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
if (!msi) {
@@ -475,39 +537,17 @@ static int fsl_of_msi_probe(struct platform_device *dev)
goto error_out;
}
- p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
- if (p && len % (2 * sizeof(u32)) != 0) {
- dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
- __func__);
- err = -EINVAL;
- goto error_out;
- }
-
- if (!p) {
- p = all_avail;
- len = sizeof(all_avail);
- }
-
- for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
- if (p[i * 2] % IRQS_PER_MSI_REG ||
- p[i * 2 + 1] % IRQS_PER_MSI_REG) {
- printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
- __func__, dev->dev.of_node->full_name,
- p[i * 2 + 1], p[i * 2]);
- err = -EINVAL;
+ for (irq_index = 0; irq_index < count; irq_index++) {
+ /* Check whether the register is contained in range */
+ if (irq_index < range->start ||
+ irq_index >= range->end)
+ continue;
+ err = fsl_msi_setup_hwirq(msi, dev, irq_index);
+ if (err)
goto error_out;
- }
-
- offset = p[i * 2] / IRQS_PER_MSI_REG;
- count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
-
- for (j = 0; j < count; j++, irq_index++) {
- err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index);
- if (err)
- goto error_out;
- }
}
+ bank++;
list_add_tail(&msi->list, &msi_head);
/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 43a9d99..6048415 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -16,6 +16,7 @@
#include <linux/of.h>
#include <asm/msi_bitmap.h>
+#define NR_MSI_BANK 4
#define NR_MSI_REG 16
#define IRQS_PER_MSI_REG 32
#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
--
1.8.1.2
^ permalink raw reply related
* [PATCH 3/5] powerpc/dts: update MSI bindings doc for MPIC v4.3
From: Minghuan Lian @ 2013-06-14 7:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
In-Reply-To: <1371194159-17332-1-git-send-email-Minghuan.Lian@freescale.com>
Add compatible "fsl,mpic-msi-v4.3" for MPIC v4.3. MPIC v4.3 contains
MSIIR and MSIIR1. MSIIR supports 8 MSI registers and MSIIR1 supports
16 MSI registers, but uses different IBS and SRS shift. When using
MSIR1, the interrupt number is not consecutive. It is hard to use
'msi-available-ranges' to describe the ranges of the available
interrupt and the ranges are related to the application, rather than
the description of the hardware. this patch also removes
'msi-available-ranges' property.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
.../devicetree/bindings/powerpc/fsl/msi-pic.txt | 49 ++++++++++------------
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
index 5693877..e851e93 100644
--- a/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+++ b/Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
@@ -1,26 +1,23 @@
* Freescale MSI interrupt controller
Required properties:
-- compatible : compatible list, contains 2 entries,
+- compatible : compatible list, may contains one or two entries,
first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
- etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
- the parent type.
+ etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
+ "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
+ version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
+ provided to access these 16 registers, compatible "fsl,mpic-msi-v4.3"
+ should be used.
- reg : It may contain one or two regions. The first region should contain
the address and the length of the shared message interrupt register set.
- The second region should contain the address of aliased MSIIR register for
- platforms that have such an alias.
-
-- msi-available-ranges: use <start count> style section to define which
- msi interrupt can be used in the 256 msi interrupts. This property is
- optional, without this, all the 256 MSI interrupts can be used.
- Each available range must begin and end on a multiple of 32 (i.e.
- no splitting an individual MSI register or the associated PIC interrupt).
+ The second region should contain the address of aliased MSIIR or MSIIR1
+ register for platforms that have such an alias, if using MSIIR1, the second
+ region must be added because different MSI group has different MSIRR1 offset.
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
and routed to the host interrupt controller. the interrupts should
- be set as edge sensitive. If msi-available-ranges is present, only
- the interrupts that correspond to available ranges shall be present.
+ be set as edge sensitive.
- interrupt-parent: the phandle for the interrupt controller
that services interrupts for this device. for 83xx cpu, the interrupts
@@ -39,20 +36,18 @@ Optional properties:
Example:
msi@41600 {
- compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
- msi-available-ranges = <0 0x100>;
- interrupts = <
- 0xe0 0
- 0xe1 0
- 0xe2 0
- 0xe3 0
- 0xe4 0
- 0xe5 0
- 0xe6 0
- 0xe7 0>;
- interrupt-parent = <&mpic>;
- };
+ compatible = "fsl,mpic-msi";
+ reg = <0x41600 0x200 0x44140 4>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0>;
+};
The Freescale hypervisor and msi-address-64
-------------------------------------------
--
1.8.1.2
^ permalink raw reply related
* [PATCH 2/5] powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3
From: Minghuan Lian @ 2013-06-14 7:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
In-Reply-To: <1371194159-17332-1-git-send-email-Minghuan.Lian@freescale.com>
MPIC controller v4.3 provides MSIIR1 to index 16 MSI registers.
MSIIR can only index 8 MSI registers. MSIIR1 uses different bits
definition than MSIIR. This patch adds ibs_shift and srs_shift to
indicate the bits definition of the MSIIR and MSIIR1, so the same
code can handle the MSIIR and MSIIR1 simultaneously.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
arch/powerpc/sysdev/fsl_msi.c | 62 ++++++++++++++++++++++++++++++++++---------
arch/powerpc/sysdev/fsl_msi.h | 4 ++-
2 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index ab02db3..34510b7 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -28,6 +28,18 @@
#include "fsl_msi.h"
#include "fsl_pci.h"
+#define MSIIR_OFFSET_MASK 0xfffff
+#define MSIIR_IBS_SHIFT 0
+#define MSIIR_SRS_SHIFT 5
+#define MSIIR1_IBS_SHIFT 4
+#define MSIIR1_SRS_SHIFT 0
+#define MSI_SRS_MASK 0xf
+#define MSI_IBS_MASK 0x1f
+
+#define msi_hwirq(msi, msir_index, intr_index) \
+ ((msir_index) << (msi)->srs_shift | \
+ ((intr_index) << (msi)->ibs_shift))
+
static LIST_HEAD(msi_head);
struct fsl_msi_feature {
@@ -80,18 +92,19 @@ static const struct irq_domain_ops fsl_msi_host_ops = {
static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
- int rc;
+ int rc, hwirq;
rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
msi_data->irqhost->of_node);
if (rc)
return rc;
- rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
- if (rc < 0) {
- msi_bitmap_free(&msi_data->bitmap);
- return rc;
- }
+ /*
+ * Reserve all the hwirqs
+ * The available hwirqs will be released in fsl_msi_setup_hwirq()
+ */
+ for (hwirq = 0; hwirq < NR_MSI_IRQS; hwirq++)
+ msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
return 0;
}
@@ -144,8 +157,9 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
msg->data = hwirq;
- pr_debug("%s: allocated srs: %d, ibs: %d\n",
- __func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
+ pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
+ (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
+ (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
}
static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
@@ -285,8 +299,8 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
intr_index = ffs(msir_value) - 1;
cascade_irq = irq_linear_revmap(msi_data->irqhost,
- msir_index * IRQS_PER_MSI_REG +
- intr_index + have_shift);
+ msi_hwirq(msi_data, msir_index,
+ intr_index + have_shift));
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
have_shift += intr_index + 1;
@@ -339,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
int offset, int irq_index)
{
struct fsl_msi_cascade_data *cascade_data = NULL;
- int virt_msir;
+ int virt_msir, i;
virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
if (virt_msir == NO_IRQ) {
@@ -360,6 +374,11 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
irq_set_handler_data(virt_msir, cascade_data);
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
+ /* Release the hwirqs corresponding to this MSI register */
+ for (i = 0; i < IRQS_PER_MSI_REG; i++)
+ msi_bitmap_free_hwirqs(&msi->bitmap,
+ msi_hwirq(msi, offset, i), 1);
+
return 0;
}
@@ -368,7 +387,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
{
const struct of_device_id *match;
struct fsl_msi *msi;
- struct resource res;
+ struct resource res, msiir;
int err, i, j, irq_index, count;
int rc;
const u32 *p;
@@ -421,10 +440,29 @@ static int fsl_of_msi_probe(struct platform_device *dev)
}
msi->msiir_offset =
features->msiir_offset + (res.start & 0xfffff);
+
+ /*
+ * First read the MSIIR/MSIIR1 offset from dts
+ * If failure use the hardcode MSIIR offset
+ */
+ if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
+ msi->msiir_offset = features->msiir_offset +
+ (res.start & MSIIR_OFFSET_MASK);
+ else
+ msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
}
msi->feature = features->fsl_pic_ip;
+ if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
+ msi->srs_shift = MSIIR1_SRS_SHIFT;
+ msi->ibs_shift = MSIIR1_IBS_SHIFT;
+
+ } else {
+ msi->srs_shift = MSIIR_SRS_SHIFT;
+ msi->ibs_shift = MSIIR_IBS_SHIFT;
+ }
+
/*
* Remember the phandle, so that we can match with any PCI nodes
* that have an "fsl,msi" property.
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index 8225f86..43a9d99 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -16,7 +16,7 @@
#include <linux/of.h>
#include <asm/msi_bitmap.h>
-#define NR_MSI_REG 8
+#define NR_MSI_REG 16
#define IRQS_PER_MSI_REG 32
#define NR_MSI_IRQS (NR_MSI_REG * IRQS_PER_MSI_REG)
@@ -31,6 +31,8 @@ struct fsl_msi {
unsigned long cascade_irq;
u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
+ u32 ibs_shift; /* Shift of interrupt bit select */
+ u32 srs_shift; /* Shift of the shared interrupt register select */
void __iomem *msi_regs;
u32 feature;
int msi_virqs[NR_MSI_REG];
--
1.8.1.2
^ permalink raw reply related
* [PATCH 1/5] powerpc/dts: add MPIC v4.3 dts node
From: Minghuan Lian @ 2013-06-14 7:15 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Minghuan Lian, Zang Roy-R61911
For the latest platform T4 and B4, MPIC controller has been updated
to v4.3. This patch adds a new file to describe the latest MPIC.
The MSI blocks number is increased to four, the registers number
of each block is increased to sixteen. MSIIR1 has been added to
access these sixteen MSI registers.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi | 153 +++++++++++++++++++++++++++
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
3 files changed, 155 insertions(+), 2 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 7399154..4c617bf 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -204,7 +204,7 @@
};
};
-/include/ "qoriq-mpic.dtsi"
+/include/ "qoriq-mpic4.3.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,b4-device-config";
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
new file mode 100644
index 0000000..e2665b8
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
@@ -0,0 +1,153 @@
+/*
+ * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <4>;
+ reg = <0x40000 0x40000>;
+ compatible = "fsl,mpic";
+ device_type = "open-pic";
+ clock-frequency = <0x0>;
+};
+
+timer@41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x100 0x41300 4>;
+ interrupts = <0 0 3 0
+ 1 0 3 0
+ 2 0 3 0
+ 3 0 3 0>;
+};
+
+msi0: msi@41600 {
+ compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
+ reg = <0x41600 0x200 0x44148 4>;
+ msi-available-ranges = <0 0x200>;
+ interrupts = <
+ 0xe0 0 0 0
+ 0xe1 0 0 0
+ 0xe2 0 0 0
+ 0xe3 0 0 0
+ 0xe4 0 0 0
+ 0xe5 0 0 0
+ 0xe6 0 0 0
+ 0xe7 0 0 0
+ 0x100 0 0 0
+ 0x101 0 0 0
+ 0x102 0 0 0
+ 0x103 0 0 0
+ 0x104 0 0 0
+ 0x105 0 0 0
+ 0x106 0 0 0
+ 0x107 0 0 0>;
+};
+
+msi1: msi@41800 {
+ compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
+ reg = <0x41800 0x200 0x45148 4>;
+ msi-available-ranges = <0 0x200>;
+ interrupts = <
+ 0xe8 0 0 0
+ 0xe9 0 0 0
+ 0xea 0 0 0
+ 0xeb 0 0 0
+ 0xec 0 0 0
+ 0xed 0 0 0
+ 0xee 0 0 0
+ 0xef 0 0 0
+ 0x108 0 0 0
+ 0x109 0 0 0
+ 0x10a 0 0 0
+ 0x10b 0 0 0
+ 0x10c 0 0 0
+ 0x10d 0 0 0
+ 0x10e 0 0 0
+ 0x10f 0 0 0>;
+};
+
+msi2: msi@41a00 {
+ compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
+ reg = <0x41a00 0x200 0x46148 4>;
+ msi-available-ranges = <0 0x200>;
+ interrupts = <
+ 0xf0 0 0 0
+ 0xf1 0 0 0
+ 0xf2 0 0 0
+ 0xf3 0 0 0
+ 0xf4 0 0 0
+ 0xf5 0 0 0
+ 0xf6 0 0 0
+ 0xf7 0 0 0
+ 0x110 0 0 0
+ 0x111 0 0 0
+ 0x112 0 0 0
+ 0x113 0 0 0
+ 0x114 0 0 0
+ 0x115 0 0 0
+ 0x116 0 0 0
+ 0x117 0 0 0>;
+};
+
+msi3: msi@41c00 {
+ compatible = "fsl,mpic-msi", "fsl,mpic-msi-v4.3";
+ reg = <0x41c00 0x200 0x47148 4>;
+ msi-available-ranges = <0 0x200>;
+ interrupts = <
+ 0xf8 0 0 0
+ 0xf9 0 0 0
+ 0xfa 0 0 0
+ 0xfb 0 0 0
+ 0xfc 0 0 0
+ 0xfd 0 0 0
+ 0xfe 0 0 0
+ 0xff 0 0 0
+ 0x118 0 0 0
+ 0x119 0 0 0
+ 0x11a 0 0 0
+ 0x11b 0 0 0
+ 0x11c 0 0 0
+ 0x11d 0 0 0
+ 0x11e 0 0 0
+ 0x11f 0 0 0>;
+};
+
+timer@42100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x42100 0x100 0x42300 4>;
+ interrupts = <4 0 3 0
+ 5 0 3 0
+ 6 0 3 0
+ 7 0 3 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index bd611a9..510afa3 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -358,7 +358,7 @@
16 2 1 30>;
};
-/include/ "qoriq-mpic.dtsi"
+/include/ "qoriq-mpic4.3.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
--
1.8.1.2
^ permalink raw reply related
* [Trivial PATCH 12/33] macintosh: Convert use of typedef ctl_table to struct ctl_table
From: Joe Perches @ 2013-06-14 2:37 UTC (permalink / raw)
To: Jiri Kosina; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1371177118.git.joe@perches.com>
This typedef is unnecessary and should just be removed.
Signed-off-by: Joe Perches <joe@perches.com>
---
drivers/macintosh/mac_hid.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/macintosh/mac_hid.c b/drivers/macintosh/mac_hid.c
index 6a82388..80d30e8 100644
--- a/drivers/macintosh/mac_hid.c
+++ b/drivers/macintosh/mac_hid.c
@@ -181,7 +181,7 @@ static void mac_hid_stop_emulation(void)
mac_hid_destroy_emumouse();
}
-static int mac_hid_toggle_emumouse(ctl_table *table, int write,
+static int mac_hid_toggle_emumouse(struct ctl_table *table, int write,
void __user *buffer, size_t *lenp,
loff_t *ppos)
{
@@ -214,7 +214,7 @@ static int mac_hid_toggle_emumouse(ctl_table *table, int write,
}
/* file(s) in /proc/sys/dev/mac_hid */
-static ctl_table mac_hid_files[] = {
+static struct ctl_table mac_hid_files[] = {
{
.procname = "mouse_button_emulation",
.data = &mouse_emulate_buttons,
@@ -240,7 +240,7 @@ static ctl_table mac_hid_files[] = {
};
/* dir in /proc/sys/dev */
-static ctl_table mac_hid_dir[] = {
+static struct ctl_table mac_hid_dir[] = {
{
.procname = "mac_hid",
.maxlen = 0,
@@ -251,7 +251,7 @@ static ctl_table mac_hid_dir[] = {
};
/* /proc/sys/dev itself, in case that is not there yet */
-static ctl_table mac_hid_root_dir[] = {
+static struct ctl_table mac_hid_root_dir[] = {
{
.procname = "dev",
.maxlen = 0,
--
1.8.1.2.459.gbcd45b4.dirty
^ permalink raw reply related
* [Trivial PATCH 05/33] powerpc: idle: Convert use of typedef ctl_table to struct ctl_table
From: Joe Perches @ 2013-06-14 2:37 UTC (permalink / raw)
To: Jiri Kosina; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <cover.1371177118.git.joe@perches.com>
This typedef is unnecessary and should just be removed.
Signed-off-by: Joe Perches <joe@perches.com>
---
arch/powerpc/kernel/idle.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 939ea7e..d7216c9 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -85,7 +85,7 @@ int powersave_nap;
/*
* Register the sysctl to set/clear powersave_nap.
*/
-static ctl_table powersave_nap_ctl_table[]={
+static struct ctl_table powersave_nap_ctl_table[] = {
{
.procname = "powersave-nap",
.data = &powersave_nap,
@@ -95,7 +95,7 @@ static ctl_table powersave_nap_ctl_table[]={
},
{}
};
-static ctl_table powersave_nap_sysctl_root[] = {
+static struct ctl_table powersave_nap_sysctl_root[] = {
{
.procname = "kernel",
.mode = 0555,
--
1.8.1.2.459.gbcd45b4.dirty
^ permalink raw reply related
* [Trivial PATCH 00/33] Remove uses of typedef ctl_table
From: Joe Perches @ 2013-06-14 2:37 UTC (permalink / raw)
To: Jiri Kosina
Cc: linux-mips, linux-nfs, linux-ia64, keyrings, linux-scsi,
linux-s390, linux-rdma, netdev, linux-kernel, codalist,
linux-raid, linux-ntfs-dev, linux-security-module, linux-cachefs,
ocfs2-devel, linux-fsdevel, openipmi-developer, xfs, linuxppc-dev,
linux-mm, linux-arm-kernel
It's clearer to use struct ctl_table instead
Joe Perches (33):
arm: kernel: isa: Convert use of typedef ctl_table to struct ctl_table
frv: Convert use of typedef ctl_table to struct ctl_table
ia64: crash: Convert use of typedef ctl_table to struct ctl_table
mips: lasat: sysctl: Convert use of typedef ctl_table to struct ctl_table
powerpc: idle: Convert use of typedef ctl_table to struct ctl_table
s390: Convert use of typedef ctl_table to struct ctl_table
tile: proc: Convert use of typedef ctl_table to struct ctl_table
x86: vdso: Convert use of typedef ctl_table to struct ctl_table
cdrom: Convert use of typedef ctl_table to struct ctl_table
char: Convert use of typedef ctl_table to struct ctl_table
infiniband: Convert use of typedef ctl_table to struct ctl_table
macintosh: Convert use of typedef ctl_table to struct ctl_table
md: Convert use of typedef ctl_table to struct ctl_table
sgi: xpc: Convert use of typedef ctl_table to struct ctl_table
parport: Convert use of typedef ctl_table to struct ctl_table
scsi_sysctl: Convert use of typedef ctl_table to struct ctl_table
coda: Convert use of typedef ctl_table to struct ctl_table
fscache: Convert use of typedef ctl_table to struct ctl_table
lockd: Convert use of typedef ctl_table to struct ctl_table
nfs: Convert use of typedef ctl_table to struct ctl_table
inotify: Convert use of typedef ctl_table to struct ctl_table
ntfs: Convert use of typedef ctl_table to struct ctl_table
ocfs2: Convert use of typedef ctl_table to struct ctl_table
quota: Convert use of typedef ctl_table to struct ctl_table
xfs: Convert use of typedef ctl_table to struct ctl_table
fs: Convert use of typedef ctl_table to struct ctl_table
key: Convert use of typedef ctl_table to struct ctl_table
ipv6: Convert use of typedef ctl_table to struct ctl_table
ndisc: Convert use of typedef ctl_table to struct ctl_table
ipc: Convert use of typedef ctl_table to struct ctl_table
sysctl: Convert use of typedef ctl_table to struct ctl_table
mm: Convert use of typedef ctl_table to struct ctl_table
security: keys: Convert use of typedef ctl_table to struct ctl_table
arch/arm/kernel/isa.c | 6 ++--
arch/frv/kernel/pm.c | 8 +++---
arch/frv/kernel/sysctl.c | 4 +--
arch/ia64/kernel/crash.c | 4 +--
arch/ia64/kernel/perfmon.c | 6 ++--
arch/mips/lasat/sysctl.c | 14 ++++-----
arch/powerpc/kernel/idle.c | 4 +--
arch/s390/appldata/appldata_base.c | 16 +++++------
arch/s390/kernel/debug.c | 4 +--
arch/s390/mm/cmm.c | 6 ++--
arch/tile/kernel/proc.c | 4 +--
arch/x86/vdso/vdso32-setup.c | 4 +--
drivers/cdrom/cdrom.c | 10 +++----
drivers/char/hpet.c | 6 ++--
drivers/char/ipmi/ipmi_poweroff.c | 6 ++--
drivers/char/random.c | 8 +++---
drivers/char/rtc.c | 6 ++--
drivers/infiniband/core/ucma.c | 2 +-
drivers/macintosh/mac_hid.c | 8 +++---
drivers/md/md.c | 6 ++--
drivers/misc/sgi-xp/xpc_main.c | 6 ++--
drivers/parport/procfs.c | 58 +++++++++++++++++++-------------------
drivers/scsi/scsi_sysctl.c | 6 ++--
fs/coda/sysctl.c | 4 +--
fs/dcache.c | 2 +-
fs/drop_caches.c | 2 +-
fs/eventpoll.c | 2 +-
fs/file_table.c | 4 +--
fs/fscache/main.c | 4 +--
fs/inode.c | 2 +-
fs/lockd/svc.c | 6 ++--
fs/nfs/nfs4sysctl.c | 6 ++--
fs/nfs/sysctl.c | 6 ++--
fs/notify/inotify/inotify_user.c | 2 +-
fs/ntfs/sysctl.c | 4 +--
fs/ocfs2/stackglue.c | 8 +++---
fs/quota/dquot.c | 6 ++--
fs/xfs/xfs_sysctl.c | 26 ++++++++---------
include/linux/key.h | 2 +-
include/net/ipv6.h | 4 +--
include/net/ndisc.h | 2 +-
ipc/ipc_sysctl.c | 14 ++++-----
ipc/mq_sysctl.c | 10 +++----
kernel/sysctl.c | 2 +-
kernel/utsname_sysctl.c | 6 ++--
mm/page-writeback.c | 2 +-
mm/page_alloc.c | 15 +++++-----
security/keys/sysctl.c | 2 +-
48 files changed, 174 insertions(+), 171 deletions(-)
--
1.8.1.2.459.gbcd45b4.dirty
^ permalink raw reply
* Re: [PATCH 1/2] powerpc: add Book E support to 64-bit hibernation
From: Scott Wood @ 2013-06-13 16:51 UTC (permalink / raw)
To: Wang Dongsheng-B40534
Cc: Wood Scott-B07421, anton@enomsg.org, johannes@sipsolutions.net,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <ABB05CD9C9F68C46A5CEDC7F15439259F74985@039-SN2MPN1-021.039d.mgd.msft.net>
On 06/13/2013 04:55:43 AM, Wang Dongsheng-B40534 wrote:
> > > +#else
> > > + /* Save SPRGs */
> > > + RESTORE_SPRG(0)
> > > + RESTORE_SPRG(1)
> > > + RESTORE_SPRG(2)
> > > + RESTORE_SPRG(3)
> > > + RESTORE_SPRG(4)
> > > + RESTORE_SPRG(5)
> > > + RESTORE_SPRG(6)
> > > + RESTORE_SPRG(7)
> >
> > Why do we need this on book3e and not on book3s?
> >
> Book3e: SPRG1 used save paca, SPRG2 be defined =20
> SPRN_SPRG_TLB_EXFRAME,...
> I think those register should be save, even now some SPRG register =20
> not be use.
Are those expected/allowed to change as a result of the restore?
-Scott=
^ permalink raw reply
* Re: [BUG] PCI related panic on powerpc based board with 3.10-rcX
From: Scott Wood @ 2013-06-13 16:49 UTC (permalink / raw)
To: Rojhalat Ibrahim; +Cc: linuxppc-dev, linux-kernel, Michael Guntsche
In-Reply-To: <7706620.VNI3PE9pqO@pcimr>
On 06/13/2013 02:21:24 AM, Rojhalat Ibrahim wrote:
> On Wednesday 12 June 2013 16:50:26 Scott Wood wrote:
> > On 06/12/2013 03:19:30 AM, Rojhalat Ibrahim wrote:
> > > On Tuesday 11 June 2013 12:28:59 Scott Wood wrote:
> > > > Yes, I figured it was non-PCIe because the code change that you =20
> said
> > > > helped was on the non-PCIe branch of the if/else. Generally =20
> it's
> > >
> > > good
> > >
> > > > to explicitly mention the chip you're using, though.
> > > >
> > > > fsl_setup_indirect_pci should be renamed to =20
> fsl_setup_indirect_pcie.
> > > > Your patch above should be applied, and fsl_setup_indirect_pcie
> > >
> > > should
> > >
> > > > be moved into the booke/86xx ifdef to avoid an unused function
> > >
> > > warning.
> > >
> > > > -Scott
> > >
> > > How about this patch? It uses setup_indirect_pci for the PCI case =20
> in
> > > mpc83xx_add_bridge. Additionally it adds a check in
> > > fsl_setup_indirect_pci
> > > to only use the modified read function in case of PCIe.
> >
> > If we're adding the check to fsl_setup_indirect_pci, there's no =20
> need to
> > change the 83xx call back to setup_indirect_pci. I see that 85xx is
> > also callirng fsl_setup_indirect_pci for both; it'd be good to be
> > consistent.
> >
> > In any case, can you send a proper patch with a signoff and commit
> > message?
> >
> > -Scott
>=20
> Where is it called for 85xx? As far as I can tell =20
> fsl_setup_indirect_pci is
> called exactly once in fsl_add_bridge and nowhere else (after =20
> applying the
> proposed patch).
fsl_add_bridge() is where it's called for 85xx.
> For 83xx the decision between PCI and PCIe has already been made at
> the point where the setup function is called. So IMO it doesn't make =20
> sense
> to call fsl_setup_indirect_pci and do the check again. Moreover PCIe =20
> on 83xx
> uses a completely different set of functions.
My concern is consistency. E.g. if 85xx is using =20
fsl_setup_indirect_pci for both, but 83xx isn't, then a developer using =20
83xx could end up breaking 85xx by introducing another PCIe dependency =20
in fsl_setup_indirect_pci. Or an 85xx developer could put something =20
non-PCIe-related in fsl_setup_indirect_pci that 83xx would benefit from.
Alternatively, you could call it fsl_setup_indirect_pcie, and move the =20
PCIe check into fsl_add_bridge().
-Scott=
^ permalink raw reply
* Re: [PATCH 15/27] powerpc/eeh: I/O chip EEH state retrieval
From: Gavin Shan @ 2013-06-13 5:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1371098537.5555.0.camel@pasglop>
On Thu, Jun 13, 2013 at 02:42:17PM +1000, Benjamin Herrenschmidt wrote:
>On Thu, 2013-06-13 at 12:26 +0800, Gavin Shan wrote:
>> So the answer is we can do it by makeing the assumption that f/w won't
>> return valid delay and we're going to use default value (1 second) for
>> guest on powernv or phyp, or we keep the delay here.
>
>Ok, at the very least then change the name to "unavailable_delay" or
>something explicit like that then :-)
>
Ok.
>BTW. I've already applied patches 1 and 2 to my tree, you don't have to
>resend those. They'll show up today or tomorrow when I push my next
>branch out.
>
Ok. Thanks, Ben.
Thanks,
Gavin
^ permalink raw reply
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