* [PATCH 3/8] powerpc/perf: Freeze PMC5/6 if we're not using them
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
On Power8 we can freeze PMC5 and 6 if we're not using them. Normally they
run all the time.
As noticed by Anshuman, we should unfreeze them when we disable the PMU
as there are legacy tools which expect them to run all the time.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/perf/core-book3s.c | 5 +++--
arch/powerpc/perf/power8-pmu.c | 4 ++++
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4a9e408..362142b 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -626,6 +626,7 @@
#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
+#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 1ab3068..3d566ee 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
#define MMCR0_FCHV 0
#define MMCR0_PMCjCE MMCR0_PMCnCE
+#define MMCR0_FC56 0
#define MMCR0_PMAO 0
#define SPRN_MMCRA SPRN_MMCR2
@@ -870,11 +871,11 @@ static void power_pmu_disable(struct pmu *pmu)
}
/*
- * Set the 'freeze counters' bit, clear PMAO.
+ * Set the 'freeze counters' bit, clear PMAO/FC56.
*/
val = mfspr(SPRN_MMCR0);
val |= MMCR0_FC;
- val &= ~MMCR0_PMAO;
+ val &= ~(MMCR0_PMAO | MMCR0_FC56);
/*
* The barrier is to make sure the mtspr has been
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 84cdc6d..d59f5b2 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -391,6 +391,10 @@ static int power8_compute_mmcr(u64 event[], int n_ev,
if (pmc_inuse & 0x7c)
mmcr[0] |= MMCR0_PMCjCE;
+ /* If we're not using PMC 5 or 6, freeze them */
+ if (!(pmc_inuse & 0x60))
+ mmcr[0] |= MMCR0_FC56;
+
mmcr[1] = mmcr1;
mmcr[2] = mmcra;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 4/8] powerpc/perf: Use existing out label in power_pmu_enable()
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
In power_pmu_enable() we can use the existing out label to reduce the
number of return paths.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/perf/core-book3s.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 3d566ee..af4b4b1 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -919,12 +919,13 @@ static void power_pmu_enable(struct pmu *pmu)
if (!ppmu)
return;
+
local_irq_save(flags);
+
cpuhw = &__get_cpu_var(cpu_hw_events);
- if (!cpuhw->disabled) {
- local_irq_restore(flags);
- return;
- }
+ if (!cpuhw->disabled)
+ goto out;
+
cpuhw->disabled = 0;
/*
--
1.7.10.4
^ permalink raw reply related
* [PATCH 5/8] powerpc/perf: Don't enable if we have zero events
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
In power_pmu_enable() we still enable the PMU even if we have zero
events. This should have no effect but doesn't make much sense. Instead
just return after telling the hypervisor that we are not using the PMCs.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/perf/core-book3s.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index af4b4b1..d3ee2e5 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -926,6 +926,11 @@ static void power_pmu_enable(struct pmu *pmu)
if (!cpuhw->disabled)
goto out;
+ if (cpuhw->n_events == 0) {
+ ppc_set_pmu_inuse(0);
+ goto out;
+ }
+
cpuhw->disabled = 0;
/*
@@ -937,8 +942,6 @@ static void power_pmu_enable(struct pmu *pmu)
if (!cpuhw->n_added) {
mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
- if (cpuhw->n_events == 0)
- ppc_set_pmu_inuse(0);
goto out_enable;
}
--
1.7.10.4
^ permalink raw reply related
* [PATCH 6/8] powerpc/perf: Drop MMCRA from thread_struct
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
In commit 59affcd "Context switch more PMU related SPRs" I added more
PMU SPRs to thread_struct, later modified in commit b11ae95. To add
insult to injury it turns out we don't need to switch MMCRA as it's
only user readable, and the value is recomputed by the PMU code.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/include/asm/processor.h | 1 -
arch/powerpc/kernel/asm-offsets.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 14a6583..48af5d7 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -289,7 +289,6 @@ struct thread_struct {
unsigned long sier;
unsigned long mmcr0;
unsigned long mmcr2;
- unsigned long mmcra;
#endif
};
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 6f16ffa..2f066ef 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -132,7 +132,6 @@ int main(void)
DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));
DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));
DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));
- DEFINE(THREAD_MMCRA, offsetof(struct thread_struct, mmcra));
#endif
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
--
1.7.10.4
^ permalink raw reply related
* [PATCH 7/8] powerpc/perf: Core EBB support for 64-bit book3s
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
Add support for EBB (Event Based Branches) on 64-bit book3s. See the
included documentation for more details.
EBBs are a feature which allows the hardware to branch directly to a
specified user space address when a PMU event overflows. This can be
used by programs for self-monitoring with no kernel involvement in the
inner loop.
Most of the logic is in the generic book3s code, primarily to avoid a
proliferation of PMU callbacks.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
Documentation/powerpc/00-INDEX | 2 +
Documentation/powerpc/pmu-ebb.txt | 122 +++++++++++++++++++
arch/powerpc/include/asm/perf_event_server.h | 6 +
arch/powerpc/include/asm/processor.h | 3 +-
arch/powerpc/include/asm/reg.h | 8 ++
arch/powerpc/include/asm/switch_to.h | 14 +++
arch/powerpc/kernel/process.c | 4 +
arch/powerpc/perf/core-book3s.c | 161 +++++++++++++++++++++++---
8 files changed, 306 insertions(+), 14 deletions(-)
create mode 100644 Documentation/powerpc/pmu-ebb.txt
diff --git a/Documentation/powerpc/00-INDEX b/Documentation/powerpc/00-INDEX
index dd9e928..05026ce 100644
--- a/Documentation/powerpc/00-INDEX
+++ b/Documentation/powerpc/00-INDEX
@@ -14,6 +14,8 @@ hvcs.txt
- IBM "Hypervisor Virtual Console Server" Installation Guide
mpc52xx.txt
- Linux 2.6.x on MPC52xx family
+pmu-ebb.txt
+ - Description of the API for using the PMU with Event Based Branches.
qe_firmware.txt
- describes the layout of firmware binaries for the Freescale QUICC
Engine and the code that parses and uploads the microcode therein.
diff --git a/Documentation/powerpc/pmu-ebb.txt b/Documentation/powerpc/pmu-ebb.txt
new file mode 100644
index 0000000..65b6989
--- /dev/null
+++ b/Documentation/powerpc/pmu-ebb.txt
@@ -0,0 +1,122 @@
+PMU Event Based Branches
+========================
+
+Event Based Branches (EBBs) are a feature which allows the hardware to
+branch directly to a specified user space address when certain events occur.
+
+The full specification is available in Power ISA v2.07:
+
+ https://www.power.org/documentation/power-isa-version-2-07/
+
+One type of event for which EBBs can be configured is PMU exceptions. This
+document describes the API for configuring the Power PMU to generate EBBs,
+using the Linux perf_events API.
+
+
+Terminology
+-----------
+
+Throughout this document we will refer to an "EBB event" or "EBB events". This
+just refers to a struct perf_event which has set the "EBB" flag in its
+attr.config. All events which can be configured on the hardware PMU are
+possible "EBB events".
+
+
+Background
+----------
+
+When a PMU EBB occurs it is delivered to the currently running process. As such
+EBBs can only sensibly be used by programs for self-monitoring.
+
+It is a feature of the perf_events API that events can be created on other
+processes, subject to standard permission checks. This is also true of EBB
+events, however unless the target process enables EBBs (via mtspr(BESCR)) no
+EBBs will ever be delivered.
+
+This makes it possible for a process to enable EBBs for itself, but not
+actually configure any events. At a later time another process can come along
+and attach an EBB event to the process, which will then cause EBBs to be
+delivered to the first process. It's not clear if this is actually useful.
+
+
+When the PMU is configured for EBBs, all PMU interrupts are delivered to the
+user process. This means once an EBB event is scheduled on the PMU, no non-EBB
+events can be configured. This means that EBB events can not be run
+concurrently with regular 'perf' commands.
+
+It is however safe to run 'perf' commands on a process which is using EBBs. In
+general the EBB event will take priority, though it depends on the exact
+options used on the perf_event_open() and the timing.
+
+
+Creating an EBB event
+---------------------
+
+To request that an event is counted using EBB, the event code should have bit
+63 set.
+
+EBB events must be created with a particular, and restrictive, set of
+attributes - this is so that they interoperate correctly with the rest of the
+perf_events subsystem.
+
+An EBB event must be created with the "pinned" and "exclusive" attributes set.
+Note that if you are creating a group of EBB events, only the leader can have
+these attributes set.
+
+An EBB event must NOT set any of the "inherit", "sample_period", "freq" or
+"enable_on_exec" attributes.
+
+An EBB event must be attached to a task. This is specified to perf_event_open()
+by passing a pid value, typically 0 indicating the current task.
+
+All events in a group must agree on whether they want EBB. That is all events
+must request EBB, or none may request EBB.
+
+
+Enabling an EBB event
+---------------------
+
+Once an EBB event has been successfully opened, it must be enabled with the
+perf_events API. This can be achieved either via the ioctl() interface, or the
+prctl() interface.
+
+However, due to the design of the perf_events API, enabling an event does not
+guarantee that it has been scheduled on the PMU. To ensure that the EBB event
+has been scheduled on the PMU, you must perform a read() on the event. If the
+read() returns EOF, then the event has not been scheduled and EBBs are not
+enabled.
+
+
+Reading an EBB event
+--------------------
+
+It is possible to read() from an EBB event. However the results are
+meaningless. Because interrupts are being delivered to the user process the
+kernel is not able to count the event, and so will return a junk value.
+
+
+Closing an EBB event
+--------------------
+
+When an EBB event is finished with, you can close it using close() as for any
+regular event. If this is the last EBB event the PMU will be deconfigured and
+no further PMU EBBs will be delivered.
+
+
+EBB Handler
+-----------
+
+The EBB handler is just regular userspace code, however it must be written in
+the style of an interrupt handler. When the handler is entered all registers
+are live (possibly) and so must be saved somehow before the handler can invoke
+other code.
+
+It's up to the program how to handle this. For C programs a relatively simple
+option is to create an interrupt frame on the stack and save registers there.
+
+Fork
+----
+
+EBB events are not inherited across fork. If the child process wishes to use
+EBBs it should open a new event for itself. Similarly the EBB state in
+BESCR/EBBHR/EBBRR is cleared across fork().
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index f265049..2dd7bfc 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -60,6 +60,7 @@ struct power_pmu {
#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
#define PPMU_HAS_SIER 0x00000040 /* Has SIER */
#define PPMU_BHRB 0x00000080 /* has BHRB feature enabled */
+#define PPMU_EBB 0x00000100 /* supports event based branch */
/*
* Values for flags to get_alternatives()
@@ -68,6 +69,11 @@ struct power_pmu {
#define PPMU_LIMITED_PMC_REQD 2 /* have to put this on a limited PMC */
#define PPMU_ONLY_COUNT_RUN 4 /* only counting in run state */
+/*
+ * We use the event config bit 63 as a flag to request EBB.
+ */
+#define EVENT_CONFIG_EBB_SHIFT 63
+
extern int register_power_pmu(struct power_pmu *);
struct pt_regs;
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 48af5d7..f9a4cdc 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -287,8 +287,9 @@ struct thread_struct {
unsigned long siar;
unsigned long sdar;
unsigned long sier;
- unsigned long mmcr0;
unsigned long mmcr2;
+ unsigned mmcr0;
+ unsigned used_ebb;
#endif
};
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 362142b..5d7d9c2 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -621,6 +621,9 @@
#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
+#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
+#define MMCR0_PMCC 0x000c0000UL /* PMC control */
+#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
@@ -674,6 +677,11 @@
#define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */
#define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */
+/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
+#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
+#define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
+#define SIER_USER_MASK 0x7fffffUL
+
#define SPRN_PA6T_MMCR0 795
#define PA6T_MMCR0_EN0 0x0000000000000001UL
#define PA6T_MMCR0_EN1 0x0000000000000002UL
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 200d763..49a13e0 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -67,4 +67,18 @@ static inline void flush_spe_to_thread(struct task_struct *t)
}
#endif
+static inline void clear_task_ebb(struct task_struct *t)
+{
+#ifdef CONFIG_PPC_BOOK3S_64
+ /* EBB perf events are not inherited, so clear all EBB state. */
+ t->thread.bescr = 0;
+ t->thread.mmcr2 = 0;
+ t->thread.mmcr0 = 0;
+ t->thread.siar = 0;
+ t->thread.sdar = 0;
+ t->thread.sier = 0;
+ t->thread.used_ebb = 0;
+#endif
+}
+
#endif /* _ASM_POWERPC_SWITCH_TO_H */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 076d124..c517dbe 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -916,7 +916,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
flush_altivec_to_thread(src);
flush_vsx_to_thread(src);
flush_spe_to_thread(src);
+
*dst = *src;
+
+ clear_task_ebb(dst);
+
return 0;
}
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index d3ee2e5..c6bbbf9 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -77,6 +77,9 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
#define MMCR0_PMCjCE MMCR0_PMCnCE
#define MMCR0_FC56 0
#define MMCR0_PMAO 0
+#define MMCR0_EBE 0
+#define MMCR0_PMCC 0
+#define MMCR0_PMCC_U6 0
#define SPRN_MMCRA SPRN_MMCR2
#define MMCRA_SAMPLE_ENABLE 0
@@ -104,6 +107,15 @@ static inline int siar_valid(struct pt_regs *regs)
return 1;
}
+static bool is_ebb_event(struct perf_event *event) { return false; }
+static int ebb_event_check(struct perf_event *event) { return 0; }
+static void ebb_event_add(struct perf_event *event) { }
+static void ebb_switch_out(unsigned long mmcr0) { }
+static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
+{
+ return mmcr0;
+}
+
static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
void power_pmu_flush_branch_stack(void) {}
@@ -464,6 +476,89 @@ void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
return;
}
+static bool is_ebb_event(struct perf_event *event)
+{
+ /*
+ * This could be a per-PMU callback, but we'd rather avoid the cost. We
+ * check that the PMU supports EBB, meaning those that don't can still
+ * use bit 63 of the event code for something else if they wish.
+ */
+ return (ppmu->flags & PPMU_EBB) &&
+ ((event->attr.config >> EVENT_CONFIG_EBB_SHIFT) & 1);
+}
+
+static int ebb_event_check(struct perf_event *event)
+{
+ struct perf_event *leader = event->group_leader;
+
+ /* Event and group leader must agree on EBB */
+ if (is_ebb_event(leader) != is_ebb_event(event))
+ return -EINVAL;
+
+ if (is_ebb_event(event)) {
+ if (!(event->attach_state & PERF_ATTACH_TASK))
+ return -EINVAL;
+
+ if (!leader->attr.pinned || !leader->attr.exclusive)
+ return -EINVAL;
+
+ if (event->attr.inherit || event->attr.sample_period ||
+ event->attr.enable_on_exec || event->attr.freq)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ebb_event_add(struct perf_event *event)
+{
+ if (!is_ebb_event(event) || current->thread.used_ebb)
+ return;
+
+ /*
+ * IFF this is the first time we've added an EBB event, set
+ * PMXE in the user MMCR0 so we can detect when it's cleared by
+ * userspace. We need this so that we can context switch while
+ * userspace is in the EBB handler (where PMXE is 0).
+ */
+ current->thread.used_ebb = 1;
+ current->thread.mmcr0 |= MMCR0_PMXE;
+}
+
+static void ebb_switch_out(unsigned long mmcr0)
+{
+ if (!(mmcr0 & MMCR0_EBE))
+ return;
+
+ current->thread.siar = mfspr(SPRN_SIAR);
+ current->thread.sier = mfspr(SPRN_SIER);
+ current->thread.sdar = mfspr(SPRN_SDAR);
+ current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
+ current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
+}
+
+static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
+{
+ if (!ebb)
+ goto out;
+
+ /* Enable EBB and read/write to all 6 PMCs for userspace */
+ mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6;
+
+ /* Add any bits from the user reg, FC or PMAO */
+ mmcr0 |= current->thread.mmcr0;
+
+ /* Be careful not to set PMXE if userspace had it cleared */
+ if (!(current->thread.mmcr0 & MMCR0_PMXE))
+ mmcr0 &= ~MMCR0_PMXE;
+
+ mtspr(SPRN_SIAR, current->thread.siar);
+ mtspr(SPRN_SIER, current->thread.sier);
+ mtspr(SPRN_SDAR, current->thread.sdar);
+ mtspr(SPRN_MMCR2, current->thread.mmcr2);
+out:
+ return mmcr0;
+}
#endif /* CONFIG_PPC64 */
static void perf_event_interrupt(struct pt_regs *regs);
@@ -734,6 +829,13 @@ static void power_pmu_read(struct perf_event *event)
if (!event->hw.idx)
return;
+
+ if (is_ebb_event(event)) {
+ val = read_pmc(event->hw.idx);
+ local64_set(&event->hw.prev_count, val);
+ return;
+ }
+
/*
* Performance monitor interrupts come even when interrupts
* are soft-disabled, as long as interrupts are hard-enabled.
@@ -854,7 +956,7 @@ static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
static void power_pmu_disable(struct pmu *pmu)
{
struct cpu_hw_events *cpuhw;
- unsigned long flags, val;
+ unsigned long flags, mmcr0, val;
if (!ppmu)
return;
@@ -871,11 +973,11 @@ static void power_pmu_disable(struct pmu *pmu)
}
/*
- * Set the 'freeze counters' bit, clear PMAO/FC56.
+ * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56.
*/
- val = mfspr(SPRN_MMCR0);
+ val = mmcr0 = mfspr(SPRN_MMCR0);
val |= MMCR0_FC;
- val &= ~(MMCR0_PMAO | MMCR0_FC56);
+ val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56);
/*
* The barrier is to make sure the mtspr has been
@@ -896,7 +998,10 @@ static void power_pmu_disable(struct pmu *pmu)
cpuhw->disabled = 1;
cpuhw->n_added = 0;
+
+ ebb_switch_out(mmcr0);
}
+
local_irq_restore(flags);
}
@@ -911,15 +1016,15 @@ static void power_pmu_enable(struct pmu *pmu)
struct cpu_hw_events *cpuhw;
unsigned long flags;
long i;
- unsigned long val;
+ unsigned long val, mmcr0;
s64 left;
unsigned int hwc_index[MAX_HWEVENTS];
int n_lim;
int idx;
+ bool ebb;
if (!ppmu)
return;
-
local_irq_save(flags);
cpuhw = &__get_cpu_var(cpu_hw_events);
@@ -934,6 +1039,13 @@ static void power_pmu_enable(struct pmu *pmu)
cpuhw->disabled = 0;
/*
+ * EBB requires an exclusive group and all events must have the EBB
+ * flag set, or not set, so we can just check a single event. Also we
+ * know we have at least one event.
+ */
+ ebb = is_ebb_event(cpuhw->event[0]);
+
+ /*
* If we didn't change anything, or only removed events,
* no need to recalculate MMCR* settings and reset the PMCs.
* Just reenable the PMU with the current MMCR* settings
@@ -1008,25 +1120,34 @@ static void power_pmu_enable(struct pmu *pmu)
++n_lim;
continue;
}
- val = 0;
- if (event->hw.sample_period) {
- left = local64_read(&event->hw.period_left);
- if (left < 0x80000000L)
- val = 0x80000000L - left;
+
+ if (ebb)
+ val = local64_read(&event->hw.prev_count);
+ else {
+ val = 0;
+ if (event->hw.sample_period) {
+ left = local64_read(&event->hw.period_left);
+ if (left < 0x80000000L)
+ val = 0x80000000L - left;
+ }
+ local64_set(&event->hw.prev_count, val);
}
- local64_set(&event->hw.prev_count, val);
+
event->hw.idx = idx;
if (event->hw.state & PERF_HES_STOPPED)
val = 0;
write_pmc(idx, val);
+
perf_event_update_userpage(event);
}
cpuhw->n_limited = n_lim;
cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
out_enable:
+ mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
+
mb();
- write_mmcr0(cpuhw, cpuhw->mmcr[0]);
+ write_mmcr0(cpuhw, mmcr0);
/*
* Enable instruction sampling if necessary
@@ -1124,6 +1245,8 @@ static int power_pmu_add(struct perf_event *event, int ef_flags)
event->hw.config = cpuhw->events[n0];
nocheck:
+ ebb_event_add(event);
+
++cpuhw->n_events;
++cpuhw->n_added;
@@ -1484,6 +1607,11 @@ static int power_pmu_event_init(struct perf_event *event)
}
}
+ /* Extra checks for EBB */
+ err = ebb_event_check(event);
+ if (err)
+ return err;
+
/*
* If this is in a group, check if it can go on with all the
* other hardware events in the group. We assume the event
@@ -1523,6 +1651,13 @@ static int power_pmu_event_init(struct perf_event *event)
local64_set(&event->hw.period_left, event->hw.last_period);
/*
+ * For EBB events we just context switch the PMC value, we don't do any
+ * of the sample_period logic. We use hw.prev_count for this.
+ */
+ if (is_ebb_event(event))
+ local64_set(&event->hw.prev_count, 0);
+
+ /*
* See if we need to reserve the PMU.
* If no events are currently in use, then we have to take a
* mutex to ensure that we don't race with another task doing
--
1.7.10.4
^ permalink raw reply related
* [PATCH 8/8] powerpc/perf: Add power8 EBB support
From: Michael Ellerman @ 2013-06-24 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sukadev, Paul Mackerras, khandual
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
Add logic to the power8 PMU code to support EBB. Future processors would
also be expected to implement similar constraints. At that time we could
possibly factor these out into common code.
Finally mark the power8 PMU as supporting EBB, which is the actual
enable switch which allows EBBs to be configured.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/perf/power8-pmu.c | 44 +++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index d59f5b2..c7f8ccc 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -31,9 +31,9 @@
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- * [ thresh_cmp ] [ thresh_ctl ]
- * |
- * thresh start/stop OR FAB match -*
+ * | [ thresh_cmp ] [ thresh_ctl ]
+ * | |
+ * *- EBB (Linux) thresh start/stop OR FAB match -*
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
@@ -117,6 +117,7 @@
(EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
(EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
+ (1ull << EVENT_CONFIG_EBB_SHIFT) | \
EVENT_PSEL_MASK)
/* MMCRA IFM bits - POWER8 */
@@ -140,10 +141,10 @@
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- * [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
- * | |
- * L1 I/D qualifier -* | Count of events for each PMC.
- * | p1, p2, p3, p4, p5, p6.
+ * | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1]
+ * EBB -* | |
+ * | | Count of events for each PMC.
+ * L1 I/D qualifier -* | p1, p2, p3, p4, p5, p6.
* nc - number of counters -*
*
* The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
@@ -159,6 +160,9 @@
#define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
#define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
+#define CNST_EBB_VAL(v) (((v) & 1) << 24)
+#define CNST_EBB_MASK CNST_EBB_VAL(1)
+
#define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
#define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
@@ -217,7 +221,7 @@ static inline bool event_is_fab_match(u64 event)
static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
{
- unsigned int unit, pmc, cache;
+ unsigned int unit, pmc, cache, ebb;
unsigned long mask, value;
mask = value = 0;
@@ -225,9 +229,13 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
if (event & ~EVENT_VALID_MASK)
return -1;
- pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
- unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
- cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
+ pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
+ unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
+ cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
+ ebb = (event >> EVENT_CONFIG_EBB_SHIFT) & 1;
+
+ /* Clear the EBB bit in the event, so event checks work below */
+ event &= ~(1ull << EVENT_CONFIG_EBB_SHIFT);
if (pmc) {
if (pmc > 6)
@@ -297,6 +305,18 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
}
+ if (!pmc && ebb)
+ /* EBB events must specify the PMC */
+ return -1;
+
+ /*
+ * All events must agree on EBB, either all request it or none.
+ * EBB events are pinned & exclusive, so this should never actually
+ * hit, but we leave it as a fallback in case.
+ */
+ mask |= CNST_EBB_VAL(ebb);
+ value |= CNST_EBB_MASK;
+
*maskp = mask;
*valp = value;
@@ -591,7 +611,7 @@ static struct power_pmu power8_pmu = {
.get_constraint = power8_get_constraint,
.get_alternatives = power8_get_alternatives,
.disable_pmc = power8_disable_pmc,
- .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB,
+ .flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
.n_generic = ARRAY_SIZE(power8_generic_events),
.generic_events = power8_generic_events,
.attr_groups = power8_pmu_attr_groups,
--
1.7.10.4
^ permalink raw reply related
* [PATCH] Do not update sysfs cpu registration from invalid context
From: Nathan Fontenot @ 2013-06-24 14:14 UTC (permalink / raw)
To: linuxppc-dev
The topology update code that updates the cpu node registration in sysfs
should not be called while in stop_machine(). The register/unregister
calls take a lock and may sleep.
This patch moves these calls outside of the call to stop_machine().
Signed-off-by:Nathan Fontenot <nfont@linux.vnet.ibm.com>
---
arch/powerpc/mm/numa.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
Index: powerpc/arch/powerpc/mm/numa.c
===================================================================
--- powerpc.orig/arch/powerpc/mm/numa.c 2013-06-24 06:53:31.000000000 -0500
+++ powerpc/arch/powerpc/mm/numa.c 2013-06-24 06:56:30.000000000 -0500
@@ -1433,11 +1433,9 @@
if (cpu != update->cpu)
continue;
- unregister_cpu_under_node(update->cpu, update->old_nid);
unmap_cpu_from_node(update->cpu);
map_cpu_to_node(update->cpu, update->new_nid);
vdso_getcpu_init();
- register_cpu_under_node(update->cpu, update->new_nid);
}
return 0;
@@ -1485,6 +1483,9 @@
stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
for (ud = &updates[0]; ud; ud = ud->next) {
+ unregister_cpu_under_node(update->cpu, update->old_nid);
+ register_cpu_under_node(update->cpu, update->new_nid);
+
dev = get_cpu_device(ud->cpu);
if (dev)
kobject_uevent(&dev->kobj, KOBJ_CHANGE);
^ permalink raw reply
* [PATCH] Correct build warnings with CONFIG_TRANSPARENT_HUGEPAGE disabled
From: Nathan Fontenot @ 2013-06-24 14:35 UTC (permalink / raw)
To: linuxppc-dev; +Cc: aneesh.kumar
Building with CONFIG_TRANSPARENT_HUGEPAGE disabled causes the following
build wearnings;
powerpc/arch/powerpc/include/asm/mmu-hash64.h: In function ‘__hash_page_thp’:
powerpc/arch/powerpc/include/asm/mmu-hash64.h:354: warning: no return statement in function returning non-void
This patch adds a return -1 to the static inline for __hash_page_thp()
to correct the warnings.
Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mmu-hash64.h | 1 +
1 file changed, 1 insertion(+)
Index: powerpc/arch/powerpc/include/asm/mmu-hash64.h
===================================================================
--- powerpc.orig/arch/powerpc/include/asm/mmu-hash64.h 2013-06-24 07:54:08.000000000 -0500
+++ powerpc/arch/powerpc/include/asm/mmu-hash64.h 2013-06-24 08:07:56.000000000 -0500
@@ -351,6 +351,7 @@
int ssize, unsigned int psize)
{
BUG();
+ return -1;
}
#endif
extern void hash_failure_debug(unsigned long ea, unsigned long access,
^ permalink raw reply
* Re: [PATCH] Correct build warnings with CONFIG_TRANSPARENT_HUGEPAGE disabled
From: Aneesh Kumar K.V @ 2013-06-24 15:05 UTC (permalink / raw)
To: Nathan Fontenot, linuxppc-dev
In-Reply-To: <51C8594B.1080701@linux.vnet.ibm.com>
Nathan Fontenot <nfont@linux.vnet.ibm.com> writes:
> Building with CONFIG_TRANSPARENT_HUGEPAGE disabled causes the following
> build wearnings;
>
> powerpc/arch/powerpc/include/asm/mmu-hash64.h: In function =E2=80=98__has=
h_page_thp=E2=80=99:
> powerpc/arch/powerpc/include/asm/mmu-hash64.h:354: warning: no return sta=
tement in function returning non-void
>
> This patch adds a return -1 to the static inline for __hash_page_thp()
> to correct the warnings.
>
> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Wondering why i am not finding this
[root@llmp24l02 thp]# make arch/powerpc/mm/hash_utils_64.o
....
.....
CC arch/powerpc/mm/hash_utils_64.o
[root@llmp24l02 thp]# grep TRANSPARENT_HUGEPAGE .config
CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=3Dy
# CONFIG_TRANSPARENT_HUGEPAGE is not set
[root@llmp24l02 thp]#=20
[root@llmp24l02 thp]# gcc --version
gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8)
Copyright (C) 2012 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> ---
> arch/powerpc/include/asm/mmu-hash64.h | 1 +
> 1 file changed, 1 insertion(+)
>
> Index: powerpc/arch/powerpc/include/asm/mmu-hash64.h
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> --- powerpc.orig/arch/powerpc/include/asm/mmu-hash64.h 2013-06-24 07:54:0=
8.000000000 -0500
> +++ powerpc/arch/powerpc/include/asm/mmu-hash64.h 2013-06-24 08:07:56.000=
000000 -0500
> @@ -351,6 +351,7 @@
> int ssize, unsigned int psize)
> {
> BUG();
> + return -1;
> }
> #endif
> extern void hash_failure_debug(unsigned long ea, unsigned long access,
^ permalink raw reply
* Re: [PATCH] Correct build warnings with CONFIG_TRANSPARENT_HUGEPAGE disabled
From: Aneesh Kumar K.V @ 2013-06-24 15:31 UTC (permalink / raw)
To: Nathan Fontenot, linuxppc-dev
In-Reply-To: <87hagnzgzk.fsf@linux.vnet.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> Nathan Fontenot <nfont@linux.vnet.ibm.com> writes:
>
>> Building with CONFIG_TRANSPARENT_HUGEPAGE disabled causes the following
>> build wearnings;
>>
>> powerpc/arch/powerpc/include/asm/mmu-hash64.h: In function =E2=80=98__ha=
sh_page_thp=E2=80=99:
>> powerpc/arch/powerpc/include/asm/mmu-hash64.h:354: warning: no return st=
atement in function returning non-void
>>
>> This patch adds a return -1 to the static inline for __hash_page_thp()
>> to correct the warnings.
>>
>> Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
>
> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> Wondering why i am not finding this
>
> [root@llmp24l02 thp]# make arch/powerpc/mm/hash_utils_64.o
> ....
> .....
> CC arch/powerpc/mm/hash_utils_64.o
> [root@llmp24l02 thp]# grep TRANSPARENT_HUGEPAGE .config
> CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=3Dy
> # CONFIG_TRANSPARENT_HUGEPAGE is not set
> [root@llmp24l02 thp]#=20
> [root@llmp24l02 thp]# gcc --version
> gcc (GCC) 4.7.2 20121109 (Red Hat 4.7.2-8)
> Copyright (C) 2012 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions. There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOS=
E.
>
>
new compilers have __builtin_unreachable in BUG. That is why it didn't
trigger for me.=20
new compiler:
_____________
static inline __attribute__((always_inline)) __attribute__((no_instrument_f=
unction)) int __hash_page_thp(unsigned long ea, unsigned long access,
unsigned long vsid, pmd_t *pmdp,
unsigned long trap, int local,
int ssize, unsigned int psize)
{
do { __asm__ __volatile__( "1: twi 31,0,0\n" ".section __bug_table,\"a\"\n=
" "2:\t" ".llong" " " "1b, %0\n" "\t.short %1, %2\n" ".org 2b+%3\n" ".previ=
ous\n" : : "i" ("/home/opensource/sources/kernels/linux-powerpc/arch/powerp=
c/include/asm/mmu-hash64.h"), "i" (353), "i" (0), "i" (sizeof(struct bug_en=
try))); __builtin_unreachable(); } while (0);
}
failure:
__________
static inline __attribute__((always_inline)) __attribute__((no_instrument_f=
unction)) int __hash_page_thp(unsigned long ea, unsigned long access,
unsigned long vsid, pmd_t *pmdp,
unsigned long trap, int local,
int ssize, unsigned int psize)
{
do { __asm__ __volatile__( "1: twi 31,0,0\n" ".section __bug_table,\"a\"\n=
" "2:\t" ".llong" " " "1b, %0\n" "\t.short %1, %2\n" ".org 2b+%3\n" ".previ=
ous\n" : : "i" ("/home/nfont/src/powerpc/arch/powerpc/include/asm/mmu-hash6=
4.h"), "i" (353), "i" (0), "i" (sizeof(struct bug_entry))); do { } while (1=
); } while (0);
}
-aneesh
^ permalink raw reply
* RE: [PATCH] Correct build warnings with CONFIG_TRANSPARENT_HUGEPAGE disabled
From: David Laight @ 2013-06-24 16:27 UTC (permalink / raw)
To: Aneesh Kumar K.V, Nathan Fontenot, linuxppc-dev
In-Reply-To: <87ehbrzfsc.fsf@linux.vnet.ibm.com>
PiBmYWlsdXJlOg0KPiBfX19fX19fX19fDQo+IHN0YXRpYyBpbmxpbmUgX19hdHRyaWJ1dGVfXygo
YWx3YXlzX2lubGluZSkpIF9fYXR0cmlidXRlX18oKG5vX2luc3RydW1lbnRfZnVuY3Rpb24pKSBp
bnQNCj4gX19oYXNoX3BhZ2VfdGhwKHVuc2lnbmVkIGxvbmcgZWEsIHVuc2lnbmVkIGxvbmcgYWNj
ZXNzLA0KPiAgICAgICB1bnNpZ25lZCBsb25nIHZzaWQsIHBtZF90ICpwbWRwLA0KPiAgICAgICB1
bnNpZ25lZCBsb25nIHRyYXAsIGludCBsb2NhbCwNCj4gICAgICAgaW50IHNzaXplLCB1bnNpZ25l
ZCBpbnQgcHNpemUpDQo+IHsNCj4gIGRvIHsgX19hc21fXyBfX3ZvbGF0aWxlX18oICIxOiB0d2kg
MzEsMCwwXG4iICIuc2VjdGlvbiBfX2J1Z190YWJsZSxcImFcIlxuIiAiMjpcdCIgIi5sbG9uZyIg
IiAiICIxYiwNCj4gJTBcbiIgIlx0LnNob3J0ICUxLCAlMlxuIiAiLm9yZyAyYislM1xuIiAiLnBy
ZXZpb3VzXG4iIDogOiAiaSINCj4gKCIvaG9tZS9uZm9udC9zcmMvcG93ZXJwYy9hcmNoL3Bvd2Vy
cGMvaW5jbHVkZS9hc20vbW11LWhhc2g2NC5oIiksICJpIiAoMzUzKSwgImkiICgwKSwgImkiDQo+
IChzaXplb2Yoc3RydWN0IGJ1Z19lbnRyeSkpKTsgZG8geyB9IHdoaWxlICgxKTsgfSB3aGlsZSAo
MCk7DQo+IH0NCg0KV2h5IGlzbid0IHRoZSAiZG8geyB9IHdoaWxlICgxKTsiIGVub3VnaCB0byBz
dG9wIHRoZSBjb21waWxlcg0KZXhwZWN0aW5nIHRoZSBhYm92ZSB0byByZXR1cm4/DQpJIGtub3cg
SSd2ZSBhZGRlZCAiZm9yICg7Oyk7IiBpbiBzb21lIGNvZGUgYmVmb3JlIG5vdy4NCkRpc2FibGlu
ZyBvcHRpbWlzYXRpb25zIHdvdWxkIGJlIGVub3VnaCAtIGJ1dCB1bmxpa2VseSB0byBiZSB0cnVl
Lg0KDQoJRGF2aWQNCg0K
^ permalink raw reply
* Re: [PATCH] Do not update sysfs cpu registration from invalid context
From: Seth Jennings @ 2013-06-24 17:18 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <51C8543F.6080905@linux.vnet.ibm.com>
On Mon, Jun 24, 2013 at 09:14:23AM -0500, Nathan Fontenot wrote:
> The topology update code that updates the cpu node registration in sysfs
> should not be called while in stop_machine(). The register/unregister
> calls take a lock and may sleep.
>
> This patch moves these calls outside of the call to stop_machine().
>
> Signed-off-by:Nathan Fontenot <nfont@linux.vnet.ibm.com>
Reviewed-by: Seth Jennings <sjenning@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/numa.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> Index: powerpc/arch/powerpc/mm/numa.c
> ===================================================================
> --- powerpc.orig/arch/powerpc/mm/numa.c 2013-06-24 06:53:31.000000000 -0500
> +++ powerpc/arch/powerpc/mm/numa.c 2013-06-24 06:56:30.000000000 -0500
> @@ -1433,11 +1433,9 @@
> if (cpu != update->cpu)
> continue;
>
> - unregister_cpu_under_node(update->cpu, update->old_nid);
> unmap_cpu_from_node(update->cpu);
> map_cpu_to_node(update->cpu, update->new_nid);
> vdso_getcpu_init();
> - register_cpu_under_node(update->cpu, update->new_nid);
> }
>
> return 0;
> @@ -1485,6 +1483,9 @@
> stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
>
> for (ud = &updates[0]; ud; ud = ud->next) {
> + unregister_cpu_under_node(update->cpu, update->old_nid);
> + register_cpu_under_node(update->cpu, update->new_nid);
> +
> dev = get_cpu_device(ud->cpu);
> if (dev)
> kobject_uevent(&dev->kobj, KOBJ_CHANGE);
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH 25/45] staging/octeon: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Srivatsa S. Bhat @ 2013-06-24 17:25 UTC (permalink / raw)
To: Joe Perches
Cc: peterz, fweisbec, oleg, walken, mingo, linux-arch,
vincent.guittot, ddaney, xiaoguangrong, wangyun, paulmck, devel,
nikunj, linux-pm, rusty, rostedt, namhyung, tglx, laijs, zhong,
Greg Kroah-Hartman, linux-kernel, sbw, netdev, tj, akpm,
linuxppc-dev
In-Reply-To: <1372015045.3137.67.camel@joe-AO722>
On 06/24/2013 12:47 AM, Joe Perches wrote:
> On Mon, 2013-06-24 at 00:25 +0530, Srivatsa S. Bhat wrote:
>> On 06/23/2013 11:47 PM, Greg Kroah-Hartman wrote:
>>> On Sun, Jun 23, 2013 at 07:13:33PM +0530, Srivatsa S. Bhat wrote:
> []
>>>> diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
> []
>> Honestly, I don't know. Let's CC the author of that code (David Daney).
>> I wonder why get_maintainer.pl didn't generate his name for this file,
>> even though the entire file is almost made up of his commits alone!
>
> Because by default, get_maintainer looks for a matching
> file entry in MAINTAINERS. Failing that, it looks at
> one year of git history. In this case, no work has been
> done on the file for quite awhile.
>
> --git-blame can be added to the get_maintainer.pl command
> line to look for % of authorship by line and commit count.
>
> Adding --git-blame can take a long time to run, that's why
> it's not on by default. Also, very old history can give
> invalid email addresses as people move around and email
> addresses decay.
>
> If you always want to find original authors, you could
> use a .get_maintainer.conf file with --git-blame in it.
>
> $ time ./scripts/get_maintainer.pl --git-blame -f drivers/staging/octeon/ethernet-tx.c
> Greg Kroah-Hartman <gregkh@linuxfoundation.org> (supporter:STAGING SUBSYSTEM,commits:4/16=25%)
> David Daney <ddaney@caviumnetworks.com> (authored lines:711/725=98%,commits:13/16=81%)
> Ralf Baechle <ralf@linux-mips.org> (commits:11/16=69%)
> Eric Dumazet <eric.dumazet@gmail.com> (commits:2/16=12%)
> Andrew Morton <akpm@linux-foundation.org> (commits:1/16=6%)
> devel@driverdev.osuosl.org (open list:STAGING SUBSYSTEM)
> linux-kernel@vger.kernel.org (open list)
>
> real 0m16.853s
> user 0m16.088s
> sys 0m0.444s
>
>
Oh, ok.. Thanks for the explanation and the tip!
Regards,
Srivatsa S. Bhat
^ permalink raw reply
* Re: [PATCH 22/45] percpu_counter: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Tejun Heo @ 2013-06-24 17:55 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: peterz, fweisbec, linux-kernel, walken, mingo, linux-arch,
vincent.guittot, xiaoguangrong, wangyun, paulmck, nikunj,
linux-pm, rusty, rostedt, Al Viro, namhyung, tglx, laijs, zhong,
netdev, oleg, sbw, akpm, linuxppc-dev
In-Reply-To: <20130623134256.19094.99231.stgit@srivatsabhat.in.ibm.com>
On Sun, Jun 23, 2013 at 07:12:59PM +0530, Srivatsa S. Bhat wrote:
> Once stop_machine() is gone from the CPU offline path, we won't be able
> to depend on disabling preemption to prevent CPUs from going offline
> from under us.
>
> Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
> offline, while invoking from atomic context.
>
> Cc: Al Viro <viro@zeniv.linux.org.uk>
> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
...
> @@ -98,6 +98,7 @@ s64 __percpu_counter_sum(struct percpu_counter *fbc)
> s64 ret;
> int cpu;
>
> + get_online_cpus_atomic();
> raw_spin_lock(&fbc->lock);
> ret = fbc->count;
> for_each_online_cpu(cpu) {
> @@ -105,6 +106,7 @@ s64 __percpu_counter_sum(struct percpu_counter *fbc)
> ret += *pcount;
> }
> raw_spin_unlock(&fbc->lock);
> + put_online_cpus_atomic();
I don't think this is necessary. CPU on/offlining is explicitly
handled via the hotplug callback which synchronizes through fbc->lock.
__percpu_counter_sum() racing with actual on/offlining doesn't affect
correctness and adding superflous get_online_cpus_atomic() around it
can be misleading.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 3/3] powerpc/pseries: Support compression of oops text via pstore
From: Kees Cook @ 2013-06-24 17:57 UTC (permalink / raw)
To: Aruna Balakrishnaiah
Cc: jkenisto, Tony Luck, Colin Cross, LKML, Anton Vorontsov,
linuxppc-dev, paulus, Anton Blanchard, mahesh
In-Reply-To: <20130624062316.12963.87911.stgit@aruna-ThinkPad-T420>
On Sun, Jun 23, 2013 at 11:23 PM, Aruna Balakrishnaiah
<aruna@linux.vnet.ibm.com> wrote:
> The patch set supports compression of oops messages while writing to NVRAM,
> this helps in capturing more of oops data to lnx,oops-log. The pstore file
> for oops messages will be in decompressed format making it readable.
>
> In case compression fails, the patch takes care of copying the header added
> by pstore and last oops_data_sz bytes of big_oops_buf to NVRAM so that we
> have recent oops messages in lnx,oops-log.
>
> In case decompression fails, it will result in absence of oops file but still
> have files (in /dev/pstore) for other partitions.
>
> Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/pseries/nvram.c | 132 +++++++++++++++++++++++++++++---
> 1 file changed, 118 insertions(+), 14 deletions(-)
>
> diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
> index 0159d74..b5ba5e2 100644
> --- a/arch/powerpc/platforms/pseries/nvram.c
> +++ b/arch/powerpc/platforms/pseries/nvram.c
> @@ -539,6 +539,65 @@ static int zip_oops(size_t text_len)
> }
>
> #ifdef CONFIG_PSTORE
> +/* Derived from logfs_uncompress */
> +int nvram_decompress(void *in, void *out, size_t inlen, size_t outlen)
> +{
> + int err, ret;
> +
> + ret = -EIO;
> + err = zlib_inflateInit(&stream);
> + if (err != Z_OK)
> + goto error;
> +
> + stream.next_in = in;
> + stream.avail_in = inlen;
> + stream.total_in = 0;
> + stream.next_out = out;
> + stream.avail_out = outlen;
> + stream.total_out = 0;
> +
> + err = zlib_inflate(&stream, Z_FINISH);
> + if (err != Z_STREAM_END)
> + goto error;
> +
> + err = zlib_inflateEnd(&stream);
> + if (err != Z_OK)
> + goto error;
> +
> + ret = stream.total_out;
> +error:
> + return ret;
> +}
> +
> +static int unzip_oops(char *oops_buf, char *big_buf)
> +{
> + struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
> + u64 timestamp = oops_hdr->timestamp;
> + char *big_oops_data = NULL;
> + char *oops_data_buf = NULL;
> + size_t big_oops_data_sz;
> + int unzipped_len;
> +
> + big_oops_data = big_buf + sizeof(struct oops_log_info);
> + big_oops_data_sz = big_oops_buf_sz - sizeof(struct oops_log_info);
> + oops_data_buf = oops_buf + sizeof(struct oops_log_info);
> +
> + unzipped_len = nvram_decompress(oops_data_buf, big_oops_data,
> + oops_hdr->report_length,
> + big_oops_data_sz);
> +
> + if (unzipped_len < 0) {
> + pr_err("nvram: decompression failed; returned %d\n",
> + unzipped_len);
> + return -1;
> + }
> + oops_hdr = (struct oops_log_info *)big_buf;
> + oops_hdr->version = OOPS_HDR_VERSION;
> + oops_hdr->report_length = (u16) unzipped_len;
> + oops_hdr->timestamp = timestamp;
> + return 0;
> +}
> +
> static int nvram_pstore_open(struct pstore_info *psi)
> {
> /* Reset the iterator to start reading partitions again */
> @@ -567,6 +626,7 @@ static int nvram_pstore_write(enum pstore_type_id type,
> size_t size, struct pstore_info *psi)
> {
> int rc;
> + unsigned int err_type = ERR_TYPE_KERNEL_PANIC;
> struct oops_log_info *oops_hdr = (struct oops_log_info *) oops_buf;
>
> /* part 1 has the recent messages from printk buffer */
> @@ -577,8 +637,31 @@ static int nvram_pstore_write(enum pstore_type_id type,
> oops_hdr->version = OOPS_HDR_VERSION;
> oops_hdr->report_length = (u16) size;
> oops_hdr->timestamp = get_seconds();
> +
> + if (big_oops_buf) {
> + rc = zip_oops(size);
> + /*
> + * If compression fails copy recent log messages from
> + * big_oops_buf to oops_data.
> + */
> + if (rc != 0) {
> + int hsize = pstore_get_header_size();
I think I would rather see the API to pstore_write() changed to
include explicit details about header sizes. Mkaing hsize a global
seems unwise, since it's not strictly going to be a constant value. It
could change between calls to the writer, for example.
Beyond that, this all seems sensible, though it would be kind of cool
to move this compression logic into the pstore core so it would get
used by default (or through a module parameter).
-Kees
> + size_t diff = size - oops_data_sz + hsize;
> +
> + if (size > oops_data_sz) {
> + memcpy(oops_data, big_oops_buf, hsize);
> + memcpy(oops_data + hsize, big_oops_buf + diff,
> + oops_data_sz - hsize);
> +
> + oops_hdr->report_length = (u16) oops_data_sz;
> + } else
> + memcpy(oops_data, big_oops_buf, size);
> + } else
> + err_type = ERR_TYPE_KERNEL_PANIC_GZ;
> + }
> +
> rc = nvram_write_os_partition(&oops_log_partition, oops_buf,
> - (int) (sizeof(*oops_hdr) + size), ERR_TYPE_KERNEL_PANIC,
> + (int) (sizeof(*oops_hdr) + oops_hdr->report_length), err_type,
> count);
>
> if (rc != 0)
> @@ -600,10 +683,11 @@ static ssize_t nvram_pstore_read(u64 *id, enum pstore_type_id *type,
> struct oops_log_info *oops_hdr;
> unsigned int err_type, id_no, size = 0;
> struct nvram_os_partition *part = NULL;
> - char *buff = NULL;
> - int sig = 0;
> + char *buff = NULL, *big_buff = NULL;
> + int rc, sig = 0;
> loff_t p;
>
> +read_partition:
> read_type++;
>
> switch (nvram_type_ids[read_type]) {
> @@ -666,6 +750,25 @@ static ssize_t nvram_pstore_read(u64 *id, enum pstore_type_id *type,
> if (nvram_type_ids[read_type] == PSTORE_TYPE_DMESG) {
> oops_hdr = (struct oops_log_info *)buff;
> *buf = buff + sizeof(*oops_hdr);
> +
> + if (err_type == ERR_TYPE_KERNEL_PANIC_GZ) {
> + big_buff = kmalloc(big_oops_buf_sz, GFP_KERNEL);
> + if (!big_buff)
> + return -ENOMEM;
> +
> + rc = unzip_oops(buff, big_buff);
> +
> + if (rc != 0) {
> + kfree(buff);
> + kfree(big_buff);
> + goto read_partition;
> + }
> +
> + oops_hdr = (struct oops_log_info *)big_buff;
> + *buf = big_buff + sizeof(*oops_hdr);
> + kfree(buff);
> + }
> +
> time->tv_sec = oops_hdr->timestamp;
> time->tv_nsec = 0;
> return oops_hdr->report_length;
> @@ -687,17 +790,18 @@ static int nvram_pstore_init(void)
> {
> int rc = 0;
>
> - nvram_pstore_info.buf = oops_data;
> - nvram_pstore_info.bufsize = oops_data_sz;
> + if (big_oops_buf) {
> + nvram_pstore_info.buf = big_oops_buf;
> + nvram_pstore_info.bufsize = big_oops_buf_sz;
> + } else {
> + nvram_pstore_info.buf = oops_data;
> + nvram_pstore_info.bufsize = oops_data_sz;
> + }
>
> rc = pstore_register(&nvram_pstore_info);
> if (rc != 0)
> pr_err("nvram: pstore_register() failed, defaults to "
> "kmsg_dump; returned %d\n", rc);
> - else
> - /*TODO: Support compression when pstore is configured */
> - pr_info("nvram: Compression of oops text supported only when "
> - "pstore is not configured");
>
> return rc;
> }
> @@ -731,11 +835,6 @@ static void __init nvram_init_oops_partition(int rtas_partition_exists)
> oops_data = oops_buf + sizeof(struct oops_log_info);
> oops_data_sz = oops_log_partition.size - sizeof(struct oops_log_info);
>
> - rc = nvram_pstore_init();
> -
> - if (!rc)
> - return;
> -
> /*
> * Figure compression (preceded by elimination of each line's <n>
> * severity prefix) will reduce the oops/panic report to at most
> @@ -759,6 +858,11 @@ static void __init nvram_init_oops_partition(int rtas_partition_exists)
> stream.workspace = NULL;
> }
>
> + rc = nvram_pstore_init();
> +
> + if (!rc)
> + return;
> +
> rc = kmsg_dump_register(&nvram_kmsg_dumper);
> if (rc != 0) {
> pr_err("nvram: kmsg_dump_register() failed; returned %d\n", rc);
>
--
Kees Cook
Chrome OS Security
^ permalink raw reply
* Re: [PATCH 22/45] percpu_counter: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Tejun Heo @ 2013-06-24 18:06 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: peterz, fweisbec, linux-kernel, walken, mingo, linux-arch,
vincent.guittot, xiaoguangrong, wangyun, paulmck, nikunj,
linux-pm, rusty, rostedt, Al Viro, namhyung, tglx, laijs, zhong,
netdev, oleg, sbw, akpm, linuxppc-dev
In-Reply-To: <20130624175535.GA1918@mtj.dyndns.org>
On Mon, Jun 24, 2013 at 10:55:35AM -0700, Tejun Heo wrote:
> > @@ -105,6 +106,7 @@ s64 __percpu_counter_sum(struct percpu_counter *fbc)
> > ret += *pcount;
> > }
> > raw_spin_unlock(&fbc->lock);
> > + put_online_cpus_atomic();
>
> I don't think this is necessary. CPU on/offlining is explicitly
> handled via the hotplug callback which synchronizes through fbc->lock.
> __percpu_counter_sum() racing with actual on/offlining doesn't affect
> correctness and adding superflous get_online_cpus_atomic() around it
> can be misleading.
Ah, okay, so you added a debug feature which triggers warning if
online mask is accessed without synchronization. Yeah, that makes
sense and while the above is not strictly necessary, it probably is
better to just add it rather than suppressing the warning in a
different way. Can you please at least add a comment explaining that?
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 22/45] percpu_counter: Use get/put_online_cpus_atomic() to prevent CPU offline
From: Srivatsa S. Bhat @ 2013-06-24 18:09 UTC (permalink / raw)
To: Tejun Heo
Cc: peterz, fweisbec, linux-kernel, walken, mingo, linux-arch,
vincent.guittot, xiaoguangrong, wangyun, paulmck, nikunj,
linux-pm, rusty, rostedt, Al Viro, namhyung, tglx, laijs, zhong,
netdev, oleg, sbw, akpm, linuxppc-dev
In-Reply-To: <20130624180636.GB1918@mtj.dyndns.org>
On 06/24/2013 11:36 PM, Tejun Heo wrote:
> On Mon, Jun 24, 2013 at 10:55:35AM -0700, Tejun Heo wrote:
>>> @@ -105,6 +106,7 @@ s64 __percpu_counter_sum(struct percpu_counter *fbc)
>>> ret += *pcount;
>>> }
>>> raw_spin_unlock(&fbc->lock);
>>> + put_online_cpus_atomic();
>>
>> I don't think this is necessary. CPU on/offlining is explicitly
>> handled via the hotplug callback which synchronizes through fbc->lock.
>> __percpu_counter_sum() racing with actual on/offlining doesn't affect
>> correctness and adding superflous get_online_cpus_atomic() around it
>> can be misleading.
>
> Ah, okay, so you added a debug feature which triggers warning if
> online mask is accessed without synchronization.
Exactly!
> Yeah, that makes
> sense and while the above is not strictly necessary, it probably is
> better to just add it rather than suppressing the warning in a
> different way.
Yeah, I was beginning to scratch my head as to how to suppress the
warning after I read your explanation as to why the calls to
get/put_online_cpus_atomic() would be superfluous in this case...
But as you said, simply invoking those functions is much simpler ;-)
> Can you please at least add a comment explaining that?
>
Sure, will do. Thanks a lot Tejun!
Regards,
Srivatsa S. Bhat
^ permalink raw reply
* Re: [PATCH 25/45] staging/octeon: Use get/put_online_cpus_atomic() to prevent CPU offline
From: David Daney @ 2013-06-24 18:17 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: peterz, fweisbec, linux-kernel, walken, mingo, linux-arch,
vincent.guittot, ddaney, xiaoguangrong, wangyun, paulmck, devel,
nikunj, linux-pm, rusty, rostedt, namhyung, tglx, laijs, zhong,
Greg Kroah-Hartman, oleg, sbw, netdev, tj, akpm, linuxppc-dev
In-Reply-To: <51C744A9.8000406@linux.vnet.ibm.com>
On 06/23/2013 11:55 AM, Srivatsa S. Bhat wrote:
> On 06/23/2013 11:47 PM, Greg Kroah-Hartman wrote:
>> On Sun, Jun 23, 2013 at 07:13:33PM +0530, Srivatsa S. Bhat wrote:
>>> Once stop_machine() is gone from the CPU offline path, we won't be able
>>> to depend on disabling preemption to prevent CPUs from going offline
>>> from under us.
>>>
>>> Use the get/put_online_cpus_atomic() APIs to prevent CPUs from going
>>> offline, while invoking from atomic context.
>>>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> Cc: devel@driverdev.osuosl.org
>>> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
>>> ---
>>>
>>> drivers/staging/octeon/ethernet-rx.c | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c
>>> index 34afc16..8588b4d 100644
>>> --- a/drivers/staging/octeon/ethernet-rx.c
>>> +++ b/drivers/staging/octeon/ethernet-rx.c
>>> @@ -36,6 +36,7 @@
>>> #include <linux/prefetch.h>
>>> #include <linux/ratelimit.h>
>>> #include <linux/smp.h>
>>> +#include <linux/cpu.h>
>>> #include <linux/interrupt.h>
>>> #include <net/dst.h>
>>> #ifdef CONFIG_XFRM
>>> @@ -97,6 +98,7 @@ static void cvm_oct_enable_one_cpu(void)
>>> return;
>>>
>>> /* ... if a CPU is available, Turn on NAPI polling for that CPU. */
>>> + get_online_cpus_atomic();
>>> for_each_online_cpu(cpu) {
>>> if (!cpu_test_and_set(cpu, core_state.cpu_state)) {
>>> v = smp_call_function_single(cpu, cvm_oct_enable_napi,
>>> @@ -106,6 +108,7 @@ static void cvm_oct_enable_one_cpu(void)
>>> break;
>>> }
>>> }
>>> + put_online_cpus_atomic();
>>
>> Does this driver really need to be doing this in the first place? If
>> so, why? The majority of network drivers don't, why is this one
>> "special"?
It depends on your definition of "need".
The current driver receives packets from *all* network ports into a
single queue (in OCTEON speak this queue is called a POW group). Under
high packet rates, the CPU time required to process the packets may
exceed the capabilities of a single CPU.
In order to increase throughput beyond the single CPU limited rate, we
bring more than one CPUs into play for NAPI receive. The code being
patched here is part of the logic that controls which CPUs are used for
NAPI receive.
Just for the record: Yes I know that doing this may lead to packet
reordering when doing forwarding.
A further question that wasn't asked is: Will the code work at all if a
CPU is taken offline even if the race, the patch eliminates, is avoided?
I doubt it.
As far as the patch goes:
Acked-by: David Daney <david.daney@cavium.com>
David Daney
>>
>
> Honestly, I don't know. Let's CC the author of that code (David Daney).
> I wonder why get_maintainer.pl didn't generate his name for this file,
> even though the entire file is almost made up of his commits alone!
>
> Regards,
> Srivatsa S. Bhat
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
^ permalink raw reply
* Re: Pull request: scottwood/linux.git for-3.10
From: Scott Wood @ 2013-06-24 18:33 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <1371660630.9073.34@snotra>
On 06/19/2013 11:50:30 AM, Scott Wood wrote:
> On 06/19/2013 10:06:38 AM, Kumar Gala wrote:
>>=20
>> On Jun 18, 2013, at 3:14 PM, Scott Wood wrote:
>>=20
>> > This fixes a regression that causes 83xx to oops on boot if a
>> > non-express PCI bus is present.
>> >
>> > The following changes since commit =20
>> 17858ca65eef148d335ffd4cfc09228a1c1cbfb5:
>> >
>> > Merge tag 'please-pull-fixia64' of =20
>> git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux (2013-06-18 =20
>> 06:29:19 -1000)
>> >
>> > are available in the git repository at:
>> >
>> >
>> > git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git =20
>> for-3.10
>> >
>> > for you to fetch changes up to =20
>> 2383ea94854bcf5a0df3c6803b980868cef95418:
>> >
>> > powerpc/pci: Fix setup of Freescale PCI / PCIe controllers =20
>> (2013-06-18 14:44:57 -0500)
>> >
>> > ----------------------------------------------------------------
>> > Rojhalat Ibrahim (1):
>> > powerpc/pci: Fix setup of Freescale PCI / PCIe controllers
>> >
>> > arch/powerpc/sysdev/fsl_pci.c | 24 +++++++++---------------
>> > 1 file changed, 9 insertions(+), 15 deletions(-)
>>=20
>> What about Rohit's patch: powerpc/pci: Fix setup of Freescale PCI / =20
>> PCIe controllers? Seems like also a fix for 3.10
>=20
> That's the patch I'm asking you to pull. :-P
Ping
-Scott=
^ permalink raw reply
* Re: [PATCH] Do not update sysfs cpu registration from invalid context
From: Seth Jennings @ 2013-06-24 19:16 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linuxppc-dev
In-Reply-To: <20130624171804.GB3869@cerebellum>
On Mon, Jun 24, 2013 at 12:18:04PM -0500, Seth Jennings wrote:
> On Mon, Jun 24, 2013 at 09:14:23AM -0500, Nathan Fontenot wrote:
> > The topology update code that updates the cpu node registration in sysfs
> > should not be called while in stop_machine(). The register/unregister
> > calls take a lock and may sleep.
> >
> > This patch moves these calls outside of the call to stop_machine().
> >
> > Signed-off-by:Nathan Fontenot <nfont@linux.vnet.ibm.com>
>
> Reviewed-by: Seth Jennings <sjenning@linux.vnet.ibm.com>
Gah! I _knew_ I should have waited for my cross compiler to finish
building. This thing doesn't build:
CC arch/powerpc/mm/numa.o
/home/sjennings/ltc/linux/arch/powerpc/mm/numa.c: In function 'arch_update_cpu_topology':
/home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: 'update' undeclared (first use in this function)
/home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: (Each undeclared identifier is reported only once
/home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: for each function it appears in.)
s/update/ud/ in the *_cpu_under_node() calls.
Seth
^ permalink raw reply
* Re: [PATCH] Do not update sysfs cpu registration from invalid context
From: Nathan Fontenot @ 2013-06-24 19:25 UTC (permalink / raw)
To: Seth Jennings; +Cc: linuxppc-dev
In-Reply-To: <20130624191611.GC3869@cerebellum>
On 06/24/2013 02:16 PM, Seth Jennings wrote:
> On Mon, Jun 24, 2013 at 12:18:04PM -0500, Seth Jennings wrote:
>> On Mon, Jun 24, 2013 at 09:14:23AM -0500, Nathan Fontenot wrote:
>>> The topology update code that updates the cpu node registration in sysfs
>>> should not be called while in stop_machine(). The register/unregister
>>> calls take a lock and may sleep.
>>>
>>> This patch moves these calls outside of the call to stop_machine().
>>>
>>> Signed-off-by:Nathan Fontenot <nfont@linux.vnet.ibm.com>
>>
>> Reviewed-by: Seth Jennings <sjenning@linux.vnet.ibm.com>
>
> Gah! I _knew_ I should have waited for my cross compiler to finish
> building. This thing doesn't build:
>
> CC arch/powerpc/mm/numa.o
> /home/sjennings/ltc/linux/arch/powerpc/mm/numa.c: In function 'arch_update_cpu_topology':
> /home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: 'update' undeclared (first use in this function)
> /home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: (Each undeclared identifier is reported only once
> /home/sjennings/ltc/linux/arch/powerpc/mm/numa.c:1486: error: for each function it appears in.)
>
> s/update/ud/ in the *_cpu_under_node() calls.
Oops! Time for patch submission re-education training.
New, and correct, patch coming soon.
-Nathan
^ permalink raw reply
* [PATCH 04/32] powerpc: delete __cpuinit usage from all users
From: Paul Gortmaker @ 2013-06-24 19:30 UTC (permalink / raw)
To: linux-kernel; +Cc: Paul Gortmaker, Paul Mackerras, linuxppc-dev
In-Reply-To: <1372102237-8757-1-git-send-email-paul.gortmaker@windriver.com>
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
This removes all the powerpc uses of the __cpuinit macros. There
are no __CPUINIT users in assembly files in powerpc.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
[This commit is part of the __cpuinit removal work. If you don't see
any problems with it, then you don't have to do anything ; it will be
submitted with all the rest of the __cpuinit removal work. On the
other hand, if you want to carry this patch in with your other pending
changes so as to handle conflicts with other pending work yourself, then
that is fine too, as the commits can largely be treated independently.
For more information, please see: https://lkml.org/lkml/2013/6/20/513 ]
arch/powerpc/include/asm/rtas.h | 4 ++--
arch/powerpc/include/asm/vdso.h | 2 +-
arch/powerpc/kernel/cacheinfo.c | 36 ++++++++++++++++++++--------------
arch/powerpc/kernel/rtas.c | 4 ++--
arch/powerpc/kernel/smp.c | 4 ++--
arch/powerpc/kernel/sysfs.c | 6 +++---
arch/powerpc/kernel/time.c | 1 -
arch/powerpc/kernel/vdso.c | 2 +-
arch/powerpc/mm/44x_mmu.c | 6 +++---
arch/powerpc/mm/hash_utils_64.c | 2 +-
arch/powerpc/mm/mmu_context_nohash.c | 6 +++---
arch/powerpc/mm/numa.c | 7 +++----
arch/powerpc/mm/tlb_nohash.c | 2 +-
arch/powerpc/perf/core-book3s.c | 4 ++--
arch/powerpc/platforms/44x/currituck.c | 4 ++--
arch/powerpc/platforms/44x/iss4xx.c | 4 ++--
arch/powerpc/platforms/85xx/smp.c | 6 +++---
arch/powerpc/platforms/powermac/smp.c | 2 +-
arch/powerpc/platforms/powernv/smp.c | 2 +-
19 files changed, 54 insertions(+), 50 deletions(-)
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 34fd704..c7a8bfc 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -350,8 +350,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
(devfn << 8) | (reg & 0xff);
}
-extern void __cpuinit rtas_give_timebase(void);
-extern void __cpuinit rtas_take_timebase(void);
+extern void rtas_give_timebase(void);
+extern void rtas_take_timebase(void);
#ifdef CONFIG_PPC_RTAS
static inline int page_is_rtas_user_buf(unsigned long pfn)
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 50f261b..0d9cecd 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -22,7 +22,7 @@ extern unsigned long vdso64_rt_sigtramp;
extern unsigned long vdso32_sigtramp;
extern unsigned long vdso32_rt_sigtramp;
-int __cpuinit vdso_getcpu_init(void);
+int vdso_getcpu_init(void);
#else /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 92c6b00..9262cf2 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -131,7 +131,8 @@ static const char *cache_type_string(const struct cache *cache)
return cache_type_info[cache->type].name;
}
-static void __cpuinit cache_init(struct cache *cache, int type, int level, struct device_node *ofnode)
+static void cache_init(struct cache *cache, int type, int level,
+ struct device_node *ofnode)
{
cache->type = type;
cache->level = level;
@@ -140,7 +141,7 @@ static void __cpuinit cache_init(struct cache *cache, int type, int level, struc
list_add(&cache->list, &cache_list);
}
-static struct cache *__cpuinit new_cache(int type, int level, struct device_node *ofnode)
+static struct cache *new_cache(int type, int level, struct device_node *ofnode)
{
struct cache *cache;
@@ -324,7 +325,8 @@ static bool cache_node_is_unified(const struct device_node *np)
return of_get_property(np, "cache-unified", NULL);
}
-static struct cache *__cpuinit cache_do_one_devnode_unified(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode_unified(struct device_node *node,
+ int level)
{
struct cache *cache;
@@ -335,7 +337,8 @@ static struct cache *__cpuinit cache_do_one_devnode_unified(struct device_node *
return cache;
}
-static struct cache *__cpuinit cache_do_one_devnode_split(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode_split(struct device_node *node,
+ int level)
{
struct cache *dcache, *icache;
@@ -357,7 +360,7 @@ err:
return NULL;
}
-static struct cache *__cpuinit cache_do_one_devnode(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode(struct device_node *node, int level)
{
struct cache *cache;
@@ -369,7 +372,8 @@ static struct cache *__cpuinit cache_do_one_devnode(struct device_node *node, in
return cache;
}
-static struct cache *__cpuinit cache_lookup_or_instantiate(struct device_node *node, int level)
+static struct cache *cache_lookup_or_instantiate(struct device_node *node,
+ int level)
{
struct cache *cache;
@@ -385,7 +389,7 @@ static struct cache *__cpuinit cache_lookup_or_instantiate(struct device_node *n
return cache;
}
-static void __cpuinit link_cache_lists(struct cache *smaller, struct cache *bigger)
+static void link_cache_lists(struct cache *smaller, struct cache *bigger)
{
while (smaller->next_local) {
if (smaller->next_local == bigger)
@@ -396,13 +400,13 @@ static void __cpuinit link_cache_lists(struct cache *smaller, struct cache *bigg
smaller->next_local = bigger;
}
-static void __cpuinit do_subsidiary_caches_debugcheck(struct cache *cache)
+static void do_subsidiary_caches_debugcheck(struct cache *cache)
{
WARN_ON_ONCE(cache->level != 1);
WARN_ON_ONCE(strcmp(cache->ofnode->type, "cpu"));
}
-static void __cpuinit do_subsidiary_caches(struct cache *cache)
+static void do_subsidiary_caches(struct cache *cache)
{
struct device_node *subcache_node;
int level = cache->level;
@@ -423,7 +427,7 @@ static void __cpuinit do_subsidiary_caches(struct cache *cache)
}
}
-static struct cache *__cpuinit cache_chain_instantiate(unsigned int cpu_id)
+static struct cache *cache_chain_instantiate(unsigned int cpu_id)
{
struct device_node *cpu_node;
struct cache *cpu_cache = NULL;
@@ -448,7 +452,7 @@ out:
return cpu_cache;
}
-static struct cache_dir *__cpuinit cacheinfo_create_cache_dir(unsigned int cpu_id)
+static struct cache_dir *cacheinfo_create_cache_dir(unsigned int cpu_id)
{
struct cache_dir *cache_dir;
struct device *dev;
@@ -653,7 +657,7 @@ static struct kobj_type cache_index_type = {
.default_attrs = cache_index_default_attrs,
};
-static void __cpuinit cacheinfo_create_index_opt_attrs(struct cache_index_dir *dir)
+static void cacheinfo_create_index_opt_attrs(struct cache_index_dir *dir)
{
const char *cache_name;
const char *cache_type;
@@ -696,7 +700,8 @@ static void __cpuinit cacheinfo_create_index_opt_attrs(struct cache_index_dir *d
kfree(buf);
}
-static void __cpuinit cacheinfo_create_index_dir(struct cache *cache, int index, struct cache_dir *cache_dir)
+static void cacheinfo_create_index_dir(struct cache *cache, int index,
+ struct cache_dir *cache_dir)
{
struct cache_index_dir *index_dir;
int rc;
@@ -722,7 +727,8 @@ err:
kfree(index_dir);
}
-static void __cpuinit cacheinfo_sysfs_populate(unsigned int cpu_id, struct cache *cache_list)
+static void cacheinfo_sysfs_populate(unsigned int cpu_id,
+ struct cache *cache_list)
{
struct cache_dir *cache_dir;
struct cache *cache;
@@ -740,7 +746,7 @@ static void __cpuinit cacheinfo_sysfs_populate(unsigned int cpu_id, struct cache
}
}
-void __cpuinit cacheinfo_cpu_online(unsigned int cpu_id)
+void cacheinfo_cpu_online(unsigned int cpu_id)
{
struct cache *cache;
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 52add6f..80b5ef4 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -1172,7 +1172,7 @@ int __init early_init_dt_scan_rtas(unsigned long node,
static arch_spinlock_t timebase_lock;
static u64 timebase = 0;
-void __cpuinit rtas_give_timebase(void)
+void rtas_give_timebase(void)
{
unsigned long flags;
@@ -1189,7 +1189,7 @@ void __cpuinit rtas_give_timebase(void)
local_irq_restore(flags);
}
-void __cpuinit rtas_take_timebase(void)
+void rtas_take_timebase(void)
{
while (!timebase)
barrier();
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ee7ac5e..85398c7 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -480,7 +480,7 @@ static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
secondary_ti = current_set[cpu] = ti;
}
-int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
{
int rc, c;
@@ -610,7 +610,7 @@ static struct device_node *cpu_to_l2cache(int cpu)
}
/* Activate a secondary processor. */
-__cpuinit void start_secondary(void *unused)
+void start_secondary(void *unused)
{
unsigned int cpu = smp_processor_id();
struct device_node *l2_cache;
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index e68a845..27a90b9 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -341,7 +341,7 @@ static struct device_attribute pa6t_attrs[] = {
#endif /* HAS_PPC_PMC_PA6T */
#endif /* HAS_PPC_PMC_CLASSIC */
-static void __cpuinit register_cpu_online(unsigned int cpu)
+static void register_cpu_online(unsigned int cpu)
{
struct cpu *c = &per_cpu(cpu_devices, cpu);
struct device *s = &c->dev;
@@ -502,7 +502,7 @@ ssize_t arch_cpu_release(const char *buf, size_t count)
#endif /* CONFIG_HOTPLUG_CPU */
-static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
+static int sysfs_cpu_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)(long)hcpu;
@@ -522,7 +522,7 @@ static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
return NOTIFY_OK;
}
-static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
+static struct notifier_block sysfs_cpu_nb = {
.notifier_call = sysfs_cpu_notify,
};
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 5fc29ad..65ab9e9 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -631,7 +631,6 @@ static int __init get_freq(char *name, int cells, unsigned long *val)
return found;
}
-/* should become __cpuinit when secondary_cpu_time_init also is */
void start_cpu_decrementer(void)
{
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index d4f463a..1d9c926 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -711,7 +711,7 @@ static void __init vdso_setup_syscall_map(void)
}
#ifdef CONFIG_PPC64
-int __cpuinit vdso_getcpu_init(void)
+int vdso_getcpu_init(void)
{
unsigned long cpu, node, val;
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 2c9441e..82b1ff7 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -41,7 +41,7 @@ int icache_44x_need_flush;
unsigned long tlb_47x_boltmap[1024/8];
-static void __cpuinit ppc44x_update_tlb_hwater(void)
+static void ppc44x_update_tlb_hwater(void)
{
extern unsigned int tlb_44x_patch_hwater_D[];
extern unsigned int tlb_44x_patch_hwater_I[];
@@ -134,7 +134,7 @@ static void __init ppc47x_update_boltmap(void)
/*
* "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
*/
-static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
+static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
{
unsigned int rA;
int bolted;
@@ -229,7 +229,7 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
}
#ifdef CONFIG_SMP
-void __cpuinit mmu_init_secondary(int cpu)
+void mmu_init_secondary(int cpu)
{
unsigned long addr;
unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index e303a6d..4481172 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -807,7 +807,7 @@ void __init early_init_mmu(void)
}
#ifdef CONFIG_SMP
-void __cpuinit early_init_mmu_secondary(void)
+void early_init_mmu_secondary(void)
{
/* Initialize hash table for that CPU */
if (!firmware_has_feature(FW_FEATURE_LPAR))
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 810f8e4..af3d78e 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -332,8 +332,8 @@ void destroy_context(struct mm_struct *mm)
#ifdef CONFIG_SMP
-static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
- unsigned long action, void *hcpu)
+static int mmu_context_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
{
unsigned int cpu = (unsigned int)(long)hcpu;
@@ -366,7 +366,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
return NOTIFY_OK;
}
-static struct notifier_block __cpuinitdata mmu_context_cpu_nb = {
+static struct notifier_block mmu_context_cpu_nb = {
.notifier_call = mmu_context_cpu_notify,
};
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 88c0425..c792cd9 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -516,7 +516,7 @@ static int of_drconf_to_nid_single(struct of_drconf_cell *drmem,
* Figure out to which domain a cpu belongs and stick it there.
* Return the id of the domain used.
*/
-static int __cpuinit numa_setup_cpu(unsigned long lcpu)
+static int numa_setup_cpu(unsigned long lcpu)
{
int nid = 0;
struct device_node *cpu = of_get_cpu_node(lcpu, NULL);
@@ -538,8 +538,7 @@ out:
return nid;
}
-static int __cpuinit cpu_numa_callback(struct notifier_block *nfb,
- unsigned long action,
+static int cpu_numa_callback(struct notifier_block *nfb, unsigned long action,
void *hcpu)
{
unsigned long lcpu = (unsigned long)hcpu;
@@ -919,7 +918,7 @@ static void __init *careful_zallocation(int nid, unsigned long size,
return ret;
}
-static struct notifier_block __cpuinitdata ppc64_numa_nb = {
+static struct notifier_block ppc64_numa_nb = {
.notifier_call = cpu_numa_callback,
.priority = 1 /* Must run before sched domains notifier. */
};
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 6888cad..41cd68d 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -648,7 +648,7 @@ void __init early_init_mmu(void)
__early_init_mmu(1);
}
-void __cpuinit early_init_mmu_secondary(void)
+void early_init_mmu_secondary(void)
{
__early_init_mmu(0);
}
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 29c6482..af94a71 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1786,7 +1786,7 @@ static void power_pmu_setup(int cpu)
cpuhw->mmcr[0] = MMCR0_FC;
}
-static int __cpuinit
+static int
power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
{
unsigned int cpu = (long)hcpu;
@@ -1803,7 +1803,7 @@ power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu
return NOTIFY_OK;
}
-int __cpuinit register_power_pmu(struct power_pmu *pmu)
+int register_power_pmu(struct power_pmu *pmu)
{
if (ppmu)
return -EBUSY; /* something's already registered */
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index c52e1b3..7f1b71a 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -91,12 +91,12 @@ static void __init ppc47x_init_irq(void)
}
#ifdef CONFIG_SMP
-static void __cpuinit smp_ppc47x_setup_cpu(int cpu)
+static void smp_ppc47x_setup_cpu(int cpu)
{
mpic_setup_this_cpu();
}
-static int __cpuinit smp_ppc47x_kick_cpu(int cpu)
+static int smp_ppc47x_kick_cpu(int cpu)
{
struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
const u64 *spin_table_addr_prop;
diff --git a/arch/powerpc/platforms/44x/iss4xx.c b/arch/powerpc/platforms/44x/iss4xx.c
index a28a862..4241bc8 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -81,12 +81,12 @@ static void __init iss4xx_init_irq(void)
}
#ifdef CONFIG_SMP
-static void __cpuinit smp_iss4xx_setup_cpu(int cpu)
+static void smp_iss4xx_setup_cpu(int cpu)
{
mpic_setup_this_cpu();
}
-static int __cpuinit smp_iss4xx_kick_cpu(int cpu)
+static int smp_iss4xx_kick_cpu(int cpu)
{
struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
const u64 *spin_table_addr_prop;
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 6a17599..5ced4f5 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -99,7 +99,7 @@ static void mpc85xx_take_timebase(void)
}
#ifdef CONFIG_HOTPLUG_CPU
-static void __cpuinit smp_85xx_mach_cpu_die(void)
+static void smp_85xx_mach_cpu_die(void)
{
unsigned int cpu = smp_processor_id();
u32 tmp;
@@ -141,7 +141,7 @@ static inline u32 read_spin_table_addr_l(void *spin_table)
return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
}
-static int __cpuinit smp_85xx_kick_cpu(int nr)
+static int smp_85xx_kick_cpu(int nr)
{
unsigned long flags;
const u64 *cpu_rel_addr;
@@ -362,7 +362,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
}
#endif /* CONFIG_KEXEC */
-static void __cpuinit smp_85xx_setup_cpu(int cpu_nr)
+static void smp_85xx_setup_cpu(int cpu_nr)
{
if (smp_85xx_ops.probe == smp_mpic_probe)
mpic_setup_this_cpu();
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index f921067..5cbd4d6 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -885,7 +885,7 @@ static int smp_core99_cpu_notify(struct notifier_block *self,
return NOTIFY_OK;
}
-static struct notifier_block __cpuinitdata smp_core99_cpu_nb = {
+static struct notifier_block smp_core99_cpu_nb = {
.notifier_call = smp_core99_cpu_notify,
};
#endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index 77784ae..89e3857 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -40,7 +40,7 @@
#define DBG(fmt...)
#endif
-static void __cpuinit pnv_smp_setup_cpu(int cpu)
+static void pnv_smp_setup_cpu(int cpu)
{
if (cpu != boot_cpuid)
xics_setup_cpu();
--
1.8.1.2
^ permalink raw reply related
* [PATCH-next 00/32] Delete support for __cpuinit
From: Paul Gortmaker @ 2013-06-24 19:30 UTC (permalink / raw)
To: linux-kernel
Cc: linux-m32r-ja, x86, linux-sh, Viresh Kumar, linux, H. Peter Anvin,
Will Deacon, David Howells, Paul Gortmaker, James Hogan,
Paul Mackerras, Helge Deller, sparclinux, linux-ia64, netdev,
Sonic Zhang, Josh Triplett, Jonas Bonn, linux-s390,
Jesper Nilsson, Russell King, Max Filippov, linux-hexagon,
Hirokazu Takata, linux-pm, cpufreq, lm-sensors, linux-acpi,
Ingo Molnar, Lennox Wu, Catalin Marinas, Matt Turner,
Paul E. McKenney, Len Brown, Fenghua Yu, Bob Liu, Mike Frysinger,
Arnd Bergmann, Chris Zankel, Heiko Carstens, linux-xtensa,
Rusty Russell, Chris Metcalf, Mikael Starvik, linux-m32r,
Ivan Kokshaysky, uclinux-dist-devel, Thomas Gleixner,
linux-arm-kernel, Richard Henderson, Jens Axboe,
Rafael J. Wysocki, Tony Luck, linux-parisc, linux-cris-kernel,
Chen Liqin, Greg Kroah-Hartman, linux390, Richard Kuo, Paul Mundt,
Vineet Gupta, Martin Schwidefsky, John Stultz, linuxppc-dev,
David S. Miller
This is the whole patch queue for removal of __cpuinit support
against the latest linux-next tree (Jun24th). Some of you may
have already seen chunks of it, or already read the logistics
of what is being done (and why) here:
https://lkml.org/lkml/2013/6/20/513
I won't repeat all that here again, other than to say this send
is to ensure arch/subsystem maintainers get a 2nd chance to know
what is going on and to look at what is being proposed for their
area of code. That, and to ensure one complete continuous copy
of it gets mailed out. You can also see the patch queue here:
http://git.kernel.org/cgit/linux/kernel/git/paulg/cpuinit-delete.git
If you've noticed that a chunk for MIPS isn't present here, that
is because it has already been queued in the linux-mips for-next
branch.
Thanks,
Paul.
---
Cc: Len Brown <lenb@kernel.org>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Bob Liu <lliubbo@gmail.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Richard Kuo <rkuo@codeaurora.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jonas Bonn <jonas@southpole.se>
Cc: Helge Deller <deller@gmx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Matt Porter <mporter@kernel.crashing.org>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Cc: Josh Triplett <josh@freedesktop.org>
Cc: Dipankar Sarma <dipankar@in.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Chen Liqin <liqin.chen@sunplusct.com>
Cc: Lennox Wu <lennox.wu@gmail.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: linux-acpi@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: uclinux-dist-devel@blackfin.uclinux.org
Cc: cpufreq@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-cris-kernel@axis.com
Cc: linux-hexagon@vger.kernel.org
Cc: lm-sensors@lm-sensors.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-m32r@ml.linux-m32r.org
Cc: linux-m32r-ja@ml.linux-m32r.org
Cc: netdev@vger.kernel.org
Cc: linux@lists.openrisc.net
Cc: linux-parisc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux390@de.ibm.com
Cc: linux-s390@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: sparclinux@vger.kernel.org
Cc: x86@kernel.org
Cc: linux-xtensa@linux-xtensa.org
Paul Gortmaker (32):
init.h: remove __cpuinit sections from the kernel
modpost: remove all traces of cpuinit/cpuexit sections
alpha: delete __cpuinit usage from all users
powerpc: delete __cpuinit usage from all users
parisc: delete __cpuinit usage from all users
ia64: delete __cpuinit usage from all ia64 users
arm: delete __cpuinit/__CPUINIT usage from all ARM users
sparc: delete __cpuinit/__CPUINIT usage from all users
arm64: delete __cpuinit usage from all users
arc: delete __cpuinit usage from all arc files
blackfin: delete __cpuinit usage from all blackfin files
s390: delete __cpuinit usage from all s390 files
sh: delete __cpuinit usage from all sh files
tile: delete __cpuinit usage from all tile files
metag: delete __cpuinit usage from all metag files
cris: delete __cpuinit usage from all cris files
frv: delete __cpuinit usage from all frv files
hexagon: delete __cpuinit usage from all hexagon files
m32r: delete __cpuinit usage from all m32r files
openrisc: delete __cpuinit usage from all openrisc files
xtensa: delete __cpuinit usage from all xtensa files
score: delete __cpuinit usage from all score files
x86: delete __cpuinit usage from all x86 files
clocksource+irqchip: delete __cpuinit usage from all related files
cpufreq: delete __cpuinit usage from all cpufreq files
hwmon: delete __cpuinit usage from all hwmon files
acpi: delete __cpuinit usage from all acpi files
net: delete __cpuinit usage from all net files
rcu: delete __cpuinit usage from all rcu files
kernel: delete __cpuinit usage from all core kernel files
drivers: delete __cpuinit usage from all remaining drivers files
block: delete __cpuinit usage from all block files
Documentation/cpu-hotplug.txt | 6 +--
arch/alpha/kernel/smp.c | 10 ++---
arch/alpha/kernel/traps.c | 4 +-
arch/arc/include/asm/irq.h | 2 +-
arch/arc/kernel/irq.c | 2 +-
arch/arc/kernel/setup.c | 10 ++---
arch/arc/kernel/smp.c | 4 +-
arch/arc/kernel/time.c | 6 +--
arch/arc/mm/cache_arc700.c | 4 +-
arch/arc/mm/tlb.c | 4 +-
arch/arm/common/mcpm_platsmp.c | 4 +-
arch/arm/include/asm/arch_timer.h | 2 +-
arch/arm/kernel/head-common.S | 1 -
arch/arm/kernel/head.S | 1 -
arch/arm/kernel/hw_breakpoint.c | 4 +-
arch/arm/kernel/perf_event_cpu.c | 6 +--
arch/arm/kernel/psci_smp.c | 3 +-
arch/arm/kernel/smp.c | 18 ++++----
arch/arm/kernel/smp_twd.c | 6 +--
arch/arm/lib/delay.c | 2 +-
arch/arm/mach-exynos/headsmp.S | 2 -
arch/arm/mach-exynos/platsmp.c | 4 +-
arch/arm/mach-highbank/platsmp.c | 2 +-
arch/arm/mach-imx/platsmp.c | 2 +-
arch/arm/mach-msm/headsmp.S | 2 -
arch/arm/mach-msm/platsmp.c | 6 +--
arch/arm/mach-msm/timer.c | 4 +-
arch/arm/mach-mvebu/coherency.c | 2 +-
arch/arm/mach-mvebu/headsmp.S | 2 -
arch/arm/mach-mvebu/platsmp.c | 5 +--
arch/arm/mach-omap2/omap-headsmp.S | 2 -
arch/arm/mach-omap2/omap-mpuss-lowpower.c | 2 +-
arch/arm/mach-omap2/omap-smp.c | 4 +-
arch/arm/mach-omap2/omap-wakeupgen.c | 4 +-
arch/arm/mach-prima2/headsmp.S | 2 -
arch/arm/mach-prima2/platsmp.c | 4 +-
arch/arm/mach-shmobile/headsmp-scu.S | 1 -
arch/arm/mach-shmobile/headsmp.S | 2 -
arch/arm/mach-shmobile/smp-emev2.c | 2 +-
arch/arm/mach-shmobile/smp-r8a7779.c | 2 +-
arch/arm/mach-shmobile/smp-sh73a0.c | 2 +-
arch/arm/mach-socfpga/headsmp.S | 1 -
arch/arm/mach-socfpga/platsmp.c | 2 +-
arch/arm/mach-spear/generic.h | 2 +-
arch/arm/mach-spear/platsmp.c | 4 +-
arch/arm/mach-tegra/platsmp.c | 4 +-
arch/arm/mach-tegra/pm.c | 2 +-
arch/arm/mach-ux500/platsmp.c | 4 +-
arch/arm/mach-zynq/common.h | 2 +-
arch/arm/mach-zynq/headsmp.S | 2 -
arch/arm/mach-zynq/platsmp.c | 6 +--
arch/arm/mm/proc-arm1020.S | 2 -
arch/arm/mm/proc-arm1020e.S | 2 -
arch/arm/mm/proc-arm1022.S | 2 -
arch/arm/mm/proc-arm1026.S | 3 --
arch/arm/mm/proc-arm720.S | 2 -
arch/arm/mm/proc-arm740.S | 2 -
arch/arm/mm/proc-arm7tdmi.S | 2 -
arch/arm/mm/proc-arm920.S | 2 -
arch/arm/mm/proc-arm922.S | 2 -
arch/arm/mm/proc-arm925.S | 2 -
arch/arm/mm/proc-arm926.S | 2 -
arch/arm/mm/proc-arm940.S | 2 -
arch/arm/mm/proc-arm946.S | 2 -
arch/arm/mm/proc-arm9tdmi.S | 2 -
arch/arm/mm/proc-fa526.S | 2 -
arch/arm/mm/proc-feroceon.S | 2 -
arch/arm/mm/proc-mohawk.S | 2 -
arch/arm/mm/proc-sa110.S | 2 -
arch/arm/mm/proc-sa1100.S | 2 -
arch/arm/mm/proc-v6.S | 2 -
arch/arm/mm/proc-v7-2level.S | 4 --
arch/arm/mm/proc-v7-3level.S | 4 --
arch/arm/mm/proc-v7.S | 2 -
arch/arm/mm/proc-xsc3.S | 2 -
arch/arm/mm/proc-xscale.S | 2 -
arch/arm/plat-versatile/platsmp.c | 6 +--
arch/arm64/include/asm/arch_timer.h | 2 +-
arch/arm64/kernel/debug-monitors.c | 6 +--
arch/arm64/kernel/hw_breakpoint.c | 4 +-
arch/arm64/kernel/smp.c | 8 ++--
arch/blackfin/kernel/perf_event.c | 2 +-
arch/blackfin/kernel/setup.c | 4 +-
arch/blackfin/mach-bf561/smp.c | 6 +--
arch/blackfin/mach-common/cache-c.c | 4 +-
arch/blackfin/mach-common/ints-priority.c | 2 +-
arch/blackfin/mach-common/smp.c | 8 ++--
arch/cris/arch-v32/kernel/smp.c | 2 +-
arch/frv/kernel/setup.c | 2 +-
arch/hexagon/kernel/setup.c | 2 +-
arch/hexagon/kernel/smp.c | 4 +-
arch/ia64/kernel/acpi.c | 4 +-
arch/ia64/kernel/err_inject.c | 8 ++--
arch/ia64/kernel/mca.c | 12 ++---
arch/ia64/kernel/numa.c | 4 +-
arch/ia64/kernel/palinfo.c | 4 +-
arch/ia64/kernel/salinfo.c | 4 +-
arch/ia64/kernel/setup.c | 10 ++---
arch/ia64/kernel/smpboot.c | 8 ++--
arch/ia64/kernel/topology.c | 18 ++++----
arch/ia64/mm/contig.c | 3 +-
arch/ia64/mm/discontig.c | 2 +-
arch/ia64/mm/numa.c | 2 +-
arch/ia64/sn/kernel/setup.c | 8 ++--
arch/ia64/xen/hypervisor.c | 2 +-
arch/m32r/kernel/smpboot.c | 2 +-
arch/metag/kernel/perf/perf_event.c | 6 +--
arch/metag/kernel/smp.c | 16 +++----
arch/metag/kernel/traps.c | 2 +-
arch/openrisc/kernel/setup.c | 2 +-
arch/parisc/kernel/firmware.c | 14 +++---
arch/parisc/kernel/hardware.c | 2 +-
arch/parisc/kernel/processor.c | 6 +--
arch/parisc/kernel/smp.c | 8 ++--
arch/powerpc/include/asm/rtas.h | 4 +-
arch/powerpc/include/asm/vdso.h | 2 +-
arch/powerpc/kernel/cacheinfo.c | 36 ++++++++-------
arch/powerpc/kernel/rtas.c | 4 +-
arch/powerpc/kernel/smp.c | 4 +-
arch/powerpc/kernel/sysfs.c | 6 +--
arch/powerpc/kernel/time.c | 1 -
arch/powerpc/kernel/vdso.c | 2 +-
arch/powerpc/mm/44x_mmu.c | 6 +--
arch/powerpc/mm/hash_utils_64.c | 2 +-
arch/powerpc/mm/mmu_context_nohash.c | 6 +--
arch/powerpc/mm/numa.c | 7 ++-
arch/powerpc/mm/tlb_nohash.c | 2 +-
arch/powerpc/perf/core-book3s.c | 4 +-
arch/powerpc/platforms/44x/currituck.c | 4 +-
arch/powerpc/platforms/44x/iss4xx.c | 4 +-
arch/powerpc/platforms/85xx/smp.c | 6 +--
arch/powerpc/platforms/powermac/smp.c | 2 +-
arch/powerpc/platforms/powernv/smp.c | 2 +-
arch/s390/kernel/cache.c | 15 +++----
arch/s390/kernel/perf_cpum_cf.c | 4 +-
arch/s390/kernel/processor.c | 2 +-
arch/s390/kernel/smp.c | 17 ++++---
arch/s390/kernel/sysinfo.c | 2 +-
arch/s390/kernel/vtime.c | 6 +--
arch/s390/mm/fault.c | 4 +-
arch/score/mm/tlb-score.c | 2 +-
arch/sh/kernel/cpu/init.c | 18 ++++----
arch/sh/kernel/cpu/sh2/probe.c | 2 +-
arch/sh/kernel/cpu/sh2a/probe.c | 2 +-
arch/sh/kernel/cpu/sh3/probe.c | 2 +-
arch/sh/kernel/cpu/sh4/probe.c | 2 +-
arch/sh/kernel/cpu/sh4a/smp-shx3.c | 6 +--
arch/sh/kernel/cpu/sh5/probe.c | 2 +-
arch/sh/kernel/perf_event.c | 4 +-
arch/sh/kernel/process.c | 2 +-
arch/sh/kernel/setup.c | 2 +-
arch/sh/kernel/smp.c | 8 ++--
arch/sh/kernel/traps_32.c | 2 +-
arch/sh/kernel/traps_64.c | 2 +-
arch/sh/mm/tlb-sh5.c | 2 +-
arch/sparc/kernel/ds.c | 11 ++---
arch/sparc/kernel/entry.h | 2 +-
arch/sparc/kernel/hvtramp.S | 1 -
arch/sparc/kernel/irq_64.c | 5 ++-
arch/sparc/kernel/leon_smp.c | 10 ++---
arch/sparc/kernel/mdesc.c | 34 +++++++-------
arch/sparc/kernel/smp_32.c | 20 ++++-----
arch/sparc/kernel/smp_64.c | 9 ++--
arch/sparc/kernel/sun4d_smp.c | 6 +--
arch/sparc/kernel/sun4m_smp.c | 6 +--
arch/sparc/kernel/sysfs.c | 4 +-
arch/sparc/kernel/trampoline_32.S | 3 --
arch/sparc/kernel/trampoline_64.S | 2 -
arch/sparc/mm/init_64.c | 2 +-
arch/sparc/mm/srmmu.c | 12 ++---
arch/tile/kernel/irq.c | 2 +-
arch/tile/kernel/messaging.c | 2 +-
arch/tile/kernel/setup.c | 12 ++---
arch/tile/kernel/smpboot.c | 8 ++--
arch/tile/kernel/time.c | 2 +-
arch/x86/include/asm/cpu.h | 2 +-
arch/x86/include/asm/microcode.h | 4 +-
arch/x86/include/asm/microcode_intel.h | 4 +-
arch/x86/include/asm/mmconfig.h | 4 +-
arch/x86/include/asm/mpspec.h | 2 +-
arch/x86/include/asm/numa.h | 6 +--
arch/x86/include/asm/prom.h | 2 +-
arch/x86/include/asm/smp.h | 2 +-
arch/x86/kernel/acpi/boot.c | 6 +--
arch/x86/kernel/apic/apic.c | 30 ++++++-------
arch/x86/kernel/apic/apic_numachip.c | 2 +-
arch/x86/kernel/apic/es7000_32.c | 2 +-
arch/x86/kernel/apic/numaq_32.c | 2 +-
arch/x86/kernel/apic/x2apic_cluster.c | 2 +-
arch/x86/kernel/apic/x2apic_uv_x.c | 14 +++---
arch/x86/kernel/cpu/amd.c | 33 +++++++-------
arch/x86/kernel/cpu/centaur.c | 26 +++++------
arch/x86/kernel/cpu/common.c | 64 +++++++++++++--------------
arch/x86/kernel/cpu/cyrix.c | 40 ++++++++---------
arch/x86/kernel/cpu/hypervisor.c | 2 +-
arch/x86/kernel/cpu/intel.c | 30 ++++++-------
arch/x86/kernel/cpu/intel_cacheinfo.c | 55 +++++++++++------------
arch/x86/kernel/cpu/mcheck/mce.c | 23 +++++-----
arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 +++---
arch/x86/kernel/cpu/mcheck/therm_throt.c | 9 ++--
arch/x86/kernel/cpu/perf_event.c | 2 +-
arch/x86/kernel/cpu/perf_event_amd_ibs.c | 2 +-
arch/x86/kernel/cpu/perf_event_amd_uncore.c | 31 +++++++------
arch/x86/kernel/cpu/perf_event_intel_uncore.c | 20 ++++-----
arch/x86/kernel/cpu/rdrand.c | 2 +-
arch/x86/kernel/cpu/scattered.c | 4 +-
arch/x86/kernel/cpu/topology.c | 2 +-
arch/x86/kernel/cpu/transmeta.c | 6 +--
arch/x86/kernel/cpu/umc.c | 2 +-
arch/x86/kernel/cpu/vmware.c | 2 +-
arch/x86/kernel/cpuid.c | 7 ++-
arch/x86/kernel/devicetree.c | 2 +-
arch/x86/kernel/head_32.S | 1 -
arch/x86/kernel/i387.c | 8 ++--
arch/x86/kernel/irq_32.c | 2 +-
arch/x86/kernel/kvm.c | 10 ++---
arch/x86/kernel/kvmclock.c | 2 +-
arch/x86/kernel/microcode_core.c | 2 +-
arch/x86/kernel/microcode_core_early.c | 6 +--
arch/x86/kernel/microcode_intel_early.c | 26 +++++------
arch/x86/kernel/mmconf-fam10h_64.c | 12 ++---
arch/x86/kernel/msr.c | 6 +--
arch/x86/kernel/process.c | 2 +-
arch/x86/kernel/setup.c | 2 +-
arch/x86/kernel/smpboot.c | 28 ++++++------
arch/x86/kernel/tboot.c | 6 +--
arch/x86/kernel/tsc.c | 4 +-
arch/x86/kernel/tsc_sync.c | 18 ++++----
arch/x86/kernel/vsyscall_64.c | 6 +--
arch/x86/kernel/x86_init.c | 4 +-
arch/x86/kernel/xsave.c | 4 +-
arch/x86/mm/mmio-mod.c | 4 +-
arch/x86/mm/numa.c | 12 ++---
arch/x86/mm/numa_emulation.c | 12 ++---
arch/x86/mm/setup_nx.c | 4 +-
arch/x86/pci/amd_bus.c | 8 ++--
arch/x86/platform/ce4100/ce4100.c | 2 +-
arch/x86/platform/mrst/mrst.c | 4 +-
arch/x86/xen/enlighten.c | 6 +--
arch/x86/xen/setup.c | 6 +--
arch/x86/xen/smp.c | 12 ++---
arch/x86/xen/spinlock.c | 2 +-
arch/x86/xen/xen-ops.h | 2 +-
arch/xtensa/kernel/time.c | 2 +-
block/blk-iopoll.c | 6 +--
block/blk-softirq.c | 6 +--
drivers/acpi/acpi_processor.c | 2 +-
drivers/acpi/processor_core.c | 8 ++--
drivers/acpi/processor_driver.c | 8 ++--
drivers/acpi/processor_idle.c | 6 +--
drivers/base/cpu.c | 2 +-
drivers/base/topology.c | 10 ++---
drivers/clocksource/arm_arch_timer.c | 8 ++--
drivers/clocksource/exynos_mct.c | 4 +-
drivers/clocksource/metag_generic.c | 6 +--
drivers/clocksource/time-armada-370-xp.c | 4 +-
drivers/clocksource/timer-marco.c | 4 +-
drivers/cpufreq/cpufreq.c | 4 +-
drivers/cpufreq/cpufreq_stats.c | 4 +-
drivers/cpufreq/dbx500-cpufreq.c | 2 +-
drivers/cpufreq/intel_pstate.c | 4 +-
drivers/cpufreq/longhaul.c | 6 +--
drivers/cpufreq/longhaul.h | 26 +++++------
drivers/cpufreq/longrun.c | 8 ++--
drivers/cpufreq/omap-cpufreq.c | 2 +-
drivers/cpufreq/powernow-k7.c | 8 ++--
drivers/cpufreq/powernow-k8.c | 6 +--
drivers/hwmon/coretemp.c | 39 ++++++++--------
drivers/hwmon/via-cputemp.c | 8 ++--
drivers/irqchip/irq-gic.c | 8 ++--
drivers/oprofile/timer_int.c | 4 +-
drivers/xen/xen-acpi-cpuhotplug.c | 2 +-
include/asm-generic/vmlinux.lds.h | 12 -----
include/linux/cpu.h | 2 +-
include/linux/init.h | 19 ++++----
include/linux/perf_event.h | 2 +-
init/calibrate.c | 13 +++---
kernel/cpu.c | 6 +--
kernel/events/core.c | 4 +-
kernel/fork.c | 2 +-
kernel/hrtimer.c | 6 +--
kernel/printk.c | 2 +-
kernel/profile.c | 2 +-
kernel/rcutorture.c | 6 +--
kernel/rcutree.c | 6 +--
kernel/rcutree.h | 4 +-
kernel/rcutree_plugin.h | 6 +--
kernel/relay.c | 2 +-
kernel/sched/core.c | 12 ++---
kernel/sched/fair.c | 2 +-
kernel/smp.c | 2 +-
kernel/smpboot.c | 2 +-
kernel/softirq.c | 8 ++--
kernel/time/tick-sched.c | 2 +-
kernel/timer.c | 10 ++---
kernel/workqueue.c | 4 +-
lib/Kconfig.debug | 2 +-
lib/earlycpio.c | 2 +-
lib/percpu_counter.c | 2 +-
mm/memcontrol.c | 2 +-
mm/page-writeback.c | 4 +-
mm/slab.c | 10 ++---
mm/slub.c | 4 +-
mm/vmstat.c | 6 +--
net/core/flow.c | 4 +-
net/iucv/iucv.c | 2 +-
scripts/mod/modpost.c | 52 ++++------------------
307 files changed, 896 insertions(+), 1037 deletions(-)
--
1.8.1.2
^ permalink raw reply
* [PATCH-next 00/32] Delete support for __cpuinit
From: Paul Gortmaker @ 2013-06-24 20:00 UTC (permalink / raw)
To: Paul Gortmaker
Cc: linux-m32r-ja, linux-s390, linux-m32r, linux-ia64, linux-parisc,
linux-cris-kernel, linux-pm, linux-sh, linux-hexagon,
linux-xtensa, linux390, linux-kernel, cpufreq, lm-sensors,
linux-acpi, netdev, sparclinux, uclinux-dist-devel, x86,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <1372102237-8757-1-git-send-email-paul.gortmaker@windriver.com>
[Resending with only lists on Cc: -- previous mail header on the 00/32
was too long; failed to get passed vger's crap filters.]
On 13-06-24 03:30 PM, Paul Gortmaker wrote:
> This is the whole patch queue for removal of __cpuinit support
> against the latest linux-next tree (Jun24th). Some of you may
> have already seen chunks of it, or already read the logistics
> of what is being done (and why) here:
>
> https://lkml.org/lkml/2013/6/20/513
>
> I won't repeat all that here again, other than to say this send
> is to ensure arch/subsystem maintainers get a 2nd chance to know
> what is going on and to look at what is being proposed for their
> area of code. That, and to ensure one complete continuous copy
> of it gets mailed out. You can also see the patch queue here:
>
> http://git.kernel.org/cgit/linux/kernel/git/paulg/cpuinit-delete.git
>
> If you've noticed that a chunk for MIPS isn't present here, that
> is because it has already been queued in the linux-mips for-next
> branch.
>
> Thanks,
> Paul.
>
> ---
> Cc: Len Brown <lenb@kernel.org>
> Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
> Cc: Richard Henderson <rth@twiddle.net>
> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
> Cc: Matt Turner <mattst88@gmail.com>
> Cc: Vineet Gupta <vgupta@synopsys.com>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Mike Frysinger <vapier@gentoo.org>
> Cc: Bob Liu <lliubbo@gmail.com>
> Cc: Sonic Zhang <sonic.zhang@analog.com>
> Cc: Jens Axboe <axboe@kernel.dk>
> Cc: John Stultz <john.stultz@linaro.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: "Rafael J. Wysocki" <rjw@sisk.pl>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Cc: Mikael Starvik <starvik@axis.com>
> Cc: Jesper Nilsson <jesper.nilsson@axis.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: David Howells <dhowells@redhat.com>
> Cc: Richard Kuo <rkuo@codeaurora.org>
> Cc: Fenghua Yu <fenghua.yu@intel.com>
> Cc: Tony Luck <tony.luck@intel.com>
> Cc: Fenghua Yu <fenghua.yu@intel.com>
> Cc: Hirokazu Takata <takata@linux-m32r.org>
> Cc: James Hogan <james.hogan@imgtec.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rusty Russell <rusty@rustcorp.com.au>
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Jonas Bonn <jonas@southpole.se>
> Cc: Helge Deller <deller@gmx.de>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Josh Boyer <jwboyer@gmail.com>
> Cc: Matt Porter <mporter@kernel.crashing.org>
> Cc: Kumar Gala <galak@kernel.crashing.org>
> Cc: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
> Cc: Josh Triplett <josh@freedesktop.org>
> Cc: Dipankar Sarma <dipankar@in.ibm.com>
> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
> Cc: Chen Liqin <liqin.chen@sunplusct.com>
> Cc: Lennox Wu <lennox.wu@gmail.com>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Chris Metcalf <cmetcalf@tilera.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: "H. Peter Anvin" <hpa@zytor.com>
> Cc: Chris Zankel <chris@zankel.net>
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> Cc: linux-acpi@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: uclinux-dist-devel@blackfin.uclinux.org
> Cc: cpufreq@vger.kernel.org
> Cc: linux-pm@vger.kernel.org
> Cc: linux-cris-kernel@axis.com
> Cc: linux-hexagon@vger.kernel.org
> Cc: lm-sensors@lm-sensors.org
> Cc: linux-ia64@vger.kernel.org
> Cc: linux-m32r@ml.linux-m32r.org
> Cc: linux-m32r-ja@ml.linux-m32r.org
> Cc: netdev@vger.kernel.org
> Cc: linux@lists.openrisc.net
> Cc: linux-parisc@vger.kernel.org
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux390@de.ibm.com
> Cc: linux-s390@vger.kernel.org
> Cc: linux-sh@vger.kernel.org
> Cc: sparclinux@vger.kernel.org
> Cc: x86@kernel.org
> Cc: linux-xtensa@linux-xtensa.org
>
> Paul Gortmaker (32):
> init.h: remove __cpuinit sections from the kernel
> modpost: remove all traces of cpuinit/cpuexit sections
> alpha: delete __cpuinit usage from all users
> powerpc: delete __cpuinit usage from all users
> parisc: delete __cpuinit usage from all users
> ia64: delete __cpuinit usage from all ia64 users
> arm: delete __cpuinit/__CPUINIT usage from all ARM users
> sparc: delete __cpuinit/__CPUINIT usage from all users
> arm64: delete __cpuinit usage from all users
> arc: delete __cpuinit usage from all arc files
> blackfin: delete __cpuinit usage from all blackfin files
> s390: delete __cpuinit usage from all s390 files
> sh: delete __cpuinit usage from all sh files
> tile: delete __cpuinit usage from all tile files
> metag: delete __cpuinit usage from all metag files
> cris: delete __cpuinit usage from all cris files
> frv: delete __cpuinit usage from all frv files
> hexagon: delete __cpuinit usage from all hexagon files
> m32r: delete __cpuinit usage from all m32r files
> openrisc: delete __cpuinit usage from all openrisc files
> xtensa: delete __cpuinit usage from all xtensa files
> score: delete __cpuinit usage from all score files
> x86: delete __cpuinit usage from all x86 files
> clocksource+irqchip: delete __cpuinit usage from all related files
> cpufreq: delete __cpuinit usage from all cpufreq files
> hwmon: delete __cpuinit usage from all hwmon files
> acpi: delete __cpuinit usage from all acpi files
> net: delete __cpuinit usage from all net files
> rcu: delete __cpuinit usage from all rcu files
> kernel: delete __cpuinit usage from all core kernel files
> drivers: delete __cpuinit usage from all remaining drivers files
> block: delete __cpuinit usage from all block files
>
> Documentation/cpu-hotplug.txt | 6 +--
> arch/alpha/kernel/smp.c | 10 ++---
> arch/alpha/kernel/traps.c | 4 +-
> arch/arc/include/asm/irq.h | 2 +-
> arch/arc/kernel/irq.c | 2 +-
> arch/arc/kernel/setup.c | 10 ++---
> arch/arc/kernel/smp.c | 4 +-
> arch/arc/kernel/time.c | 6 +--
> arch/arc/mm/cache_arc700.c | 4 +-
> arch/arc/mm/tlb.c | 4 +-
> arch/arm/common/mcpm_platsmp.c | 4 +-
> arch/arm/include/asm/arch_timer.h | 2 +-
> arch/arm/kernel/head-common.S | 1 -
> arch/arm/kernel/head.S | 1 -
> arch/arm/kernel/hw_breakpoint.c | 4 +-
> arch/arm/kernel/perf_event_cpu.c | 6 +--
> arch/arm/kernel/psci_smp.c | 3 +-
> arch/arm/kernel/smp.c | 18 ++++----
> arch/arm/kernel/smp_twd.c | 6 +--
> arch/arm/lib/delay.c | 2 +-
> arch/arm/mach-exynos/headsmp.S | 2 -
> arch/arm/mach-exynos/platsmp.c | 4 +-
> arch/arm/mach-highbank/platsmp.c | 2 +-
> arch/arm/mach-imx/platsmp.c | 2 +-
> arch/arm/mach-msm/headsmp.S | 2 -
> arch/arm/mach-msm/platsmp.c | 6 +--
> arch/arm/mach-msm/timer.c | 4 +-
> arch/arm/mach-mvebu/coherency.c | 2 +-
> arch/arm/mach-mvebu/headsmp.S | 2 -
> arch/arm/mach-mvebu/platsmp.c | 5 +--
> arch/arm/mach-omap2/omap-headsmp.S | 2 -
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 2 +-
> arch/arm/mach-omap2/omap-smp.c | 4 +-
> arch/arm/mach-omap2/omap-wakeupgen.c | 4 +-
> arch/arm/mach-prima2/headsmp.S | 2 -
> arch/arm/mach-prima2/platsmp.c | 4 +-
> arch/arm/mach-shmobile/headsmp-scu.S | 1 -
> arch/arm/mach-shmobile/headsmp.S | 2 -
> arch/arm/mach-shmobile/smp-emev2.c | 2 +-
> arch/arm/mach-shmobile/smp-r8a7779.c | 2 +-
> arch/arm/mach-shmobile/smp-sh73a0.c | 2 +-
> arch/arm/mach-socfpga/headsmp.S | 1 -
> arch/arm/mach-socfpga/platsmp.c | 2 +-
> arch/arm/mach-spear/generic.h | 2 +-
> arch/arm/mach-spear/platsmp.c | 4 +-
> arch/arm/mach-tegra/platsmp.c | 4 +-
> arch/arm/mach-tegra/pm.c | 2 +-
> arch/arm/mach-ux500/platsmp.c | 4 +-
> arch/arm/mach-zynq/common.h | 2 +-
> arch/arm/mach-zynq/headsmp.S | 2 -
> arch/arm/mach-zynq/platsmp.c | 6 +--
> arch/arm/mm/proc-arm1020.S | 2 -
> arch/arm/mm/proc-arm1020e.S | 2 -
> arch/arm/mm/proc-arm1022.S | 2 -
> arch/arm/mm/proc-arm1026.S | 3 --
> arch/arm/mm/proc-arm720.S | 2 -
> arch/arm/mm/proc-arm740.S | 2 -
> arch/arm/mm/proc-arm7tdmi.S | 2 -
> arch/arm/mm/proc-arm920.S | 2 -
> arch/arm/mm/proc-arm922.S | 2 -
> arch/arm/mm/proc-arm925.S | 2 -
> arch/arm/mm/proc-arm926.S | 2 -
> arch/arm/mm/proc-arm940.S | 2 -
> arch/arm/mm/proc-arm946.S | 2 -
> arch/arm/mm/proc-arm9tdmi.S | 2 -
> arch/arm/mm/proc-fa526.S | 2 -
> arch/arm/mm/proc-feroceon.S | 2 -
> arch/arm/mm/proc-mohawk.S | 2 -
> arch/arm/mm/proc-sa110.S | 2 -
> arch/arm/mm/proc-sa1100.S | 2 -
> arch/arm/mm/proc-v6.S | 2 -
> arch/arm/mm/proc-v7-2level.S | 4 --
> arch/arm/mm/proc-v7-3level.S | 4 --
> arch/arm/mm/proc-v7.S | 2 -
> arch/arm/mm/proc-xsc3.S | 2 -
> arch/arm/mm/proc-xscale.S | 2 -
> arch/arm/plat-versatile/platsmp.c | 6 +--
> arch/arm64/include/asm/arch_timer.h | 2 +-
> arch/arm64/kernel/debug-monitors.c | 6 +--
> arch/arm64/kernel/hw_breakpoint.c | 4 +-
> arch/arm64/kernel/smp.c | 8 ++--
> arch/blackfin/kernel/perf_event.c | 2 +-
> arch/blackfin/kernel/setup.c | 4 +-
> arch/blackfin/mach-bf561/smp.c | 6 +--
> arch/blackfin/mach-common/cache-c.c | 4 +-
> arch/blackfin/mach-common/ints-priority.c | 2 +-
> arch/blackfin/mach-common/smp.c | 8 ++--
> arch/cris/arch-v32/kernel/smp.c | 2 +-
> arch/frv/kernel/setup.c | 2 +-
> arch/hexagon/kernel/setup.c | 2 +-
> arch/hexagon/kernel/smp.c | 4 +-
> arch/ia64/kernel/acpi.c | 4 +-
> arch/ia64/kernel/err_inject.c | 8 ++--
> arch/ia64/kernel/mca.c | 12 ++---
> arch/ia64/kernel/numa.c | 4 +-
> arch/ia64/kernel/palinfo.c | 4 +-
> arch/ia64/kernel/salinfo.c | 4 +-
> arch/ia64/kernel/setup.c | 10 ++---
> arch/ia64/kernel/smpboot.c | 8 ++--
> arch/ia64/kernel/topology.c | 18 ++++----
> arch/ia64/mm/contig.c | 3 +-
> arch/ia64/mm/discontig.c | 2 +-
> arch/ia64/mm/numa.c | 2 +-
> arch/ia64/sn/kernel/setup.c | 8 ++--
> arch/ia64/xen/hypervisor.c | 2 +-
> arch/m32r/kernel/smpboot.c | 2 +-
> arch/metag/kernel/perf/perf_event.c | 6 +--
> arch/metag/kernel/smp.c | 16 +++----
> arch/metag/kernel/traps.c | 2 +-
> arch/openrisc/kernel/setup.c | 2 +-
> arch/parisc/kernel/firmware.c | 14 +++---
> arch/parisc/kernel/hardware.c | 2 +-
> arch/parisc/kernel/processor.c | 6 +--
> arch/parisc/kernel/smp.c | 8 ++--
> arch/powerpc/include/asm/rtas.h | 4 +-
> arch/powerpc/include/asm/vdso.h | 2 +-
> arch/powerpc/kernel/cacheinfo.c | 36 ++++++++-------
> arch/powerpc/kernel/rtas.c | 4 +-
> arch/powerpc/kernel/smp.c | 4 +-
> arch/powerpc/kernel/sysfs.c | 6 +--
> arch/powerpc/kernel/time.c | 1 -
> arch/powerpc/kernel/vdso.c | 2 +-
> arch/powerpc/mm/44x_mmu.c | 6 +--
> arch/powerpc/mm/hash_utils_64.c | 2 +-
> arch/powerpc/mm/mmu_context_nohash.c | 6 +--
> arch/powerpc/mm/numa.c | 7 ++-
> arch/powerpc/mm/tlb_nohash.c | 2 +-
> arch/powerpc/perf/core-book3s.c | 4 +-
> arch/powerpc/platforms/44x/currituck.c | 4 +-
> arch/powerpc/platforms/44x/iss4xx.c | 4 +-
> arch/powerpc/platforms/85xx/smp.c | 6 +--
> arch/powerpc/platforms/powermac/smp.c | 2 +-
> arch/powerpc/platforms/powernv/smp.c | 2 +-
> arch/s390/kernel/cache.c | 15 +++----
> arch/s390/kernel/perf_cpum_cf.c | 4 +-
> arch/s390/kernel/processor.c | 2 +-
> arch/s390/kernel/smp.c | 17 ++++---
> arch/s390/kernel/sysinfo.c | 2 +-
> arch/s390/kernel/vtime.c | 6 +--
> arch/s390/mm/fault.c | 4 +-
> arch/score/mm/tlb-score.c | 2 +-
> arch/sh/kernel/cpu/init.c | 18 ++++----
> arch/sh/kernel/cpu/sh2/probe.c | 2 +-
> arch/sh/kernel/cpu/sh2a/probe.c | 2 +-
> arch/sh/kernel/cpu/sh3/probe.c | 2 +-
> arch/sh/kernel/cpu/sh4/probe.c | 2 +-
> arch/sh/kernel/cpu/sh4a/smp-shx3.c | 6 +--
> arch/sh/kernel/cpu/sh5/probe.c | 2 +-
> arch/sh/kernel/perf_event.c | 4 +-
> arch/sh/kernel/process.c | 2 +-
> arch/sh/kernel/setup.c | 2 +-
> arch/sh/kernel/smp.c | 8 ++--
> arch/sh/kernel/traps_32.c | 2 +-
> arch/sh/kernel/traps_64.c | 2 +-
> arch/sh/mm/tlb-sh5.c | 2 +-
> arch/sparc/kernel/ds.c | 11 ++---
> arch/sparc/kernel/entry.h | 2 +-
> arch/sparc/kernel/hvtramp.S | 1 -
> arch/sparc/kernel/irq_64.c | 5 ++-
> arch/sparc/kernel/leon_smp.c | 10 ++---
> arch/sparc/kernel/mdesc.c | 34 +++++++-------
> arch/sparc/kernel/smp_32.c | 20 ++++-----
> arch/sparc/kernel/smp_64.c | 9 ++--
> arch/sparc/kernel/sun4d_smp.c | 6 +--
> arch/sparc/kernel/sun4m_smp.c | 6 +--
> arch/sparc/kernel/sysfs.c | 4 +-
> arch/sparc/kernel/trampoline_32.S | 3 --
> arch/sparc/kernel/trampoline_64.S | 2 -
> arch/sparc/mm/init_64.c | 2 +-
> arch/sparc/mm/srmmu.c | 12 ++---
> arch/tile/kernel/irq.c | 2 +-
> arch/tile/kernel/messaging.c | 2 +-
> arch/tile/kernel/setup.c | 12 ++---
> arch/tile/kernel/smpboot.c | 8 ++--
> arch/tile/kernel/time.c | 2 +-
> arch/x86/include/asm/cpu.h | 2 +-
> arch/x86/include/asm/microcode.h | 4 +-
> arch/x86/include/asm/microcode_intel.h | 4 +-
> arch/x86/include/asm/mmconfig.h | 4 +-
> arch/x86/include/asm/mpspec.h | 2 +-
> arch/x86/include/asm/numa.h | 6 +--
> arch/x86/include/asm/prom.h | 2 +-
> arch/x86/include/asm/smp.h | 2 +-
> arch/x86/kernel/acpi/boot.c | 6 +--
> arch/x86/kernel/apic/apic.c | 30 ++++++-------
> arch/x86/kernel/apic/apic_numachip.c | 2 +-
> arch/x86/kernel/apic/es7000_32.c | 2 +-
> arch/x86/kernel/apic/numaq_32.c | 2 +-
> arch/x86/kernel/apic/x2apic_cluster.c | 2 +-
> arch/x86/kernel/apic/x2apic_uv_x.c | 14 +++---
> arch/x86/kernel/cpu/amd.c | 33 +++++++-------
> arch/x86/kernel/cpu/centaur.c | 26 +++++------
> arch/x86/kernel/cpu/common.c | 64 +++++++++++++--------------
> arch/x86/kernel/cpu/cyrix.c | 40 ++++++++---------
> arch/x86/kernel/cpu/hypervisor.c | 2 +-
> arch/x86/kernel/cpu/intel.c | 30 ++++++-------
> arch/x86/kernel/cpu/intel_cacheinfo.c | 55 +++++++++++------------
> arch/x86/kernel/cpu/mcheck/mce.c | 23 +++++-----
> arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 +++---
> arch/x86/kernel/cpu/mcheck/therm_throt.c | 9 ++--
> arch/x86/kernel/cpu/perf_event.c | 2 +-
> arch/x86/kernel/cpu/perf_event_amd_ibs.c | 2 +-
> arch/x86/kernel/cpu/perf_event_amd_uncore.c | 31 +++++++------
> arch/x86/kernel/cpu/perf_event_intel_uncore.c | 20 ++++-----
> arch/x86/kernel/cpu/rdrand.c | 2 +-
> arch/x86/kernel/cpu/scattered.c | 4 +-
> arch/x86/kernel/cpu/topology.c | 2 +-
> arch/x86/kernel/cpu/transmeta.c | 6 +--
> arch/x86/kernel/cpu/umc.c | 2 +-
> arch/x86/kernel/cpu/vmware.c | 2 +-
> arch/x86/kernel/cpuid.c | 7 ++-
> arch/x86/kernel/devicetree.c | 2 +-
> arch/x86/kernel/head_32.S | 1 -
> arch/x86/kernel/i387.c | 8 ++--
> arch/x86/kernel/irq_32.c | 2 +-
> arch/x86/kernel/kvm.c | 10 ++---
> arch/x86/kernel/kvmclock.c | 2 +-
> arch/x86/kernel/microcode_core.c | 2 +-
> arch/x86/kernel/microcode_core_early.c | 6 +--
> arch/x86/kernel/microcode_intel_early.c | 26 +++++------
> arch/x86/kernel/mmconf-fam10h_64.c | 12 ++---
> arch/x86/kernel/msr.c | 6 +--
> arch/x86/kernel/process.c | 2 +-
> arch/x86/kernel/setup.c | 2 +-
> arch/x86/kernel/smpboot.c | 28 ++++++------
> arch/x86/kernel/tboot.c | 6 +--
> arch/x86/kernel/tsc.c | 4 +-
> arch/x86/kernel/tsc_sync.c | 18 ++++----
> arch/x86/kernel/vsyscall_64.c | 6 +--
> arch/x86/kernel/x86_init.c | 4 +-
> arch/x86/kernel/xsave.c | 4 +-
> arch/x86/mm/mmio-mod.c | 4 +-
> arch/x86/mm/numa.c | 12 ++---
> arch/x86/mm/numa_emulation.c | 12 ++---
> arch/x86/mm/setup_nx.c | 4 +-
> arch/x86/pci/amd_bus.c | 8 ++--
> arch/x86/platform/ce4100/ce4100.c | 2 +-
> arch/x86/platform/mrst/mrst.c | 4 +-
> arch/x86/xen/enlighten.c | 6 +--
> arch/x86/xen/setup.c | 6 +--
> arch/x86/xen/smp.c | 12 ++---
> arch/x86/xen/spinlock.c | 2 +-
> arch/x86/xen/xen-ops.h | 2 +-
> arch/xtensa/kernel/time.c | 2 +-
> block/blk-iopoll.c | 6 +--
> block/blk-softirq.c | 6 +--
> drivers/acpi/acpi_processor.c | 2 +-
> drivers/acpi/processor_core.c | 8 ++--
> drivers/acpi/processor_driver.c | 8 ++--
> drivers/acpi/processor_idle.c | 6 +--
> drivers/base/cpu.c | 2 +-
> drivers/base/topology.c | 10 ++---
> drivers/clocksource/arm_arch_timer.c | 8 ++--
> drivers/clocksource/exynos_mct.c | 4 +-
> drivers/clocksource/metag_generic.c | 6 +--
> drivers/clocksource/time-armada-370-xp.c | 4 +-
> drivers/clocksource/timer-marco.c | 4 +-
> drivers/cpufreq/cpufreq.c | 4 +-
> drivers/cpufreq/cpufreq_stats.c | 4 +-
> drivers/cpufreq/dbx500-cpufreq.c | 2 +-
> drivers/cpufreq/intel_pstate.c | 4 +-
> drivers/cpufreq/longhaul.c | 6 +--
> drivers/cpufreq/longhaul.h | 26 +++++------
> drivers/cpufreq/longrun.c | 8 ++--
> drivers/cpufreq/omap-cpufreq.c | 2 +-
> drivers/cpufreq/powernow-k7.c | 8 ++--
> drivers/cpufreq/powernow-k8.c | 6 +--
> drivers/hwmon/coretemp.c | 39 ++++++++--------
> drivers/hwmon/via-cputemp.c | 8 ++--
> drivers/irqchip/irq-gic.c | 8 ++--
> drivers/oprofile/timer_int.c | 4 +-
> drivers/xen/xen-acpi-cpuhotplug.c | 2 +-
> include/asm-generic/vmlinux.lds.h | 12 -----
> include/linux/cpu.h | 2 +-
> include/linux/init.h | 19 ++++----
> include/linux/perf_event.h | 2 +-
> init/calibrate.c | 13 +++---
> kernel/cpu.c | 6 +--
> kernel/events/core.c | 4 +-
> kernel/fork.c | 2 +-
> kernel/hrtimer.c | 6 +--
> kernel/printk.c | 2 +-
> kernel/profile.c | 2 +-
> kernel/rcutorture.c | 6 +--
> kernel/rcutree.c | 6 +--
> kernel/rcutree.h | 4 +-
> kernel/rcutree_plugin.h | 6 +--
> kernel/relay.c | 2 +-
> kernel/sched/core.c | 12 ++---
> kernel/sched/fair.c | 2 +-
> kernel/smp.c | 2 +-
> kernel/smpboot.c | 2 +-
> kernel/softirq.c | 8 ++--
> kernel/time/tick-sched.c | 2 +-
> kernel/timer.c | 10 ++---
> kernel/workqueue.c | 4 +-
> lib/Kconfig.debug | 2 +-
> lib/earlycpio.c | 2 +-
> lib/percpu_counter.c | 2 +-
> mm/memcontrol.c | 2 +-
> mm/page-writeback.c | 4 +-
> mm/slab.c | 10 ++---
> mm/slub.c | 4 +-
> mm/vmstat.c | 6 +--
> net/core/flow.c | 4 +-
> net/iucv/iucv.c | 2 +-
> scripts/mod/modpost.c | 52 ++++------------------
> 307 files changed, 896 insertions(+), 1037 deletions(-)
>
^ permalink raw reply
* Pull request: scottwood/linux.git for-3.10
From: Scott Wood @ 2013-06-24 22:02 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
This fixes a regression that causes 83xx to oops on boot if a
non-express PCI bus is present. It is the same patch as the last pull
request, but with the changelog reworded to be clearer that this is a
regression.
The following changes since commit 17858ca65eef148d335ffd4cfc09228a1c1cbfb5:
Merge tag 'please-pull-fixia64' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux (2013-06-18 06:29:19 -1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git for-3.10
for you to fetch changes up to b37e161388ac3980d5dfb73050e85874b84253eb:
powerpc/pci: Fix boot panic on mpc83xx (regression) (2013-06-24 16:54:09 -0500)
----------------------------------------------------------------
Rojhalat Ibrahim (1):
powerpc/pci: Fix boot panic on mpc83xx (regression)
arch/powerpc/sysdev/fsl_pci.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
^ permalink raw reply
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