* Re: [PATCH v2 2/2] perf tools: Make Power7 events available for perf
From: Vince Weaver @ 2013-06-25 16:46 UTC (permalink / raw)
To: Runzhen Wang
Cc: acme, vincent.weaver, Peter Zijlstra, linux-kernel,
Stephane Eranian, xiaoguangrong, paulus, sukadev, linuxppc-dev,
mingo
In-Reply-To: <1372170933-4538-3-git-send-email-runzhen@linux.vnet.ibm.com>
On Tue, 25 Jun 2013, Runzhen Wang wrote:
> This patch makes all the POWER7 events available in sysfs.
>
> ...
>
> $ size arch/powerpc/perf/power7-pmu.o
> text data bss dec hex filename
> 3073 2720 0 5793 16a1 arch/powerpc/perf/power7-pmu.o
>
> and after the patch is applied, it is:
>
> $ size arch/powerpc/perf/power7-pmu.o
> text data bss dec hex filename
> 15950 31112 0 47062 b7d6 arch/powerpc/perf/power7-pmu.o
So if I'm reading this right, there's 45k of overhead for just one cpu
type?
What happens if we do this on x86?
If we have similar for p6/p4/core2/nehalem/ivb/snb/amd10h/amd15h/amd16h/knb
that's 450k of event defintions in the kernel. And may I remind everyone
that you can't compile perf_event support as a module, nor can you
unconfigure it on x86 (it's always built in, no option to disable).
I'd like to repeat my unpopular position that we just link perf against
libpfm4 and keep event tables in userspace where they belong.
Vince
^ permalink raw reply
* Re: [PATCH 3/3] powerpc/pseries: Support compression of oops text via pstore
From: Kees Cook @ 2013-06-25 16:55 UTC (permalink / raw)
To: Aruna Balakrishnaiah
Cc: jkenisto, Tony Luck, mahesh, Colin Cross, LKML, linuxppc-dev,
paulus, Anton Blanchard, Anton Vorontsov
In-Reply-To: <51C94101.3030702@linux.vnet.ibm.com>
On Tue, Jun 25, 2013 at 12:04 AM, Aruna Balakrishnaiah
<aruna@linux.vnet.ibm.com> wrote:
> Hi Kees,
>
>
> On Monday 24 June 2013 11:27 PM, Kees Cook wrote:
>>
>> On Sun, Jun 23, 2013 at 11:23 PM, Aruna Balakrishnaiah
>> <aruna@linux.vnet.ibm.com> wrote:
>>>
>>> The patch set supports compression of oops messages while writing to
>>> NVRAM,
>>> this helps in capturing more of oops data to lnx,oops-log. The pstore
>>> file
>>> for oops messages will be in decompressed format making it readable.
>>>
>>> In case compression fails, the patch takes care of copying the header
>>> added
>>> by pstore and last oops_data_sz bytes of big_oops_buf to NVRAM so that we
>>> have recent oops messages in lnx,oops-log.
>>>
>>> In case decompression fails, it will result in absence of oops file but
>>> still
>>> have files (in /dev/pstore) for other partitions.
>>>
>>> Signed-off-by: Aruna Balakrishnaiah <aruna@linux.vnet.ibm.com>
>>> ---
>>> arch/powerpc/platforms/pseries/nvram.c | 132
>>> +++++++++++++++++++++++++++++---
>>> 1 file changed, 118 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/arch/powerpc/platforms/pseries/nvram.c
>>> b/arch/powerpc/platforms/pseries/nvram.c
>>> index 0159d74..b5ba5e2 100644
>>> --- a/arch/powerpc/platforms/pseries/nvram.c
>>> +++ b/arch/powerpc/platforms/pseries/nvram.c
>>> @@ -539,6 +539,65 @@ static int zip_oops(size_t text_len)
>>> }
>>>
>>> #ifdef CONFIG_PSTORE
>>> +/* Derived from logfs_uncompress */
>>> +int nvram_decompress(void *in, void *out, size_t inlen, size_t outlen)
>>> +{
>>> + int err, ret;
>>> +
>>> + ret = -EIO;
>>> + err = zlib_inflateInit(&stream);
>>> + if (err != Z_OK)
>>> + goto error;
>>> +
>>> + stream.next_in = in;
>>> + stream.avail_in = inlen;
>>> + stream.total_in = 0;
>>> + stream.next_out = out;
>>> + stream.avail_out = outlen;
>>> + stream.total_out = 0;
>>> +
>>> + err = zlib_inflate(&stream, Z_FINISH);
>>> + if (err != Z_STREAM_END)
>>> + goto error;
>>> +
>>> + err = zlib_inflateEnd(&stream);
>>> + if (err != Z_OK)
>>> + goto error;
>>> +
>>> + ret = stream.total_out;
>>> +error:
>>> + return ret;
>>> +}
>>> +
>>> +static int unzip_oops(char *oops_buf, char *big_buf)
>>> +{
>>> + struct oops_log_info *oops_hdr = (struct oops_log_info
>>> *)oops_buf;
>>> + u64 timestamp = oops_hdr->timestamp;
>>> + char *big_oops_data = NULL;
>>> + char *oops_data_buf = NULL;
>>> + size_t big_oops_data_sz;
>>> + int unzipped_len;
>>> +
>>> + big_oops_data = big_buf + sizeof(struct oops_log_info);
>>> + big_oops_data_sz = big_oops_buf_sz - sizeof(struct
>>> oops_log_info);
>>> + oops_data_buf = oops_buf + sizeof(struct oops_log_info);
>>> +
>>> + unzipped_len = nvram_decompress(oops_data_buf, big_oops_data,
>>> + oops_hdr->report_length,
>>> + big_oops_data_sz);
>>> +
>>> + if (unzipped_len < 0) {
>>> + pr_err("nvram: decompression failed; returned %d\n",
>>> +
>>> unzipped_len);
>>> + return -1;
>>> + }
>>> + oops_hdr = (struct oops_log_info *)big_buf;
>>> + oops_hdr->version = OOPS_HDR_VERSION;
>>> + oops_hdr->report_length = (u16) unzipped_len;
>>> + oops_hdr->timestamp = timestamp;
>>> + return 0;
>>> +}
>>> +
>>> static int nvram_pstore_open(struct pstore_info *psi)
>>> {
>>> /* Reset the iterator to start reading partitions again */
>>> @@ -567,6 +626,7 @@ static int nvram_pstore_write(enum pstore_type_id
>>> type,
>>> size_t size, struct pstore_info *psi)
>>> {
>>> int rc;
>>> + unsigned int err_type = ERR_TYPE_KERNEL_PANIC;
>>> struct oops_log_info *oops_hdr = (struct oops_log_info *)
>>> oops_buf;
>>>
>>> /* part 1 has the recent messages from printk buffer */
>>> @@ -577,8 +637,31 @@ static int nvram_pstore_write(enum pstore_type_id
>>> type,
>>> oops_hdr->version = OOPS_HDR_VERSION;
>>> oops_hdr->report_length = (u16) size;
>>> oops_hdr->timestamp = get_seconds();
>>> +
>>> + if (big_oops_buf) {
>>> + rc = zip_oops(size);
>>> + /*
>>> + * If compression fails copy recent log messages from
>>> + * big_oops_buf to oops_data.
>>> + */
>>> + if (rc != 0) {
>>> + int hsize = pstore_get_header_size();
>>
>> I think I would rather see the API to pstore_write() changed to
>> include explicit details about header sizes. Mkaing hsize a global
>> seems unwise, since it's not strictly going to be a constant value. It
>> could change between calls to the writer, for example.
>
>
> Introducing headersize in pstore_write() API would need changes at
> multiple places whereits being called. The idea is to move the
> compression support to pstore infrastructure so that other platforms
> could also make use of it. Once the compression support gets in,
> header size argument in pstore_write() will have to be deprecated.
>
> Till the time compression support for pstore goes in, can't we call
> pstore_header_size before every write call to knowthe header size.
I think it would be cleaner for it to be passed as part of the
pstore_write function. It does mean touching all the other callers,
but using a global variable for this is just wrong, IMO. :)
It would be a progression, at some point in the future, the
pstore_write function could lose the header size argument when it was
the right time.
-Kees
>
>> Beyond that, this all seems sensible, though it would be kind of cool
>> to move this compression logic into the pstore core so it would get
>> used by default (or through a module parameter).
>> -Kees
>>
>>> + size_t diff = size - oops_data_sz + hsize;
>>> +
>>> + if (size > oops_data_sz) {
>>> + memcpy(oops_data, big_oops_buf, hsize);
>>> + memcpy(oops_data + hsize, big_oops_buf +
>>> diff,
>>> + oops_data_sz - hsize);
>>> +
>>> + oops_hdr->report_length = (u16)
>>> oops_data_sz;
>>> + } else
>>> + memcpy(oops_data, big_oops_buf, size);
>>> + } else
>>> + err_type = ERR_TYPE_KERNEL_PANIC_GZ;
>>> + }
>>> +
>>> rc = nvram_write_os_partition(&oops_log_partition, oops_buf,
>>> - (int) (sizeof(*oops_hdr) + size), ERR_TYPE_KERNEL_PANIC,
>>> + (int) (sizeof(*oops_hdr) + oops_hdr->report_length),
>>> err_type,
>>> count);
>>>
>>> if (rc != 0)
>>> @@ -600,10 +683,11 @@ static ssize_t nvram_pstore_read(u64 *id, enum
>>> pstore_type_id *type,
>>> struct oops_log_info *oops_hdr;
>>> unsigned int err_type, id_no, size = 0;
>>> struct nvram_os_partition *part = NULL;
>>> - char *buff = NULL;
>>> - int sig = 0;
>>> + char *buff = NULL, *big_buff = NULL;
>>> + int rc, sig = 0;
>>> loff_t p;
>>>
>>> +read_partition:
>>> read_type++;
>>>
>>> switch (nvram_type_ids[read_type]) {
>>> @@ -666,6 +750,25 @@ static ssize_t nvram_pstore_read(u64 *id, enum
>>> pstore_type_id *type,
>>> if (nvram_type_ids[read_type] == PSTORE_TYPE_DMESG) {
>>> oops_hdr = (struct oops_log_info *)buff;
>>> *buf = buff + sizeof(*oops_hdr);
>>> +
>>> + if (err_type == ERR_TYPE_KERNEL_PANIC_GZ) {
>>> + big_buff = kmalloc(big_oops_buf_sz, GFP_KERNEL);
>>> + if (!big_buff)
>>> + return -ENOMEM;
>>> +
>>> + rc = unzip_oops(buff, big_buff);
>>> +
>>> + if (rc != 0) {
>>> + kfree(buff);
>>> + kfree(big_buff);
>>> + goto read_partition;
>>> + }
>>> +
>>> + oops_hdr = (struct oops_log_info *)big_buff;
>>> + *buf = big_buff + sizeof(*oops_hdr);
>>> + kfree(buff);
>>> + }
>>> +
>>> time->tv_sec = oops_hdr->timestamp;
>>> time->tv_nsec = 0;
>>> return oops_hdr->report_length;
>>> @@ -687,17 +790,18 @@ static int nvram_pstore_init(void)
>>> {
>>> int rc = 0;
>>>
>>> - nvram_pstore_info.buf = oops_data;
>>> - nvram_pstore_info.bufsize = oops_data_sz;
>>> + if (big_oops_buf) {
>>> + nvram_pstore_info.buf = big_oops_buf;
>>> + nvram_pstore_info.bufsize = big_oops_buf_sz;
>>> + } else {
>>> + nvram_pstore_info.buf = oops_data;
>>> + nvram_pstore_info.bufsize = oops_data_sz;
>>> + }
>>>
>>> rc = pstore_register(&nvram_pstore_info);
>>> if (rc != 0)
>>> pr_err("nvram: pstore_register() failed, defaults to "
>>> "kmsg_dump; returned %d\n", rc);
>>> - else
>>> - /*TODO: Support compression when pstore is configured */
>>> - pr_info("nvram: Compression of oops text supported only
>>> when "
>>> - "pstore is not configured");
>>>
>>> return rc;
>>> }
>>> @@ -731,11 +835,6 @@ static void __init nvram_init_oops_partition(int
>>> rtas_partition_exists)
>>> oops_data = oops_buf + sizeof(struct oops_log_info);
>>> oops_data_sz = oops_log_partition.size - sizeof(struct
>>> oops_log_info);
>>>
>>> - rc = nvram_pstore_init();
>>> -
>>> - if (!rc)
>>> - return;
>>> -
>>> /*
>>> * Figure compression (preceded by elimination of each line's
>>> <n>
>>> * severity prefix) will reduce the oops/panic report to at most
>>> @@ -759,6 +858,11 @@ static void __init nvram_init_oops_partition(int
>>> rtas_partition_exists)
>>> stream.workspace = NULL;
>>> }
>>>
>>> + rc = nvram_pstore_init();
>>> +
>>> + if (!rc)
>>> + return;
>>> +
>>> rc = kmsg_dump_register(&nvram_kmsg_dumper);
>>> if (rc != 0) {
>>> pr_err("nvram: kmsg_dump_register() failed; returned
>>> %d\n", rc);
>>>
>>
>>
>> --
>> Kees Cook
>> Chrome OS Security
>> _______________________________________________
>> Linuxppc-dev mailing list
>> Linuxppc-dev@lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>>
>
--
Kees Cook
Chrome OS Security
^ permalink raw reply
* [PATCH] Fix string emulation for 32-bit process on ppc64
From: James Yang @ 2013-06-25 16:41 UTC (permalink / raw)
To: benh, galak, Scott Wood; +Cc: linuxppc-dev
String instruction emulation would erroneously result in a segfault if
the upper bits of the EA are set and is so high that it fails access
check. Truncate the EA to 32 bits if the process is 32-bit.
Signed-off-by: James Yang <James.Yang@freescale.com>
---
arch/powerpc/kernel/traps.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index dce1bea..c72e7e9 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -840,6 +840,10 @@ static int emulate_string_inst(struct pt_regs *regs, u32 instword)
u8 val;
u32 shift = 8 * (3 - (pos & 0x3));
+ /* if process is 32-bit, clear upper 32 bits of EA */
+ if ((regs->msr & MSR_64BIT) == 0)
+ EA &= 0xFFFFFFFF;
+
switch ((instword & PPC_INST_STRING_MASK)) {
case PPC_INST_LSWX:
case PPC_INST_LSWI:
--
1.7.0.4
^ permalink raw reply related
* Re: Regression in RCU subsystem in latest mainline kernel
From: Paul E. McKenney @ 2013-06-25 16:03 UTC (permalink / raw)
To: Michael Ellerman
Cc: Rojhalat Ibrahim, linuxppc-dev, linux-kernel, Steven Rostedt
In-Reply-To: <20130625074422.GB29957@concordia>
On Tue, Jun 25, 2013 at 05:44:23PM +1000, Michael Ellerman wrote:
> On Tue, Jun 25, 2013 at 05:19:14PM +1000, Michael Ellerman wrote:
> >
> > Here's another trace from 3.10-rc7 plus a few local patches.
>
> And here's another with CONFIG_RCU_CPU_STALL_INFO=y in case that's useful:
>
> PASS running test_pmc5_6_overuse()
> INFO: rcu_sched self-detected stall on CPU
> 8: (1 GPs behind) idle=8eb/140000000000002/0 softirq=215/220
So this CPU has been out of action since before the beginning of the
current grace period ("1 GPs behind"). It is not idle, having taken
a pair of nested interrupts from process context (matching the stack
below). This CPU has take five softirqs since the last grace period
that it noticed, which makes it likely that the loop is within the
softirq handler.
> (t=2100 jiffies g=18446744073709551583 c=18446744073709551582 q=13)
Assuming HZ=100, this stall has been going on for 21 seconds. There
is a grace period in progress according to RCU's global state (which
this CPU is not yet aware of). There are a total of 13 RCU callbacks
queued across the entire system.
If the system is at all responsive, I suggest using ftrace (either from
the boot command line or at runtime) to trace __do_softirq() and
hrtimer_interrupt().
Thanx, Paul
> cpu 0x8: Vector: 0 at [c0000003ea03eae0]
> pc: c00000000011d9b0: .rcu_check_callbacks+0x450/0x910
> lr: c00000000011d9b0: .rcu_check_callbacks+0x450/0x910
> sp: c0000003ea03ec40
> msr: 9000000000009032
> current = 0xc0000003ebf9f4a0
> paca = 0xc00000000fdc2400 softe: 0 irq_happened: 0x00
> pid = 2444, comm = power8-events
> enter ? for help
> [c0000003ea03ed70] c000000000094cd0 .update_process_times+0x40/0x90
> [c0000003ea03ee00] c0000000000df050 .tick_sched_handle.isra.13+0x20/0xa0
> [c0000003ea03ee80] c0000000000df2bc .tick_sched_timer+0x5c/0xa0
> [c0000003ea03ef20] c0000000000b3728 .__run_hrtimer+0x98/0x260
> [c0000003ea03efc0] c0000000000b4738 .hrtimer_interrupt+0x138/0x3c0
> [c0000003ea03f0d0] c00000000001cd34 .timer_interrupt+0x124/0x2f0
> [c0000003ea03f180] c00000000000a4f4 restore_check_irq_replay+0x68/0xa8
> --- Exception: 901 (Decrementer) at c000000000093ad4 .run_timer_softirq+0x74/0x360
> [c0000003ea03f580] c000000000089ac4 .__do_softirq+0x174/0x350
> [c0000003ea03f6a0] c000000000089ea8 .irq_exit+0xb8/0x100
> [c0000003ea03f720] c00000000001cd68 .timer_interrupt+0x158/0x2f0
> [c0000003ea03f7d0] c00000000000a4f4 restore_check_irq_replay+0x68/0xa8
> --- Exception: 901 (Decrementer) at c00000000014a520 .task_function_call+0x60/0x70
> [c0000003ea03fac0] c00000000014a634 .perf_event_enable+0x104/0x1c0 (unreliable)
> [c0000003ea03fb70] c0000000001495ec .perf_event_for_each_child+0x5c/0xf0
> [c0000003ea03fc00] c00000000014cd78 .perf_ioctl+0x108/0x400
> [c0000003ea03fca0] c0000000001d9aa0 .do_vfs_ioctl+0xb0/0x740
> [c0000003ea03fd80] c0000000001da188 .SyS_ioctl+0x58/0xb0
> [c0000003ea03fe30] c000000000009d54 syscall_exit+0x0/0x98
> --- Exception: c01 (System Call) at 00001fffffee03d0
> SP (3ffff5e7cc90) is in userspace
>
>
> cheers
>
^ permalink raw reply
* RE: [PATCH 3/3] powerpc/pseries: Support compression of oops text via pstore
From: Luck, Tony @ 2013-06-25 16:02 UTC (permalink / raw)
To: Aruna Balakrishnaiah, Kees Cook
Cc: jkenisto@linux.vnet.ibm.com, mahesh@linux.vnet.ibm.com,
Colin Cross, LKML, linuxppc-dev@ozlabs.org, paulus@samba.org,
Anton Blanchard, Anton Vorontsov
In-Reply-To: <51C94101.3030702@linux.vnet.ibm.com>
> Introducing headersize in pstore_write() API would need changes at
> multiple places whereits being called. The idea is to move the
> compression support to pstore infrastructure so that other platforms
> could also make use of it.
Any thoughts on the back/forward compatibility as we switch to compressed
pstore data? E.g. imagine I have a system installed with some Linux distr=
ibution
with a kernel too old to know about compressed pstore. I use that machine t=
o
run the latest kernels that do compression ... and one fine day one of them=
crashes
hard - logging in compressed form to pstore. Now I boot my distro kernel to=
pick
up the pieces ... what do I see in /sys/fs/pstore/*? Some compressed files?=
Can I
read them with some tool?
This somewhat of a corner case - but not completely unrealistic ... I'd at =
least
like to be reassured that the old kernel won't choke when it sees the compr=
essed
blobs.
-Tony
^ permalink raw reply
* kexec hangs on P2020
From: Stefani Seibold @ 2013-06-25 15:31 UTC (permalink / raw)
To: linuxppc-dev
Hi,
i have tried to kexec a 32 bit kernel on a Freescale P2020 dual core CPU
(e500v2, revison 5.1 - pvr 8021 1051), but Kexec will hang.
The host and the kexec kernel are 3.9.4, but i have cross checked with
the current 3.10 kernel, there is no notable change in this code path.
Invoking kexec with
kexec --command-line "$(cat /proc/cmdline)" -t elf-ppc --dtb=rs2020.dtb \
--reuse-node="/cpus/PowerPC,P2020@0/timebase-frequency" \
--reuse-node="/cpus/PowerPC,P2020@0/bus-frequency" \
--reuse-node="/cpus/PowerPC,P2020@0/clock-frequency" \
--reuse-node="/cpus/PowerPC,P2020@0/next-level-cache" \
--reuse-node="/cpus/PowerPC,P2020@1/timebase-frequency" \
--reuse-node="/cpus/PowerPC,P2020@1/bus-frequency" \
--reuse-node="/cpus/PowerPC,P2020@1/clock-frequency" \
--reuse-node="/cpus/PowerPC,P2020@1/next-level-cache" \
--reuse-node="/cpus/PowerPC,P2020@1/cpu-release-addr" \
--reuse-node="/cpus/PowerPC,P2020@1/enable-method" \
--reuse-node="/soc@ffe00000/bus-frequency" \
--reuse-node="/soc@ffe00000/serial@4500/clock-frequency" \
--reuse-node="/soc@ffe00000/ethernet@24000/local-mac-address" \
-d -l -x vmlinux
kexec -e
This will be the result output of the run:
kernel: 0x48032008 kernel_size: 4fde98
0000000000000000-0000000080000000 : 0
get base memory ranges:1
nr_segments = 0
nr_segments = 0
nr_segments = 1
segment[0].buf = 0x48042008
segment[0].bufsz = 4ed620
segment[0].mem = (nil)
segment[0].memsz = 518000
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 518012
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 51801a
sym: sha256_starts info: 12 other: 00 shndx: 1 value: 99c size: e0
sym: sha256_starts value: 51899c addr: 518024
sym: sha256_update info: 12 other: 00 shndx: 1 value: 565c size: 1b0
sym: sha256_update value: 51d65c addr: 518038
sym: sha256_finish info: 12 other: 00 shndx: 1 value: 580c size: 528
sym: sha256_finish value: 51d80c addr: 518050
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 518056
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 51805a
sym: memcmp info: 12 other: 00 shndx: 1 value: 664 size: 40
sym: memcmp value: 518664 addr: 518068
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd34 addr: 51807a
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd64 addr: 51807e
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd34 addr: 518082
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 51808c
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd54 addr: 518092
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd54 addr: 518096
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 51809c
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd64 addr: 5180a6
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 5180b4
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd6c addr: 5180c2
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 5180c6
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd6c addr: 5180ca
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dda8 addr: 5180ce
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 5180d4
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd70 addr: 5180da
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd70 addr: 5180de
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 5180e8
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 5180fc
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd6c addr: 51810a
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd6c addr: 51810e
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 518114
sym: _rest32gpr_29_x info: 12 other: 00 shndx: 1 value: 8fc size: 0
sym: _rest32gpr_29_x value: 5188fc addr: 518124
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd80 addr: 51812e
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd80 addr: 518136
sym: printf info: 12 other: 00 shndx: 1 value: 55c size: 68
sym: printf value: 51855c addr: 518140
sym: setup_arch info: 12 other: 00 shndx: 1 value: 98c size: 4
sym: setup_arch value: 51898c addr: 518144
sym: verify_sha256_digest info: 12 other: 00 shndx: 1 value: 0 size: 128
sym: verify_sha256_digest value: 518000 addr: 518148
sym: post_verification_setup_arch info: 12 other: 00 shndx: 1 value: 990 size: 4
sym: post_verification_setup_arch value: 518990 addr: 518158
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd94 addr: 51817a
sym: .rodata.str1.4 info: 03 other: 00 shndx: 3 value: 0 size: 0
sym: .rodata.str1.4 value: 51dd94 addr: 518196
sym: putchar info: 12 other: 00 shndx: 1 value: 998 size: 4
sym: putchar value: 518998 addr: 5181b8
sym: putchar info: 12 other: 00 shndx: 1 value: 998 size: 4
sym: putchar value: 518998 addr: 51821c
sym: __lshrdi3 info: 10 other: 00 shndx: 1 value: 968 size: 0
sym: __lshrdi3 value: 518968 addr: 51833c
sym: putchar info: 12 other: 00 shndx: 1 value: 998 size: 4
sym: putchar value: 518998 addr: 5184cc
sym: _rest32gpr_21_x info: 12 other: 00 shndx: 1 value: 8dc size: 0
sym: _rest32gpr_21_x value: 5188dc addr: 5184fc
sym: vsprintf info: 12 other: 00 shndx: 1 value: 16c size: 394
sym: vsprintf value: 51816c addr: 518548
sym: vsprintf info: 12 other: 00 shndx: 1 value: 16c size: 394
sym: vsprintf value: 51816c addr: 5185b0
sym: my_thread_ptr info: 11 other: 00 shndx: 5 value: 10 size: 4
sym: my_thread_ptr value: 51df18 addr: 5187b6
sym: my_thread_ptr info: 11 other: 00 shndx: 5 value: 10 size: 4
sym: my_thread_ptr value: 51df18 addr: 5187ba
sym: stack info: 11 other: 00 shndx: 5 value: 8 size: 4
sym: stack value: 51df10 addr: 5187c2
sym: stack info: 11 other: 00 shndx: 5 value: 8 size: 4
sym: stack value: 51df10 addr: 5187c6
sym: purgatory info: 12 other: 00 shndx: 1 value: 128 size: 44
sym: purgatory value: 518128 addr: 5187d0
sym: dt_offset info: 11 other: 00 shndx: 5 value: c size: 4
sym: dt_offset value: 51df14 addr: 5187ea
sym: dt_offset info: 11 other: 00 shndx: 5 value: c size: 4
sym: dt_offset value: 51df14 addr: 5187ee
sym: kernel info: 11 other: 00 shndx: 5 value: 14 size: 4
sym: kernel value: 51df1c addr: 518806
sym: kernel info: 11 other: 00 shndx: 5 value: 14 size: 4
sym: kernel value: 51df1c addr: 51880a
sym: memcpy info: 12 other: 00 shndx: 1 value: 630 size: 34
sym: memcpy value: 518630 addr: 51d74c
sym: sha256_process info: 12 other: 00 shndx: 1 value: a7c size: 4be0
sym: sha256_process value: 518a7c addr: 51d760
sym: sha256_process info: 12 other: 00 shndx: 1 value: a7c size: 4be0
sym: sha256_process value: 518a7c addr: 51d798
sym: memcpy info: 12 other: 00 shndx: 1 value: 630 size: 34
sym: memcpy value: 518630 addr: 51d7e8
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dec8 addr: 51d91a
sym: .data info: 03 other: 00 shndx: 4 value: 0 size: 0
sym: .data value: 51dec8 addr: 51d91e
sym: sha256_update info: 12 other: 00 shndx: 1 value: 565c size: 1b0
sym: sha256_update value: 51d65c addr: 51d924
sym: sha256_update info: 12 other: 00 shndx: 1 value: 565c size: 1b0
sym: sha256_update value: 51d65c addr: 51d938
reserve regions: 1
0: offset: 17fd000, size: 3000
debug.dtb written
kexec_load: entry = 0x5186a4 flags = 0
nr_segments = 3
segment[0].buf = 0x48042008
segment[0].bufsz = 4ed620
segment[0].mem = (nil)
segment[0].memsz = 518000
segment[1].buf = 0x1007b2e0
segment[1].bufsz = 5f20
segment[1].mem = 0x518000
segment[1].memsz = 6000
segment[2].buf = 0x10081268
segment[2].bufsz = 25da
segment[2].mem = 0x17fd000
segment[2].memsz = 3000
[ 273.189790] sd 0:0:0:0: [sda] Synchronizing SCSI cache
[ 273.266505] xhci_hcd 0001:03:00.0: Host not halted after 16000 microseconds.
[ 273.273681] Starting new kernel
[ 273.280271] Bye!
The same is still working on a Freescale 834x PowerPC CPU and the output
of kexec looks similary.
This is a extract of my kernel .config
#
# Processor support
#
# CONFIG_PPC_BOOK3S_32 is not set
CONFIG_PPC_85xx=y
# CONFIG_PPC_8xx is not set
# CONFIG_40x is not set
# CONFIG_44x is not set
# CONFIG_E200 is not set
CONFIG_E500=y
# CONFIG_PPC_E500MC is not set
CONFIG_FSL_EMB_PERFMON=y
CONFIG_BOOKE=y
CONFIG_FSL_BOOKE=y
CONFIG_PPC_FSL_BOOK3E=y
# CONFIG_PHYS_64BIT is not set
CONFIG_SPE=y
CONFIG_PPC_MMU_NOHASH=y
CONFIG_PPC_BOOK3E_MMU=y
# CONFIG_PPC_MM_SLICES is not set
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_PPC32=y
CONFIG_32BIT=y
CONFIG_WORD_SIZE=32
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
CONFIG_NR_IRQS=512
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_GENERIC_LOCKBREAK=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_GPIO=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_PPC_UDBG_16550=y
CONFIG_GENERIC_TBSYNC=y
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
# CONFIG_EPAPR_BOOT is not set
CONFIG_DEFAULT_UIMAGE=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_PPC_ADV_DEBUG_REGS=y
CONFIG_PPC_ADV_DEBUG_IACS=2
CONFIG_PPC_ADV_DEBUG_DACS=2
CONFIG_PPC_ADV_DEBUG_DVCS=0
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_HAVE_IRQ_WORK=y
CONFIG_KEXEC=y
# CONFIG_CRASH_DUMP is not set
CONFIG_PPC_4K_PAGES=y
#
# Advanced setup
#
CONFIG_ADVANCED_OPTIONS=y
# CONFIG_LOWMEM_SIZE_BOOL is not set
CONFIG_LOWMEM_SIZE=0x30000000
# CONFIG_LOWMEM_CAM_NUM_BOOL is not set
CONFIG_LOWMEM_CAM_NUM=3
CONFIG_DYNAMIC_MEMSTART=y
# CONFIG_PAGE_OFFSET_BOOL is not set
CONFIG_PAGE_OFFSET=0xc0000000
# CONFIG_KERNEL_START_BOOL is not set
CONFIG_KERNEL_START=0xc0000000
# CONFIG_PHYSICAL_START_BOOL is not set
CONFIG_PHYSICAL_START=0x00000000
CONFIG_PHYSICAL_ALIGN=0x04000000
# CONFIG_TASK_SIZE_BOOL is not set
CONFIG_TASK_SIZE=0xc0000000
The version of the kexec tool is 2.04.
Any ideas?
- Stefani
^ permalink raw reply
* [PATCH v2 0/2] perf tools: Power7 events name available for perf
From: Runzhen Wang @ 2013-06-25 14:35 UTC (permalink / raw)
To: linuxppc-dev, linux-kernel
Cc: acme, xiaoguangrong, paulus, Runzhen Wang, sukadev
Thank for Sukadev Bhattip and Xiao Guangrong's help.
Thank for Michael Ellerman's review.
There is the Change Log for v2:
1. As Michael Ellerman suggested, I added runtime overhead information
in the 0002 patch's description.
2. Put the events name in a new head file which is named "power7-events-list.h",
and use several macros, such as,
#define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _code)
#include "power7-events-list.h"
#undef EVENT
to generate different outputs.
Thanks
Runzhen Wang
Runzhen Wang (2):
perf tools: fix a typo of a Power7 event name
perf tools: Make Power7 events available for perf
.../testing/sysfs-bus-event_source-devices-events | 2 +-
arch/powerpc/include/asm/perf_event_server.h | 4 +-
arch/powerpc/perf/power7-events-list.h | 548 ++++++++++++++++++++
arch/powerpc/perf/power7-pmu.c | 150 ++----
4 files changed, 584 insertions(+), 120 deletions(-)
create mode 100644 arch/powerpc/perf/power7-events-list.h
--
1.7.9.5
^ permalink raw reply
* [PATCH v3 1/2] perf tools: fix a typo of a Power7 event name
From: Runzhen Wang @ 2013-06-25 14:35 UTC (permalink / raw)
To: linuxppc-dev, linux-kernel
Cc: acme, xiaoguangrong, paulus, Runzhen Wang, sukadev
In-Reply-To: <1372170933-4538-1-git-send-email-runzhen@linux.vnet.ibm.com>
In the Power7 PMU guide:
https://www.power.org/documentation/commonly-used-metrics-for-performance-analysis/
PM_BRU_MPRED is referred to as PM_BR_MPRED.
It fixed the typo by changing the name of the event in kernel
and documentation accordingly.
This patch changes the ABI, there are some reasons I think it's ok:
- It is relatively new interface, specific to the Power7 platform.
- No tools that we know of actually use this interface at this point
(none are listed near the interface).
- Users of this interface (eg oprofile users migrating to perf)
would be more used to the "PM_BR_MPRED" rather than "PM_BRU_MPRED".
- These are in the ABI/testing at this point rather than ABI/stable,
so hoping we have some wiggle room.
Signed-off-by: Runzhen Wang <runzhen@linux.vnet.ibm.com>
---
.../testing/sysfs-bus-event_source-devices-events | 2 +-
arch/powerpc/perf/power7-pmu.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
index 8b25ffb..3c1cc24 100644
--- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
+++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
@@ -29,7 +29,7 @@ Description: Generic performance monitoring events
What: /sys/devices/cpu/events/PM_1PLUS_PPC_CMPL
/sys/devices/cpu/events/PM_BRU_FIN
- /sys/devices/cpu/events/PM_BRU_MPRED
+ /sys/devices/cpu/events/PM_BR_MPRED
/sys/devices/cpu/events/PM_CMPLU_STALL
/sys/devices/cpu/events/PM_CMPLU_STALL_BRU
/sys/devices/cpu/events/PM_CMPLU_STALL_DCACHE_MISS
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 13c3f0e..d1821b8 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -60,7 +60,7 @@
#define PME_PM_LD_REF_L1 0xc880
#define PME_PM_LD_MISS_L1 0x400f0
#define PME_PM_BRU_FIN 0x10068
-#define PME_PM_BRU_MPRED 0x400f6
+#define PME_PM_BR_MPRED 0x400f6
#define PME_PM_CMPLU_STALL_FXU 0x20014
#define PME_PM_CMPLU_STALL_DIV 0x40014
@@ -349,7 +349,7 @@ static int power7_generic_events[] = {
[PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1,
[PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1,
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
- [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BRU_MPRED,
+ [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BR_MPRED,
};
#define C(x) PERF_COUNT_HW_CACHE_##x
@@ -405,7 +405,7 @@ GENERIC_EVENT_ATTR(instructions, INST_CMPL);
GENERIC_EVENT_ATTR(cache-references, LD_REF_L1);
GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
GENERIC_EVENT_ATTR(branch-instructions, BRU_FIN);
-GENERIC_EVENT_ATTR(branch-misses, BRU_MPRED);
+GENERIC_EVENT_ATTR(branch-misses, BR_MPRED);
POWER_EVENT_ATTR(CYC, CYC);
POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC);
@@ -414,7 +414,7 @@ POWER_EVENT_ATTR(INST_CMPL, INST_CMPL);
POWER_EVENT_ATTR(LD_REF_L1, LD_REF_L1);
POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1);
POWER_EVENT_ATTR(BRU_FIN, BRU_FIN)
-POWER_EVENT_ATTR(BRU_MPRED, BRU_MPRED);
+POWER_EVENT_ATTR(BR_MPRED, BR_MPRED);
POWER_EVENT_ATTR(CMPLU_STALL_FXU, CMPLU_STALL_FXU);
POWER_EVENT_ATTR(CMPLU_STALL_DIV, CMPLU_STALL_DIV);
@@ -449,7 +449,7 @@ static struct attribute *power7_events_attr[] = {
GENERIC_EVENT_PTR(LD_REF_L1),
GENERIC_EVENT_PTR(LD_MISS_L1),
GENERIC_EVENT_PTR(BRU_FIN),
- GENERIC_EVENT_PTR(BRU_MPRED),
+ GENERIC_EVENT_PTR(BR_MPRED),
POWER_EVENT_PTR(CYC),
POWER_EVENT_PTR(GCT_NOSLOT_CYC),
@@ -458,7 +458,7 @@ static struct attribute *power7_events_attr[] = {
POWER_EVENT_PTR(LD_REF_L1),
POWER_EVENT_PTR(LD_MISS_L1),
POWER_EVENT_PTR(BRU_FIN),
- POWER_EVENT_PTR(BRU_MPRED),
+ POWER_EVENT_PTR(BR_MPRED),
POWER_EVENT_PTR(CMPLU_STALL_FXU),
POWER_EVENT_PTR(CMPLU_STALL_DIV),
--
1.7.9.5
^ permalink raw reply related
* [PATCH v2 2/2] perf tools: Make Power7 events available for perf
From: Runzhen Wang @ 2013-06-25 14:35 UTC (permalink / raw)
To: linuxppc-dev, linux-kernel
Cc: acme, xiaoguangrong, paulus, Runzhen Wang, sukadev
In-Reply-To: <1372170933-4538-1-git-send-email-runzhen@linux.vnet.ibm.com>
Power7 supports over 530 different perf events but only a small
subset of these can be specified by name, for the remaining
events, we must specify them by their raw code:
perf stat -e r2003c <application>
This patch makes all the POWER7 events available in sysfs.
So we can instead specify these as:
perf stat -e 'cpu/PM_CMPLU_STALL_DFU/' <application>
where PM_CMPLU_STALL_DFU is the r2003c in previous example.
Before this patch is applied, the size of power7-pmu.o is:
$ size arch/powerpc/perf/power7-pmu.o
text data bss dec hex filename
3073 2720 0 5793 16a1 arch/powerpc/perf/power7-pmu.o
and after the patch is applied, it is:
$ size arch/powerpc/perf/power7-pmu.o
text data bss dec hex filename
15950 31112 0 47062 b7d6 arch/powerpc/perf/power7-pmu.o
For the run time overhead, I use two scripts, one is "event_name.sh",
which contains 50 event names, it looks like:
# ./perf record -e 'cpu/PM_CMPLU_STALL_DFU/' -e ..... /bin/sleep 1
the other one is named "event_code.sh" which use corresponding events raw
code instead of events names, it looks like:
# ./perf record -e r2003c -e ...... /bin/sleep 1
below is the result.
Using events name:
[root@localhost perf]# time ./event_name.sh
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.002 MB perf.data (~102 samples) ]
real 0m1.192s
user 0m0.028s
sys 0m0.106s
Using events raw code:
[root@localhost perf]# time ./event_code.sh
[ perf record: Woken up 1 times to write data ]
[ perf record: Captured and wrote 0.003 MB perf.data (~112 samples) ]
real 0m1.198s
user 0m0.028s
sys 0m0.105s
Signed-off-by: Runzhen Wang <runzhen@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/perf_event_server.h | 4 +-
arch/powerpc/perf/power7-events-list.h | 548 ++++++++++++++++++++++++++
arch/powerpc/perf/power7-pmu.c | 148 ++-----
3 files changed, 582 insertions(+), 118 deletions(-)
create mode 100644 arch/powerpc/perf/power7-events-list.h
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index f265049..d9270d8 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -136,11 +136,11 @@ extern ssize_t power_events_sysfs_show(struct device *dev,
#define EVENT_PTR(_id, _suffix) &EVENT_VAR(_id, _suffix).attr.attr
#define EVENT_ATTR(_name, _id, _suffix) \
- PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_PM_##_id, \
+ PMU_EVENT_ATTR(_name, EVENT_VAR(_id, _suffix), PME_##_id, \
power_events_sysfs_show)
#define GENERIC_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _g)
#define GENERIC_EVENT_PTR(_id) EVENT_PTR(_id, _g)
-#define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(PM_##_name, _id, _p)
+#define POWER_EVENT_ATTR(_name, _id) EVENT_ATTR(_name, _id, _p)
#define POWER_EVENT_PTR(_id) EVENT_PTR(_id, _p)
diff --git a/arch/powerpc/perf/power7-events-list.h b/arch/powerpc/perf/power7-events-list.h
new file mode 100644
index 0000000..a67e8a9
--- /dev/null
+++ b/arch/powerpc/perf/power7-events-list.h
@@ -0,0 +1,548 @@
+/*
+ * Performance counter support for POWER7 processors.
+ *
+ * Copyright 2013 Runzhen Wang, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+EVENT(PM_IC_DEMAND_L2_BR_ALL, 0x4898)
+EVENT(PM_GCT_UTIL_7_TO_10_SLOTS, 0x20a0)
+EVENT(PM_PMC2_SAVED, 0x10022)
+EVENT(PM_CMPLU_STALL_DFU, 0x2003c)
+EVENT(PM_VSU0_16FLOP, 0xa0a4)
+EVENT(PM_MRK_LSU_DERAT_MISS, 0x3d05a)
+EVENT(PM_MRK_ST_CMPL, 0x10034)
+EVENT(PM_NEST_PAIR3_ADD, 0x40881)
+EVENT(PM_L2_ST_DISP, 0x46180)
+EVENT(PM_L2_CASTOUT_MOD, 0x16180)
+EVENT(PM_ISEG, 0x20a4)
+EVENT(PM_MRK_INST_TIMEO, 0x40034)
+EVENT(PM_L2_RCST_DISP_FAIL_ADDR, 0x36282)
+EVENT(PM_LSU1_DC_PREF_STREAM_CONFIRM, 0xd0b6)
+EVENT(PM_IERAT_WR_64K, 0x40be)
+EVENT(PM_MRK_DTLB_MISS_16M, 0x4d05e)
+EVENT(PM_IERAT_MISS, 0x100f6)
+EVENT(PM_MRK_PTEG_FROM_LMEM, 0x4d052)
+EVENT(PM_FLOP, 0x100f4)
+EVENT(PM_THRD_PRIO_4_5_CYC, 0x40b4)
+EVENT(PM_BR_PRED_TA, 0x40aa)
+EVENT(PM_CMPLU_STALL_FXU, 0x20014)
+EVENT(PM_EXT_INT, 0x200f8)
+EVENT(PM_VSU_FSQRT_FDIV, 0xa888)
+EVENT(PM_MRK_LD_MISS_EXPOSED_CYC, 0x1003e)
+EVENT(PM_LSU1_LDF, 0xc086)
+EVENT(PM_IC_WRITE_ALL, 0x488c)
+EVENT(PM_LSU0_SRQ_STFWD, 0xc0a0)
+EVENT(PM_PTEG_FROM_RL2L3_MOD, 0x1c052)
+EVENT(PM_MRK_DATA_FROM_L31_SHR, 0x1d04e)
+EVENT(PM_DATA_FROM_L21_MOD, 0x3c046)
+EVENT(PM_VSU1_SCAL_DOUBLE_ISSUED, 0xb08a)
+EVENT(PM_VSU0_8FLOP, 0xa0a0)
+EVENT(PM_POWER_EVENT1, 0x1006e)
+EVENT(PM_DISP_CLB_HELD_BAL, 0x2092)
+EVENT(PM_VSU1_2FLOP, 0xa09a)
+EVENT(PM_LWSYNC_HELD, 0x209a)
+EVENT(PM_PTEG_FROM_DL2L3_SHR, 0x3c054)
+EVENT(PM_INST_FROM_L21_MOD, 0x34046)
+EVENT(PM_IERAT_XLATE_WR_16MPLUS, 0x40bc)
+EVENT(PM_IC_REQ_ALL, 0x4888)
+EVENT(PM_DSLB_MISS, 0xd090)
+EVENT(PM_L3_MISS, 0x1f082)
+EVENT(PM_LSU0_L1_PREF, 0xd0b8)
+EVENT(PM_VSU_SCALAR_SINGLE_ISSUED, 0xb884)
+EVENT(PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE, 0xd0be)
+EVENT(PM_L2_INST, 0x36080)
+EVENT(PM_VSU0_FRSP, 0xa0b4)
+EVENT(PM_FLUSH_DISP, 0x2082)
+EVENT(PM_PTEG_FROM_L2MISS, 0x4c058)
+EVENT(PM_VSU1_DQ_ISSUED, 0xb09a)
+EVENT(PM_CMPLU_STALL_LSU, 0x20012)
+EVENT(PM_MRK_DATA_FROM_DMEM, 0x1d04a)
+EVENT(PM_LSU_FLUSH_ULD, 0xc8b0)
+EVENT(PM_PTEG_FROM_LMEM, 0x4c052)
+EVENT(PM_MRK_DERAT_MISS_16M, 0x3d05c)
+EVENT(PM_THRD_ALL_RUN_CYC, 0x2000c)
+EVENT(PM_MEM0_PREFETCH_DISP, 0x20083)
+EVENT(PM_MRK_STALL_CMPLU_CYC_COUNT, 0x3003f)
+EVENT(PM_DATA_FROM_DL2L3_MOD, 0x3c04c)
+EVENT(PM_VSU_FRSP, 0xa8b4)
+EVENT(PM_MRK_DATA_FROM_L21_MOD, 0x3d046)
+EVENT(PM_PMC1_OVERFLOW, 0x20010)
+EVENT(PM_VSU0_SINGLE, 0xa0a8)
+EVENT(PM_MRK_PTEG_FROM_L3MISS, 0x2d058)
+EVENT(PM_MRK_PTEG_FROM_L31_SHR, 0x2d056)
+EVENT(PM_VSU0_VECTOR_SP_ISSUED, 0xb090)
+EVENT(PM_VSU1_FEST, 0xa0ba)
+EVENT(PM_MRK_INST_DISP, 0x20030)
+EVENT(PM_VSU0_COMPLEX_ISSUED, 0xb096)
+EVENT(PM_LSU1_FLUSH_UST, 0xc0b6)
+EVENT(PM_INST_CMPL, 0x2)
+EVENT(PM_FXU_IDLE, 0x1000e)
+EVENT(PM_LSU0_FLUSH_ULD, 0xc0b0)
+EVENT(PM_MRK_DATA_FROM_DL2L3_MOD, 0x3d04c)
+EVENT(PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC, 0x3001c)
+EVENT(PM_LSU1_REJECT_LMQ_FULL, 0xc0a6)
+EVENT(PM_INST_PTEG_FROM_L21_MOD, 0x3e056)
+EVENT(PM_INST_FROM_RL2L3_MOD, 0x14042)
+EVENT(PM_SHL_CREATED, 0x5082)
+EVENT(PM_L2_ST_HIT, 0x46182)
+EVENT(PM_DATA_FROM_DMEM, 0x1c04a)
+EVENT(PM_L3_LD_MISS, 0x2f082)
+EVENT(PM_FXU1_BUSY_FXU0_IDLE, 0x4000e)
+EVENT(PM_DISP_CLB_HELD_RES, 0x2094)
+EVENT(PM_L2_SN_SX_I_DONE, 0x36382)
+EVENT(PM_GRP_CMPL, 0x30004)
+EVENT(PM_STCX_CMPL, 0xc098)
+EVENT(PM_VSU0_2FLOP, 0xa098)
+EVENT(PM_L3_PREF_MISS, 0x3f082)
+EVENT(PM_LSU_SRQ_SYNC_CYC, 0xd096)
+EVENT(PM_LSU_REJECT_ERAT_MISS, 0x20064)
+EVENT(PM_L1_ICACHE_MISS, 0x200fc)
+EVENT(PM_LSU1_FLUSH_SRQ, 0xc0be)
+EVENT(PM_LD_REF_L1_LSU0, 0xc080)
+EVENT(PM_VSU0_FEST, 0xa0b8)
+EVENT(PM_VSU_VECTOR_SINGLE_ISSUED, 0xb890)
+EVENT(PM_FREQ_UP, 0x4000c)
+EVENT(PM_DATA_FROM_LMEM, 0x3c04a)
+EVENT(PM_LSU1_LDX, 0xc08a)
+EVENT(PM_PMC3_OVERFLOW, 0x40010)
+EVENT(PM_MRK_BR_MPRED, 0x30036)
+EVENT(PM_SHL_MATCH, 0x5086)
+EVENT(PM_MRK_BR_TAKEN, 0x10036)
+EVENT(PM_CMPLU_STALL_BRU, 0x4004e)
+EVENT(PM_ISLB_MISS, 0xd092)
+EVENT(PM_CYC, 0x1e)
+EVENT(PM_DISP_HELD_THERMAL, 0x30006)
+EVENT(PM_INST_PTEG_FROM_RL2L3_SHR, 0x2e054)
+EVENT(PM_LSU1_SRQ_STFWD, 0xc0a2)
+EVENT(PM_GCT_NOSLOT_BR_MPRED, 0x4001a)
+EVENT(PM_1PLUS_PPC_CMPL, 0x100f2)
+EVENT(PM_PTEG_FROM_DMEM, 0x2c052)
+EVENT(PM_VSU_2FLOP, 0xa898)
+EVENT(PM_GCT_FULL_CYC, 0x4086)
+EVENT(PM_MRK_DATA_FROM_L3_CYC, 0x40020)
+EVENT(PM_LSU_SRQ_S0_ALLOC, 0xd09d)
+EVENT(PM_MRK_DERAT_MISS_4K, 0x1d05c)
+EVENT(PM_BR_MPRED_TA, 0x40ae)
+EVENT(PM_INST_PTEG_FROM_L2MISS, 0x4e058)
+EVENT(PM_DPU_HELD_POWER, 0x20006)
+EVENT(PM_RUN_INST_CMPL, 0x400fa)
+EVENT(PM_MRK_VSU_FIN, 0x30032)
+EVENT(PM_LSU_SRQ_S0_VALID, 0xd09c)
+EVENT(PM_GCT_EMPTY_CYC, 0x20008)
+EVENT(PM_IOPS_DISP, 0x30014)
+EVENT(PM_RUN_SPURR, 0x10008)
+EVENT(PM_PTEG_FROM_L21_MOD, 0x3c056)
+EVENT(PM_VSU0_1FLOP, 0xa080)
+EVENT(PM_SNOOP_TLBIE, 0xd0b2)
+EVENT(PM_DATA_FROM_L3MISS, 0x2c048)
+EVENT(PM_VSU_SINGLE, 0xa8a8)
+EVENT(PM_DTLB_MISS_16G, 0x1c05e)
+EVENT(PM_CMPLU_STALL_VECTOR, 0x2001c)
+EVENT(PM_FLUSH, 0x400f8)
+EVENT(PM_L2_LD_HIT, 0x36182)
+EVENT(PM_NEST_PAIR2_AND, 0x30883)
+EVENT(PM_VSU1_1FLOP, 0xa082)
+EVENT(PM_IC_PREF_REQ, 0x408a)
+EVENT(PM_L3_LD_HIT, 0x2f080)
+EVENT(PM_GCT_NOSLOT_IC_MISS, 0x2001a)
+EVENT(PM_DISP_HELD, 0x10006)
+EVENT(PM_L2_LD, 0x16080)
+EVENT(PM_LSU_FLUSH_SRQ, 0xc8bc)
+EVENT(PM_BC_PLUS_8_CONV, 0x40b8)
+EVENT(PM_MRK_DATA_FROM_L31_MOD_CYC, 0x40026)
+EVENT(PM_CMPLU_STALL_VECTOR_LONG, 0x4004a)
+EVENT(PM_L2_RCST_BUSY_RC_FULL, 0x26282)
+EVENT(PM_TB_BIT_TRANS, 0x300f8)
+EVENT(PM_THERMAL_MAX, 0x40006)
+EVENT(PM_LSU1_FLUSH_ULD, 0xc0b2)
+EVENT(PM_LSU1_REJECT_LHS, 0xc0ae)
+EVENT(PM_LSU_LRQ_S0_ALLOC, 0xd09f)
+EVENT(PM_L3_CO_L31, 0x4f080)
+EVENT(PM_POWER_EVENT4, 0x4006e)
+EVENT(PM_DATA_FROM_L31_SHR, 0x1c04e)
+EVENT(PM_BR_UNCOND, 0x409e)
+EVENT(PM_LSU1_DC_PREF_STREAM_ALLOC, 0xd0aa)
+EVENT(PM_PMC4_REWIND, 0x10020)
+EVENT(PM_L2_RCLD_DISP, 0x16280)
+EVENT(PM_THRD_PRIO_2_3_CYC, 0x40b2)
+EVENT(PM_MRK_PTEG_FROM_L2MISS, 0x4d058)
+EVENT(PM_IC_DEMAND_L2_BHT_REDIRECT, 0x4098)
+EVENT(PM_LSU_DERAT_MISS, 0x200f6)
+EVENT(PM_IC_PREF_CANCEL_L2, 0x4094)
+EVENT(PM_MRK_FIN_STALL_CYC_COUNT, 0x1003d)
+EVENT(PM_BR_PRED_CCACHE, 0x40a0)
+EVENT(PM_GCT_UTIL_1_TO_2_SLOTS, 0x209c)
+EVENT(PM_MRK_ST_CMPL_INT, 0x30034)
+EVENT(PM_LSU_TWO_TABLEWALK_CYC, 0xd0a6)
+EVENT(PM_MRK_DATA_FROM_L3MISS, 0x2d048)
+EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
+EVENT(PM_LSU_SET_MPRED, 0xc0a8)
+EVENT(PM_FLUSH_DISP_TLBIE, 0x208a)
+EVENT(PM_VSU1_FCONV, 0xa0b2)
+EVENT(PM_DERAT_MISS_16G, 0x4c05c)
+EVENT(PM_INST_FROM_LMEM, 0x3404a)
+EVENT(PM_IC_DEMAND_L2_BR_REDIRECT, 0x409a)
+EVENT(PM_CMPLU_STALL_SCALAR_LONG, 0x20018)
+EVENT(PM_INST_PTEG_FROM_L2, 0x1e050)
+EVENT(PM_PTEG_FROM_L2, 0x1c050)
+EVENT(PM_MRK_DATA_FROM_L21_SHR_CYC, 0x20024)
+EVENT(PM_MRK_DTLB_MISS_4K, 0x2d05a)
+EVENT(PM_VSU0_FPSCR, 0xb09c)
+EVENT(PM_VSU1_VECT_DOUBLE_ISSUED, 0xb082)
+EVENT(PM_MRK_PTEG_FROM_RL2L3_MOD, 0x1d052)
+EVENT(PM_MEM0_RQ_DISP, 0x10083)
+EVENT(PM_L2_LD_MISS, 0x26080)
+EVENT(PM_VMX_RESULT_SAT_1, 0xb0a0)
+EVENT(PM_L1_PREF, 0xd8b8)
+EVENT(PM_MRK_DATA_FROM_LMEM_CYC, 0x2002c)
+EVENT(PM_GRP_IC_MISS_NONSPEC, 0x1000c)
+EVENT(PM_PB_NODE_PUMP, 0x10081)
+EVENT(PM_SHL_MERGED, 0x5084)
+EVENT(PM_NEST_PAIR1_ADD, 0x20881)
+EVENT(PM_DATA_FROM_L3, 0x1c048)
+EVENT(PM_LSU_FLUSH, 0x208e)
+EVENT(PM_LSU_SRQ_SYNC_COUNT, 0xd097)
+EVENT(PM_PMC2_OVERFLOW, 0x30010)
+EVENT(PM_LSU_LDF, 0xc884)
+EVENT(PM_POWER_EVENT3, 0x3006e)
+EVENT(PM_DISP_WT, 0x30008)
+EVENT(PM_CMPLU_STALL_REJECT, 0x40016)
+EVENT(PM_IC_BANK_CONFLICT, 0x4082)
+EVENT(PM_BR_MPRED_CR_TA, 0x48ae)
+EVENT(PM_L2_INST_MISS, 0x36082)
+EVENT(PM_CMPLU_STALL_ERAT_MISS, 0x40018)
+EVENT(PM_NEST_PAIR2_ADD, 0x30881)
+EVENT(PM_MRK_LSU_FLUSH, 0xd08c)
+EVENT(PM_L2_LDST, 0x16880)
+EVENT(PM_INST_FROM_L31_SHR, 0x1404e)
+EVENT(PM_VSU0_FIN, 0xa0bc)
+EVENT(PM_LARX_LSU, 0xc894)
+EVENT(PM_INST_FROM_RMEM, 0x34042)
+EVENT(PM_DISP_CLB_HELD_TLBIE, 0x2096)
+EVENT(PM_MRK_DATA_FROM_DMEM_CYC, 0x2002e)
+EVENT(PM_BR_PRED_CR, 0x40a8)
+EVENT(PM_LSU_REJECT, 0x10064)
+EVENT(PM_GCT_UTIL_3_TO_6_SLOTS, 0x209e)
+EVENT(PM_CMPLU_STALL_END_GCT_NOSLOT, 0x10028)
+EVENT(PM_LSU0_REJECT_LMQ_FULL, 0xc0a4)
+EVENT(PM_VSU_FEST, 0xa8b8)
+EVENT(PM_NEST_PAIR0_AND, 0x10883)
+EVENT(PM_PTEG_FROM_L3, 0x2c050)
+EVENT(PM_POWER_EVENT2, 0x2006e)
+EVENT(PM_IC_PREF_CANCEL_PAGE, 0x4090)
+EVENT(PM_VSU0_FSQRT_FDIV, 0xa088)
+EVENT(PM_MRK_GRP_CMPL, 0x40030)
+EVENT(PM_VSU0_SCAL_DOUBLE_ISSUED, 0xb088)
+EVENT(PM_GRP_DISP, 0x3000a)
+EVENT(PM_LSU0_LDX, 0xc088)
+EVENT(PM_DATA_FROM_L2, 0x1c040)
+EVENT(PM_MRK_DATA_FROM_RL2L3_MOD, 0x1d042)
+EVENT(PM_LD_REF_L1, 0xc880)
+EVENT(PM_VSU0_VECT_DOUBLE_ISSUED, 0xb080)
+EVENT(PM_VSU1_2FLOP_DOUBLE, 0xa08e)
+EVENT(PM_THRD_PRIO_6_7_CYC, 0x40b6)
+EVENT(PM_BC_PLUS_8_RSLV_TAKEN, 0x40ba)
+EVENT(PM_BR_MPRED_CR, 0x40ac)
+EVENT(PM_L3_CO_MEM, 0x4f082)
+EVENT(PM_LD_MISS_L1, 0x400f0)
+EVENT(PM_DATA_FROM_RL2L3_MOD, 0x1c042)
+EVENT(PM_LSU_SRQ_FULL_CYC, 0x1001a)
+EVENT(PM_TABLEWALK_CYC, 0x10026)
+EVENT(PM_MRK_PTEG_FROM_RMEM, 0x3d052)
+EVENT(PM_LSU_SRQ_STFWD, 0xc8a0)
+EVENT(PM_INST_PTEG_FROM_RMEM, 0x3e052)
+EVENT(PM_FXU0_FIN, 0x10004)
+EVENT(PM_LSU1_L1_SW_PREF, 0xc09e)
+EVENT(PM_PTEG_FROM_L31_MOD, 0x1c054)
+EVENT(PM_PMC5_OVERFLOW, 0x10024)
+EVENT(PM_LD_REF_L1_LSU1, 0xc082)
+EVENT(PM_INST_PTEG_FROM_L21_SHR, 0x4e056)
+EVENT(PM_CMPLU_STALL_THRD, 0x1001c)
+EVENT(PM_DATA_FROM_RMEM, 0x3c042)
+EVENT(PM_VSU0_SCAL_SINGLE_ISSUED, 0xb084)
+EVENT(PM_BR_MPRED_LSTACK, 0x40a6)
+EVENT(PM_MRK_DATA_FROM_RL2L3_MOD_CYC, 0x40028)
+EVENT(PM_LSU0_FLUSH_UST, 0xc0b4)
+EVENT(PM_LSU_NCST, 0xc090)
+EVENT(PM_BR_TAKEN, 0x20004)
+EVENT(PM_INST_PTEG_FROM_LMEM, 0x4e052)
+EVENT(PM_GCT_NOSLOT_BR_MPRED_IC_MISS, 0x4001c)
+EVENT(PM_DTLB_MISS_4K, 0x2c05a)
+EVENT(PM_PMC4_SAVED, 0x30022)
+EVENT(PM_VSU1_PERMUTE_ISSUED, 0xb092)
+EVENT(PM_SLB_MISS, 0xd890)
+EVENT(PM_LSU1_FLUSH_LRQ, 0xc0ba)
+EVENT(PM_DTLB_MISS, 0x300fc)
+EVENT(PM_VSU1_FRSP, 0xa0b6)
+EVENT(PM_VSU_VECTOR_DOUBLE_ISSUED, 0xb880)
+EVENT(PM_L2_CASTOUT_SHR, 0x16182)
+EVENT(PM_DATA_FROM_DL2L3_SHR, 0x3c044)
+EVENT(PM_VSU1_STF, 0xb08e)
+EVENT(PM_ST_FIN, 0x200f0)
+EVENT(PM_PTEG_FROM_L21_SHR, 0x4c056)
+EVENT(PM_L2_LOC_GUESS_WRONG, 0x26480)
+EVENT(PM_MRK_STCX_FAIL, 0xd08e)
+EVENT(PM_LSU0_REJECT_LHS, 0xc0ac)
+EVENT(PM_IC_PREF_CANCEL_HIT, 0x4092)
+EVENT(PM_L3_PREF_BUSY, 0x4f080)
+EVENT(PM_MRK_BRU_FIN, 0x2003a)
+EVENT(PM_LSU1_NCLD, 0xc08e)
+EVENT(PM_INST_PTEG_FROM_L31_MOD, 0x1e054)
+EVENT(PM_LSU_NCLD, 0xc88c)
+EVENT(PM_LSU_LDX, 0xc888)
+EVENT(PM_L2_LOC_GUESS_CORRECT, 0x16480)
+EVENT(PM_THRESH_TIMEO, 0x10038)
+EVENT(PM_L3_PREF_ST, 0xd0ae)
+EVENT(PM_DISP_CLB_HELD_SYNC, 0x2098)
+EVENT(PM_VSU_SIMPLE_ISSUED, 0xb894)
+EVENT(PM_VSU1_SINGLE, 0xa0aa)
+EVENT(PM_DATA_TABLEWALK_CYC, 0x3001a)
+EVENT(PM_L2_RC_ST_DONE, 0x36380)
+EVENT(PM_MRK_PTEG_FROM_L21_MOD, 0x3d056)
+EVENT(PM_LARX_LSU1, 0xc096)
+EVENT(PM_MRK_DATA_FROM_RMEM, 0x3d042)
+EVENT(PM_DISP_CLB_HELD, 0x2090)
+EVENT(PM_DERAT_MISS_4K, 0x1c05c)
+EVENT(PM_L2_RCLD_DISP_FAIL_ADDR, 0x16282)
+EVENT(PM_SEG_EXCEPTION, 0x28a4)
+EVENT(PM_FLUSH_DISP_SB, 0x208c)
+EVENT(PM_L2_DC_INV, 0x26182)
+EVENT(PM_PTEG_FROM_DL2L3_MOD, 0x4c054)
+EVENT(PM_DSEG, 0x20a6)
+EVENT(PM_BR_PRED_LSTACK, 0x40a2)
+EVENT(PM_VSU0_STF, 0xb08c)
+EVENT(PM_LSU_FX_FIN, 0x10066)
+EVENT(PM_DERAT_MISS_16M, 0x3c05c)
+EVENT(PM_MRK_PTEG_FROM_DL2L3_MOD, 0x4d054)
+EVENT(PM_GCT_UTIL_11_PLUS_SLOTS, 0x20a2)
+EVENT(PM_INST_FROM_L3, 0x14048)
+EVENT(PM_MRK_IFU_FIN, 0x3003a)
+EVENT(PM_ITLB_MISS, 0x400fc)
+EVENT(PM_VSU_STF, 0xb88c)
+EVENT(PM_LSU_FLUSH_UST, 0xc8b4)
+EVENT(PM_L2_LDST_MISS, 0x26880)
+EVENT(PM_FXU1_FIN, 0x40004)
+EVENT(PM_SHL_DEALLOCATED, 0x5080)
+EVENT(PM_L2_SN_M_WR_DONE, 0x46382)
+EVENT(PM_LSU_REJECT_SET_MPRED, 0xc8a8)
+EVENT(PM_L3_PREF_LD, 0xd0ac)
+EVENT(PM_L2_SN_M_RD_DONE, 0x46380)
+EVENT(PM_MRK_DERAT_MISS_16G, 0x4d05c)
+EVENT(PM_VSU_FCONV, 0xa8b0)
+EVENT(PM_ANY_THRD_RUN_CYC, 0x100fa)
+EVENT(PM_LSU_LMQ_FULL_CYC, 0xd0a4)
+EVENT(PM_MRK_LSU_REJECT_LHS, 0xd082)
+EVENT(PM_MRK_LD_MISS_L1_CYC, 0x4003e)
+EVENT(PM_MRK_DATA_FROM_L2_CYC, 0x20020)
+EVENT(PM_INST_IMC_MATCH_DISP, 0x30016)
+EVENT(PM_MRK_DATA_FROM_RMEM_CYC, 0x4002c)
+EVENT(PM_VSU0_SIMPLE_ISSUED, 0xb094)
+EVENT(PM_CMPLU_STALL_DIV, 0x40014)
+EVENT(PM_MRK_PTEG_FROM_RL2L3_SHR, 0x2d054)
+EVENT(PM_VSU_FMA_DOUBLE, 0xa890)
+EVENT(PM_VSU_4FLOP, 0xa89c)
+EVENT(PM_VSU1_FIN, 0xa0be)
+EVENT(PM_NEST_PAIR1_AND, 0x20883)
+EVENT(PM_INST_PTEG_FROM_RL2L3_MOD, 0x1e052)
+EVENT(PM_RUN_CYC, 0x200f4)
+EVENT(PM_PTEG_FROM_RMEM, 0x3c052)
+EVENT(PM_LSU_LRQ_S0_VALID, 0xd09e)
+EVENT(PM_LSU0_LDF, 0xc084)
+EVENT(PM_FLUSH_COMPLETION, 0x30012)
+EVENT(PM_ST_MISS_L1, 0x300f0)
+EVENT(PM_L2_NODE_PUMP, 0x36480)
+EVENT(PM_INST_FROM_DL2L3_SHR, 0x34044)
+EVENT(PM_MRK_STALL_CMPLU_CYC, 0x3003e)
+EVENT(PM_VSU1_DENORM, 0xa0ae)
+EVENT(PM_MRK_DATA_FROM_L31_SHR_CYC, 0x20026)
+EVENT(PM_NEST_PAIR0_ADD, 0x10881)
+EVENT(PM_INST_FROM_L3MISS, 0x24048)
+EVENT(PM_EE_OFF_EXT_INT, 0x2080)
+EVENT(PM_INST_PTEG_FROM_DMEM, 0x2e052)
+EVENT(PM_INST_FROM_DL2L3_MOD, 0x3404c)
+EVENT(PM_PMC6_OVERFLOW, 0x30024)
+EVENT(PM_VSU_2FLOP_DOUBLE, 0xa88c)
+EVENT(PM_TLB_MISS, 0x20066)
+EVENT(PM_FXU_BUSY, 0x2000e)
+EVENT(PM_L2_RCLD_DISP_FAIL_OTHER, 0x26280)
+EVENT(PM_LSU_REJECT_LMQ_FULL, 0xc8a4)
+EVENT(PM_IC_RELOAD_SHR, 0x4096)
+EVENT(PM_GRP_MRK, 0x10031)
+EVENT(PM_MRK_ST_NEST, 0x20034)
+EVENT(PM_VSU1_FSQRT_FDIV, 0xa08a)
+EVENT(PM_LSU0_FLUSH_LRQ, 0xc0b8)
+EVENT(PM_LARX_LSU0, 0xc094)
+EVENT(PM_IBUF_FULL_CYC, 0x4084)
+EVENT(PM_MRK_DATA_FROM_DL2L3_SHR_CYC, 0x2002a)
+EVENT(PM_LSU_DC_PREF_STREAM_ALLOC, 0xd8a8)
+EVENT(PM_GRP_MRK_CYC, 0x10030)
+EVENT(PM_MRK_DATA_FROM_RL2L3_SHR_CYC, 0x20028)
+EVENT(PM_L2_GLOB_GUESS_CORRECT, 0x16482)
+EVENT(PM_LSU_REJECT_LHS, 0xc8ac)
+EVENT(PM_MRK_DATA_FROM_LMEM, 0x3d04a)
+EVENT(PM_INST_PTEG_FROM_L3, 0x2e050)
+EVENT(PM_FREQ_DOWN, 0x3000c)
+EVENT(PM_PB_RETRY_NODE_PUMP, 0x30081)
+EVENT(PM_INST_FROM_RL2L3_SHR, 0x1404c)
+EVENT(PM_MRK_INST_ISSUED, 0x10032)
+EVENT(PM_PTEG_FROM_L3MISS, 0x2c058)
+EVENT(PM_RUN_PURR, 0x400f4)
+EVENT(PM_MRK_GRP_IC_MISS, 0x40038)
+EVENT(PM_MRK_DATA_FROM_L3, 0x1d048)
+EVENT(PM_CMPLU_STALL_DCACHE_MISS, 0x20016)
+EVENT(PM_PTEG_FROM_RL2L3_SHR, 0x2c054)
+EVENT(PM_LSU_FLUSH_LRQ, 0xc8b8)
+EVENT(PM_MRK_DERAT_MISS_64K, 0x2d05c)
+EVENT(PM_INST_PTEG_FROM_DL2L3_MOD, 0x4e054)
+EVENT(PM_L2_ST_MISS, 0x26082)
+EVENT(PM_MRK_PTEG_FROM_L21_SHR, 0x4d056)
+EVENT(PM_LWSYNC, 0xd094)
+EVENT(PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE, 0xd0bc)
+EVENT(PM_MRK_LSU_FLUSH_LRQ, 0xd088)
+EVENT(PM_INST_IMC_MATCH_CMPL, 0x100f0)
+EVENT(PM_NEST_PAIR3_AND, 0x40883)
+EVENT(PM_PB_RETRY_SYS_PUMP, 0x40081)
+EVENT(PM_MRK_INST_FIN, 0x30030)
+EVENT(PM_MRK_PTEG_FROM_DL2L3_SHR, 0x3d054)
+EVENT(PM_INST_FROM_L31_MOD, 0x14044)
+EVENT(PM_MRK_DTLB_MISS_64K, 0x3d05e)
+EVENT(PM_LSU_FIN, 0x30066)
+EVENT(PM_MRK_LSU_REJECT, 0x40064)
+EVENT(PM_L2_CO_FAIL_BUSY, 0x16382)
+EVENT(PM_MEM0_WQ_DISP, 0x40083)
+EVENT(PM_DATA_FROM_L31_MOD, 0x1c044)
+EVENT(PM_THERMAL_WARN, 0x10016)
+EVENT(PM_VSU0_4FLOP, 0xa09c)
+EVENT(PM_BR_MPRED_CCACHE, 0x40a4)
+EVENT(PM_CMPLU_STALL_IFU, 0x4004c)
+EVENT(PM_L1_DEMAND_WRITE, 0x408c)
+EVENT(PM_FLUSH_BR_MPRED, 0x2084)
+EVENT(PM_MRK_DTLB_MISS_16G, 0x1d05e)
+EVENT(PM_MRK_PTEG_FROM_DMEM, 0x2d052)
+EVENT(PM_L2_RCST_DISP, 0x36280)
+EVENT(PM_CMPLU_STALL, 0x4000a)
+EVENT(PM_LSU_PARTIAL_CDF, 0xc0aa)
+EVENT(PM_DISP_CLB_HELD_SB, 0x20a8)
+EVENT(PM_VSU0_FMA_DOUBLE, 0xa090)
+EVENT(PM_FXU0_BUSY_FXU1_IDLE, 0x3000e)
+EVENT(PM_IC_DEMAND_CYC, 0x10018)
+EVENT(PM_MRK_DATA_FROM_L21_SHR, 0x3d04e)
+EVENT(PM_MRK_LSU_FLUSH_UST, 0xd086)
+EVENT(PM_INST_PTEG_FROM_L3MISS, 0x2e058)
+EVENT(PM_VSU_DENORM, 0xa8ac)
+EVENT(PM_MRK_LSU_PARTIAL_CDF, 0xd080)
+EVENT(PM_INST_FROM_L21_SHR, 0x3404e)
+EVENT(PM_IC_PREF_WRITE, 0x408e)
+EVENT(PM_BR_PRED, 0x409c)
+EVENT(PM_INST_FROM_DMEM, 0x1404a)
+EVENT(PM_IC_PREF_CANCEL_ALL, 0x4890)
+EVENT(PM_LSU_DC_PREF_STREAM_CONFIRM, 0xd8b4)
+EVENT(PM_MRK_LSU_FLUSH_SRQ, 0xd08a)
+EVENT(PM_MRK_FIN_STALL_CYC, 0x1003c)
+EVENT(PM_L2_RCST_DISP_FAIL_OTHER, 0x46280)
+EVENT(PM_VSU1_DD_ISSUED, 0xb098)
+EVENT(PM_PTEG_FROM_L31_SHR, 0x2c056)
+EVENT(PM_DATA_FROM_L21_SHR, 0x3c04e)
+EVENT(PM_LSU0_NCLD, 0xc08c)
+EVENT(PM_VSU1_4FLOP, 0xa09e)
+EVENT(PM_VSU1_8FLOP, 0xa0a2)
+EVENT(PM_VSU_8FLOP, 0xa8a0)
+EVENT(PM_LSU_LMQ_SRQ_EMPTY_CYC, 0x2003e)
+EVENT(PM_DTLB_MISS_64K, 0x3c05e)
+EVENT(PM_THRD_CONC_RUN_INST, 0x300f4)
+EVENT(PM_MRK_PTEG_FROM_L2, 0x1d050)
+EVENT(PM_PB_SYS_PUMP, 0x20081)
+EVENT(PM_VSU_FIN, 0xa8bc)
+EVENT(PM_MRK_DATA_FROM_L31_MOD, 0x1d044)
+EVENT(PM_THRD_PRIO_0_1_CYC, 0x40b0)
+EVENT(PM_DERAT_MISS_64K, 0x2c05c)
+EVENT(PM_PMC2_REWIND, 0x30020)
+EVENT(PM_INST_FROM_L2, 0x14040)
+EVENT(PM_GRP_BR_MPRED_NONSPEC, 0x1000a)
+EVENT(PM_INST_DISP, 0x200f2)
+EVENT(PM_MEM0_RD_CANCEL_TOTAL, 0x30083)
+EVENT(PM_LSU0_DC_PREF_STREAM_CONFIRM, 0xd0b4)
+EVENT(PM_L1_DCACHE_RELOAD_VALID, 0x300f6)
+EVENT(PM_VSU_SCALAR_DOUBLE_ISSUED, 0xb888)
+EVENT(PM_L3_PREF_HIT, 0x3f080)
+EVENT(PM_MRK_PTEG_FROM_L31_MOD, 0x1d054)
+EVENT(PM_CMPLU_STALL_STORE, 0x2004a)
+EVENT(PM_MRK_FXU_FIN, 0x20038)
+EVENT(PM_PMC4_OVERFLOW, 0x10010)
+EVENT(PM_MRK_PTEG_FROM_L3, 0x2d050)
+EVENT(PM_LSU0_LMQ_LHR_MERGE, 0xd098)
+EVENT(PM_BTAC_HIT, 0x508a)
+EVENT(PM_L3_RD_BUSY, 0x4f082)
+EVENT(PM_LSU0_L1_SW_PREF, 0xc09c)
+EVENT(PM_INST_FROM_L2MISS, 0x44048)
+EVENT(PM_LSU0_DC_PREF_STREAM_ALLOC, 0xd0a8)
+EVENT(PM_L2_ST, 0x16082)
+EVENT(PM_VSU0_DENORM, 0xa0ac)
+EVENT(PM_MRK_DATA_FROM_DL2L3_SHR, 0x3d044)
+EVENT(PM_BR_PRED_CR_TA, 0x48aa)
+EVENT(PM_VSU0_FCONV, 0xa0b0)
+EVENT(PM_MRK_LSU_FLUSH_ULD, 0xd084)
+EVENT(PM_BTAC_MISS, 0x5088)
+EVENT(PM_MRK_LD_MISS_EXPOSED_CYC_COUNT, 0x1003f)
+EVENT(PM_MRK_DATA_FROM_L2, 0x1d040)
+EVENT(PM_LSU_DCACHE_RELOAD_VALID, 0xd0a2)
+EVENT(PM_VSU_FMA, 0xa884)
+EVENT(PM_LSU0_FLUSH_SRQ, 0xc0bc)
+EVENT(PM_LSU1_L1_PREF, 0xd0ba)
+EVENT(PM_IOPS_CMPL, 0x10014)
+EVENT(PM_L2_SYS_PUMP, 0x36482)
+EVENT(PM_L2_RCLD_BUSY_RC_FULL, 0x46282)
+EVENT(PM_LSU_LMQ_S0_ALLOC, 0xd0a1)
+EVENT(PM_FLUSH_DISP_SYNC, 0x2088)
+EVENT(PM_MRK_DATA_FROM_DL2L3_MOD_CYC, 0x4002a)
+EVENT(PM_L2_IC_INV, 0x26180)
+EVENT(PM_MRK_DATA_FROM_L21_MOD_CYC, 0x40024)
+EVENT(PM_L3_PREF_LDST, 0xd8ac)
+EVENT(PM_LSU_SRQ_EMPTY_CYC, 0x40008)
+EVENT(PM_LSU_LMQ_S0_VALID, 0xd0a0)
+EVENT(PM_FLUSH_PARTIAL, 0x2086)
+EVENT(PM_VSU1_FMA_DOUBLE, 0xa092)
+EVENT(PM_1PLUS_PPC_DISP, 0x400f2)
+EVENT(PM_DATA_FROM_L2MISS, 0x200fe)
+EVENT(PM_SUSPENDED, 0x0)
+EVENT(PM_VSU0_FMA, 0xa084)
+EVENT(PM_CMPLU_STALL_SCALAR, 0x40012)
+EVENT(PM_STCX_FAIL, 0xc09a)
+EVENT(PM_VSU0_FSQRT_FDIV_DOUBLE, 0xa094)
+EVENT(PM_DC_PREF_DST, 0xd0b0)
+EVENT(PM_VSU1_SCAL_SINGLE_ISSUED, 0xb086)
+EVENT(PM_L3_HIT, 0x1f080)
+EVENT(PM_L2_GLOB_GUESS_WRONG, 0x26482)
+EVENT(PM_MRK_DFU_FIN, 0x20032)
+EVENT(PM_INST_FROM_L1, 0x4080)
+EVENT(PM_BRU_FIN, 0x10068)
+EVENT(PM_IC_DEMAND_REQ, 0x4088)
+EVENT(PM_VSU1_FSQRT_FDIV_DOUBLE, 0xa096)
+EVENT(PM_VSU1_FMA, 0xa086)
+EVENT(PM_MRK_LD_MISS_L1, 0x20036)
+EVENT(PM_VSU0_2FLOP_DOUBLE, 0xa08c)
+EVENT(PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM, 0xd8bc)
+EVENT(PM_INST_PTEG_FROM_L31_SHR, 0x2e056)
+EVENT(PM_MRK_LSU_REJECT_ERAT_MISS, 0x30064)
+EVENT(PM_MRK_DATA_FROM_L2MISS, 0x4d048)
+EVENT(PM_DATA_FROM_RL2L3_SHR, 0x1c04c)
+EVENT(PM_INST_FROM_PREF, 0x14046)
+EVENT(PM_VSU1_SQ, 0xb09e)
+EVENT(PM_L2_LD_DISP, 0x36180)
+EVENT(PM_L2_DISP_ALL, 0x46080)
+EVENT(PM_THRD_GRP_CMPL_BOTH_CYC, 0x10012)
+EVENT(PM_VSU_FSQRT_FDIV_DOUBLE, 0xa894)
+EVENT(PM_BR_MPRED, 0x400f6)
+EVENT(PM_INST_PTEG_FROM_DL2L3_SHR, 0x3e054)
+EVENT(PM_VSU_1FLOP, 0xa880)
+EVENT(PM_HV_CYC, 0x2000a)
+EVENT(PM_MRK_LSU_FIN, 0x40032)
+EVENT(PM_MRK_DATA_FROM_RL2L3_SHR, 0x1d04c)
+EVENT(PM_DTLB_MISS_16M, 0x4c05e)
+EVENT(PM_LSU1_LMQ_LHR_MERGE, 0xd09a)
+EVENT(PM_IFU_FIN, 0x40066)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index d1821b8..56c67bc 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -53,37 +53,13 @@
/*
* Power7 event codes.
*/
-#define PME_PM_CYC 0x1e
-#define PME_PM_GCT_NOSLOT_CYC 0x100f8
-#define PME_PM_CMPLU_STALL 0x4000a
-#define PME_PM_INST_CMPL 0x2
-#define PME_PM_LD_REF_L1 0xc880
-#define PME_PM_LD_MISS_L1 0x400f0
-#define PME_PM_BRU_FIN 0x10068
-#define PME_PM_BR_MPRED 0x400f6
-
-#define PME_PM_CMPLU_STALL_FXU 0x20014
-#define PME_PM_CMPLU_STALL_DIV 0x40014
-#define PME_PM_CMPLU_STALL_SCALAR 0x40012
-#define PME_PM_CMPLU_STALL_SCALAR_LONG 0x20018
-#define PME_PM_CMPLU_STALL_VECTOR 0x2001c
-#define PME_PM_CMPLU_STALL_VECTOR_LONG 0x4004a
-#define PME_PM_CMPLU_STALL_LSU 0x20012
-#define PME_PM_CMPLU_STALL_REJECT 0x40016
-#define PME_PM_CMPLU_STALL_ERAT_MISS 0x40018
-#define PME_PM_CMPLU_STALL_DCACHE_MISS 0x20016
-#define PME_PM_CMPLU_STALL_STORE 0x2004a
-#define PME_PM_CMPLU_STALL_THRD 0x1001c
-#define PME_PM_CMPLU_STALL_IFU 0x4004c
-#define PME_PM_CMPLU_STALL_BRU 0x4004e
-#define PME_PM_GCT_NOSLOT_IC_MISS 0x2001a
-#define PME_PM_GCT_NOSLOT_BR_MPRED 0x4001a
-#define PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 0x4001c
-#define PME_PM_GRP_CMPL 0x30004
-#define PME_PM_1PLUS_PPC_CMPL 0x100f2
-#define PME_PM_CMPLU_STALL_DFU 0x2003c
-#define PME_PM_RUN_CYC 0x200f4
-#define PME_PM_RUN_INST_CMPL 0x400fa
+#define EVENT(_name, _code) \
+ PME_##_name = _code,
+
+enum {
+#include "power7-events-list.h"
+};
+#undef EVENT
/*
* Layout of constraint bits:
@@ -398,96 +374,36 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
};
-GENERIC_EVENT_ATTR(cpu-cycles, CYC);
-GENERIC_EVENT_ATTR(stalled-cycles-frontend, GCT_NOSLOT_CYC);
-GENERIC_EVENT_ATTR(stalled-cycles-backend, CMPLU_STALL);
-GENERIC_EVENT_ATTR(instructions, INST_CMPL);
-GENERIC_EVENT_ATTR(cache-references, LD_REF_L1);
-GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1);
-GENERIC_EVENT_ATTR(branch-instructions, BRU_FIN);
-GENERIC_EVENT_ATTR(branch-misses, BR_MPRED);
-
-POWER_EVENT_ATTR(CYC, CYC);
-POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC);
-POWER_EVENT_ATTR(CMPLU_STALL, CMPLU_STALL);
-POWER_EVENT_ATTR(INST_CMPL, INST_CMPL);
-POWER_EVENT_ATTR(LD_REF_L1, LD_REF_L1);
-POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1);
-POWER_EVENT_ATTR(BRU_FIN, BRU_FIN)
-POWER_EVENT_ATTR(BR_MPRED, BR_MPRED);
-
-POWER_EVENT_ATTR(CMPLU_STALL_FXU, CMPLU_STALL_FXU);
-POWER_EVENT_ATTR(CMPLU_STALL_DIV, CMPLU_STALL_DIV);
-POWER_EVENT_ATTR(CMPLU_STALL_SCALAR, CMPLU_STALL_SCALAR);
-POWER_EVENT_ATTR(CMPLU_STALL_SCALAR_LONG, CMPLU_STALL_SCALAR_LONG);
-POWER_EVENT_ATTR(CMPLU_STALL_VECTOR, CMPLU_STALL_VECTOR);
-POWER_EVENT_ATTR(CMPLU_STALL_VECTOR_LONG, CMPLU_STALL_VECTOR_LONG);
-POWER_EVENT_ATTR(CMPLU_STALL_LSU, CMPLU_STALL_LSU);
-POWER_EVENT_ATTR(CMPLU_STALL_REJECT, CMPLU_STALL_REJECT);
-
-POWER_EVENT_ATTR(CMPLU_STALL_ERAT_MISS, CMPLU_STALL_ERAT_MISS);
-POWER_EVENT_ATTR(CMPLU_STALL_DCACHE_MISS, CMPLU_STALL_DCACHE_MISS);
-POWER_EVENT_ATTR(CMPLU_STALL_STORE, CMPLU_STALL_STORE);
-POWER_EVENT_ATTR(CMPLU_STALL_THRD, CMPLU_STALL_THRD);
-POWER_EVENT_ATTR(CMPLU_STALL_IFU, CMPLU_STALL_IFU);
-POWER_EVENT_ATTR(CMPLU_STALL_BRU, CMPLU_STALL_BRU);
-POWER_EVENT_ATTR(GCT_NOSLOT_IC_MISS, GCT_NOSLOT_IC_MISS);
-
-POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED, GCT_NOSLOT_BR_MPRED);
-POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED_IC_MISS, GCT_NOSLOT_BR_MPRED_IC_MISS);
-POWER_EVENT_ATTR(GRP_CMPL, GRP_CMPL);
-POWER_EVENT_ATTR(1PLUS_PPC_CMPL, 1PLUS_PPC_CMPL);
-POWER_EVENT_ATTR(CMPLU_STALL_DFU, CMPLU_STALL_DFU);
-POWER_EVENT_ATTR(RUN_CYC, RUN_CYC);
-POWER_EVENT_ATTR(RUN_INST_CMPL, RUN_INST_CMPL);
+GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
+GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
+GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
+GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
+GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
+GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED);
+
+#define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _name);
+#include "power7-events-list.h"
+#undef EVENT
+
+#define EVENT(_name, _code) POWER_EVENT_PTR(_name),
static struct attribute *power7_events_attr[] = {
- GENERIC_EVENT_PTR(CYC),
- GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
- GENERIC_EVENT_PTR(CMPLU_STALL),
- GENERIC_EVENT_PTR(INST_CMPL),
- GENERIC_EVENT_PTR(LD_REF_L1),
- GENERIC_EVENT_PTR(LD_MISS_L1),
- GENERIC_EVENT_PTR(BRU_FIN),
- GENERIC_EVENT_PTR(BR_MPRED),
-
- POWER_EVENT_PTR(CYC),
- POWER_EVENT_PTR(GCT_NOSLOT_CYC),
- POWER_EVENT_PTR(CMPLU_STALL),
- POWER_EVENT_PTR(INST_CMPL),
- POWER_EVENT_PTR(LD_REF_L1),
- POWER_EVENT_PTR(LD_MISS_L1),
- POWER_EVENT_PTR(BRU_FIN),
- POWER_EVENT_PTR(BR_MPRED),
-
- POWER_EVENT_PTR(CMPLU_STALL_FXU),
- POWER_EVENT_PTR(CMPLU_STALL_DIV),
- POWER_EVENT_PTR(CMPLU_STALL_SCALAR),
- POWER_EVENT_PTR(CMPLU_STALL_SCALAR_LONG),
- POWER_EVENT_PTR(CMPLU_STALL_VECTOR),
- POWER_EVENT_PTR(CMPLU_STALL_VECTOR_LONG),
- POWER_EVENT_PTR(CMPLU_STALL_LSU),
- POWER_EVENT_PTR(CMPLU_STALL_REJECT),
-
- POWER_EVENT_PTR(CMPLU_STALL_ERAT_MISS),
- POWER_EVENT_PTR(CMPLU_STALL_DCACHE_MISS),
- POWER_EVENT_PTR(CMPLU_STALL_STORE),
- POWER_EVENT_PTR(CMPLU_STALL_THRD),
- POWER_EVENT_PTR(CMPLU_STALL_IFU),
- POWER_EVENT_PTR(CMPLU_STALL_BRU),
- POWER_EVENT_PTR(GCT_NOSLOT_IC_MISS),
- POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED),
-
- POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED_IC_MISS),
- POWER_EVENT_PTR(GRP_CMPL),
- POWER_EVENT_PTR(1PLUS_PPC_CMPL),
- POWER_EVENT_PTR(CMPLU_STALL_DFU),
- POWER_EVENT_PTR(RUN_CYC),
- POWER_EVENT_PTR(RUN_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_CYC),
+ GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
+ GENERIC_EVENT_PTR(PM_CMPLU_STALL),
+ GENERIC_EVENT_PTR(PM_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_LD_REF_L1),
+ GENERIC_EVENT_PTR(PM_LD_MISS_L1),
+ GENERIC_EVENT_PTR(PM_BRU_FIN),
+ GENERIC_EVENT_PTR(PM_BR_MPRED),
+
+ #include "power7-events-list.h"
+ #undef EVENT
NULL
};
-
static struct attribute_group power7_pmu_events_group = {
.name = "events",
.attrs = power7_events_attr,
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH 2/6] powerpc/eeh: Check PCIe link after reset
From: Benjamin Herrenschmidt @ 2013-06-25 11:58 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <1372154461-29674-3-git-send-email-shangw@linux.vnet.ibm.com>
On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
> After reset (e.g. complete reset) in order to bring the fenced PHB
> back, the PCIe link might not be ready yet. The patch intends to
> make sure the PCIe link is ready before accessing its subordinate
> PCI devices. The patch also fixes that wrong values restored to
> PCI_COMMAND register for PCI bridges.
This should also help if we end up doing a full reset for ER cases
right ?
IE, in a setup with PHB -> device (no switch), if the device driver
requests a fundamental reset, we should do a PERST at the PHB level (are
we ?) and thus restore things in a similar way.
> Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++++++++++++++----
> 1 files changed, 144 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
> index 55943fc..016588a 100644
> --- a/arch/powerpc/kernel/eeh_pe.c
> +++ b/arch/powerpc/kernel/eeh_pe.c
> @@ -22,6 +22,7 @@
> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> */
>
> +#include <linux/delay.h>
> #include <linux/export.h>
> #include <linux/gfp.h>
> #include <linux/init.h>
> @@ -567,30 +568,132 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
> eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
> }
>
> -/**
> - * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
> - * @data: EEH device
> - * @flag: Unused
> +/*
> + * Some PCI bridges (e.g. PLX bridges) have primary/secondary
> + * buses assigned explicitly by firmware, and we probably have
> + * lost that after reset. So we have to delay the check until
> + * the PCI-CFG registers have been restored for the parent
> + * bridge.
> *
> - * Loads the PCI configuration space base address registers,
> - * the expansion ROM base address, the latency timer, and etc.
> - * from the saved values in the device node.
> + * Don't use normal PCI-CFG accessors, which probably has been
> + * blocked on normal path during the stage. So we need utilize
> + * eeh operations, which is always permitted.
> */
> -static void *eeh_restore_one_device_bars(void *data, void *flag)
> +static void eeh_bridge_check_link(struct pci_dev *pdev,
> + struct device_node *dn)
> +{
> + int cap;
> + uint32_t val;
> + int timeout = 0;
> +
> + /*
> + * We only check root port and downstream ports of
> + * PCIe switches
> + */
> + if (!pci_is_pcie(pdev) ||
> + (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
> + pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
> + return;
> +
> + pr_debug("%s: Check PCIe link for %s ...\n",
> + __func__, pci_name(pdev));
> +
> + /* Check slot status */
> + cap = pdev->pcie_cap;
> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
> + if (!(val & PCI_EXP_SLTSTA_PDS)) {
> + pr_debug(" No card in the slot (0x%04x) !\n", val);
> + return;
> + }
> +
> + /* Check power status if we have the capability */
> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
> + if (val & PCI_EXP_SLTCAP_PCP) {
> + eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
> + if (val & PCI_EXP_SLTCTL_PCC) {
> + pr_debug(" In power-off state, power it on ...\n");
> + val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
> + val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
> + eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
> + msleep(2 * 1000);
> + }
> + }
> +
> + /* Enable link */
> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
> + val &= ~PCI_EXP_LNKCTL_LD;
> + eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
> +
> + /* Check link */
> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
> + if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
> + pr_debug(" No link reporting capability (0x%08x) \n", val);
> + msleep(1000);
> + return;
> + }
> +
> + /* Wait the link is up until timeout (5s) */
> + timeout = 0;
> + while (timeout < 5000) {
> + msleep(20);
> + timeout += 20;
> +
> + eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
> + if (val & PCI_EXP_LNKSTA_DLLLA)
> + break;
> + }
> +
> + if (val & PCI_EXP_LNKSTA_DLLLA)
> + pr_debug(" Link up (%s)\n",
> + (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
> + else
> + pr_debug(" Link not ready (0x%04x)\n", val);
> +}
> +
> +#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
> +#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
> +
> +static void eeh_restore_bridge_bars(struct pci_dev *pdev,
> + struct eeh_dev *edev,
> + struct device_node *dn)
> +{
> + int i;
> +
> + /*
> + * Device BARs: 0x10 - 0x18
> + * Bus numbers and windows: 0x18 - 0x30
> + */
> + for (i = 4; i < 13; i++)
> + eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
> + /* Rom: 0x38 */
> + eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
> +
> + /* Cache line & Latency timer: 0xC 0xD */
> + eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
> + SAVED_BYTE(PCI_CACHE_LINE_SIZE));
> + eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
> + SAVED_BYTE(PCI_LATENCY_TIMER));
> + /* Max latency, min grant, interrupt ping and line: 0x3C */
> + eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
> +
> + /* PCI Command: 0x4 */
> + eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
> +
> + /* Check the PCIe link is ready */
> + eeh_bridge_check_link(pdev, dn);
> +}
> +
> +static void eeh_restore_device_bars(struct eeh_dev *edev,
> + struct device_node *dn)
> {
> int i;
> u32 cmd;
> - struct eeh_dev *edev = (struct eeh_dev *)data;
> - struct device_node *dn = eeh_dev_to_of_node(edev);
>
> for (i = 4; i < 10; i++)
> eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
> /* 12 == Expansion ROM Address */
> eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
>
> -#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
> -#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
> -
> eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
> SAVED_BYTE(PCI_CACHE_LINE_SIZE));
> eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
> @@ -613,6 +716,34 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
> else
> cmd &= ~PCI_COMMAND_SERR;
> eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
> +}
> +
> +/**
> + * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
> + * @data: EEH device
> + * @flag: Unused
> + *
> + * Loads the PCI configuration space base address registers,
> + * the expansion ROM base address, the latency timer, and etc.
> + * from the saved values in the device node.
> + */
> +static void *eeh_restore_one_device_bars(void *data, void *flag)
> +{
> + struct pci_dev *pdev = NULL;
> + struct eeh_dev *edev = (struct eeh_dev *)data;
> + struct device_node *dn = eeh_dev_to_of_node(edev);
> +
> + /* Trace the PCI bridge */
> + if (eeh_probe_mode_dev()) {
> + pdev = eeh_dev_to_pci_dev(edev);
> + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
> + pdev = NULL;
> + }
> +
> + if (pdev)
> + eeh_restore_bridge_bars(pdev, edev, dn);
> + else
> + eeh_restore_device_bars(edev, dn);
>
> return NULL;
> }
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Benjamin Herrenschmidt @ 2013-06-25 11:56 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <1372154461-29674-2-git-send-email-shangw@linux.vnet.ibm.com>
On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
> + pci_regs_buf[0] = 0;
> + eeh_pe_for_each_dev(pe, edev) {
> + loglen += eeh_gather_pci_data(edev, pci_regs_buf,
> + EEH_PCI_REGS_LOG_LEN);
> + }
> + }
Unless I'm mistaken, this is buggy and will overwrite the content of
pci_regs_buf for every device (they will all write over the same
portion of the log).
Ben.
^ permalink raw reply
* Re: [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Benjamin Herrenschmidt @ 2013-06-25 11:55 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <1372154461-29674-2-git-send-email-shangw@linux.vnet.ibm.com>
On Tue, 2013-06-25 at 18:00 +0800, Gavin Shan wrote:
> + /*
> + * When the PHB is fenced or dead, it's pointless to collect
> + * the data from PCI config space because it should return
> + * 0xFF's. For ER, we still retrieve the data from the PCI
> + * config space.
> + */
> + if (eeh_probe_mode_dev() &&
> + (pe->type & EEH_PE_PHB) &&
> + (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
> + valid_cfg_log = false;
> +
I'm still unsure about that one. EEH_PE_ISOLATED could be the result
of a normal ER of PE#0 (which can happen for various reasons other
than a fence) in which case the config space is available and
interesting.
I would either not bother and collect the FF's, or make this specific
to fence and only fence.
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 2/8] powerpc/perf: Rework disable logic in pmu_disable()
From: Anshuman Khandual @ 2013-06-25 11:22 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, sukadev, Paul Mackerras
In-Reply-To: <1372073336-8189-2-git-send-email-michael@ellerman.id.au>
On 06/24/2013 04:58 PM, Michael Ellerman wrote:
> In pmu_disable() we disable the PMU by setting the FC (Freeze Counters)
> bit in MMCR0. In order to do this we have to read/modify/write MMCR0.
>
> It's possible that we read a value from MMCR0 which has PMAO (PMU Alert
> Occurred) set. When we write that value back it will cause an interrupt
> to occur. We will then end up in the PMU interrupt handler even though
> we are supposed to have just disabled the PMU.
>
Is that possible ? First of all MMCR0[PMAO] could not be written by SW.
Even if you try writing it, how its going to generate PMU interrupt ?
HW sets this bit MMCR0[PMAO] after a PMU interrupt has already occurred
not that if we set this, a PMU interrupt would be generated.
> We can avoid this by making sure we never write PMAO back. We should not
Making sure that we dont write PMAO back is a good idea though.
> lose interrupts because when the PMU is re-enabled the overflowed values
> will cause another interrupt.
>
I doubt this theory.
> We also reorder the clearing of SAMPLE_ENABLE so that is done after the
> PMU is frozen. Otherwise there is a small window between the clearing of
> SAMPLE_ENABLE and the setting of FC where we could take an interrupt and
> incorrectly see SAMPLE_ENABLE not set. This would for example change the
> logic in perf_read_regs().
>
Agreed
^ permalink raw reply
* Re: [PATCH 1/8] powerpc/perf: Check that events only include valid bits on Power8
From: Anshuman Khandual @ 2013-06-25 10:55 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, sukadev, Paul Mackerras
In-Reply-To: <1372073336-8189-1-git-send-email-michael@ellerman.id.au>
On 06/24/2013 04:58 PM, Michael Ellerman wrote:
> A mistake we have made in the past is that we pull out the fields we
> need from the event code, but don't check that there are no unknown bits
> set. This means that we can't ever assign meaning to those unknown bits
> in future.
>
> Although we have once again failed to do this at release, it is still
> early days for Power8 so I think we can still slip this in and get away
> with it.
>
> Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Reviewed-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
^ permalink raw reply
* Re: [RFC PATCH 1/3] mm/cma: Move dma contiguous changes into a seperate config
From: Anshuman Khandual @ 2013-06-25 10:15 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linux-mm, paulus, linuxppc-dev
In-Reply-To: <1372062327-7028-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
> diff --git a/drivers/base/Makefile b/drivers/base/Makefile
> index 4e22ce3..5d93bb5 100644
> --- a/drivers/base/Makefile
> +++ b/drivers/base/Makefile
> @@ -6,7 +6,7 @@ obj-y := core.o bus.o dd.o syscore.o \
> attribute_container.o transport_class.o \
> topology.o
> obj-$(CONFIG_DEVTMPFS) += devtmpfs.o
> -obj-$(CONFIG_CMA) += dma-contiguous.o
> +obj-$(CONFIG_DMA_CMA) += dma-contiguous.o
> obj-y += power/
> obj-$(CONFIG_HAS_DMA) += dma-mapping.o
> obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o
> diff --git a/include/linux/dma-contiguous.h b/include/linux/dma-contiguous.h
> index 01b5c84..00141d3 100644
> --- a/include/linux/dma-contiguous.h
> +++ b/include/linux/dma-contiguous.h
> @@ -57,7 +57,7 @@ struct cma;
> struct page;
> struct device;
>
> -#ifdef CONFIG_CMA
> +#ifdef CONFIG_DMA_CMA
>
We have some generic CMA documentation available in this file which need
to be moved to a more generic place (generic MM) as we are differentiating
it from DMA specific usage. Ideally we should have two documentation
(1) CMA usage for any subsystem
(2) DMA specific CMA usage
> /*
> * There is always at least global CMA area and a few optional device
> diff --git a/mm/Kconfig b/mm/Kconfig
> index e742d06..b362369 100644
> --- a/mm/Kconfig
> +++ b/mm/Kconfig
> @@ -477,3 +477,23 @@ config FRONTSWAP
> and swap data is stored as normal on the matching swap device.
>
> If unsure, say Y to enable frontswap.
> +
> +config CMA
> + bool "Contiguous Memory Allocator"
> + depends on HAVE_MEMBLOCK
> + select MIGRATION
> + select MEMORY_ISOLATION
> + help
> + This enables the Contiguous Memory Allocator which allows other
> + subsystem to allocate big physically-contiguous blocks of memory
Should be "any subsystem" instead of "other subsystem"
> +
> + If unsure, say "n".
> +
> +config CMA_DEBUG
> + bool "CMA debug messages (DEVELOPMENT)"
> + depends on DEBUG_KERNEL && CMA
> + help
> + Turns on debug messages in CMA. This produces KERN_DEBUG
> + messages for every CMA call as well as various messages while
> + processing calls such as dma_alloc_from_contiguous().
> + This option does not affect warning and error messages.
>
We should probably split up these debug configs as well to differentiate between
generic CMA_DEBUG and DMA_CMA_DEBUG options.
Regards
Anshuman
^ permalink raw reply
* [PATCH 4/6] powerpc/eeh: Fix address catch for PowerNV
From: Gavin Shan @ 2013-06-25 10:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
On the PowerNV platform, the EEH address cache isn't built correctly
because we skipped the EEH devices without binding PE. The patch
fixes that.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh_cache.c | 2 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 1 +
2 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 1d5d9a6..858ebea 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -194,7 +194,7 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
}
/* Skip any devices for which EEH is not enabled. */
- if (!edev->pe) {
+ if (!eeh_probe_mode_dev() && !edev->pe) {
#ifdef DEBUG
pr_info("PCI: skip building address cache for=%s - %s\n",
pci_name(dev), dn->full_name);
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 3e5c3d5..0ff9a3a 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -998,6 +998,7 @@ static void pnv_pci_ioda_fixup(void)
pnv_pci_ioda_create_dbgfs();
#ifdef CONFIG_EEH
+ eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
eeh_addr_cache_build();
eeh_init();
#endif
--
1.7.5.4
^ permalink raw reply related
* [PATCH 3/6] powerpc/powernv: Replace variables with flags
From: Gavin Shan @ 2013-06-25 10:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
We have 2 fields in "struct pnv_phb" to trace the states. The patch
replace the fields with one and introduces flags for that. The patch
doesn't impact the logic.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/eeh-ioda.c | 8 ++++----
arch/powerpc/platforms/powernv/pci.c | 4 ++--
arch/powerpc/platforms/powernv/pci.h | 7 +++++--
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 84f3036..85025d7 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -132,7 +132,7 @@ static int ioda_eeh_post_init(struct pci_controller *hose)
&ioda_eeh_dbgfs_ops);
#endif
- phb->eeh_enabled = 1;
+ phb->eeh_state |= PNV_EEH_STATE_ENABLED;
}
return 0;
@@ -815,7 +815,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
* removed, we needn't take care of it any more.
*/
phb = hose->private_data;
- if (phb->removed)
+ if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
continue;
rc = opal_pci_next_error(phb->opal_id,
@@ -850,7 +850,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
list_for_each_entry_safe(hose, tmp,
&hose_list, list_node) {
phb = hose->private_data;
- phb->removed = 1;
+ phb->eeh_state |= PNV_EEH_STATE_REMOVED;
}
WARN(1, "EEH: dead IOC detected\n");
@@ -867,7 +867,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
WARN(1, "EEH: dead PHB#%x detected\n",
hose->global_number);
- phb->removed = 1;
+ phb->eeh_state |= PNV_EEH_STATE_REMOVED;
ret = 3;
goto out;
} else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 6d9a506..1f31826 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -308,7 +308,7 @@ static int pnv_pci_read_config(struct pci_bus *bus,
if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
return PCIBIOS_SUCCESSFUL;
- if (phb->eeh_enabled) {
+ if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
if (*val == EEH_IO_ERROR_VALUE(size)) {
busdn = pci_bus_to_OF_node(bus);
for (dn = busdn->child; dn; dn = dn->sibling) {
@@ -358,7 +358,7 @@ static int pnv_pci_write_config(struct pci_bus *bus,
/* Check if the PHB got frozen due to an error (no response) */
#ifdef CONFIG_EEH
- if (!phb->eeh_enabled)
+ if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
pnv_pci_config_check_eeh(phb, bus, bdfn);
#else
pnv_pci_config_check_eeh(phb, bus, bdfn);
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 43906e3..40bdf02 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -78,6 +78,10 @@ struct pnv_eeh_ops {
int (*configure_bridge)(struct eeh_pe *pe);
int (*next_error)(struct eeh_pe **pe);
};
+
+#define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
+#define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
+
#endif /* CONFIG_EEH */
struct pnv_phb {
@@ -92,8 +96,7 @@ struct pnv_phb {
#ifdef CONFIG_EEH
struct pnv_eeh_ops *eeh_ops;
- int eeh_enabled;
- int removed;
+ int eeh_state;
#endif
#ifdef CONFIG_DEBUG_FS
--
1.7.5.4
^ permalink raw reply related
* [PATCH v2 00/6] Follow-up fixes for EEH on PowerNV
From: Gavin Shan @ 2013-06-25 10:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
The series of patches are follow-up in order to make EEH workable for PowerNV
platform on Juno-IOC-L machine. Couple of issues have been fixed with help of
Ben:
- Check PCIe link after PHB complete reset
- Restore config space for bridges
- The EEH address cache wasn't built successfully
- Misc cleanup on output messages
- Misc cleanup on EEH flags maintained by "struct pnv_phb"
- Misc cleanup on properties of functions to avoid build warnings
The series of patches have been verified on Juno-IOC-L machine:
Trigger frozen PE:
echo 0x0000000002000000 > /sys/kernel/debug/powerpc/PCI0000/err_injct
sleep 1
echo 0x0 > /sys/kernel/debug/powerpc/PCI0000/err_injct
Trigger fenced PHB:
echo 0x8000000000000000 > /sys/kernel/debug/powerpc/PCI0000/err_injct
Changelog:
v1 -> v2:
* Remove the mechanism to block PCI-CFG and MMIO.
* Add one patch to do cleanup on output messages.
* Add one patch to avoid build warnings.
* Split functions to restore BARs for PCI devices and bridges separately.
---
arch/powerpc/include/asm/eeh.h | 4 +-
arch/powerpc/kernel/eeh.c | 43 ++++++--
arch/powerpc/kernel/eeh_cache.c | 4 +-
arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++---
arch/powerpc/platforms/powernv/eeh-ioda.c | 33 ++++---
arch/powerpc/platforms/powernv/pci-ioda.c | 1 +
arch/powerpc/platforms/powernv/pci.c | 4 +-
arch/powerpc/platforms/powernv/pci.h | 7 +-
8 files changed, 207 insertions(+), 46 deletions(-)
Thanks,
Gavin
^ permalink raw reply
* [PATCH 5/6] powerpc/eeh: Refactor the output message
From: Gavin Shan @ 2013-06-25 10:01 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
We needn't the the whole backtrace other than one-line message in
the error reporting interrupt handler. For errors triggered by
access PCI config space or MMIO, we replace "WARN(1, ...)" with
pr_err() and dump_stack().
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh.c | 9 +++++++--
arch/powerpc/platforms/powernv/eeh-ioda.c | 25 ++++++++++++++++---------
2 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 60deb42..38e4b40 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -324,7 +324,9 @@ static int eeh_phb_check_failure(struct eeh_pe *pe)
eeh_serialize_unlock(flags);
eeh_send_failure_event(phb_pe);
- WARN(1, "EEH: PHB failure detected\n");
+ pr_err("EEH: PHB#%x failure detected\n",
+ phb_pe->phb->global_number);
+ dump_stack();
return 1;
out:
@@ -453,7 +455,10 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
* a stack trace will help the device-driver authors figure
* out what happened. So print that out.
*/
- WARN(1, "EEH: failure detected\n");
+ pr_err("EEH: Frozen PE#%x detected on PHB#%x\n",
+ pe->addr, pe->phb->global_number);
+ dump_stack();
+
return 1;
dn_unlock:
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index 85025d7..0cd1c4a 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -853,11 +853,14 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
phb->eeh_state |= PNV_EEH_STATE_REMOVED;
}
- WARN(1, "EEH: dead IOC detected\n");
+ pr_err("EEH: dead IOC detected\n");
ret = 4;
goto out;
- } else if (severity == OPAL_EEH_SEV_INF)
+ } else if (severity == OPAL_EEH_SEV_INF) {
+ pr_info("EEH: IOC informative error "
+ "detected\n");
ioda_eeh_hub_diag(hose);
+ }
break;
case OPAL_EEH_PHB_ERROR:
@@ -865,8 +868,8 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
if (ioda_eeh_get_phb_pe(hose, pe))
break;
- WARN(1, "EEH: dead PHB#%x detected\n",
- hose->global_number);
+ pr_err("EEH: dead PHB#%x detected\n",
+ hose->global_number);
phb->eeh_state |= PNV_EEH_STATE_REMOVED;
ret = 3;
goto out;
@@ -874,20 +877,24 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
if (ioda_eeh_get_phb_pe(hose, pe))
break;
- WARN(1, "EEH: fenced PHB#%x detected\n",
- hose->global_number);
+ pr_err("EEH: fenced PHB#%x detected\n",
+ hose->global_number);
ret = 2;
goto out;
- } else if (severity == OPAL_EEH_SEV_INF)
+ } else if (severity == OPAL_EEH_SEV_INF) {
+ pr_info("EEH: PHB#%x informative error "
+ "detected\n",
+ hose->global_number);
ioda_eeh_phb_diag(hose);
+ }
break;
case OPAL_EEH_PE_ERROR:
if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
break;
- WARN(1, "EEH: Frozen PE#%x on PHB#%x detected\n",
- (*pe)->addr, (*pe)->phb->global_number);
+ pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
+ (*pe)->addr, (*pe)->phb->global_number);
ret = 1;
goto out;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCH 6/6] powerpc/eeh: Avoid build warnings
From: Gavin Shan @ 2013-06-25 10:01 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
The patch is for avoiding following build warnings:
The function .pnv_pci_ioda_fixup() references
the function __init .eeh_init().
This is often because .pnv_pci_ioda_fixup lacks a __init
The function .pnv_pci_ioda_fixup() references
the function __init .eeh_addr_cache_build().
This is often because .pnv_pci_ioda_fixup lacks a __init
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/eeh.h | 4 ++--
arch/powerpc/kernel/eeh.c | 2 +-
arch/powerpc/kernel/eeh_cache.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index dd65e31..09a8743 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -202,13 +202,13 @@ struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
void *eeh_dev_init(struct device_node *dn, void *data);
void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
-int __init eeh_init(void);
+int eeh_init(void);
int __init eeh_ops_register(struct eeh_ops *ops);
int __exit eeh_ops_unregister(const char *name);
unsigned long eeh_check_failure(const volatile void __iomem *token,
unsigned long val);
int eeh_dev_check_failure(struct eeh_dev *edev);
-void __init eeh_addr_cache_build(void);
+void eeh_addr_cache_build(void);
void eeh_add_device_tree_early(struct device_node *);
void eeh_add_device_tree_late(struct pci_bus *);
void eeh_add_sysfs_files(struct pci_bus *);
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 38e4b40..f055e6f 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -751,7 +751,7 @@ int __exit eeh_ops_unregister(const char *name)
* Even if force-off is set, the EEH hardware is still enabled, so that
* newer systems can boot.
*/
-int __init eeh_init(void)
+int eeh_init(void)
{
struct pci_controller *hose, *tmp;
struct device_node *phb;
diff --git a/arch/powerpc/kernel/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 858ebea..ea9a94c 100644
--- a/arch/powerpc/kernel/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -285,7 +285,7 @@ void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
* Must be run late in boot process, after the pci controllers
* have been scanned for devices (after all device resources are known).
*/
-void __init eeh_addr_cache_build(void)
+void eeh_addr_cache_build(void)
{
struct device_node *dn;
struct eeh_dev *edev;
--
1.7.5.4
^ permalink raw reply related
* [PATCH 2/6] powerpc/eeh: Check PCIe link after reset
From: Gavin Shan @ 2013-06-25 10:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
After reset (e.g. complete reset) in order to bring the fenced PHB
back, the PCIe link might not be ready yet. The patch intends to
make sure the PCIe link is ready before accessing its subordinate
PCI devices. The patch also fixes that wrong values restored to
PCI_COMMAND register for PCI bridges.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh_pe.c | 157 ++++++++++++++++++++++++++++++++++++++----
1 files changed, 144 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index 55943fc..016588a 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -22,6 +22,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gfp.h>
#include <linux/init.h>
@@ -567,30 +568,132 @@ void eeh_pe_state_clear(struct eeh_pe *pe, int state)
eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
}
-/**
- * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
- * @data: EEH device
- * @flag: Unused
+/*
+ * Some PCI bridges (e.g. PLX bridges) have primary/secondary
+ * buses assigned explicitly by firmware, and we probably have
+ * lost that after reset. So we have to delay the check until
+ * the PCI-CFG registers have been restored for the parent
+ * bridge.
*
- * Loads the PCI configuration space base address registers,
- * the expansion ROM base address, the latency timer, and etc.
- * from the saved values in the device node.
+ * Don't use normal PCI-CFG accessors, which probably has been
+ * blocked on normal path during the stage. So we need utilize
+ * eeh operations, which is always permitted.
*/
-static void *eeh_restore_one_device_bars(void *data, void *flag)
+static void eeh_bridge_check_link(struct pci_dev *pdev,
+ struct device_node *dn)
+{
+ int cap;
+ uint32_t val;
+ int timeout = 0;
+
+ /*
+ * We only check root port and downstream ports of
+ * PCIe switches
+ */
+ if (!pci_is_pcie(pdev) ||
+ (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
+ pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
+ return;
+
+ pr_debug("%s: Check PCIe link for %s ...\n",
+ __func__, pci_name(pdev));
+
+ /* Check slot status */
+ cap = pdev->pcie_cap;
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
+ if (!(val & PCI_EXP_SLTSTA_PDS)) {
+ pr_debug(" No card in the slot (0x%04x) !\n", val);
+ return;
+ }
+
+ /* Check power status if we have the capability */
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
+ if (val & PCI_EXP_SLTCAP_PCP) {
+ eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
+ if (val & PCI_EXP_SLTCTL_PCC) {
+ pr_debug(" In power-off state, power it on ...\n");
+ val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
+ val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
+ eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
+ msleep(2 * 1000);
+ }
+ }
+
+ /* Enable link */
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
+ val &= ~PCI_EXP_LNKCTL_LD;
+ eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
+
+ /* Check link */
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
+ if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
+ pr_debug(" No link reporting capability (0x%08x) \n", val);
+ msleep(1000);
+ return;
+ }
+
+ /* Wait the link is up until timeout (5s) */
+ timeout = 0;
+ while (timeout < 5000) {
+ msleep(20);
+ timeout += 20;
+
+ eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
+ if (val & PCI_EXP_LNKSTA_DLLLA)
+ break;
+ }
+
+ if (val & PCI_EXP_LNKSTA_DLLLA)
+ pr_debug(" Link up (%s)\n",
+ (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
+ else
+ pr_debug(" Link not ready (0x%04x)\n", val);
+}
+
+#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
+#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
+
+static void eeh_restore_bridge_bars(struct pci_dev *pdev,
+ struct eeh_dev *edev,
+ struct device_node *dn)
+{
+ int i;
+
+ /*
+ * Device BARs: 0x10 - 0x18
+ * Bus numbers and windows: 0x18 - 0x30
+ */
+ for (i = 4; i < 13; i++)
+ eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
+ /* Rom: 0x38 */
+ eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
+
+ /* Cache line & Latency timer: 0xC 0xD */
+ eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
+ SAVED_BYTE(PCI_CACHE_LINE_SIZE));
+ eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
+ SAVED_BYTE(PCI_LATENCY_TIMER));
+ /* Max latency, min grant, interrupt ping and line: 0x3C */
+ eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
+
+ /* PCI Command: 0x4 */
+ eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
+
+ /* Check the PCIe link is ready */
+ eeh_bridge_check_link(pdev, dn);
+}
+
+static void eeh_restore_device_bars(struct eeh_dev *edev,
+ struct device_node *dn)
{
int i;
u32 cmd;
- struct eeh_dev *edev = (struct eeh_dev *)data;
- struct device_node *dn = eeh_dev_to_of_node(edev);
for (i = 4; i < 10; i++)
eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
/* 12 == Expansion ROM Address */
eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
-#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
-#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
-
eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
SAVED_BYTE(PCI_CACHE_LINE_SIZE));
eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
@@ -613,6 +716,34 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
else
cmd &= ~PCI_COMMAND_SERR;
eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
+}
+
+/**
+ * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
+ * @data: EEH device
+ * @flag: Unused
+ *
+ * Loads the PCI configuration space base address registers,
+ * the expansion ROM base address, the latency timer, and etc.
+ * from the saved values in the device node.
+ */
+static void *eeh_restore_one_device_bars(void *data, void *flag)
+{
+ struct pci_dev *pdev = NULL;
+ struct eeh_dev *edev = (struct eeh_dev *)data;
+ struct device_node *dn = eeh_dev_to_of_node(edev);
+
+ /* Trace the PCI bridge */
+ if (eeh_probe_mode_dev()) {
+ pdev = eeh_dev_to_pci_dev(edev);
+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
+ pdev = NULL;
+ }
+
+ if (pdev)
+ eeh_restore_bridge_bars(pdev, edev, dn);
+ else
+ eeh_restore_device_bars(edev, dn);
return NULL;
}
--
1.7.5.4
^ permalink raw reply related
* [PATCH 1/6] powerpc/eeh: Don't collect PCI-CFG data on PHB
From: Gavin Shan @ 2013-06-25 10:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
In-Reply-To: <1372154461-29674-1-git-send-email-shangw@linux.vnet.ibm.com>
When the PHB is fenced or dead, it's pointless to collect the data
from PCI config space of subordinate PCI devices since it should
return 0xFF's. It also has potential risk to incur additional errors.
The patch avoids collecting PCI-CFG data while PHB is in fenced or
dead state.
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh.c | 34 ++++++++++++++++++++++++----------
1 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 951a632..60deb42 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -232,16 +232,30 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
{
size_t loglen = 0;
struct eeh_dev *edev;
+ bool valid_cfg_log = true;
- eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
- eeh_ops->configure_bridge(pe);
- eeh_pe_restore_bars(pe);
-
- pci_regs_buf[0] = 0;
- eeh_pe_for_each_dev(pe, edev) {
- loglen += eeh_gather_pci_data(edev, pci_regs_buf,
- EEH_PCI_REGS_LOG_LEN);
- }
+ /*
+ * When the PHB is fenced or dead, it's pointless to collect
+ * the data from PCI config space because it should return
+ * 0xFF's. For ER, we still retrieve the data from the PCI
+ * config space.
+ */
+ if (eeh_probe_mode_dev() &&
+ (pe->type & EEH_PE_PHB) &&
+ (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
+ valid_cfg_log = false;
+
+ if (valid_cfg_log) {
+ eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+ eeh_ops->configure_bridge(pe);
+ eeh_pe_restore_bars(pe);
+
+ pci_regs_buf[0] = 0;
+ eeh_pe_for_each_dev(pe, edev) {
+ loglen += eeh_gather_pci_data(edev, pci_regs_buf,
+ EEH_PCI_REGS_LOG_LEN);
+ }
+ }
eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
}
--
1.7.5.4
^ permalink raw reply related
* Re: [PATCH 2/2] powerpc/hw_brk: Fix clearing of extraneous IRQ
From: Anshuman Khandual @ 2013-06-25 8:59 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, Edjunior Barbosa Machado
In-Reply-To: <1372052843-19109-2-git-send-email-mikey@neuling.org>
On 06/24/2013 11:17 AM, Michael Neuling wrote:
> In 9422de3 "powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint
> registers" we changed the way we mark extraneous irqs with this:
>
> - info->extraneous_interrupt = !((bp->attr.bp_addr <= dar) &&
> - (dar - bp->attr.bp_addr < bp->attr.bp_len));
> + if (!((bp->attr.bp_addr <= dar) &&
> + (dar - bp->attr.bp_addr < bp->attr.bp_len)))
> + info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
>
> Unfortunately this is bogus as it never clears extraneous IRQ if it's already
> set.
>
> This correctly clears extraneous IRQ before possibly setting it.
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/hw_brk: Fix setting of length for exact mode breakpoints
From: Anshuman Khandual @ 2013-06-25 8:48 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, Edjunior Barbosa Machado
In-Reply-To: <1372052843-19109-1-git-send-email-mikey@neuling.org>
On 06/24/2013 11:17 AM, Michael Neuling wrote:
> The smallest match region for both the DABR and DAWR is 8 bytes, so the
> kernel needs to filter matches when users want to look at regions smaller than
> this.
>
> Currently we set the length of PPC_BREAKPOINT_MODE_EXACT breakpoints to 8.
> This is wrong as in exact mode we should only match on 1 address, hence the
> length should be 1.
>
> This ensures that the kernel will filter out any exact mode hardware breakpoint
> matches on any addresses other than the requested one.
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
Reviewed-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
^ permalink raw reply
* Re: [PATCH 03/10] powerpc/eeh: Check PCIe link after reset
From: Gavin Shan @ 2013-06-25 8:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <1372147064.3944.200.camel@pasglop>
On Tue, Jun 25, 2013 at 05:57:44PM +1000, Benjamin Herrenschmidt wrote:
>On Tue, 2013-06-25 at 15:47 +0800, Gavin Shan wrote:
>> If we just have complete reset for fenced PHB, we need restore it
>> from the cache (edev->config_space[1]) instead of reading that from
>> hardware. Fenced PHB is the special case on PowerNV :-)
>
>Well not really...
>
>In general we can also end up doing a hard reset under pHyp, and bridges
>can lose their state as well, which means they need to be restored from
>cache.
>
>We don't see the real PHB, but we might see the bridges if we have a PE
>that contains a bridge, for example, a PCIe card with a switch on it.
>
>If we hard reset that (because the driver requested it) or if pHyp did a
>reset due to a fence behind the scene, that bridge *will* have lost its
>state and will need to be reconfigured too... or is RTAS doing it all ?
>
Ok. So that would be job of eeh_ops->configure_bridge(). On pSeries, it
should have done with that.
Thanks,
Gavin
^ permalink raw reply
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