* [PATCH 05/63] powerpc: Simplify logic in include/uapi/asm/elf.h
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <1375804940-22050-1-git-send-email-anton@samba.org>
Simplify things by putting all the 32bit and 64bit defines
together instead of in two spots.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/include/uapi/asm/elf.h | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index 05b8d56..89fa042 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -107,6 +107,11 @@ typedef elf_gregset_t32 compat_elf_gregset_t;
# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
# define ELF_NVSRHALFREG 32 /* Half the vsx registers */
# define ELF_GREG_TYPE elf_greg_t64
+# define ELF_ARCH EM_PPC64
+# define ELF_CLASS ELFCLASS64
+# define ELF_DATA ELFDATA2MSB
+typedef elf_greg_t64 elf_greg_t;
+typedef elf_gregset_t64 elf_gregset_t;
#else
# define ELF_NEVRREG 34 /* includes acc (as 2) */
# define ELF_NVRREG 33 /* includes vscr */
@@ -114,20 +119,10 @@ typedef elf_gregset_t32 compat_elf_gregset_t;
# define ELF_ARCH EM_PPC
# define ELF_CLASS ELFCLASS32
# define ELF_DATA ELFDATA2MSB
+typedef elf_greg_t32 elf_greg_t;
+typedef elf_gregset_t32 elf_gregset_t;
#endif /* __powerpc64__ */
-#ifndef ELF_ARCH
-# define ELF_ARCH EM_PPC64
-# define ELF_CLASS ELFCLASS64
-# define ELF_DATA ELFDATA2MSB
- typedef elf_greg_t64 elf_greg_t;
- typedef elf_gregset_t64 elf_gregset_t;
-#else
- /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
- typedef elf_greg_t32 elf_greg_t;
- typedef elf_gregset_t32 elf_gregset_t;
-#endif /* ELF_ARCH */
-
/* Floating point registers */
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
--
1.8.1.2
^ permalink raw reply related
* [PATCH 04/63] powerpc: Remove SAVE_VSRU and REST_VSRU macros
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <1375804940-22050-1-git-send-email-anton@samba.org>
We always use VMX loads and stores to manage the high 32
VSRs. Remove these unused macros.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/include/asm/ppc_asm.h | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 2f1b6c5..b5c85f1 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -219,19 +219,6 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
-/* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); STXVD2X(n+32,R##base,R##b)
-#define SAVE_2VSRSU(n,b,base) SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
-#define SAVE_4VSRSU(n,b,base) SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
-#define SAVE_8VSRSU(n,b,base) SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
-#define SAVE_16VSRSU(n,b,base) SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
-#define SAVE_32VSRSU(n,b,base) SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base) li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
-#define REST_2VSRSU(n,b,base) REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
-#define REST_4VSRSU(n,b,base) REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
-#define REST_8VSRSU(n,b,base) REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
-#define REST_16VSRSU(n,b,base) REST_8VSRSU(n,b,base); REST_8VSRSU(n+8,b,base)
-#define REST_32VSRSU(n,b,base) REST_16VSRSU(n,b,base); REST_16VSRSU(n+16,b,base)
/*
* b = base register for addressing, o = base offset from register of 1st EVR
--
1.8.1.2
^ permalink raw reply related
* [PATCH 03/63] powerpc: Wrap MSR macros with parentheses
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <1375804940-22050-1-git-send-email-anton@samba.org>
Not having parentheses around a macro is asking for trouble.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/include/asm/reg.h | 8 ++++----
arch/powerpc/include/asm/reg_booke.h | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6840e4..a312e0c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -115,10 +115,10 @@
#define MSR_64BIT MSR_SF
/* Server variant */
-#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
-#define MSR_KERNEL MSR_ | MSR_64BIT
-#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64 MSR_USER32 | MSR_64BIT
+#define MSR_ (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
+#define MSR_KERNEL (MSR_ | MSR_64BIT)
+#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
+#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
#elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_8xx)
/* Default MSR for kernel mode. */
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b417de3..ed8f836 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -29,10 +29,10 @@
#if defined(CONFIG_PPC_BOOK3E_64)
#define MSR_64BIT MSR_CM
-#define MSR_ MSR_ME | MSR_CE
-#define MSR_KERNEL MSR_ | MSR_64BIT
-#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
-#define MSR_USER64 MSR_USER32 | MSR_64BIT
+#define MSR_ (MSR_ME | MSR_CE)
+#define MSR_KERNEL (MSR_ | MSR_64BIT)
+#define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
+#define MSR_USER64 (MSR_USER32 | MSR_64BIT)
#elif defined (CONFIG_40x)
#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
--
1.8.1.2
^ permalink raw reply related
* [PATCH 02/63] powerpc: handle unaligned ldbrx/stdbrx
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <1375804940-22050-1-git-send-email-anton@samba.org>
Normally when we haven't implemented an alignment handler for
a load or store instruction the process will be terminated.
The alignment handler uses the DSISR (or a pseudo one) to locate
the right handler. Unfortunately ldbrx and stdbrx overlap lfs and
stfs so we incorrectly think ldbrx is an lfs and stdbrx is an
stfs.
This bug is particularly nasty - instead of terminating the
process we apply an incorrect fixup and continue on.
With more and more overlapping instructions we should stop
creating a pseudo DSISR and index using the instruction directly,
but for now add a special case to catch ldbrx/stdbrx.
Signed-off-by: Anton Blanchard <anton@samba.org>
Cc: <stable@vger.kernel.org>
---
arch/powerpc/kernel/align.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index ee5b690..52e5758 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -764,6 +764,16 @@ int fix_alignment(struct pt_regs *regs)
nb = aligninfo[instr].len;
flags = aligninfo[instr].flags;
+ /* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */
+ if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) {
+ nb = 8;
+ flags = LD+SW;
+ } else if (IS_XFORM(instruction) &&
+ ((instruction >> 1) & 0x3ff) == 660) {
+ nb = 8;
+ flags = ST+SW;
+ }
+
/* Byteswap little endian loads and stores */
swiz = 0;
if (regs->msr & MSR_LE) {
--
1.8.1.2
^ permalink raw reply related
* [PATCH 01/63] powerpc: Align p_toc
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <1375804940-22050-1-git-send-email-anton@samba.org>
p_toc is an 8 byte relative offset to the TOC that we place in the
text section. This means it is only 4 byte aligned where it should
be 8 byte aligned. Add an explicit alignment.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/kernel/head_64.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index b61363d..3d11d80 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -703,6 +703,7 @@ _GLOBAL(relative_toc)
mtlr r0
blr
+.balign 8
p_toc: .llong __toc_start + 0x8000 - 0b
/*
--
1.8.1.2
^ permalink raw reply related
* [PATCH 00/63] 64bit PowerPC little endian support
From: Anton Blanchard @ 2013-08-06 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras; +Cc: linuxppc-dev
This patchset adds support for building a 64bit PowerPC little
endian kernel.
binutils and gcc support (powerpcle/powerpc64le) is already
upstream. For gcc you can use gcc tip, or for the less adventurous
the gcc 4.8 branch works too.
QEMU patches to boot a little endian kernel will be posted over the
next day.
Anton
--
Alistair Popple (4):
powerpc: More little endian fixes for prom.c
powerpc: More little endian fixes for setup-common.c
powerpc: Little endian fixes for legacy_serial.c
powerpc: Make NUMA device node code endian safe
Anton Blanchard (53):
powerpc: Align p_toc
powerpc: handle unaligned ldbrx/stdbrx
powerpc: Wrap MSR macros with parentheses
powerpc: Remove SAVE_VSRU and REST_VSRU macros
powerpc: Simplify logic in include/uapi/asm/elf.h
powerpc/pseries: Simplify H_GET_TERM_CHAR
powerpc: Fix a number of sparse warnings
powerpc/pci: Don't use bitfield for force_32bit_msi
powerpc: Stop using non-architected shared_proc field in lppaca
powerpc: Make RTAS device tree accesses endian safe
powerpc: Make cache info device tree accesses endian safe
powerpc: Make RTAS calls endian safe
powerpc: Make logical to real cpu mapping code endian safe
powerpc: Add some endian annotations to time and xics code
powerpc: Fix some endian issues in xics code
powerpc: of_parse_dma_window should take a __be32 *dma_window
powerpc: Make device tree accesses in cache info code endian safe
powerpc: Make device tree accesses in HVC VIO console endian safe
powerpc: Make device tree accesses in VIO subsystem endian safe
powerpc: Make OF PCI device tree accesses endian safe
powerpc: Make PCI device node device tree accesses endian safe
powerpc: Add endian annotations to lppaca, slb_shadow and dtl_entry
powerpc: Fix little endian lppaca, slb_shadow and dtl_entry
powerpc: Emulate instructions in little endian mode
powerpc: Little endian SMP IPI demux
powerpc/pseries: Fix endian issues in H_GET_TERM_CHAR/H_PUT_TERM_CHAR
powerpc: Fix little endian coredumps
powerpc: Make rwlocks endian safe
powerpc: Fix endian issues in VMX copy loops
powerpc: Book 3S MMU little endian support
powerpc: Fix offset of FPRs in VSX registers in little endian builds
powerpc: PTRACE_PEEKUSR/PTRACE_POKEUSER of FPR registers in little
endian builds
powerpc: Little endian builds double word swap VSX state during
context save/restore
powerpc: Add little endian support for word-at-a-time functions
powerpc: Set MSR_LE bit on little endian builds
powerpc: Reset MSR_LE on signal entry
powerpc: Add endian safe trampoline to pseries secondary thread entry
pseries: Add H_SET_MODE to change exception endianness
powerpc/kvm/book3s_hv: Add little endian guest support
powerpc: Remove open coded byte swap macro in alignment handler
powerpc: Remove hard coded FP offsets in alignment handler
powerpc: Alignment handler shouldn't access VSX registers with TS_FPR
powerpc: Add little endian support to alignment handler
powerpc: Handle VSX alignment faults in little endian mode
ibmveth: Fix little endian issues
ibmvscsi: Fix little endian issues
[SCSI] lpfc: Don't force CONFIG_GENERIC_CSUM on
powerpc: Use generic checksum code in little endian
powerpc: Use generic memcpy code in little endian
powerpc: uname should return ppc64le/ppcle on little endian builds
powerpc: Don't set HAVE_EFFICIENT_UNALIGNED_ACCESS on little endian
builds
powerpc: Work around little endian gcc bug
powerpc: Add pseries_le_defconfig
Benjamin Herrenschmidt (2):
powerpc: Make prom_init.c endian safe
powerpc: endian safe trampoline
Ian Munsie (4):
powerpc: Make prom.c device tree accesses endian safe
powerpc: Support endian agnostic MMIO
powerpc: Include the appropriate endianness header
powerpc: Add ability to build little endian kernels
arch/powerpc/Kconfig | 5 +-
arch/powerpc/Makefile | 37 ++-
arch/powerpc/boot/Makefile | 3 +-
arch/powerpc/configs/pseries_le_defconfig | 347 ++++++++++++++++++++++++
arch/powerpc/include/asm/asm-compat.h | 9 +
arch/powerpc/include/asm/checksum.h | 5 +
arch/powerpc/include/asm/hvcall.h | 2 +
arch/powerpc/include/asm/io.h | 67 +++--
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/asm/lppaca.h | 68 +++--
arch/powerpc/include/asm/mmu-hash64.h | 4 +-
arch/powerpc/include/asm/paca.h | 5 +
arch/powerpc/include/asm/pci-bridge.h | 2 +-
arch/powerpc/include/asm/ppc-opcode.h | 3 +
arch/powerpc/include/asm/ppc_asm.h | 68 +++--
arch/powerpc/include/asm/processor.h | 12 +-
arch/powerpc/include/asm/prom.h | 5 +-
arch/powerpc/include/asm/reg.h | 13 +-
arch/powerpc/include/asm/reg_booke.h | 8 +-
arch/powerpc/include/asm/rtas.h | 8 +-
arch/powerpc/include/asm/spinlock.h | 6 +-
arch/powerpc/include/asm/string.h | 4 +
arch/powerpc/include/asm/word-at-a-time.h | 71 +++++
arch/powerpc/include/uapi/asm/byteorder.h | 4 +
arch/powerpc/include/uapi/asm/elf.h | 21 +-
arch/powerpc/kernel/align.c | 172 ++++++++----
arch/powerpc/kernel/asm-offsets.c | 1 +
arch/powerpc/kernel/cacheinfo.c | 12 +-
arch/powerpc/kernel/entry_64.S | 47 ++--
arch/powerpc/kernel/head_64.S | 4 +
arch/powerpc/kernel/legacy_serial.c | 8 +-
arch/powerpc/kernel/lparcfg.c | 14 +-
arch/powerpc/kernel/paca.c | 10 +-
arch/powerpc/kernel/pci-common.c | 10 +-
arch/powerpc/kernel/pci_64.c | 4 +-
arch/powerpc/kernel/pci_dn.c | 20 +-
arch/powerpc/kernel/pci_of_scan.c | 23 +-
arch/powerpc/kernel/ppc_ksyms.c | 4 +
arch/powerpc/kernel/prom.c | 64 ++---
arch/powerpc/kernel/prom_init.c | 253 +++++++++--------
arch/powerpc/kernel/prom_parse.c | 17 +-
arch/powerpc/kernel/ptrace.c | 8 +-
arch/powerpc/kernel/rtas.c | 66 ++---
arch/powerpc/kernel/setup-common.c | 13 +-
arch/powerpc/kernel/setup_64.c | 14 +-
arch/powerpc/kernel/signal_32.c | 3 +-
arch/powerpc/kernel/signal_64.c | 11 +-
arch/powerpc/kernel/smp.c | 21 +-
arch/powerpc/kernel/time.c | 18 +-
arch/powerpc/kernel/traps.c | 2 +-
arch/powerpc/kernel/vdso32/vdso32.lds.S | 4 +
arch/powerpc/kernel/vdso64/vdso64.lds.S | 4 +
arch/powerpc/kernel/vio.c | 33 ++-
arch/powerpc/kvm/book3s_64_mmu_hv.c | 2 +-
arch/powerpc/kvm/book3s_64_slb.S | 4 +
arch/powerpc/kvm/book3s_hv.c | 46 +++-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 4 +
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 27 +-
arch/powerpc/lib/Makefile | 18 +-
arch/powerpc/lib/copyuser_power7.S | 54 ++--
arch/powerpc/lib/locks.c | 4 +-
arch/powerpc/lib/memcpy_power7.S | 55 ++--
arch/powerpc/mm/fault.c | 6 +-
arch/powerpc/mm/hash_native_64.c | 46 ++--
arch/powerpc/mm/hash_utils_64.c | 40 ++-
arch/powerpc/mm/numa.c | 102 +++----
arch/powerpc/mm/slb.c | 9 +-
arch/powerpc/mm/subpage-prot.c | 4 +-
arch/powerpc/perf/core-book3s.c | 2 +-
arch/powerpc/platforms/Kconfig.cputype | 11 +
arch/powerpc/platforms/cell/iommu.c | 2 +-
arch/powerpc/platforms/powernv/opal.c | 2 +-
arch/powerpc/platforms/pseries/dtl.c | 2 +-
arch/powerpc/platforms/pseries/hotplug-cpu.c | 4 +-
arch/powerpc/platforms/pseries/hvconsole.c | 17 +-
arch/powerpc/platforms/pseries/iommu.c | 8 +-
arch/powerpc/platforms/pseries/lpar.c | 21 +-
arch/powerpc/platforms/pseries/plpar_wrappers.h | 50 ++--
arch/powerpc/platforms/pseries/processor_idle.c | 8 +-
arch/powerpc/platforms/pseries/pseries_energy.c | 4 +-
arch/powerpc/platforms/pseries/setup.c | 46 +++-
arch/powerpc/sysdev/xics/icp-native.c | 2 +-
arch/powerpc/sysdev/xics/xics-common.c | 10 +-
drivers/net/ethernet/ibm/ibmveth.c | 4 +-
drivers/net/ethernet/ibm/ibmveth.h | 19 +-
drivers/scsi/Kconfig | 1 -
drivers/scsi/ibmvscsi/ibmvscsi.c | 153 ++++++-----
drivers/scsi/ibmvscsi/viosrp.h | 46 ++--
drivers/tty/hvc/hvc_vio.c | 4 +-
89 files changed, 1697 insertions(+), 778 deletions(-)
create mode 100644 arch/powerpc/configs/pseries_le_defconfig
--
1.8.1.2
^ permalink raw reply
* Re: mm/slab: ppc: ubi: kmalloc_slab WARNING / PPC + UBI driver
From: Christoph Lameter @ 2013-08-06 14:57 UTC (permalink / raw)
To: Wladislav Wiebe
Cc: dedekind1, Mel Gorman, dwmw2, Pekka Enberg, linux-mm, linux-mtd,
linuxppc-dev
In-Reply-To: <5200A29C.9060702@gmail.com>
On Tue, 6 Aug 2013, Wladislav Wiebe wrote:
> ok, just saw in slab/for-linus branch that those stuff is reverted again..
No that was only for the 3.11 merge by Linus. The 3.12 patches have not
been put into pekkas tree.
^ permalink raw reply
* RE: [PATCH 5/6 v2] kvm: powerpc: booke: Add linux pte lookup like booke3s
From: Bhushan Bharat-R65777 @ 2013-08-06 14:46 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org, agraf@suse.de,
kvm-ppc@vger.kernel.org, kvm@vger.kernel.org
In-Reply-To: <1375730341.13074.38.camel@snotra.buserror.net>
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^ permalink raw reply
* [PATCH 5/6 v3] kvm: powerpc: keep only pte search logic in lookup_linux_pte
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
lookup_linux_pte() was searching for a pte and also sets access
flags is writable. This function now searches only pte while
access flag setting is done explicitly.
This pte lookup is not kvm specific, so moved to common code (asm/pgtable.h)
My Followup patch will use this on booke.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- New change
arch/powerpc/include/asm/pgtable.h | 23 +++++++++++++++++++++
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 38 +++++++++++-----------------------
2 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 690c8c2..d4d16ab 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -254,6 +254,29 @@ static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
}
#endif /* !CONFIG_HUGETLB_PAGE */
+static inline pte_t *lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
+ unsigned long *pte_sizep)
+{
+ pte_t *ptep;
+ unsigned long ps = *pte_sizep;
+ unsigned int shift;
+
+ ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
+ if (!ptep)
+ return __pte(0);
+ if (shift)
+ *pte_sizep = 1ul << shift;
+ else
+ *pte_sizep = PAGE_SIZE;
+
+ if (ps > *pte_sizep)
+ return __pte(0);
+
+ if (!pte_present(*ptep))
+ return __pte(0);
+
+ return ptep;
+}
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 105b00f..7e6200c 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -134,27 +134,6 @@ static void remove_revmap_chain(struct kvm *kvm, long pte_index,
unlock_rmap(rmap);
}
-static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
- int writing, unsigned long *pte_sizep)
-{
- pte_t *ptep;
- unsigned long ps = *pte_sizep;
- unsigned int shift;
-
- ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
- if (!ptep)
- return __pte(0);
- if (shift)
- *pte_sizep = 1ul << shift;
- else
- *pte_sizep = PAGE_SIZE;
- if (ps > *pte_sizep)
- return __pte(0);
- if (!pte_present(*ptep))
- return __pte(0);
- return kvmppc_read_update_linux_pte(ptep, writing);
-}
-
static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
{
asm volatile(PPC_RELEASE_BARRIER "" : : : "memory");
@@ -174,6 +153,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
unsigned long *physp, pte_size;
unsigned long is_io;
unsigned long *rmap;
+ pte_t *ptep;
pte_t pte;
unsigned int writing;
unsigned long mmu_seq;
@@ -233,8 +213,9 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags,
/* Look up the Linux PTE for the backing page */
pte_size = psize;
- pte = lookup_linux_pte(pgdir, hva, writing, &pte_size);
- if (pte_present(pte)) {
+ ptep = lookup_linux_pte(pgdir, hva, &pte_size);
+ if (pte_present(pte_val(*ptep))) {
+ pte = kvmppc_read_update_linux_pte(ptep, writing);
if (writing && !pte_write(pte))
/* make the actual HPTE be read-only */
ptel = hpte_make_readonly(ptel);
@@ -662,6 +643,7 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
unsigned long psize, gfn, hva;
struct kvm_memory_slot *memslot;
pgd_t *pgdir = vcpu->arch.pgdir;
+ pte_t *ptep;
pte_t pte;
psize = hpte_page_size(v, r);
@@ -669,9 +651,13 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
memslot = __gfn_to_memslot(kvm_memslots(kvm), gfn);
if (memslot) {
hva = __gfn_to_hva_memslot(memslot, gfn);
- pte = lookup_linux_pte(pgdir, hva, 1, &psize);
- if (pte_present(pte) && !pte_write(pte))
- r = hpte_make_readonly(r);
+ ptep = lookup_linux_pte(pgdir, hva, &psize);
+ if (pte_present(pte_val(*ptep))) {
+ pte = kvmppc_read_update_linux_pte(ptep,
+ 1);
+ if (pte_present(pte) && !pte_write(pte))
+ r = hpte_make_readonly(r);
+ }
}
}
}
--
1.7.0.4
^ permalink raw reply related
* [PATCH 6/6 v3] kvm: powerpc: use caching attributes as per linux pte
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
KVM uses same WIM tlb attributes as the corresponding qemu pte.
For this we now search the linux pte for the requested page and
get these cache caching/coherency attributes from pte.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- setting pgdir before kvmppc_fix_ee_before_entry() on vcpu_run
- Aligned as per changes in patch 5/6
- setting WIMG for pfnmap pages also
v1->v2
- Use Linux pte for wimge rather than RAM/no-RAM mechanism
arch/powerpc/include/asm/kvm_host.h | 2 +-
arch/powerpc/kvm/booke.c | 2 +-
arch/powerpc/kvm/e500.h | 8 ++++--
arch/powerpc/kvm/e500_mmu_host.c | 36 ++++++++++++++++++++--------------
4 files changed, 28 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 3328353..583d405 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -535,6 +535,7 @@ struct kvm_vcpu_arch {
#endif
gpa_t paddr_accessed;
gva_t vaddr_accessed;
+ pgd_t *pgdir;
u8 io_gpr; /* GPR used as IO source/target */
u8 mmio_is_bigendian;
@@ -592,7 +593,6 @@ struct kvm_vcpu_arch {
struct list_head run_list;
struct task_struct *run_task;
struct kvm_run *kvm_run;
- pgd_t *pgdir;
spinlock_t vpa_update_lock;
struct kvmppc_vpa vpa;
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 17722d8..0d96d50 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -696,8 +696,8 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
kvmppc_load_guest_fp(vcpu);
#endif
+ vcpu->arch.pgdir = current->mm->pgd;
kvmppc_fix_ee_before_entry();
-
ret = __kvmppc_vcpu_run(kvm_run, vcpu);
/* No need for kvm_guest_exit. It's done in handle_exit.
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 4fd9650..fc4b2f6 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -31,11 +31,13 @@ enum vcpu_ftr {
#define E500_TLB_NUM 2
/* entry is mapped somewhere in host TLB */
-#define E500_TLB_VALID (1 << 0)
+#define E500_TLB_VALID (1 << 31)
/* TLB1 entry is mapped by host TLB1, tracked by bitmaps */
-#define E500_TLB_BITMAP (1 << 1)
+#define E500_TLB_BITMAP (1 << 30)
/* TLB1 entry is mapped by host TLB0 */
-#define E500_TLB_TLB0 (1 << 2)
+#define E500_TLB_TLB0 (1 << 29)
+/* Lower 5 bits have WIMGE value */
+#define E500_TLB_WIMGE_MASK (0x1f)
struct tlbe_ref {
pfn_t pfn; /* valid only for TLB0, except briefly */
diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 1c6a9d7..001a2b0 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -64,15 +64,6 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode)
return mas3;
}
-static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode)
-{
-#ifdef CONFIG_SMP
- return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M;
-#else
- return mas2 & MAS2_ATTRIB_MASK;
-#endif
-}
-
/*
* writing shadow tlb entry to host TLB
*/
@@ -248,10 +239,12 @@ static inline int tlbe_is_writable(struct kvm_book3e_206_tlb_entry *tlbe)
static inline void kvmppc_e500_ref_setup(struct tlbe_ref *ref,
struct kvm_book3e_206_tlb_entry *gtlbe,
- pfn_t pfn)
+ pfn_t pfn, int wimg)
{
ref->pfn = pfn;
ref->flags |= E500_TLB_VALID;
+ /* Use guest supplied MAS2_G and MAS2_E */
+ ref->flags |= (gtlbe->mas2 & MAS2_ATTRIB_MASK) | wimg;
if (tlbe_is_writable(gtlbe))
kvm_set_pfn_dirty(pfn);
@@ -312,8 +305,7 @@ static void kvmppc_e500_setup_stlbe(
/* Force IPROT=0 for all guest mappings. */
stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID;
- stlbe->mas2 = (gvaddr & MAS2_EPN) |
- e500_shadow_mas2_attrib(gtlbe->mas2, pr);
+ stlbe->mas2 = (gvaddr & MAS2_EPN) | (ref->flags & E500_TLB_WIMGE_MASK);
stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) |
e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);
@@ -332,6 +324,10 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
unsigned long hva;
int pfnmap = 0;
int tsize = BOOK3E_PAGESZ_4K;
+ unsigned long tsize_pages = 0;
+ pte_t *ptep;
+ int wimg = 0;
+ pgd_t *pgdir;
/*
* Translate guest physical to true physical, acquiring
@@ -394,7 +390,7 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
*/
for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
- unsigned long gfn_start, gfn_end, tsize_pages;
+ unsigned long gfn_start, gfn_end;
tsize_pages = 1 << (tsize - 2);
gfn_start = gfn & ~(tsize_pages - 1);
@@ -436,7 +432,8 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
}
if (likely(!pfnmap)) {
- unsigned long tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
+ tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);
+
pfn = gfn_to_pfn_memslot(slot, gfn);
if (is_error_noslot_pfn(pfn)) {
printk(KERN_ERR "Couldn't get real page for gfn %lx!\n",
@@ -449,7 +446,16 @@ static inline int kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
gvaddr &= ~((tsize_pages << PAGE_SHIFT) - 1);
}
- kvmppc_e500_ref_setup(ref, gtlbe, pfn);
+ pgdir = vcpu_e500->vcpu.arch.pgdir;
+ ptep = lookup_linux_pte(pgdir, hva, &tsize_pages);
+ if (pte_present(*ptep)) {
+ wimg = (pte_val(*ptep) >> PTE_WIMGE_SHIFT) & MAS2_WIMGE_MASK;
+ } else {
+ printk(KERN_ERR "pte not present: gfn %lx, pfn %lx\n",
+ (long)gfn, pfn);
+ return -EINVAL;
+ }
+ kvmppc_e500_ref_setup(ref, gtlbe, pfn, wimg);
kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize,
ref, gvaddr, stlbe);
--
1.7.0.4
^ permalink raw reply related
* [PATCH 4/6 v3] powerpc: move linux pte/hugepte search to more generic file
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
Linux pte search functions find_linux_pte_or_hugepte() and
find_linux_pte() have nothing specific to 64bit anymore.
So they are move from pgtable-ppc64.h to asm/pgtable.h
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- no change
v1->v2
- This is a new change in this version
arch/powerpc/include/asm/pgtable-ppc64.h | 36 -----------------------------
arch/powerpc/include/asm/pgtable.h | 37 ++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index e3d55f6..d257d98 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -340,42 +340,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
void pgtable_cache_init(void);
-/*
- * find_linux_pte returns the address of a linux pte for a given
- * effective address and directory. If not found, it returns zero.
- */
-static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
-{
- pgd_t *pg;
- pud_t *pu;
- pmd_t *pm;
- pte_t *pt = NULL;
-
- pg = pgdir + pgd_index(ea);
- if (!pgd_none(*pg)) {
- pu = pud_offset(pg, ea);
- if (!pud_none(*pu)) {
- pm = pmd_offset(pu, ea);
- if (pmd_present(*pm))
- pt = pte_offset_kernel(pm, ea);
- }
- }
- return pt;
-}
-
-#ifdef CONFIG_HUGETLB_PAGE
-pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
- unsigned *shift);
-#else
-static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
- unsigned *shift)
-{
- if (shift)
- *shift = 0;
- return find_linux_pte(pgdir, ea);
-}
-#endif /* !CONFIG_HUGETLB_PAGE */
-
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index b6293d2..690c8c2 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -217,6 +217,43 @@ extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
unsigned long end, int write, struct page **pages, int *nr);
+
+/*
+ * find_linux_pte returns the address of a linux pte for a given
+ * effective address and directory. If not found, it returns zero.
+ */
+static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
+{
+ pgd_t *pg;
+ pud_t *pu;
+ pmd_t *pm;
+ pte_t *pt = NULL;
+
+ pg = pgdir + pgd_index(ea);
+ if (!pgd_none(*pg)) {
+ pu = pud_offset(pg, ea);
+ if (!pud_none(*pu)) {
+ pm = pmd_offset(pu, ea);
+ if (pmd_present(*pm))
+ pt = pte_offset_kernel(pm, ea);
+ }
+ }
+ return pt;
+}
+
+#ifdef CONFIG_HUGETLB_PAGE
+pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
+ unsigned *shift);
+#else
+static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
+ unsigned *shift)
+{
+ if (shift)
+ *shift = 0;
+ return find_linux_pte(pgdir, ea);
+}
+#endif /* !CONFIG_HUGETLB_PAGE */
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
--
1.7.0.4
^ permalink raw reply related
* [PATCH 3/6 v3] kvm: powerpc: allow guest control "G" attribute in mas2
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
"G" bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting "G", so allow him.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- no change
v1->v2
- no change
arch/powerpc/kvm/e500.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 277cb18..4fd9650 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -117,7 +117,7 @@ static inline struct kvmppc_vcpu_e500 *to_e500(struct kvm_vcpu *vcpu)
#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
#define MAS2_ATTRIB_MASK \
- (MAS2_X0 | MAS2_X1 | MAS2_E)
+ (MAS2_X0 | MAS2_X1 | MAS2_E | MAS2_G)
#define MAS3_ATTRIB_MASK \
(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
--
1.7.0.4
^ permalink raw reply related
* [PATCH 0/6 v3] kvm: powerpc: use cache attributes from linux pte
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
From: Bharat Bhushan <bharat.bhushan@freescale.com>
First patch is a typo fix where book3e define _PAGE_LENDIAN while it should be
defined as _PAGE_ENDIAN. This seems to show that this is never exercised :-)
Second and third patch is to allow guest controlling "G"-Guarded and
"E"-Endian TLB attributes respectively.
Fourth and fifth patch is moving functions/logic in common code
so they can be used on booke also.
Sixth patch is actually setting caching attributes (TLB.WIMGE) using
corresponding Linux pte.
v2->v3
- now lookup_linux_pte() only have pte search logic and it does not
set any access flags in pte. There is already a function for setting
access flag which will be called explicitly where needed.
On booke we only need to search for pte to get WIMG.
v1->v2
- Earlier caching attributes (WIMGE) were set based of page is RAM or not
But now we get these attributes from corresponding Linux PTE.
Bharat Bhushan (6):
powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN
kvm: powerpc: allow guest control "E" attribute in mas2
kvm: powerpc: allow guest control "G" attribute in mas2
powerpc: move linux pte/hugepte search to more generic file
kvm: powerpc: keep only pte search logic in lookup_linux_pte
kvm: powerpc: use caching attributes as per linux pte
arch/powerpc/include/asm/kvm_host.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64.h | 36 ------------------
arch/powerpc/include/asm/pgtable.h | 60 ++++++++++++++++++++++++++++++
arch/powerpc/include/asm/pte-book3e.h | 2 +-
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 38 ++++++-------------
arch/powerpc/kvm/booke.c | 2 +-
arch/powerpc/kvm/e500.h | 10 +++--
arch/powerpc/kvm/e500_mmu_host.c | 36 ++++++++++-------
8 files changed, 102 insertions(+), 84 deletions(-)
^ permalink raw reply
* [PATCH 1/6 v3] powerpc: book3e: _PAGE_LENDIAN must be _PAGE_ENDIAN
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is "_PAGE_LENDIAN" which is wrong and should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- no change
v1->v2
- no change
arch/powerpc/include/asm/pte-book3e.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-book3e.h b/arch/powerpc/include/asm/pte-book3e.h
index 0156702..576ad88 100644
--- a/arch/powerpc/include/asm/pte-book3e.h
+++ b/arch/powerpc/include/asm/pte-book3e.h
@@ -40,7 +40,7 @@
#define _PAGE_U1 0x010000
#define _PAGE_U0 0x020000
#define _PAGE_ACCESSED 0x040000
-#define _PAGE_LENDIAN 0x080000
+#define _PAGE_ENDIAN 0x080000
#define _PAGE_GUARDED 0x100000
#define _PAGE_COHERENT 0x200000 /* M: enforce memory coherence */
#define _PAGE_NO_CACHE 0x400000 /* I: cache inhibit */
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/6 v3] kvm: powerpc: allow guest control "E" attribute in mas2
From: Bharat Bhushan @ 2013-08-06 11:31 UTC (permalink / raw)
To: scottwood, benh, agraf, paulus, kvm, kvm-ppc, linuxppc-dev; +Cc: Bharat Bhushan
In-Reply-To: <1375788674-13140-1-git-send-email-Bharat.Bhushan@freescale.com>
"E" bit in MAS2 bit indicates whether the page is accessed
in Little-Endian or Big-Endian byte order.
There is no reason to stop guest setting "E", so allow him."
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
v2->v3
- no change
v1->v2
- no change
arch/powerpc/kvm/e500.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index c2e5e98..277cb18 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -117,7 +117,7 @@ static inline struct kvmppc_vcpu_e500 *to_e500(struct kvm_vcpu *vcpu)
#define E500_TLB_USER_PERM_MASK (MAS3_UX|MAS3_UR|MAS3_UW)
#define E500_TLB_SUPER_PERM_MASK (MAS3_SX|MAS3_SR|MAS3_SW)
#define MAS2_ATTRIB_MASK \
- (MAS2_X0 | MAS2_X1)
+ (MAS2_X0 | MAS2_X1 | MAS2_E)
#define MAS3_ATTRIB_MASK \
(MAS3_U0 | MAS3_U1 | MAS3_U2 | MAS3_U3 \
| E500_TLB_USER_PERM_MASK | E500_TLB_SUPER_PERM_MASK)
--
1.7.0.4
^ permalink raw reply related
* [PATCH] powerpc: Convert out of line __arch_hweight to inline
From: Madhavan Srinivasan @ 2013-08-06 11:30 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Madhavan Srinivasan, anton
Patch attempts to improve the performace of __arch_hweight functions by
making them inline instead of current out of line implementation.
Testcase is to disable/enable SMT on a large (192 thread) POWER7 lpar.
Program used for SMT disable/enable is "ppc64_cpu" with "--smt=[off/on]"
option. Here are the perf output. In this case, __arch_hweight64 is
called by __bitmap_weight.
Without patch (ppc64_cpu --smt=off):
17.60% ppc64_cpu [kernel.kallsyms] [k] .deactivate_slab
....
4.85% ppc64_cpu [kernel.kallsyms] [k] .__bitmap_weight
....
1.36% ppc64_cpu [kernel.kallsyms] [k] .__disable_runtime
1.29% ppc64_cpu [kernel.kallsyms] [k] .__arch_hweight64
With patch (ppc64_cpu --smt=off):
17.29% ppc64_cpu [kernel.kallsyms] [k] .deactivate_slab
....
3.71% ppc64_cpu [kernel.kallsyms] [k] .__bitmap_weight
3.26% ppc64_cpu [kernel.kallsyms] [k]
.build_overlap_sched_groups
....
Without patch (ppc64_cpu --smt=on):
8.35% ppc64_cpu [kernel.kallsyms] [k] .strlen
7.00% ppc64_cpu [kernel.kallsyms] [k] .memset
6.78% ppc64_cpu [kernel.kallsyms] [k] .__bitmap_weight
4.23% ppc64_cpu [kernel.kallsyms] [k] .deactivate_slab
....
1.58% ppc64_cpu [kernel.kallsyms] [k]
.refresh_zone_stat_thresholds
1.57% ppc64_cpu [kernel.kallsyms] [k] .__arch_hweight64
1.54% ppc64_cpu [kernel.kallsyms] [k] .__enable_runtime
....
With patch (ppc64_cpu --smt=on):
9.44% ppc64_cpu [kernel.kallsyms] [k] .strlen
6.43% ppc64_cpu [kernel.kallsyms] [k] .memset
5.48% ppc64_cpu [kernel.kallsyms] [k] .__bitmap_weight
4.59% ppc64_cpu [kernel.kallsyms] [k] .insert_entry
4.29% ppc64_cpu [kernel.kallsyms] [k] .deactivate_slab
....
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/bitops.h | 130 ++++++++++++++++++++++++++++++++-
arch/powerpc/include/asm/ppc-opcode.h | 6 ++
arch/powerpc/lib/Makefile | 2 +-
3 files changed, 133 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 910194e..136fe6a 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -43,8 +43,10 @@
#endif
#include <linux/compiler.h>
+#include <linux/types.h>
#include <asm/asm-compat.h>
#include <asm/synch.h>
+#include <asm/cputable.h>
/*
* clear_bit doesn't imply a memory barrier
@@ -263,10 +265,130 @@ static __inline__ int fls64(__u64 x)
#endif /* __powerpc64__ */
#ifdef CONFIG_PPC64
-unsigned int __arch_hweight8(unsigned int w);
-unsigned int __arch_hweight16(unsigned int w);
-unsigned int __arch_hweight32(unsigned int w);
-unsigned long __arch_hweight64(__u64 w);
+
+static inline unsigned int __arch_hweight8(unsigned int w)
+{
+ unsigned int register iop asm("r3") = w;
+ unsigned int register tmp asm("r4");
+ __asm__ __volatile__ (
+ stringify_in_c(BEGIN_FTR_SECTION)
+ "bl .__sw_hweight8;"
+ "nop;"
+ stringify_in_c(FTR_SECTION_ELSE)
+ PPC_POPCNTB_M(%1,%2) ";"
+ "clrldi %0,%1,64-8;"
+ stringify_in_c(ALT_FTR_SECTION_END_IFCLR((%3)))
+ : "=r" (iop), "=r" (tmp)
+ : "r" (iop), "i" (CPU_FTR_POPCNTB)
+ : "r0", "r1", "r5", "r6", "r7", "r8", "r9",
+ "r10", "r11", "r12", "r13", "r31", "lr", "cr0", "xer");
+
+ return iop;
+}
+
+static inline unsigned int __arch_hweight16(unsigned int w)
+{
+ unsigned int register iop asm("r3") = w;
+ unsigned int register tmp asm("r4");
+ __asm__ __volatile__ (
+ stringify_in_c(BEGIN_FTR_SECTION)
+ "bl .__sw_hweight16;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ stringify_in_c(FTR_SECTION_ELSE)
+ stringify_in_c(BEGIN_FTR_SECTION_NESTED(50))
+ PPC_POPCNTB_M(%0,%2) ";"
+ "srdi %1,%0,8;"
+ "add %0,%1,%0;"
+ "clrldi %0,%0,64-8;"
+ stringify_in_c(FTR_SECTION_ELSE_NESTED(50))
+ "clrlwi %0,%2,16;"
+ PPC_POPCNTW_M(%1,%0) ";"
+ "clrldi %0,%1,64-8;"
+ stringify_in_c(ALT_FTR_SECTION_END_NESTED_IFCLR(%4,50))
+ stringify_in_c(ALT_FTR_SECTION_END_IFCLR((%3)))
+ : "=r" (iop), "=r" (tmp)
+ : "r" (iop), "i" (CPU_FTR_POPCNTB), "i" (CPU_FTR_POPCNTD)
+ : "r0", "r1", "r5", "r6", "r7", "r8", "r9",
+ "r10", "r11", "r12", "r13", "r31", "lr", "cr0", "xer");
+
+ return iop;
+}
+
+static inline unsigned int __arch_hweight32(unsigned int w)
+{
+ unsigned int register iop asm("r3") = w;
+ unsigned int register tmp asm("r4");
+ __asm__ __volatile__ (
+ stringify_in_c(BEGIN_FTR_SECTION)
+ "bl .__sw_hweight32;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ stringify_in_c(FTR_SECTION_ELSE)
+ stringify_in_c(BEGIN_FTR_SECTION_NESTED(51))
+ PPC_POPCNTB_M(%0,%2) ";"
+ "srdi %1,%0,16;"
+ "add %0,%1,%0;"
+ "srdi %1,%0,8;"
+ "add %0,%1,%0;"
+ "clrldi %0,%0,64-8;"
+ stringify_in_c(FTR_SECTION_ELSE_NESTED(51))
+ PPC_POPCNTW_M(%1,%2) ";"
+ "clrldi %0,%1,64-8;"
+ stringify_in_c(ALT_FTR_SECTION_END_NESTED_IFCLR(%4,51))
+ stringify_in_c(ALT_FTR_SECTION_END_IFCLR((%3)))
+ : "=r" (iop), "=r" (tmp)
+ : "r" (iop), "i" (CPU_FTR_POPCNTB), "i" (CPU_FTR_POPCNTD)
+ : "r0", "r1", "r5", "r6", "r7", "r8", "r9",
+ "r10", "r11", "r12", "r13", "r31", "lr", "cr0", "xer");
+
+ return iop;
+}
+
+static inline __u64 __arch_hweight64(__u64 w)
+{
+ __u64 register iop asm("r3") = w;
+ __u64 register tmp asm("r4");
+ __asm__ __volatile__ (
+ stringify_in_c(BEGIN_FTR_SECTION)
+ "bl .__sw_hweight64;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ "nop;"
+ stringify_in_c(FTR_SECTION_ELSE)
+ stringify_in_c(BEGIN_FTR_SECTION_NESTED(52))
+ PPC_POPCNTB_M(%0,%2) ";"
+ "srdi %1,%0,32;"
+ "add %0,%1,%0;"
+ "srdi %1,%0,16;"
+ "add %0,%1,%0;"
+ "srdi %1,%0,8;"
+ "add %0,%1,%0;"
+ "clrldi %0,%0,64-8;"
+ stringify_in_c(FTR_SECTION_ELSE_NESTED(52))
+ PPC_POPCNTD_M(%1,%2) ";"
+ "clrldi %0,%1,64-8;"
+ stringify_in_c(ALT_FTR_SECTION_END_NESTED_IFCLR(%4,52))
+ stringify_in_c(ALT_FTR_SECTION_END_IFCLR((%3)))
+ : "=r" (iop), "=r" (tmp)
+ : "r" (iop), "i" (CPU_FTR_POPCNTB), "i" (CPU_FTR_POPCNTD)
+ : "r0", "r1", "r5", "r6", "r7", "r8", "r9",
+ "r10", "r11", "r12", "r13", "r31", "lr", "cr0", "xer");
+
+ return iop;
+}
+
#include <asm-generic/bitops/const_hweight.h>
#else
#include <asm-generic/bitops/hweight.h>
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index eccfc16..fc8767a 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -245,6 +245,12 @@
__PPC_RA(a) | __PPC_RS(s))
#define PPC_POPCNTW(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
__PPC_RA(a) | __PPC_RS(s))
+#define PPC_POPCNTB_M(a, s) stringify_in_c(.long PPC_INST_POPCNTB | \
+ ___PPC_RA(a) | ___PPC_RS(s))
+#define PPC_POPCNTD_M(a, s) stringify_in_c(.long PPC_INST_POPCNTD | \
+ ___PPC_RA(a) | ___PPC_RS(s))
+#define PPC_POPCNTW_M(a, s) stringify_in_c(.long PPC_INST_POPCNTW | \
+ ___PPC_RA(a) | ___PPC_RS(s))
#define PPC_RFCI stringify_in_c(.long PPC_INST_RFCI)
#define PPC_RFDI stringify_in_c(.long PPC_INST_RFDI)
#define PPC_RFMCI stringify_in_c(.long PPC_INST_RFMCI)
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 4504332..66f553d 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_HAS_IOMEM) += devres.o
obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
memcpy_64.o usercopy_64.o mem_64.o string.o \
- checksum_wrappers_64.o hweight_64.o \
+ checksum_wrappers_64.o \
copyuser_power7.o string_64.o copypage_power7.o \
memcpy_power7.o
obj-$(CONFIG_PPC_EMULATE_SSTEP) += sstep.o ldstfp.o
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH 3/3] powerpc: check CPU_FTR_COHERENT_ICACHE in __flush_dcache_icache for 64bit kernel
From: Benjamin Herrenschmidt @ 2013-08-06 10:36 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1375784612-14399-4-git-send-email-haokexin@gmail.com>
On Tue, 2013-08-06 at 18:23 +0800, Kevin Hao wrote:
> We don't need to flush the dcache and invalidate the icache on the
> CPU which has CPU_FTR_COHERENT_ICACHE set.
Actually we probably need an isync...
Ben.
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> arch/powerpc/kernel/misc_64.S | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index a781566..32e78e2 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -207,6 +207,9 @@ _GLOBAL(flush_inval_dcache_range)
> * void __flush_dcache_icache(void *page)
> */
> _GLOBAL(__flush_dcache_icache)
> +BEGIN_FTR_SECTION
> + blr
> +END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> /*
> * Flush the data cache to memory
> *
^ permalink raw reply
* Re: [PATCH 1/3] powerpc: move the testing of CPU_FTR_COHERENT_ICACHE into __flush_icache_range
From: Benjamin Herrenschmidt @ 2013-08-06 10:35 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1375784612-14399-2-git-send-email-haokexin@gmail.com>
On Tue, 2013-08-06 at 18:23 +0800, Kevin Hao wrote:
> In function flush_icache_range(), we use cpu_has_feature() to test
> the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal
> for two reasons:
> a) For ppc32, the function __flush_icache_range() already do this
> check with the macro END_FTR_SECTION_IFSET.
> b) Compare with the cpu_has_feature(), the method of using macro
> END_FTR_SECTION_IFSET will not introduce any runtime overhead.
Nak.
It adds the overhead of calling into a function :-)
What about modifying cpu_has_feature to use jump labels ? It might solve
the problem of no runtime overhead ... however it might also be hard to
keep the ability to remove the whole statement at compile time if the
bit doesn't fit in the POSSIBLE mask... unless you find the right macro
magic.
In any case, I suspect the function call introduces more overhead than
the bit test + conditional branch which will generally predict very
well, so the patch as-is is probably a regression.
Did you measure ?
Ben.
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> arch/powerpc/include/asm/cacheflush.h | 3 +--
> arch/powerpc/kernel/misc_64.S | 4 +++-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
> index b843e35..60b620d 100644
> --- a/arch/powerpc/include/asm/cacheflush.h
> +++ b/arch/powerpc/include/asm/cacheflush.h
> @@ -35,8 +35,7 @@ extern void __flush_disable_L1(void);
> extern void __flush_icache_range(unsigned long, unsigned long);
> static inline void flush_icache_range(unsigned long start, unsigned long stop)
> {
> - if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
> - __flush_icache_range(start, stop);
> + __flush_icache_range(start, stop);
> }
>
> extern void flush_icache_user_range(struct vm_area_struct *vma,
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index 6820e45..74d87f1 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -68,7 +68,9 @@ PPC64_CACHES:
> */
>
> _KPROBE(__flush_icache_range)
> -
> +BEGIN_FTR_SECTION
> + blr
> +END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> /*
> * Flush the data cache to memory
> *
^ permalink raw reply
* [PATCH 3/3] powerpc: check CPU_FTR_COHERENT_ICACHE in __flush_dcache_icache for 64bit kernel
From: Kevin Hao @ 2013-08-06 10:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <1375784612-14399-1-git-send-email-haokexin@gmail.com>
We don't need to flush the dcache and invalidate the icache on the
CPU which has CPU_FTR_COHERENT_ICACHE set.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/kernel/misc_64.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index a781566..32e78e2 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -207,6 +207,9 @@ _GLOBAL(flush_inval_dcache_range)
* void __flush_dcache_icache(void *page)
*/
_GLOBAL(__flush_dcache_icache)
+BEGIN_FTR_SECTION
+ blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*
--
1.8.3.1
^ permalink raw reply related
* [PATCH 2/3] powerpc: remove the symbol __flush_icache_range
From: Kevin Hao @ 2013-08-06 10:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <1375784612-14399-1-git-send-email-haokexin@gmail.com>
And now the function flush_icache_range() is just a wrapper which
only invoke the function __flush_icache_range() directly. So we
don't have reason to keep it anymore.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/include/asm/cacheflush.h | 7 +------
arch/powerpc/kernel/misc_32.S | 2 +-
arch/powerpc/kernel/misc_64.S | 2 +-
arch/powerpc/kernel/ppc_ksyms.c | 1 -
4 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 60b620d..5b93122 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -32,12 +32,7 @@ extern void flush_dcache_page(struct page *page);
extern void __flush_disable_L1(void);
-extern void __flush_icache_range(unsigned long, unsigned long);
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
- __flush_icache_range(start, stop);
-}
-
+extern void flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index e469f30..3f70dbf 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -327,7 +327,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
*
* flush_icache_range(unsigned long start, unsigned long stop)
*/
-_KPROBE(__flush_icache_range)
+_KPROBE(flush_icache_range)
BEGIN_FTR_SECTION
blr /* for 601, do nothing */
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 74d87f1..a781566 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -67,7 +67,7 @@ PPC64_CACHES:
* flush all bytes from start through stop-1 inclusive
*/
-_KPROBE(__flush_icache_range)
+_KPROBE(flush_icache_range)
BEGIN_FTR_SECTION
blr
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index c296665..380a6f9 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -111,7 +111,6 @@ EXPORT_SYMBOL(giveup_spe);
#ifndef CONFIG_PPC64
EXPORT_SYMBOL(flush_instruction_cache);
#endif
-EXPORT_SYMBOL(__flush_icache_range);
EXPORT_SYMBOL(flush_dcache_range);
#ifdef CONFIG_SMP
--
1.8.3.1
^ permalink raw reply related
* [PATCH 1/3] powerpc: move the testing of CPU_FTR_COHERENT_ICACHE into __flush_icache_range
From: Kevin Hao @ 2013-08-06 10:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
In-Reply-To: <1375784612-14399-1-git-send-email-haokexin@gmail.com>
In function flush_icache_range(), we use cpu_has_feature() to test
the feature bit of CPU_FTR_COHERENT_ICACHE. But this seems not optimal
for two reasons:
a) For ppc32, the function __flush_icache_range() already do this
check with the macro END_FTR_SECTION_IFSET.
b) Compare with the cpu_has_feature(), the method of using macro
END_FTR_SECTION_IFSET will not introduce any runtime overhead.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
---
arch/powerpc/include/asm/cacheflush.h | 3 +--
arch/powerpc/kernel/misc_64.S | 4 +++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index b843e35..60b620d 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -35,8 +35,7 @@ extern void __flush_disable_L1(void);
extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
- if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
- __flush_icache_range(start, stop);
+ __flush_icache_range(start, stop);
}
extern void flush_icache_user_range(struct vm_area_struct *vma,
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 6820e45..74d87f1 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -68,7 +68,9 @@ PPC64_CACHES:
*/
_KPROBE(__flush_icache_range)
-
+BEGIN_FTR_SECTION
+ blr
+END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
/*
* Flush the data cache to memory
*
--
1.8.3.1
^ permalink raw reply related
* [PATCH 0/3] powerpc: several patches for icache flush
From: Kevin Hao @ 2013-08-06 10:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc
These patches passed the build test with the following configurations.
ppc40x_defconfig
ppc64e_defconfig
ppc64_defconfig
mpc85xx_defconfig
mpc85xx_smp_defconfig
corenet32_smp_defconfig
corenet64_smp_defconfig
ppc44x_defconfig
mpc885_ads_defconfig
pseries_defconfig
Boot test on a p5020ds board.
---
Kevin Hao (3):
powerpc: move the testing of CPU_FTR_COHERENT_ICACHE into
__flush_icache_range
powerpc: remove the symbol __flush_icache_range
powerpc: check CPU_FTR_COHERENT_ICACHE in __flush_dcache_icache for
64bit kernel
arch/powerpc/include/asm/cacheflush.h | 8 +-------
arch/powerpc/kernel/misc_32.S | 2 +-
arch/powerpc/kernel/misc_64.S | 9 +++++++--
arch/powerpc/kernel/ppc_ksyms.c | 1 -
4 files changed, 9 insertions(+), 11 deletions(-)
--
1.8.3.1
^ permalink raw reply
* Re: PCIE device errors after linux kernel upgrade
From: Leon Ravich @ 2013-08-06 8:34 UTC (permalink / raw)
To: Johannes Thumshirn; +Cc: Bjorn Helgaas, linux-pci@vger.kernel.org, linuxppc-dev
In-Reply-To: <20130806073633.GA21492@jtlinux>
>> Have you looked up the error values from the EDAC driver?
[ 37.961580] PCIE error(s) detected
[ 37.964971] PCIE ERR_DR register: 0x00020000
=> Invalid CONFIG_ADDR/PEX_CONFIG_DATA access detected
[ 37.969229] PCIE ERR_CAP_STAT register: 0x00000041 =>
Transaction originated from PEX_CONFIG_ADDR/PEX_CONFIG_DATA.
[ 37.974008] PCIE ERR_CAP_R0 register: 0x00000800
=> PCI Express packet format 0, PCI express packet type 4
[ 37.978614] PCIE ERR_CAP_R1 register: 0x00000000
[ 37.983218] PCIE ERR_CAP_R2 register: 0x00000000
[ 37.987823] PCIE ERR_CAP_R3 register: 0x00000000
>> If it's just a reboot without panic, could there be a watchdog resetting the
>> board?
does not look like a watch dog , no watch dog printout. no freeze .
On 6 August 2013 10:36, Johannes Thumshirn <johannes.thumshirn@men.de> wrote:
> On Tue, Aug 06, 2013 at 10:26:18AM +0300, Leon Ravich wrote:
>> Hi Johannes
>> no panic just reboot.
>> it is not the first read, it takes few minutes of work with pcie to reboot.
>>
>
> Ah, OK. Unfortunately I can't really help you then.
>
> Have you looked up the error values from the EDAC driver?
>
> If it's just a reboot without panic, could there be a watchdog resetting the
> board?
>
>
>>
>>
>> On 6 August 2013 10:07, Johannes Thumshirn <johannes.thumshirn@men.de> wrote:
>> > On Mon, Aug 05, 2013 at 09:38:45AM -0600, Bjorn Helgaas wrote:
>> >> [+cc linuxppc-dev]
>> >>
>> >> On Mon, Aug 5, 2013 at 5:17 AM, Leon Ravich <lravich@gmail.com> wrote:
>> >> > Hi all ,
>> >> > I am trying to upgrade ours embedded device (freescale powerPC P2020 cpu)
>> >> > linux kernel , till now we used 2.6.32 I am trying to upgrade to 3.8.13 .
>> >> > I took the source from freescale git:
>> >> > git://git.freescale.com/ppc/sdk/linux.git
>> >> >
>> >> > on our embedded device we have an FPGA connected through PCIE .
>> >> >
>> >> > on each boot we loading the rbf design to the FPGA and the rescan pci bus to let
>> >> > kernel detect it .
>> >> >
>> >> > during the rescan I getting error messages:
>> >> > genirq: Setting trigger mode 0 for irq 27 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.060898] genirq: Setting trigger mode 0 for irq 28 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.069461] genirq: Setting trigger mode 0 for irq 31 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.078010] genirq: Setting trigger mode 0 for irq 32 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.086576] genirq: Setting trigger mode 0 for irq 33 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.095143] genirq: Setting trigger mode 0 for irq 37 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.103715] genirq: Setting trigger mode 0 for irq 38 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >> > [ 22.112282] genirq: Setting trigger mode 0 for irq 39 failed
>> >> > (mpc8xxx_irq_set_type+0x0/0xec)
>> >>
>> >> Hmm, I don't know much about IRQ issues.
>> >>
>> >> > [ 37.945785] pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't
>> >> > match header type 01)
>> >>
>> >> There's a recent patch related to this:
>> >> http://lkml.kernel.org/r/1374823418-1550-1-git-send-email-Chunhe.Lan@freescale.com
>> >>
>> >> > [ 37.953640] PCIE error(s) detected
>> >> > [ 37.953858] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
>> >> > [ 37.953988] pci 0000:00:00.0: BAR 8: assigned [mem 0xc0000000-0xdfffffff]
>> >> > [ 37.953994] pci 0000:00:00.0: BAR 7: can't assign io (size 0x10000)
>> >> > [ 37.954000] pci 0000:01:00.0: BAR 0: assigned [mem 0xc0000000-0xc00fffff]
>> >> > [ 37.954013] pci 0000:01:00.0: BAR 1: assigned [mem 0xc0100000-0xc017ffff]
>> >> > [ 37.954025] pci 0000:01:00.0: BAR 2: assigned [mem 0xc0180000-0xc01fffff]
>> >> > [ 37.954036] pci 0000:00:00.0: PCI bridge to [bus 01]
>> >> > [ 37.954041] pci 0000:00:00.0: bridge window [mem 0xc0000000-0xdfffffff]
>> >> > [ 38.007354] PCIE ERR_DR register: 0x80020000
>> >> > [ 38.011613] PCIE ERR_CAP_STAT register: 0x00000041
>> >> > [ 38.016392] PCIE ERR_CAP_R0 register: 0x00000800
>> >> > [ 38.020997] PCIE ERR_CAP_R1 register: 0x00000000
>> >> > [ 38.025602] PCIE ERR_CAP_R2 register: 0x00000000
>> >> > [ 38.030207] PCIE ERR_CAP_R3 register: 0x00000000
>> >> >
>> >> >
>> >> > and after a few minutes I linux reboot it self,
>> >> >
>> >> >
>> >> > where can I start debugging it??
>> >>
>> >> I'd start by applying the header quirk patch above, then comparing the
>> >> complete console log (boot with "ignore_loglevel") from 2.6.32 and
>> >> 3.8.13.
>> >>
>> >> Bjorn
>> >> _______________________________________________
>> >> Linuxppc-dev mailing list
>> >> Linuxppc-dev@lists.ozlabs.org
>> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
>> >
>> > Hi,
>> >
>> > I have a similar problem here on a P4080 based board with the same 3.8 Kernel
>> > from freescale git. Does your system panic (maybe due to a machine check
>> > exception)? If yes could it be the first read from the PCI device?
>> >
>> > Johannes
>>
>>
>>
>> --
>> Leonid Ravich
--
Leonid Ravich
^ permalink raw reply
* Re: PCIE device errors after linux kernel upgrade
From: Johannes Thumshirn @ 2013-08-06 7:36 UTC (permalink / raw)
To: Leon Ravich
Cc: Johannes Thumshirn, Bjorn Helgaas, linuxppc-dev,
linux-pci@vger.kernel.org
In-Reply-To: <CAPWoNkKo6Cfg0Hr2QYBXVnUrC-UQwES65UUHfSvR3nBvZrfFoA@mail.gmail.com>
On Tue, Aug 06, 2013 at 10:26:18AM +0300, Leon Ravich wrote:
> Hi Johannes
> no panic just reboot.
> it is not the first read, it takes few minutes of work with pcie to reboot.
>
Ah, OK. Unfortunately I can't really help you then.
Have you looked up the error values from the EDAC driver?
If it's just a reboot without panic, could there be a watchdog resetting the
board?
>
>
> On 6 August 2013 10:07, Johannes Thumshirn <johannes.thumshirn@men.de> wrote:
> > On Mon, Aug 05, 2013 at 09:38:45AM -0600, Bjorn Helgaas wrote:
> >> [+cc linuxppc-dev]
> >>
> >> On Mon, Aug 5, 2013 at 5:17 AM, Leon Ravich <lravich@gmail.com> wrote:
> >> > Hi all ,
> >> > I am trying to upgrade ours embedded device (freescale powerPC P2020 cpu)
> >> > linux kernel , till now we used 2.6.32 I am trying to upgrade to 3.8.13 .
> >> > I took the source from freescale git:
> >> > git://git.freescale.com/ppc/sdk/linux.git
> >> >
> >> > on our embedded device we have an FPGA connected through PCIE .
> >> >
> >> > on each boot we loading the rbf design to the FPGA and the rescan pci bus to let
> >> > kernel detect it .
> >> >
> >> > during the rescan I getting error messages:
> >> > genirq: Setting trigger mode 0 for irq 27 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.060898] genirq: Setting trigger mode 0 for irq 28 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.069461] genirq: Setting trigger mode 0 for irq 31 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.078010] genirq: Setting trigger mode 0 for irq 32 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.086576] genirq: Setting trigger mode 0 for irq 33 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.095143] genirq: Setting trigger mode 0 for irq 37 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.103715] genirq: Setting trigger mode 0 for irq 38 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >> > [ 22.112282] genirq: Setting trigger mode 0 for irq 39 failed
> >> > (mpc8xxx_irq_set_type+0x0/0xec)
> >>
> >> Hmm, I don't know much about IRQ issues.
> >>
> >> > [ 37.945785] pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't
> >> > match header type 01)
> >>
> >> There's a recent patch related to this:
> >> http://lkml.kernel.org/r/1374823418-1550-1-git-send-email-Chunhe.Lan@freescale.com
> >>
> >> > [ 37.953640] PCIE error(s) detected
> >> > [ 37.953858] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> >> > [ 37.953988] pci 0000:00:00.0: BAR 8: assigned [mem 0xc0000000-0xdfffffff]
> >> > [ 37.953994] pci 0000:00:00.0: BAR 7: can't assign io (size 0x10000)
> >> > [ 37.954000] pci 0000:01:00.0: BAR 0: assigned [mem 0xc0000000-0xc00fffff]
> >> > [ 37.954013] pci 0000:01:00.0: BAR 1: assigned [mem 0xc0100000-0xc017ffff]
> >> > [ 37.954025] pci 0000:01:00.0: BAR 2: assigned [mem 0xc0180000-0xc01fffff]
> >> > [ 37.954036] pci 0000:00:00.0: PCI bridge to [bus 01]
> >> > [ 37.954041] pci 0000:00:00.0: bridge window [mem 0xc0000000-0xdfffffff]
> >> > [ 38.007354] PCIE ERR_DR register: 0x80020000
> >> > [ 38.011613] PCIE ERR_CAP_STAT register: 0x00000041
> >> > [ 38.016392] PCIE ERR_CAP_R0 register: 0x00000800
> >> > [ 38.020997] PCIE ERR_CAP_R1 register: 0x00000000
> >> > [ 38.025602] PCIE ERR_CAP_R2 register: 0x00000000
> >> > [ 38.030207] PCIE ERR_CAP_R3 register: 0x00000000
> >> >
> >> >
> >> > and after a few minutes I linux reboot it self,
> >> >
> >> >
> >> > where can I start debugging it??
> >>
> >> I'd start by applying the header quirk patch above, then comparing the
> >> complete console log (boot with "ignore_loglevel") from 2.6.32 and
> >> 3.8.13.
> >>
> >> Bjorn
> >> _______________________________________________
> >> Linuxppc-dev mailing list
> >> Linuxppc-dev@lists.ozlabs.org
> >> https://lists.ozlabs.org/listinfo/linuxppc-dev
> >
> > Hi,
> >
> > I have a similar problem here on a P4080 based board with the same 3.8 Kernel
> > from freescale git. Does your system panic (maybe due to a machine check
> > exception)? If yes could it be the first read from the PCI device?
> >
> > Johannes
>
>
>
> --
> Leonid Ravich
^ permalink raw reply
* [PATCH v3 3/3] selftests: Add test of PMU instruction counting on powerpc
From: Michael Ellerman @ 2013-08-06 7:42 UTC (permalink / raw)
To: linuxppc-dev
Cc: Jeremy Kerr, Andrew Morton, Michael Neuling, linux-kernel,
Anton Blanchard
In-Reply-To: <1375774957-30052-1-git-send-email-michael@ellerman.id.au>
This commit adds a test of instruction counting using the PMU on powerpc.
Although the bulk of the code is architecture agnostic, the code needs to
run a precisely sized loop which is implemented in assembler.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
v2,3: No change
tools/testing/selftests/powerpc/Makefile | 2 +-
tools/testing/selftests/powerpc/pmu/Makefile | 23 ++++
.../selftests/powerpc/pmu/count_instructions.c | 135 +++++++++++++++++++++
tools/testing/selftests/powerpc/pmu/event.c | 105 ++++++++++++++++
tools/testing/selftests/powerpc/pmu/event.h | 39 ++++++
tools/testing/selftests/powerpc/pmu/loop.S | 46 +++++++
6 files changed, 349 insertions(+), 1 deletion(-)
create mode 100644 tools/testing/selftests/powerpc/pmu/Makefile
create mode 100644 tools/testing/selftests/powerpc/pmu/count_instructions.c
create mode 100644 tools/testing/selftests/powerpc/pmu/event.c
create mode 100644 tools/testing/selftests/powerpc/pmu/event.h
create mode 100644 tools/testing/selftests/powerpc/pmu/loop.S
diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
index b315740..bd24ae5 100644
--- a/tools/testing/selftests/powerpc/Makefile
+++ b/tools/testing/selftests/powerpc/Makefile
@@ -13,7 +13,7 @@ CFLAGS := -Wall -O2 -flto -Wall -Werror -DGIT_VERSION='"$(GIT_VERSION)"' -I$(CUR
export CC CFLAGS
-TARGETS =
+TARGETS = pmu
endif
diff --git a/tools/testing/selftests/powerpc/pmu/Makefile b/tools/testing/selftests/powerpc/pmu/Makefile
new file mode 100644
index 0000000..7216f00
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/Makefile
@@ -0,0 +1,23 @@
+noarg:
+ $(MAKE) -C ../
+
+PROGS := count_instructions
+EXTRA_SOURCES := ../harness.c event.c
+
+all: $(PROGS)
+
+$(PROGS): $(EXTRA_SOURCES)
+
+# loop.S can only be built 64-bit
+count_instructions: loop.S count_instructions.c $(EXTRA_SOURCES)
+ $(CC) $(CFLAGS) -m64 -o $@ $^
+
+run_tests: all
+ @-for PROG in $(PROGS); do \
+ ./$$PROG; \
+ done;
+
+clean:
+ rm -f $(PROGS) loop.o
+
+.PHONY: all run_tests clean
diff --git a/tools/testing/selftests/powerpc/pmu/count_instructions.c b/tools/testing/selftests/powerpc/pmu/count_instructions.c
new file mode 100644
index 0000000..312b4f0
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/count_instructions.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2013, Michael Ellerman, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#define _GNU_SOURCE
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+#include <sys/prctl.h>
+
+#include "event.h"
+#include "utils.h"
+
+extern void thirty_two_instruction_loop(u64 loops);
+
+static void setup_event(struct event *e, u64 config, char *name)
+{
+ event_init_opts(e, config, PERF_TYPE_HARDWARE, name);
+
+ e->attr.disabled = 1;
+ e->attr.exclude_kernel = 1;
+ e->attr.exclude_hv = 1;
+ e->attr.exclude_idle = 1;
+}
+
+static int do_count_loop(struct event *events, u64 instructions,
+ u64 overhead, bool report)
+{
+ s64 difference, expected;
+ double percentage;
+
+ prctl(PR_TASK_PERF_EVENTS_ENABLE);
+
+ /* Run for 1M instructions */
+ thirty_two_instruction_loop(instructions >> 5);
+
+ prctl(PR_TASK_PERF_EVENTS_DISABLE);
+
+ event_read(&events[0]);
+ event_read(&events[1]);
+
+ expected = instructions + overhead;
+ difference = events[0].result.value - expected;
+ percentage = (double)difference / events[0].result.value * 100;
+
+ if (report) {
+ event_report(&events[0]);
+ event_report(&events[1]);
+
+ printf("Looped for %llu instructions, overhead %llu\n", instructions, overhead);
+ printf("Expected %llu\n", expected);
+ printf("Actual %llu\n", events[0].result.value);
+ printf("Delta %lld, %f%%\n", difference, percentage);
+ }
+
+ event_reset(&events[0]);
+ event_reset(&events[1]);
+
+ if (difference < 0)
+ difference = -difference;
+
+ /* Tolerate a difference below 0.0001 % */
+ difference *= 10000 * 100;
+ if (difference / events[0].result.value)
+ return -1;
+
+ return 0;
+}
+
+/* Count how many instructions it takes to do a null loop */
+static u64 determine_overhead(struct event *events)
+{
+ u64 current, overhead;
+ int i;
+
+ do_count_loop(events, 0, 0, false);
+ overhead = events[0].result.value;
+
+ for (i = 0; i < 100; i++) {
+ do_count_loop(events, 0, 0, false);
+ current = events[0].result.value;
+ if (current < overhead) {
+ printf("Replacing overhead %llu with %llu\n", overhead, current);
+ overhead = current;
+ }
+ }
+
+ return overhead;
+}
+
+static int count_instructions(void)
+{
+ struct event events[2];
+ u64 overhead;
+
+ setup_event(&events[0], PERF_COUNT_HW_INSTRUCTIONS, "instructions");
+ setup_event(&events[1], PERF_COUNT_HW_CPU_CYCLES, "cycles");
+
+ if (event_open(&events[0])) {
+ perror("perf_event_open");
+ return -1;
+ }
+
+ if (event_open_with_group(&events[1], events[0].fd)) {
+ perror("perf_event_open");
+ return -1;
+ }
+
+ overhead = determine_overhead(events);
+ printf("Overhead of null loop: %llu instructions\n", overhead);
+
+ /* Run for 1M instructions */
+ FAIL_IF(do_count_loop(events, 0x100000, overhead, true));
+
+ /* Run for 10M instructions */
+ FAIL_IF(do_count_loop(events, 0xa00000, overhead, true));
+
+ /* Run for 100M instructions */
+ FAIL_IF(do_count_loop(events, 0x6400000, overhead, true));
+
+ /* Run for 1G instructions */
+ FAIL_IF(do_count_loop(events, 0x40000000, overhead, true));
+
+ event_close(&events[0]);
+ event_close(&events[1]);
+
+ return 0;
+}
+
+int main(void)
+{
+ return test_harness(count_instructions, "count_instructions");
+}
diff --git a/tools/testing/selftests/powerpc/pmu/event.c b/tools/testing/selftests/powerpc/pmu/event.c
new file mode 100644
index 0000000..2b2d11d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/event.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2013, Michael Ellerman, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#define _GNU_SOURCE
+#include <unistd.h>
+#include <sys/syscall.h>
+#include <string.h>
+#include <stdio.h>
+#include <sys/ioctl.h>
+
+#include "event.h"
+
+
+int perf_event_open(struct perf_event_attr *attr, pid_t pid, int cpu,
+ int group_fd, unsigned long flags)
+{
+ return syscall(__NR_perf_event_open, attr, pid, cpu,
+ group_fd, flags);
+}
+
+void event_init_opts(struct event *e, u64 config, int type, char *name)
+{
+ memset(e, 0, sizeof(*e));
+
+ e->name = name;
+
+ e->attr.type = type;
+ e->attr.config = config;
+ e->attr.size = sizeof(e->attr);
+ /* This has to match the structure layout in the header */
+ e->attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED | \
+ PERF_FORMAT_TOTAL_TIME_RUNNING;
+}
+
+void event_init_named(struct event *e, u64 config, char *name)
+{
+ event_init_opts(e, config, PERF_TYPE_RAW, name);
+}
+
+#define PERF_CURRENT_PID 0
+#define PERF_NO_CPU -1
+#define PERF_NO_GROUP -1
+
+int event_open_with_options(struct event *e, pid_t pid, int cpu, int group_fd)
+{
+ e->fd = perf_event_open(&e->attr, pid, cpu, group_fd, 0);
+ if (e->fd == -1) {
+ perror("perf_event_open");
+ return -1;
+ }
+
+ return 0;
+}
+
+int event_open_with_group(struct event *e, int group_fd)
+{
+ return event_open_with_options(e, PERF_CURRENT_PID, PERF_NO_CPU, group_fd);
+}
+
+int event_open(struct event *e)
+{
+ return event_open_with_options(e, PERF_CURRENT_PID, PERF_NO_CPU, PERF_NO_GROUP);
+}
+
+void event_close(struct event *e)
+{
+ close(e->fd);
+}
+
+int event_reset(struct event *e)
+{
+ return ioctl(e->fd, PERF_EVENT_IOC_RESET);
+}
+
+int event_read(struct event *e)
+{
+ int rc;
+
+ rc = read(e->fd, &e->result, sizeof(e->result));
+ if (rc != sizeof(e->result)) {
+ fprintf(stderr, "read error on event %p!\n", e);
+ return -1;
+ }
+
+ return 0;
+}
+
+void event_report_justified(struct event *e, int name_width, int result_width)
+{
+ printf("%*s: result %*llu ", name_width, e->name, result_width,
+ e->result.value);
+
+ if (e->result.running == e->result.enabled)
+ printf("running/enabled %llu\n", e->result.running);
+ else
+ printf("running %llu enabled %llu\n", e->result.running,
+ e->result.enabled);
+}
+
+void event_report(struct event *e)
+{
+ event_report_justified(e, 0, 0);
+}
diff --git a/tools/testing/selftests/powerpc/pmu/event.h b/tools/testing/selftests/powerpc/pmu/event.h
new file mode 100644
index 0000000..e699319
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/event.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2013, Michael Ellerman, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#ifndef _SELFTESTS_POWERPC_PMU_EVENT_H
+#define _SELFTESTS_POWERPC_PMU_EVENT_H
+
+#include <unistd.h>
+#include <linux/perf_event.h>
+
+#include "utils.h"
+
+
+struct event {
+ struct perf_event_attr attr;
+ char *name;
+ int fd;
+ /* This must match the read_format we use */
+ struct {
+ u64 value;
+ u64 running;
+ u64 enabled;
+ } result;
+};
+
+void event_init(struct event *e, u64 config);
+void event_init_named(struct event *e, u64 config, char *name);
+void event_init_opts(struct event *e, u64 config, int type, char *name);
+int event_open_with_options(struct event *e, pid_t pid, int cpu, int group_fd);
+int event_open_with_group(struct event *e, int group_fd);
+int event_open(struct event *e);
+void event_close(struct event *e);
+int event_reset(struct event *e);
+int event_read(struct event *e);
+void event_report_justified(struct event *e, int name_width, int result_width);
+void event_report(struct event *e);
+
+#endif /* _SELFTESTS_POWERPC_PMU_EVENT_H */
diff --git a/tools/testing/selftests/powerpc/pmu/loop.S b/tools/testing/selftests/powerpc/pmu/loop.S
new file mode 100644
index 0000000..8820e3d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/pmu/loop.S
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2013, Michael Ellerman, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+ .text
+
+ .global thirty_two_instruction_loop
+ .type .thirty_two_instruction_loop,@function
+ .section ".opd","aw",@progbits
+thirty_two_instruction_loop:
+ .quad .thirty_two_instruction_loop, .TOC.@tocbase, 0
+ .previous
+.thirty_two_instruction_loop:
+ cmpwi %r3,0
+ beqlr
+ addi %r4,%r3,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1
+ addi %r4,%r4,1 # 28 addi's
+ subi %r3,%r3,1
+ b .thirty_two_instruction_loop
--
1.8.1.2
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