* [PATCH 2/3 V3] mmc:sdhc: get voltage from sdhc host
From: Haijun Zhang @ 2013-08-12 1:39 UTC (permalink / raw)
To: linux-mmc, linuxppc-dev; +Cc: X.Xie, cbouatmailru, scottwood, cjb, Haijun Zhang
In-Reply-To: <1376271546-25085-1-git-send-email-Haijun.Zhang@freescale.com>
We use host->ocr_mask to hold the voltage get from device-tree
node, In case host->ocr_mask was available, we use host->ocr_mask
as the final available voltage can be used by MMC/SD/SDIO card.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
---
changes for V3:
- changed the type of mask
drivers/mmc/host/sdhci.c | 3 +++
include/linux/mmc/sdhci.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index a78bd4f..57541e0 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3119,6 +3119,9 @@ int sdhci_add_host(struct sdhci_host *host)
SDHCI_MAX_CURRENT_MULTIPLIER;
}
+ if (host->ocr_mask)
+ ocr_avail = host->ocr_mask;
+
mmc->ocr_avail = ocr_avail;
mmc->ocr_avail_sdio = ocr_avail;
if (host->ocr_avail_sdio)
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index e3c6a74..3e781b8 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -171,6 +171,7 @@ struct sdhci_host {
unsigned int ocr_avail_sdio; /* OCR bit masks */
unsigned int ocr_avail_sd;
unsigned int ocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
--
1.8.0
^ permalink raw reply related
* [PATCH V3] mmc:of_spi: Update the code of getting voltage-ranges
From: Haijun Zhang @ 2013-08-12 1:39 UTC (permalink / raw)
To: linux-mmc, linuxppc-dev; +Cc: X.Xie, cbouatmailru, scottwood, cjb, Haijun Zhang
In-Reply-To: <1376271546-25085-1-git-send-email-Haijun.Zhang@freescale.com>
Using function mmc_of_parse_voltage() to get voltage-ranges.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
---
changes for V3:
- changes the type of ocr_mask and function mmc_of_parse_voltage
drivers/mmc/host/of_mmc_spi.c | 23 +++--------------------
1 file changed, 3 insertions(+), 20 deletions(-)
diff --git a/drivers/mmc/host/of_mmc_spi.c b/drivers/mmc/host/of_mmc_spi.c
index d720b5e..fd1928d 100644
--- a/drivers/mmc/host/of_mmc_spi.c
+++ b/drivers/mmc/host/of_mmc_spi.c
@@ -90,8 +90,7 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct spi_device *spi)
struct device *dev = &spi->dev;
struct device_node *np = dev->of_node;
struct of_mmc_spi *oms;
- const u32 *voltage_ranges;
- int num_ranges;
+ u32 ocr_mask;
int i;
int ret = -EINVAL;
@@ -102,26 +101,10 @@ struct mmc_spi_platform_data *mmc_spi_get_pdata(struct spi_device *spi)
if (!oms)
return NULL;
- voltage_ranges = of_get_property(np, "voltage-ranges", &num_ranges);
- num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
- if (!voltage_ranges || !num_ranges) {
- dev_err(dev, "OF: voltage-ranges unspecified\n");
+ if (mmc_of_parse_voltage(np, &ocr_mask))
goto err_ocr;
- }
-
- for (i = 0; i < num_ranges; i++) {
- const int j = i * 2;
- u32 mask;
- mask = mmc_vddrange_to_ocrmask(be32_to_cpu(voltage_ranges[j]),
- be32_to_cpu(voltage_ranges[j + 1]));
- if (!mask) {
- ret = -EINVAL;
- dev_err(dev, "OF: voltage-range #%d is invalid\n", i);
- goto err_ocr;
- }
- oms->pdata.ocr_mask |= mask;
- }
+ oms->pdata.ocr_mask |= ocr_mask;
for (i = 0; i < ARRAY_SIZE(oms->gpios); i++) {
enum of_gpio_flags gpio_flags;
--
1.8.0
^ permalink raw reply related
* [PATCH 1/3 V4] mmc:core: parse voltage from device-tree
From: Haijun Zhang @ 2013-08-12 1:39 UTC (permalink / raw)
To: linux-mmc, linuxppc-dev; +Cc: X.Xie, cbouatmailru, scottwood, cjb, Haijun Zhang
Add function to support get voltage from device-tree.
If there are voltage-range specified in device-tree node, this function
will parse it and return the available voltage mask.
Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
---
changes for V4:
- Add new parameter mask to return voltages.
changes for V3:
- Correct the type of return value.
drivers/mmc/core/core.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/mmc/core.h | 2 ++
2 files changed, 46 insertions(+)
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 49a5bca..b9b9fb6 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -27,6 +27,7 @@
#include <linux/fault-inject.h>
#include <linux/random.h>
#include <linux/slab.h>
+#include <linux/of.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
@@ -1196,6 +1197,49 @@ u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max)
}
EXPORT_SYMBOL(mmc_vddrange_to_ocrmask);
+#ifdef CONFIG_OF
+
+/**
+ * mmc_of_parse_voltage - return mask of supported voltages
+ * @np: The device node need to be parsed.
+ * @mask: mask of voltages available for MMC/SD/SDIO
+ *
+ * 1. Return zero on success.
+ * 2. Return negative errno: voltage-range is invalid.
+ */
+int mmc_of_parse_voltage(struct device_node *np, u32 *mask)
+{
+ const u32 *voltage_ranges;
+ int num_ranges, i;
+
+ voltage_ranges = of_get_property(np, "voltage-ranges", &num_ranges);
+ num_ranges = num_ranges / sizeof(*voltage_ranges) / 2;
+ if (!voltage_ranges || !num_ranges) {
+ pr_info("%s: voltage-ranges unspecified\n", np->full_name);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < num_ranges; i++) {
+ const int j = i * 2;
+ u32 ocr_mask;
+
+ ocr_mask = mmc_vddrange_to_ocrmask(
+ be32_to_cpu(voltage_ranges[j]),
+ be32_to_cpu(voltage_ranges[j + 1]));
+ if (!ocr_mask) {
+ pr_err("%s: voltage-range #%d is invalid\n",
+ np->full_name, i);
+ return -EINVAL;
+ }
+ *mask |= ocr_mask;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(mmc_of_parse_voltage);
+
+#endif /* CONFIG_OF */
+
#ifdef CONFIG_REGULATOR
/**
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 443243b..da51bec 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -208,6 +208,8 @@ static inline void mmc_claim_host(struct mmc_host *host)
__mmc_claim_host(host, NULL);
}
+struct device_node;
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
+extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
#endif /* LINUX_MMC_CORE_H */
--
1.8.0
^ permalink raw reply related
* Re: Failure to detect PCI card
From: Benjamin Herrenschmidt @ 2013-08-12 2:32 UTC (permalink / raw)
To: Peter LaDow; +Cc: Anatolij Gustschin, linuxppc-dev, David Hawkins
In-Reply-To: <CAN8Q1EczGM+aQMPti+QdvUHHbsn=ARV7sKptXc5M7gvEFoDkKQ@mail.gmail.com>
On Thu, 2013-08-08 at 13:31 -0700, Peter LaDow wrote:
> For those that are interested, we did figure out what was going on.
> Turns out that the clock buffer driving the PCI connector was, well,
> less than adequate. With some cards, the load on the clock line was
> large enough that the clock was in horrible shape. Fixing the clock
> line and the card that failed to be recognized started working. For
> the other cards that worked, the load on the clock line was
> significantly less, but the clock was still marginal.
>
> Anyway, turned out to be a hardware issue. Thanks to all that helped!
Do that help with e1000 as well ? IE. A bad clock might have caused
malfunctions of the DMA for example...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/3] cpufreq: pmac64: speed up frequency switch
From: Benjamin Herrenschmidt @ 2013-08-12 1:07 UTC (permalink / raw)
To: Rafael J. Wysocki
Cc: Nick Piggin, Viresh Kumar, Aaro Koskinen, linuxppc-dev, linux-pm
In-Reply-To: <1374614043.3916.84.camel@pasglop>
On Wed, 2013-07-24 at 07:14 +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2013-07-23 at 23:20 +0200, Rafael J. Wysocki wrote:
> > All looks good in the patchset from 10000 feet (or more), but I need
> > Ben to speak here.
>
> I want to give it a quick spin on the HW here, I'll ack then. But yes,
> it looks good.
Seems to work here on the quad G5.
However, If I use on-demand, there's a huge latency of switch as far as
I can tell (about 10s) after I start/stop a bunch of CPU eaters... I
quite like how the userspace "powernowd" which I used to use switches
more aggressively.
Is that expected ?
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 2/2] Register bootmem pages at boot on powerpc
From: Benjamin Herrenschmidt @ 2013-08-12 0:19 UTC (permalink / raw)
To: Nathan Fontenot; +Cc: linux-mm, linuxppc-dev
In-Reply-To: <52050B80.8010602@linux.vnet.ibm.com>
On Fri, 2013-08-09 at 10:32 -0500, Nathan Fontenot wrote:
> +void register_page_bootmem_memmap(unsigned long section_nr,
> + struct page *start_page, unsigned long size)
> +{
> + WARN_ONCE(1, KERN_INFO
> + "Sparse Vmemmap not fully supported for bootmem info nodes\n");
> +}
> #endif /* CONFIG_SPARSEMEM_VMEMMAP */
But SPARSEMEM_VMEMMAP is our default on ppc64 pseries ... and you are
select'ing the new option, so it looks like we are missing something
here...
Can you tell me a bit more, the above makes me nervous...
Cheers,
Ben.
> Index: powerpc/arch/powerpc/mm/mem.c
> ===================================================================
> --- powerpc.orig/arch/powerpc/mm/mem.c
> +++ powerpc/arch/powerpc/mm/mem.c
> @@ -297,12 +297,21 @@ void __init paging_init(void)
> }
> #endif /* ! CONFIG_NEED_MULTIPLE_NODES */
>
> +static void __init register_page_bootmem_info(void)
> +{
> + int i;
> +
> + for_each_online_node(i)
> + register_page_bootmem_info_node(NODE_DATA(i));
> +}
> +
> void __init mem_init(void)
> {
> #ifdef CONFIG_SWIOTLB
> swiotlb_init(0);
> #endif
>
> + register_page_bootmem_info();
> high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
> set_max_mapnr(max_pfn);
> free_all_bootmem();
> Index: powerpc/mm/Kconfig
> ===================================================================
> --- powerpc.orig/mm/Kconfig
> +++ powerpc/mm/Kconfig
> @@ -183,7 +183,7 @@ config MEMORY_HOTPLUG_SPARSE
> config MEMORY_HOTREMOVE
> bool "Allow for memory hot remove"
> select MEMORY_ISOLATION
> - select HAVE_BOOTMEM_INFO_NODE if X86_64
> + select HAVE_BOOTMEM_INFO_NODE if (X86_64 || PPC64)
> depends on MEMORY_HOTPLUG && ARCH_ENABLE_MEMORY_HOTREMOVE
> depends on MIGRATION
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [RFC] powerpc: put the common parts of the ppc64*defconfigs in a Kconfig file
From: Stephen Rothwell @ 2013-08-11 23:59 UTC (permalink / raw)
To: Kumar Gala; +Cc: ppc-dev
In-Reply-To: <37F6E4C6-0428-4707-A46A-B9DB9A145747@kernel.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 1771 bytes --]
Hi Kumar,
Thanks for your comments.
On Fri, 9 Aug 2013 09:41:54 -0500 Kumar Gala <galak@kernel.crashing.org> wrote:
>
>
> On Aug 9, 2013, at 1:24 AM, Stephen Rothwell wrote:
>
> > We cannot put the unsetting of config options in the Kconfig file, nor
> > the integer or string options.
> >
> > I checked that after this we get the same .config files generated (except
> > for the addition of the new PPC64_DEFCONFIG* config options.
> >
> > Any thoughts?
> > ---
> > arch/powerpc/Kconfig | 2 +
> > arch/powerpc/configs/Kconfig | 295 +++++++++++++++++++++++++++++++++
> > arch/powerpc/configs/ppc64_defconfig | 301 +---------------------------------
> > arch/powerpc/configs/ppc64e_defconfig | 297 +--------------------------------
> > 4 files changed, 302 insertions(+), 593 deletions(-)
> > create mode 100644 arch/powerpc/configs/Kconfig
>
> Am I missing something here, isn't this a bit of a maintenance pain if
> symbol names change?
I don't think it is any worse than what we have, and in fact may be
better. Currently if someone renames a config option, they usually do
nothing about the defconfigs, this way, at least if the option is in
configs/Kconfig, they may update it.
> Also, how much of a benefit is this?
There has been some discussion about Anton adding 2 new defconfigs that
are very similar to the current defconfigs. This is an attempt to
reduce the amount of unnecessary repetition and churn.
A similar thing could be done for other sets of similar defconfig files.
There was a plan a few years ago to replace the defconfigs with Kconfig
fragments and this would be a step along that path.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH 5/7] powerpc/perf: Define big-endian version of perf_mem_data_src
From: Michael Ellerman @ 2013-08-11 23:57 UTC (permalink / raw)
To: Vince Weaver
Cc: Anton Blanchard, linux-kernel, Stephane Eranian, linuxppc-dev,
Paul Mackerras, Sukadev Bhattiprolu, Anshuman Khandual
In-Reply-To: <alpine.DEB.2.02.1308102232120.4119@pianoman.cluster.toy>
On Sat, Aug 10, 2013 at 10:34:58PM -0400, Vince Weaver wrote:
> On Sat, 10 Aug 2013, Sukadev Bhattiprolu wrote:
>
> >
> > include/uapi/linux/perf_event.h | 55 +++++++++++++++++++++++++++++++++++++++
> > 1 files changed, 55 insertions(+), 0 deletions(-)
>
> > +#define __PERF_LE 1234
> > +#define __PERF_BE 4321
> > +
> > +#if defined(__KERNEL__)
>
> I could be wrong, but I thought files under uapi weren't supposed to
> contain __KERNEL__ code. Wasn't that the whole point of uapi?
Yes.
> Also having the perf_event interface depend on endianess just seems like a
> complicated mess. Can't we just declare the interface to be a certain
> endianess and have the kernel byte-swap as necessary?
Yes I think so. The interface is already defined and it's little endian,
so on big endian we just need to swap.
The only part I'm not clear on is how things are handled in perf
userspace, it seems to already do some byte swapping.
cheers
^ permalink raw reply
* [PATCH] powerpc/kvm: Handle the boundary condition correctly
From: Aneesh Kumar K.V @ 2013-08-11 18:20 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
We should be able to copy upto count bytes
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 710d313..0ae6bb6 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -1362,7 +1362,7 @@ static ssize_t kvm_htab_read(struct file *file, char __user *buf,
lbuf = (unsigned long __user *)buf;
nb = 0;
- while (nb + sizeof(hdr) + HPTE_SIZE < count) {
+ while (nb + sizeof(hdr) + HPTE_SIZE <= count) {
/* Initialize header */
hptr = (struct kvm_get_htab_header __user *)buf;
hdr.n_valid = 0;
@@ -1385,7 +1385,7 @@ static ssize_t kvm_htab_read(struct file *file, char __user *buf,
/* Grab a series of valid entries */
while (i < kvm->arch.hpt_npte &&
hdr.n_valid < 0xffff &&
- nb + HPTE_SIZE < count &&
+ nb + HPTE_SIZE <= count &&
record_hpte(flags, hptp, hpte, revp, 1, first_pass)) {
/* valid entry, write it out */
++hdr.n_valid;
--
1.8.1.2
^ permalink raw reply related
* [PATCH] powerpc/kvm: Copy the pvr value after memset
From: Aneesh Kumar K.V @ 2013-08-11 18:19 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Otherwise we would clear the pvr value
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/kvm/book3s_hv.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 2efa9dd..dd1b72c 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -680,13 +680,12 @@ static int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
}
int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
- struct kvm_sregs *sregs)
+ struct kvm_sregs *sregs)
{
int i;
- sregs->pvr = vcpu->arch.pvr;
-
memset(sregs, 0, sizeof(struct kvm_sregs));
+ sregs->pvr = vcpu->arch.pvr;
for (i = 0; i < vcpu->arch.slb_max; i++) {
sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige;
sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv;
@@ -696,7 +695,7 @@ int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
}
int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
- struct kvm_sregs *sregs)
+ struct kvm_sregs *sregs)
{
int i, j;
--
1.8.1.2
^ permalink raw reply related
* Re: [PATCH 5/7] powerpc/perf: Define big-endian version of perf_mem_data_src
From: Sukadev Bhattiprolu @ 2013-08-11 17:15 UTC (permalink / raw)
To: Vince Weaver
Cc: Anton Blanchard, linux-kernel, Stephane Eranian, linuxppc-dev,
Paul Mackerras, Anshuman Khandual
In-Reply-To: <alpine.DEB.2.02.1308102232120.4119@pianoman.cluster.toy>
Vince Weaver [vince@deater.net] wrote:
| On Sat, 10 Aug 2013, Sukadev Bhattiprolu wrote:
|
| >
| > include/uapi/linux/perf_event.h | 55 +++++++++++++++++++++++++++++++++++++++
| > 1 files changed, 55 insertions(+), 0 deletions(-)
|
| > +#define __PERF_LE 1234
| > +#define __PERF_BE 4321
| > +
| > +#if defined(__KERNEL__)
|
| I could be wrong, but I thought files under uapi weren't supposed to
| contain __KERNEL__ code. Wasn't that the whole point of uapi?
|
| Also having the perf_event interface depend on endianess just seems like a
| complicated mess. Can't we just declare the interface to be a certain
| endianess and have the kernel byte-swap as necessary?
Except for the __KERNEL__ check, it looked like this approach would keep
the kernel and user code same. Would it complicate user space ?
I tried to avoid the __KERNEL__ check hack, but like I tried to explain
in the patch, user space and kernel do the endian check differently.
And, there are about ~300 sites in the kernel with __*ENDIAN checks
Sukadev
^ permalink raw reply
* Re: [PATCH 5/7] powerpc/perf: Define big-endian version of perf_mem_data_src
From: Vince Weaver @ 2013-08-11 2:34 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: Anton Blanchard, linux-kernel, Stephane Eranian, linuxppc-dev,
Paul Mackerras, Anshuman Khandual
In-Reply-To: <20130810175153.GF15551@us.ibm.com>
On Sat, 10 Aug 2013, Sukadev Bhattiprolu wrote:
>
> include/uapi/linux/perf_event.h | 55 +++++++++++++++++++++++++++++++++++++++
> 1 files changed, 55 insertions(+), 0 deletions(-)
> +#define __PERF_LE 1234
> +#define __PERF_BE 4321
> +
> +#if defined(__KERNEL__)
I could be wrong, but I thought files under uapi weren't supposed to
contain __KERNEL__ code. Wasn't that the whole point of uapi?
Also having the perf_event interface depend on endianess just seems like a
complicated mess. Can't we just declare the interface to be a certain
endianess and have the kernel byte-swap as necessary?
Vince
^ permalink raw reply
* Re: Build regressions/improvements in v3.11-rc4
From: Geert Uytterhoeven @ 2013-08-10 18:19 UTC (permalink / raw)
To: Linux Kernel Development; +Cc: Linux/PPC Development, linux-sh
In-Reply-To: <alpine.DEB.2.02.1308102018140.30352@ayla.of.borg>
On Sat, 10 Aug 2013, Geert Uytterhoeven wrote:
> JFYI, when comparing v3.11-rc4 to v3.11-rc3[3], the summaries are:
> - build errors: +20/-35
+ arch/powerpc/kernel/cacheinfo.c: error: 'size_kb' may be used uninitialized in this function [-Werror=uninitialized]: => 526:16
+ arch/powerpc/kernel/pci_dn.c: error: 'ret' may be used uninitialized in this function [-Werror=uninitialized]: => 97:8
+ arch/powerpc/kvm/book3s_hv.c: error: 'vcpus_to_update[need_vpa_update]' may be used uninitialized in this function [-Werror=uninitialized]: => 1187:22
+ arch/powerpc/kvm/book3s_xics.c: error: implicit declaration of function 'get_tb' [-Werror=implicit-function-declaration]: => 812:3
+ arch/powerpc/mm/hash_native_64.c: error: 'a_size' may be used uninitialized in this function [-Werror=uninitialized]: => 578:10
+ arch/powerpc/platforms/cell/axon_msi.c: error: 'ph' may be used uninitialized in this function [-Werror=uninitialized]: => 172:2
+ arch/powerpc/platforms/cell/axon_msi.c: error: 'prop' may be used uninitialized in this function [-Werror=uninitialized]: => 237:2
+ arch/powerpc/platforms/cell/beat_iommu.c: error: 'dma_base' may be used uninitialized in this function [-Werror=uninitialized]: => 69:11
+ arch/powerpc/platforms/cell/beat_iommu.c: error: 'dma_size' may be used uninitialized in this function [-Werror=uninitialized]: => 68:2
+ arch/powerpc/platforms/cell/beat_iommu.c: error: 'io_page_size' may be used uninitialized in this function [-Werror=uninitialized]: => 68:54
+ arch/powerpc/platforms/cell/beat_wrapper.h: error: 'io_space_id' may be used uninitialized in this function [-Werror=uninitialized]: => 249:2
+ arch/powerpc/platforms/cell/beat_wrapper.h: error: 'ioid' may be used uninitialized in this function [-Werror=uninitialized]: => 249:2
+ arch/powerpc/platforms/cell/spufs/inode.c: error: incompatible types when assigning to type 'kgid_t' from type 'int': => 628:16
+ arch/powerpc/platforms/cell/spufs/inode.c: error: incompatible types when assigning to type 'kuid_t' from type 'int': => 623:16
+ arch/powerpc/platforms/powernv/pci-ioda.c: error: 'hose' may be used uninitialized in this function [-Werror=uninitialized]: => 1175:74
+ arch/powerpc/platforms/pseries/pci.c: error: 'pcie_link_speed_stats' may be used uninitialized in this function [-Werror=uninitialized]: => 150:31
powerpc-randconfig
+ arch/sh/mm/cache-sh4.c: error: 'cached_to_uncached' undeclared (first use in this function): => 99:17
+ arch/sh/mm/cache-sh4.c: error: implicit declaration of function 'cpu_context' [-Werror=implicit-function-declaration]: => 192:2
sh-randconfig
> [1] http://kisskb.ellerman.id.au/kisskb/head/6510/ (all 120 configs)
> [3] http://kisskb.ellerman.id.au/kisskb/head/6490/ (all 120 configs)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 7/7] powerpc/perf: Export Power7 memory hierarchy info to user space
From: Sukadev Bhattiprolu @ 2013-08-10 17:52 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 7/7] powerpc/perf: Export Power7 memory hierarchy info to user space.
On Power7, the DCACHE_SRC field in MMCRA register identify the memory
hierarchy level (eg: L1, L2 etc) from which a data-cache miss for a
marked instruction was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Some memory hierarchy levels in Power7 don't map into the arch-neutral
levels. However, since newer generation of the processor (i.e. Power8) uses
fewer levels than in Power7, we don't really need to define new hierarchy
levels just for Power7.
We instead, map as many levels as possible and approximate the rest. See
comments near dcache-src_map[] in the patch.
The hierarchy level information could be used with 'perf record --data'
or 'perf mem' command to analyze application behavior.
Usage:
perf mem record <application>
perf mem report
OR
perf record --data <application>
perf report -D
Sample records contain a 'data_src' field which encodes the memory
hierarchy level: Eg: data_src 0x442 indicates MEM_OP_LOAD, MEM_LVL_HIT,
MEM_LVL_L2 (i.e load hit L2).
Cc: Stephane Eranian <eranian@google.com>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
Thanks to input from Stephane Eranian and Michael Ellerman.
Changelog[v3]:
[Michael Ellerman] If newer levels that we defined in [v2] are not
needed for Power8, ignore the new levels for Power7 also, and
approximate them.
Separate the TLB level mapping to a separate patchset.
Changelog[v2]:
[Stephane Eranian] Define new levels rather than ORing the L2 and L3
with REM_CCE1 and REM_CCE2.
[Stephane Eranian] allocate a bit PERF_MEM_XLVL_NA for architectures
that don't use the ->mem_xlvl field.
Insert the TLB patch ahead so the new TLB bits are contigous with
existing TLB bits.
arch/powerpc/perf/power7-pmu.c | 65 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 65 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 161861d..f8143d6 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -329,6 +329,70 @@ static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
}
+#define POWER7_MMCRA_DCACHE_MISS (0x1LL << 55)
+#define POWER7_MMCRA_DCACHE_SRC_SHIFT 51
+#define POWER7_MMCRA_DCACHE_SRC_MASK (0xFLL << POWER7_MMCRA_DCACHE_SRC_SHIFT)
+
+#define P(a, b) PERF_MEM_S(a, b)
+#define PLH(a, b) (P(OP, LOAD) | P(LVL, HIT) | P(a, b))
+/*
+ * Map the Power7 DCACHE_SRC field (bits 9..12) in MMCRA register to the
+ * architecture-neutral memory hierarchy levels. For the levels in Power7
+ * that don't map to the arch-neutral levels, approximate to nearest
+ * level.
+ *
+ * 1-hop: indicates another core on the same chip (2.1 and 3.1 levels).
+ * 2-hops: indicates a different chip on same or different node (remote
+ * and distant levels).
+ *
+ * For consistency with this interpretation of the hops, we dont use
+ * the REM_RAM1 level below.
+ *
+ * The *SHR and *MOD states of the cache are ignored/not exported to user.
+ *
+ * ### Levels marked with ### in comments below are approximated
+ */
+static u64 dcache_src_map[] = {
+ PLH(LVL, L2), /* 00: FROM_L2 */
+ PLH(LVL, L3), /* 01: FROM_L3 */
+
+ P(LVL, NA), /* 02: Reserved */
+ P(LVL, NA), /* 03: Reserved */
+
+ PLH(LVL, REM_CCE1), /* 04: FROM_L2.1_SHR ### */
+ PLH(LVL, REM_CCE1), /* 05: FROM_L2.1_MOD ### */
+
+ PLH(LVL, REM_CCE1), /* 06: FROM_L3.1_SHR ### */
+ PLH(LVL, REM_CCE1), /* 07: FROM_L3.1_MOD ### */
+
+ PLH(LVL, REM_CCE2), /* 08: FROM_RL2L3_SHR ### */
+ PLH(LVL, REM_CCE2), /* 09: FROM_RL2L3_MOD ### */
+
+ PLH(LVL, REM_CCE2), /* 10: FROM_DL2L3_SHR ### */
+ PLH(LVL, REM_CCE2), /* 11: FROM_DL2L3_MOD ### */
+
+ PLH(LVL, LOC_RAM), /* 12: FROM_LMEM */
+ PLH(LVL, REM_RAM2), /* 13: FROM_RMEM ### */
+ PLH(LVL, REM_RAM2), /* 14: FROM_DMEM */
+
+ P(LVL, NA), /* 15: Reserved */
+};
+
+static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ u64 idx;
+ u64 mmcra = regs->dsisr;
+
+ if (mmcra & POWER7_MMCRA_DCACHE_MISS) {
+ idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK;
+ idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT;
+
+ dsrc->val |= dcache_src_map[idx];
+ }
+}
+
+
static int power7_generic_events[] = {
[PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC,
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
@@ -453,6 +517,7 @@ static struct power_pmu power7_pmu = {
.get_constraint = power7_get_constraint,
.get_alternatives = power7_get_alternatives,
.disable_pmc = power7_disable_pmc,
+ .get_mem_data_src = power7_get_mem_data_src,
.flags = PPMU_ALT_SIPR,
.attr_groups = power7_pmu_attr_groups,
.n_generic = ARRAY_SIZE(power7_generic_events),
--
1.7.1
^ permalink raw reply related
* [PATCH 6/7] powerpc/perf: Export Power8 memory hierarchy info to user space
From: Sukadev Bhattiprolu @ 2013-08-10 17:52 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 6/7] powerpc/perf: Export Power8 memory hierarchy info to user space.
On Power8, the LDST field in SIER identifies the memory hierarchy level
(eg: L1, L2 etc), from which a data-cache miss for a marked instruction
was satisfied.
Use the 'perf_mem_data_src' object to export this hierarchy level to user
space. Fortunately, the memory hierarchy levels in Power8 map fairly easily
into the arch-neutral levels as described by the ldst_src_map[] table.
This hierarchy level information can be used with 'perf record --data'
or 'perf mem' command to analyze application behavior.
Usage:
$ perf mem record <application>
$ perf mem report
OR
$ perf record --data <application>
$ perf report -D
Sample records contain a 'data_src' field which encodes the memory
hierarchy level: Eg: data_src 0x442 indicates MEM_OP_LOAD, MEM_LVL_HIT,
MEM_LVL_L2 (i.e load hit L2).
Cc: Stephane Eranian <eranian@google.com>
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/perf_event_server.h | 2 +
arch/powerpc/perf/core-book3s.c | 11 +++++
arch/powerpc/perf/power8-pmu.c | 53 ++++++++++++++++++++++++++
3 files changed, 66 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index cc5f45b..2252798 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -37,6 +37,8 @@ struct power_pmu {
void (*config_bhrb)(u64 pmu_bhrb_filter);
void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
int (*limited_pmc_event)(u64 event_id);
+ void (*get_mem_data_src)(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs);
u32 flags;
const struct attribute_group **attr_groups;
int n_generic;
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index a3985ae..e61fd05 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1693,6 +1693,13 @@ ssize_t power_events_sysfs_show(struct device *dev,
return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
}
+static inline void power_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ if (ppmu->get_mem_data_src)
+ ppmu->get_mem_data_src(dsrc, regs);
+}
+
struct pmu power_pmu = {
.pmu_enable = power_pmu_enable,
.pmu_disable = power_pmu_disable,
@@ -1774,6 +1781,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
data.br_stack = &cpuhw->bhrb_stack;
}
+ if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
+ ppmu->get_mem_data_src)
+ ppmu->get_mem_data_src(&data.data_src, regs);
+
if (perf_event_overflow(event, &data, regs))
power_pmu_stop(event, 0);
}
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 0a7b632..2aaae63 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -538,6 +538,58 @@ static struct attribute_group power8_pmu_events_group = {
.attrs = power8_events_attr,
};
+#define POWER8_SIER_TYPE_SHIFT 15
+#define POWER8_SIER_TYPE_MASK (0x7LL << POWER8_SIER_TYPE_SHIFT)
+
+#define POWER8_SIER_LDST_SHIFT 1
+#define POWER8_SIER_LDST_MASK (0x7LL << POWER8_SIER_LDST_SHIFT)
+
+#define P(a, b) PERF_MEM_S(a, b)
+#define PLH(a, b) (P(OP, LOAD) | P(LVL, HIT) | P(a, b))
+#define PSM(a, b) (P(OP, STORE) | P(LVL, MISS) | P(a, b))
+
+/*
+ * Power8 interpretations:
+ * REM_CCE1: 1-hop indicates L2/L3 cache of a different core on same chip
+ * REM_CCE2: 2-hop indicates different chip or different node.
+ */
+static u64 ldst_src_map[] = {
+ /* 000 */ P(LVL, NA),
+
+ /* 001 */ PLH(LVL, L1),
+ /* 010 */ PLH(LVL, L2),
+ /* 011 */ PLH(LVL, L3),
+ /* 100 */ PLH(LVL, LOC_RAM),
+ /* 101 */ PLH(LVL, REM_CCE1),
+ /* 110 */ PLH(LVL, REM_CCE2),
+
+ /* 111 */ PSM(LVL, L1),
+};
+
+static inline bool is_load_store_inst(u64 sier)
+{
+ u64 val;
+ val = (sier & POWER8_SIER_TYPE_MASK) >> POWER8_SIER_TYPE_SHIFT;
+
+ /* 1 = load, 2 = store */
+ return val == 1 || val == 2;
+}
+
+static void power8_get_mem_data_src(union perf_mem_data_src *dsrc,
+ struct pt_regs *regs)
+{
+ u64 idx;
+ u64 sier;
+
+ sier = mfspr(SPRN_SIER);
+
+ if (is_load_store_inst(sier)) {
+ idx = (sier & POWER8_SIER_LDST_MASK) >> POWER8_SIER_LDST_SHIFT;
+
+ dsrc->val |= ldst_src_map[idx];
+ }
+}
+
PMU_FORMAT_ATTR(event, "config:0-49");
PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
PMU_FORMAT_ATTR(mark, "config:8");
@@ -641,6 +693,7 @@ static struct power_pmu power8_pmu = {
.get_constraint = power8_get_constraint,
.get_alternatives = power8_get_alternatives,
.disable_pmc = power8_disable_pmc,
+ .get_mem_data_src = power8_get_mem_data_src,
.flags = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
.n_generic = ARRAY_SIZE(power8_generic_events),
.generic_events = power8_generic_events,
--
1.7.1
^ permalink raw reply related
* [PATCH 5/7] powerpc/perf: Define big-endian version of perf_mem_data_src
From: Sukadev Bhattiprolu @ 2013-08-10 17:51 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 5/7] powerpc/perf: Define big-endian version of perf_mem_data_src
perf_mem_data_src is an union that is initialized via the ->val field
and accessed via the bitmap fields. For this to work on big endian
platforms, we also need a big-endian represenation of perf_mem_data_src.
Cc: Stephane Eranian <eranian@google.com>
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
Thanks to input from Stephane Eranian and Michael Ellerman.
include/uapi/linux/perf_event.h | 55 +++++++++++++++++++++++++++++++++++++++
1 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 62c25a2..8497c51 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -19,6 +19,47 @@
#include <asm/byteorder.h>
/*
+ * Kernel and userspace check for endianness in incompatible ways.
+ * In user space, <endian.h> defines both __BIG_ENDIAN and __LITTLE_ENDIAN
+ * but sets __BYTE_ORDER to one or the other. So user space uses checks are:
+ *
+ * #if __BYTE_ORDER == __LITTLE_ENDIAN
+ *
+ * In the kernel, __BYTE_ORDER is undefined, so using the above check doesn't
+ * work. Further, kernel code assumes that exactly one of __BIG_ENDIAN and
+ * __LITTLE_ENDIAN is defined. So the kernel checks are like:
+ *
+ * #if defined(__LITTLE_ENDIAN)
+ *
+ * But we can't use that check in user space since __LITTLE_ENDIAN (and
+ * __BIG_ENDIAN) are always defined.
+ *
+ * Since some perf data structures depend on endianness _and_ are shared
+ * between kernel and user, perf needs its own notion of endian macros (at
+ * least until user and kernel endian checks converge).
+ */
+#define __PERF_LE 1234
+#define __PERF_BE 4321
+
+#if defined(__KERNEL__)
+
+#if defined(__LITTLE_ENDIAN)
+#define __PERF_BYTE_ORDER __PERF_LE
+#elif defined(__BIG_ENDIAN)
+#define __PERF_BYTE_ORDER __PERF_BE
+#endif
+
+#else /* __KERNEL__ */
+
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define __PERF_BYTE_ORDER __PERF_LE
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define __PERF_BYTE_ORDER __PERF_BE
+#endif
+
+#endif /* __KERNEL__ */
+
+/*
* User-space ABI bits:
*/
@@ -659,6 +700,7 @@ enum perf_callchain_context {
#define PERF_FLAG_FD_OUTPUT (1U << 1)
#define PERF_FLAG_PID_CGROUP (1U << 2) /* pid=cgroup id, per-cpu mode only */
+#if __PERF_BYTE_ORDER == __PERF_LE
union perf_mem_data_src {
__u64 val;
struct {
@@ -670,6 +712,19 @@ union perf_mem_data_src {
mem_rsvd:31;
};
};
+#elif __PERF_BYTE_ORDER == __PERF_BE
+union perf_mem_data_src {
+ __u64 val;
+ struct {
+ __u64 mem_rsvd:31,
+ mem_dtlb:7, /* tlb access */
+ mem_lock:2, /* lock instr */
+ mem_snoop:5, /* snoop mode */
+ mem_lvl:14, /* memory hierarchy level */
+ mem_op:5; /* type of opcode */
+ };
+};
+#endif
/* type of opcode (load/store/prefetch,code) */
#define PERF_MEM_OP_NA 0x01 /* not available */
--
1.7.1
^ permalink raw reply related
* [PATCH 4/7] powerpc/perf: Create mem-loads/mem-stores events for Power7
From: Sukadev Bhattiprolu @ 2013-08-10 17:51 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 4/7] powerpc/perf: Create mem-loads/mem-stores events for Power7
'perf mem' command depends on the support for generic hardware events
'mem-loads' and 'mem-stores'.
Create those events for Power7 and map them both to the event PM_MRK_GRP_CMPL.
While PM_MRK_GRP_CMPL is strictly not restricted to loads and stores, that
seems to be a close/resonable match.
Cc: Stephane Eranian <eranian@google.com>
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/power7-pmu.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 56c67bc..161861d 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -58,6 +58,18 @@
enum {
#include "power7-events-list.h"
+ /*
+ * Normally, generic events like 'cycles' are aliases for a real
+ * event PM_CYC. So we want both the event and the alias listed in
+ * sysfs. But mem-loads and mem-stores are just aliases - they are
+ * not listed in power7_generic_events[] for instance. Adding them
+ * to power7-events-list.h will unnecessariliy create PM_MEM_LOADS
+ * and PM_MEM_STORES events in sysfs when that file is processed
+ * again below. To save a couple of sysfs entries, define these
+ * separately.
+ */
+ EVENT(PM_MEM_LOADS, 0x40030)
+ EVENT(PM_MEM_STORES, 0x40030)
};
#undef EVENT
@@ -382,6 +394,8 @@ GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED);
+GENERIC_EVENT_ATTR(mem-loads, PM_MEM_LOADS);
+GENERIC_EVENT_ATTR(mem-stores, PM_MEM_STORES);
#define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _name);
#include "power7-events-list.h"
@@ -398,6 +412,8 @@ static struct attribute *power7_events_attr[] = {
GENERIC_EVENT_PTR(PM_LD_MISS_L1),
GENERIC_EVENT_PTR(PM_BRU_FIN),
GENERIC_EVENT_PTR(PM_BR_MPRED),
+ GENERIC_EVENT_PTR(PM_MEM_LOADS),
+ GENERIC_EVENT_PTR(PM_MEM_STORES),
#include "power7-events-list.h"
#undef EVENT
--
1.7.1
^ permalink raw reply related
* [PATCH 3/7] powerpc/perf: Create mem-loads/mem-stores events for Power8
From: Sukadev Bhattiprolu @ 2013-08-10 17:50 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 3/7] powerpc/perf: Create mem-loads/mem-stores events for Power8
'perf mem' command depends on the support for generic hardware events
'mem-loads' and 'mem-stores'.
Create those events for Power8 and map them both to the event PM_MRK_GRP_CMPL.
While PM_MRK_GRP_CMPL is strictly not restricted to loads and stores, that
seems to be a close/resonable match.
Cc: Stephane Eranian <eranian@google.com>
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/power8-pmu.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index ff98fb8..0a7b632 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -24,6 +24,8 @@
#define PME_PM_INST_CMPL 0x00002
#define PME_PM_BRU_FIN 0x10068
#define PME_PM_BR_MPRED_CMPL 0x400f6
+#define PME_PM_MEM_LOADS 0x40130
+#define PME_PM_MEM_STORES 0x40130
/*
@@ -516,6 +518,8 @@ GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
+GENERIC_EVENT_ATTR(mem-loads, PM_MEM_LOADS);
+GENERIC_EVENT_ATTR(mem-stores, PM_MEM_STORES);
static struct attribute *power8_events_attr[] = {
GENERIC_EVENT_PTR(PM_CYC),
@@ -524,6 +528,8 @@ static struct attribute *power8_events_attr[] = {
GENERIC_EVENT_PTR(PM_INST_CMPL),
GENERIC_EVENT_PTR(PM_BRU_FIN),
GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
+ GENERIC_EVENT_PTR(PM_MEM_LOADS),
+ GENERIC_EVENT_PTR(PM_MEM_STORES),
NULL
};
--
1.7.1
^ permalink raw reply related
* [PATCH 2/7] powerpc/perf: Export Power8 generic events in sysfs
From: Sukadev Bhattiprolu @ 2013-08-10 17:50 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 2/7] powerpc/perf: Export Power8 generic events in sysfs
Export existing Power8 generic events in sysfs.
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/power8-pmu.c | 23 +++++++++++++++++++++++
1 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 30c6b12..ff98fb8 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -510,6 +510,28 @@ static void power8_disable_pmc(unsigned int pmc, unsigned long mmcr[])
mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
}
+GENERIC_EVENT_ATTR(cpu-cyles, PM_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
+GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
+GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
+GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
+GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
+
+static struct attribute *power8_events_attr[] = {
+ GENERIC_EVENT_PTR(PM_CYC),
+ GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
+ GENERIC_EVENT_PTR(PM_CMPLU_STALL),
+ GENERIC_EVENT_PTR(PM_INST_CMPL),
+ GENERIC_EVENT_PTR(PM_BRU_FIN),
+ GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
+ NULL
+};
+
+static struct attribute_group power8_pmu_events_group = {
+ .name = "events",
+ .attrs = power8_events_attr,
+};
+
PMU_FORMAT_ATTR(event, "config:0-49");
PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
PMU_FORMAT_ATTR(mark, "config:8");
@@ -546,6 +568,7 @@ struct attribute_group power8_pmu_format_group = {
static const struct attribute_group *power8_pmu_attr_groups[] = {
&power8_pmu_format_group,
+ &power8_pmu_events_group,
NULL,
};
--
1.7.1
^ permalink raw reply related
* [PATCH 1/7] powerpc/perf: Rename Power8 macros to start with PME
From: Sukadev Bhattiprolu @ 2013-08-10 17:49 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
In-Reply-To: <20130810174831.GA15551@us.ibm.com>
[PATCH 1/7] powerpc/perf: Rename Power8 macros to start with PME
We use helpers like GENERIC_EVENT_ATTR() to list the generic events in
sysfs. To avoid name collisions, GENERIC_EVENT_ATTR() requires the perf
event macros to start with PME.
Cc: Paul Mckerras <paulus@samba.org>
Cc: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/power8-pmu.c | 24 ++++++++++++------------
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 96a64d6..30c6b12 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -18,12 +18,12 @@
/*
* Some power8 event codes.
*/
-#define PM_CYC 0x0001e
-#define PM_GCT_NOSLOT_CYC 0x100f8
-#define PM_CMPLU_STALL 0x4000a
-#define PM_INST_CMPL 0x00002
-#define PM_BRU_FIN 0x10068
-#define PM_BR_MPRED_CMPL 0x400f6
+#define PME_PM_CYC 0x0001e
+#define PME_PM_GCT_NOSLOT_CYC 0x100f8
+#define PME_PM_CMPLU_STALL 0x4000a
+#define PME_PM_INST_CMPL 0x00002
+#define PME_PM_BRU_FIN 0x10068
+#define PME_PM_BR_MPRED_CMPL 0x400f6
/*
@@ -550,12 +550,12 @@ static const struct attribute_group *power8_pmu_attr_groups[] = {
};
static int power8_generic_events[] = {
- [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
- [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
- [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
- [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
- [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
- [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
+ [PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC,
+ [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PME_PM_CMPLU_STALL,
+ [PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN,
+ [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BR_MPRED_CMPL,
};
static u64 power8_bhrb_filter_map(u64 branch_sample_type)
--
1.7.1
^ permalink raw reply related
* [PATCH 0/7]: Enable 'perf mem' command for Power
From: Sukadev Bhattiprolu @ 2013-08-10 17:48 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
Cc: Anton Blanchard, Paul Mackerras, Stephane Eranian,
Anshuman Khandual
[PATCH 0/7]: Enable 'perf mem' command for Power
'perf mem' command enables analyzing the memory operations of an
application. It needs the kernel to export the memory hierarcy
level from which a load instruction was satisfied.
It also needs the Power kernel to make the 'mem-loads' and 'mem-stores'
generic events available in sysfs. While there, we also export the
other Power8 generic events in sysfs.
Thanks to input from Stephane Eranian and Michael Ellerman.
P.S. The patchset builds on several configurations including pmac32_defconfig.
But I am unable to verify the build on few other configs due to a problem
unrleated to this patchset. That is being discussed in a separate thread.
I would like some feedback on this patchset in the meanwhile.
Sukadev Bhattiprolu (7):
powerpc/perf: Rename Power8 macros to start with PME
powerpc/perf: Export Power8 generic events in sysfs
powerpc/perf: Create mem-loads/mem-stores events for Power8
powerpc/perf: Create mem-loads/mem-stores events for Power7
powerpc/perf: Define big-endian version of perf_mem_data_src
powerpc/perf: Export Power8 memory hierarchy info to user space.
powerpc/perf: Export Power7 memory hierarchy info to user space.
arch/powerpc/include/asm/perf_event_server.h | 2 +
arch/powerpc/perf/core-book3s.c | 11 +++
arch/powerpc/perf/power7-pmu.c | 81 ++++++++++++++++++++
arch/powerpc/perf/power8-pmu.c | 106 +++++++++++++++++++++++---
include/uapi/linux/perf_event.h | 55 +++++++++++++
5 files changed, 243 insertions(+), 12 deletions(-)
^ permalink raw reply
* Re: Build errors on mainline kernel
From: Andreas Schwab @ 2013-08-10 17:47 UTC (permalink / raw)
To: Sukadev Bhattiprolu; +Cc: linuxppc-dev
In-Reply-To: <20130810164526.GA11718@us.ibm.com>
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
> Andreas Schwab [schwab@linux-m68k.org] wrote:
> | Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
> |
> | > {standard input}: Assembler messages:
> | > {standard input}:244: Error: junk at end of line: `1'
> | > make[2]: *** [arch/powerpc/platforms/85xx/smp.o] Error 1
> | > make[1]: *** [arch/powerpc/platforms/85xx/smp.o] Error 2
> | > make: *** [sub-make] Error 2
> |
> | Run "make arch/powerpc/platforms/85xx/smp.s" to create the assembler
> | file.
>
> Ok. Here are few lines around 244, the whole file is below. I can't
> find the junk '1'. There is a '1' at EOL on 240 but that is also
> on several lines in the file.
The offending line is line 307 (due to the added comments at the start):
mfcr 0,1 # tmp145, tmp146
This is a Power4 insn, but you are compiling for e500.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: Build errors on mainline kernel
From: Sukadev Bhattiprolu @ 2013-08-10 16:45 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev
In-Reply-To: <m2y58axbi8.fsf@linux-m68k.org>
Andreas Schwab [schwab@linux-m68k.org] wrote:
| Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
|
| > {standard input}: Assembler messages:
| > {standard input}:244: Error: junk at end of line: `1'
| > make[2]: *** [arch/powerpc/platforms/85xx/smp.o] Error 1
| > make[1]: *** [arch/powerpc/platforms/85xx/smp.o] Error 2
| > make: *** [sub-make] Error 2
|
| Run "make arch/powerpc/platforms/85xx/smp.s" to create the assembler
| file.
Ok. Here are few lines around 244, the whole file is below. I can't
find the junk '1'. There is a '1' at EOL on 240 but that is also
on several lines in the file.
239 #APP
240 # 161 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
241 sync;lwz 0,112(9);twi 0,0,0;isync #, tmp171
242 # 0 "" 2
243 #NO_APP
244 cmpdi 7,31,0 #, tmp172, flags
245 beq 7,.L23 #
246 bl .trace_hardirqs_on #
247 nop
248 mr 3,31 #, flags
249 bl .arch_local_irq_restore #
250 nop
---
.file "smp.c"
# rs6000/powerpc options: -mcpu=power4 -mtune=power7 -msdata=none
.section ".toc","aw"
.section ".text"
# GNU C (GCC) version 4.4.6 20120305 (Red Hat 4.4.6-4) (ppc64-redhat-linux)
# compiled by GNU C version 4.4.6 20120305 (Red Hat 4.4.6-4), GMP version 4.3.1, MPFR version 2.4.1.
# GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072
# options passed: -nostdinc -I/root/tmp/linux.git/arch/powerpc/include
# -Iarch/powerpc/include/generated -I/root/tmp/linux.git/include -Iinclude
# -I/root/tmp/linux.git/arch/powerpc/include/uapi
# -Iarch/powerpc/include/generated/uapi -I/root/tmp/linux.git/include/uapi
# -Iinclude/generated/uapi
# -I/root/tmp/linux.git/arch/powerpc/platforms/85xx
# -Iarch/powerpc/platforms/85xx -I/root/tmp/linux.git/arch/powerpc
# -Iarch/powerpc -I/root/tmp/linux.git/arch/powerpc -Iarch/powerpc
# -D__unix__ -D__gnu_linux__ -D__linux__ -Dunix -D__unix -Dlinux -D__linux
# -Asystem=linux -Asystem=unix -Asystem=posix -D__KERNEL__
# -DCC_HAVE_ASM_GOTO -DKBUILD_STR(s)=#s -DKBUILD_BASENAME=KBUILD_STR(smp)
# -DKBUILD_MODNAME=KBUILD_STR(smp) -isystem
# /usr/lib/gcc/ppc64-redhat-linux/4.4.6/include -include
# /root/tmp/linux.git/include/linux/kconfig.h -MD
# arch/powerpc/platforms/85xx/.smp.s.d
# /root/tmp/linux.git/arch/powerpc/platforms/85xx/smp.c -mbig -msecure-plt
# -m64 -msoft-float -mtraceback=no -mcall-aixdesc -mcmodel=medium
# -mtune=power7 -mno-altivec -mno-vsx -mno-spe -mspe=no -mno-string
# -mcpu=power4 -auxbase-strip arch/powerpc/platforms/85xx/smp.s -O2 -Wall
# -Wundef -Wstrict-prototypes -Wno-trigraphs
# -Werror-implicit-function-declaration -Wno-format-security
# -Wframe-larger-than=2048 -Wno-unused-but-set-variable
# -Wdeclaration-after-statement -Wno-pointer-sign -fno-strict-aliasing
# -fno-common -fno-delete-null-pointer-checks -funit-at-a-time
# -fno-dwarf2-cfi-asm -fno-stack-protector -fomit-frame-pointer
# -fno-strict-overflow -fconserve-stack -fverbose-asm
# options enabled: -falign-loops -fargument-alias -fauto-inc-dec
# -fbranch-count-reg -fcaller-saves -fcprop-registers -fcrossjumping
# -fcse-follow-jumps -fdefer-pop -fearly-inlining
# -feliminate-unused-debug-types -fexpensive-optimizations
# -fforward-propagate -ffunction-cse -fgcse -fgcse-lm
# -fguess-branch-probability -fident -fif-conversion -fif-conversion2
# -findirect-inlining -finline -finline-functions-called-once
# -finline-small-functions -fipa-cp -fipa-pure-const -fipa-reference
# -fira-share-save-slots -fira-share-spill-slots -fivopts
# -fkeep-static-consts -fleading-underscore -fmath-errno -fmerge-constants
# -fmerge-debug-strings -fmove-loop-invariants -fomit-frame-pointer
# -foptimize-register-move -foptimize-sibling-calls -fpeephole -fpeephole2
# -freg-struct-return -fregmove -freorder-blocks -freorder-functions
# -frerun-cse-after-loop -fsched-interblock -fsched-spec
# -fsched-stalled-insns-dep -fschedule-insns -fschedule-insns2
# -fsection-anchors -fsigned-zeros -fsplit-ivs-in-unroller
# -fsplit-wide-types -fthread-jumps -ftoplevel-reorder -ftrapping-math
# -ftree-builtin-call-dce -ftree-ccp -ftree-ch -ftree-coalesce-vars
# -ftree-copy-prop -ftree-copyrename -ftree-cselim -ftree-dce
# -ftree-dominator-opts -ftree-dse -ftree-fre -ftree-loop-im
# -ftree-loop-ivcanon -ftree-loop-optimize -ftree-parallelize-loops=
# -ftree-pre -ftree-reassoc -ftree-scev-cprop -ftree-sink -ftree-sra
# -ftree-switch-conversion -ftree-ter -ftree-vect-loop-version -ftree-vrp
# -funit-at-a-time -fverbose-asm -fzero-initialized-in-bss -m64
# -maix-struct-return -malign-branch-targets -malways-hint -mbig
# -mbig-endian -mfp-in-toc -mfused-madd -mgen-cell-microcode -mglibc
# -mmfcrf -mnew-mnemonics -mpowerpc -mpowerpc-gfxopt -mpowerpc-gpopt
# -mpowerpc64 -msched-groups -msched-prolog -msecure-plt -msoft-float
# -mupdate -mvectorize-builtins -mvrsave -mvsx-scalar-double
# Compiler executable checksum: ada2cddef4477a14790d56c4372eb769
.align 2
.p2align 4,,15
.section ".opd","aw"
.align 3
mpc85xx_take_timebase:
.quad .mpc85xx_take_timebase,.TOC.@tocbase
.previous
.size mpc85xx_take_timebase,24
.type .mpc85xx_take_timebase,@function
.mpc85xx_take_timebase:
mflr 0 #,
std 31,-8(1) #,
std 0,16(1) #,
stdu 1,-128(1) #,,
#APP
# 59 "/root/tmp/linux.git/arch/powerpc/include/asm/hw_irq.h" 1
li 0,0; lbz 31,850(13); stb 0,850(13) # zero, flags,
# 0 "" 2
#NO_APP
bl .trace_hardirqs_off #
nop
addis 11,2,.LANCHOR0@toc@ha # tmp143,,
addi 9,11,.LANCHOR0@toc@l # tmp144, tmp143,
lwz 0,4(9) # tb_valid,
cmpwi 7,0,0 #, tmp128, tb_valid
li 0,1 # tmp124,
stw 0,.LANCHOR0@toc@l(11) # tb_req, tmp124
bne 7,.L2 #
.p2align 4,,15
.L7:
lwz 0,4(9) # tb_valid,
cmpwi 7,0,0 #, tmp132, tb_valid
beq 7,.L7 #
.L2:
ld 11,8(9) # timebase, timebase.511
li 0,0 # tmp135,
#APP
# 131 "/root/tmp/linux.git/arch/powerpc/include/asm/time.h" 1
mtspr 0x11C,0 # tmp135
# 0 "" 2
#NO_APP
srdi 10,11,32 # tmp137, timebase.511,
#APP
# 132 "/root/tmp/linux.git/arch/powerpc/include/asm/time.h" 1
mtspr 0x11D,10 # tmp137
# 0 "" 2
#NO_APP
rldicl 11,11,0,32 # timebase.511, timebase.511
#APP
# 133 "/root/tmp/linux.git/arch/powerpc/include/asm/time.h" 1
mtspr 0x11C,11 # timebase.511
# 0 "" 2
# 25 "/root/tmp/linux.git/arch/powerpc/include/asm/synch.h" 1
isync
# 0 "" 2
#NO_APP
cmpdi 7,31,0 #, tmp142, flags
stw 0,4(9) # tb_valid, tmp135
beq 7,.L10 #
bl .trace_hardirqs_on #
nop
mr 3,31 #, flags
bl .arch_local_irq_restore #
nop
addi 1,1,128 #,,
ld 0,16(1) #,
ld 31,-8(1) #,
mtlr 0 #,
blr #
.p2align 4,,15
.L10:
li 3,0 #,
bl .arch_local_irq_restore #
nop
bl .trace_hardirqs_off #
nop
addi 1,1,128 #,,
ld 0,16(1) #,
ld 31,-8(1) #,
mtlr 0 #,
blr #
.size .mpc85xx_take_timebase,.-.mpc85xx_take_timebase
.align 2
.p2align 4,,15
.section ".opd","aw"
.align 3
mpc85xx_give_timebase:
.quad .mpc85xx_give_timebase,.TOC.@tocbase
.previous
.size mpc85xx_give_timebase,24
.type .mpc85xx_give_timebase,@function
.mpc85xx_give_timebase:
mflr 0 #,
std 31,-8(1) #,
std 0,16(1) #,
stdu 1,-128(1) #,,
#APP
# 59 "/root/tmp/linux.git/arch/powerpc/include/asm/hw_irq.h" 1
li 0,0; lbz 31,850(13); stb 0,850(13) # zero, flags,
# 0 "" 2
#NO_APP
bl .trace_hardirqs_off #
nop
addis 11,2,.LANCHOR0@toc@ha # tmp173,,
lwz 0,.LANCHOR0@toc@l(11) # tb_req,
cmpwi 7,0,0 #, tmp135, tb_req
bne 7,.L22 #
addi 9,11,.LANCHOR0@toc@l # tmp174, tmp173,
.p2align 4,,15
.L13:
lwz 0,0(9) # tb_req,
cmpwi 7,0,0 #, tmp139, tb_req
beq 7,.L13 #
.L12:
li 0,0 # tmp142,
stw 0,.LANCHOR0@toc@l(11) # tb_req, tmp142
ld 11,16(9) # guts, guts
#APP
# 161 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;lwz 0,112(11);twi 0,0,0;isync #, tmp146
# 0 "" 2
#NO_APP
ori 0,0,20480 #, tmp147, tmp146,
rldicl 0,0,0,32 # D.32947, tmp147
#APP
# 167 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;stw 0,112(11) #, D.32947
# 0 "" 2
#NO_APP
li 0,1 # tmp148,
stb 0,852(13) # <variable>.io_sync, tmp148
ld 11,16(9) # guts, guts
#APP
# 161 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;lwz 0,112(11);twi 0,0,0;isync #, tmp152
# 0 "" 2
# 107 "/root/tmp/linux.git/arch/powerpc/include/asm/time.h" 1
mftb 0 # rval
# 0 "" 2
#NO_APP
std 0,8(9) # timebase, rval
#APP
# 73 "/root/tmp/linux.git/arch/powerpc/platforms/85xx/smp.c" 1
sync
# 0 "" 2
#NO_APP
li 0,1 # tmp157,
mr 11,9 # tmp177, tmp174
stw 0,4(9) # tb_valid, tmp157
.p2align 4,,15
.L14:
lwz 0,4(9) # tb_valid,
cmpwi 7,0,0 #, tmp161, tb_valid
bne 7,.L14 #
ld 9,16(11) # guts, guts
#APP
# 161 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;lwz 10,112(9);twi 0,10,0;isync #, tmp165
# 0 "" 2
#NO_APP
lis 0,0xffff # tmp166,
ori 0,0,45055 #, tmp166, tmp166,
rldicl 0,0,0,32 # tmp166, tmp166
and 0,0,10 # D.32963, tmp166, tmp165
#APP
# 167 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;stw 0,112(9) #, D.32963
# 0 "" 2
#NO_APP
li 0,1 # tmp167,
stb 0,852(13) # <variable>.io_sync, tmp167
ld 9,16(11) # guts, guts
#APP
# 161 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;lwz 0,112(9);twi 0,0,0;isync #, tmp171
# 0 "" 2
#NO_APP
cmpdi 7,31,0 #, tmp172, flags
beq 7,.L23 #
bl .trace_hardirqs_on #
nop
mr 3,31 #, flags
bl .arch_local_irq_restore #
nop
addi 1,1,128 #,,
ld 0,16(1) #,
ld 31,-8(1) #,
mtlr 0 #,
blr #
.p2align 4,,15
.L23:
li 3,0 #,
bl .arch_local_irq_restore #
nop
bl .trace_hardirqs_off #
nop
addi 1,1,128 #,,
ld 0,16(1) #,
ld 31,-8(1) #,
mtlr 0 #,
blr #
.L22:
addi 9,11,.LANCHOR0@toc@l # tmp174, tmp173,
b .L12 #
.size .mpc85xx_give_timebase,.-.mpc85xx_give_timebase
.section ".toc","aw"
.LC0:
.tc paca[TC],paca
.LC4:
.tc high_memory[TC],high_memory
.LC5:
.tc generic_secondary_smp_init[TC],generic_secondary_smp_init
.section ".text"
.align 2
.p2align 4,,15
.section ".opd","aw"
.align 3
smp_85xx_kick_cpu:
.quad .smp_85xx_kick_cpu,.TOC.@tocbase
.previous
.size smp_85xx_kick_cpu,24
.type .smp_85xx_kick_cpu,@function
.smp_85xx_kick_cpu:
mflr 0 #,
std 28,-32(1) #,
mfcr 12 #
std 29,-24(1) #,
std 31,-8(1) #,
std 30,-16(1) #,
addis 9,2,.LC0@toc@ha # tmp140,,
ld 9,.LC0@toc@l(9) #, tmp139
cmplwi 7,3,31 #, tmp146,
mr 31,3 # nr, nr
std 0,16(1) #,
sldi 0,3,10 # tmp141, nr,
stw 12,8(1) #,
stdu 1,-144(1) #,,
ld 9,0(9) # paca, paca
add 9,9,0 # tmp142, paca, tmp141
lha 30,48(9) # <variable>.hw_cpu_id, D.32974
mfcr 0,1 # tmp145, tmp146
rlwinm 0,0,30,1 # tmp145,
#APP
# 154 "/root/tmp/linux.git/arch/powerpc/platforms/85xx/smp.c" 1
1: tdnei 0,0 # tmp145
.section __bug_table,"a"
2: .llong 1b, .LC1 #
.short 154, 2305 #,
.org 2b+24 #
.previous
# 0 "" 2
#NO_APP
li 4,0 #,
bl .of_get_cpu_node #
nop
addis 4,2,.LC2@toc@ha # tmp148,,
li 5,0 #,
addi 4,4,.LC2@toc@l #, tmp148,
bl .of_get_property #
nop
cmpdi 0,3,0 # tmp149, D.29375
beq- 0,.L34 #
addis 9,2,.LC4@toc@ha # tmp153,,
lis 0,0x4000 # tmp155,
ld 3,0(3) #* D.29375, D.29379
ld 9,.LC4@toc@l(9) #, tmp152
sldi 0,0,32 # tmp155, tmp155,
ld 9,0(9) # high_memory, high_memory
add 9,9,0 # tmp154, high_memory, tmp155
subfc 9,3,9 # ioremappable, D.29379, tmp154
subfe 9,9,9 # ioremappable
neg 9,9 # ioremappable, ioremappable
cmpdi 4,9,0 #, tmp171, ioremappable
bne 4,.L35 #
subf 29,0,3 # spin_table, tmp155, D.29379
.L28:
#APP
# 59 "/root/tmp/linux.git/arch/powerpc/include/asm/hw_irq.h" 1
li 0,0; lbz 28,850(13); stb 0,850(13) # zero, flags,
# 0 "" 2
#NO_APP
bl .trace_hardirqs_off #
nop
mr 3,31 #, nr
addi 31,29,24 # D.32994, spin_table,
rldicl 30,30,0,32 # hw_cpu.520, D.32974
bl .smp_generic_kick_cpu #
nop
mr 3,29 #, spin_table
mr 4,31 #, D.32994
bl .flush_dcache_range #
nop
#APP
# 167 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;stw 30,20(29) #, hw_cpu.520
# 0 "" 2
#NO_APP
li 9,1 # tmp162,
addis 11,2,.LC5@toc@ha # tmp164,,
stb 9,852(13) # <variable>.io_sync, tmp162
ld 11,.LC5@toc@l(11) #, tmp163
lis 0,0x4000 # tmp165,
sldi 0,0,32 # tmp165, tmp165,
ld 11,0(11) #, tmp166
add 0,0,11 # D.29395, tmp165, tmp166
#APP
# 172 "/root/tmp/linux.git/arch/powerpc/include/asm/io.h" 1
sync;std 0,0(29) #* spin_table, D.29395
# 0 "" 2
#NO_APP
stb 9,852(13) # <variable>.io_sync, tmp162
mr 4,31 #, D.32994
mr 3,29 #, spin_table
bl .flush_dcache_range #
nop
cmpdi 7,28,0 #, tmp168, flags
bne 7,.L29 #
li 3,0 #,
bl .arch_local_irq_restore #
nop
bl .trace_hardirqs_off #
nop
bne 4,.L31 #
.L33:
li 3,0 # ret,
.L26:
addi 1,1,144 #,,
ld 0,16(1) #,
lwz 12,8(1) #,
ld 28,-32(1) #,
ld 29,-24(1) #,
mtlr 0 #,
ld 30,-16(1) #,
ld 31,-8(1) #,
mtcrf 8,12 #,
blr #
.p2align 4,,15
.L29:
bl .trace_hardirqs_on #
nop
mr 3,28 #, flags
bl .arch_local_irq_restore #
nop
beq 4,.L33 #
.L31:
mr 3,29 #, spin_table
bl .iounmap #
nop
b .L33 #
.p2align 4,,15
.L35:
li 4,24 #,
lis 5,0x20 #,
bl .ioremap_prot #
nop
mr 29,3 # spin_table,
b .L28 #
.L34:
addis 3,2,.LC3@toc@ha # tmp151,,
mr 4,31 #, nr
addi 3,3,.LC3@toc@l #, tmp151,
bl .printk #
nop
li 3,-2 # ret,
b .L26 #
.size .smp_85xx_kick_cpu,.-.smp_85xx_kick_cpu
.section ".toc","aw"
.LC7:
.tc smp_mpic_probe[TC],smp_mpic_probe
.LC8:
.tc smp_mpic_message_pass[TC],smp_mpic_message_pass
.LC9:
.tc doorbell_cause_ipi[TC],doorbell_cause_ipi
.LC11:
.tc smp_ops[TC],smp_ops
.section .init.text,"ax",@progbits
.align 2
.globl mpc85xx_smp_init
.section ".opd","aw"
.align 3
mpc85xx_smp_init:
.quad .mpc85xx_smp_init,.TOC.@tocbase
.previous
.size mpc85xx_smp_init,24
.type .mpc85xx_smp_init,@function
.globl .mpc85xx_smp_init
.mpc85xx_smp_init:
mflr 0 #,
std 31,-8(1) #,
addis 9,2,smp_85xx_setup_cpu@toc@ha # tmp125,,
addis 31,2,.LANCHOR1@toc@ha # tmp123,,
std 30,-16(1) #,
addi 30,31,.LANCHOR1@toc@l # tmp122, tmp123,
std 28,-32(1) #,
std 29,-24(1) #,
addis 4,2,.LC6@toc@ha # tmp127,,
li 3,0 #,
std 0,16(1) #,
addi 0,9,smp_85xx_setup_cpu@toc@l # tmp124, tmp125,
stdu 1,-144(1) #,,
std 0,32(30) # smp_85xx_ops.setup_cpu, tmp124
addi 4,4,.LC6@toc@l #, tmp127,
bl .of_find_node_by_type #
nop
cmpdi 7,3,0 #, tmp128,
beq 7,.L37 #
addis 11,2,.LC8@toc@ha # tmp136,,
addis 9,2,.LC7@toc@ha # tmp132,,
ld 9,.LC7@toc@l(9) #, tmp131
ld 0,.LC8@toc@l(11) #, tmp135
std 9,16(30) # smp_85xx_ops.probe, tmp131
std 0,.LANCHOR1@toc@l(31) # smp_85xx_ops.message_pass, tmp135
.L37:
addis 9,2,.LC9@toc@ha # tmp143,,
addis 30,2,.LANCHOR2@toc@ha # tmp145,,
ld 0,.LC9@toc@l(9) #, tmp142
addis 9,2,.LANCHOR1@toc@ha # tmp138,,
addi 30,30,.LANCHOR2@toc@l # tmp144, tmp145,
addi 31,9,.LANCHOR1@toc@l # tmp137, tmp138,
li 11,0 # tmp139,
std 0,8(31) # smp_85xx_ops.cause_ipi, tmp142
li 3,0 #,
mr 4,30 #, tmp144
li 5,0 #,
std 11,.LANCHOR1@toc@l(9) # smp_85xx_ops.message_pass, tmp139
bl .of_find_matching_node_and_match #
nop
mr. 29,3 # np.619,
beq 0,.L38 #
li 4,0 #,
addis 28,2,.LANCHOR0@toc@ha # tmp148,,
bl .of_iomap #
nop
addi 28,28,.LANCHOR0@toc@l # tmp147, tmp148,
std 3,16(28) # guts,
mr 3,29 #, np.619
bl .of_node_put #
nop
ld 0,16(28) # guts, guts
cmpdi 7,0,0 #, tmp152, guts
bne+ 7,.L39 #
addis 3,2,.LC10@toc@ha # tmp154,,
addi 4,30,1400 #, tmp144,
addi 3,3,.LC10@toc@l #, tmp154,
bl .printk #
nop
b .L41 #
.L39:
addis 9,2,mpc85xx_take_timebase@toc@ha # tmp165,,
addis 11,2,mpc85xx_give_timebase@toc@ha # tmp161,,
addi 0,11,mpc85xx_give_timebase@toc@l # tmp160, tmp161,
addi 9,9,mpc85xx_take_timebase@toc@l # tmp164, tmp165,
std 9,48(31) # smp_85xx_ops.take_timebase, tmp164
std 0,56(31) # smp_85xx_ops.give_timebase, tmp160
.L38:
addis 9,2,.LC11@toc@ha # tmp167,,
addis 11,2,.LANCHOR1@toc@ha # tmp169,,
ld 9,.LC11@toc@l(9) #, tmp166
addi 0,11,.LANCHOR1@toc@l # tmp168, tmp169,
std 0,0(9) # smp_ops, tmp168
.L41:
addi 1,1,144 #,,
ld 0,16(1) #,
ld 28,-32(1) #,
ld 29,-24(1) #,
ld 30,-16(1) #,
mtlr 0 #,
ld 31,-8(1) #,
blr #
.size .mpc85xx_smp_init,.-.mpc85xx_smp_init
.section ".toc","aw"
.set .LC12,.LC7
.section ".text"
.align 2
.p2align 4,,15
.section ".opd","aw"
.align 3
smp_85xx_setup_cpu:
.quad .smp_85xx_setup_cpu,.TOC.@tocbase
.previous
.size smp_85xx_setup_cpu,24
.type .smp_85xx_setup_cpu,@function
.smp_85xx_setup_cpu:
mflr 0 #,
addis 9,2,.LANCHOR1@toc@ha # tmp121,,
addi 9,9,.LANCHOR1@toc@l # tmp120, tmp121,
addis 11,2,.LC12@toc@ha # tmp123,,
std 0,16(1) #,
ld 0,.LC12@toc@l(11) #, tmp122
stdu 1,-112(1) #,,
ld 9,16(9) # smp_85xx_ops.probe, smp_85xx_ops.probe
cmpd 7,9,0 # tmp122, tmp125, smp_85xx_ops.probe
beq 7,.L45 #
bl .doorbell_setup_this_cpu #
nop
addi 1,1,112 #,,
ld 0,16(1) #,
mtlr 0 #,
blr #
.p2align 4,,15
.L45:
bl .mpic_setup_this_cpu #
nop
bl .doorbell_setup_this_cpu #
nop
addi 1,1,112 #,,
ld 0,16(1) #,
mtlr 0 #,
blr #
.size .smp_85xx_setup_cpu,.-.smp_85xx_setup_cpu
.globl smp_85xx_ops
.section .rodata
.align 3
.set .LANCHOR2,. + 0
.type mpc85xx_smp_guts_ids, @object
.size mpc85xx_smp_guts_ids, 1400
mpc85xx_smp_guts_ids:
# compatible:
.zero 64
.string "fsl,mpc8572-guts"
.zero 111
.zero 8
# compatible:
.zero 64
.string "fsl,p1020-guts"
.zero 113
.zero 8
# compatible:
.zero 64
.string "fsl,p1021-guts"
.zero 113
.zero 8
# compatible:
.zero 64
.string "fsl,p1022-guts"
.zero 113
.zero 8
# compatible:
.zero 64
.string "fsl,p1023-guts"
.zero 113
.zero 8
# compatible:
.zero 64
.string "fsl,p2020-guts"
.zero 113
.zero 8
.zero 200
.type __func__.29417, @object
.size __func__.29417, 17
__func__.29417:
.string "mpc85xx_smp_init"
.section ".data"
.align 3
.set .LANCHOR1,. + 0
.type smp_85xx_ops, @object
.size smp_85xx_ops, 88
smp_85xx_ops:
# kick_cpu:
.zero 24
.quad smp_85xx_kick_cpu
.zero 56
.section .rodata.str1.8,"aMS",@progbits,1
.align 3
.LC1:
.string "/root/tmp/linux.git/arch/powerpc/platforms/85xx/smp.c"
.zero 2
.LC2:
.string "cpu-release-addr"
.zero 7
.LC3:
.string "\0013No cpu-release-addr for cpu %d\n"
.zero 6
.LC6:
.string "open-pic"
.zero 7
.LC10:
.string "\0013%s: Could not map guts node address\n"
.section ".bss"
.align 3
.set .LANCHOR0,. + 0
.type tb_req, @object
.size tb_req, 4
tb_req:
.zero 4
.type tb_valid, @object
.size tb_valid, 4
tb_valid:
.zero 4
.type timebase, @object
.size timebase, 8
timebase:
.zero 8
.type guts, @object
.size guts, 8
guts:
.zero 8
.ident "GCC: (GNU) 4.4.6 20120305 (Red Hat 4.4.6-4)"
.section .note.GNU-stack,"",@progbits
^ permalink raw reply
* Re: Build errors on mainline kernel
From: Andreas Schwab @ 2013-08-10 7:15 UTC (permalink / raw)
To: Sukadev Bhattiprolu; +Cc: linuxppc-dev
In-Reply-To: <20130810010119.GA29407__43692.6458766267$1376096568$gmane$org@us.ibm.com>
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
> {standard input}: Assembler messages:
> {standard input}:244: Error: junk at end of line: `1'
> make[2]: *** [arch/powerpc/platforms/85xx/smp.o] Error 1
> make[1]: *** [arch/powerpc/platforms/85xx/smp.o] Error 2
> make: *** [sub-make] Error 2
Run "make arch/powerpc/platforms/85xx/smp.s" to create the assembler
file.
Andreas.
--
Andreas Schwab, schwab@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* [PATCH] powerpc/ppc64: remove __volatile__ in get_current()
From: James Yang @ 2013-08-10 4:49 UTC (permalink / raw)
To: benh, scottwood; +Cc: James Yang, linuxppc-dev
Uses of get_current() that normally get optimized away still result in
a load instruction of the current pointer in 64-bit because the inline
asm uses __volatile__. This patch removes __volatile__ so that nop-ed
uses of get_current() don't actually result in a load of the pointer.
Signed-off-by: James Yang <James.Yang@freescale.com>
---
arch/powerpc/include/asm/current.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/current.h b/arch/powerpc/include/asm/current.h
index e2c7f06..bb250c8 100644
--- a/arch/powerpc/include/asm/current.h
+++ b/arch/powerpc/include/asm/current.h
@@ -19,7 +19,7 @@ static inline struct task_struct *get_current(void)
{
struct task_struct *task;
- __asm__ __volatile__("ld %0,%1(13)"
+ __asm__ ("ld %0,%1(13)"
: "=r" (task)
: "i" (offsetof(struct paca_struct, __current)));
--
1.7.0.4
^ permalink raw reply related
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