* [RFC PATCH v4 10/12] powerpc/book3s: Queue up and process delayed MCE events.
From: Mahesh J Salgaonkar @ 2013-09-16 12:42 UTC (permalink / raw)
To: linuxppc-dev, Paul Mackerras, Benjamin Herrenschmidt
Cc: Jeremy Kerr, Anton Blanchard
In-Reply-To: <20130916123908.16111.4657.stgit@mars.in.ibm.com>
From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
When machine check real mode handler can not continue into host kernel
in V mode, it returns from the interrupt and we loose MCE event which
never gets logged. In such a situation queue up the MCE event so that
we can log it later when we get back into host kernel with r1 pointing to
kernel stack e.g. during syscall exit.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mce.h | 3 +
arch/powerpc/kernel/entry_64.S | 5 +
arch/powerpc/kernel/exceptions-64s.S | 7 +-
arch/powerpc/kernel/mce.c | 154 +++++++++++++++++++++++++++++++++
arch/powerpc/platforms/powernv/opal.c | 97 ---------------------
5 files changed, 168 insertions(+), 98 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 87cad2a..3276b40 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -190,5 +190,8 @@ extern void save_mce_event(struct pt_regs *regs, long handled,
struct mce_error_info *mce_err, uint64_t addr);
extern int get_mce_event(struct machine_check_event *mce, bool release);
extern void release_mce_event(void);
+extern void machine_check_queue_event(void);
+extern void machine_check_process_queued_event(void);
+extern void machine_check_print_event_info(struct machine_check_event *evt);
#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 2bd0b88..71bcd41 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -183,6 +183,11 @@ syscall_exit:
bl .do_show_syscall_exit
ld r3,RESULT(r1)
#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+BEGIN_FTR_SECTION
+ bl .machine_check_process_queued_event
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+#endif
CURRENT_THREAD_INFO(r12, r1)
ld r8,_MSR(r1)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 0a92ba4..ce57cec 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -824,7 +824,8 @@ BEGIN_FTR_SECTION
/* Supervisor state loss */
li r0,1
stb r0,PACA_NAPSTATELOST(r13)
-3: MACHINE_CHECK_HANDLER_WINDUP
+3: bl .machine_check_queue_event
+ MACHINE_CHECK_HANDLER_WINDUP
GET_PACA(r13)
ld r1,PACAR1(r13)
b .power7_enter_nap_mode
@@ -864,8 +865,10 @@ BEGIN_FTR_SECTION
2:
/*
* Return from MC interrupt.
- * TODO: Queue up the MCE event so that we can log it later.
+ * Queue up the MCE event so that we can log it later, while
+ * returning from kernel or opal call.
*/
+ bl .machine_check_queue_event
MACHINE_CHECK_HANDLER_WINDUP
rfid
9:
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index aeecdf1..1cca4b6 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -31,6 +31,10 @@
static DEFINE_PER_CPU(int, mce_nest_count);
static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event);
+/* Queue for delayed MCE events. */
+static DEFINE_PER_CPU(int, mce_queue_count);
+static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event_queue);
+
static void mce_set_error_info(struct machine_check_event *mce,
struct mce_error_info *mce_err)
{
@@ -162,3 +166,153 @@ void release_mce_event(void)
{
get_mce_event(NULL, true);
}
+
+/*
+ * Queue up the MCE event which then can be handled later.
+ */
+void machine_check_queue_event(void)
+{
+ int index;
+ struct machine_check_event evt;
+
+ if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
+ return;
+
+ index = __get_cpu_var(mce_queue_count)++;
+ /* If queue is full, just return for now. */
+ if (index >= MAX_MC_EVT) {
+ __get_cpu_var(mce_queue_count)--;
+ return;
+ }
+ __get_cpu_var(mce_event_queue[index]) = evt;
+}
+
+/*
+ * process pending MCE event from the mce event queue. This function will be
+ * called during syscall exit.
+ */
+void machine_check_process_queued_event(void)
+{
+ int index;
+
+ preempt_disable();
+ /*
+ * For now just print it to console.
+ * TODO: log this error event to FSP or nvram.
+ */
+ while (__get_cpu_var(mce_queue_count) > 0) {
+ index = __get_cpu_var(mce_queue_count) - 1;
+ machine_check_print_event_info(
+ &__get_cpu_var(mce_event_queue[index]));
+ __get_cpu_var(mce_queue_count)--;
+ }
+ preempt_enable();
+}
+
+void machine_check_print_event_info(struct machine_check_event *evt)
+{
+ const char *level, *sevstr, *subtype;
+ static const char *mc_ue_types[] = {
+ "Indeterminate",
+ "Instruction fetch",
+ "Page table walk ifetch",
+ "Load/Store",
+ "Page table walk Load/Store",
+ };
+ static const char *mc_slb_types[] = {
+ "Indeterminate",
+ "Parity",
+ "Multihit",
+ };
+ static const char *mc_erat_types[] = {
+ "Indeterminate",
+ "Parity",
+ "Multihit",
+ };
+ static const char *mc_tlb_types[] = {
+ "Indeterminate",
+ "Parity",
+ "Multihit",
+ };
+
+ /* Print things out */
+ if (evt->version != MCE_V1) {
+ pr_err("Machine Check Exception, Unknown event version %d !\n",
+ evt->version);
+ return;
+ }
+ switch(evt->severity) {
+ case MCE_SEV_NO_ERROR:
+ level = KERN_INFO;
+ sevstr = "Harmless";
+ break;
+ case MCE_SEV_WARNING:
+ level = KERN_WARNING;
+ sevstr = "";
+ break;
+ case MCE_SEV_ERROR_SYNC:
+ level = KERN_ERR;
+ sevstr = "Severe";
+ break;
+ case MCE_SEV_FATAL:
+ default:
+ level = KERN_ERR;
+ sevstr = "Fatal";
+ break;
+ }
+
+ printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
+ evt->disposition == MCE_DISPOSITION_RECOVERED ?
+ "Recovered" : "[Not recovered");
+ printk("%s Initiator: %s\n", level,
+ evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
+ switch(evt->error_type) {
+ case MCE_ERROR_TYPE_UE:
+ subtype = evt->u.ue_error.ue_error_type <
+ ARRAY_SIZE(mc_ue_types) ?
+ mc_ue_types[evt->u.ue_error.ue_error_type]
+ : "Unknown";
+ printk("%s Error type: UE [%s]\n", level, subtype);
+ if (evt->u.ue_error.effective_address_provided)
+ printk("%s Effective address: %016llx\n",
+ level, evt->u.ue_error.effective_address);
+ if (evt->u.ue_error.physical_address_provided)
+ printk("%s Physial address: %016llx\n",
+ level, evt->u.ue_error.physical_address);
+ break;
+ case MCE_ERROR_TYPE_SLB:
+ subtype = evt->u.slb_error.slb_error_type <
+ ARRAY_SIZE(mc_slb_types) ?
+ mc_slb_types[evt->u.slb_error.slb_error_type]
+ : "Unknown";
+ printk("%s Error type: SLB [%s]\n", level, subtype);
+ if (evt->u.slb_error.effective_address_provided)
+ printk("%s Effective address: %016llx\n",
+ level, evt->u.slb_error.effective_address);
+ break;
+ case MCE_ERROR_TYPE_ERAT:
+ subtype = evt->u.erat_error.erat_error_type <
+ ARRAY_SIZE(mc_erat_types) ?
+ mc_erat_types[evt->u.erat_error.erat_error_type]
+ : "Unknown";
+ printk("%s Error type: ERAT [%s]\n", level, subtype);
+ if (evt->u.erat_error.effective_address_provided)
+ printk("%s Effective address: %016llx\n",
+ level, evt->u.erat_error.effective_address);
+ break;
+ case MCE_ERROR_TYPE_TLB:
+ subtype = evt->u.tlb_error.tlb_error_type <
+ ARRAY_SIZE(mc_tlb_types) ?
+ mc_tlb_types[evt->u.tlb_error.tlb_error_type]
+ : "Unknown";
+ printk("%s Error type: TLB [%s]\n", level, subtype);
+ if (evt->u.tlb_error.effective_address_provided)
+ printk("%s Effective address: %016llx\n",
+ level, evt->u.tlb_error.effective_address);
+ break;
+ default:
+ case MCE_ERROR_TYPE_UNKNOWN:
+ printk("%s Error type: Unknown\n", level);
+ break;
+ }
+}
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index bcbbcdc..f789514 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -247,29 +247,6 @@ int opal_put_chars(uint32_t vtermno, const char *data, int total_len)
int opal_machine_check(struct pt_regs *regs)
{
struct machine_check_event evt;
- const char *level, *sevstr, *subtype;
- static const char *opal_mc_ue_types[] = {
- "Indeterminate",
- "Instruction fetch",
- "Page table walk ifetch",
- "Load/Store",
- "Page table walk Load/Store",
- };
- static const char *opal_mc_slb_types[] = {
- "Indeterminate",
- "Parity",
- "Multihit",
- };
- static const char *opal_mc_erat_types[] = {
- "Indeterminate",
- "Parity",
- "Multihit",
- };
- static const char *opal_mc_tlb_types[] = {
- "Indeterminate",
- "Parity",
- "Multihit",
- };
if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
return 0;
@@ -280,80 +257,8 @@ int opal_machine_check(struct pt_regs *regs)
evt.version);
return 0;
}
- switch(evt.severity) {
- case MCE_SEV_NO_ERROR:
- level = KERN_INFO;
- sevstr = "Harmless";
- break;
- case MCE_SEV_WARNING:
- level = KERN_WARNING;
- sevstr = "";
- break;
- case MCE_SEV_ERROR_SYNC:
- level = KERN_ERR;
- sevstr = "Severe";
- break;
- case MCE_SEV_FATAL:
- default:
- level = KERN_ERR;
- sevstr = "Fatal";
- break;
- }
+ machine_check_print_event_info(&evt);
- printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
- evt.disposition == MCE_DISPOSITION_RECOVERED ?
- "Recovered" : "[Not recovered");
- printk("%s Initiator: %s\n", level,
- evt.initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
- switch(evt.error_type) {
- case MCE_ERROR_TYPE_UE:
- subtype = evt.u.ue_error.ue_error_type <
- ARRAY_SIZE(opal_mc_ue_types) ?
- opal_mc_ue_types[evt.u.ue_error.ue_error_type]
- : "Unknown";
- printk("%s Error type: UE [%s]\n", level, subtype);
- if (evt.u.ue_error.effective_address_provided)
- printk("%s Effective address: %016llx\n",
- level, evt.u.ue_error.effective_address);
- if (evt.u.ue_error.physical_address_provided)
- printk("%s Physial address: %016llx\n",
- level, evt.u.ue_error.physical_address);
- break;
- case MCE_ERROR_TYPE_SLB:
- subtype = evt.u.slb_error.slb_error_type <
- ARRAY_SIZE(opal_mc_slb_types) ?
- opal_mc_slb_types[evt.u.slb_error.slb_error_type]
- : "Unknown";
- printk("%s Error type: SLB [%s]\n", level, subtype);
- if (evt.u.slb_error.effective_address_provided)
- printk("%s Effective address: %016llx\n",
- level, evt.u.slb_error.effective_address);
- break;
- case MCE_ERROR_TYPE_ERAT:
- subtype = evt.u.erat_error.erat_error_type <
- ARRAY_SIZE(opal_mc_erat_types) ?
- opal_mc_erat_types[evt.u.erat_error.erat_error_type]
- : "Unknown";
- printk("%s Error type: ERAT [%s]\n", level, subtype);
- if (evt.u.erat_error.effective_address_provided)
- printk("%s Effective address: %016llx\n",
- level, evt.u.erat_error.effective_address);
- break;
- case MCE_ERROR_TYPE_TLB:
- subtype = evt.u.tlb_error.tlb_error_type <
- ARRAY_SIZE(opal_mc_tlb_types) ?
- opal_mc_tlb_types[evt.u.tlb_error.tlb_error_type]
- : "Unknown";
- printk("%s Error type: TLB [%s]\n", level, subtype);
- if (evt.u.tlb_error.effective_address_provided)
- printk("%s Effective address: %016llx\n",
- level, evt.u.tlb_error.effective_address);
- break;
- default:
- case MCE_ERROR_TYPE_UNKNOWN:
- printk("%s Error type: Unknown\n", level);
- break;
- }
return evt.severity == MCE_SEV_FATAL ? 0 : 1;
}
^ permalink raw reply related
* [RFC PATCH v4 11/12] powerpc/powernv: Remove machine check handling in OPAL.
From: Mahesh J Salgaonkar @ 2013-09-16 12:42 UTC (permalink / raw)
To: linuxppc-dev, Paul Mackerras, Benjamin Herrenschmidt
Cc: Jeremy Kerr, Anton Blanchard
In-Reply-To: <20130916123908.16111.4657.stgit@mars.in.ibm.com>
From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Now that we are ready to handle machine check directly in linux, do not
register with firmware to handle machine check exception.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/opal.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index f789514..0170d19 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -83,14 +83,10 @@ static int __init opal_register_exception_handlers(void)
if (!(powerpc_firmware_features & FW_FEATURE_OPAL))
return -ENODEV;
- /* Hookup some exception handlers. We use the fwnmi area at 0x7000
- * to provide the glue space to OPAL
+ /* Hookup some exception handlers except machine check. We use the
+ * fwnmi area at 0x7000 to provide the glue space to OPAL
*/
glue = 0x7000;
- opal_register_exception_handler(OPAL_MACHINE_CHECK_HANDLER,
- __pa(opal_mc_secondary_handler[0]),
- glue);
- glue += 128;
opal_register_exception_handler(OPAL_HYPERVISOR_MAINTENANCE_HANDLER,
0, glue);
glue += 128;
^ permalink raw reply related
* [RFC PATCH v4 12/12] powerpc/powernv: Machine check exception handling.
From: Mahesh J Salgaonkar @ 2013-09-16 12:42 UTC (permalink / raw)
To: linuxppc-dev, Paul Mackerras, Benjamin Herrenschmidt
Cc: Jeremy Kerr, Anton Blanchard
In-Reply-To: <20130916123908.16111.4657.stgit@mars.in.ibm.com>
From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Add basic error handling in machine check exception handler.
- If MSR_RI isn't set, we can not recover.
- Check if disposition set to OpalMCE_DISPOSITION_RECOVERED.
- Check if address at fault is inside kernel address space, if not then send
SIGBUS to process if we hit exception when in userspace.
- If address at fault is not provided then and if we get a synchronous machine
check while in userspace then kill the task.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/mce.h | 1 +
arch/powerpc/kernel/mce.c | 27 +++++++++++++++++++++
arch/powerpc/platforms/powernv/opal.c | 43 ++++++++++++++++++++++++++++++++-
3 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
index 3276b40..a2b8c7b 100644
--- a/arch/powerpc/include/asm/mce.h
+++ b/arch/powerpc/include/asm/mce.h
@@ -193,5 +193,6 @@ extern void release_mce_event(void);
extern void machine_check_queue_event(void);
extern void machine_check_process_queued_event(void);
extern void machine_check_print_event_info(struct machine_check_event *evt);
+extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
#endif /* __ASM_PPC64_MCE_H__ */
diff --git a/arch/powerpc/kernel/mce.c b/arch/powerpc/kernel/mce.c
index 1cca4b6..3100509 100644
--- a/arch/powerpc/kernel/mce.c
+++ b/arch/powerpc/kernel/mce.c
@@ -316,3 +316,30 @@ void machine_check_print_event_info(struct machine_check_event *evt)
break;
}
}
+
+uint64_t get_mce_fault_addr(struct machine_check_event *evt)
+{
+ switch (evt->error_type) {
+ case MCE_ERROR_TYPE_UE:
+ if (evt->u.ue_error.effective_address_provided)
+ return evt->u.ue_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_SLB:
+ if (evt->u.slb_error.effective_address_provided)
+ return evt->u.slb_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_ERAT:
+ if (evt->u.erat_error.effective_address_provided)
+ return evt->u.erat_error.effective_address;
+ break;
+ case MCE_ERROR_TYPE_TLB:
+ if (evt->u.tlb_error.effective_address_provided)
+ return evt->u.tlb_error.effective_address;
+ break;
+ default:
+ case MCE_ERROR_TYPE_UNKNOWN:
+ break;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(get_mce_fault_addr);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 0170d19..2070970 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -17,6 +17,7 @@
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/slab.h>
+#include <linux/sched.h>
#include <asm/opal.h>
#include <asm/firmware.h>
#include <asm/mce.h>
@@ -240,6 +241,44 @@ int opal_put_chars(uint32_t vtermno, const char *data, int total_len)
return written;
}
+static int opal_recover_mce(struct pt_regs *regs,
+ struct machine_check_event *evt)
+{
+ int recovered = 0;
+ uint64_t ea = get_mce_fault_addr(evt);
+
+ if (!(regs->msr & MSR_RI)) {
+ /* If MSR_RI isn't set, we cannot recover */
+ recovered = 0;
+ } else if (evt->disposition == MCE_DISPOSITION_RECOVERED) {
+ /* Platform corrected itself */
+ recovered = 1;
+ } else if (ea && !is_kernel_addr(ea)) {
+ /*
+ * Faulting address is not in kernel text. We should be fine.
+ * We need to find which process uses this address.
+ * For now, kill the task if we have received exception when
+ * in userspace.
+ *
+ * TODO: Queue up this address for hwpoisioning later.
+ */
+ if (user_mode(regs) && !is_global_init(current)) {
+ _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+ recovered = 1;
+ } else
+ recovered = 0;
+ } else if (user_mode(regs) && !is_global_init(current) &&
+ evt->severity == MCE_SEV_ERROR_SYNC) {
+ /*
+ * If we have received a synchronous error when in userspace
+ * kill the task.
+ */
+ _exception(SIGBUS, regs, BUS_MCEERR_AR, regs->nip);
+ recovered = 1;
+ }
+ return recovered;
+}
+
int opal_machine_check(struct pt_regs *regs)
{
struct machine_check_event evt;
@@ -255,7 +294,9 @@ int opal_machine_check(struct pt_regs *regs)
}
machine_check_print_event_info(&evt);
- return evt.severity == MCE_SEV_FATAL ? 0 : 1;
+ if (opal_recover_mce(regs, &evt))
+ return 1;
+ return 0;
}
static irqreturn_t opal_interrupt(int irq, void *data)
^ permalink raw reply related
* Re: [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
From: Kumar Gala @ 2013-09-16 16:10 UTC (permalink / raw)
To: Kevin Hao; +Cc: Scott Wood, linuxppc
In-Reply-To: <20130913011128.GA1859@pek-khao-d1.corp.ad.wrs.com>
On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote:
> On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote:
>> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
Just a nit, but subject is missing 'e' in 'cornet' :)
- k
^ permalink raw reply
* Re: [PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
From: Scott Wood @ 2013-09-16 19:42 UTC (permalink / raw)
To: Zhang Haijun; +Cc: linuxppc-dev, X.Xie, Haijun Zhang
In-Reply-To: <5236BD62.8050604@freescale.com>
On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
> On 09/02/2013 06:37 PM, Haijun Zhang wrote:
> > We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
> > to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12.
> >
> > Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
> > ---
> > arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > index 5180d9d..0c0efa9 100644
> > --- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
> > @@ -130,7 +130,7 @@ usb@22000 {
> >
> > /include/ "pq3-esdhc-0.dtsi"
> > sdhc@2e000 {
> > - fsl,sdhci-auto-cmd12;
> > + sdhci,auto-cmd12;
> > interrupts = <41 0x2 0 0>;
> > };
> >
> >
>
>
> Hi, scott
>
> Could you help review this patch?
I process patches in periodic batches. There's no need for a reminder
when it's only been two weeks, as long as it's still marked "new" or
"under review" in patchwork (and you should include a patchwork link in
any such reminder e-mail). Especially for a trivial patch such as this,
no comment often means I looked at it and saw no problems and will take
it in the next batch.
Though if you want a comment, don't capitalize "powerpc" in the
subject. :-)
-Scott
^ permalink raw reply
* Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree nodes
From: Scott Wood @ 2013-09-16 20:39 UTC (permalink / raw)
To: Tang Yuantian-B29983
Cc: Wood Scott-B07421, Li Yang-Leo-R58472,
linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org
In-Reply-To: <D07C73A334FF604B95B3CBD2A545D07B15089208@039-SN2MPN1-011.039d.mgd.msft.net>
On Thu, 2013-09-12 at 21:50 -0500, Tang Yuantian-B29983 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: 2013=E5=B9=B49=E6=9C=8812=E6=97=A5 =E6=98=9F=E6=9C=9F=E5=9B=9B =
22:44
> > To: Tang Yuantian-B29983
> > Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc-
> > dev@lists.ozlabs.org; devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device tree
> > nodes
> >=20
> > On Wed, 2013-09-11 at 20:31 -0500, Tang Yuantian-B29983 wrote:
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: 2013=E5=B9=B49=E6=9C=8812=E6=97=A5 =E6=98=9F=E6=9C=9F=E5=9B=
=9B 9:10
> > > > To: Tang Yuantian-B29983
> > > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org;
> > > > devicetree@vger.kernel.org; Li Yang-Leo-R58472
> > > > Subject: Re: [PATCH v4] powerpc/mpc85xx: Update the clock device
> > > > tree nodes
> > > >
> > > > This description of "reg" is overly specific (assumes how the par=
ent
> > > > node's ranges are set up), incomplete (there's a size as well as =
the
> > > > offset), and does not apply to the clockgen node itself (you
> > > > probably shouldn't lump them together like this).
> > > >
> > > Do you mean I should explain the REG of clockgen and its child node
> > respectively?
> > >
> > > > > +- clocks : shall be the input parent clock phandle for the clo=
ck.
> > > >
> > > > Not required on the clockgen node
> > > >
> > > Required by child node of clockgen.
> >=20
> > My point is that you're lumping several different types of nodes toge=
ther
> > with one binding, when some parts of the binding are not applicable t=
o
> > the clockgen node.
> >=20
> Not several, just two types of nodes.
> One is clockgen node, the other is PLL and mux nodes.
clockgen + PLL + mux =3D 3 =3D several :-)
> The reason they lumped together is that the clockgen node is not only I=
P block
> Node but also a clock provider node
I don't understand why that merits lumping them together.
Just describe them separately.
> At first, I want to add a extra fixed-clock node and move the clock-fre=
quency of clockgen=20
> Node to it, but it is against the backward compatibility
Right.
> which I think it is not a big deal, Because nobody hasn't used it yet.
The point is it will require updating U-Boot to use it, versus existing
U-Boots which already patch up the clock-frequency in the clockgen node.
And there's nothing semantically wrong with the way it currently is.
> If I add a extra node with the clock-frequency property and don't move =
the
> clock-frequency property of clockgen, that would be redundant because b=
oth clockgen node
> and the extra node have the same clock-frequency node.
> So, I choose what I did now.
I'm not complaining about how you structured the nodes, just how you
documented them.
-Scott
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/fsl-booke: Add initial T104x_QDS board support
From: Scott Wood @ 2013-09-16 20:44 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: Wood Scott-B07421, Jain Priyanka-B32167, Aggrwal Poonam-B10812,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F874F607E1@039-SN1MPN1-006.039d.mgd.msft.net>
On Fri, 2013-09-13 at 02:35 -0500, Kushwaha Prabhakar-B32579 wrote:
>
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Thursday, September 12, 2013 5:11 AM
> > To: Kushwaha Prabhakar-B32579
> > Cc: linuxppc-dev@lists.ozlabs.org; galak@kernel.crashing.org; Jain
> > Priyanka-B32167; Aggrwal Poonam-B10812
> > Subject: Re: [PATCH 1/2] powerpc/fsl-booke: Add initial T104x_QDS board
> > support
> >
> > On Wed, 2013-09-11 at 12:28 +0530, Prabhakar Kushwaha wrote:
> > > + aliases {
> > > + /* TODO */
> > > + };
> >
> > TODO? Did you mean this patch as an RFC?
> >
>
>
> actually, this patch is not adding in dpaa related node(fman,bman etc).
> I am keeping place holder for alias of Ethernet nodes.
If you don't have any board-level aliases yet, then just don't include
the aliases node in this file.
> > Also, whitespace.
> >
>
> does whitespace is not captured in checkpatch?
Not in dts files.
> > Maybe some of this stuff could be put in a common dtsi between t1040 and
> > t1042?
> >
> > Ideally for t1042 you'd just take the entire t1040 tree as an include,
> > and add the switch
> >
>
> means, I just create T1042qds.dts and for T1040.dts include t1042dts + switch
Is it t1040 that has the switch or t1042?
-Scott
^ permalink raw reply
* Re: [PATCH v2] powerpc 8xx: Fixing issue with CONFIG_PIN_TLB
From: Scott Wood @ 2013-09-16 21:02 UTC (permalink / raw)
To: leroy christophe; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <52329CDF.9020103@c-s.fr>
On Fri, 2013-09-13 at 07:04 +0200, leroy christophe wrote:
> Le 12/09/2013 20:44, Scott Wood a =C3=A9crit :
> > On Thu, 2013-09-12 at 20:25 +0200, Christophe Leroy wrote:
> >> This is a reorganisation of the setup of the TLB at kernel startup, =
in order
> >> to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 =
of MPC866
> >> and MPC885 reference manuals.
> >>
> >> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> >>
> >> diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S linux-3.11/ar=
ch/powerpc/kernel/head_8xx.S
> >> --- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02 22:46:1=
0.000000000 +0200
> >> +++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 11:28:54.00=
0000000 +0200
> >> @@ -785,27 +785,24 @@
> >> * these mappings is mapped by page tables.
> >> */
> >> initial_mmu:
> >> - tlbia /* Invalidate all TLB entries */
> >> -/* Always pin the first 8 MB ITLB to prevent ITLB
> >> - misses while mucking around with SRR0/SRR1 in asm
> >> -*/
> >> - lis r8, MI_RSV4I@h
> >> - ori r8, r8, 0x1c00
> >> -
> >> + lis r8, MI_RESETVAL@h
> >> mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
> >> =20
> >> -#ifdef CONFIG_PIN_TLB
> >> - lis r10, (MD_RSV4I | MD_RESETVAL)@h
> >> - ori r10, r10, 0x1c00
> >> - mr r8, r10
> >> -#else
> >> lis r10, MD_RESETVAL@h
> >> -#endif
> >> #ifndef CONFIG_8xx_COPYBACK
> >> oris r10, r10, MD_WTDEF@h
> >> #endif
> >> mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
> >> =20
> >> + tlbia /* Invalidate all TLB entries */
> > Is this change to make sure we invalidate everything even if the
> > bootloader set RSV4I?
> Most probably. It is step 2 of the process defined in MPC866 and MPC885=
=20
> Reference Manuals:
>=20
> =C2=A78.10.3 Loading Locked TLB Entries:
> The process of loading a single reserved entry in the TLB is as follows=
:
To minimize code churn we should just fix actual problems, rather than
shuffle things around to conform to a suggested sequence. After all,
we're not just trying to load a single entry.
> >> + ori r8, r8, 0x1c00
> >> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
> >> +#ifdef CONFIG_PIN_TLB
> >> + ori r10, r10, 0x1c00
> >> + mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
> >> +#endif
> > Still 0x1c00?
> Yes, I kept the same entries in order to limit modifications:
> * 28 =3D First 8Mbytes page
> * 29 =3D IMMR
> * 30 =3D Second 8Mbytes page
> * 31 =3D Third 8Mbytes page
If you actually want to program them in increasing order then it looks
like you're still missing a write to CTR between the last two 8M entries
-- thus you'll overwrite the IMMR with the last 8M entry. That was the
same problem that v1 fixed -- did that change get lost accidentally?
The hardware wants to decrement; why fight it?
> >> /* Now map the lower 8 Meg into the TLBs. For this quick hack,
> >> * we can load the instruction and data TLB registers with the
> >> * same values.
> >> @@ -825,6 +822,12 @@
> >> mtspr SPRN_MI_AP, r8
> >> mtspr SPRN_MD_AP, r8
> >> =20
> >> + /* Always pin the first 8 MB ITLB to prevent ITLB
> >> + * misses while mucking around with SRR0/SRR1 in asm
> >> + */
> >> + lis r8, (MI_RSV4I | MI_RESETVAL)@h
> >> + mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
> > Entry 0 is not pinnable.
> Here we are not trying to pin entry 0.
Sorry, misread the patch.
> We are at step 8, we are setting=20
> MI_RSV4I. At the same time, we set MD_CTR to 0 which is off the pinned=20
> range, to be sure that we won't overwrite one of the pinned entries.
>
> The main difference compared to the previous implementation is that=20
> before, we were setting the RSV4I bit before loading the TLB entries.=20
> Now, as defined in the Reference Manuals, we are doing it at the end.
Have you seen any evidence that it matters?
-Scott
^ permalink raw reply
* Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Scott Wood @ 2013-09-16 21:09 UTC (permalink / raw)
To: Wang Dongsheng-B40534; +Cc: Wood Scott-B07421, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <ABB05CD9C9F68C46A5CEDC7F154392590107C5F0@039-SN2MPN1-021.039d.mgd.msft.net>
On Thu, 2013-09-12 at 21:53 -0500, Wang Dongsheng-B40534 wrote:
>
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, September 13, 2013 2:07 AM
> > To: Wang Dongsheng-B40534
> > Cc: Wood Scott-B07421; galak@kernel.crashing.org; linuxppc-
> > dev@lists.ozlabs.org
> > Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state and
> > altivec idle
> >
> > On Wed, 2013-09-11 at 22:48 -0500, Wang Dongsheng-B40534 wrote:
> > >
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: Thursday, September 12, 2013 7:04 AM
> > > > To: Wang Dongsheng-B40534
> > > > Cc: galak@kernel.crashing.org; linuxppc-dev@lists.ozlabs.org
> > > > Subject: Re: [PATCH v3 4/4] powerpc/85xx: add sysfs for pw20 state
> > > > and altivec idle
> > > >
> > > > On Wed, 2013-09-11 at 13:56 +0800, Dongsheng Wang wrote:
> > > > > From: Wang Dongsheng <dongsheng.wang@freescale.com>
> > > > >
> > > > > Add a sys interface to enable/diable pw20 state or altivec idle,
> > > > > and control the wait entry time.
> > > > >
> > > > > Enable/Disable interface:
> > > > > 0, disable. 1, enable.
> > > > > /sys/devices/system/cpu/cpuX/pw20_state
> > > > > /sys/devices/system/cpu/cpuX/altivec_idle
> > > > >
> > > > > Set wait entry bit interface:
> > > > > bit value range 0~63, 0 bit is Mintime, 63 bit is Maxtime.
> > > > > /sys/devices/system/cpu/cpuX/pw20_wait_entry_bit
> > > > > /sys/devices/system/cpu/cpuX/altivec_idle_wait_entry_bit
> > > >
> > > > I'm no fan of the way powerpc does bit numbering, but don't flip it
> > > > around here -- you'll just cause confusion.
> > > >
> > > OK. 0 bit is maxtime, 63 bit is mintime.
> > >
> > > > Better yet, this interface should take real time units rather than a
> > > > timebase bit.
> > > >
> > > I think the real time is not suitable, because timebase bit does not
> > > correspond with real time.
> >
> > It's a bit sloppy due to how the hardware works, but you could convert it
> > like you did in earlier patches. Semantically it should probably be the
> > minimum time to wait before entering the low power state.
> >
> But there has a problem, we can't convert bit to the real time when user read this sysfs.
> Like:
> echo 1000(us) > /sys/*/pw20_wait_entry_bit, after convert we get bit is 49.
> cat /sys/*/pw20_wait_entry_bit, after convert the time is 1598(us).
>
> The read out of the time is not real time. Unless we define a variable to save the real time.
It's not the end of the world if the value is different when read back.
It just gets rounded up when you write it.
> > > > Also, you disable the power saving mode if the maximum interval is
> > > > selected,
> > > It's not disable the pw20 state or altivec idle, just max-delay entry
> > time.
> >
> > No, the code checks for zero to set or clear the enabling bit (e.g.
> > PW20_WAIT).
> >
> There has pw20_state/altivec_idle sys interface to control "enable/disable",
> There is only to control wait bit. Did you mean remove "pw20_state/altivec_idle"
> sys interface, and reuse "pw20_wait_entry_bit/altivec_idle*" sys interface?
> When echo zero into "pw20_wait_entry_bit" we just to disable pw20 state, I think that is reasonable. :)
Sorry, I misread the patch and didn't realize these were separate
interfaces.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
From: Scott Wood @ 2013-09-16 21:18 UTC (permalink / raw)
To: Kushwaha Prabhakar-B32579
Cc: Wood Scott-B07421, Aggrwal Poonam-B10812, Jain Priyanka-B32167,
Sethi Varun-B16395, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <071A08F2C6A57E4E94D980ECA553F874F607C5@039-SN1MPN1-006.039d.mgd.msft.net>
On Fri, 2013-09-13 at 02:30 -0500, Kushwaha Prabhakar-B32579 wrote:
> > I also question the need to define separate t1040 compatible values for
> > all of these, if the only difference is whether the onboard switch is
> > enabled or not.
> >
>
> so should I use T104x as compatible field. and in T1040 device tree add extra node for l2 switch.
No, because we don't know if there will be (e.g) a t1043 that is
different. Just use t1040 as the canonical name.
> > Please update the clock stuff based on
> > http://patchwork.ozlabs.org/patch/274134/
> >
>
> this patch is still under discussion. May I have to wait for the final patch.
> or may I rebase on v4.
You can wait for the final patch, or you can update based on the current
state of the discussion, and be ready to update again if anything
changes.
> > > +/include/ "qoriq-dma-0.dtsi"
> > > + dma@100300 {
> > > + fsl,iommu-parent = <&pamu0>;
> > > + fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
> > > + };
> > > +
> > > +/include/ "qoriq-dma-1.dtsi"
> > > + dma@101300 {
> > > + fsl,iommu-parent = <&pamu0>;
> > > + fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
> > > + };
> >
> > These are elo3:
> > http://patchwork.ozlabs.org/patch/271238/
>
> This patch is still under discussion.
> I am not sure, I should wait for final patch or change code as per v9 version.
I think that patch is pretty well settled at this point. Just make it a
prerequisite for this patch.
-Scott
^ permalink raw reply
* Re: [PATCH][v2] powerpc/mpc85xx:Add initial device tree support of T104x
From: Scott Wood @ 2013-09-16 21:27 UTC (permalink / raw)
To: Prabhakar Kushwaha
Cc: Varun Sethi, Poonam Aggrwal, linuxppc-dev, Priyanka Jain
In-Reply-To: <1379253688-11798-1-git-send-email-prabhakar@freescale.com>
On Sun, 2013-09-15 at 19:31 +0530, Prabhakar Kushwaha wrote:
> The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
> processor cores with high-performance data path acceleration architecture
> and network peripheral interfaces required for networking & telecommunications.
>
> T1042 personality is a reduced personality of T1040 without Integrated 8-port
> Gigabit Ethernet switch.
>
> The T1040/T1042 SoC includes the following function and features:
>
> - Four e5500 cores, each with a private 256 KB L2 cache
> - 256 KB shared L3 CoreNet platform cache (CPC)
> - Interconnect CoreNet platform
> - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
> support
> - Data Path Acceleration Architecture (DPAA) incorporating acceleration
> for the following functions:
> - Packet parsing, classification, and distribution
> - Queue management for scheduling, packet sequencing, and congestion
> management
> - Cryptography Acceleration (SEC 5.0)
> - RegEx Pattern Matching Acceleration (PME 2.2)
> - IEEE Std 1588 support
> - Hardware buffer management for buffer allocation and deallocation
> - Ethernet interfaces
> - Integrated 8-port Gigabit Ethernet switch (T1040 only)
> - Four 1 Gbps Ethernet controllers
> - Two RGMII interfaces or one RGMII and one MII interfaces
> - High speed peripheral interfaces
> - Four PCI Express 2.0 controllers running at up to 5 GHz
> - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
> - Upto two QSGMII interface
> - Upto six SGMII interface supporting 1000 Mbps
> - One SGMII interface supporting upto 2500 Mbps
> - Additional peripheral interfaces
> - Two USB 2.0 controllers with integrated PHY
> - SD/eSDHC/eMMC
> - eSPI controller
> - Four I2C controllers
> - Four UARTs
> - Four GPIO controllers
> - Integrated flash controller (IFC)
> - Change this to LCD/ HDMI interface (DIU) with 12 bit dual data rate
> - TDM interface
> - Multicore programmable interrupt controller (PIC)
> - Two 8-channel DMA engines
> - Single source clocking implementation
> - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> ---
> Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
> Branch next
>
> Changes for v2: Incorporated Scott's comments
> - Update t1040si-post.dtsi
> - update clock device tree node as per
> http://patchwork.ozlabs.org/patch/274134/
> - removed DMA node, It will be added later as per
> http://patchwork.ozlabs.org/patch/271238/
> - Updated display compatible field
>
> arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 41 +++
> arch/powerpc/boot/dts/fsl/t1042si-post.dtsi | 418 +++++++++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 109 +++++++
> 3 files changed, 568 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
> create mode 100644 arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> new file mode 100644
> index 0000000..ca820f6
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
> @@ -0,0 +1,41 @@
> +/*
> + * T1040 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote products
> + * derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "t1042si-post.dtsi"
> +
> +&soc {
> + l2switch@800000 {
> + reg = <0x800000 0x400000>;
> + };
No compatible or anything else?
> +};
> diff --git a/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
> new file mode 100644
> index 0000000..6bfbcda
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/fsl/t1042si-post.dtsi
> @@ -0,0 +1,418 @@
> +/*
> + * t1042 Silicon/SoC Device Tree Source (post include)
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote products
> + * derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +&ifc {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,ifc", "simple-bus";
> + interrupts = <25 2 0 0>;
> +};
> +
> +&pci0 {
> + compatible = "fsl,t104x-pcie", "fsl,qoriq-pcie-v2.4", "fsl,qoriq-pcie";
No "t104x" as discussed in the other thread (sorry for the delayed
response on that one).
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 4>;
> + compatible = "fsl,qoriq-chassis2-core-pll";
> + clocks = <&clockgen>;
> + clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> + };
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 4>;
> + compatible = "fsl,qoriq-chassis2-core-pll";
> + clocks = <&clockgen>;
> + clock-output-names = "pll1", "pll1-div2", "pll1-div4";
> + };
As I mentioned in the clockgen thread, I think "fsl,qoriq-core-pll-2.0"
would be better and more consistent.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy in device tree
From: Scott Wood @ 2013-09-16 22:39 UTC (permalink / raw)
To: Zhao Qiang-B45475; +Cc: Liu Shengzhou-B36685, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <36B508A30383C943B69CE30E685EB89CEA34A6@039-SN2MPN1-013.039d.mgd.msft.net>
On Fri, 2013-09-13 at 03:17 +0000, Zhao Qiang-B45475 wrote:
> On Sep 13, 2013, at 12:42 AM, Kumar Gala wrote:
>
> > -----Original Message-----
> > From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > Sent: Friday, September 13, 2013 12:42 AM
> > To: Liu Shengzhou-B36685
> > Cc: Zhao Qiang-B45475; linuxppc-dev@lists.ozlabs.org
> > Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of ethernet-phy
> > in device tree
> >
> >
> > On Sep 12, 2013, at 1:54 AM, Liu Shengzhou-B36685 wrote:
> >
> > >
> > >
> > >> -----Original Message-----
> > >> From: Kumar Gala [mailto:galak@kernel.crashing.org]
> > >> Sent: Wednesday, September 11, 2013 11:13 PM
> > >> To: Zhao Qiang-B45475
> > >> Cc: linuxppc-dev@lists.ozlabs.org; Liu Shengzhou-B36685
> > >> Subject: Re: [PATCH] powerpc/p1010rdb:remove interrupts of
> > >> ethernet-phy in device tree
> > >>
> > >>
> > >> On Sep 10, 2013, at 10:49 PM, Zhao Qiang wrote:
> > >>
> > >>
> > >> NAK. The device tree should represent the HW not what drivers decide
> > >> to do with it.
> > >>
> > >> If different board revs have different interrupt signals than create
> > >> dts's to handle the 2 board revs.
> > >>
> > >> - k
> > >>
> > > You mean we need to create p1010rdb-pa.dtsi and p1010rdb-pb.dtsi
> > replacing current p1010rdb.dtsi just because of the unused phy interrupt?
> > > and phy interrupt is not present in those dts of P3/P4/P5 platforms.
> > > Actually currently many hardware are not present in dts, such as a lot
> > of i2c devices, temperature monitor, etc.
> > >
> > > -Shengzhou
> > >
> >
> > I'm saying of the board revs are different w/regards to how the PHY
> > interrupt is wired, than create two .dts one for each of the board revs.
> >
> > If the p3/p4/p5 platforms are missing the phy interrupt in the .dts than
> > its an error.
> >
> > Other devices like i2c, temp mon, etc should be added. There is a
> > difference between something not existing because people haven't gotten
> > around to it / there isn't a binding vs a using the lack of information
> > as a configuration mechanism.
> >
> > - k
> >
> >
>
> Kumar, please advice your solution, thanks.
He already did -- have separate dts files. This doesn't need to result
in massive duplication, because everything but the phy interrupt (and
any other differences there may be between revisions) can go into a
common dtsi file.
-Scott
^ permalink raw reply
* Re: [PATCH v9 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Scott Wood @ 2013-09-16 22:46 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree@vger.kernel.org, ian.campbell@citrix.com, Pawel Moll,
swarren@wwwdotorg.org, Hongbo Zhang, linux-kernel@vger.kernel.org,
rob.herring@calxeda.com, vinod.koul@intel.com, djbw@fb.com,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20130912171541.GH22013@e106331-lin.cambridge.arm.com>
On Thu, 2013-09-12 at 18:15 +0100, Mark Rutland wrote:
> On Tue, Sep 03, 2013 at 10:01:50AM +0100, Hongbo Zhang wrote:
> > On 09/02/2013 11:58 PM, Mark Rutland wrote:
> > > May some channels be unusable for some reason, or will all eight
> > > channels be wired on any given Elo3 DMA?
> > Sorry, not get your point clearly, maybe you are clear now because of my
> > previous explanations.
>
> I assume that on any El03 DMA, there won't be a case where you can't
> describe the channel at 0x80, for instance. It will always be present
> (but it might not be wired up to anything any therefore be useful)?
>
> This was related to my concerns about the status register description --
> if the channels at 0x0,0x80,0x100,0x180 weren't wired, what would get
> described in the dt? I guess that would never actually happen because
> all 8 channels must always be present in the Elo3 IP block.
If a channel is not usable for whatever reason (other than that "used
for a different fixed purpose and thus described with a different
compatible" thing that was mentioned earlier in these threads), wouldn't
it just have status = "disabled" or similar, or be absent?
-Scott
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/85xx: introduce cornet_generic machine
From: Kevin Hao @ 2013-09-16 22:51 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc
In-Reply-To: <D81C91AE-0731-4BED-BBFA-5B9ED202C9FB@kernel.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 351 bytes --]
On Mon, Sep 16, 2013 at 11:10:27AM -0500, Kumar Gala wrote:
>
> On Sep 12, 2013, at 8:11 PM, Kevin Hao wrote:
>
> > On Thu, Sep 12, 2013 at 01:44:46PM -0500, Scott Wood wrote:
> >> On Thu, 2013-09-12 at 15:13 +0800, Kevin Hao wrote:
>
> Just a nit, but subject is missing 'e' in 'cornet' :)
Will fix.
Thanks,
Kevin
>
> - k
>
[-- Attachment #2: Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* [Patch v2] powerpc/corenet64_smp_defconfig: Enable most SPI splash
From: York Sun @ 2013-09-16 23:35 UTC (permalink / raw)
To: galak; +Cc: scottwood, linuxppc-dev
Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on
P5040DS.
Signed-off-by: York Sun <yorksun@freescale.com>
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 6c8b020..1ec6f0c 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -66,6 +66,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
CONFIG_FTL=y
CONFIG_MTD_CFI=y
CONFIG_MTD_GEN_PROBE=y
--
1.7.9.5
^ permalink raw reply related
* [Patch v2 1/2] powerpc/t4240emu: Add device tree file for t4240emu
From: York Sun @ 2013-09-16 23:38 UTC (permalink / raw)
To: galak; +Cc: scottwood, linuxppc-dev
T4240EMU is an emulator target with minimum peripherals. It is based on
T4240QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
resync with t4240qds.dts
arch/powerpc/boot/dts/t4240emu.dts | 270 ++++++++++++++++++++++++++++++++++++
1 file changed, 270 insertions(+)
create mode 100644 arch/powerpc/boot/dts/t4240emu.dts
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
new file mode 100644
index 0000000..44c5a0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -0,0 +1,270 @@
+/*
+ * T4240 emulator Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl/e6500_power_isa.dtsi"
+/ {
+ compatible = "fsl,T4240";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ next-level-cache = <&L2_1>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ next-level-cache = <&L2_1>;
+ };
+
+ cpu4: PowerPC,e6500@8 {
+ device_type = "cpu";
+ reg = <8 9>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu5: PowerPC,e6500@10 {
+ device_type = "cpu";
+ reg = <10 11>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu6: PowerPC,e6500@12 {
+ device_type = "cpu";
+ reg = <12 13>;
+ next-level-cache = <&L2_2>;
+ };
+ cpu7: PowerPC,e6500@14 {
+ device_type = "cpu";
+ reg = <14 15>;
+ next-level-cache = <&L2_2>;
+ };
+
+ cpu8: PowerPC,e6500@16 {
+ device_type = "cpu";
+ reg = <16 17>;
+ next-level-cache = <&L2_3>;
+ };
+ cpu9: PowerPC,e6500@18 {
+ device_type = "cpu";
+ reg = <18 19>;
+ next-level-cache = <&L2_3>;
+ };
+ cpu10: PowerPC,e6500@20 {
+ device_type = "cpu";
+ reg = <20 21>;
+ next-level-cache = <&L2_3>;
+ };
+ cpu11: PowerPC,e6500@22 {
+ device_type = "cpu";
+ reg = <22 23>;
+ next-level-cache = <&L2_3>;
+ };
+ };
+};
+
+/ {
+ model = "fsl,T4240QDS";
+ compatible = "fsl,T4240EMU", "fsl,T4240QDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xff800000 0x00010000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ };
+
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc", "simple-bus";
+ interrupts = <25 2 0 0>;
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 29>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.7",
+ "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 23>;
+ };
+
+ ddr2: memory-controller@9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.7",
+ "fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 22>;
+ };
+
+ ddr3: memory-controller@a000 {
+ compatible = "fsl,qoriq-memory-controller-v4.7",
+ "fsl,qoriq-memory-controller";
+ reg = <0xa000 0x1000>;
+ interrupts = <16 2 1 21>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,t4240-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000
+ 0x12000 0x1000>;
+ interrupts = <16 2 1 27
+ 16 2 1 26
+ 16 2 1 25>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 31>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x6000>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 30>;
+ };
+
+/include/ "fsl/qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ fsl,liodn-bits = <12>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
+ reg = <0xe1000 0x1000>;
+ };
+
+/include/ "fsl/qoriq-dma-0.dtsi"
+/include/ "fsl/qoriq-dma-1.dtsi"
+
+/include/ "fsl/qoriq-i2c-0.dtsi"
+/include/ "fsl/qoriq-i2c-1.dtsi"
+/include/ "fsl/qoriq-duart-0.dtsi"
+/include/ "fsl/qoriq-duart-1.dtsi"
+
+ L2_1: l2-cache-controller@c20000 {
+ compatible = "fsl,t4240-l2-cache-controller";
+ reg = <0xc20000 0x40000>;
+ next-level-cache = <&cpc>;
+ };
+ L2_2: l2-cache-controller@c60000 {
+ compatible = "fsl,t4240-l2-cache-controller";
+ reg = <0xc60000 0x40000>;
+ next-level-cache = <&cpc>;
+ };
+ L2_3: l2-cache-controller@ca0000 {
+ compatible = "fsl,t4240-l2-cache-controller";
+ reg = <0xca0000 0x40000>;
+ next-level-cache = <&cpc>;
+ };
+};
+
--
1.7.9.5
^ permalink raw reply related
* [Patch v2 2/2] powerpc/b4860emu: Add device tree file for b4860emu
From: York Sun @ 2013-09-16 23:38 UTC (permalink / raw)
To: galak; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1379374687-13922-1-git-send-email-yorksun@freescale.com>
B4860EMU is a emualtor target with minimum peripherals. It is based on
B4860QDS and trimmed down most peripherals due to either not modeled or
lack of board level connections. The main purpose of this minimum dts is
to speed up booting on emulator.
Signed-off-by: York Sun <yorksun@freescale.com>
---
Change log:
v2: remote reviewed-by and tested-by lines added by gerrit
resync with b4860qds.dts
arch/powerpc/boot/dts/b4860emu.dts | 219 ++++++++++++++++++++++++++++++++++++
1 file changed, 219 insertions(+)
create mode 100644 arch/powerpc/boot/dts/b4860emu.dts
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
new file mode 100644
index 0000000..0f91230
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -0,0 +1,219 @@
+/*
+ * B4860 emulator Device Tree Source
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of
+ * this software, even if advised of the possibility of such damage.
+ */
+
+/dts-v1/;
+
+/include/ "fsl/e6500_power_isa.dtsi"
+
+/ {
+ compatible = "fsl,B4860";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ aliases {
+ ccsr = &soc;
+
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ serial3 = &serial3;
+ dma0 = &dma0;
+ dma1 = &dma1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: PowerPC,e6500@0 {
+ device_type = "cpu";
+ reg = <0 1>;
+ next-level-cache = <&L2>;
+ };
+ cpu1: PowerPC,e6500@2 {
+ device_type = "cpu";
+ reg = <2 3>;
+ next-level-cache = <&L2>;
+ };
+ cpu2: PowerPC,e6500@4 {
+ device_type = "cpu";
+ reg = <4 5>;
+ next-level-cache = <&L2>;
+ };
+ cpu3: PowerPC,e6500@6 {
+ device_type = "cpu";
+ reg = <6 7>;
+ next-level-cache = <&L2>;
+ };
+ };
+};
+
+/ {
+ model = "fsl,B4860QDS";
+ compatible = "fsl,B4860EMU", "fsl,B4860QDS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xff800000 0x00010000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+
+ };
+};
+
+&ifc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc", "simple-bus";
+ interrupts = <25 2 0 0>;
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+
+ soc-sram-error {
+ compatible = "fsl,soc-sram-error";
+ interrupts = <16 2 1 2>;
+ };
+
+ corenet-law@0 {
+ compatible = "fsl,corenet-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <32>;
+ };
+
+ ddr1: memory-controller@8000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
+ reg = <0x8000 0x1000>;
+ interrupts = <16 2 1 8>;
+ };
+
+ ddr2: memory-controller@9000 {
+ compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
+ reg = <0x9000 0x1000>;
+ interrupts = <16 2 1 9>;
+ };
+
+ cpc: l3-cache-controller@10000 {
+ compatible = "fsl,b4-l3-cache-controller", "cache";
+ reg = <0x10000 0x1000
+ 0x11000 0x1000>;
+ interrupts = <16 2 1 4>;
+ };
+
+ corenet-cf@18000 {
+ compatible = "fsl,b4-corenet-cf";
+ reg = <0x18000 0x1000>;
+ interrupts = <16 2 1 0>;
+ fsl,ccf-num-csdids = <32>;
+ fsl,ccf-num-snoopids = <32>;
+ };
+
+ iommu@20000 {
+ compatible = "fsl,pamu-v1.0", "fsl,pamu";
+ reg = <0x20000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupts = <
+ 24 2 0 0
+ 16 2 1 1>;
+ pamu0: pamu@0 {
+ reg = <0 0x1000>;
+ fsl,primary-cache-geometry = <8 1>;
+ fsl,secondary-cache-geometry = <32 2>;
+ };
+ };
+
+/include/ "fsl/qoriq-mpic.dtsi"
+
+ guts: global-utilities@e0000 {
+ compatible = "fsl,b4-device-config";
+ reg = <0xe0000 0xe00>;
+ fsl,has-rstcr;
+ fsl,liodn-bits = <12>;
+ };
+
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
+ reg = <0xe1000 0x1000>;
+ };
+
+/include/ "fsl/qoriq-dma-0.dtsi"
+ dma@100300 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
+ };
+
+/include/ "fsl/qoriq-dma-1.dtsi"
+ dma@101300 {
+ fsl,iommu-parent = <&pamu0>;
+ fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
+ };
+
+/include/ "fsl/qoriq-i2c-0.dtsi"
+/include/ "fsl/qoriq-i2c-1.dtsi"
+/include/ "fsl/qoriq-duart-0.dtsi"
+/include/ "fsl/qoriq-duart-1.dtsi"
+
+ L2: l2-cache-controller@c20000 {
+ compatible = "fsl,b4-l2-cache-controller";
+ reg = <0xc20000 0x1000>;
+ next-level-cache = <&cpc>;
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* Re: [linuxppc-release] [Patch v2] powerpc/corenet64_smp_defconfig: Enable most SPI splash
From: York Sun @ 2013-09-16 23:40 UTC (permalink / raw)
To: galak; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1379374541-13838-1-git-send-email-yorksun@freescale.com>
On 09/16/2013 04:35 PM, York Sun wrote:
> Enable CONFIG_MTD_M25P80 for corenet64_smp_defconfig. Verified on
> P5040DS.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> Change log:
> v2: remote reviewed-by and tested-by lines added by gerrit
>
Pardon my typo. I meant to type "remove", instead of "remote".
York
^ permalink raw reply
* Re: [linuxppc-release] [Patch v2 1/2] powerpc/t4240emu: Add device tree file for t4240emu
From: York Sun @ 2013-09-16 23:40 UTC (permalink / raw)
To: galak; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1379374687-13922-1-git-send-email-yorksun@freescale.com>
On 09/16/2013 04:38 PM, York Sun wrote:
> T4240EMU is an emulator target with minimum peripherals. It is based on
> T4240QDS and trimmed down most peripherals due to either not modeled or
> lack of board level connections. The main purpose of this minimum dts is
> to speed up booting on emulator.
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> Change log:
> v2: remote reviewed-by and tested-by lines added by gerrit
> resync with t4240qds.dts
>
Pardon my typo. I meant to type "remove", instead of "remote".
York
^ permalink raw reply
* Re: [PATCH 2/2][RFC][v3] pci: fsl: rework PCI driver compatible with Layerscape
From: Scott Wood @ 2013-09-17 0:05 UTC (permalink / raw)
To: Minghuan Lian; +Cc: linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1378980438-29888-2-git-send-email-Minghuan.Lian@freescale.com>
On Thu, 2013-09-12 at 18:07 +0800, Minghuan Lian wrote:
> The Freescale's Layerscape series processors will use the same PCI
> controller but change cores from PowerPC to ARM. This patch is to
> rework FSL PCI driver to support PowerPC and ARM simultaneously.
> PowerPC uses structure pci_controller to describe PCI controller,
> but arm uses structure hw_pci and pci_sys_data. They also have
> different architecture implementation and initialization flow.
> The architecture-dependent driver will bridge the gap, get the
> settings from the common driver and initialize the corresponding
> structure and call the related interface to register PCI controller.
> The common driver pci-fsl.c removes all the architecture-specific
> code and provides structure fsl_pci to store all the controller
> settings and the common functionalities that include reading/writing
> PCI configuration space, parsing dts node and getting the MEM/IO and
> bus number ranges, setting ATMU and check link status.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> ---
> Based on upstream master
> The function has been tested on MPC8315ERDB MPC8572DS P5020DS P3041DS
> and T4240QDS boards
>
> Change log:
> v3:
> 1. use 'fsl_arch' as function name prefix of all the
> architecture-specific hooks.
> 2. Move PCI compatible definitions from arch/powerpc/sysdev/fsl_pci.c
> to driver/pci/host/pci-fsl.c
>
> v2:
> 1. Use 'pci' instead of 'pcie' in new file name and file contents.
> 2. Use iowrite32be()/iowrite32() instead of out_be32/le32()
> 3. Fix ppc_md.dma_set_mask setting
> 4. Synchronizes host->first_busno and pci->first_busno.
> 5. Fix PCI IO space settings
> 6. Some small changes according to Scott's comments.
>
>
> arch/powerpc/Kconfig | 1 +
> arch/powerpc/sysdev/fsl_pci.c | 150 +++++++++-
> drivers/edac/mpc85xx_edac.c | 9 -
> drivers/pci/host/Kconfig | 4 +
> drivers/pci/host/Makefile | 1 +
> drivers/pci/host/pci-fsl.c | 656 +++++++++++++++++++++++++++---------------
> include/linux/fsl/pci.h | 69 +++++
> 7 files changed, 648 insertions(+), 242 deletions(-)
The PCI mailing list and maintainer should be included.
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 6b7530f..657d90f 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -691,6 +691,7 @@ config FSL_SOC
>
> config FSL_PCI
> bool
> + select PCI_FSL if FSL_SOC_BOOKE || PPC_86xx
> select PPC_INDIRECT_PCI
> select PCI_QUIRKS
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index a189ff0..4cb12e8 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>
> #define MAX_PHYS_ADDR_BITS 40
> -static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
> +
> +u64 fsl_arch_pci64_dma_offset(void)
> +{
> + return 1ull << MAX_PHYS_ADDR_BITS;
> +}
>
> static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
> {
> @@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
> if ((dev->bus == &pci_bus_type) &&
> dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
> set_dma_ops(dev, &dma_direct_ops);
> - set_dma_offset(dev, pci64_dma_offset);
> + set_dma_offset(dev, fsl_arch_pci64_dma_offset());
> }
Is the intent for fsl_arch_pci64_dma_offset() to eventually do something
that isn't calculable at compile time?
> *dev->dma_mask = dma_mask;
> return 0;
> }
>
> +struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
> +{
> + struct pci_controller *hose = sys;
> + struct fsl_pci *pci = hose->private_data;
If this were just to convert to fsl_pci, that seems like header
material.
> + /* Update the first bus number */
> + if (pci->first_busno != hose->first_busno)
> + pci->first_busno = hose->first_busno;
This isn't part of the interface description in the header...
> +static int mpc83xx_pcie_check_link(struct pci_controller *hose)
> +{
> + u32 val = 0;
> +
> +#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> +#define PCIE_LTSSM_L0 0x16 /* L0 state */
> +
> + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
> + if (val < PCIE_LTSSM_L0)
> + return 1;
> + return 0;
> +}
Aren't PCIE_LTSSM and PCIE_LTSSM_L0 defined in include/linux/fsl/pci.h
at this point?
> @@ -260,14 +259,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
> /* we only need the error registers */
> r.start += 0xe00;
>
> - if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
> - pdata->name)) {
> - printk(KERN_ERR "%s: Error while requesting mem region\n",
> - __func__);
> - res = -EBUSY;
> - goto err;
> - }
Why? If the relationship between the edac driver and the main pci
driver is changing, explain that.
> pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
> if (!pdata->pci_vbase) {
> printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 3d95048..37d25ae 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -19,4 +19,8 @@ config PCI_TEGRA
> bool "NVIDIA Tegra PCIe controller"
> depends on ARCH_TEGRA
>
> +config PCI_FSL
> + bool "Freescale PCI/PCIe controller"
> + depends on FSL_SOC_BOOKE || PPC_86xx
Needs help text.
Make it clear that this is for 85xx/86xx/QorIQ/Layerscape, not all
Freescale chips with PCI/PCIe.
> no_bridge:
> - iounmap(hose->private_data);
> - /* unmap cfg_data & cfg_addr separately if not on same page */
> - if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
> - ((unsigned long)hose->cfg_addr & PAGE_MASK))
> - iounmap(hose->cfg_data);
> - iounmap(hose->cfg_addr);
> - pcibios_free_controller(hose);
> - return -ENODEV;
> + dev_info(&pdev->dev, "It works as EP mode\n");
> + return -EPERM;
This is a poorly phrased message. In any case, what does this change
have to do with making the PCI driver compatible with layerscape?
-Scott
^ permalink raw reply
* Re: [PATCH v2 1/3] powerpc/booke64: add sync after writing PTE
From: Scott Wood @ 2013-09-17 0:06 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1379281131.4098.48.camel@pasglop>
On Mon, 2013-09-16 at 07:38 +1000, Benjamin Herrenschmidt wrote:
> On Fri, 2013-09-13 at 22:50 -0500, Scott Wood wrote:
> > The ISA says that a sync is needed to order a PTE write with a
> > subsequent hardware tablewalk lookup. On e6500, without this sync
> > we've been observed to die with a DSI due to a PTE write not being seen
> > by a subsequent access, even when everything happens on the same
> > CPU.
>
> This is gross, I didn't realize we had that bogosity in the
> architecture...
>
> Did you measure the performance impact ?
I didn't see a noticeable impact on the tests I ran, but those were
aimed at measuring TLB miss overhead. I'll need to try it with a
benchmark that's more oriented around lots of page table updates.
-Scott
^ permalink raw reply
* Re: [PATCH] Powerpc/dts: Correct sdhci quirk for bsc9131
From: Zhang Haijun @ 2013-09-17 0:56 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, X.Xie, Haijun Zhang
In-Reply-To: <1379360577.2536.142.camel@snotra.buserror.net>
I see, thanks. ^_^
=E4=BA=8E 2013/9/17 3:42, Scott Wood =E5=86=99=E9=81=93:
> On Mon, 2013-09-16 at 16:12 +0800, Zhang Haijun wrote:
>> On 09/02/2013 06:37 PM, Haijun Zhang wrote:
>>> We use property "sdhci,auto-cmd12" instead of "fsl,sdhci-auto-cmd12"
>>> to distinguish if the sdhc host has quirk SDHCI_QUIRK_MULTIBLOCK_READ=
_ACMD12.
>>>
>>> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
>>> ---
>>> arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/pow=
erpc/boot/dts/fsl/bsc9131si-post.dtsi
>>> index 5180d9d..0c0efa9 100644
>>> --- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
>>> +++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
>>> @@ -130,7 +130,7 @@ usb@22000 {
>>>
>>> /include/ "pq3-esdhc-0.dtsi"
>>> sdhc@2e000 {
>>> - fsl,sdhci-auto-cmd12;
>>> + sdhci,auto-cmd12;
>>> interrupts =3D <41 0x2 0 0>;
>>> };
>>>
>>>
>>
>> Hi, scott
>>
>> Could you help review this patch?
> I process patches in periodic batches. There's no need for a reminder
> when it's only been two weeks, as long as it's still marked "new" or
> "under review" in patchwork (and you should include a patchwork link in
> any such reminder e-mail). Especially for a trivial patch such as this=
,
> no comment often means I looked at it and saw no problems and will take
> it in the next batch.
>
> Though if you want a comment, don't capitalize "powerpc" in the
> subject. :-)
>
> -Scott
>
>
--=20
Thanks & Regards
Haijun.
^ permalink raw reply
* RE: [PATCH] powerpc/mpc85xx:Add initial device tree support of T104x
From: Kushwaha Prabhakar-B32579 @ 2013-09-17 2:11 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: Sethi Varun-B16395, Jain Priyanka-B32167, Aggrwal Poonam-B10812,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1379366325.2536.178.camel@snotra.buserror.net>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgU2VwdGVtYmVyIDE3LCAyMDEzIDI6NDkgQU0NCj4gVG86IEt1
c2h3YWhhIFByYWJoYWthci1CMzI1NzkNCj4gQ2M6IFdvb2QgU2NvdHQtQjA3NDIxOyBsaW51eHBw
Yy1kZXZAbGlzdHMub3psYWJzLm9yZzsNCj4gZ2FsYWtAa2VybmVsLmNyYXNoaW5nLm9yZzsgQWdn
cndhbCBQb29uYW0tQjEwODEyOyBKYWluIFByaXlhbmthLUIzMjE2NzsNCj4gU2V0aGkgVmFydW4t
QjE2Mzk1DQo+IFN1YmplY3Q6IFJlOiBbUEFUQ0hdIHBvd2VycGMvbXBjODV4eDpBZGQgaW5pdGlh
bCBkZXZpY2UgdHJlZSBzdXBwb3J0IG9mDQo+IFQxMDR4DQo+IA0KPiBPbiBGcmksIDIwMTMtMDkt
MTMgYXQgMDI6MzAgLTA1MDAsIEt1c2h3YWhhIFByYWJoYWthci1CMzI1Nzkgd3JvdGU6DQo+ID4g
PiBJIGFsc28gcXVlc3Rpb24gdGhlIG5lZWQgdG8gZGVmaW5lIHNlcGFyYXRlIHQxMDQwIGNvbXBh
dGlibGUgdmFsdWVzDQo+ID4gPiBmb3IgYWxsIG9mIHRoZXNlLCBpZiB0aGUgb25seSBkaWZmZXJl
bmNlIGlzIHdoZXRoZXIgdGhlIG9uYm9hcmQNCj4gPiA+IHN3aXRjaCBpcyBlbmFibGVkIG9yIG5v
dC4NCj4gPiA+DQo+ID4NCj4gPiBzbyBzaG91bGQgSSB1c2UgVDEwNHggYXMgY29tcGF0aWJsZSBm
aWVsZC4gYW5kIGluIFQxMDQwIGRldmljZSB0cmVlIGFkZA0KPiBleHRyYSBub2RlIGZvciBsMiBz
d2l0Y2guDQoNCkkgYW0gdXNpbmcgVDEwNDIgYXMgYmFzZSBkdHMgYW5kIFQxMDQwIGluY2x1ZGVz
IFQxMDQwICsgbDJzd2l0Y2guIA0KDQpzbyBpZiBJIHVzZSBUMTA0MiBpbiBjb21wYXRpYmxlLiBJ
dCB3aWxsIGdpdmUgd3JvbmcgZmllbGQgZm9yIHNvbWVvbmUgd29ya2luZyBvbiBUMTA0MFFEUy4N
Cg0KYmVzdCBzb2x1dGlvbiBzaG91bGQgYmUgdG8gaGF2ZSANCiBhKSBoYXZlIFQxMDQyIGluIGNv
bXBhdGlibGUgZmllbGQuDQogYikgVDEwNDAgZHRzIG92ZXJyaWRlIFQxMDQyIHRvIHQxMDQwIGlu
IGNvbXBhdGlibGUgZmllbGQuDQppdCB3aWxsIGdpdmUgY29ycmVjdCBwaWN0dXJlDQoNCg0KUmVn
YXJkcywNClByYWJoYWthcg0KDQo=
^ permalink raw reply
* RE: [PATCH v4] powerpc/mpc85xx: Update the clock device tree nodes
From: Tang Yuantian-B29983 @ 2013-09-17 7:19 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
Li Yang-Leo-R58472
In-Reply-To: <1379363970.2536.151.camel@snotra.buserror.net>
PiA+ID4gT24gV2VkLCAyMDEzLTA5LTExIGF0IDIwOjMxIC0wNTAwLCBUYW5nIFl1YW50aWFuLUIy
OTk4MyB3cm90ZToNCj4gPiA+ID4gPiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+ID4g
PiA+IEZyb206IFdvb2QgU2NvdHQtQjA3NDIxDQo+ID4gPiA+ID4gU2VudDogMjAxM+W5tDnmnIgx
MuaXpSDmmJ/mnJ/lm5sgOToxMA0KPiA+ID4gPiA+IFRvOiBUYW5nIFl1YW50aWFuLUIyOTk4Mw0K
PiA+ID4gPiA+IENjOiBnYWxha0BrZXJuZWwuY3Jhc2hpbmcub3JnOyBsaW51eHBwYy1kZXZAbGlz
dHMub3psYWJzLm9yZzsNCj4gPiA+ID4gPiBkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZzsgTGkg
WWFuZy1MZW8tUjU4NDcyDQo+ID4gPiA+ID4gU3ViamVjdDogUmU6IFtQQVRDSCB2NF0gcG93ZXJw
Yy9tcGM4NXh4OiBVcGRhdGUgdGhlIGNsb2NrIGRldmljZQ0KPiA+ID4gPiA+IHRyZWUgbm9kZXMN
Cj4gPiA+ID4gPg0KPiA+ID4gPiA+IFRoaXMgZGVzY3JpcHRpb24gb2YgInJlZyIgaXMgb3Zlcmx5
IHNwZWNpZmljIChhc3N1bWVzIGhvdyB0aGUNCj4gPiA+ID4gPiBwYXJlbnQgbm9kZSdzIHJhbmdl
cyBhcmUgc2V0IHVwKSwgaW5jb21wbGV0ZSAodGhlcmUncyBhIHNpemUgYXMNCj4gPiA+ID4gPiB3
ZWxsIGFzIHRoZSBvZmZzZXQpLCBhbmQgZG9lcyBub3QgYXBwbHkgdG8gdGhlIGNsb2NrZ2VuIG5v
ZGUNCj4gPiA+ID4gPiBpdHNlbGYgKHlvdSBwcm9iYWJseSBzaG91bGRuJ3QgbHVtcCB0aGVtIHRv
Z2V0aGVyIGxpa2UgdGhpcykuDQo+ID4gPiA+ID4NCj4gPiA+ID4gRG8geW91IG1lYW4gSSBzaG91
bGQgZXhwbGFpbiB0aGUgUkVHIG9mIGNsb2NrZ2VuIGFuZCBpdHMgY2hpbGQNCj4gPiA+ID4gbm9k
ZQ0KPiA+ID4gcmVzcGVjdGl2ZWx5Pw0KPiA+ID4gPg0KPiA+ID4gPiA+ID4gKy0gY2xvY2tzIDog
c2hhbGwgYmUgdGhlIGlucHV0IHBhcmVudCBjbG9jayBwaGFuZGxlIGZvciB0aGUNCj4gY2xvY2su
DQo+ID4gPiA+ID4NCj4gPiA+ID4gPiBOb3QgcmVxdWlyZWQgb24gdGhlIGNsb2NrZ2VuIG5vZGUN
Cj4gPiA+ID4gPg0KPiA+ID4gPiBSZXF1aXJlZCBieSBjaGlsZCBub2RlIG9mIGNsb2NrZ2VuLg0K
PiA+ID4NCj4gPiA+IE15IHBvaW50IGlzIHRoYXQgeW91J3JlIGx1bXBpbmcgc2V2ZXJhbCBkaWZm
ZXJlbnQgdHlwZXMgb2Ygbm9kZXMNCj4gPiA+IHRvZ2V0aGVyIHdpdGggb25lIGJpbmRpbmcsIHdo
ZW4gc29tZSBwYXJ0cyBvZiB0aGUgYmluZGluZyBhcmUgbm90DQo+ID4gPiBhcHBsaWNhYmxlIHRv
IHRoZSBjbG9ja2dlbiBub2RlLg0KPiA+ID4NCj4gPiBOb3Qgc2V2ZXJhbCwganVzdCB0d28gdHlw
ZXMgb2Ygbm9kZXMuDQo+ID4gT25lIGlzIGNsb2NrZ2VuIG5vZGUsIHRoZSBvdGhlciBpcyBQTEwg
YW5kIG11eCBub2Rlcy4NCj4gDQo+IGNsb2NrZ2VuICsgUExMICsgbXV4ID0gMyA9IHNldmVyYWwg
Oi0pDQo+IA0KPiA+IFRoZSByZWFzb24gdGhleSBsdW1wZWQgdG9nZXRoZXIgaXMgdGhhdCB0aGUg
Y2xvY2tnZW4gbm9kZSBpcyBub3Qgb25seQ0KPiA+IElQIGJsb2NrIE5vZGUgYnV0IGFsc28gYSBj
bG9jayBwcm92aWRlciBub2RlDQo+IA0KPiBJIGRvbid0IHVuZGVyc3RhbmQgd2h5IHRoYXQgbWVy
aXRzIGx1bXBpbmcgdGhlbSB0b2dldGhlci4NCj4gDQo+IEp1c3QgZGVzY3JpYmUgdGhlbSBzZXBh
cmF0ZWx5Lg0KPiANCkl0IGlzIG5vdCB0aGF0IGVhc3kgdG8gc2VwYXJhdGUgdGhlbSBiZWNhdXNl
IGNsb2NrZ2VuIG5vZGUgcGxheXMgdHdvIHR5cGVzDQpPZiByb2xlcy4gVGFrZSBSRUcgcHJvcGVy
dHkgYXMgZXhhbXBsZToNCkFzIElQIGJsb2NrIG5vZGUsIFJFRyBzaG91bGQgYmUgcmVnID0gPDB4
ZTEwMDAgMHgxMDAwPiwgd2hpbGUgYXMNCkNsb2NrIHByb3ZpZGVyIG5vZGUsIGl0IHNob3VsZCBi
ZSByZWcgPSA8MHhhYmMgMHg0PiBvciBubyByZWcgYXQgYWxsKGZvciBmaXhlZCBjbG9jaykuDQoN
Cj4gPiBBdCBmaXJzdCwgSSB3YW50IHRvIGFkZCBhIGV4dHJhIGZpeGVkLWNsb2NrIG5vZGUgYW5k
IG1vdmUgdGhlDQo+ID4gY2xvY2stZnJlcXVlbmN5IG9mIGNsb2NrZ2VuIE5vZGUgdG8gaXQsIGJ1
dCBpdCBpcyBhZ2FpbnN0IHRoZSBiYWNrd2FyZA0KPiA+IGNvbXBhdGliaWxpdHkNCj4gDQo+IFJp
Z2h0Lg0KPiANCj4gPiB3aGljaCBJIHRoaW5rIGl0IGlzIG5vdCBhIGJpZyBkZWFsLCBCZWNhdXNl
IG5vYm9keSBoYXNuJ3QgdXNlZCBpdCB5ZXQuDQo+IA0KPiBUaGUgcG9pbnQgaXMgaXQgd2lsbCBy
ZXF1aXJlIHVwZGF0aW5nIFUtQm9vdCB0byB1c2UgaXQsIHZlcnN1cyBleGlzdGluZw0KPiBVLUJv
b3RzIHdoaWNoIGFscmVhZHkgcGF0Y2ggdXAgdGhlIGNsb2NrLWZyZXF1ZW5jeSBpbiB0aGUgY2xv
Y2tnZW4gbm9kZS4NCj4gQW5kIHRoZXJlJ3Mgbm90aGluZyBzZW1hbnRpY2FsbHkgd3Jvbmcgd2l0
aCB0aGUgd2F5IGl0IGN1cnJlbnRseSBpcy4NCj4gDQpZZXMsIG5vdGhpbmcgd3JvbmcgYWJvdXQg
aXQuDQpCdXQgd2Ugd2lsbCBrZWVwIGFkZGluZyB0aGUgY2xvY2tnZW4teC55IG5vZGUgYWxsIHRo
ZSB0aW1lIGluIHVib290Lg0KSWYgd2UgaGF2ZSBvbmUgZXh0cmEgbm9kZSB0byBrZWVwIGNsb2Nr
LWZyZXF1ZW5jeSwgaXQgd291bGQgYmUgdXBkYXRlZCBvbmx5IG9uY2UuDQoNCj4gPiBJZiBJIGFk
ZCBhIGV4dHJhIG5vZGUgd2l0aCB0aGUgY2xvY2stZnJlcXVlbmN5IHByb3BlcnR5IGFuZCBkb24n
dCBtb3ZlDQo+ID4gdGhlIGNsb2NrLWZyZXF1ZW5jeSBwcm9wZXJ0eSBvZiBjbG9ja2dlbiwgdGhh
dCB3b3VsZCBiZSByZWR1bmRhbnQNCj4gPiBiZWNhdXNlIGJvdGggY2xvY2tnZW4gbm9kZSBhbmQg
dGhlIGV4dHJhIG5vZGUgaGF2ZSB0aGUgc2FtZSBjbG9jay0NCj4gZnJlcXVlbmN5IG5vZGUuDQo+
ID4gU28sIEkgY2hvb3NlIHdoYXQgSSBkaWQgbm93Lg0KPiANCj4gSSdtIG5vdCBjb21wbGFpbmlu
ZyBhYm91dCBob3cgeW91IHN0cnVjdHVyZWQgdGhlIG5vZGVzLCBqdXN0IGhvdyB5b3UNCj4gZG9j
dW1lbnRlZCB0aGVtLg0KPiANCkFzIEkgc2FpZCBpdCBpcyBoYXJkIHRvIGRvY3VtZW50IGNsb2Nr
Z2VuIG5vZGUgaWYgd2UgZG9uJ3Qgc2VwYXJhdGUgaXRzDQp0d28gcm9sZXMuDQpJIHRoaW5rIHRo
ZSBmb2xsb3dpbmcgc3RydWN0dXJlIGlzIGJldHRlci4NCg0KKyAgIGNsb2NrZ2VuOiBnbG9iYWwt
dXRpbGl0aWVzQGUxMDAwIHsNCisgICAgICAgY29tcGF0aWJsZSA9ICJmc2wscDUwMjAtY2xvY2tn
ZW4iLCAiZnNsLHFvcmlxLWNsb2NrZ2VuLTEuMCI7DQorICAgICAgIHJlZyA9IDwweGUxMDAwIDB4
MTAwMD47DQorICAgICAgICNhZGRyZXNzLWNlbGxzID0gPDE+Ow0KKyAgICAgICAjc2l6ZS1jZWxs
cyA9IDwxPjsNCgkgIA0KCSAgU3lzY2xrOnN5c2NsayB7DQoJICAJY29tcGF0aWJsZSA9ICJmc2ws
cW9yaXEtc3lzY2xrIiwgImZpeGVkLWNsb2NrIjsNCiAgICAgICAJY2xvY2stb3V0cHV0LW5hbWVz
ID0gInN5c2NsayI7DQogICAgICAgCSNjbG9jay1jZWxscyA9IDwwPjsgICANCgkJY2xvY2stZnJl
cXVlbmN5ID0gPDA+OwkJDQoJICB9DQorICAgICAgIHBsbDA6IHBsbDBAODAwIHsNCisgICAgICAg
ICAgICNjbG9jay1jZWxscyA9IDwxPjsNCisgICAgICAgICAgIHJlZyA9IDwweDgwMCAweDQ+Ow0K
KyAgICAgICAgICAgY29tcGF0aWJsZSA9ICJmc2wscW9yaXEtY2hhc3NpczEtY29yZS1wbGwiOw0K
KyAgICAgICAgICAgY2xvY2tzID0gPCYgU3lzY2xrID47DQorICAgICAgICAgICBjbG9jay1vdXRw
dXQtbmFtZXMgPSAicGxsMCIsICJwbGwwLWRpdjIiOw0KKyAgICAgICB9Ow0KDQpSZWdhcmRzLA0K
WXVhbnRpYW4NCg0KPiAtU2NvdHQNCj4gDQoNCg==
^ permalink raw reply
* Re: [PATCH 2/2][RFC][v3] pci: fsl: rework PCI driver compatible with Layerscape
From: Lian Minghuan-b31939 @ 2013-09-17 9:23 UTC (permalink / raw)
To: Scott Wood; +Cc: Minghuan Lian, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1379376308.2536.217.camel@snotra.buserror.net>
Hi Scott,
Thanks for your comments.
please see my replies in line.
On 09/17/2013 08:05 AM, Scott Wood wrote:
> On Thu, 2013-09-12 at 18:07 +0800, Minghuan Lian wrote:
>> The Freescale's Layerscape series processors will use the same PCI
>> controller but change cores from PowerPC to ARM. This patch is to
>> rework FSL PCI driver to support PowerPC and ARM simultaneously.
>> PowerPC uses structure pci_controller to describe PCI controller,
>> but arm uses structure hw_pci and pci_sys_data. They also have
>> different architecture implementation and initialization flow.
>> The architecture-dependent driver will bridge the gap, get the
>> settings from the common driver and initialize the corresponding
>> structure and call the related interface to register PCI controller.
>> The common driver pci-fsl.c removes all the architecture-specific
>> code and provides structure fsl_pci to store all the controller
>> settings and the common functionalities that include reading/writing
>> PCI configuration space, parsing dts node and getting the MEM/IO and
>> bus number ranges, setting ATMU and check link status.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
>> ---
>> Based on upstream master
>> The function has been tested on MPC8315ERDB MPC8572DS P5020DS P3041DS
>> and T4240QDS boards
>>
>> Change log:
>> v3:
>> 1. use 'fsl_arch' as function name prefix of all the
>> architecture-specific hooks.
>> 2. Move PCI compatible definitions from arch/powerpc/sysdev/fsl_pci.c
>> to driver/pci/host/pci-fsl.c
>>
>> v2:
>> 1. Use 'pci' instead of 'pcie' in new file name and file contents.
>> 2. Use iowrite32be()/iowrite32() instead of out_be32/le32()
>> 3. Fix ppc_md.dma_set_mask setting
>> 4. Synchronizes host->first_busno and pci->first_busno.
>> 5. Fix PCI IO space settings
>> 6. Some small changes according to Scott's comments.
>>
>>
>> arch/powerpc/Kconfig | 1 +
>> arch/powerpc/sysdev/fsl_pci.c | 150 +++++++++-
>> drivers/edac/mpc85xx_edac.c | 9 -
>> drivers/pci/host/Kconfig | 4 +
>> drivers/pci/host/Makefile | 1 +
>> drivers/pci/host/pci-fsl.c | 656 +++++++++++++++++++++++++++---------------
>> include/linux/fsl/pci.h | 69 +++++
>> 7 files changed, 648 insertions(+), 242 deletions(-)
> The PCI mailing list and maintainer should be included.
[Minghuan] Ok, I will remove 'RFC' and re-send the patch according to
you comments.
>> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
>> index 6b7530f..657d90f 100644
>> --- a/arch/powerpc/Kconfig
>> +++ b/arch/powerpc/Kconfig
>> @@ -691,6 +691,7 @@ config FSL_SOC
>>
>> config FSL_PCI
>> bool
>> + select PCI_FSL if FSL_SOC_BOOKE || PPC_86xx
>> select PPC_INDIRECT_PCI
>> select PCI_QUIRKS
>>
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
>> index a189ff0..4cb12e8 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -62,7 +62,11 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>
>> #define MAX_PHYS_ADDR_BITS 40
>> -static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
>> +
>> +u64 fsl_arch_pci64_dma_offset(void)
>> +{
>> + return 1ull << MAX_PHYS_ADDR_BITS;
>> +}
>>
>> static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
>> {
>> @@ -77,17 +81,43 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
>> if ((dev->bus == &pci_bus_type) &&
>> dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
>> set_dma_ops(dev, &dma_direct_ops);
>> - set_dma_offset(dev, pci64_dma_offset);
>> + set_dma_offset(dev, fsl_arch_pci64_dma_offset());
>> }
> Is the intent for fsl_arch_pci64_dma_offset() to eventually do something
> that isn't calculable at compile time?
>
[Minghuan] fsl_arch_pci64_dma_offset() is also called by pci-fsl.c to
setup inbound ATMU.
I think different platform or architecture(LS1) may use different dma
offset(maybe I am wrong
they can use the same offset 1ull << MAX_PHYS_ADDR_BITS). I selected
u64 fsl_arch_pci64_dma_offset(void) not extern u64 pci64_dma_offset to
share the global
value between /driver/pci/host/pci-fsl.c and
arch/powerpc/sysdev/fsl_pci.c or / arch/arm/..../fsl_pci.c
'extern' variable will cause the warning when checking patch.
>> *dev->dma_mask = dma_mask;
>> return 0;
>> }
>>
>> +struct fsl_pci *fsl_arch_sys_to_pci(void *sys)
>> +{
>> + struct pci_controller *hose = sys;
>> + struct fsl_pci *pci = hose->private_data;
> If this were just to convert to fsl_pci, that seems like header
> material.
[Minghuan] In arm architecture it will be implemented like this:
struct fsl_pci *fsl_arch_sys_to_pci(void *sys) {
struct pci_sys_data *sys_data = sys;
return sys_data->private_data;
}
driver/pci/host/pci-fsl.c should not include any arch specific header file.
and can not recognize structure pci_controller used in powerpc and
pci_sys_data used in arm.
>> + /* Update the first bus number */
>> + if (pci->first_busno != hose->first_busno)
>> + pci->first_busno = hose->first_busno;
> This isn't part of the interface description in the header...
[Minghuan] Yes. host->first_busno will be reassigned if defined
PCI_REASSIGN_ALL_BUS.
and I can not find a chance to update pci->first_busno. this will cause
we can not
read/write pci configuration space when the hose->first_busno is changed
but pci->first_busno
is not updated synchronously.
the following code to check first_busno when access the configuration space.
if (pci->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) {
if (bus != pci->first_busno)
return PCIBIOS_DEVICE_NOT_FOUND;
...
}
bus_no = (bus == pci->first_busno) ? pci->self_busno : bus;
So I added the sentences to this function to fix the issue.
>
>> +static int mpc83xx_pcie_check_link(struct pci_controller *hose)
>> +{
>> + u32 val = 0;
>> +
>> +#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
>> +#define PCIE_LTSSM_L0 0x16 /* L0 state */
>> +
>> + early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
>> + if (val < PCIE_LTSSM_L0)
>> + return 1;
>> + return 0;
>> +}
> Aren't PCIE_LTSSM and PCIE_LTSSM_L0 defined in include/linux/fsl/pci.h
> at this point?
[Minghuan] Yes. I will remove the duplicate definitions.
>> @@ -260,14 +259,6 @@ int mpc85xx_pci_err_probe(struct platform_device *op)
>> /* we only need the error registers */
>> r.start += 0xe00;
>>
>> - if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
>> - pdata->name)) {
>> - printk(KERN_ERR "%s: Error while requesting mem region\n",
>> - __func__);
>> - res = -EBUSY;
>> - goto err;
>> - }
> Why? If the relationship between the edac driver and the main pci
> driver is changing, explain that.
[Minghuan] Ok.
The main pci driver used devm_ioremap_resource() to map regester space.
So PCI EDAC driver would encounter an error when calling
devm_request_mem_region()
EDAC just only need to ioremap the error interrupt registers region and
not need
to call devm_request_mem_region().
>
>> pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
>> if (!pdata->pci_vbase) {
>> printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index 3d95048..37d25ae 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -19,4 +19,8 @@ config PCI_TEGRA
>> bool "NVIDIA Tegra PCIe controller"
>> depends on ARCH_TEGRA
>>
>> +config PCI_FSL
>> + bool "Freescale PCI/PCIe controller"
>> + depends on FSL_SOC_BOOKE || PPC_86xx
> Needs help text.
>
> Make it clear that this is for 85xx/86xx/QorIQ/Layerscape, not all
> Freescale chips with PCI/PCIe.
[Minghuan] Ok. I will add help text.
>> no_bridge:
>> - iounmap(hose->private_data);
>> - /* unmap cfg_data & cfg_addr separately if not on same page */
>> - if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
>> - ((unsigned long)hose->cfg_addr & PAGE_MASK))
>> - iounmap(hose->cfg_data);
>> - iounmap(hose->cfg_addr);
>> - pcibios_free_controller(hose);
>> - return -ENODEV;
>> + dev_info(&pdev->dev, "It works as EP mode\n");
>> + return -EPERM;
> This is a poorly phrased message. In any case, what does this change
> have to do with making the PCI driver compatible with layerscape?
[Minghuan] I can not quite understand what you mean.
Should I remove the "dev_info(&pdev->dev, "It works as EP mode\n");"
and not change ENODEV to EPERM?
we do not really need this change.
If the controller is in EP mode, we only need to return an error,
because at this time
'hose' has not been created.
> -Scott
>
>
^ permalink raw reply
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