* Re: [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support
From: Scott Wood @ 2013-09-24 23:22 UTC (permalink / raw)
To: Xie Xiaobo; +Cc: linuxppc-dev, Michael Johnston
In-Reply-To: <1380019739-8196-3-git-send-email-X.Xie@freescale.com>
On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
> + partition@80000 {
> + /* 3.5 MB for Linux Kernel Image */
> + reg = <0x00080000 0x00380000>;
> + label = "NOR Linux Kernel Image";
> + };
Is this enough?
> + partition@400000 {
> + /* 58.75MB for JFFS2 based Root file System */
> + reg = <0x00400000 0x03ac0000>;
> + label = "NOR Root File System";
> + };
Don't specify jffs2.
> + /* CS2 for Display */
> + ssd1289@2,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ssd1289";
> + reg = <0x2 0x0000 0x0002
> + 0x2 0x0002 0x0002>;
> + };
Node names should be generic. What does ssd1289 do? If this is
actually the display device, then it should be called "display@2,0".
How about a vendor prefix on that compatible? Why
#address-cells/#size-cells despite no child nodes? Where is a binding
that says what each of those two reg resources mean?
> diff --git a/arch/powerpc/boot/dts/p1025twr_32b.dts b/arch/powerpc/boot/dts/p1025twr_32b.dts
> new file mode 100644
> index 0000000..ccb173f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p1025twr_32b.dts
> @@ -0,0 +1,135 @@
> +/*
> + * P1025 TWR Device Tree Source (32-bit address map)
> + *
> + * Copyright 2013 Freescale Semiconductor Inc.
> + *
> + * Redistribution and use in source and binary forms, with or without
> + * modification, are permitted provided that the following conditions are met:
> + * * Redistributions of source code must retain the above copyright
> + * notice, this list of conditions and the following disclaimer.
> + * * Redistributions in binary form must reproduce the above copyright
> + * notice, this list of conditions and the following disclaimer in the
> + * documentation and/or other materials provided with the distribution.
> + * * Neither the name of Freescale Semiconductor nor the
> + * names of its contributors may be used to endorse or promote products
> + * derived from this software without specific prior written permission.
> + *
> + *
> + * ALTERNATIVELY, this software may be distributed under the terms of the
> + * GNU General Public License ("GPL") as published by the Free Software
> + * Foundation, either version 2 of that License or (at your option) any
> + * later version.
> + *
> + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
> + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
> + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
> + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> + */
> +
> +/include/ "fsl/p1021si-pre.dtsi"
> +/ {
> + model = "fsl,P1025";
> + compatible = "fsl,TWR-P1025";
> +
> + memory {
> + device_type = "memory";
> + };
> +
> + lbc: localbus@ffe05000 {
> + reg = <0 0xffe05000 0 0x1000>;
> +
> + /* NOR Flash and SSD1289 */
> + ranges = <0x0 0x0 0x0 0xec000000 0x04000000
> + 0x2 0x0 0x0 0xe0000000 0x00020000>;
> + };
> +
> + soc: soc@ffe00000 {
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + };
> +
> + pci0: pcie@ffe09000 {
> + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
> + reg = <0 0xffe09000 0 0x1000>;
> + pcie@0 {
> + ranges = <0x2000000 0x0 0xa0000000
> + 0x2000000 0x0 0xa0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +
> + pci1: pcie@ffe0a000 {
> + reg = <0 0xffe0a000 0 0x1000>;
> + ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
> + pcie@0 {
> + ranges = <0x2000000 0x0 0x80000000
> + 0x2000000 0x0 0x80000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +
> + qe: qe@ffe80000 {
> + ranges = <0x0 0x0 0xffe80000 0x40000>;
> + reg = <0 0xffe80000 0 0x480>;
> + brg-frequency = <0>;
> + bus-frequency = <0>;
> + status = "disabled"; /* no firmware loaded */
> +
> + enet3: ucc@2000 {
> + device_type = "network";
> + compatible = "ucc_geth";
> + rx-clock-name = "clk12";
> + tx-clock-name = "clk9";
> + pio-handle = <&pio1>;
> + phy-handle = <&qe_phy0>;
> + phy-connection-type = "mii";
> + };
> +
> + mdio@2120 {
> + qe_phy0: ethernet-phy@18 {
> + interrupt-parent = <&mpic>;
> + interrupts = <4 1 0 0>;
> + reg = <0x18>;
> + device_type = "ethernet-phy";
> + };
> + qe_phy1: ethernet-phy@19 {
> + interrupt-parent = <&mpic>;
> + interrupts = <5 1 0 0>;
> + reg = <0x19>;
> + device_type = "ethernet-phy";
> + };
> + tbi-phy@11 {
> + reg = <0x11>;
> + device_type = "tbi-phy";
> + };
> + };
> +
> + enet4: ucc@2400 {
> + device_type = "network";
> + compatible = "ucc_geth";
> + rx-clock-name = "none";
> + tx-clock-name = "clk13";
> + pio-handle = <&pio2>;
> + phy-handle = <&qe_phy1>;
> + phy-connection-type = "rmii";
> + };
> + };
> +};
Don't duplicate all this just for 32/36 bit. Use a dtsi for (e.g.) the
contents of the QE node.
Is there a strong need to support both 32 and 36 bit in the first place?
> +/* ************************************************************************
> + *
> + * Setup the architecture
> + *
> + */
> +static void __init twr_p1025_setup_arch(void)
> +{
> +#ifdef CONFIG_QUICC_ENGINE
> + struct device_node *np;
> +#endif
> +
> + if (ppc_md.progress)
> + ppc_md.progress("twr_p1025_setup_arch()", 0);
> +
> + mpc85xx_smp_init();
> +
> + fsl_pci_assign_primary();
> +
> +#ifdef CONFIG_QUICC_ENGINE
> + mpc85xx_qe_init();
> +
> +#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
> + if (machine_is(twr_p1025)) {
> + struct ccsr_guts __iomem *guts;
> +
> + np = of_find_node_by_name(NULL, "global-utilities");
Look for it by compatible.
> + if (np) {
> + guts = of_iomap(np, 0);
> + if (!guts)
> + pr_err("twr_p1025: could not map"
> + "global utilities register\n");
Don't linewrap printed string constants (this is an exception to the
80-column rule).
> + else {
> + /* P1025 has pins muxed for QE and other functions. To
> + * enable QE UEC mode, we need to set bit QE0 for UCC1
> + * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
> + * and QE12 for QE MII management signals in PMUXCR
> + * register.
> + */
> +
> + printk(KERN_INFO "P1025 pinmux configured for QE\n");
Bad indentation, and use pr_info() (or better, just remove it; it's
implied by the absence of the error on the other branch of the if).
> +
> + /* Set QE mux bits in PMUXCR */
> + setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
> + MPC85xx_PMUXCR_QE(3) |
> + MPC85xx_PMUXCR_QE(9) |
> + MPC85xx_PMUXCR_QE(12));
> + iounmap(guts);
> +
> +#if defined(CONFIG_SERIAL_QE)
> + /* On P1025TWR board, the UCC7 acted as UART port.
> + * However, The UCC7's CTS pin is low level in default,
> + * it will impact the transmission in full duplex
> + * communication. So disable the Flow control pin PA18.
> + * The UCC7 UART just can use RXD and TXD pins.
> + */
> + par_io_config_pin(0, 18, 0, 0, 0, 0);
> +#endif
Any reason not to do this unconditionally?
-Scott
^ permalink raw reply
* Re: [PATCH V4 1/3] powerpc/85xx: Add QE common init functions
From: Scott Wood @ 2013-09-24 23:13 UTC (permalink / raw)
To: Xie Xiaobo; +Cc: linuxppc-dev
In-Reply-To: <1380019739-8196-1-git-send-email-X.Xie@freescale.com>
On Tue, 2013-09-24 at 18:48 +0800, Xie Xiaobo wrote:
> Define two QE init functions in common file, and avoid
> the same codes being duplicated in board files.
>
> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
> ---
> V4 -> V3: Nochange
>
> arch/powerpc/platforms/85xx/common.c | 51 +++++++++++++++++++++++++++++++++++
> arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++++++
> 2 files changed, 59 insertions(+)
>
> diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
> index d0861a0..08fff48 100644
> --- a/arch/powerpc/platforms/85xx/common.c
> +++ b/arch/powerpc/platforms/85xx/common.c
> @@ -7,6 +7,9 @@
> */
> #include <linux/of_platform.h>
>
> +#include <asm/machdep.h>
> +#include <asm/qe.h>
> +#include <asm/qe_ic.h>
> #include <sysdev/cpm2_pic.h>
>
> #include "mpc85xx.h"
> @@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
> irq_set_chained_handler(irq, cpm2_cascade);
> }
> #endif
> +
> +#ifdef CONFIG_QUICC_ENGINE
> +void __init mpc85xx_qe_pic_init(void)
> +{
> + struct device_node *np;
> +
> + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
> + if (np) {
> + if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
> + qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
> + else
> + qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
> + qe_ic_cascade_high_mpic);
> + of_node_put(np);
> + } else
> + pr_err("%s: Could not find qe-ic node\n", __func__);
> +}
Have the caller pass in a flag indicating the type of cascade. Or,
perhaps this function isn't worth factoring out. Where is the check for
p1021_mds? Where did 8568/9 MDS come from? I don't see those checks
removed in patch 2.
BTW, when you move code from one place to another, do it in one patch.
Don't add it in one patch and then remove it in another. A more useful
split would have been one patch handling qe_init and another handling
qe_pic_init.
-Scott
^ permalink raw reply
* Re: [PATCH v3 3/3] powerpc/85xx: use one kernel option for all the CoreNet_Generic boards
From: Scott Wood @ 2013-09-24 22:41 UTC (permalink / raw)
To: Kevin Hao; +Cc: linuxppc
In-Reply-To: <1379991797-29222-4-git-send-email-haokexin@gmail.com>
On Tue, 2013-09-24 at 11:03 +0800, Kevin Hao wrote:
> Currently all these boards use the same machine struct and also select
> the same kernel options, so it seems a bit of redundant to keep one
> separate kernel option for each board. Also update the defconfigs
> according to this change.
>
> Signed-off-by: Kevin Hao <haokexin@gmail.com>
> ---
> A new patch in v3.
>
> arch/powerpc/configs/corenet32_smp_defconfig | 6 +-
> arch/powerpc/configs/corenet64_smp_defconfig | 5 +-
> arch/powerpc/configs/ppc64e_defconfig | 2 +-
> arch/powerpc/platforms/85xx/Kconfig | 97 +++-------------------------
> 4 files changed, 12 insertions(+), 98 deletions(-)
>
> diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
> index 3dfab4c..1d9cb29 100644
> --- a/arch/powerpc/configs/corenet32_smp_defconfig
> +++ b/arch/powerpc/configs/corenet32_smp_defconfig
> @@ -23,11 +23,7 @@ CONFIG_MODVERSIONS=y
> # CONFIG_BLK_DEV_BSG is not set
> CONFIG_PARTITION_ADVANCED=y
> CONFIG_MAC_PARTITION=y
> -CONFIG_P2041_RDB=y
> -CONFIG_P3041_DS=y
> -CONFIG_P4080_DS=y
> -CONFIG_P5020_DS=y
> -CONFIG_P5040_DS=y
> +CONFIG_CORENET_GENERIC=y
> CONFIG_HIGHMEM=y
> # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> CONFIG_BINFMT_MISC=m
> diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
> index fa94fb3..63508dd 100644
> --- a/arch/powerpc/configs/corenet64_smp_defconfig
> +++ b/arch/powerpc/configs/corenet64_smp_defconfig
> @@ -21,10 +21,7 @@ CONFIG_MODVERSIONS=y
> # CONFIG_BLK_DEV_BSG is not set
> CONFIG_PARTITION_ADVANCED=y
> CONFIG_MAC_PARTITION=y
> -CONFIG_B4_QDS=y
> -CONFIG_P5020_DS=y
> -CONFIG_P5040_DS=y
> -CONFIG_T4240_QDS=y
> +CONFIG_CORENET_GENERIC=y
> # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
> CONFIG_BINFMT_MISC=m
> CONFIG_MATH_EMULATION=y
> diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
> index 0085dc4..0a6be6d 100644
> --- a/arch/powerpc/configs/ppc64e_defconfig
> +++ b/arch/powerpc/configs/ppc64e_defconfig
> @@ -23,7 +23,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
> CONFIG_PARTITION_ADVANCED=y
> CONFIG_MAC_PARTITION=y
> CONFIG_EFI_PARTITION=y
> -CONFIG_P5020_DS=y
> +CONFIG_CORENET_GENERIC=y
> CONFIG_CPU_FREQ=y
> CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> CONFIG_CPU_FREQ_GOV_USERSPACE=y
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index 3bee943..04456fb 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -218,36 +218,8 @@ config GE_IMP3A
> This board is a 3U CompactPCI Single Board Computer with a Freescale
> P2020 processor.
>
> -config P2041_RDB
> - bool "Freescale P2041 RDB"
> - select DEFAULT_UIMAGE
> - select PPC_E500MC
> - select PHYS_64BIT
> - select SWIOTLB
> - select ARCH_REQUIRE_GPIOLIB
> - select GPIO_MPC8XXX
> - select HAS_RAPIDIO
> - select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> - help
> - This option enables support for the P2041 RDB board
> -
> -config P3041_DS
> - bool "Freescale P3041 DS"
> - select DEFAULT_UIMAGE
> - select PPC_E500MC
> - select PHYS_64BIT
> - select SWIOTLB
> - select ARCH_REQUIRE_GPIOLIB
> - select GPIO_MPC8XXX
> - select HAS_RAPIDIO
> - select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> - help
> - This option enables support for the P3041 DS board
> -
> -config P4080_DS
> - bool "Freescale P4080 DS"
> +config CORENET_GENERIC
> + bool "Freescale CoreNet Generic"
> select DEFAULT_UIMAGE
> select PPC_E500MC
> select PHYS_64BIT
> @@ -256,50 +228,20 @@ config P4080_DS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> help
> - This option enables support for the P4080 DS board
> + This option enables support for the P2041 RDB, P3041 DS, P4080 DS, P5020 DS
> + and P5040 DS boards
>
> config SGY_CTS1000
> tristate "Servergy CTS-1000 support"
> select GPIOLIB
> select OF_GPIO
> - depends on P4080_DS
> + depends on CORENET_GENERIC
> help
> Enable this to support functionality in Servergy's CTS-1000 systems.
>
> endif # PPC32
>
> -config P5020_DS
> - bool "Freescale P5020 DS"
> - select DEFAULT_UIMAGE
> - select E500
> - select PPC_E500MC
> - select PHYS_64BIT
> - select SWIOTLB
> - select ARCH_REQUIRE_GPIOLIB
> - select GPIO_MPC8XXX
> - select HAS_RAPIDIO
> - select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> - help
> - This option enables support for the P5020 DS board
> -
> -config P5040_DS
> - bool "Freescale P5040 DS"
> - select DEFAULT_UIMAGE
> - select E500
> - select PPC_E500MC
> - select PHYS_64BIT
> - select SWIOTLB
> - select ARCH_REQUIRE_GPIOLIB
> - select GPIO_MPC8XXX
> - select HAS_RAPIDIO
> - select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> - help
> - This option enables support for the P5040 DS board
> -
> config PPC_QEMU_E500
> bool "QEMU generic e500 platform"
> select DEFAULT_UIMAGE
> @@ -317,8 +259,8 @@ config PPC_QEMU_E500
>
> if PPC64
>
> -config T4240_QDS
> - bool "Freescale T4240 QDS"
> +config CORENET_GENERIC
> + bool "Freescale CoreNet Generic"
> select DEFAULT_UIMAGE
> select E500
> select PPC_E500MC
> @@ -328,33 +270,12 @@ config T4240_QDS
> select GPIO_MPC8XXX
> select HAS_RAPIDIO
> select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> help
> - This option enables support for the T4240 QDS board
> -
> -config B4_QDS
> - bool "Freescale B4 QDS"
> - select DEFAULT_UIMAGE
> - select E500
> - select PPC_E500MC
> - select PHYS_64BIT
> - select SWIOTLB
> - select GPIOLIB
> - select ARCH_REQUIRE_GPIOLIB
> - select HAS_RAPIDIO
> - select PPC_EPAPR_HV_PIC
> - select CORENET_GENERIC
> - help
> - This option enables support for the B4 QDS board
> - The B4 application development system B4 QDS is a complete
> - debugging environment intended for engineers developing
> - applications for the B4.
> + This option enables support for the P5020 DS, P5040 DS, T4240 QDS
> + and B4 QDS boards
Is there any difference between the 32-bit and 64-bit versions of this
config symbol, other than the help text?
-Scott
^ permalink raw reply
* Re: [PATCH 8/8][v4] powerpc/perf: Export Power7 memory hierarchy info to user space.
From: Sukadev Bhattiprolu @ 2013-09-24 22:30 UTC (permalink / raw)
To: Anshuman Khandual
Cc: linuxppc-dev, Michael Ellerman, Paul Mackerras, linux-kernel,
Stephane Eranian
In-Reply-To: <523AB8B2.1060202@linux.vnet.ibm.com>
Anshuman Khandual [khandual@linux.vnet.ibm.com] wrote:
| On 09/14/2013 06:19 AM, Sukadev Bhattiprolu wrote:
| > +static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
| > + struct pt_regs *regs)
| > +{
| > + u64 idx;
| > + u64 mmcra = regs->dsisr;
| > + u64 addr;
| > + int ret;
| > + unsigned int instr;
| > +
| > + if (mmcra & POWER7_MMCRA_DCACHE_MISS) {
| > + idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK;
| > + idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT;
| > +
| > + dsrc->val |= dcache_src_map[idx];
| > + return;
| > + }
| > +
| > + instr = 0;
| > + addr = perf_instruction_pointer(regs);
| > +
| > + if (is_kernel_addr(addr))
| > + instr = *(unsigned int *)addr;
| > + else {
| > + pagefault_disable();
| > + ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
| > + pagefault_enable();
| > + if (ret)
| > + instr = 0;
| > + }
| > + if (instr && instr_is_load_store(&instr))
|
|
| Wondering if there is any possibility of getting positive values for
| "(mmcra & POWER7_MMCRA_DCACHE_SRC_MASK) >> POWER7_MMCRA_DCACHE_SRC_SHIFT"
| when the marked instruction did not have MMCRA[POWER7_MMCRA_DCACHE_MISS]
| bit set. In that case we should actually compute dsrc->val as in the previous
| case. I did couple of experiments on a P7 box, but was not able to find a
| instance for a marked instruction whose MMCRA[POWER7_MMCRA_DCACHE_MISS] bit
| not set and have a positive value POWER7_MMCRA_DCACHE_SRC field.
Confirmed again with the hardware team that if there was no DCACHE_MISS,
the DCACHE_SRC field will be clear.
Thanks,
Sukadev
^ permalink raw reply
* Re: mm: insure topdown mmap chooses addresses above security minimum
From: Russell King - ARM Linux @ 2013-09-24 21:28 UTC (permalink / raw)
To: Timothy Pepper
Cc: linux-mips, Paul Mundt, linux-sh, x86, Ralf Baechle, linux-mm,
Ingo Molnar, Paul Mackerras, H. Peter Anvin, sparclinux,
Thomas Gleixner, linuxppc-dev, David S. Miller, linux-arm-kernel
In-Reply-To: <1380057811-5352-1-git-send-email-timothy.c.pepper@linux.intel.com>
On Tue, Sep 24, 2013 at 02:23:31PM -0700, Timothy Pepper wrote:
> diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
> index 0c63562..0e7355d 100644
> --- a/arch/arm/mm/mmap.c
> +++ b/arch/arm/mm/mmap.c
> @@ -9,6 +9,7 @@
> #include <linux/io.h>
> #include <linux/personality.h>
> #include <linux/random.h>
> +#include <linux/security.h>
> #include <asm/cachetype.h>
>
> #define COLOUR_ALIGN(addr,pgoff) \
> @@ -146,7 +147,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
>
> info.flags = VM_UNMAPPED_AREA_TOPDOWN;
> info.length = len;
> - info.low_limit = PAGE_SIZE;
> + info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
> info.high_limit = mm->mmap_base;
> info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
> info.align_offset = pgoff << PAGE_SHIFT;
This looks sane for ARM.
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Thanks.
^ permalink raw reply
* mm: insure topdown mmap chooses addresses above security minimum
From: Timothy Pepper @ 2013-09-24 21:23 UTC (permalink / raw)
Cc: linux-mips, Russell King, Paul Mundt, linux-sh, x86, Ralf Baechle,
linux-mm, Ingo Molnar, Paul Mackerras, Tim Pepper, H. Peter Anvin,
sparclinux, Thomas Gleixner, linuxppc-dev, David S. Miller,
linux-arm-kernel
A security check is performed on mmap addresses in
security/security.c:security_mmap_addr(). It uses mmap_min_addr to insure
mmaps don't get addresses lower than a user configurable guard value
(/proc/sys/vm/mmap_min_addr). The arch specific mmap topdown searches
look for a map candidate address all the way down to a low_limit that is
currently hard coded as PAGE_SIZE. Depending on compile time options
and userspace setting the procfs tunable, the security check's view of
the minimum allowable address may be something greater than PAGE_SIZE.
This leaves a gap where get_unmapped_area()'s call to get_area() might
return an address above PAGE_SIZE, but below mmap_min_addr, and thus
get_unmapped_area() fails.
This was seen on x86_64 in the case of a topdown address space and a large
stack rlimit, with mmap_min_addr having been set to 32k by the distro.
This left a 28k gap where the get area search intends to place a small
mmap, but then get_unmapped_area() stumbles at the security check.
What should have happened is the address search wraps back to a higher
address, the search continues and perhaps succeeds. Indeed an mmap of
a larger size gets a topdown search that does wrap around back up into
the rlimit stack reserve and succeeds assuming suitable free space.
But a small mmap fits in the low gap and always fails. It becomes
possible to make large mmaps but not small ones.
When an explicit address hint is given, mm/mmap.c's round_hint_to_min()
will round up to mmap_min_addr.
A topdown search's low_limit should similarly consider mmap_min_addr
instead of just PAGE_SIZE.
Signed-off-by: Tim Pepper <timothy.c.pepper@linux.intel.com>
Cc: linux-mm@kvack.org
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: linux-sh@vger.kernel.org
Cc: "David S. Miller" <davem@davemloft.net>
Cc: sparclinux@vger.kernel.org
--
arch/arm/mm/mmap.c | 3 ++-
arch/mips/mm/mmap.c | 3 ++-
arch/powerpc/mm/slice.c | 3 ++-
arch/sh/mm/mmap.c | 3 ++-
arch/sparc/kernel/sys_sparc_64.c | 3 ++-
arch/x86/kernel/sys_x86_64.c | 3 ++-
6 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 0c63562..0e7355d 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/personality.h>
#include <linux/random.h>
+#include <linux/security.h>
#include <asm/cachetype.h>
#define COLOUR_ALIGN(addr,pgoff) \
@@ -146,7 +147,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm->mmap_base;
info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
index f1baadd..8c0deb7 100644
--- a/arch/mips/mm/mmap.c
+++ b/arch/mips/mm/mmap.c
@@ -14,6 +14,7 @@
#include <linux/personality.h>
#include <linux/random.h>
#include <linux/sched.h>
+#include <linux/security.h>
unsigned long shm_align_mask = PAGE_SIZE - 1; /* Sane caches */
EXPORT_SYMBOL(shm_align_mask);
@@ -102,7 +103,7 @@ static unsigned long arch_get_unmapped_area_common(struct file *filp,
if (dir == DOWN) {
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm->mmap_base;
addr = vm_unmapped_area(&info);
diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
index 3e99c14..34fc601 100644
--- a/arch/powerpc/mm/slice.c
+++ b/arch/powerpc/mm/slice.c
@@ -30,6 +30,7 @@
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/export.h>
+#include <linux/security.h>
#include <asm/mman.h>
#include <asm/mmu.h>
#include <asm/spu.h>
@@ -338,7 +339,7 @@ static unsigned long slice_find_area_topdown(struct mm_struct *mm,
addr = prev;
goto prev_slice;
}
- info.low_limit = addr;
+ info.low_limit = max(addr, PAGE_ALIGN(mmap_min_addr));
found = vm_unmapped_area(&info);
if (!(found & ~PAGE_MASK))
diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c
index 6777177..1e0c53d 100644
--- a/arch/sh/mm/mmap.c
+++ b/arch/sh/mm/mmap.c
@@ -11,6 +11,7 @@
#include <linux/mm.h>
#include <linux/mman.h>
#include <linux/module.h>
+#include <linux/security.h>
#include <asm/page.h>
#include <asm/processor.h>
@@ -119,7 +120,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm->mmap_base;
info.align_mask = do_colour_align ? (PAGE_MASK & shm_align_mask) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 51561b8..dab0a5d 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -24,6 +24,7 @@
#include <linux/personality.h>
#include <linux/random.h>
#include <linux/export.h>
+#include <linux/security.h>
#include <asm/uaccess.h>
#include <asm/utrap.h>
@@ -188,7 +189,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm->mmap_base;
info.align_mask = do_color_align ? (PAGE_MASK & (SHMLBA - 1)) : 0;
info.align_offset = pgoff << PAGE_SHIFT;
diff --git a/arch/x86/kernel/sys_x86_64.c b/arch/x86/kernel/sys_x86_64.c
index 30277e2..93e563e 100644
--- a/arch/x86/kernel/sys_x86_64.c
+++ b/arch/x86/kernel/sys_x86_64.c
@@ -15,6 +15,7 @@
#include <linux/random.h>
#include <linux/uaccess.h>
#include <linux/elf.h>
+#include <linux/security.h>
#include <asm/ia32.h>
#include <asm/syscalls.h>
@@ -172,7 +173,7 @@ arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
info.flags = VM_UNMAPPED_AREA_TOPDOWN;
info.length = len;
- info.low_limit = PAGE_SIZE;
+ info.low_limit = max(PAGE_SIZE, PAGE_ALIGN(mmap_min_addr));
info.high_limit = mm->mmap_base;
info.align_mask = filp ? get_align_mask() : 0;
info.align_offset = pgoff << PAGE_SHIFT;
^ permalink raw reply related
* Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property
From: Scott Wood @ 2013-09-24 19:37 UTC (permalink / raw)
To: Hu Mingkai-B21284; +Cc: Wood Scott-B07421, linuxppc-dev@ozlabs.org
In-Reply-To: <CF6CBFBA8EBBB949B6E321556F6E15090A1517D2@039-SN2MPN1-012.039d.mgd.msft.net>
On Tue, 2013-09-24 at 05:27 -0500, Hu Mingkai-B21284 wrote:
>
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Tuesday, September 24, 2013 7:03 AM
> > To: Hu Mingkai-B21284
> > Cc: Wood Scott-B07421; linuxppc-dev@ozlabs.org
> > Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions
> > property
> >
> > On Tue, 2013-09-17 at 06:06 -0500, Hu Mingkai-B21284 wrote:
> > > Scott,
> > > Sorry for the delayed response.
> > > Please fine my comments.
> > > Thanks,
> > > Mingkai
> > >
> > > > -----Original Message-----
> > > > From: Wood Scott-B07421
> > > > Sent: Thursday, September 12, 2013 9:16 AM
> > > > To: Hu Mingkai-B21284
> > > > Cc: Wood Scott-B07421; linuxppc-dev@ozlabs.org
> > > > Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI
> > > > partitions property
> > > >
> > > > On Tue, 2013-09-10 at 21:07 -0500, Hu Mingkai-B21284 wrote:
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Wood Scott-B07421
> > > > > > Sent: Wednesday, September 11, 2013 7:33 AM
> > > > > > To: Hu Mingkai-B21284
> > > > > > Cc: linuxppc-dev@ozlabs.org
> > > > > > Subject: Re: [PATCH] powerpc/85xx: DTS - re-organize the SPI
> > > > > > partitions property
> > > > > >
> > > > > > What happens to exsting users whose flash is laid out the
> > > > > > existing way, when they upgrade to these device trees?
> > > > > >
> > > > >
> > > > > The SPI flash layout should be mapping the new device tree.
> > > > >
> > > > > If the existing device tree is used to deploy the SPI flash, the
> > > > > following issues must be run into as the commit message described:
> > > > >
> > > > > 1. Kernel images would be overlapped with U-Boot image.
> > > > > 2. Kernel images would be overlapped with FMAN ucode.
> > > > > 3. Saving environment variables will crash the kernel image.
> > > >
> > > > Has the SPI U-Boot image always been larger than 512K for all these
> > > > platforms? Why, given that we're under 512K for other boot modes?
> > > >
> > >
> > > For DPAA platform, the ld script used to link the u-boot image is
> > > "./arch/powerpc/cpu/mpc85xx/u-boot.lds" which will generate the 512K
> > > u-boot Image. This image will be split into 64bytes and appended PBL
> > > command for Each 64bytes pieces, so the size of final image must be
> > greater than 512K.
> >
> > What is the entry point in SRAM when you load from PBL? If it is (or can
> > be made to be) the beginning of the image rather than the end, then turn
> > off the resetvec and the fixed image size that results.
> >
>
> 1. Thus a special ld script need to be provided.
This is already supported. See CONFIG_SYS_MPC85XX_NO_RESETVEC.
> 2. Now the spi image size is about 540KB, that's to say the PBL needs about ~30K
> for PBL commands. It's hard to save such a big space even we turn off the
> resetvec.
Turning off the resetvec doesn't just eliminate the resetvec code; it
eliminates the padding to 512K (or if it doesn't, that's a bug to be
fixed).
> > > > > > We really should not be putting partition layout info in the
> > > > > > device tree to begin with...
> > > > > >
> > > > > OK, I will remove the layout diagram in the commit message.
> > > >
> > > > That's not what I meant. I meant that the dts should be describing
> > > > hardware, and this is the sort of trouble we run into when we
> > > > deviate from that. A better way would be to use the mtdparts command
> > line option.
> > > > Even better would be some sort of on-flash partition table.
> > > >
> > >
> > > You're right, but maybe some customer has already used the device tree
> > partition table...
> >
> > My main point was to encourage us to shift away from this rather than to
> > rip it out right this instant.
> >
>
> Yes, that's the correct way we should go.
> Would you please pick up this patch first to resolve current issue we faced?
> And we can consider to use the mtdparts or on-flash partition table for long term.
Fixing U-Boot would make the problem go away without any issues with
partition compatibility. Are you sure nobody's using these SPI
partitions without booting from SPI? Even if nobody's using this, it
seems a wasteful solution. These are pretty small flashes.
-Scott
^ permalink raw reply
* Re: [PATCH v10 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Stephen Warren @ 2013-09-24 17:31 UTC (permalink / raw)
To: Hongbo Zhang
Cc: mark.rutland, devicetree, ian.campbell, pawel.moll, vinod.koul,
linux-kernel, rob.herring, djbw, linuxppc-dev
In-Reply-To: <524169E3.7030408@freescale.com>
On 09/24/2013 04:30 AM, Hongbo Zhang wrote:
> On 09/24/2013 01:04 AM, Stephen Warren wrote:
>> On 09/18/2013 04:15 AM, hongbo.zhang@freescale.com wrote:
>>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>>
>>> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
>>> patch adds
>>> the device tree nodes for them.
>>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
>>> b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
>>> +Required properties:
>>> +
>>> +- compatible : must include "fsl,elo3-dma"
>>> +- reg : DMA General Status Registers, i.e. DGSR0 which
>>> contains
>>> + status for channel 1~4, and DGSR1 for channel 5~8
>> Is that a single entry, which is large enough to cover both registers,
>> or a pair of entries, one per register? Reading the text, I might assume
>> the former, but looking at the examples, it's the latter.
> My impression is that I cannot tell it is one larger entry or two
> entries by reading the description text, but the example gives the answer.
> Is it so important to specify it is only one entry or entries list?
> I prefer language as concise as possible, especially for the common
> properties such as reg and interrupt (eg the reg is implicitly offset
> and length of registers, can be continuous or not), it is difficult or
> unnecessary or impossible to describe much details, the example can also
> work as a complementary description, otherwise no need to put an example
> in the binding document.
The description of the properties should fully describe them. The
example is just an example, not a specification of the properties.
^ permalink raw reply
* Re: [PATCH] powerpc/83xx: gianfar_ptp: select 1588 clock source through dts file
From: Richard Cochran @ 2013-09-24 17:14 UTC (permalink / raw)
To: Aida Mynzhasova; +Cc: devicetree, linuxppc-dev, netdev
In-Reply-To: <1380008397-22980-1-git-send-email-aida.mynzhasova@skitlab.ru>
On Tue, Sep 24, 2013 at 11:39:57AM +0400, Aida Mynzhasova wrote:
> Currently IEEE 1588 timer reference clock source is determined through
> hard-coded value in gianfar_ptp driver. This patch allows to select ptp
> clock source by means of device tree file node.
>
> For instance:
>
> fsl,cksel = <0>;
>
> for using external (TSEC_TMR_CLK input) high precision timer
> reference clock.
>
> Other acceptable values:
>
> <1> : eTSEC system clock
> <2> : eTSEC1 transmit clock
> <3> : RTC clock input
I think it would be useful to have this table in the binding document
as well.
Thanks,
Richard
^ permalink raw reply
* Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
From: Kumar Gala @ 2013-09-24 15:48 UTC (permalink / raw)
To: Bhushan Bharat-R65777
Cc: Wood Scott-B07421, Wang Dongsheng-B40534,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0717DD00@039-SN2MPN1-011.039d.mgd.msft.net>
On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote:
>=20
>=20
>> -----Original Message-----
>> From: Linuxppc-dev [mailto:linuxppc-dev-
>> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of =
Dongsheng
>> Wang
>> Sent: Tuesday, September 24, 2013 2:58 PM
>> To: Wood Scott-B07421
>> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
>> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 =
define
>>=20
>> From: Wang Dongsheng <dongsheng.wang@freescale.com>
>>=20
>> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec =
idle
>> patches.
>>=20
>> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
>> ---
>> *v3:
>> Add bit definitions for PWRMGTCR0.
>>=20
>> arch/powerpc/include/asm/reg.h | 2 ++
>> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
>> 2 files changed, 11 insertions(+)
>>=20
>> diff --git a/arch/powerpc/include/asm/reg.h =
b/arch/powerpc/include/asm/reg.h
>> index 64264bf..d4160ca 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -1053,6 +1053,8 @@
>> #define PVR_8560 0x80200000
>> #define PVR_VER_E500V1 0x8020
>> #define PVR_VER_E500V2 0x8021
>> +#define PVR_VER_E6500 0x8040
>> +
>> /*
>> * For the 8xx processors, all of them report the same PVR family for
>> * the PowerPC core. The various versions of these processors must be =
diff --
>> git a/arch/powerpc/include/asm/reg_booke.h
>> b/arch/powerpc/include/asm/reg_booke.h
>> index ed8f836..4a6457e 100644
>> --- a/arch/powerpc/include/asm/reg_booke.h
>> +++ b/arch/powerpc/include/asm/reg_booke.h
>> @@ -170,6 +170,7 @@
>> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status =
Register 1
>> */
>> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
>> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability =
Register */
>> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control =
register 0 */
>=20
> Is this generic for booke or e6500 specific? I can't see this register =
either in ISA and EREF.
> Also I can see SPRN_ICCR also with same SPRN, how that is possible?
Its possibly because the register maybe in implementation specific =
region. I'm guessing ICCR is a 40x specific register.
- k
^ permalink raw reply
* [PATCH] powerpc: BPF JIT compiler for 64bit LE
From: Philippe Bergheaud @ 2013-09-24 12:13 UTC (permalink / raw)
To: Linuxppc-dev; +Cc: Philippe Bergheaud
This enables the Berkeley Packet Filter JIT compiler
for the PowerPC running in 64bit Little Endian.
Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 1 +
arch/powerpc/net/bpf_jit.h | 10 ++++++++++
arch/powerpc/net/bpf_jit_64.S | 9 ++++++++-
arch/powerpc/net/bpf_jit_comp.c | 17 ++---------------
4 files changed, 21 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 247fa1d..23c2b63 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -154,6 +154,7 @@
/* Misc instructions for BPF compiler */
#define PPC_INST_LD 0xe8000000
#define PPC_INST_LHZ 0xa0000000
+#define PPC_INST_LHBRX 0x7c00062c
#define PPC_INST_LWZ 0x80000000
#define PPC_INST_STD 0xf8000000
#define PPC_INST_STDU 0xf8000001
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 8a5dfaf..0baf2b8 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -92,6 +92,8 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
___PPC_RA(base) | IMM_L(i))
#define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \
___PPC_RA(base) | IMM_L(i))
+#define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \
+ ___PPC_RA(base) | ___PPC_RB(b))
/* Convenience helpers for the above with 'far' offsets: */
#define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \
else { PPC_ADDIS(r, base, IMM_HA(i)); \
@@ -186,6 +188,14 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \
} } while (0);
+#define PPC_LHBRX_OFFS(r, base, i) \
+ do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0)
+#ifdef __LITTLE_ENDIAN__
+#define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
+#else
+#define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
+#endif
+
static inline bool is_nearbranch(int offset)
{
return (offset < 32768) && (offset >= -32768);
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index 7d3a3b5..e76eba7 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -43,8 +43,11 @@ sk_load_word_positive_offset:
cmpd r_scratch1, r_addr
blt bpf_slow_path_word
/* Nope, just hitting the header. cr0 here is eq or gt! */
+#ifdef __LITTLE_ENDIAN__
+ lwbrx r_A, r_D, r_addr
+#else
lwzx r_A, r_D, r_addr
- /* When big endian we don't need to byteswap. */
+#endif
blr /* Return success, cr0 != LT */
.globl sk_load_half
@@ -56,7 +59,11 @@ sk_load_half_positive_offset:
subi r_scratch1, r_HL, 2
cmpd r_scratch1, r_addr
blt bpf_slow_path_half
+#ifdef __LITTLE_ENDIAN__
+ lhbrx r_A, r_D, r_addr
+#else
lhzx r_A, r_D, r_addr
+#endif
blr
.globl sk_load_byte
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index c427ae3..9e212f9 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -17,14 +17,8 @@
#include "bpf_jit.h"
-#ifndef __BIG_ENDIAN
-/* There are endianness assumptions herein. */
-#error "Little-endian PPC not supported in BPF compiler"
-#endif
-
int bpf_jit_enable __read_mostly;
-
static inline void bpf_flush_icache(void *start, void *end)
{
smp_wmb();
@@ -346,18 +340,11 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
break;
/*** Ancillary info loads ***/
-
- /* None of the BPF_S_ANC* codes appear to be passed by
- * sk_chk_filter(). The interpreter and the x86 BPF
- * compiler implement them so we do too -- they may be
- * planted in future.
- */
case BPF_S_ANC_PROTOCOL: /* A = ntohs(skb->protocol); */
BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
protocol) != 2);
- PPC_LHZ_OFFS(r_A, r_skb, offsetof(struct sk_buff,
- protocol));
- /* ntohs is a NOP with BE loads. */
+ PPC_NTOHS_OFFS(r_A, r_skb, offsetof(struct sk_buff,
+ protocol));
break;
case BPF_S_ANC_IFINDEX:
PPC_LD_OFFS(r_scratch1, r_skb, offsetof(struct sk_buff,
--
1.7.10.4
^ permalink raw reply related
* RE: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
From: Bhushan Bharat-R65777 @ 2013-09-24 11:21 UTC (permalink / raw)
To: Wang Dongsheng-B40534, Wood Scott-B07421
Cc: Wang Dongsheng-B40534, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1380014871-22937-1-git-send-email-dongsheng.wang@freescale.com>
> -----Original Message-----
> From: Linuxppc-dev [mailto:linuxppc-dev-
> bounces+bharat.bhushan=3Dfreescale.com@lists.ozlabs.org] On Behalf Of Don=
gsheng
> Wang
> Sent: Tuesday, September 24, 2013 2:58 PM
> To: Wood Scott-B07421
> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534
> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 def=
ine
>=20
> From: Wang Dongsheng <dongsheng.wang@freescale.com>
>=20
> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec idle
> patches.
>=20
> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> ---
> *v3:
> Add bit definitions for PWRMGTCR0.
>=20
> arch/powerpc/include/asm/reg.h | 2 ++
> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
> 2 files changed, 11 insertions(+)
>=20
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/re=
g.h
> index 64264bf..d4160ca 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -1053,6 +1053,8 @@
> #define PVR_8560 0x80200000
> #define PVR_VER_E500V1 0x8020
> #define PVR_VER_E500V2 0x8021
> +#define PVR_VER_E6500 0x8040
> +
> /*
> * For the 8xx processors, all of them report the same PVR family for
> * the PowerPC core. The various versions of these processors must be di=
ff --
> git a/arch/powerpc/include/asm/reg_booke.h
> b/arch/powerpc/include/asm/reg_booke.h
> index ed8f836..4a6457e 100644
> --- a/arch/powerpc/include/asm/reg_booke.h
> +++ b/arch/powerpc/include/asm/reg_booke.h
> @@ -170,6 +170,7 @@
> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1
> */
> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
Is this generic for booke or e6500 specific? I can't see this register eith=
er in ISA and EREF.
Also I can see SPRN_ICCR also with same SPRN, how that is possible?
-Bharat
> #define SPRN_SVR 0x3FF /* System Version Register */
>=20
> /*
> @@ -216,6 +217,14 @@
> #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity
> checking */
> #define CCR1_TCS 0x00000080 /* Timer Clock Select */
>=20
> +/* Bit definitions for PWRMGTCR0. */
> +#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
> +#define PWRMGTCR0_PW20_ENT_SHIFT 8
> +#define PWRMGTCR0_PW20_ENT 0x3F00
> +#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
> +#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
> +#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
> +
> /* Bit definitions for the MCSR. */
> #define MCSR_MCS 0x80000000 /* Machine Check Summary */
> #define MCSR_IB 0x40000000 /* Instruction PLB Error */
> --
> 1.8.0
>=20
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH V4 3/3] powerpc/85xx: Add TWR-P1025 board support
From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw)
To: linuxppc-dev, scottwood; +Cc: Michael Johnston, Xie Xiaobo
In-Reply-To: <1380019739-8196-1-git-send-email-X.Xie@freescale.com>
TWR-P1025 Overview
-----------------
512Mbyte DDR3 (on board DDR)
64MB Nor Flash
eTSEC1: Connected to RGMII PHY AR8035
eTSEC3: Connected to RGMII PHY AR8035
Two USB2.0 Type A
One microSD Card slot
One mini-PCIe slot
One mini-USB TypeB dual UART
Signed-off-by: Michael Johnston <michael.johnston@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
---
Patch V4: Fix the mdio phy interrupt issue in dts
Patch V3: fix pcie range issue in dts
Patch V2: QE related init codes were factored out to a common file
arch/powerpc/boot/dts/p1025twr.dtsi | 244 ++++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/p1025twr_32b.dts | 135 ++++++++++++++++++
arch/powerpc/platforms/85xx/Kconfig | 6 +
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/twr_p102x.c | 142 +++++++++++++++++++
5 files changed, 528 insertions(+)
create mode 100644 arch/powerpc/boot/dts/p1025twr.dtsi
create mode 100644 arch/powerpc/boot/dts/p1025twr_32b.dts
create mode 100644 arch/powerpc/platforms/85xx/twr_p102x.c
diff --git a/arch/powerpc/boot/dts/p1025twr.dtsi b/arch/powerpc/boot/dts/p1025twr.dtsi
new file mode 100644
index 0000000..4b1d5f7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr.dtsi
@@ -0,0 +1,244 @@
+/*
+ * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/{
+ aliases {
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ };
+};
+
+&lbc {
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = <0x0 0x00040000>;
+ label = "NOR Vitesse-7385 Firmware";
+ read-only;
+ };
+
+ partition@40000 {
+ /* 256KB for DTB Image */
+ reg = <0x00040000 0x00040000>;
+ label = "NOR DTB Image";
+ };
+
+ partition@80000 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = <0x00080000 0x00380000>;
+ label = "NOR Linux Kernel Image";
+ };
+
+ partition@400000 {
+ /* 58.75MB for JFFS2 based Root file System */
+ reg = <0x00400000 0x03ac0000>;
+ label = "NOR Root File System";
+ };
+
+ partition@ec0000 {
+ /* This location must not be altered */
+ /* 256KB for QE ucode firmware*/
+ reg = <0x03ec0000 0x00040000>;
+ label = "NOR QE microcode firmware";
+ read-only;
+ };
+
+ partition@f00000 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = <0x03f00000 0x00100000>;
+ label = "NOR U-Boot Image";
+ read-only;
+ };
+ };
+
+ /* CS2 for Display */
+ ssd1289@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ssd1289";
+ reg = <0x2 0x0000 0x0002
+ 0x2 0x0002 0x0002>;
+ };
+
+};
+
+&soc {
+ usb@22000 {
+ phy_type = "ulpi";
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <1 1 0 0>;
+ reg = <0x2>;
+ };
+
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <2 1 0 0>;
+ reg = <0x1>;
+ };
+
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@25000 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26000 {
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
+
+ };
+
+ enet1: ethernet@b1000 {
+ status = "disabled";
+ };
+
+ enet2: ethernet@b2000 {
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ par_io@e0100 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xe0100 0x60>;
+ ranges = <0x0 0xe0100 0x60>;
+ device_type = "par_io";
+ num-ports = <3>;
+ pio1: ucc_pin@01 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
+ 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
+ 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
+ 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
+ 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
+ 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
+ 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
+ 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
+ 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
+ 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
+ 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
+ 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
+ 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
+ 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
+ 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
+ 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
+ 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
+ };
+
+ pio2: ucc_pin@02 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
+ 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
+ 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
+ 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
+ 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
+ 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
+ 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
+ 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
+ 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
+ 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
+ };
+
+ pio3: ucc_pin@03 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
+ 0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
+ 0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
+ 0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
+ 0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
+ };
+
+ pio4: ucc_pin@04 {
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
+ 0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
+ 0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
+ 0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
+ 0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
+ };
+ };
+};
+
+&qe {
+ serial2: ucc@2600 {
+ device_type = "serial";
+ compatible = "ucc_uart";
+ port-number = <0>;
+ rx-clock-name = "brg6";
+ tx-clock-name = "brg6";
+ pio-handle = <&pio3>;
+ };
+
+ serial3: ucc@2200 {
+ device_type = "serial";
+ compatible = "ucc_uart";
+ port-number = <1>;
+ rx-clock-name = "brg2";
+ tx-clock-name = "brg2";
+ pio-handle = <&pio4>;
+ };
+};
diff --git a/arch/powerpc/boot/dts/p1025twr_32b.dts b/arch/powerpc/boot/dts/p1025twr_32b.dts
new file mode 100644
index 0000000..ccb173f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025twr_32b.dts
@@ -0,0 +1,135 @@
+/*
+ * P1025 TWR Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1021si-pre.dtsi"
+/ {
+ model = "fsl,P1025";
+ compatible = "fsl,TWR-P1025";
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+
+ /* NOR Flash and SSD1289 */
+ ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+ 0x2 0x0 0x0 0xe0000000 0x00020000>;
+ };
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ reg = <0 0xffe09000 0 0x1000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ qe: qe@ffe80000 {
+ ranges = <0x0 0x0 0xffe80000 0x40000>;
+ reg = <0 0xffe80000 0 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <0>;
+ status = "disabled"; /* no firmware loaded */
+
+ enet3: ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ rx-clock-name = "clk12";
+ tx-clock-name = "clk9";
+ pio-handle = <&pio1>;
+ phy-handle = <&qe_phy0>;
+ phy-connection-type = "mii";
+ };
+
+ mdio@2120 {
+ qe_phy0: ethernet-phy@18 {
+ interrupt-parent = <&mpic>;
+ interrupts = <4 1 0 0>;
+ reg = <0x18>;
+ device_type = "ethernet-phy";
+ };
+ qe_phy1: ethernet-phy@19 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1 0 0>;
+ reg = <0x19>;
+ device_type = "ethernet-phy";
+ };
+ tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet4: ucc@2400 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ rx-clock-name = "none";
+ tx-clock-name = "clk13";
+ pio-handle = <&pio2>;
+ phy-handle = <&qe_phy1>;
+ phy-connection-type = "rmii";
+ };
+ };
+};
+
+/include/ "p1025twr.dtsi"
+/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index de2eb93..b1a7d0a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -123,6 +123,12 @@ config P1023_RDS
help
This option enables support for the P1023 RDS and RDB boards
+config TWR_P102x
+ bool "Freescale TWR-P102x"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the TWR-P1025 board.
+
config SOCRATES
bool "Socrates"
select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 53c9f75..228c4dd 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
obj-$(CONFIG_P1023_RDS) += p1023_rds.o
+obj-$(CONFIG_TWR_P102x) += twr_p102x.o
obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
new file mode 100644
index 0000000..8ba3b25
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Michael Johnston <michael.johnston@freescale.com>
+ *
+ * Description:
+ * TWR-P102x Board Setup
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/pci.h>
+#include <linux/of_platform.h>
+
+#include <asm/pci-bridge.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/fsl_guts.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+static void __init twr_p1025_pic_init(void)
+{
+ struct mpic *mpic;
+
+ mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ mpc85xx_qe_pic_init();
+#endif
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init twr_p1025_setup_arch(void)
+{
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("twr_p1025_setup_arch()", 0);
+
+ mpc85xx_smp_init();
+
+ fsl_pci_assign_primary();
+
+#ifdef CONFIG_QUICC_ENGINE
+ mpc85xx_qe_init();
+
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ if (machine_is(twr_p1025)) {
+ struct ccsr_guts __iomem *guts;
+
+ np = of_find_node_by_name(NULL, "global-utilities");
+ if (np) {
+ guts = of_iomap(np, 0);
+ if (!guts)
+ pr_err("twr_p1025: could not map"
+ "global utilities register\n");
+ else {
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management signals in PMUXCR
+ * register.
+ */
+
+ printk(KERN_INFO "P1025 pinmux configured for QE\n");
+
+ /* Set QE mux bits in PMUXCR */
+ setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ MPC85xx_PMUXCR_QE(3) |
+ MPC85xx_PMUXCR_QE(9) |
+ MPC85xx_PMUXCR_QE(12));
+ iounmap(guts);
+
+#if defined(CONFIG_SERIAL_QE)
+ /* On P1025TWR board, the UCC7 acted as UART port.
+ * However, The UCC7's CTS pin is low level in default,
+ * it will impact the transmission in full duplex
+ * communication. So disable the Flow control pin PA18.
+ * The UCC7 UART just can use RXD and TXD pins.
+ */
+ par_io_config_pin(0, 18, 0, 0, 0, 0);
+#endif
+ /* Drive PB29 to CPLD low - CPLD will then change
+ * muxing from LBC to QE */
+ par_io_config_pin(1, 29, 1, 0, 0, 0);
+ par_io_data_set(1, 29, 0);
+ }
+ of_node_put(np);
+ }
+ }
+#endif
+#endif /* CONFIG_QUICC_ENGINE */
+
+ printk(KERN_INFO "TWR-P1025 board from Freescale Semiconductor\n");
+}
+
+machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
+
+static int __init twr_p1025_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "fsl,TWR-P1025");
+}
+
+define_machine(twr_p1025) {
+ .name = "TWR-P1025",
+ .probe = twr_p1025_probe,
+ .setup_arch = twr_p1025_setup_arch,
+ .init_IRQ = twr_p1025_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.8.0
^ permalink raw reply related
* [PATCH V4 2/3] powerpc/85xx: Use common init functions for QE
From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw)
To: linuxppc-dev, scottwood; +Cc: Xie Xiaobo
In-Reply-To: <1380019739-8196-1-git-send-email-X.Xie@freescale.com>
Use common init functions instead of the duplicated codes
in some platforms with QUICC Engine.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
---
V4: new patch
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 55 ++-----------------------------
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 36 ++------------------
2 files changed, 4 insertions(+), 87 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index a7b3621..da28d74 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -238,32 +238,7 @@ static void __init mpc85xx_mds_qe_init(void)
{
struct device_node *np;
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!np) {
- np = of_find_node_by_name(NULL, "qe");
- if (!np)
- return;
- }
-
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- qe_reset();
- of_node_put(np);
-
- np = of_find_node_by_name(NULL, "par_io");
- if (np) {
- struct device_node *ucc;
-
- par_io_init(np);
- of_node_put(np);
-
- for_each_node_by_name(ucc, "ucc")
- par_io_of_config(ucc);
- }
-
+ mpc85xx_qe_init();
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
@@ -293,34 +268,8 @@ static void __init mpc85xx_mds_qe_init(void)
}
}
-
-static void __init mpc85xx_mds_qeic_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
-}
#else
static void __init mpc85xx_mds_qe_init(void) { }
-static void __init mpc85xx_mds_qeic_init(void) { }
#endif /* CONFIG_QUICC_ENGINE */
static void __init mpc85xx_mds_setup_arch(void)
@@ -395,7 +344,7 @@ static void __init mpc85xx_mds_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
- mpc85xx_mds_qeic_init();
+ mpc85xx_qe_pic_init();
}
static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 53b6fb0..67d78e2 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -49,10 +49,6 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -69,16 +65,8 @@ void __init mpc85xx_rdb_pic_init(void)
mpic_init(mpic);
#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
+ mpc85xx_qe_pic_init();
#endif
-
}
/*
@@ -98,26 +86,8 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!np) {
- pr_err("%s: Could not find Quicc Engine node\n", __func__);
- goto qe_fail;
- }
+ mpc85xx_qe_init();
- qe_reset();
- of_node_put(np);
-
- np = of_find_node_by_name(NULL, "par_io");
- if (np) {
- struct device_node *ucc;
-
- par_io_init(np);
- of_node_put(np);
-
- for_each_node_by_name(ucc, "ucc")
- par_io_of_config(ucc);
-
- }
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
@@ -148,8 +118,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
}
#endif
-
-qe_fail:
#endif /* CONFIG_QUICC_ENGINE */
printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
--
1.8.0
^ permalink raw reply related
* [PATCH V4 1/3] powerpc/85xx: Add QE common init functions
From: Xie Xiaobo @ 2013-09-24 10:48 UTC (permalink / raw)
To: linuxppc-dev, scottwood; +Cc: Xie Xiaobo
Define two QE init functions in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
---
V4 -> V3: Nochange
arch/powerpc/platforms/85xx/common.c | 51 +++++++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx.h | 8 ++++++
2 files changed, 59 insertions(+)
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index d0861a0..08fff48 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -7,6 +7,9 @@
*/
#include <linux/of_platform.h>
+#include <asm/machdep.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
#include <sysdev/cpm2_pic.h>
#include "mpc85xx.h"
@@ -80,3 +83,51 @@ void __init mpc85xx_cpm2_pic_init(void)
irq_set_chained_handler(irq, cpm2_cascade);
}
#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+void __init mpc85xx_qe_pic_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (np) {
+ if (machine_is(mpc8568_mds) || machine_is(mpc8569_mds))
+ qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
+ else
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+ } else
+ pr_err("%s: Could not find qe-ic node\n", __func__);
+}
+
+void __init mpc85xx_qe_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!np) {
+ np = of_find_node_by_name(NULL, "qe");
+ if (!np) {
+ pr_err("%s: Could not find Quicc Engine node\n",
+ __func__);
+ return;
+ }
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, "par_io");
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, "ucc")
+ par_io_of_config(ucc);
+
+ }
+}
+#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index 2aa7c5d..1d39095 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -8,4 +8,12 @@ extern void mpc85xx_cpm2_pic_init(void);
static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */
+#ifdef CONFIG_QUICC_ENGINE
+extern void mpc85xx_qe_pic_init(void);
+extern void mpc85xx_qe_init(void);
+#else
+static inline void __init mpc85xx_qe_pic_init(void) {}
+static inline void __init mpc85xx_qe_init(void) {}
+#endif
+
#endif
--
1.8.0
^ permalink raw reply related
* [PATCH] dts/c293pcie: Add range field for IFC NAND
From: Prabhakar Kushwaha @ 2013-09-24 10:50 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Prabhakar Kushwaha
C290PCIe has NAND flash present on IFC Chip Select(CS) 1.
So Add "ranges" field for NAND flash on CS1.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Based upon git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
branch next
arch/powerpc/boot/dts/c293pcie.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
index 1238bda..6681cc2 100644
--- a/arch/powerpc/boot/dts/c293pcie.dts
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -45,6 +45,7 @@
ifc: ifc@fffe1e000 {
reg = <0xf 0xffe1e000 0 0x2000>;
ranges = <0x0 0x0 0xf 0xec000000 0x04000000
+ 0x1 0x0 0xf 0xff800000 0x00010000
0x2 0x0 0xf 0xffdf0000 0x00010000>;
};
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v10 2/3] DMA: Freescale: Add new 8-channel DMA engine device tree nodes
From: Hongbo Zhang @ 2013-09-24 10:30 UTC (permalink / raw)
To: Stephen Warren
Cc: mark.rutland, devicetree, ian.campbell, pawel.moll, vinod.koul,
linux-kernel, rob.herring, djbw, linuxppc-dev
In-Reply-To: <524074A7.7000001@wwwdotorg.org>
On 09/24/2013 01:04 AM, Stephen Warren wrote:
> On 09/18/2013 04:15 AM, hongbo.zhang@freescale.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>
>> Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
>> the device tree nodes for them.
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/dma.txt b/Documentation/devicetree/bindings/powerpc/fsl/dma.txt
>> +Required properties:
>> +
>> +- compatible : must include "fsl,elo3-dma"
>> +- reg : DMA General Status Registers, i.e. DGSR0 which contains
>> + status for channel 1~4, and DGSR1 for channel 5~8
> Is that a single entry, which is large enough to cover both registers,
> or a pair of entries, one per register? Reading the text, I might assume
> the former, but looking at the examples, it's the latter.
My impression is that I cannot tell it is one larger entry or two
entries by reading the description text, but the example gives the answer.
Is it so important to specify it is only one entry or entries list?
I prefer language as concise as possible, especially for the common
properties such as reg and interrupt (eg the reg is implicitly offset
and length of registers, can be continuous or not), it is difficult or
unnecessary or impossible to describe much details, the example can also
work as a complementary description, otherwise no need to put an example
in the binding document.
> ...
> +Example:
>> +dma@100300 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "fsl,elo3-dma";
>> + reg = <0x100300 0x4>,
>> + <0x100600 0x4>;
>
^ permalink raw reply
* RE: [PATCH] powerpc/85xx: DTS - re-organize the SPI partitions property
From: Hu Mingkai-B21284 @ 2013-09-24 10:27 UTC (permalink / raw)
To: Wood Scott-B07421; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <1379977371.24959.57.camel@snotra.buserror.net>
DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogV29vZCBTY290dC1CMDc0
MjENCj4gU2VudDogVHVlc2RheSwgU2VwdGVtYmVyIDI0LCAyMDEzIDc6MDMgQU0NCj4gVG86IEh1
IE1pbmdrYWktQjIxMjg0DQo+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsgbGludXhwcGMtZGV2QG96
bGFicy5vcmcNCj4gU3ViamVjdDogUmU6IFtQQVRDSF0gcG93ZXJwYy84NXh4OiBEVFMgLSByZS1v
cmdhbml6ZSB0aGUgU1BJIHBhcnRpdGlvbnMNCj4gcHJvcGVydHkNCj4gDQo+IE9uIFR1ZSwgMjAx
My0wOS0xNyBhdCAwNjowNiAtMDUwMCwgSHUgTWluZ2thaS1CMjEyODQgd3JvdGU6DQo+ID4gU2Nv
dHQsDQo+ID4gU29ycnkgZm9yIHRoZSBkZWxheWVkIHJlc3BvbnNlLg0KPiA+IFBsZWFzZSBmaW5l
IG15IGNvbW1lbnRzLg0KPiA+IFRoYW5rcywNCj4gPiBNaW5na2FpDQo+ID4NCj4gPiA+IC0tLS0t
T3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+ID4gPiBGcm9tOiBXb29kIFNjb3R0LUIwNzQyMQ0KPiA+
ID4gU2VudDogVGh1cnNkYXksIFNlcHRlbWJlciAxMiwgMjAxMyA5OjE2IEFNDQo+ID4gPiBUbzog
SHUgTWluZ2thaS1CMjEyODQNCj4gPiA+IENjOiBXb29kIFNjb3R0LUIwNzQyMTsgbGludXhwcGMt
ZGV2QG96bGFicy5vcmcNCj4gPiA+IFN1YmplY3Q6IFJlOiBbUEFUQ0hdIHBvd2VycGMvODV4eDog
RFRTIC0gcmUtb3JnYW5pemUgdGhlIFNQSQ0KPiA+ID4gcGFydGl0aW9ucyBwcm9wZXJ0eQ0KPiA+
ID4NCj4gPiA+IE9uIFR1ZSwgMjAxMy0wOS0xMCBhdCAyMTowNyAtMDUwMCwgSHUgTWluZ2thaS1C
MjEyODQgd3JvdGU6DQo+ID4gPiA+DQo+ID4gPiA+ID4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0t
LS0NCj4gPiA+ID4gPiBGcm9tOiBXb29kIFNjb3R0LUIwNzQyMQ0KPiA+ID4gPiA+IFNlbnQ6IFdl
ZG5lc2RheSwgU2VwdGVtYmVyIDExLCAyMDEzIDc6MzMgQU0NCj4gPiA+ID4gPiBUbzogSHUgTWlu
Z2thaS1CMjEyODQNCj4gPiA+ID4gPiBDYzogbGludXhwcGMtZGV2QG96bGFicy5vcmcNCj4gPiA+
ID4gPiBTdWJqZWN0OiBSZTogW1BBVENIXSBwb3dlcnBjLzg1eHg6IERUUyAtIHJlLW9yZ2FuaXpl
IHRoZSBTUEkNCj4gPiA+ID4gPiBwYXJ0aXRpb25zIHByb3BlcnR5DQo+ID4gPiA+ID4NCj4gPiA+
ID4gPiBXaGF0IGhhcHBlbnMgdG8gZXhzdGluZyB1c2VycyB3aG9zZSBmbGFzaCBpcyBsYWlkIG91
dCB0aGUNCj4gPiA+ID4gPiBleGlzdGluZyB3YXksIHdoZW4gdGhleSB1cGdyYWRlIHRvIHRoZXNl
IGRldmljZSB0cmVlcz8NCj4gPiA+ID4gPg0KPiA+ID4gPg0KPiA+ID4gPiBUaGUgU1BJIGZsYXNo
IGxheW91dCBzaG91bGQgYmUgbWFwcGluZyB0aGUgbmV3IGRldmljZSB0cmVlLg0KPiA+ID4gPg0K
PiA+ID4gPiBJZiB0aGUgZXhpc3RpbmcgZGV2aWNlIHRyZWUgaXMgdXNlZCB0byBkZXBsb3kgdGhl
IFNQSSBmbGFzaCwgdGhlDQo+ID4gPiA+IGZvbGxvd2luZyBpc3N1ZXMgbXVzdCBiZSBydW4gaW50
byBhcyB0aGUgY29tbWl0IG1lc3NhZ2UgZGVzY3JpYmVkOg0KPiA+ID4gPg0KPiA+ID4gPiAxLiBL
ZXJuZWwgaW1hZ2VzIHdvdWxkIGJlIG92ZXJsYXBwZWQgd2l0aCBVLUJvb3QgaW1hZ2UuDQo+ID4g
PiA+IDIuIEtlcm5lbCBpbWFnZXMgd291bGQgYmUgb3ZlcmxhcHBlZCB3aXRoIEZNQU4gdWNvZGUu
DQo+ID4gPiA+IDMuIFNhdmluZyBlbnZpcm9ubWVudCB2YXJpYWJsZXMgd2lsbCBjcmFzaCB0aGUg
a2VybmVsIGltYWdlLg0KPiA+ID4NCj4gPiA+IEhhcyB0aGUgU1BJIFUtQm9vdCBpbWFnZSBhbHdh
eXMgYmVlbiBsYXJnZXIgdGhhbiA1MTJLIGZvciBhbGwgdGhlc2UNCj4gPiA+IHBsYXRmb3Jtcz8g
IFdoeSwgZ2l2ZW4gdGhhdCB3ZSdyZSB1bmRlciA1MTJLIGZvciBvdGhlciBib290IG1vZGVzPw0K
PiA+ID4NCj4gPg0KPiA+IEZvciBEUEFBIHBsYXRmb3JtLCB0aGUgbGQgc2NyaXB0IHVzZWQgdG8g
bGluayB0aGUgdS1ib290IGltYWdlIGlzDQo+ID4gIi4vYXJjaC9wb3dlcnBjL2NwdS9tcGM4NXh4
L3UtYm9vdC5sZHMiIHdoaWNoIHdpbGwgZ2VuZXJhdGUgdGhlIDUxMksNCj4gPiB1LWJvb3QgSW1h
Z2UuIFRoaXMgaW1hZ2Ugd2lsbCBiZSBzcGxpdCBpbnRvIDY0Ynl0ZXMgYW5kIGFwcGVuZGVkIFBC
TA0KPiA+IGNvbW1hbmQgZm9yIEVhY2ggNjRieXRlcyBwaWVjZXMsIHNvIHRoZSBzaXplIG9mIGZp
bmFsIGltYWdlIG11c3QgYmUNCj4gZ3JlYXRlciB0aGFuIDUxMksuDQo+IA0KPiBXaGF0IGlzIHRo
ZSBlbnRyeSBwb2ludCBpbiBTUkFNIHdoZW4geW91IGxvYWQgZnJvbSBQQkw/ICBJZiBpdCBpcyAo
b3IgY2FuDQo+IGJlIG1hZGUgdG8gYmUpIHRoZSBiZWdpbm5pbmcgb2YgdGhlIGltYWdlIHJhdGhl
ciB0aGFuIHRoZSBlbmQsIHRoZW4gdHVybg0KPiBvZmYgdGhlIHJlc2V0dmVjIGFuZCB0aGUgZml4
ZWQgaW1hZ2Ugc2l6ZSB0aGF0IHJlc3VsdHMuDQo+IA0KDQoxLiBUaHVzIGEgc3BlY2lhbCBsZCBz
Y3JpcHQgbmVlZCB0byBiZSBwcm92aWRlZC4NCjIuIE5vdyB0aGUgc3BpIGltYWdlIHNpemUgaXMg
YWJvdXQgNTQwS0IsIHRoYXQncyB0byBzYXkgdGhlIFBCTCBuZWVkcyBhYm91dCB+MzBLDQogICBm
b3IgUEJMIGNvbW1hbmRzLiBJdCdzIGhhcmQgdG8gc2F2ZSBzdWNoIGEgYmlnIHNwYWNlIGV2ZW4g
d2UgdHVybiBvZmYgdGhlDQogICByZXNldHZlYy4NCg0KPiA+ID4gPiA+IFdlIHJlYWxseSBzaG91
bGQgbm90IGJlIHB1dHRpbmcgcGFydGl0aW9uIGxheW91dCBpbmZvIGluIHRoZQ0KPiA+ID4gPiA+
IGRldmljZSB0cmVlIHRvIGJlZ2luIHdpdGguLi4NCj4gPiA+ID4gPg0KPiA+ID4gPiBPSywgSSB3
aWxsIHJlbW92ZSB0aGUgbGF5b3V0IGRpYWdyYW0gaW4gdGhlIGNvbW1pdCBtZXNzYWdlLg0KPiA+
ID4NCj4gPiA+IFRoYXQncyBub3Qgd2hhdCBJIG1lYW50LiAgSSBtZWFudCB0aGF0IHRoZSBkdHMg
c2hvdWxkIGJlIGRlc2NyaWJpbmcNCj4gPiA+IGhhcmR3YXJlLCBhbmQgdGhpcyBpcyB0aGUgc29y
dCBvZiB0cm91YmxlIHdlIHJ1biBpbnRvIHdoZW4gd2UNCj4gPiA+IGRldmlhdGUgZnJvbSB0aGF0
LiAgQSBiZXR0ZXIgd2F5IHdvdWxkIGJlIHRvIHVzZSB0aGUgbXRkcGFydHMgY29tbWFuZA0KPiBs
aW5lIG9wdGlvbi4NCj4gPiA+IEV2ZW4gYmV0dGVyIHdvdWxkIGJlIHNvbWUgc29ydCBvZiBvbi1m
bGFzaCBwYXJ0aXRpb24gdGFibGUuDQo+ID4gPg0KPiA+DQo+ID4gWW91J3JlIHJpZ2h0LCBidXQg
bWF5YmUgc29tZSBjdXN0b21lciBoYXMgYWxyZWFkeSB1c2VkIHRoZSBkZXZpY2UgdHJlZQ0KPiBw
YXJ0aXRpb24gdGFibGUuLi4NCj4gDQo+IE15IG1haW4gcG9pbnQgd2FzIHRvIGVuY291cmFnZSB1
cyB0byBzaGlmdCBhd2F5IGZyb20gdGhpcyByYXRoZXIgdGhhbiB0bw0KPiByaXAgaXQgb3V0IHJp
Z2h0IHRoaXMgaW5zdGFudC4NCj4gDQoNClllcywgdGhhdCdzIHRoZSBjb3JyZWN0IHdheSB3ZSBz
aG91bGQgZ28uDQpXb3VsZCB5b3UgcGxlYXNlIHBpY2sgdXAgdGhpcyBwYXRjaCBmaXJzdCB0byBy
ZXNvbHZlIGN1cnJlbnQgaXNzdWUgd2UgZmFjZWQ/DQpBbmQgd2UgY2FuIGNvbnNpZGVyIHRvIHVz
ZSB0aGUgbXRkcGFydHMgb3Igb24tZmxhc2ggcGFydGl0aW9uIHRhYmxlIGZvciBsb25nIHRlcm0u
DQoNClRoYW5rcywNCk1pbmdrYWkNCg==
^ permalink raw reply
* Re: [PATCH v2] pci: fix interrupt-map for bridges
From: Nikunj A Dadhania @ 2013-09-24 9:42 UTC (permalink / raw)
To: Alexey Kardashevskiy, linuxppc-dev; +Cc: Alexey Kardashevskiy
In-Reply-To: <1380007334-466-1-git-send-email-aik@ozlabs.ru>
Alexey Kardashevskiy <aik@ozlabs.ru> writes:
> The previous scheme always put 0 as a parent slot#. However it is
> not always the case and QEMU's PCI bridge does not support putting
> device at slot#0 as it claims SHPC support for hotplug.
>
> This modifies the interrups map to let the linux guest resolve XICS
> global interrupt number correctly.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Thanks, Will pull this for next build.
Regards
Nikunj
> ---
> Changes:
> v2:
> * removed redundand r-stack push-pop
>
^ permalink raw reply
* [PATCH v4 3/4] powerpc/85xx: add hardware automatically enter pw20 state
From: Dongsheng Wang @ 2013-09-24 9:28 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1380014925-23300-2-git-send-email-dongsheng.wang@freescale.com>
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Assembly code instead of C code.
*v2:
Remove:
delete setup_idle_hw_governor function.
delete "Fix erratum" for rev1.
Move:
move setup_* into __setup/restore_cpu_e6500.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4789056..49e738e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup)
/*
* FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+ mfspr r3, SPRN_PWRMGTCR0
+
+ /* Set PW20_WAIT bit, enable pw20 state*/
+ ori r3, r3, PWRMGTCR0_PW20_WAIT
+ li r11, PW20_WAIT_IDLE_BIT
+
+ /* Set Automatic PW20 Core Idle Count */
+ rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+ mtspr SPRN_PWRMGTCR0, r3
+
+ blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
* value for AV_WAIT_IDLE_BIT.
*/
#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
@@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500)
#ifdef CONFIG_PPC64
bl .setup_altivec_ivors
#endif
+ bl setup_pw20_idle
bl setup_altivec_idle
bl __setup_cpu_e5500
mtlr r6
@@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500)
_GLOBAL(__restore_cpu_e6500)
mflr r5
bl .setup_altivec_ivors
+ bl .setup_pw20_idle
bl .setup_altivec_idle
bl __restore_cpu_e5500
mtlr r5
--
1.8.0
^ permalink raw reply related
* [PATCH v4 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Dongsheng Wang @ 2013-09-24 9:28 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1380014925-23300-2-git-send-email-dongsheng.wang@freescale.com>
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~47(ns): TB[63]
48~95(ns): TB[62]
96~191(ns): TB[61]
192~383(ns): TB[62]
384~767(ns): TB[60]
...
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v4:
Move code from 85xx/common.c to kernel/sysfs.c.
Remove has_pw20_altivec_idle function.
Change wait "entry_bit" to wait time.
arch/powerpc/kernel/sysfs.c | 291 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 291 insertions(+)
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 27a90b9..23fece6 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -85,6 +85,279 @@ __setup("smt-snooze-delay=", setup_smt_snooze_delay);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT 63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+ u64 cycle;
+
+ cycle = div_u64(ns, 1000 / tb_ticks_per_usec);
+ if (!cycle)
+ return 0;
+
+ return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+ u32 *value = val;
+
+ *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+ value &= PWRMGTCR0_PW20_WAIT;
+
+ return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+ u32 *value = val;
+ u32 pw20_state;
+
+ pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
+ pw20_state |= PWRMGTCR0_PW20_WAIT;
+ else
+ pw20_state &= ~PWRMGTCR0_PW20_WAIT;
+
+ mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ if (kstrtou32(buf, 0, &value))
+ return -EINVAL;
+
+ if (value > 1)
+ return -EINVAL;
+
+ smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
+
+ return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ u64 tb_cycle;
+ u64 time;
+
+ unsigned int cpu = dev->id;
+
+ if (!pw20_wt) {
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+ value = (value & PWRMGTCR0_PW20_ENT) >>
+ PWRMGTCR0_PW20_ENT_SHIFT;
+
+ tb_cycle = (1 << (MAX_BIT - value)) * 2;
+ time = tb_cycle * (1000 / tb_ticks_per_usec) - 1;
+ } else {
+ time = pw20_wt;
+ }
+
+ return sprintf(buf, "%llu\n", time);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+ u32 *value = val;
+ u32 pw20_idle;
+
+ pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+ /* Set Automatic PW20 Core Idle Count */
+ /* clear count */
+ pw20_idle &= ~PWRMGTCR0_PW20_ENT;
+
+ /* set count */
+ pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
+
+ mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 entry_bit;
+ u64 value;
+
+ unsigned int cpu = dev->id;
+
+ if (kstrtou64(buf, 0, &value))
+ return -EINVAL;
+
+ if (!value)
+ return -EINVAL;
+
+ entry_bit = get_idle_ticks_bit(value);
+ if (entry_bit > MAX_BIT)
+ return -EINVAL;
+
+ pw20_wt = value;
+ smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+ &entry_bit, 1);
+
+ return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+ value &= PWRMGTCR0_AV_IDLE_PD_EN;
+
+ return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+ u32 *value = val;
+ u32 altivec_idle;
+
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
+ altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
+ else
+ altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
+
+ mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ if (kstrtou32(buf, 0, &value))
+ return -EINVAL;
+
+ if (value > 1)
+ return -EINVAL;
+
+ smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
+
+ return count;
+}
+
+static ssize_t show_altivec_idle_wait_time(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ u64 tb_cycle;
+ u64 time;
+
+ unsigned int cpu = dev->id;
+
+ if (!altivec_idle_wt) {
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+ value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
+ PWRMGTCR0_AV_IDLE_CNT_SHIFT;
+
+ tb_cycle = (1 << (MAX_BIT - value)) * 2;
+ time = tb_cycle * (1000 / tb_ticks_per_usec) - 1;
+ } else {
+ time = altivec_idle_wt;
+ }
+
+ return sprintf(buf, "%llu\n", time);
+}
+
+static void set_altivec_idle_wait_entry_bit(void *val)
+{
+ u32 *value = val;
+ u32 altivec_idle;
+
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+ /* Set Automatic AltiVec Idle Count */
+ /* clear count */
+ altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
+
+ /* set count */
+ altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
+
+ mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle_wait_time(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 entry_bit;
+ u64 value;
+
+ unsigned int cpu = dev->id;
+
+ if (kstrtou64(buf, 0, &value))
+ return -EINVAL;
+
+ if (!value)
+ return -EINVAL;
+
+ entry_bit = get_idle_ticks_bit(value);
+ if (entry_bit > MAX_BIT)
+ return -EINVAL;
+
+ altivec_idle_wt = value;
+ smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
+ &entry_bit, 1);
+
+ return count;
+}
+
+/*
+ * Enable/Disable interface:
+ * 0, disable. 1, enable.
+ */
+static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
+static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
+
+/*
+ * Set wait time interface:(Nanosecond)
+ * Example: Base on TBfreq is 41MHZ.
+ * 1~47(ns): TB[63]
+ * 48~95(ns): TB[62]
+ * 96~191(ns): TB[61]
+ * 192~383(ns): TB[62]
+ * 384~767(ns): TB[60]
+ * ...
+ */
+static DEVICE_ATTR(pw20_wait_time, 0600,
+ show_pw20_wait_time,
+ store_pw20_wait_time);
+static DEVICE_ATTR(altivec_idle_wait_time, 0600,
+ show_altivec_idle_wait_time,
+ store_altivec_idle_wait_time);
+#endif
+
/*
* Enabling PMCs will slow partition context switch times so we only do
* it the first time we write to the PMCs.
@@ -407,6 +680,15 @@ static void register_cpu_online(unsigned int cpu)
device_create_file(s, &dev_attr_pir);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+ if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+ device_create_file(s, &dev_attr_pw20_state);
+ device_create_file(s, &dev_attr_pw20_wait_time);
+
+ device_create_file(s, &dev_attr_altivec_idle);
+ device_create_file(s, &dev_attr_altivec_idle_wait_time);
+ }
+#endif
cacheinfo_cpu_online(cpu);
}
@@ -479,6 +761,15 @@ static void unregister_cpu_online(unsigned int cpu)
device_remove_file(s, &dev_attr_pir);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+ if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+ device_remove_file(s, &dev_attr_pw20_state);
+ device_remove_file(s, &dev_attr_pw20_wait_time);
+
+ device_remove_file(s, &dev_attr_altivec_idle);
+ device_remove_file(s, &dev_attr_altivec_idle_wait_time);
+ }
+#endif
cacheinfo_cpu_offline(cpu);
}
--
1.8.0
^ permalink raw reply related
* [PATCH v4 2/4] powerpc/85xx: add hardware automatically enter altivec idle state
From: Dongsheng Wang @ 2013-09-24 9:28 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev, Wang Dongsheng
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Assembly code instead of C code.
*v2:
Remove:
delete setup_idle_hw_governor function.
delete "Fix erratum" for rev1.
Move:
move setup_* into __setup/restore_cpu_e6500.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..4789056 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+ mfspr r3, SPRN_PWRMGTCR0
+
+ /* Enable Altivec Idle */
+ oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+ li r11, AV_WAIT_IDLE_BIT
+
+ /* Set Automatic AltiVec Idle Count */
+ rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+ mtspr SPRN_PWRMGTCR0, r3
+
+ blr
+
_GLOBAL(__setup_cpu_e6500)
mflr r6
#ifdef CONFIG_PPC64
bl .setup_altivec_ivors
#endif
+ bl setup_altivec_idle
bl __setup_cpu_e5500
mtlr r6
blr
@@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500)
_GLOBAL(__restore_cpu_e6500)
mflr r5
bl .setup_altivec_ivors
+ bl .setup_altivec_idle
bl __restore_cpu_e5500
mtlr r5
blr
--
1.8.0
^ permalink raw reply related
* [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
From: Dongsheng Wang @ 2013-09-24 9:27 UTC (permalink / raw)
To: scottwood; +Cc: linuxppc-dev, Wang Dongsheng
From: Wang Dongsheng <dongsheng.wang@freescale.com>
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Add bit definitions for PWRMGTCR0.
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
#define PVR_8560 0x80200000
#define PVR_VER_E500V1 0x8020
#define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500 0x8040
+
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
#define SPRN_SVR 0x3FF /* System Version Register */
/*
@@ -216,6 +217,14 @@
#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define CCR1_TCS 0x00000080 /* Timer Clock Select */
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT 8
+#define PWRMGTCR0_PW20_ENT 0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
+#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
+
/* Bit definitions for the MCSR. */
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
--
1.8.0
^ permalink raw reply related
* Re: [PATCH] powerpc/4xx: Fix warning in kilauea.dtb
From: Ian Campbell @ 2013-09-24 9:10 UTC (permalink / raw)
To: Josh Boyer
Cc: Tirumala R Marri, Rupjyoti Sarmah, linux-kernel, Josh Boyer,
Paul Mackerras, linuxppc-dev
In-Reply-To: <20130603133633.GA18391@zod>
On Mon, 2013-06-03 at 09:36 -0400, Josh Boyer wrote:
> On Mon, Jun 03, 2013 at 12:00:24PM +0100, Ian Campbell wrote:
> >Currently I see:
> > DTC arch/powerpc/boot/kilauea.dtb
> >Warning (reg_format): "reg" property in /plb/ppc4xx-msi@C10000000 has invalid length (12 bytes) (#address-cells == 1, #size-cells == 1)
> >
> >It appears that unlike the other plarforms handled by 3fb7933850fa
> >"powerpc/4xx: Adding PCIe MSI support" this platform does not use address-cells=2.
>
> Right, it's a 405, not a 440. I should have caught that in the initial
> review.
>
> >Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> >Cc: Rupjyoti Sarmah <rsarmah@apm.com>
> >Cc: Tirumala R Marri <tmarri@apm.com>
> >Cc: Josh Boyer <jwboyer@linux.vnet.ibm.com>
>
> That address should bounce. It hasn't been active in almost 2 years.
>
> >Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >Cc: Paul Mackerras <paulus@samba.org>
> >Cc: linuxppc-dev@lists.ozlabs.org
> >Cc: linux-kernel@vger.kernel.org
>
> Acked-by: Josh Boyer <jwboyer@gmail.com>
This still doesn't appear to be fixed v3.12-rc2. Ping?
>
> >---
> > arch/powerpc/boot/dts/kilauea.dts | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
> >index 1613d6e..5ba7f01 100644
> >--- a/arch/powerpc/boot/dts/kilauea.dts
> >+++ b/arch/powerpc/boot/dts/kilauea.dts
> >@@ -406,7 +406,7 @@
> >
> > MSI: ppc4xx-msi@C10000000 {
> > compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
> >- reg = < 0x0 0xEF620000 0x100>;
> >+ reg = <0xEF620000 0x100>;
> > sdr-base = <0x4B0>;
> > msi-data = <0x00000000>;
> > msi-mask = <0x44440000>;
> >--
> >1.7.10.4
> >
> >_______________________________________________
> >Linuxppc-dev mailing list
> >Linuxppc-dev@lists.ozlabs.org
> >https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] powerpc/dts/virtex440: declare address/size-cells for phy device
From: Ian Campbell @ 2013-09-24 9:11 UTC (permalink / raw)
To: linux-kernel; +Cc: Paul Mackerras, linuxppc-dev, Gernot Vormayr
In-Reply-To: <1370257241-23923-1-git-send-email-ian.campbell@citrix.com>
On Mon, 2013-06-03 at 12:00 +0100, Ian Campbell wrote:
> This fixes a warning:
>
> DTC arch/powerpc/boot/virtex440-ml507.dtb
> Warning (reg_format): "reg" property in /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7
I still see this in v3.12-rc2. Ping?
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Gernot Vormayr <gvormayr@gmail.com>
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/powerpc/boot/dts/virtex440-ml507.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
> index fc7073b..391a4e2 100644
> --- a/arch/powerpc/boot/dts/virtex440-ml507.dts
> +++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
> @@ -257,6 +257,8 @@
> #size-cells = <1>;
> compatible = "xlnx,compound";
> ethernet@81c00000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> compatible = "xlnx,xps-ll-temac-1.01.b";
> device_type = "network";
> interrupt-parent = <&xps_intc_0>;
^ permalink raw reply
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