* Re: [PATCH RFC 07/77] PCI/MSI: Re-design MSI/MSI-X interrupts enablement pattern
From: Tejun Heo @ 2013-10-09 15:54 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, linux-doc, VMware, Inc., linux-nvme, linux-ide,
linux-s390, Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar,
linux-pci, iss_storagedev, linux-driver, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
linux390, linuxppc-dev
In-Reply-To: <20131008074826.GD10669@dhcp-26-207.brq.redhat.com>
Hello, Alexander.
On Tue, Oct 08, 2013 at 09:48:26AM +0200, Alexander Gordeev wrote:
> > If there are many which duplicate the above pattern, it'd probably be
> > worthwhile to provide a helper? It's usually a good idea to reduce
> > the amount of boilerplate code in drivers.
>
> I wanted to limit discussion in v1 to as little changes as possible.
> I 'planned' those helper(s) for a separate effort if/when the most
> important change is accepted and soaked a bit.
The thing is doing it this way generates more churns and noises. Once
the simpler ones live behind a wrapper which can be built on the
existing interface, we can have both reduced cost and more latitude on
the complex cases.
> > If we do things this way, it breaks all drivers using this interface
> > until they're converted, right?
>
> Right. And the rest of the series does it.
Which breaks bisection which we shouldn't do.
> > Also, it probably isn't the best idea
> > to flip the behavior like this as this can go completely unnoticed (no
> > compiler warning or anything, the same function just behaves
> > differently). Maybe it'd be a better idea to introduce a simpler
> > interface that most can be converted to?
>
> Well, an *other* interface is a good idea. What do you mean with the
> simpler here?
I'm still talking about a simpler wrapper for common cases, which is
the important part anyway.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Tejun Heo @ 2013-10-09 15:46 UTC (permalink / raw)
To: Ben Hutchings
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Alexander Gordeev,
linux-pci, iss_storagedev, linux-driver, Bjorn Helgaas,
Dan Williams, Jon Mason, Ingo Molnar,
Solarflare linux maintainers, netdev, linux-kernel, Ralf Baechle,
e1000-devel, Martin Schwidefsky, linux390, linuxppc-dev
In-Reply-To: <1381178881.1536.28.camel@bwh-desktop.uk.level5networks.com>
On Mon, Oct 07, 2013 at 09:48:01PM +0100, Ben Hutchings wrote:
> > There is one major flaw in min-max approach - the generic MSI layer
> > will have to take decisions on exact number of MSIs to request, not
> > device drivers.
> [...
>
> No, the min-max functions should be implemented using the same loop that
> drivers are expected to use now.
Wheee... earlier in the thread I thought you guys were referring to
yourselves in the third person and was getting a bit worried. :)
--
tejun
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Tejun Heo @ 2013-10-09 15:43 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar, linux-pci,
iss_storagedev, linux-driver, linux390, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
Ben Hutchings, linuxppc-dev
In-Reply-To: <20131009125715.GC32733@dhcp-26-207.brq.redhat.com>
Hello,
On Wed, Oct 09, 2013 at 02:57:16PM +0200, Alexander Gordeev wrote:
> On Mon, Oct 07, 2013 at 02:01:11PM -0400, Tejun Heo wrote:
> > Hmmm... yean, the race condition could be an issue as multiple msi
> > allocation might fail even if the driver can and explicitly handle
> > multiple allocation if the quota gets reduced inbetween.
>
> BTW, should we care about the quota getting increased inbetween?
> That would entail.. kind of pci_get_msi_limit() :), but IMHO it is
> not worth it.
I think we shouldn't. If the resource was low during a point in time
during allocation, it's fine to base the result on that - the resource
was actually low and which answer we return is just a question of
timing and both are correct. The only reason the existing race
condition is problematic is because it may fail even if the resource
never falls below the failure point.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Tejun Heo @ 2013-10-09 15:41 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar, linux-pci,
iss_storagedev, linux-driver, linux390, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
Ben Hutchings, linuxppc-dev
In-Reply-To: <20131008122215.GA14389@dhcp-26-207.brq.redhat.com>
Hello,
On Tue, Oct 08, 2013 at 02:22:16PM +0200, Alexander Gordeev wrote:
> If we talk about pSeries quota, then the current pSeries pci_enable_msix()
> implementation is racy internally and could fail if the quota went down
> *while* pci_enable_msix() is executing. In this case the loop will have to
> exit rather than retry with a lower number (what number?).
Ah, okay, so that one is already broken.
> In this regard the new scheme does not bring anything new and relies on
> the fact this race does not hit and therefore does not worry.
>
> If we talk about quota as it has to be, then yes - the loop scheme seems
> more preferable.
>
> Overall, looks like we just need to fix the pSeries implementation,
> if the guys want it, he-he :)
If we can't figure out a better interface for the retry case, I think
what can really help is having a simple interface for the simpler
cases.
> > The problem case is where multiple msi(x) allocation fails completely
> > because the global limit went down before inquiry and allocation. In
> > the loop based interface, it'd retry with the lower number.
>
> I am probably missing something here. If the global limit went down before
> inquiry then the inquiry will get what is available and try to allocate with
> than number.
Oh, I should have written between inquiry and allocation. Sorry.
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH 1/2][v2] pci: fsl: derive the common PCI driver to drivers/pci/host
From: Bjorn Helgaas @ 2013-10-09 14:53 UTC (permalink / raw)
To: Lian Minghuan-b31939
Cc: linux-pci@vger.kernel.org, Zang Roy-R61911, Minghuan Lian,
Paul Mackerras, Scott Wood, linuxppc-dev
In-Reply-To: <52552C8D.1050303@freescale.com>
On Wed, Oct 9, 2013 at 4:14 AM, Lian Minghuan-b31939
<B31939@freescale.com> wrote:
> arch/powerpc/sysdev/fsl_pci.c | 521 +-----------------
> arch/powerpc/sysdev/fsl_pci.h | 89 ----
> .../fsl_pci.c => drivers/pci/host/pci-fsl-common.c | 591
> +--------------------
> .../fsl_pci.h => include/linux/fsl/pci-common.h | 45 +-
>
> Is there any way to avoid putting this file in include/linux? I know
> you want to share it beyond PowerPC, and I know there are similar
> examples there already, but this is all arch-specific or
> chipset-specific stuff that seems like it should be in some
> not-so-public place. It doesn't seem scalable to add an include/linux
> subdirectory for every chipset that might be shared across
> architectures.
>
> [Minghuan] I can move pci-common.h to drivers/pci/host/
> But in arch/powerpc/sysdev/fsl_pci.c I must include the header file
> like this:
> #include "../../../drivers/pci/host/pci-fsl-common.h".
> How about this modification?
Given the existence of include/linux/fsl/ even before this patch, I'm
OK with it as-is.
After you work through Scott's comments on [2/2] and get his ack, I'll
merge the whole bundle as a group.
Bjorn
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Alexander Gordeev @ 2013-10-09 12:57 UTC (permalink / raw)
To: Tejun Heo
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar, linux-pci,
iss_storagedev, linux-driver, linux390, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
Ben Hutchings, linuxppc-dev
In-Reply-To: <20131007180111.GC2481@htj.dyndns.org>
On Mon, Oct 07, 2013 at 02:01:11PM -0400, Tejun Heo wrote:
> Hmmm... yean, the race condition could be an issue as multiple msi
> allocation might fail even if the driver can and explicitly handle
> multiple allocation if the quota gets reduced inbetween.
BTW, should we care about the quota getting increased inbetween?
That would entail.. kind of pci_get_msi_limit() :), but IMHO it is
not worth it.
> tejun
--
Regards,
Alexander Gordeev
agordeev@redhat.com
^ permalink raw reply
* Re: [PATCH 1/2][v2] pci: fsl: derive the common PCI driver to drivers/pci/host
From: Lian Minghuan-b31939 @ 2013-10-09 10:14 UTC (permalink / raw)
To: Bjorn Helgaas, Minghuan Lian
Cc: linux-pci@vger.kernel.org, Zang Roy-R61911, Paul Mackerras,
Scott Wood, linuxppc-dev
In-Reply-To: <CAErSpo7LXqXmrw1gPwKHsJkKaAcDr2W_+tcC8b9T_5Mab1Arnw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 44962 bytes --]
Hi Bjorn,
Thanks for your review, please see my comments inline.
On 10/09/2013 03:13 AM, Bjorn Helgaas wrote:
> [+cc Ben, Paul, linuxppc-dev]
>
> On Mon, Sep 30, 2013 at 04:52:54PM +0800, Minghuan Lian wrote:
>> The Freescale's Layerscape series processors will use ARM cores.
>> The LS1's PCIe controllers is the same as T4240's. So it's better
>> the PCIe controller driver can support PowerPC and ARM
>> simultaneously. This patch is for this purpose. It derives
>> the common functions from arch/powerpc/sysdev/fsl_pci.c to
>> drivers/pci/host/pci-fsl-common.c and leaves the architecture
>> specific functions which should be implemented in arch related files.
>>
>> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
> I cc'd the powerpc maintainers so we can work out which tree this
> should go through.
>
>> ---
>> change log:
>> v1-v2:
>> 1. rename pci.h to pci-common.h
>> 2. rename pci-fsl.c to pci-fsl-common.c
>>
>> Based on upstream master.
>> Based on the discussion of RFC version here
>> http://patchwork.ozlabs.org/patch/274487/
>>
>> arch/powerpc/sysdev/fsl_pci.c | 521 +-----------------
>> arch/powerpc/sysdev/fsl_pci.h | 89 ----
>> .../fsl_pci.c => drivers/pci/host/pci-fsl-common.c | 591 +--------------------
>> .../fsl_pci.h => include/linux/fsl/pci-common.h | 45 +-
> Is there any way to avoid putting this file in include/linux? I know
> you want to share it beyond PowerPC, and I know there are similar
> examples there already, but this is all arch-specific or
> chipset-specific stuff that seems like it should be in some
> not-so-public place. It doesn't seem scalable to add an include/linux
> subdirectory for every chipset that might be shared across
> architectures.
[Minghuan] I can move pci-common.h to drivers/pci/host/
But in arch/powerpc/sysdev/fsl_pci.c I must include the header file
like this:
#include "../../../drivers/pci/host/pci-fsl-common.h"./
/How about this modification?
> I assume this patch basically just moves code around, so the only
> question I really care about is where it ends up.
[Minghuan] patch 2/2 modified the code, removed arch-specific code from
drivers/pci/host/pci-fsl.c. When I verify the pci driver code on LS1
board, I will
submit a patch to support ARM arch.
> Bjorn
>
>> 4 files changed, 7 insertions(+), 1239 deletions(-)
>> copy arch/powerpc/sysdev/fsl_pci.c => drivers/pci/host/pci-fsl-common.c (54%)
>> copy arch/powerpc/sysdev/fsl_pci.h => include/linux/fsl/pci-common.h (79%)
>>
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
>> index ccfb50d..26039e3 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>> @@ -27,6 +27,7 @@
>> #include <linux/log2.h>
>> #include <linux/slab.h>
>> #include <linux/uaccess.h>
>> +#include <linux/fsl/pci-common.h>
>>
>> #include <asm/io.h>
>> #include <asm/prom.h>
>> @@ -58,57 +59,8 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
>> return;
>> }
>>
>> -static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
>> - int, int, u32 *);
>> -
>> -static int fsl_pcie_check_link(struct pci_controller *hose)
>> -{
>> - u32 val = 0;
>> -
>> - if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
>> - if (hose->ops->read == fsl_indirect_read_config) {
>> - struct pci_bus bus;
>> - bus.number = hose->first_busno;
>> - bus.sysdata = hose;
>> - bus.ops = hose->ops;
>> - indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
>> - } else
>> - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
>> - if (val < PCIE_LTSSM_L0)
>> - return 1;
>> - } else {
>> - struct ccsr_pci __iomem *pci = hose->private_data;
>> - /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
>> - val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
>> - >> PEX_CSR0_LTSSM_SHIFT;
>> - if (val != PEX_CSR0_LTSSM_L0)
>> - return 1;
>> - }
>> -
>> - return 0;
>> -}
>> -
>> -static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
>> - int offset, int len, u32 *val)
>> -{
>> - struct pci_controller *hose = pci_bus_to_host(bus);
>> -
>> - if (fsl_pcie_check_link(hose))
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> - else
>> - hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> -
>> - return indirect_read_config(bus, devfn, offset, len, val);
>> -}
>> -
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>>
>> -static struct pci_ops fsl_indirect_pcie_ops =
>> -{
>> - .read = fsl_indirect_read_config,
>> - .write = indirect_write_config,
>> -};
>> -
>> #define MAX_PHYS_ADDR_BITS 40
>> static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
>>
>> @@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
>> return 0;
>> }
>>
>> -static int setup_one_atmu(struct ccsr_pci __iomem *pci,
>> - unsigned int index, const struct resource *res,
>> - resource_size_t offset)
>> -{
>> - resource_size_t pci_addr = res->start - offset;
>> - resource_size_t phys_addr = res->start;
>> - resource_size_t size = resource_size(res);
>> - u32 flags = 0x80044000; /* enable & mem R/W */
>> - unsigned int i;
>> -
>> - pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
>> - (u64)res->start, (u64)size);
>> -
>> - if (res->flags & IORESOURCE_PREFETCH)
>> - flags |= 0x10000000; /* enable relaxed ordering */
>> -
>> - for (i = 0; size > 0; i++) {
>> - unsigned int bits = min(ilog2(size),
>> - __ffs(pci_addr | phys_addr));
>> -
>> - if (index + i >= 5)
>> - return -1;
>> -
>> - out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
>> - out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
>> - out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
>> - out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
>> -
>> - pci_addr += (resource_size_t)1U << bits;
>> - phys_addr += (resource_size_t)1U << bits;
>> - size -= (resource_size_t)1U << bits;
>> - }
>> -
>> - return i;
>> -}
>> -
>> -/* atmu setup for fsl pci/pcie controller */
>> -static void setup_pci_atmu(struct pci_controller *hose)
>> -{
>> - struct ccsr_pci __iomem *pci = hose->private_data;
>> - int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
>> - u64 mem, sz, paddr_hi = 0;
>> - u64 offset = 0, paddr_lo = ULLONG_MAX;
>> - u32 pcicsrbar = 0, pcicsrbar_sz;
>> - u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
>> - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
>> - const char *name = hose->dn->full_name;
>> - const u64 *reg;
>> - int len;
>> -
>> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> - if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
>> - win_idx = 2;
>> - start_idx = 0;
>> - end_idx = 3;
>> - }
>> - }
>> -
>> - /* Disable all windows (except powar0 since it's ignored) */
>> - for(i = 1; i < 5; i++)
>> - out_be32(&pci->pow[i].powar, 0);
>> - for (i = start_idx; i < end_idx; i++)
>> - out_be32(&pci->piw[i].piwar, 0);
>> -
>> - /* Setup outbound MEM window */
>> - for(i = 0, j = 1; i < 3; i++) {
>> - if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
>> - continue;
>> -
>> - paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
>> - paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
>> -
>> - /* We assume all memory resources have the same offset */
>> - offset = hose->mem_offset[i];
>> - n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
>> -
>> - if (n < 0 || j >= 5) {
>> - pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
>> - hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
>> - } else
>> - j += n;
>> - }
>> -
>> - /* Setup outbound IO window */
>> - if (hose->io_resource.flags & IORESOURCE_IO) {
>> - if (j >= 5) {
>> - pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
>> - } else {
>> - pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
>> - "phy base 0x%016llx.\n",
>> - (u64)hose->io_resource.start,
>> - (u64)resource_size(&hose->io_resource),
>> - (u64)hose->io_base_phys);
>> - out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
>> - out_be32(&pci->pow[j].potear, 0);
>> - out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
>> - /* Enable, IO R/W */
>> - out_be32(&pci->pow[j].powar, 0x80088000
>> - | (ilog2(hose->io_resource.end
>> - - hose->io_resource.start + 1) - 1));
>> - }
>> - }
>> -
>> - /* convert to pci address space */
>> - paddr_hi -= offset;
>> - paddr_lo -= offset;
>> -
>> - if (paddr_hi == paddr_lo) {
>> - pr_err("%s: No outbound window space\n", name);
>> - return;
>> - }
>> -
>> - if (paddr_lo == 0) {
>> - pr_err("%s: No space for inbound window\n", name);
>> - return;
>> - }
>> -
>> - /* setup PCSRBAR/PEXCSRBAR */
>> - early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
>> - early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
>> - pcicsrbar_sz = ~pcicsrbar_sz + 1;
>> -
>> - if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
>> - (paddr_lo > 0x100000000ull))
>> - pcicsrbar = 0x100000000ull - pcicsrbar_sz;
>> - else
>> - pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
>> - early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
>> -
>> - paddr_lo = min(paddr_lo, (u64)pcicsrbar);
>> -
>> - pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
>> -
>> - /* Setup inbound mem window */
>> - mem = memblock_end_of_DRAM();
>> -
>> - /*
>> - * The msi-address-64 property, if it exists, indicates the physical
>> - * address of the MSIIR register. Normally, this register is located
>> - * inside CCSR, so the ATMU that covers all of CCSR is used. But if
>> - * this property exists, then we normally need to create a new ATMU
>> - * for it. For now, however, we cheat. The only entity that creates
>> - * this property is the Freescale hypervisor, and the address is
>> - * specified in the partition configuration. Typically, the address
>> - * is located in the page immediately after the end of DDR. If so, we
>> - * can avoid allocating a new ATMU by extending the DDR ATMU by one
>> - * page.
>> - */
>> - reg = of_get_property(hose->dn, "msi-address-64", &len);
>> - if (reg && (len == sizeof(u64))) {
>> - u64 address = be64_to_cpup(reg);
>> -
>> - if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
>> - pr_info("%s: extending DDR ATMU to cover MSIIR", name);
>> - mem += PAGE_SIZE;
>> - } else {
>> - /* TODO: Create a new ATMU for MSIIR */
>> - pr_warn("%s: msi-address-64 address of %llx is "
>> - "unsupported\n", name, address);
>> - }
>> - }
>> -
>> - sz = min(mem, paddr_lo);
>> - mem_log = ilog2(sz);
>> -
>> - /* PCIe can overmap inbound & outbound since RX & TX are separated */
>> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> - /* Size window to exact size if power-of-two or one size up */
>> - if ((1ull << mem_log) != mem) {
>> - mem_log++;
>> - if ((1ull << mem_log) > mem)
>> - pr_info("%s: Setting PCI inbound window "
>> - "greater than memory size\n", name);
>> - }
>> -
>> - piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
>> -
>> - /* Setup inbound memory window */
>> - out_be32(&pci->piw[win_idx].pitar, 0x00000000);
>> - out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
>> - out_be32(&pci->piw[win_idx].piwar, piwar);
>> - win_idx--;
>> -
>> - hose->dma_window_base_cur = 0x00000000;
>> - hose->dma_window_size = (resource_size_t)sz;
>> -
>> - /*
>> - * if we have >4G of memory setup second PCI inbound window to
>> - * let devices that are 64-bit address capable to work w/o
>> - * SWIOTLB and access the full range of memory
>> - */
>> - if (sz != mem) {
>> - mem_log = ilog2(mem);
>> -
>> - /* Size window up if we dont fit in exact power-of-2 */
>> - if ((1ull << mem_log) != mem)
>> - mem_log++;
>> -
>> - piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
>> -
>> - /* Setup inbound memory window */
>> - out_be32(&pci->piw[win_idx].pitar, 0x00000000);
>> - out_be32(&pci->piw[win_idx].piwbear,
>> - pci64_dma_offset >> 44);
>> - out_be32(&pci->piw[win_idx].piwbar,
>> - pci64_dma_offset >> 12);
>> - out_be32(&pci->piw[win_idx].piwar, piwar);
>> -
>> - /*
>> - * install our own dma_set_mask handler to fixup dma_ops
>> - * and dma_offset
>> - */
>> - ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
>> -
>> - pr_info("%s: Setup 64-bit PCI DMA window\n", name);
>> - }
>> - } else {
>> - u64 paddr = 0;
>> -
>> - /* Setup inbound memory window */
>> - out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
>> - out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
>> - out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
>> - win_idx--;
>> -
>> - paddr += 1ull << mem_log;
>> - sz -= 1ull << mem_log;
>> -
>> - if (sz) {
>> - mem_log = ilog2(sz);
>> - piwar |= (mem_log - 1);
>> -
>> - out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
>> - out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
>> - out_be32(&pci->piw[win_idx].piwar, piwar);
>> - win_idx--;
>> -
>> - paddr += 1ull << mem_log;
>> - }
>> -
>> - hose->dma_window_base_cur = 0x00000000;
>> - hose->dma_window_size = (resource_size_t)paddr;
>> - }
>> -
>> - if (hose->dma_window_size < mem) {
>> -#ifdef CONFIG_SWIOTLB
>> - ppc_swiotlb_enable = 1;
>> -#else
>> - pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
>> - "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
>> - name);
>> -#endif
>> - /* adjusting outbound windows could reclaim space in mem map */
>> - if (paddr_hi < 0xffffffffull)
>> - pr_warning("%s: WARNING: Outbound window cfg leaves "
>> - "gaps in memory map. Adjusting the memory map "
>> - "could reduce unnecessary bounce buffering.\n",
>> - name);
>> -
>> - pr_info("%s: DMA window size is 0x%llx\n", name,
>> - (u64)hose->dma_window_size);
>> - }
>> -}
>> -
>> -static void __init setup_pci_cmd(struct pci_controller *hose)
>> -{
>> - u16 cmd;
>> - int cap_x;
>> -
>> - early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
>> - cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
>> - | PCI_COMMAND_IO;
>> - early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
>> -
>> - cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
>> - if (cap_x) {
>> - int pci_x_cmd = cap_x + PCI_X_CMD;
>> - cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
>> - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
>> - early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
>> - } else {
>> - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
>> - }
>> -}
>> -
>> void fsl_pcibios_fixup_bus(struct pci_bus *bus)
>> {
>> struct pci_controller *hose = pci_bus_to_host(bus);
>> @@ -454,112 +121,6 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
>> }
>> }
>>
>> -int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
>> -{
>> - int len;
>> - struct pci_controller *hose;
>> - struct resource rsrc;
>> - const int *bus_range;
>> - u8 hdr_type, progif;
>> - struct device_node *dev;
>> - struct ccsr_pci __iomem *pci;
>> -
>> - dev = pdev->dev.of_node;
>> -
>> - if (!of_device_is_available(dev)) {
>> - pr_warning("%s: disabled\n", dev->full_name);
>> - return -ENODEV;
>> - }
>> -
>> - pr_debug("Adding PCI host bridge %s\n", dev->full_name);
>> -
>> - /* Fetch host bridge registers address */
>> - if (of_address_to_resource(dev, 0, &rsrc)) {
>> - printk(KERN_WARNING "Can't get pci register base!");
>> - return -ENOMEM;
>> - }
>> -
>> - /* Get bus range if any */
>> - bus_range = of_get_property(dev, "bus-range", &len);
>> - if (bus_range == NULL || len < 2 * sizeof(int))
>> - printk(KERN_WARNING "Can't get bus-range for %s, assume"
>> - " bus 0\n", dev->full_name);
>> -
>> - pci_add_flags(PCI_REASSIGN_ALL_BUS);
>> - hose = pcibios_alloc_controller(dev);
>> - if (!hose)
>> - return -ENOMEM;
>> -
>> - /* set platform device as the parent */
>> - hose->parent = &pdev->dev;
>> - hose->first_busno = bus_range ? bus_range[0] : 0x0;
>> - hose->last_busno = bus_range ? bus_range[1] : 0xff;
>> -
>> - pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
>> - (u64)rsrc.start, (u64)resource_size(&rsrc));
>> -
>> - pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
>> - if (!hose->private_data)
>> - goto no_bridge;
>> -
>> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
>> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
>> -
>> - if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
>> -
>> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> - /* use fsl_indirect_read_config for PCIe */
>> - hose->ops = &fsl_indirect_pcie_ops;
>> - /* For PCIE read HEADER_TYPE to identify controler mode */
>> - early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
>> - if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
>> - goto no_bridge;
>> -
>> - } else {
>> - /* For PCI read PROG to identify controller mode */
>> - early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
>> - if ((progif & 1) == 1)
>> - goto no_bridge;
>> - }
>> -
>> - setup_pci_cmd(hose);
>> -
>> - /* check PCI express link status */
>> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
>> - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
>> - if (fsl_pcie_check_link(hose))
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> - }
>> -
>> - printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>> - "Firmware bus number: %d->%d\n",
>> - (unsigned long long)rsrc.start, hose->first_busno,
>> - hose->last_busno);
>> -
>> - pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
>> - hose, hose->cfg_addr, hose->cfg_data);
>> -
>> - /* Interpret the "ranges" property */
>> - /* This also maps the I/O region and sets isa_io/mem_base */
>> - pci_process_bridge_OF_ranges(hose, dev, is_primary);
>> -
>> - /* Setup PEX window registers */
>> - setup_pci_atmu(hose);
>> -
>> - return 0;
>> -
>> -no_bridge:
>> - iounmap(hose->private_data);
>> - /* unmap cfg_data & cfg_addr separately if not on same page */
>> - if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
>> - ((unsigned long)hose->cfg_addr & PAGE_MASK))
>> - iounmap(hose->cfg_data);
>> - iounmap(hose->cfg_addr);
>> - pcibios_free_controller(hose);
>> - return -ENODEV;
>> -}
>> #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
>>
>> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
>> @@ -1029,26 +590,6 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
>> #endif
>>
>> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>> -static const struct of_device_id pci_ids[] = {
>> - { .compatible = "fsl,mpc8540-pci", },
>> - { .compatible = "fsl,mpc8548-pcie", },
>> - { .compatible = "fsl,mpc8610-pci", },
>> - { .compatible = "fsl,mpc8641-pcie", },
>> - { .compatible = "fsl,qoriq-pcie-v2.1", },
>> - { .compatible = "fsl,qoriq-pcie-v2.2", },
>> - { .compatible = "fsl,qoriq-pcie-v2.3", },
>> - { .compatible = "fsl,qoriq-pcie-v2.4", },
>> - { .compatible = "fsl,qoriq-pcie-v3.0", },
>> -
>> - /*
>> - * The following entries are for compatibility with older device
>> - * trees.
>> - */
>> - { .compatible = "fsl,p1022-pcie", },
>> - { .compatible = "fsl,p4080-pcie", },
>> -
>> - {},
>> -};
>>
>> struct device_node *fsl_pci_primary;
>>
>> @@ -1083,64 +624,4 @@ void fsl_pci_assign_primary(void)
>> }
>> }
>> }
>> -
>> -static int fsl_pci_probe(struct platform_device *pdev)
>> -{
>> - int ret;
>> - struct device_node *node;
>> -
>> - node = pdev->dev.of_node;
>> - ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
>> -
>> - mpc85xx_pci_err_probe(pdev);
>> -
>> - return 0;
>> -}
>> -
>> -#ifdef CONFIG_PM
>> -static int fsl_pci_resume(struct device *dev)
>> -{
>> - struct pci_controller *hose;
>> - struct resource pci_rsrc;
>> -
>> - hose = pci_find_hose_for_OF_device(dev->of_node);
>> - if (!hose)
>> - return -ENODEV;
>> -
>> - if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
>> - dev_err(dev, "Get pci register base failed.");
>> - return -ENODEV;
>> - }
>> -
>> - setup_pci_atmu(hose);
>> -
>> - return 0;
>> -}
>> -
>> -static const struct dev_pm_ops pci_pm_ops = {
>> - .resume = fsl_pci_resume,
>> -};
>> -
>> -#define PCI_PM_OPS (&pci_pm_ops)
>> -
>> -#else
>> -
>> -#define PCI_PM_OPS NULL
>> -
>> -#endif
>> -
>> -static struct platform_driver fsl_pci_driver = {
>> - .driver = {
>> - .name = "fsl-pci",
>> - .pm = PCI_PM_OPS,
>> - .of_match_table = pci_ids,
>> - },
>> - .probe = fsl_pci_probe,
>> -};
>> -
>> -static int __init fsl_pci_init(void)
>> -{
>> - return platform_driver_register(&fsl_pci_driver);
>> -}
>> -arch_initcall(fsl_pci_init);
>> #endif
>> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
>> index 8d455df..ce77aad 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.h
>> +++ b/arch/powerpc/sysdev/fsl_pci.h
>> @@ -21,95 +21,6 @@ struct platform_device;
>> #define PCI_FSL_BRR1 0xbf8
>> #define PCI_FSL_BRR1_VER 0xffff
>>
>> -#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
>> -#define PCIE_LTSSM_L0 0x16 /* L0 state */
>> -#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
>> -#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
>> -#define PIWAR_EN 0x80000000 /* Enable */
>> -#define PIWAR_PF 0x20000000 /* prefetch */
>> -#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
>> -#define PIWAR_READ_SNOOP 0x00050000
>> -#define PIWAR_WRITE_SNOOP 0x00005000
>> -#define PIWAR_SZ_MASK 0x0000003f
>> -
>> -/* PCI/PCI Express outbound window reg */
>> -struct pci_outbound_window_regs {
>> - __be32 potar; /* 0x.0 - Outbound translation address register */
>> - __be32 potear; /* 0x.4 - Outbound translation extended address register */
>> - __be32 powbar; /* 0x.8 - Outbound window base address register */
>> - u8 res1[4];
>> - __be32 powar; /* 0x.10 - Outbound window attributes register */
>> - u8 res2[12];
>> -};
>> -
>> -/* PCI/PCI Express inbound window reg */
>> -struct pci_inbound_window_regs {
>> - __be32 pitar; /* 0x.0 - Inbound translation address register */
>> - u8 res1[4];
>> - __be32 piwbar; /* 0x.8 - Inbound window base address register */
>> - __be32 piwbear; /* 0x.c - Inbound window base extended address register */
>> - __be32 piwar; /* 0x.10 - Inbound window attributes register */
>> - u8 res2[12];
>> -};
>> -
>> -/* PCI/PCI Express IO block registers for 85xx/86xx */
>> -struct ccsr_pci {
>> - __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
>> - __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
>> - __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
>> - __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
>> - __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
>> - __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
>> - __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
>> - u8 res2[4];
>> - __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
>> - __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
>> - __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
>> - __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
>> - u8 res3[3016];
>> - __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
>> - __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
>> -
>> -/* PCI/PCI Express outbound window 0-4
>> - * Window 0 is the default window and is the only window enabled upon reset.
>> - * The default outbound register set is used when a transaction misses
>> - * in all of the other outbound windows.
>> - */
>> - struct pci_outbound_window_regs pow[5];
>> - u8 res14[96];
>> - struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
>> - u8 res6[96];
>> -/* PCI/PCI Express inbound window 3-0
>> - * inbound window 1 supports only a 32-bit base address and does not
>> - * define an inbound window base extended address register.
>> - */
>> - struct pci_inbound_window_regs piw[4];
>> -
>> - __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
>> - u8 res21[4];
>> - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
>> - u8 res22[4];
>> - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
>> - u8 res23[12];
>> - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
>> - u8 res24[4];
>> - __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
>> - __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
>> - __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
>> - __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
>> - u8 res_e38[200];
>> - __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
>> - u8 res_f04[16];
>> - __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
>> -#define PEX_CSR0_LTSSM_MASK 0xFC
>> -#define PEX_CSR0_LTSSM_SHIFT 2
>> -#define PEX_CSR0_LTSSM_L0 0x11
>> - __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
>> - u8 res_f1c[228];
>> -
>> -};
>> -
>> -extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
>> extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
>> extern int mpc83xx_add_bridge(struct device_node *dev);
>> u64 fsl_pci_immrbar_base(struct pci_controller *hose);
>> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/drivers/pci/host/pci-fsl-common.c
>> similarity index 54%
>> copy from arch/powerpc/sysdev/fsl_pci.c
>> copy to drivers/pci/host/pci-fsl-common.c
>> index ccfb50d..69d338b 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.c
>> +++ b/drivers/pci/host/pci-fsl-common.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * MPC83xx/85xx/86xx PCI/PCIE support routing.
>> + * 85xx/86xx/LS PCI/PCIE support routing.
>> *
>> * Copyright 2007-2012 Freescale Semiconductor, Inc.
>> * Copyright 2008-2009 MontaVista Software, Inc.
>> @@ -8,9 +8,6 @@
>> * Recode: ZHANG WEI <wei.zhang@freescale.com>
>> * Rewrite the routing for Frescale PCI and PCI Express
>> * Roy Zang <tie-fei.zang@freescale.com>
>> - * MPC83xx PCI-Express support:
>> - * Tony Li <tony.li@freescale.com>
>> - * Anton Vorontsov <avorontsov@ru.mvista.com>
>> *
>> * This program is free software; you can redistribute it and/or modify it
>> * under the terms of the GNU General Public License as published by the
>> @@ -38,29 +35,6 @@
>> #include <sysdev/fsl_soc.h>
>> #include <sysdev/fsl_pci.h>
>>
>> -static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
>> -
>> -static void quirk_fsl_pcie_header(struct pci_dev *dev)
>> -{
>> - u8 hdr_type;
>> -
>> - /* if we aren't a PCIe don't bother */
>> - if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
>> - return;
>> -
>> - /* if we aren't in host mode don't bother */
>> - pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
>> - if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
>> - return;
>> -
>> - dev->class = PCI_CLASS_BRIDGE_PCI << 8;
>> - fsl_pcie_bus_fixup = 1;
>> - return;
>> -}
>> -
>> -static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
>> - int, int, u32 *);
>> -
>> static int fsl_pcie_check_link(struct pci_controller *hose)
>> {
>> u32 val = 0;
>> @@ -109,29 +83,6 @@ static struct pci_ops fsl_indirect_pcie_ops =
>> .write = indirect_write_config,
>> };
>>
>> -#define MAX_PHYS_ADDR_BITS 40
>> -static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
>> -
>> -static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
>> -{
>> - if (!dev->dma_mask || !dma_supported(dev, dma_mask))
>> - return -EIO;
>> -
>> - /*
>> - * Fixup PCI devices that are able to DMA to above the physical
>> - * address width of the SoC such that we can address any internal
>> - * SoC address from across PCI if needed
>> - */
>> - if ((dev->bus == &pci_bus_type) &&
>> - dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
>> - set_dma_ops(dev, &dma_direct_ops);
>> - set_dma_offset(dev, pci64_dma_offset);
>> - }
>> -
>> - *dev->dma_mask = dma_mask;
>> - return 0;
>> -}
>> -
>> static int setup_one_atmu(struct ccsr_pci __iomem *pci,
>> unsigned int index, const struct resource *res,
>> resource_size_t offset)
>> @@ -417,43 +368,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
>> }
>> }
>>
>> -void fsl_pcibios_fixup_bus(struct pci_bus *bus)
>> -{
>> - struct pci_controller *hose = pci_bus_to_host(bus);
>> - int i, is_pcie = 0, no_link;
>> -
>> - /* The root complex bridge comes up with bogus resources,
>> - * we copy the PHB ones in.
>> - *
>> - * With the current generic PCI code, the PHB bus no longer
>> - * has bus->resource[0..4] set, so things are a bit more
>> - * tricky.
>> - */
>> -
>> - if (fsl_pcie_bus_fixup)
>> - is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
>> - no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
>> -
>> - if (bus->parent == hose->bus && (is_pcie || no_link)) {
>> - for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
>> - struct resource *res = bus->resource[i];
>> - struct resource *par;
>> -
>> - if (!res)
>> - continue;
>> - if (i == 0)
>> - par = &hose->io_resource;
>> - else if (i < 4)
>> - par = &hose->mem_resources[i-1];
>> - else par = NULL;
>> -
>> - res->start = par ? par->start : 0;
>> - res->end = par ? par->end : 0;
>> - res->flags = par ? par->flags : 0;
>> - }
>> - }
>> -}
>> -
>> int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
>> {
>> int len;
>> @@ -560,475 +474,7 @@ no_bridge:
>> pcibios_free_controller(hose);
>> return -ENODEV;
>> }
>> -#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
>> -
>> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
>> -
>> -#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
>> -struct mpc83xx_pcie_priv {
>> - void __iomem *cfg_type0;
>> - void __iomem *cfg_type1;
>> - u32 dev_base;
>> -};
>> -
>> -struct pex_inbound_window {
>> - u32 ar;
>> - u32 tar;
>> - u32 barl;
>> - u32 barh;
>> -};
>> -
>> -/*
>> - * With the convention of u-boot, the PCIE outbound window 0 serves
>> - * as configuration transactions outbound.
>> - */
>> -#define PEX_OUTWIN0_BAR 0xCA4
>> -#define PEX_OUTWIN0_TAL 0xCA8
>> -#define PEX_OUTWIN0_TAH 0xCAC
>> -#define PEX_RC_INWIN_BASE 0xE60
>> -#define PEX_RCIWARn_EN 0x1
>> -
>> -static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
>> -{
>> - struct pci_controller *hose = pci_bus_to_host(bus);
>> -
>> - if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> - /*
>> - * Workaround for the HW bug: for Type 0 configure transactions the
>> - * PCI-E controller does not check the device number bits and just
>> - * assumes that the device number bits are 0.
>> - */
>> - if (bus->number == hose->first_busno ||
>> - bus->primary == hose->first_busno) {
>> - if (devfn & 0xf8)
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> - }
>> -
>> - if (ppc_md.pci_exclude_device) {
>> - if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> - }
>> -
>> - return PCIBIOS_SUCCESSFUL;
>> -}
>> -
>> -static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
>> - unsigned int devfn, int offset)
>> -{
>> - struct pci_controller *hose = pci_bus_to_host(bus);
>> - struct mpc83xx_pcie_priv *pcie = hose->dn->data;
>> - u32 dev_base = bus->number << 24 | devfn << 16;
>> - int ret;
>> -
>> - ret = mpc83xx_pcie_exclude_device(bus, devfn);
>> - if (ret)
>> - return NULL;
>> -
>> - offset &= 0xfff;
>> -
>> - /* Type 0 */
>> - if (bus->number == hose->first_busno)
>> - return pcie->cfg_type0 + offset;
>> -
>> - if (pcie->dev_base == dev_base)
>> - goto mapped;
>> -
>> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
>> -
>> - pcie->dev_base = dev_base;
>> -mapped:
>> - return pcie->cfg_type1 + offset;
>> -}
>> -
>> -static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
>> - int offset, int len, u32 *val)
>> -{
>> - void __iomem *cfg_addr;
>> -
>> - cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
>> - if (!cfg_addr)
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> -
>> - switch (len) {
>> - case 1:
>> - *val = in_8(cfg_addr);
>> - break;
>> - case 2:
>> - *val = in_le16(cfg_addr);
>> - break;
>> - default:
>> - *val = in_le32(cfg_addr);
>> - break;
>> - }
>> -
>> - return PCIBIOS_SUCCESSFUL;
>> -}
>> -
>> -static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
>> - int offset, int len, u32 val)
>> -{
>> - struct pci_controller *hose = pci_bus_to_host(bus);
>> - void __iomem *cfg_addr;
>> -
>> - cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
>> - if (!cfg_addr)
>> - return PCIBIOS_DEVICE_NOT_FOUND;
>> -
>> - /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
>> - if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
>> - val &= 0xffffff00;
>> -
>> - switch (len) {
>> - case 1:
>> - out_8(cfg_addr, val);
>> - break;
>> - case 2:
>> - out_le16(cfg_addr, val);
>> - break;
>> - default:
>> - out_le32(cfg_addr, val);
>> - break;
>> - }
>> -
>> - return PCIBIOS_SUCCESSFUL;
>> -}
>> -
>> -static struct pci_ops mpc83xx_pcie_ops = {
>> - .read = mpc83xx_pcie_read_config,
>> - .write = mpc83xx_pcie_write_config,
>> -};
>> -
>> -static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
>> - struct resource *reg)
>> -{
>> - struct mpc83xx_pcie_priv *pcie;
>> - u32 cfg_bar;
>> - int ret = -ENOMEM;
>> -
>> - pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
>> - if (!pcie)
>> - return ret;
>> -
>> - pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
>> - if (!pcie->cfg_type0)
>> - goto err0;
>> -
>> - cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
>> - if (!cfg_bar) {
>> - /* PCI-E isn't configured. */
>> - ret = -ENODEV;
>> - goto err1;
>> - }
>> -
>> - pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
>> - if (!pcie->cfg_type1)
>> - goto err1;
>> -
>> - WARN_ON(hose->dn->data);
>> - hose->dn->data = pcie;
>> - hose->ops = &mpc83xx_pcie_ops;
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
>> -
>> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
>> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
>> -
>> - if (fsl_pcie_check_link(hose))
>> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
>> -
>> - return 0;
>> -err1:
>> - iounmap(pcie->cfg_type0);
>> -err0:
>> - kfree(pcie);
>> - return ret;
>> -
>> -}
>> -
>> -int __init mpc83xx_add_bridge(struct device_node *dev)
>> -{
>> - int ret;
>> - int len;
>> - struct pci_controller *hose;
>> - struct resource rsrc_reg;
>> - struct resource rsrc_cfg;
>> - const int *bus_range;
>> - int primary;
>> -
>> - is_mpc83xx_pci = 1;
>> -
>> - if (!of_device_is_available(dev)) {
>> - pr_warning("%s: disabled by the firmware.\n",
>> - dev->full_name);
>> - return -ENODEV;
>> - }
>> - pr_debug("Adding PCI host bridge %s\n", dev->full_name);
>> -
>> - /* Fetch host bridge registers address */
>> - if (of_address_to_resource(dev, 0, &rsrc_reg)) {
>> - printk(KERN_WARNING "Can't get pci register base!\n");
>> - return -ENOMEM;
>> - }
>> -
>> - memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
>> -
>> - if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
>> - printk(KERN_WARNING
>> - "No pci config register base in dev tree, "
>> - "using default\n");
>> - /*
>> - * MPC83xx supports up to two host controllers
>> - * one at 0x8500 has config space registers at 0x8300
>> - * one at 0x8600 has config space registers at 0x8380
>> - */
>> - if ((rsrc_reg.start & 0xfffff) == 0x8500)
>> - rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
>> - else if ((rsrc_reg.start & 0xfffff) == 0x8600)
>> - rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
>> - }
>> - /*
>> - * Controller at offset 0x8500 is primary
>> - */
>> - if ((rsrc_reg.start & 0xfffff) == 0x8500)
>> - primary = 1;
>> - else
>> - primary = 0;
>> -
>> - /* Get bus range if any */
>> - bus_range = of_get_property(dev, "bus-range", &len);
>> - if (bus_range == NULL || len < 2 * sizeof(int)) {
>> - printk(KERN_WARNING "Can't get bus-range for %s, assume"
>> - " bus 0\n", dev->full_name);
>> - }
>> -
>> - pci_add_flags(PCI_REASSIGN_ALL_BUS);
>> - hose = pcibios_alloc_controller(dev);
>> - if (!hose)
>> - return -ENOMEM;
>> -
>> - hose->first_busno = bus_range ? bus_range[0] : 0;
>> - hose->last_busno = bus_range ? bus_range[1] : 0xff;
>> -
>> - if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
>> - ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
>> - if (ret)
>> - goto err0;
>> - } else {
>> - setup_indirect_pci(hose, rsrc_cfg.start,
>> - rsrc_cfg.start + 4, 0);
>> - }
>> -
>> - printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
>> - "Firmware bus number: %d->%d\n",
>> - (unsigned long long)rsrc_reg.start, hose->first_busno,
>> - hose->last_busno);
>> -
>> - pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
>> - hose, hose->cfg_addr, hose->cfg_data);
>> -
>> - /* Interpret the "ranges" property */
>> - /* This also maps the I/O region and sets isa_io/mem_base */
>> - pci_process_bridge_OF_ranges(hose, dev, primary);
>> -
>> - return 0;
>> -err0:
>> - pcibios_free_controller(hose);
>> - return ret;
>> -}
>> -#endif /* CONFIG_PPC_83xx */
>> -
>> -u64 fsl_pci_immrbar_base(struct pci_controller *hose)
>> -{
>> -#ifdef CONFIG_PPC_83xx
>> - if (is_mpc83xx_pci) {
>> - struct mpc83xx_pcie_priv *pcie = hose->dn->data;
>> - struct pex_inbound_window *in;
>> - int i;
>> -
>> - /* Walk the Root Complex Inbound windows to match IMMR base */
>> - in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
>> - for (i = 0; i < 4; i++) {
>> - /* not enabled, skip */
>> - if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
>> - continue;
>> -
>> - if (get_immrbase() == in_le32(&in[i].tar))
>> - return (u64)in_le32(&in[i].barh) << 32 |
>> - in_le32(&in[i].barl);
>> - }
>> -
>> - printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
>> - }
>> -#endif
>> -
>> -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>> - if (!is_mpc83xx_pci) {
>> - u32 base;
>> -
>> - pci_bus_read_config_dword(hose->bus,
>> - PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
>> - return base;
>> - }
>> -#endif
>> -
>> - return 0;
>> -}
>>
>> -#ifdef CONFIG_E500
>> -static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
>> -{
>> - unsigned int rd, ra, rb, d;
>> -
>> - rd = get_rt(inst);
>> - ra = get_ra(inst);
>> - rb = get_rb(inst);
>> - d = get_d(inst);
>> -
>> - switch (get_op(inst)) {
>> - case 31:
>> - switch (get_xop(inst)) {
>> - case OP_31_XOP_LWZX:
>> - case OP_31_XOP_LWBRX:
>> - regs->gpr[rd] = 0xffffffff;
>> - break;
>> -
>> - case OP_31_XOP_LWZUX:
>> - regs->gpr[rd] = 0xffffffff;
>> - regs->gpr[ra] += regs->gpr[rb];
>> - break;
>> -
>> - case OP_31_XOP_LBZX:
>> - regs->gpr[rd] = 0xff;
>> - break;
>> -
>> - case OP_31_XOP_LBZUX:
>> - regs->gpr[rd] = 0xff;
>> - regs->gpr[ra] += regs->gpr[rb];
>> - break;
>> -
>> - case OP_31_XOP_LHZX:
>> - case OP_31_XOP_LHBRX:
>> - regs->gpr[rd] = 0xffff;
>> - break;
>> -
>> - case OP_31_XOP_LHZUX:
>> - regs->gpr[rd] = 0xffff;
>> - regs->gpr[ra] += regs->gpr[rb];
>> - break;
>> -
>> - case OP_31_XOP_LHAX:
>> - regs->gpr[rd] = ~0UL;
>> - break;
>> -
>> - case OP_31_XOP_LHAUX:
>> - regs->gpr[rd] = ~0UL;
>> - regs->gpr[ra] += regs->gpr[rb];
>> - break;
>> -
>> - default:
>> - return 0;
>> - }
>> - break;
>> -
>> - case OP_LWZ:
>> - regs->gpr[rd] = 0xffffffff;
>> - break;
>> -
>> - case OP_LWZU:
>> - regs->gpr[rd] = 0xffffffff;
>> - regs->gpr[ra] += (s16)d;
>> - break;
>> -
>> - case OP_LBZ:
>> - regs->gpr[rd] = 0xff;
>> - break;
>> -
>> - case OP_LBZU:
>> - regs->gpr[rd] = 0xff;
>> - regs->gpr[ra] += (s16)d;
>> - break;
>> -
>> - case OP_LHZ:
>> - regs->gpr[rd] = 0xffff;
>> - break;
>> -
>> - case OP_LHZU:
>> - regs->gpr[rd] = 0xffff;
>> - regs->gpr[ra] += (s16)d;
>> - break;
>> -
>> - case OP_LHA:
>> - regs->gpr[rd] = ~0UL;
>> - break;
>> -
>> - case OP_LHAU:
>> - regs->gpr[rd] = ~0UL;
>> - regs->gpr[ra] += (s16)d;
>> - break;
>> -
>> - default:
>> - return 0;
>> - }
>> -
>> - return 1;
>> -}
>> -
>> -static int is_in_pci_mem_space(phys_addr_t addr)
>> -{
>> - struct pci_controller *hose;
>> - struct resource *res;
>> - int i;
>> -
>> - list_for_each_entry(hose, &hose_list, list_node) {
>> - if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
>> - continue;
>> -
>> - for (i = 0; i < 3; i++) {
>> - res = &hose->mem_resources[i];
>> - if ((res->flags & IORESOURCE_MEM) &&
>> - addr >= res->start && addr <= res->end)
>> - return 1;
>> - }
>> - }
>> - return 0;
>> -}
>> -
>> -int fsl_pci_mcheck_exception(struct pt_regs *regs)
>> -{
>> - u32 inst;
>> - int ret;
>> - phys_addr_t addr = 0;
>> -
>> - /* Let KVM/QEMU deal with the exception */
>> - if (regs->msr & MSR_GS)
>> - return 0;
>> -
>> -#ifdef CONFIG_PHYS_64BIT
>> - addr = mfspr(SPRN_MCARU);
>> - addr <<= 32;
>> -#endif
>> - addr += mfspr(SPRN_MCAR);
>> -
>> - if (is_in_pci_mem_space(addr)) {
>> - if (user_mode(regs)) {
>> - pagefault_disable();
>> - ret = get_user(regs->nip, &inst);
>> - pagefault_enable();
>> - } else {
>> - ret = probe_kernel_address(regs->nip, inst);
>> - }
>> -
>> - if (mcheck_handle_load(regs, inst)) {
>> - regs->nip += 4;
>> - return 1;
>> - }
>> - }
>> -
>> - return 0;
>> -}
>> -#endif
>> -
>> -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>> static const struct of_device_id pci_ids[] = {
>> { .compatible = "fsl,mpc8540-pci", },
>> { .compatible = "fsl,mpc8548-pcie", },
>> @@ -1050,40 +496,6 @@ static const struct of_device_id pci_ids[] = {
>> {},
>> };
>>
>> -struct device_node *fsl_pci_primary;
>> -
>> -void fsl_pci_assign_primary(void)
>> -{
>> - struct device_node *np;
>> -
>> - /* Callers can specify the primary bus using other means. */
>> - if (fsl_pci_primary)
>> - return;
>> -
>> - /* If a PCI host bridge contains an ISA node, it's primary. */
>> - np = of_find_node_by_type(NULL, "isa");
>> - while ((fsl_pci_primary = of_get_parent(np))) {
>> - of_node_put(np);
>> - np = fsl_pci_primary;
>> -
>> - if (of_match_node(pci_ids, np) && of_device_is_available(np))
>> - return;
>> - }
>> -
>> - /*
>> - * If there's no PCI host bridge with ISA, arbitrarily
>> - * designate one as primary. This can go away once
>> - * various bugs with primary-less systems are fixed.
>> - */
>> - for_each_matching_node(np, pci_ids) {
>> - if (of_device_is_available(np)) {
>> - fsl_pci_primary = np;
>> - of_node_put(np);
>> - return;
>> - }
>> - }
>> -}
>> -
>> static int fsl_pci_probe(struct platform_device *pdev)
>> {
>> int ret;
>> @@ -1143,4 +555,3 @@ static int __init fsl_pci_init(void)
>> return platform_driver_register(&fsl_pci_driver);
>> }
>> arch_initcall(fsl_pci_init);
>> -#endif
>> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/include/linux/fsl/pci-common.h
>> similarity index 79%
>> copy from arch/powerpc/sysdev/fsl_pci.h
>> copy to include/linux/fsl/pci-common.h
>> index 8d455df..5e4f683 100644
>> --- a/arch/powerpc/sysdev/fsl_pci.h
>> +++ b/include/linux/fsl/pci-common.h
>> @@ -1,5 +1,5 @@
>> /*
>> - * MPC85xx/86xx PCI Express structure define
>> + * MPC85xx/86xx/LS PCI Express structure define
>> *
>> * Copyright 2007,2011 Freescale Semiconductor, Inc
>> *
>> @@ -11,15 +11,8 @@
>> */
>>
>> #ifdef __KERNEL__
>> -#ifndef __POWERPC_FSL_PCI_H
>> -#define __POWERPC_FSL_PCI_H
>> -
>> -struct platform_device;
>> -
>> -
>> -/* FSL PCI controller BRR1 register */
>> -#define PCI_FSL_BRR1 0xbf8
>> -#define PCI_FSL_BRR1_VER 0xffff
>> +#ifndef __PCI_COMMON_H
>> +#define __PCI_COMMON_H
>>
>> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
>> #define PCIE_LTSSM_L0 0x16 /* L0 state */
>> @@ -52,7 +45,7 @@ struct pci_inbound_window_regs {
>> u8 res2[12];
>> };
>>
>> -/* PCI/PCI Express IO block registers for 85xx/86xx */
>> +/* PCI/PCI Express IO block registers for 85xx/86xx/LS */
>> struct ccsr_pci {
>> __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
>> __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
>> @@ -109,33 +102,5 @@ struct ccsr_pci {
>>
>> };
>>
>> -extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
>> -extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
>> -extern int mpc83xx_add_bridge(struct device_node *dev);
>> -u64 fsl_pci_immrbar_base(struct pci_controller *hose);
>> -
>> -extern struct device_node *fsl_pci_primary;
>> -
>> -#ifdef CONFIG_PCI
>> -void fsl_pci_assign_primary(void);
>> -#else
>> -static inline void fsl_pci_assign_primary(void) {}
>> -#endif
>> -
>> -#ifdef CONFIG_EDAC_MPC85XX
>> -int mpc85xx_pci_err_probe(struct platform_device *op);
>> -#else
>> -static inline int mpc85xx_pci_err_probe(struct platform_device *op)
>> -{
>> - return -ENOTSUPP;
>> -}
>> -#endif
>> -
>> -#ifdef CONFIG_FSL_PCI
>> -extern int fsl_pci_mcheck_exception(struct pt_regs *);
>> -#else
>> -static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
>> -#endif
>> -
>> -#endif /* __POWERPC_FSL_PCI_H */
>> +#endif /* __PCI_COMMON_H */
>> #endif /* __KERNEL__ */
>> --
>> 1.8.1.2
>>
>>
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^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Add a debugfs file to read the firmware console
From: Benjamin Herrenschmidt @ 2013-10-09 6:51 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <20131009060613.GC28160@concordia>
On Wed, 2013-10-09 at 17:06 +1100, Michael Ellerman wrote:
> Call it twice.
>
> And you wonder why no one reviews your patches?
Not that easy :-) I had a look at using it and unless I did something
stupid, it wasn't actually that trivial to figure out what arg to pass
it for calling it twice, ie, it didn't simplify the code
significantly ... I had another problem too but I don't remember what
it was. But it could be that I had a very dumb moment...
Cheers,
Ben.
^ permalink raw reply
* [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Yuantian.Tang @ 2013-10-09 6:38 UTC (permalink / raw)
To: galak; +Cc: devicetree, linuxppc-dev, Tang Yuantian
From: Tang Yuantian <yuantian.tang@freescale.com>
The following SoCs will be affected: p2041, p3041, p4080,
p5020, p5040, b4420, b4860, t4240
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
v5:
- refine the binding document
- update the compatible string
v4:
- add binding document
- update compatible string
- update the reg property
v3:
- fix typo
v2:
- add t4240, b4420, b4860 support
- remove pll/4 clock from p2041, p3041 and p5020 board
.../devicetree/bindings/clock/corenet-clock.txt | 111 ++++++++++++++++++++
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 35 +++++++
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 +
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 35 +++++++
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 4 +
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 60 +++++++++++
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 60 +++++++++++
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 4 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 112 +++++++++++++++++++++
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 8 ++
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 42 ++++++++
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 2 +
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 60 +++++++++++
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 4 +
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 85 ++++++++++++++++
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12 +++
17 files changed, 640 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt
new file mode 100644
index 0000000..8efc62d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
@@ -0,0 +1,111 @@
+* Clock Block on Freescale CoreNet Platforms
+
+Freescale CoreNet chips take primary clocking input from the external
+SYSCLK signal. The SYSCLK input (frequency) is multiplied using
+multiple phase locked loops (PLL) to create a variety of frequencies
+which can then be passed to a variety of internal logic, including
+cores and peripheral IP blocks.
+Please refer to the Reference Manual for details.
+
+1. Clock Block Binding
+
+Required properties:
+- compatible: Should include one or more of the following:
+ - "fsl,<chip>-clockgen": for chip specific clock block
+ - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x clock
+- reg: Offset and length of the clock register set
+- clock-frequency: Indicates input clock frequency of clock block.
+ Will be set by u-boot
+
+Recommended properties:
+- #ddress-cells: Specifies the number of cells used to represent
+ physical base addresses. Must be present if the device has
+ sub-nodes and set to 1 if present
+- #size-cells: Specifies the number of cells used to represent
+ the size of an address. Must be present if the device has
+ sub-nodes and set to 1 if present
+
+2. Clock Provider/Consumer Binding
+
+Most of the binding are from the common clock binding[1].
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : Should include one or more of the following:
+ - "fsl,qoriq-core-pll-[1,2].x": Indicates a core PLL clock device
+ - "fsl,qoriq-core-mux-[1,2].x": Indicates a core multiplexer clock
+ device; divided from the core PLL clock
+ - "fixed-clock": From common clock binding; indicates output clock
+ of oscillator
+ - "fsl,qoriq-sysclk-[1,2].x": Indicates input system clock
+- #clock-cells: From common clock binding; indicates the number of
+ output clock. 0 is for one output clock; 1 for more than one clock
+
+Recommended properties:
+- clocks: Should be the phandle of input parent clock
+- clock-names: From common clock binding, indicates the clock name
+- clock-output-names: From common clock binding, indicates the names of
+ output clocks
+- reg: Should be the offset and length of clock block base address.
+ The length should be 4.
+
+Example for clock block and clock provider:
+/ {
+ clockgen: global-utilities@e1000 {
+ compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
+ };
+ }
+
+Example for clock consumer:
+
+/ {
+ cpu0: PowerPC,e5500@0 {
+ ...
+ clocks = <&mux0>;
+ ...
+ };
+ }
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 5a6615d..e910e82 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -86,6 +86,41 @@
clockgen: global-utilities@e1000 {
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+ <&pll1 0>, <&pll1 1>, <&pll1 2>;
+ clock-names = "pll0_0", "pll0_1", "pll0_2",
+ "pll1_0", "pll1_1", "pll1_2";
+ clock-output-names = "cmux0";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 7b4426e..a11126b 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -62,11 +62,13 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c8..5cfcfe4 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -130,6 +130,41 @@
clockgen: global-utilities@e1000 {
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+ <&pll1 0>, <&pll1 1>, <&pll1 2>;
+ clock-names = "pll0_0", "pll0_1", "pll0_2",
+ "pll1_0", "pll1_1", "pll1_2";
+ clock-output-names = "cmux0";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 5263fa4..185a231 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -62,21 +62,25 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
+ clocks = <&mux0>;
next-level-cache = <&L2>;
};
};
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index dc6cc5a..f3f7f65 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -308,6 +308,66 @@
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
+
+ mux2: mux2@40 {
+ #clock-cells = <0>;
+ reg = <0x40 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux2";
+ };
+
+ mux3: mux3@60 {
+ #clock-cells = <0>;
+ reg = <0x60 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux3";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 7a2697d..22f3b14 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -81,6 +81,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
+ clocks = <&mux0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
+ clocks = <&mux1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
+ clocks = <&mux2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
+ clocks = <&mux3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 3fa1e22..9bab9c9 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -335,6 +335,66 @@
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
+
+ mux2: mux2@40 {
+ #clock-cells = <0>;
+ reg = <0x40 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux2";
+ };
+
+ mux3: mux3@60 {
+ #clock-cells = <0>;
+ reg = <0x60 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux3";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index c9ca2c3..468e8be 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -82,6 +82,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
+ clocks = <&mux0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
@@ -90,6 +91,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
+ clocks = <&mux1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
@@ -98,6 +100,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
+ clocks = <&mux2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
@@ -106,6 +109,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
+ clocks = <&mux3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7..2108269 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -355,6 +355,118 @@
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ pll2: pll2@840 {
+ #clock-cells = <1>;
+ reg = <0x840 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll2", "pll2-div2";
+ };
+
+ pll3: pll3@860 {
+ #clock-cells = <1>;
+ reg = <0x860 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll3", "pll3-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
+
+ mux2: mux2@40 {
+ #clock-cells = <0>;
+ reg = <0x40 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux2";
+ };
+
+ mux3: mux3@60 {
+ #clock-cells = <0>;
+ reg = <0x60 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux3";
+ };
+
+ mux4: mux4@80 {
+ #clock-cells = <0>;
+ reg = <0x80 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+ clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+ clock-output-names = "cmux4";
+ };
+
+ mux5: mux5@a0 {
+ #clock-cells = <0>;
+ reg = <0xa0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+ clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+ clock-output-names = "cmux5";
+ };
+
+ mux6: mux6@c0 {
+ #clock-cells = <0>;
+ reg = <0xc0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+ clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+ clock-output-names = "cmux6";
+ };
+
+ mux7: mux7@e0 {
+ #clock-cells = <0>;
+ reg = <0xe0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
+ clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
+ clock-output-names = "cmux7";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 493d9a0..0040b5a 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -81,6 +81,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
+ clocks = <&mux0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
+ clocks = <&mux1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
+ clocks = <&mux2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
+ clocks = <&mux3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
@@ -113,6 +117,7 @@
cpu4: PowerPC,e500mc@4 {
device_type = "cpu";
reg = <4>;
+ clocks = <&mux4>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
next-level-cache = <&cpc>;
@@ -121,6 +126,7 @@
cpu5: PowerPC,e500mc@5 {
device_type = "cpu";
reg = <5>;
+ clocks = <&mux5>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
next-level-cache = <&cpc>;
@@ -129,6 +135,7 @@
cpu6: PowerPC,e500mc@6 {
device_type = "cpu";
reg = <6>;
+ clocks = <&mux6>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
next-level-cache = <&cpc>;
@@ -137,6 +144,7 @@
cpu7: PowerPC,e500mc@7 {
device_type = "cpu";
reg = <7>;
+ clocks = <&mux7>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index bc3ae5a..e09f8cd 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -340,6 +340,48 @@
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 8df47fc..fe1a2e6 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -88,6 +88,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
+ clocks = <&mux0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
@@ -96,6 +97,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
+ clocks = <&mux1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index a91897f..109f132 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -300,6 +300,66 @@
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux1";
+ };
+
+ mux2: mux2@40 {
+ #clock-cells = <0>;
+ reg = <0x40 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux2";
+ };
+
+ mux3: mux3@60 {
+ #clock-cells = <0>;
+ reg = <0x60 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
+ clock-output-names = "cmux3";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 40ca943..3674686 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,6 +81,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
+ clocks = <&mux0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
+ clocks = <&mux1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
+ clocks = <&mux2>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
+ clocks = <&mux3>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 510afa3..d45434f 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -370,6 +370,91 @@
clockgen: global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ }
+
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+ };
+
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+ };
+
+ pll2: pll2@840 {
+ #clock-cells = <1>;
+ reg = <0x840 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll2", "pll2-div2", "pll2-div4";
+ };
+
+ pll3: pll3@860 {
+ #clock-cells = <1>;
+ reg = <0x860 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll3", "pll3-div2", "pll3-div4";
+ };
+
+ pll4: pll4@880 {
+ #clock-cells = <1>;
+ reg = <0x880 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll4", "pll4-div2", "pll4-div4";
+ };
+
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+ <&pll1 0>, <&pll1 1>, <&pll1 2>,
+ <&pll2 0>, <&pll2 1>, <&pll2 2>;
+ clock-names = "pll0_0", "pll0_1", "pll0_2",
+ "pll1_0", "pll1_1", "pll1_2",
+ "pll2_0", "pll2_1", "pll2_2";
+ clock-output-names = "cmux0";
+ };
+
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
+ <&pll1 0>, <&pll1 1>, <&pll1 2>,
+ <&pll2 0>, <&pll2 1>, <&pll2 2>;
+ clock-names = "pll0_0", "pll0_1", "pll0_2",
+ "pll1_0", "pll1_1", "pll1_2",
+ "pll2_0", "pll2_1", "pll2_2";
+ clock-output-names = "cmux1";
+ };
+
+ mux2: mux2@40 {
+ #clock-cells = <0>;
+ reg = <0x40 0x4>;
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
+ <&pll4 0>, <&pll4 1>, <&pll4 2>;
+ clock-names = "pll3_0", "pll3_1", "pll3_2",
+ "pll4_0", "pll4_1", "pll4_2";
+ clock-output-names = "cmux2";
+ };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index a93c55a..0b8ccc5 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -67,61 +67,73 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
+ clocks = <&mux0>;
next-level-cache = <&L2_1>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
+ clocks = <&mux0>;
next-level-cache = <&L2_1>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
+ clocks = <&mux0>;
next-level-cache = <&L2_1>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
+ clocks = <&mux0>;
next-level-cache = <&L2_1>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
+ clocks = <&mux1>;
next-level-cache = <&L2_2>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
+ clocks = <&mux1>;
next-level-cache = <&L2_2>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
+ clocks = <&mux1>;
next-level-cache = <&L2_2>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
+ clocks = <&mux1>;
next-level-cache = <&L2_2>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
+ clocks = <&mux2>;
next-level-cache = <&L2_3>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
+ clocks = <&mux2>;
next-level-cache = <&L2_3>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
+ clocks = <&mux2>;
next-level-cache = <&L2_3>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
+ clocks = <&mux2>;
next-level-cache = <&L2_3>;
};
};
--
1.8.0
^ permalink raw reply related
* Re: [PATCH] powerpc/powernv: Add a debugfs file to read the firmware console
From: Michael Ellerman @ 2013-10-09 6:06 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1381292601.645.258.camel@pasglop>
On Wed, Oct 09, 2013 at 03:23:21PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2013-10-09 at 14:23 +1100, Michael Ellerman wrote:
> > On Tue, Oct 08, 2013 at 06:46:40PM +1100, Benjamin Herrenschmidt wrote:
> > > With OPALv3, the firmware can provide the address of it's internal console
> > > to Linux, which we can then display using debugfs. This is handy for
> > > diagnostics and debugging.
> > >
> > > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > > ---
> > >
> > > diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
> > > index 2911abe..10d7894 100644
> > > --- a/arch/powerpc/platforms/powernv/opal.c
> > > +++ b/arch/powerpc/platforms/powernv/opal.c
> > > @@ -17,6 +17,8 @@
> > > #include <linux/interrupt.h>
> > > #include <linux/notifier.h>
> > > #include <linux/slab.h>
> > > +#include <linux/debugfs.h>
> > > +#include <linux/uaccess.h>
> > > #include <asm/opal.h>
> > > #include <asm/firmware.h>
> > >
> > > @@ -27,6 +29,21 @@ struct opal {
> > > u64 entry;
> > > } opal;
> > >
> > > +/* OPAL in-memory console */
> >
> > It might be nice to point out that the format of the struct is defined
> > by OPAL and must be in sync with what OPAL is using.
>
> Yes, we could move the structure definition to opal.h...
>
> > > +struct memcons {
> > > + uint64_t magic;
> >
> > u64 ?
>
> Who cares ?
That's what we use in the kernel. But no I don't care.
> > > +#define MEMCONS_MAGIC 0x6630696567726173
> > > + uint64_t obuf_phys;
> > > + uint64_t ibuf_phys;
> > > + uint32_t obuf_size;
> > > + uint32_t ibuf_size;
> > > + uint32_t out_pos;
> > > +#define MEMCONS_OUT_POS_WRAP 0x80000000u
> > > +#define MEMCONS_OUT_POS_MASK 0x00ffffffu
> >
> > Where does this come from?
>
> My a** :-) I made it up as I wrote the OPAL side one, why ?
...
> > > + uint32_t in_prod;
> > > + uint32_t in_cons;
> > > +};
> >
> > Should it be packed?
>
> Nope, no need. It's all nice and naturally aligned.
Sure, that's obvious.
> > > @@ -369,6 +386,90 @@ static irqreturn_t opal_interrupt(int irq, void *data)
> > > return IRQ_HANDLED;
> > > }
> > >
> > > +#ifdef CONFIG_DEBUG_FS
> > > +static ssize_t opal_memcons_read(struct file *file, char __user *to,
> > > + size_t count, loff_t *ppos)
> > > +{
> > > + struct memcons *mc = file->private_data;
> > > + size_t available, ret, chunk0, chunk1, lcount;
> > > + const char *start, *conbuf = __va(mc->obuf_phys);
> > > + loff_t opos, pos;
> > > +
> > > + /*
> > > + * Find out how much is in the buffer. If it has wrapped
> > > + * the whole buffer, else just the beginning. It has wrapped
> > > + * if the next character is not \0
> > > + */
> > > + if (mc->out_pos & MEMCONS_OUT_POS_WRAP) {
> > > + available = mc->obuf_size;
> > > + chunk1 = mc->out_pos & MEMCONS_OUT_POS_MASK;
> > > + start = conbuf + chunk1;
> > > + chunk0 = mc->obuf_size - chunk1;
> > > + } else {
> > > + available = mc->out_pos;
> > > + start = conbuf;
> > > + chunk0 = available;
> > > + chunk1 = 0;
> > > + }
> >
> > Surely simple_read_from_buffer() could make some of this simpler?
>
> If you can find a way to make it deal with a ring buffer...
Call it twice.
And you wonder why no one reviews your patches?
cheers
^ permalink raw reply
* Re: [PATCH] powerpc, perf: Configure BHRB filter before enabling PMU interrupts
From: Michael Ellerman @ 2013-10-09 6:03 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linuxppc-dev, mikey
In-Reply-To: <5254DFA8.2050100@linux.vnet.ibm.com>
On Wed, Oct 09, 2013 at 10:16:32AM +0530, Anshuman Khandual wrote:
> On 10/09/2013 06:51 AM, Michael Ellerman wrote:
> > On Tue, Oct 08, 2013 at 12:51:18PM +0530, Anshuman Khandual wrote:
> >> On 10/08/2013 09:51 AM, Michael Ellerman wrote:
> >>> On Mon, Oct 07, 2013 at 10:00:26AM +0530, Anshuman Khandual wrote:
> >>>> Right now the `config_bhrb` PMU specific call happens after write_mmcr0
> >>>> which actually enables the PMU for event counting and interrupt. So
> >>>> there is a small window of time where the PMU and BHRB runs without the
> >>>> required HW branch filter (if any) enabled in BHRB. This can cause some
> >>>> of the branch samples to be collected through BHRB without any filter
> >>>> being applied and hence affecting the correctness of the results. This
> >>>> patch moves the BHRB config function call before enabling the interrupts.
> >>>
> >>> Patch looks good.
> >>>
> >>> But it reminds me I have an item in my TODO list:
> >>> - "Why can't config_bhrb() be done in compute_mmcr()" ?
> >>>
> >>
> >> compute_mmcr() function deals with generic MMCR* configs for normal PMU
> >> events. Even if BHRB config touches MMCRA register, it's configuration
> >> does not interfere with the PMU config for general events. So its best
> >> to keep them separate.
> >
> > I'm unconvinced. If they'd been together to begin with this bug never
> > would have happened.
>
> This is an ordering of configuration problem. Putting them together in the
> same function does not rule out the chances of this ordering problem. Could
> you please kindly explain how this could have been avoided ?
The existing code already makes sure to write MMCRA before MMCR0.
cheers
^ permalink raw reply
* [PATCH] powerpc: Added __cmpdi2 for signed 64bit comparision
From: Bharat Bhushan @ 2013-10-09 5:11 UTC (permalink / raw)
To: scottwood, linuxppc-dev, benh; +Cc: Bharat Bhushan
This was missing on powerpc and I am getting compilation error
drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kernel/misc_32.S | 14 ++++++++++++++
arch/powerpc/kernel/ppc_ksyms.c | 2 ++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 777d999..7c0eec2 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -644,6 +644,20 @@ _GLOBAL(__lshrdi3)
blr
/*
+ * 64-bit comparison: __cmpdi2(s64 a, s64 b)
+ * Returns 0 if a < b, 1 if a == b, 2 if a > b.
+ */
+_GLOBAL(__cmpdi2)
+ cmpw r3,r5
+ li r3,1
+ bne 1f
+ cmplw r4,r6
+ beqlr
+1: li r3,0
+ bltlr
+ li r3,2
+ blr
+/*
* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
* Returns 0 if a < b, 1 if a == b, 2 if a > b.
*/
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 21646db..5674c00 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -143,6 +143,8 @@ EXPORT_SYMBOL(__ashldi3);
EXPORT_SYMBOL(__lshrdi3);
int __ucmpdi2(unsigned long long, unsigned long long);
EXPORT_SYMBOL(__ucmpdi2);
+int __cmpdi2(long long, long long);
+EXPORT_SYMBOL(__cmpdi2);
#endif
long long __bswapdi2(long long);
EXPORT_SYMBOL(__bswapdi2);
--
1.7.0.4
^ permalink raw reply related
* RE: [PATCH 1/4] powerpc: Added __cmpdi2 for signed 64bit comparision
From: Bhushan Bharat-R65777 @ 2013-10-09 5:17 UTC (permalink / raw)
To: Bhushan Bharat-R65777, Wood Scott-B07421,
linuxppc-dev@lists.ozlabs.org, benh@kernel.crashing.org
In-Reply-To: <1381295322-7197-1-git-send-email-Bharat.Bhushan@freescale.com>
Oops it came as 1/4,
I am sorry, please ignore this
Thanks
-Bharat
> -----Original Message-----
> From: Bhushan Bharat-R65777
> Sent: Wednesday, October 09, 2013 10:39 AM
> To: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; benh@kernel.crashin=
g.org
> Cc: Bhushan Bharat-R65777; Bhushan Bharat-R65777
> Subject: [PATCH 1/4] powerpc: Added __cmpdi2 for signed 64bit comparision
>=20
> This was missing on powerpc and I am getting compilation error
> drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
> drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
>=20
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> ---
> arch/powerpc/kernel/misc_32.S | 14 ++++++++++++++
> arch/powerpc/kernel/ppc_ksyms.c | 2 ++
> 2 files changed, 16 insertions(+), 0 deletions(-)
>=20
> diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.=
S index
> 777d999..7c0eec2 100644
> --- a/arch/powerpc/kernel/misc_32.S
> +++ b/arch/powerpc/kernel/misc_32.S
> @@ -644,6 +644,20 @@ _GLOBAL(__lshrdi3)
> blr
>=20
> /*
> + * 64-bit comparison: __cmpdi2(s64 a, s64 b)
> + * Returns 0 if a < b, 1 if a =3D=3D b, 2 if a > b.
> + */
> +_GLOBAL(__cmpdi2)
> + cmpw r3,r5
> + li r3,1
> + bne 1f
> + cmplw r4,r6
> + beqlr
> +1: li r3,0
> + bltlr
> + li r3,2
> + blr
> +/*
> * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
> * Returns 0 if a < b, 1 if a =3D=3D b, 2 if a > b.
> */
> diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ks=
yms.c
> index 21646db..5674c00 100644
> --- a/arch/powerpc/kernel/ppc_ksyms.c
> +++ b/arch/powerpc/kernel/ppc_ksyms.c
> @@ -143,6 +143,8 @@ EXPORT_SYMBOL(__ashldi3); EXPORT_SYMBOL(__lshrdi3); =
int
> __ucmpdi2(unsigned long long, unsigned long long); EXPORT_SYMBOL(__ucmpd=
i2);
> +int __cmpdi2(long long, long long);
> +EXPORT_SYMBOL(__cmpdi2);
> #endif
> long long __bswapdi2(long long);
> EXPORT_SYMBOL(__bswapdi2);
> --
> 1.7.0.4
^ permalink raw reply
* [PATCH 1/4] powerpc: Added __cmpdi2 for signed 64bit comparision
From: Bharat Bhushan @ 2013-10-09 5:08 UTC (permalink / raw)
To: scottwood, linuxppc-dev, benh; +Cc: Bharat Bhushan
This was missing on powerpc and I am getting compilation error
drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
drivers/vfio/pci/vfio_pci_rdwr.c:193: undefined reference to `__cmpdi2'
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
---
arch/powerpc/kernel/misc_32.S | 14 ++++++++++++++
arch/powerpc/kernel/ppc_ksyms.c | 2 ++
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 777d999..7c0eec2 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -644,6 +644,20 @@ _GLOBAL(__lshrdi3)
blr
/*
+ * 64-bit comparison: __cmpdi2(s64 a, s64 b)
+ * Returns 0 if a < b, 1 if a == b, 2 if a > b.
+ */
+_GLOBAL(__cmpdi2)
+ cmpw r3,r5
+ li r3,1
+ bne 1f
+ cmplw r4,r6
+ beqlr
+1: li r3,0
+ bltlr
+ li r3,2
+ blr
+/*
* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
* Returns 0 if a < b, 1 if a == b, 2 if a > b.
*/
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 21646db..5674c00 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -143,6 +143,8 @@ EXPORT_SYMBOL(__ashldi3);
EXPORT_SYMBOL(__lshrdi3);
int __ucmpdi2(unsigned long long, unsigned long long);
EXPORT_SYMBOL(__ucmpdi2);
+int __cmpdi2(long long, long long);
+EXPORT_SYMBOL(__cmpdi2);
#endif
long long __bswapdi2(long long);
EXPORT_SYMBOL(__bswapdi2);
--
1.7.0.4
^ permalink raw reply related
* RE: [PATCH 1/7] powerpc: Add interface to get msi region information
From: Bhushan Bharat-R65777 @ 2013-10-09 4:47 UTC (permalink / raw)
To: Wood Scott-B07421
Cc: agraf@suse.de, joro@8bytes.org, linux-kernel@vger.kernel.org,
iommu@lists.linux-foundation.org, alex.williamson@redhat.com,
linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1381273037.7979.298.camel@snotra.buserror.net>
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IGF0IDAuDQoNCldpbGwgY29ycmVjdCB0aGlzDQoNClRoYW5rcw0KLUJoYXJhdA0KDQo+IA0KPiAt
U2NvdHQNCj4gDQoNCg==
^ permalink raw reply
* Re: [PATCH] powerpc, perf: Configure BHRB filter before enabling PMU interrupts
From: Anshuman Khandual @ 2013-10-09 4:46 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, mikey
In-Reply-To: <20131009012130.GA23780@concordia>
On 10/09/2013 06:51 AM, Michael Ellerman wrote:
> On Tue, Oct 08, 2013 at 12:51:18PM +0530, Anshuman Khandual wrote:
>> On 10/08/2013 09:51 AM, Michael Ellerman wrote:
>>> On Mon, Oct 07, 2013 at 10:00:26AM +0530, Anshuman Khandual wrote:
>>>> Right now the `config_bhrb` PMU specific call happens after write_mmcr0
>>>> which actually enables the PMU for event counting and interrupt. So
>>>> there is a small window of time where the PMU and BHRB runs without the
>>>> required HW branch filter (if any) enabled in BHRB. This can cause some
>>>> of the branch samples to be collected through BHRB without any filter
>>>> being applied and hence affecting the correctness of the results. This
>>>> patch moves the BHRB config function call before enabling the interrupts.
>>>
>>> Patch looks good.
>>>
>>> But it reminds me I have an item in my TODO list:
>>> - "Why can't config_bhrb() be done in compute_mmcr()" ?
>>>
>>
>> compute_mmcr() function deals with generic MMCR* configs for normal PMU
>> events. Even if BHRB config touches MMCRA register, it's configuration
>> does not interfere with the PMU config for general events. So its best
>> to keep them separate.
>
> I'm unconvinced. If they'd been together to begin with this bug never
> would have happened.
This is an ordering of configuration problem. Putting them together in the
same function does not rule out the chances of this ordering problem. Could
you please kindly explain how this could have been avoided ?
>
> And there's the added overhead of another indirect function call.
>
This overhead should be minimal given the fact that we already call so
many PMU specific indirect calls. BHRB is a different part of the PMU
hardware, so a separate call for this purpose is not a bad idea. AFAIK,
X86 does that too for LBR. But yes it is debatable.
>> Besides, we can always look at these code consolidation
>> issues in future.
>
> The future is now.
What I meant was functional correctness has always more priority than
code consolidation efforts. Yes I will look into this after book3s
software branch filtering code has been merged.
>
>> But this patch solves a problem which is happening right now.
>
> Sure, I'm not saying we shouldn't merge it as a fix. But I think we
> should do the cleanup to move it into compute_mmcr() for 3.13.
yeah that sounds reasonable.
Regards
Anshuman
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Benjamin Herrenschmidt @ 2013-10-09 4:24 UTC (permalink / raw)
To: H. Peter Anvin
Cc: linux-mips, VMware, Inc., linux-pci, linux-nvme, linux-ide,
linux-s390, Andy King, linux-scsi, linux-rdma, x86,
Alexander Gordeev, iss_storagedev, linux-driver, Tejun Heo,
Bjorn Helgaas, Dan Williams, Jon Mason, Ingo Molnar,
Solarflare linux maintainers, netdev, linux-kernel, Ralf Baechle,
e1000-devel, Martin Schwidefsky, linux390, linuxppc-dev
In-Reply-To: <5254D397.9030307@zytor.com>
On Tue, 2013-10-08 at 20:55 -0700, H. Peter Anvin wrote:
> Why not add a minimum number to pci_enable_msix(), i.e.:
>
> pci_enable_msix(pdev, msix_entries, nvec, minvec)
>
> ... which means "nvec" is the number of interrupts *requested*, and
> "minvec" is the minimum acceptable number (otherwise fail).
Which is exactly what Ben (the other Ben :-) suggested and that I
supports...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Add a debugfs file to read the firmware console
From: Benjamin Herrenschmidt @ 2013-10-09 4:23 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <20131009032314.GD23780@concordia>
On Wed, 2013-10-09 at 14:23 +1100, Michael Ellerman wrote:
> On Tue, Oct 08, 2013 at 06:46:40PM +1100, Benjamin Herrenschmidt wrote:
> > With OPALv3, the firmware can provide the address of it's internal console
> > to Linux, which we can then display using debugfs. This is handy for
> > diagnostics and debugging.
> >
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> >
> > diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
> > index 2911abe..10d7894 100644
> > --- a/arch/powerpc/platforms/powernv/opal.c
> > +++ b/arch/powerpc/platforms/powernv/opal.c
> > @@ -17,6 +17,8 @@
> > #include <linux/interrupt.h>
> > #include <linux/notifier.h>
> > #include <linux/slab.h>
> > +#include <linux/debugfs.h>
> > +#include <linux/uaccess.h>
> > #include <asm/opal.h>
> > #include <asm/firmware.h>
> >
> > @@ -27,6 +29,21 @@ struct opal {
> > u64 entry;
> > } opal;
> >
> > +/* OPAL in-memory console */
>
> It might be nice to point out that the format of the struct is defined
> by OPAL and must be in sync with what OPAL is using.
Yes, we could move the structure definition to opal.h...
> > +struct memcons {
> > + uint64_t magic;
>
> u64 ?
Who cares ? Especially if it goes into opal.h it should stick to the
types used in that file.
> > +#define MEMCONS_MAGIC 0x6630696567726173
> > + uint64_t obuf_phys;
> > + uint64_t ibuf_phys;
> > + uint32_t obuf_size;
> > + uint32_t ibuf_size;
> > + uint32_t out_pos;
> > +#define MEMCONS_OUT_POS_WRAP 0x80000000u
> > +#define MEMCONS_OUT_POS_MASK 0x00ffffffu
>
> Where does this come from?
My a** :-) I made it up as I wrote the OPAL side one, why ?
> > + uint32_t in_prod;
> > + uint32_t in_cons;
> > +};
>
> Should it be packed?
Nope, no need. It's all nice and naturally aligned.
> > @@ -369,6 +386,90 @@ static irqreturn_t opal_interrupt(int irq, void *data)
> > return IRQ_HANDLED;
> > }
> >
> > +#ifdef CONFIG_DEBUG_FS
> > +static ssize_t opal_memcons_read(struct file *file, char __user *to,
> > + size_t count, loff_t *ppos)
> > +{
> > + struct memcons *mc = file->private_data;
> > + size_t available, ret, chunk0, chunk1, lcount;
> > + const char *start, *conbuf = __va(mc->obuf_phys);
> > + loff_t opos, pos;
> > +
> > + /*
> > + * Find out how much is in the buffer. If it has wrapped
> > + * the whole buffer, else just the beginning. It has wrapped
> > + * if the next character is not \0
> > + */
> > + if (mc->out_pos & MEMCONS_OUT_POS_WRAP) {
> > + available = mc->obuf_size;
> > + chunk1 = mc->out_pos & MEMCONS_OUT_POS_MASK;
> > + start = conbuf + chunk1;
> > + chunk0 = mc->obuf_size - chunk1;
> > + } else {
> > + available = mc->out_pos;
> > + start = conbuf;
> > + chunk0 = available;
> > + chunk1 = 0;
> > + }
>
> Surely simple_read_from_buffer() could make some of this simpler?
If you can find a way to make it deal with a ring buffer...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: H. Peter Anvin @ 2013-10-09 3:55 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar, linux-pci,
iss_storagedev, linux-driver, Tejun Heo, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
linux390, linuxppc-dev
In-Reply-To: <cover.1380703262.git.agordeev@redhat.com>
On 10/02/2013 03:29 AM, Alexander Gordeev wrote:
>
> As result, device drivers will cease to use the overcomplicated
> repeated fallbacks technique and resort to a straightforward
> pattern - determine the number of MSI/MSI-X interrupts required
> before calling pci_enable_msi_block() and pci_enable_msix()
> interfaces:
>
>
> rc = pci_msix_table_size(adapter->pdev);
> if (rc < 0)
> return rc;
>
> nvec = min(nvec, rc);
> if (nvec < FOO_DRIVER_MINIMUM_NVEC) {
> return -ENOSPC;
>
> for (i = 0; i < nvec; i++)
> adapter->msix_entries[i].entry = i;
>
> rc = pci_enable_msix(adapter->pdev,
> adapter->msix_entries, nvec);
> return rc;
>
Why not add a minimum number to pci_enable_msix(), i.e.:
pci_enable_msix(pdev, msix_entries, nvec, minvec)
... which means "nvec" is the number of interrupts *requested*, and
"minvec" is the minimum acceptable number (otherwise fail).
-hpa
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Add a debugfs file to read the firmware console
From: Michael Ellerman @ 2013-10-09 3:23 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1381218400.645.204.camel@pasglop>
On Tue, Oct 08, 2013 at 06:46:40PM +1100, Benjamin Herrenschmidt wrote:
> With OPALv3, the firmware can provide the address of it's internal console
> to Linux, which we can then display using debugfs. This is handy for
> diagnostics and debugging.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
> index 2911abe..10d7894 100644
> --- a/arch/powerpc/platforms/powernv/opal.c
> +++ b/arch/powerpc/platforms/powernv/opal.c
> @@ -17,6 +17,8 @@
> #include <linux/interrupt.h>
> #include <linux/notifier.h>
> #include <linux/slab.h>
> +#include <linux/debugfs.h>
> +#include <linux/uaccess.h>
> #include <asm/opal.h>
> #include <asm/firmware.h>
>
> @@ -27,6 +29,21 @@ struct opal {
> u64 entry;
> } opal;
>
> +/* OPAL in-memory console */
It might be nice to point out that the format of the struct is defined
by OPAL and must be in sync with what OPAL is using.
> +struct memcons {
> + uint64_t magic;
u64 ?
> +#define MEMCONS_MAGIC 0x6630696567726173
> + uint64_t obuf_phys;
> + uint64_t ibuf_phys;
> + uint32_t obuf_size;
> + uint32_t ibuf_size;
> + uint32_t out_pos;
> +#define MEMCONS_OUT_POS_WRAP 0x80000000u
> +#define MEMCONS_OUT_POS_MASK 0x00ffffffu
Where does this come from?
> + uint32_t in_prod;
> + uint32_t in_cons;
> +};
Should it be packed?
> @@ -369,6 +386,90 @@ static irqreturn_t opal_interrupt(int irq, void *data)
> return IRQ_HANDLED;
> }
>
> +#ifdef CONFIG_DEBUG_FS
> +static ssize_t opal_memcons_read(struct file *file, char __user *to,
> + size_t count, loff_t *ppos)
> +{
> + struct memcons *mc = file->private_data;
> + size_t available, ret, chunk0, chunk1, lcount;
> + const char *start, *conbuf = __va(mc->obuf_phys);
> + loff_t opos, pos;
> +
> + /*
> + * Find out how much is in the buffer. If it has wrapped
> + * the whole buffer, else just the beginning. It has wrapped
> + * if the next character is not \0
> + */
> + if (mc->out_pos & MEMCONS_OUT_POS_WRAP) {
> + available = mc->obuf_size;
> + chunk1 = mc->out_pos & MEMCONS_OUT_POS_MASK;
> + start = conbuf + chunk1;
> + chunk0 = mc->obuf_size - chunk1;
> + } else {
> + available = mc->out_pos;
> + start = conbuf;
> + chunk0 = available;
> + chunk1 = 0;
> + }
Surely simple_read_from_buffer() could make some of this simpler?
cheers
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Mark Lord @ 2013-10-09 1:55 UTC (permalink / raw)
To: Alexander Gordeev, linux-kernel
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Linus Torvalds,
Ingo Molnar, linux-pci, iss_storagedev, linux-driver, Tejun Heo,
Bjorn Helgaas, Dan Williams, Jon Mason,
Solarflare linux maintainers, netdev, Ralf Baechle, e1000-devel,
Martin Schwidefsky, linux390, linuxppc-dev
In-Reply-To: <cover.1380703262.git.agordeev@redhat.com>
On 13-10-02 06:29 AM, Alexander Gordeev wrote:
..
> This update converts pci_enable_msix() and pci_enable_msi_block()
> interfaces to canonical kernel functions and makes them return a
> error code in case of failure or 0 in case of success.
Rather than silently break dozens of drivers in mysterious ways,
please invent new function names for the replacements to the
existing pci_enable_msix() and pci_enable_msi_block() functions.
That way, both in-tree and out-of-tree drivers will notice the API change,
rather than having it go unseen and just failing for unknown reasons.
Thanks.
^ permalink raw reply
* Re: [PATCH RFC 00/77] Re-design MSI/MSI-X interrupts enablement pattern
From: Michael Ellerman @ 2013-10-09 1:34 UTC (permalink / raw)
To: Alexander Gordeev
Cc: linux-mips, VMware, Inc., linux-nvme, linux-ide, linux-s390,
Andy King, linux-scsi, linux-rdma, x86, Ingo Molnar, linux-pci,
iss_storagedev, linux-driver, Tejun Heo, Bjorn Helgaas,
Dan Williams, Jon Mason, Solarflare linux maintainers, netdev,
linux-kernel, Ralf Baechle, e1000-devel, Martin Schwidefsky,
linux390, linuxppc-dev
In-Reply-To: <20131008073301.GC10669@dhcp-26-207.brq.redhat.com>
On Tue, Oct 08, 2013 at 09:33:02AM +0200, Alexander Gordeev wrote:
> On Tue, Oct 08, 2013 at 03:33:30PM +1100, Michael Ellerman wrote:
> > On Wed, Oct 02, 2013 at 12:29:04PM +0200, Alexander Gordeev wrote:
> > > This technique proved to be confusing and error-prone. Vast share
> > > of device drivers simply fail to follow the described guidelines.
> >
> > To clarify "Vast share of device drivers":
> >
> > - 58 drivers call pci_enable_msix()
> > - 24 try a single allocation and then fallback to MSI/LSI
> > - 19 use the loop style allocation as above
> > - 14 try an allocation, and if it fails retry once
> > - 1 incorrectly continues when pci_enable_msix() returns > 0
> >
> > So 33 drivers (> 50%) successfully make use of the "confusing and
> > error-prone" return value.
>
> Ok, you caught me - 'vast share' is incorrect and is a subject to
> rewording. But out of 19/58 how many drivers tested fallbacks on the
> real hardware? IOW, which drivers are affected by the pSeries quota?
It's not 19/58, it's 33/58.
As to how many we care about on powerpc I can't say, so you have a point
there. But I still think the interface is not actually that terrible.
cheers
^ permalink raw reply
* Re: [PATCH 5/9][v5] powerpc: implement is_instr_load_store().
From: Michael Ellerman @ 2013-10-09 1:27 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: linux-kernel, Stephane Eranian, linuxppc-dev, Paul Mackerras,
Arnaldo Carvalho de Melo, Anshuman Khandual
In-Reply-To: <1381280599.15322.1.camel@concordia>
On Wed, Oct 09, 2013 at 12:03:19PM +1100, Michael Ellerman wrote:
> On Tue, 2013-10-08 at 12:31 -0700, Sukadev Bhattiprolu wrote:
> > Michael Ellerman [michael@ellerman.id.au] wrote:
> > | bool is_load_store(int ext_opcode)
> > | {
> > | upper = ext_opcode >> 5;
> > | lower = ext_opcode & 0x1f;
> > |
> > | /* Short circuit as many misses as we can */
> > | if (lower < 3 || lower > 23)
> > | return false;
> >
> > I see some loads/stores like these which are not covered by
> > the above check. Is it ok to ignore them ?
> >
> > lower == 29: ldepx, stdepx, eviddepx, evstddepx
> >
> > lower == 31: lwepx, lbepx, lfdepx, stfdepx,
>
> Those are the external process ID instructions, which I've never heard
> of anyone using, I think we can ignore them.
>
> > Looking through the opcode maps, I also see these for primary
> > op code 4:
> >
> > evldd, evlddx, evldwx, evldw, evldh, evldhx.
> >
> > Should we include those also ?
>
> Yes I think so. I didn't check any of the other opcodes for you.
Paul points out these are for the SPE extension, which we also don't
care about. So ignore those as well.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc, perf: Configure BHRB filter before enabling PMU interrupts
From: Michael Ellerman @ 2013-10-09 1:21 UTC (permalink / raw)
To: Anshuman Khandual; +Cc: linuxppc-dev, mikey
In-Reply-To: <5253B26E.3020800@linux.vnet.ibm.com>
On Tue, Oct 08, 2013 at 12:51:18PM +0530, Anshuman Khandual wrote:
> On 10/08/2013 09:51 AM, Michael Ellerman wrote:
> > On Mon, Oct 07, 2013 at 10:00:26AM +0530, Anshuman Khandual wrote:
> >> Right now the `config_bhrb` PMU specific call happens after write_mmcr0
> >> which actually enables the PMU for event counting and interrupt. So
> >> there is a small window of time where the PMU and BHRB runs without the
> >> required HW branch filter (if any) enabled in BHRB. This can cause some
> >> of the branch samples to be collected through BHRB without any filter
> >> being applied and hence affecting the correctness of the results. This
> >> patch moves the BHRB config function call before enabling the interrupts.
> >
> > Patch looks good.
> >
> > But it reminds me I have an item in my TODO list:
> > - "Why can't config_bhrb() be done in compute_mmcr()" ?
> >
>
> compute_mmcr() function deals with generic MMCR* configs for normal PMU
> events. Even if BHRB config touches MMCRA register, it's configuration
> does not interfere with the PMU config for general events. So its best
> to keep them separate.
I'm unconvinced. If they'd been together to begin with this bug never
would have happened.
And there's the added overhead of another indirect function call.
> Besides, we can always look at these code consolidation
> issues in future.
The future is now.
> But this patch solves a problem which is happening right now.
Sure, I'm not saying we shouldn't merge it as a fix. But I think we
should do the cleanup to move it into compute_mmcr() for 3.13.
cheers
^ permalink raw reply
* Re: [PATCH 5/9][v5] powerpc: implement is_instr_load_store().
From: Michael Ellerman @ 2013-10-09 1:03 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: linux-kernel, Stephane Eranian, linuxppc-dev, Paul Mackerras,
Arnaldo Carvalho de Melo, Anshuman Khandual
In-Reply-To: <20131008193117.GA699@us.ibm.com>
On Tue, 2013-10-08 at 12:31 -0700, Sukadev Bhattiprolu wrote:
> Michael Ellerman [michael@ellerman.id.au] wrote:
> | bool is_load_store(int ext_opcode)
> | {
> | upper = ext_opcode >> 5;
> | lower = ext_opcode & 0x1f;
> |
> | /* Short circuit as many misses as we can */
> | if (lower < 3 || lower > 23)
> | return false;
>
> I see some loads/stores like these which are not covered by
> the above check. Is it ok to ignore them ?
>
> lower == 29: ldepx, stdepx, eviddepx, evstddepx
>
> lower == 31: lwepx, lbepx, lfdepx, stfdepx,
Those are the external process ID instructions, which I've never heard
of anyone using, I think we can ignore them.
> Looking through the opcode maps, I also see these for primary
> op code 4:
>
> evldd, evlddx, evldwx, evldw, evldh, evldhx.
>
> Should we include those also ?
Yes I think so. I didn't check any of the other opcodes for you.
cheers
^ permalink raw reply
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