* [PATCH] warning: symbol value 'm' invalid for MCU_MPC8349EMITX
From: Christian Kujau @ 2013-10-28 12:51 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Geert Uytterhoeven
Hi,
during "make ppc6xx_defconfig" the following happens:
HOSTCC scripts/basic/fixdep
GEN /usr/local/src/tmp/lnx/Makefile
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/zconf.tab.o
HOSTLD scripts/kconfig/conf
arch/powerpc/configs/ppc6xx_defconfig:74:warning: symbol value 'm' invalid for MCU_MPC8349EMITX
Setting CONFIG_MCU_MPC8349EMITX=y in ppc6xx_defconfig makes the warning
go away. This too has been reported by Geert Uytterhoeven a long time ago:
https://lkml.org/lkml/2011/11/13/11 - I only came across this because I
needed a "clean" defconfig for this Powerbook G5.
Signed-off-by: Christian Kujau <lists@nerdbynature.de>
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index 20ebfaf..c2353bf 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -71,7 +71,7 @@ CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_PPC_BESTCOMM=y
CONFIG_GPIO_MPC8XXX=y
-CONFIG_MCU_MPC8349EMITX=m
+CONFIG_MCU_MPC8349EMITX=y
CONFIG_HIGHMEM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
Christian.
--
BOFH excuse #312:
incompatible bit-registration operators
^ permalink raw reply related
* Re: perf events ring buffer memory barrier on powerpc
From: Victor Kaplansky @ 2013-10-28 12:38 UTC (permalink / raw)
To: Frederic Weisbecker
Cc: Michael Neuling, Mathieu Desnoyers, Peter Zijlstra, LKML,
Linux PPC dev, Anton Blanchard
In-Reply-To: <CAFTL4hxn47KFKZPLgKeBxxdaAbA4vg9QVzctuW4ZrSgmfX5bAQ@mail.gmail.com>
> From: Frederic Weisbecker <fweisbec@gmail.com>
>
> 2013/10/25 Peter Zijlstra <peterz@infradead.org>:
> > On Wed, Oct 23, 2013 at 03:19:51PM +0100, Frederic Weisbecker wrote:
> > I would argue for
> >
> > READ ->data_tail READ ->data_head
> > smp_rmb() (A) smp_rmb() (C)
> > WRITE $data READ $data
> > smp_wmb() (B) smp_mb() (D)
> > STORE ->data_head WRITE ->data_tail
> >
> > Where A pairs with D, and B pairs with C.
> >
> > I don't think A needs to be a full barrier because we won't in fact
> > write data until we see the store from userspace. So we simply don't
> > issue the data WRITE until we observe it.
> >
> > OTOH, D needs to be a full barrier since it separates the data READ
from
> > the tail WRITE.
> >
> > For B a WMB is sufficient since it separates two WRITEs, and for C an
> > RMB is sufficient since it separates two READs.
>
> Hmm, I need to defer on you for that, I'm not yet comfortable with
> picking specific barrier flavours when both write and read are
> involved in a same side :)
I think you have a point :) IMO, memory barrier (A) is superfluous.
At producer side we need to ensure that "WRITE $data" is not committed to
memory
before "READ ->data_tail" had seen a new value and if the old one indicated
that
there is no enough space for a new entry. All this is already guaranteed by
control flow dependancy on single CPU - writes will not be committed to the
memory
if read value of "data_tail" doesn't specify enough free space in the ring
buffer.
Likewise, on consumer side, we can make use of natural data dependency and
memory ordering guarantee for single CPU and try to replace "smp_mb" by
a more light-weight "smp_rmb":
READ ->data_tail READ ->data_head
// ... smp_rmb() (C)
WRITE $data READ $data
smp_wmb() (B) smp_rmb() (D)
READ $header_size
STORE ->data_head WRITE ->data_tail = $old_data_tail +
$header_size
We ensure that all $data is read before "data_tail" is written by doing
"READ $header_size" after
all other data is read and we rely on natural data dependancy between
"data_tail" write
and "header_size" read.
-- Victor
^ permalink raw reply
* [PATCH] ADB_PMU_LED_IDE selects LEDS_TRIGGER_IDE_DISK which has unmet direct dependencies
From: Christian Kujau @ 2013-10-28 11:26 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Geert Uytterhoeven
Hi,
for quite some time the following is printed (twice) after doing
"make oldconfig":
[...]
scripts/kconfig/conf --oldconfig Kconfig
warning: (ADB_PMU_LED_IDE) selects LEDS_TRIGGER_IDE_DISK which has unmet direct dependencies (NEW_LEDS && IDE_GD_ATA && LEDS_TRIGGERS)
warning: (ADB_PMU_LED_IDE) selects LEDS_TRIGGER_IDE_DISK which has unmet direct dependencies (NEW_LEDS && IDE_GD_ATA && LEDS_TRIGGERS)
I never got around to look into this. But I remember that (when I still
had CONFIG_IDE selected, because CONFIG_PATA_MACIO was not working for my
PowerBook G5), I always had ADB_PMU_LED_IDE selected, so this option was
carried over to my current config.
When doing "make menuconfig" with this generated config I could see that
all 3 necessary options are selected:
Support for PMU based PowerMacs CONFIG_ADB_PMU
Support for the Power/iBook front LED CONFIG_ADB_PMU_LED
Use front LED as IDE LED by default CONFIG_ADB_PMU_LED_IDE
And CONFIG_ADB_PMU_LED_IDE selects CONFIG_LEDS_TRIGGER_IDE_DISK, which in
turn depends on CONFIG_IDE_GD_ATA - but in "make menuconfig" I could still
*unselect* CONFIG_IDE (since I'm using CONFIG_PATA_MACIO) and the 3
options above were still available. I guess "make oldconfig" noticed that
and hence printed the warning above.
The following patch causes ADB_PMU_LED to depend on IDE_GD_ATA, so that
the options above are only available when IDE_GD_ATA is actually selected
and thus eliminates the warning.
Signed-off-by: Christian Kujau <lists@nerdbynature.de>
diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig
index 696238b..f30ac9d 100644
--- a/drivers/macintosh/Kconfig
+++ b/drivers/macintosh/Kconfig
@@ -90,6 +90,7 @@ config ADB_PMU
config ADB_PMU_LED
bool "Support for the Power/iBook front LED"
depends on ADB_PMU
+ depends on IDE_GD_ATA
select NEW_LEDS
select LEDS_CLASS
help
Being a kbuild n00b, I don't know if this is the correct approach though.
After looking through the archives I found that this has been reported by
Geert back in 2012 already: https://lkml.org/lkml/2012/3/13/556
Thanks,
Christian.
--
BOFH excuse #186:
permission denied
^ permalink raw reply related
* Re: perf events ring buffer memory barrier on powerpc
From: Frederic Weisbecker @ 2013-10-28 10:02 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Michael Neuling, Mathieu Desnoyers, LKML, Linux PPC dev,
Anton Blanchard, Victor Kaplansky
In-Reply-To: <20131025173749.GG19466@laptop.lan>
2013/10/25 Peter Zijlstra <peterz@infradead.org>:
> On Wed, Oct 23, 2013 at 03:19:51PM +0100, Frederic Weisbecker wrote:
> I would argue for:
>
> READ ->data_tail READ ->data_head
> smp_rmb() (A) smp_rmb() (C)
> WRITE $data READ $data
> smp_wmb() (B) smp_mb() (D)
> STORE ->data_head WRITE ->data_tail
>
> Where A pairs with D, and B pairs with C.
>
> I don't think A needs to be a full barrier because we won't in fact
> write data until we see the store from userspace. So we simply don't
> issue the data WRITE until we observe it.
>
> OTOH, D needs to be a full barrier since it separates the data READ from
> the tail WRITE.
>
> For B a WMB is sufficient since it separates two WRITEs, and for C an
> RMB is sufficient since it separates two READs.
Hmm, I need to defer on you for that, I'm not yet comfortable with
picking specific barrier flavours when both write and read are
involved in a same side :)
^ permalink raw reply
* Re: perf events ring buffer memory barrier on powerpc
From: Peter Zijlstra @ 2013-10-28 9:22 UTC (permalink / raw)
To: Victor Kaplansky
Cc: Michael Neuling, Mathieu Desnoyers, linux-kernel, Linux PPC dev,
anton, Frederic Weisbecker
In-Reply-To: <OF1519E98D.692AF083-ON42257C11.002E693E-42257C11.00317D48@il.ibm.com>
On Sun, Oct 27, 2013 at 11:00:33AM +0200, Victor Kaplansky wrote:
> Peter Zijlstra <peterz@infradead.org> wrote on 10/25/2013 07:37:49 PM:
>
> > I would argue for:
> >
> > READ ->data_tail READ ->data_head
> > smp_rmb() (A) smp_rmb() (C)
> > WRITE $data READ $data
> > smp_wmb() (B) smp_mb() (D)
> > STORE ->data_head WRITE ->data_tail
> >
> > Where A pairs with D, and B pairs with C.
>
> 1. I agree. My only concern is that architectures which do use atomic
> operations
> with memory barriers, will issue two consecutive barriers now, which is
> sub-optimal.
Yeah, although that would be fairly easy to optimize by the CPUs itself;
not sure they actually do this though.
But we don't really have much choice aside of introducing things like:
smp_wmb__after_local_$op; and I'm fairly sure people won't like adding a
ton of conditional barriers like that either.
> 2. I think the comment in "include/linux/perf_event.h" describing
> "data_head" and
> "data_tail" for user space need an update as well. Current version -
Oh, indeed. Thanks; I'll update that too!
^ permalink raw reply
* linux-next: build failure after merge of the dt-rh tree
From: Stephen Rothwell @ 2013-10-28 8:38 UTC (permalink / raw)
To: Rob Herring; +Cc: linux-kernel, Rob Herring, linux-next, linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 2029 bytes --]
Hi Rob,
After merging the dt-rh tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
arch/powerpc/platforms/powernv/rng.c: In function 'rng_init_per_cpu':
arch/powerpc/platforms/powernv/rng.c:64:2: error: implicit declaration of function 'of_get_ibm_chip_id' [-Werror=implicit-function-declaration]
chip_id = of_get_ibm_chip_id(dn);
^
arch/powerpc/platforms/powernv/rng.c: In function 'rng_create':
arch/powerpc/platforms/powernv/rng.c:85:2: error: implicit declaration of function 'of_iomap' [-Werror=implicit-function-declaration]
rng->regs = of_iomap(dn, 0);
^
arch/powerpc/platforms/powernv/rng.c:85:12: error: assignment makes pointer from integer without a cast [-Werror]
rng->regs = of_iomap(dn, 0);
^
Caused by commit a4da0d50b2a0 ("powerpc: Implement
arch_get_random_long/int() for powernv") from the powerpc tree
interacting with commit b5b4bb3f6a11 ("of: only include prom.h on sparc")
from the dt-rh tree.
I added this merge fix patch (which will need to be sent to Linus when
these two trees get merged, or could be applied now to the powerpc tree):
From: Stephen Rothwell <sfr@canb.auug.org.au>
Date: Mon, 28 Oct 2013 19:34:41 +1100
Subject: [PATCH] powerpc: add include of prom.h to fix powernv/rng.c build
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/platforms/powernv/rng.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/powernv/rng.c b/arch/powerpc/platforms/powernv/rng.c
index 02db7d73cf8b..483b06640efb 100644
--- a/arch/powerpc/platforms/powernv/rng.c
+++ b/arch/powerpc/platforms/powernv/rng.c
@@ -11,10 +11,12 @@
#include <linux/kernel.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <asm/archrandom.h>
#include <asm/io.h>
+#include <asm/prom.h>
#include <asm/machdep.h>
--
1.8.4.rc3
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
[-- Attachment #2: Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply related
* RE: [PATCHv1 1/8] ALSA: Add SAI SoC Digital Audio Interface driver.
From: Xiubo Li-B47053 @ 2013-10-28 7:15 UTC (permalink / raw)
To: Mark Brown
Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org,
linux-doc@vger.kernel.org, tiwai@suse.de, Wang Huan-B18965,
timur@tabi.org, perex@perex.cz, Guo Shawn-R65073,
LW@KARO-electronics.de, linux@arm.linux.org.uk,
Chen Guangyu-B42378, linux-arm-kernel@lists.infradead.org,
grant.likely@linaro.org, devicetree@vger.kernel.org,
ian.campbell@citrix.com, pawel.moll@arm.com,
swarren@wwwdotorg.org, rob.herring@calxeda.com, oskar@scara.com,
Estevam Fabio-R49496, lgirdwood@gmail.com,
linux-kernel@vger.kernel.org, rob@landley.net,
Jin Zhengxiong-R64188, shawn.guo@linaro.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20131024110543.GA18506@sirena.org.uk>
> > +static struct snd_pcm_hardware snd_fsl_hardware =3D {
> > + .info =3D SNDRV_PCM_INFO_INTERLEAVED |
> > + SNDRV_PCM_INFO_BLOCK_TRANSFER |
> > + SNDRV_PCM_INFO_MMAP |
> > + SNDRV_PCM_INFO_MMAP_VALID |
> > + SNDRV_PCM_INFO_PAUSE |
> > + SNDRV_PCM_INFO_RESUME,
> > + .formats =3D SNDRV_PCM_FMTBIT_S16_LE,
> > + .rate_min =3D 8000,
> > + .channels_min =3D 2,
> > + .channels_max =3D 2,
> > + .buffer_bytes_max =3D FSL_SAI_DMABUF_SIZE,
> > + .period_bytes_min =3D 4096,
> > + .period_bytes_max =3D FSL_SAI_DMABUF_SIZE / TCD_NUMBER,
> > + .periods_min =3D TCD_NUMBER,
> > + .periods_max =3D TCD_NUMBER,
> > + .fifo_size =3D 0,
> > +};
>=20
> There's a patch in -next that lets the generic dmaengine code figure out
> some settings from the dmacontroller rather than requiring the driver to
> explicitly provide configuration - it's "ASoC: dmaengine-pcm: Provide
> default config". Please update your driver to use this, or let's work
> out what it doesn't do any try to fix it.
>
I will do a research.
=20
> > + ret =3D fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
> > + FSL_FMT_TRANSMITTER);
> > + if (ret) {
> > + dev_err(cpu_dai->dev,
> > + "Cannot set sai's transmitter sysclk: %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + ret =3D fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
> > + FSL_FMT_RECEIVER);
>=20
> As other people have commented these should be exposed as separate clocks
> rather than set in sync, unless there's some hardware reason they need to
> be identical. If that is the case then a comment explaining the
> limitation would be good.
>=20
> Similarly with several of the other functions.
>=20
As I have replied before, there is one function couldn't be separated for t=
he hardware limitation.
> > +int fsl_sai_dai_remove(struct snd_soc_dai *dai) {
> > + struct fsl_sai *sai =3D dev_get_drvdata(dai->dev);
> > +
> > + clk_disable_unprepare(sai->clk);
>=20
> It'd be a bit nicer to only enable the clock while the driver is actively
> being used rather than all the time the system is powered up but it's not
> a blocker for merge.
>=20
Actully there are to "XXX_probe" functions and two "XXX_remove" functions:
fsl_sai_dai_probe() and fsl_sai_dai_remove() are callbacks of the ASoC subs=
ystem.
And in fsl_sai_dai_probe() needs to read/write the SAI controller's registe=
rs, so
the clk_enable_prepare() must be here and clk_disable_unprepare() in fsl_sa=
i_dai_remove().
fsl_sai_probe() and fsl_sai_remove() are the driver's probe and remove inte=
rfaces.
So the "+ clk_disable_unprepare(sai->clk);" sentence in fsl_sai_remove() wi=
ll be removed later.
> > + ret =3D snd_soc_register_component(&pdev->dev, &fsl_component,
> > + &fsl_sai_dai, 1);
> > + if (ret)
> > + return ret;
>=20
> There's a devm_snd_soc_register_component() in -next, please use that.
>=20
See the next version.
> > +
> > + ret =3D fsl_pcm_dma_init(pdev);
> > + if (ret)
> > + goto out;
> > +
> > + platform_set_drvdata(pdev, sai);
>=20
> These should go before the driver is registered with the subsystem
> otherwise you've got a race where something might try to use the driver
> before init is finished.
>=20
> > +static int fsl_sai_remove(struct platform_device *pdev) {
> > + struct fsl_sai *sai =3D platform_get_drvdata(pdev);
> > +
> > + fsl_pcm_dma_exit(pdev);
> > +
> > + snd_soc_unregister_component(&pdev->dev);
>=20
> Similarly here, unregister from the subsystem then clean up after.
>=20
See the next version.
> > +#define SAI_CR5_FBT(x) ((x) << 8)
> > +#define SAI_CR5_FBT_MASK (0x1f << 8)
> > +
> > +/* SAI audio dividers */
> > +#define FSL_SAI_TX_DIV 0
> > +#define FSL_SAI_RX_DIV 1
>=20
> Make the namespacing consistent please - for preference use FSL_SAI
> always.
>
See the next version.
^ permalink raw reply
* RE: [PATCHv1 5/8] ASoC: sgtl5000: Revise the bugs about the sgt15000 codec.
From: Xiubo Li-B47053 @ 2013-10-28 6:07 UTC (permalink / raw)
To: Mark Brown
Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org,
linux-doc@vger.kernel.org, tiwai@suse.de, Wang Huan-B18965,
timur@tabi.org, perex@perex.cz, Guo Shawn-R65073,
LW@KARO-electronics.de, linux@arm.linux.org.uk,
Chen Guangyu-B42378, linux-arm-kernel@lists.infradead.org,
grant.likely@linaro.org, devicetree@vger.kernel.org,
ian.campbell@citrix.com, pawel.moll@arm.com,
swarren@wwwdotorg.org, rob.herring@calxeda.com, oskar@scara.com,
Estevam Fabio-R49496, lgirdwood@gmail.com,
linux-kernel@vger.kernel.org, rob@landley.net,
Jin Zhengxiong-R64188, shawn.guo@linaro.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20131018172814.GT2443@sirena.org.uk>
> > @@ -883,14 +883,19 @@ static int ldo_regulator_register(struct
> snd_soc_codec *codec,
> > struct regulator_init_data *init_data,
> > int voltage)
> > {
> > +#ifdef CONFIG_SND_SOC_FSL_SGTL5000
> > + return 0;
> > +#else
> > dev_err(codec->dev, "this setup needs regulator support in the
> kernel\n");
> > return -EINVAL;
> > +#endif
> > }
>=20
> If these systems don't actually need the internal regulator then should
> they not be trying to enable it? =20
>
Yes, I think do not trying to enable the regulator is much better.
>Alternatively if it's OK to ignore this then why is this conditional in th=
e board?
>=20
The CONFIG_SND_SOC_FSL_SGTL5000 micro maybe confuse you and others.
And it should be CONFIG_SND_SOC_FSL_SGTL5000_VF610....
^ permalink raw reply
* RE: [alsa-devel] [PATCHv1 1/8] ALSA: Add SAI SoC Digital Audio Interface driver.
From: Xiubo Li-B47053 @ 2013-10-28 5:58 UTC (permalink / raw)
To: djbw@fb.com, vinod.koul@intel.com
Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org,
linux-doc@vger.kernel.org, tiwai@suse.de, Wang Huan-B18965,
timur@tabi.org, linux-kernel@vger.kernel.org, Guo Shawn-R65073,
LW@KARO-electronics.de, Lars-Peter Clausen,
linux@arm.linux.org.uk, Chen Guangyu-B42378, oskar@scara.com,
grant.likely@linaro.org, devicetree@vger.kernel.org,
ian.campbell@citrix.com, pawel.moll@arm.com,
swarren@wwwdotorg.org, rob.herring@calxeda.com,
broonie@kernel.org, linux-arm-kernel@lists.infradead.org,
Estevam Fabio-R49496, lgirdwood@gmail.com, rob@landley.net,
Jin Zhengxiong-R64188, shawn.guo@linaro.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <526021B0.6050206@metafoo.de>
Hi Dan, Vinod,
> > +static int fsl_sai_probe(struct platform_device *pdev) {
> [...]
> > +
> > + sai->dma_params_rx.addr =3D res->start + SAI_RDR;
> > + sai->dma_params_rx.maxburst =3D 6;
> > + index =3D of_property_match_string(np, "dma-names", "rx");
> > + ret =3D of_parse_phandle_with_args(np, "dmas", "#dma-cells", index,
> > + &dma_args);
> > + if (ret)
> > + return ret;
> > + sai->dma_params_rx.slave_id =3D dma_args.args[1];
> > +
> > + sai->dma_params_tx.addr =3D res->start + SAI_TDR;
> > + sai->dma_params_tx.maxburst =3D 6;
> > + index =3D of_property_match_string(np, "dma-names", "tx");
> > + ret =3D of_parse_phandle_with_args(np, "dmas", "#dma-cells", index,
> > + &dma_args);
> > + if (ret)
> > + return ret;
> > + sai->dma_params_tx.slave_id =3D dma_args.args[1];
>=20
> The driver should not have to manually parse the dma devicetree
> properties, this is something that should be handled by the dma engine
> driver.
>=20
What do you think about the DMA slave_id ?
I have been noticed by one colleague that this should be parsed here, which
is from your opinions ?
> > +
> > + ret =3D snd_soc_register_component(&pdev->dev, &fsl_component,
> > + &fsl_sai_dai, 1);
> > + if (ret)
> > + return ret;
> > +
> > + ret =3D fsl_pcm_dma_init(pdev);
> > + if (ret)
> > + goto out;
^ permalink raw reply
* [PATCH] powerpc: FA_DUMP depends on KEXEC
From: Michael Ellerman @ 2013-10-28 4:00 UTC (permalink / raw)
To: linuxppc-dev
If you try and build the FA_DUMP code with CONFIG_KEXEC=n, you see
errors such as the following:
arch/powerpc/kernel/fadump.c
408:2: error: 'crashing_cpu' undeclared (first use in this function)
410:2: error: implicit declaration of function 'crash_save_vmcoreinfo'
513:22: error: storage size of 'prstatus' isn't known
520:2: error: implicit declaration of function 'elf_core_copy_kernel_regs'
521:36: error: 'KEXEC_CORE_NOTE_NAME' undeclared (first use in this function)
624:49: error: 'note_buf_t' undeclared (first use in this function)
872:2: error: implicit declaration of function 'paddr_vmcoreinfo_note'
874:18: error: 'vmcoreinfo_max_size' undeclared (first use in this function)
This is because although FA_DUMP doesn't use kexec as the actual reboot
mechanism, it does use parts of the kexec code to assemble/disassemble
the crash image.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 38f3b7e..9d4e80e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -404,7 +404,7 @@ config CRASH_DUMP
config FA_DUMP
bool "Firmware-assisted dump"
- depends on PPC64 && PPC_RTAS && CRASH_DUMP
+ depends on PPC64 && PPC_RTAS && CRASH_DUMP && KEXEC
help
A robust mechanism to get reliable kernel crash dump with
assistance from firmware. This approach does not use kexec,
--
1.8.3.2
^ permalink raw reply related
* RE: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Tang Yuantian-B29983 @ 2013-10-28 2:20 UTC (permalink / raw)
To: Grant Likely, galak@kernel.crashing.org
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20131025201108.B06B8C405AE@trevor.secretlab.ca>
> > +1. Clock Block Binding
> > +
> > +Required properties:
> > +- compatible: Should include one or more of the following:
> > + - "fsl,<chip>-clockgen": for chip specific clock block
> > + - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x clock
> > +- reg: Offset and length of the clock register set
> > +- clock-frequency: Indicates input clock frequency of clock block.
> > + Will be set by u-boot
> > +
> > +Recommended properties:
> > +- #ddress-cells: Specifies the number of cells used to represent
>=20
> typo
Thanks, someone else already pointed out it. Will fix in next patch.
Regards,
Yuantian
>=20
> > + physical base addresses. Must be present if the device has
> > + sub-nodes and set to 1 if present
> > +- #size-cells: Specifies the number of cells used to represent
> > + the size of an address. Must be present if the device has
> > + sub-nodes and set to 1 if present
> > +
> > +2. Clock Provider/Consumer Binding
> > +
> > +Most of the binding are from the common clock binding[1].
> > + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> > +
> > +Required properties:
> > +- compatible : Should include one or more of the following:
> > + - "fsl,qoriq-core-pll-[1,2].x": Indicates a core PLL clock device
> > + - "fsl,qoriq-core-mux-[1,2].x": Indicates a core multiplexer clock
> > + device; divided from the core PLL clock
> > + - "fixed-clock": From common clock binding; indicates output clock
> > + of oscillator
> > + - "fsl,qoriq-sysclk-[1,2].x": Indicates input system clock
> > +- #clock-cells: From common clock binding; indicates the number of
> > + output clock. 0 is for one output clock; 1 for more than one clock
> > +
> > +Recommended properties:
> > +- clocks: Should be the phandle of input parent clock
> > +- clock-names: From common clock binding, indicates the clock name
> > +- clock-output-names: From common clock binding, indicates the names
> of
> > + output clocks
> > +- reg: Should be the offset and length of clock block base address.
> > + The length should be 4.
>=20
> Binding looks reasonable to me.
>=20
> g.
>=20
> > +
> > +Example for clock block and clock provider:
> > +/ {
> > + clockgen: global-utilities@e1000 {
> > + compatible =3D "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> > + reg =3D <0xe1000 0x1000>;
> > + clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > + };
> > + }
> > +
> > +Example for clock consumer:
> > +
> > +/ {
> > + cpu0: PowerPC,e5500@0 {
> > + ...
> > + clocks =3D <&mux0>;
> > + ...
> > + };
> > + }
> > diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> > index 5a6615d..e910e82 100644
> > --- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> > @@ -86,6 +86,41 @@
> >
> > clockgen: global-utilities@e1000 {
> > compatible =3D "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-2.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2", "pll0-div4";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2", "pll1-div4";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-2.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll0 2>,
> > + <&pll1 0>, <&pll1 1>, <&pll1 2>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll0_2",
> > + "pll1_0", "pll1_1", "pll1_2";
> > + clock-output-names =3D "cmux0";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> > index 7b4426e..a11126b 100644
> > --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> > @@ -62,11 +62,13 @@
> > cpu0: PowerPC,e6500@0 {
> > device_type =3D "cpu";
> > reg =3D <0 1>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > cpu1: PowerPC,e6500@2 {
> > device_type =3D "cpu";
> > reg =3D <2 3>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > };
> > diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> > index e5cf6c8..5cfcfe4 100644
> > --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> > @@ -130,6 +130,41 @@
> >
> > clockgen: global-utilities@e1000 {
> > compatible =3D "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-2.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2", "pll0-div4";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2", "pll1-div4";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-2.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll0 2>,
> > + <&pll1 0>, <&pll1 1>, <&pll1 2>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll0_2",
> > + "pll1_0", "pll1_1", "pll1_2";
> > + clock-output-names =3D "cmux0";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> > index 5263fa4..185a231 100644
> > --- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> > @@ -62,21 +62,25 @@
> > cpu0: PowerPC,e6500@0 {
> > device_type =3D "cpu";
> > reg =3D <0 1>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > cpu1: PowerPC,e6500@2 {
> > device_type =3D "cpu";
> > reg =3D <2 3>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > cpu2: PowerPC,e6500@4 {
> > device_type =3D "cpu";
> > reg =3D <4 5>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > cpu3: PowerPC,e6500@6 {
> > device_type =3D "cpu";
> > reg =3D <6 7>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2>;
> > };
> > };
> > diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> > index dc6cc5a..f3f7f65 100644
> > --- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> > @@ -308,6 +308,66 @@
> > compatible =3D "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
> > reg =3D <0xe1000 0x1000>;
> > clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > +
> > + mux2: mux2@40 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x40 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux2";
> > + };
> > +
> > + mux3: mux3@60 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x60 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux3";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> > index 7a2697d..22f3b14 100644
> > --- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> > @@ -81,6 +81,7 @@
> > cpu0: PowerPC,e500mc@0 {
> > device_type =3D "cpu";
> > reg =3D <0>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_0>;
> > L2_0: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -89,6 +90,7 @@
> > cpu1: PowerPC,e500mc@1 {
> > device_type =3D "cpu";
> > reg =3D <1>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_1>;
> > L2_1: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -97,6 +99,7 @@
> > cpu2: PowerPC,e500mc@2 {
> > device_type =3D "cpu";
> > reg =3D <2>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_2>;
> > L2_2: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -105,6 +108,7 @@
> > cpu3: PowerPC,e500mc@3 {
> > device_type =3D "cpu";
> > reg =3D <3>;
> > + clocks =3D <&mux3>;
> > next-level-cache =3D <&L2_3>;
> > L2_3: l2-cache {
> > next-level-cache =3D <&cpc>;
> > diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> > index 3fa1e22..9bab9c9 100644
> > --- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> > @@ -335,6 +335,66 @@
> > compatible =3D "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
> > reg =3D <0xe1000 0x1000>;
> > clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > +
> > + mux2: mux2@40 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x40 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux2";
> > + };
> > +
> > + mux3: mux3@60 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x60 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux3";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> > index c9ca2c3..468e8be 100644
> > --- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> > @@ -82,6 +82,7 @@
> > cpu0: PowerPC,e500mc@0 {
> > device_type =3D "cpu";
> > reg =3D <0>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_0>;
> > L2_0: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -90,6 +91,7 @@
> > cpu1: PowerPC,e500mc@1 {
> > device_type =3D "cpu";
> > reg =3D <1>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_1>;
> > L2_1: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -98,6 +100,7 @@
> > cpu2: PowerPC,e500mc@2 {
> > device_type =3D "cpu";
> > reg =3D <2>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_2>;
> > L2_2: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -106,6 +109,7 @@
> > cpu3: PowerPC,e500mc@3 {
> > device_type =3D "cpu";
> > reg =3D <3>;
> > + clocks =3D <&mux3>;
> > next-level-cache =3D <&L2_3>;
> > L2_3: l2-cache {
> > next-level-cache =3D <&cpc>;
> > diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> > index 34769a7..2108269 100644
> > --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> > @@ -355,6 +355,118 @@
> > compatible =3D "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
> > reg =3D <0xe1000 0x1000>;
> > clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + pll2: pll2@840 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x840 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll2", "pll2-div2";
> > + };
> > +
> > + pll3: pll3@860 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x860 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll3", "pll3-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > +
> > + mux2: mux2@40 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x40 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux2";
> > + };
> > +
> > + mux3: mux3@60 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x60 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux3";
> > + };
> > +
> > + mux4: mux4@80 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x80 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> > + clock-names =3D "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> > + clock-output-names =3D "cmux4";
> > + };
> > +
> > + mux5: mux5@a0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0xa0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> > + clock-names =3D "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> > + clock-output-names =3D "cmux5";
> > + };
> > +
> > + mux6: mux6@c0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0xc0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> > + clock-names =3D "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> > + clock-output-names =3D "cmux6";
> > + };
> > +
> > + mux7: mux7@e0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0xe0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> > + clock-names =3D "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> > + clock-output-names =3D "cmux7";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> > index 493d9a0..0040b5a 100644
> > --- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> > @@ -81,6 +81,7 @@
> > cpu0: PowerPC,e500mc@0 {
> > device_type =3D "cpu";
> > reg =3D <0>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_0>;
> > L2_0: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -89,6 +90,7 @@
> > cpu1: PowerPC,e500mc@1 {
> > device_type =3D "cpu";
> > reg =3D <1>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_1>;
> > L2_1: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -97,6 +99,7 @@
> > cpu2: PowerPC,e500mc@2 {
> > device_type =3D "cpu";
> > reg =3D <2>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_2>;
> > L2_2: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -105,6 +108,7 @@
> > cpu3: PowerPC,e500mc@3 {
> > device_type =3D "cpu";
> > reg =3D <3>;
> > + clocks =3D <&mux3>;
> > next-level-cache =3D <&L2_3>;
> > L2_3: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -113,6 +117,7 @@
> > cpu4: PowerPC,e500mc@4 {
> > device_type =3D "cpu";
> > reg =3D <4>;
> > + clocks =3D <&mux4>;
> > next-level-cache =3D <&L2_4>;
> > L2_4: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -121,6 +126,7 @@
> > cpu5: PowerPC,e500mc@5 {
> > device_type =3D "cpu";
> > reg =3D <5>;
> > + clocks =3D <&mux5>;
> > next-level-cache =3D <&L2_5>;
> > L2_5: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -129,6 +135,7 @@
> > cpu6: PowerPC,e500mc@6 {
> > device_type =3D "cpu";
> > reg =3D <6>;
> > + clocks =3D <&mux6>;
> > next-level-cache =3D <&L2_6>;
> > L2_6: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -137,6 +144,7 @@
> > cpu7: PowerPC,e500mc@7 {
> > device_type =3D "cpu";
> > reg =3D <7>;
> > + clocks =3D <&mux7>;
> > next-level-cache =3D <&L2_7>;
> > L2_7: l2-cache {
> > next-level-cache =3D <&cpc>;
> > diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> > index bc3ae5a..e09f8cd 100644
> > --- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> > @@ -340,6 +340,48 @@
> > compatible =3D "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> > reg =3D <0xe1000 0x1000>;
> > clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> > index 8df47fc..fe1a2e6 100644
> > --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> > @@ -88,6 +88,7 @@
> > cpu0: PowerPC,e5500@0 {
> > device_type =3D "cpu";
> > reg =3D <0>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_0>;
> > L2_0: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -96,6 +97,7 @@
> > cpu1: PowerPC,e5500@1 {
> > device_type =3D "cpu";
> > reg =3D <1>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_1>;
> > L2_1: l2-cache {
> > next-level-cache =3D <&cpc>;
> > diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> > index a91897f..109f132 100644
> > --- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> > @@ -300,6 +300,66 @@
> > compatible =3D "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
> > reg =3D <0xe1000 0x1000>;
> > clock-frequency =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-1.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-1.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux1";
> > + };
> > +
> > + mux2: mux2@40 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x40 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux2";
> > + };
> > +
> > + mux3: mux3@60 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x60 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-1.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> > + clock-output-names =3D "cmux3";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> > index 40ca943..3674686 100644
> > --- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> > @@ -81,6 +81,7 @@
> > cpu0: PowerPC,e5500@0 {
> > device_type =3D "cpu";
> > reg =3D <0>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_0>;
> > L2_0: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -89,6 +90,7 @@
> > cpu1: PowerPC,e5500@1 {
> > device_type =3D "cpu";
> > reg =3D <1>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_1>;
> > L2_1: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -97,6 +99,7 @@
> > cpu2: PowerPC,e5500@2 {
> > device_type =3D "cpu";
> > reg =3D <2>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_2>;
> > L2_2: l2-cache {
> > next-level-cache =3D <&cpc>;
> > @@ -105,6 +108,7 @@
> > cpu3: PowerPC,e5500@3 {
> > device_type =3D "cpu";
> > reg =3D <3>;
> > + clocks =3D <&mux3>;
> > next-level-cache =3D <&L2_3>;
> > L2_3: l2-cache {
> > next-level-cache =3D <&cpc>;
> > diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> > b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> > index 510afa3..d45434f 100644
> > --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> > @@ -370,6 +370,91 @@
> > clockgen: global-utilities@e1000 {
> > compatible =3D "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
> > reg =3D <0xe1000 0x1000>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > +
> > + sysclk: sysclk {
> > + #clock-cells =3D <0>;
> > + compatible =3D "fsl,qoriq-sysclk-2.0", "fixed-clock";
> > + clock-output-names =3D "sysclk";
> > + }
> > +
> > + pll0: pll0@800 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x800 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll0", "pll0-div2", "pll0-div4";
> > + };
> > +
> > + pll1: pll1@820 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x820 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll1", "pll1-div2", "pll1-div4";
> > + };
> > +
> > + pll2: pll2@840 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x840 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll2", "pll2-div2", "pll2-div4";
> > + };
> > +
> > + pll3: pll3@860 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x860 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll3", "pll3-div2", "pll3-div4";
> > + };
> > +
> > + pll4: pll4@880 {
> > + #clock-cells =3D <1>;
> > + reg =3D <0x880 0x4>;
> > + compatible =3D "fsl,qoriq-core-pll-2.0";
> > + clocks =3D <&sysclk>;
> > + clock-output-names =3D "pll4", "pll4-div2", "pll4-div4";
> > + };
> > +
> > + mux0: mux0@0 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x0 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-2.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll0 2>,
> > + <&pll1 0>, <&pll1 1>, <&pll1 2>,
> > + <&pll2 0>, <&pll2 1>, <&pll2 2>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll0_2",
> > + "pll1_0", "pll1_1", "pll1_2",
> > + "pll2_0", "pll2_1", "pll2_2";
> > + clock-output-names =3D "cmux0";
> > + };
> > +
> > + mux1: mux1@20 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x20 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-2.0";
> > + clocks =3D <&pll0 0>, <&pll0 1>, <&pll0 2>,
> > + <&pll1 0>, <&pll1 1>, <&pll1 2>,
> > + <&pll2 0>, <&pll2 1>, <&pll2 2>;
> > + clock-names =3D "pll0_0", "pll0_1", "pll0_2",
> > + "pll1_0", "pll1_1", "pll1_2",
> > + "pll2_0", "pll2_1", "pll2_2";
> > + clock-output-names =3D "cmux1";
> > + };
> > +
> > + mux2: mux2@40 {
> > + #clock-cells =3D <0>;
> > + reg =3D <0x40 0x4>;
> > + compatible =3D "fsl,qoriq-core-mux-2.0";
> > + clocks =3D <&pll3 0>, <&pll3 1>, <&pll3 2>,
> > + <&pll4 0>, <&pll4 1>, <&pll4 2>;
> > + clock-names =3D "pll3_0", "pll3_1", "pll3_2",
> > + "pll4_0", "pll4_1", "pll4_2";
> > + clock-output-names =3D "cmux2";
> > + };
> > };
> >
> > rcpm: global-utilities@e2000 {
> > diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> > b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> > index a93c55a..0b8ccc5 100644
> > --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> > +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> > @@ -67,61 +67,73 @@
> > cpu0: PowerPC,e6500@0 {
> > device_type =3D "cpu";
> > reg =3D <0 1>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_1>;
> > };
> > cpu1: PowerPC,e6500@2 {
> > device_type =3D "cpu";
> > reg =3D <2 3>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_1>;
> > };
> > cpu2: PowerPC,e6500@4 {
> > device_type =3D "cpu";
> > reg =3D <4 5>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_1>;
> > };
> > cpu3: PowerPC,e6500@6 {
> > device_type =3D "cpu";
> > reg =3D <6 7>;
> > + clocks =3D <&mux0>;
> > next-level-cache =3D <&L2_1>;
> > };
> > cpu4: PowerPC,e6500@8 {
> > device_type =3D "cpu";
> > reg =3D <8 9>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_2>;
> > };
> > cpu5: PowerPC,e6500@10 {
> > device_type =3D "cpu";
> > reg =3D <10 11>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_2>;
> > };
> > cpu6: PowerPC,e6500@12 {
> > device_type =3D "cpu";
> > reg =3D <12 13>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_2>;
> > };
> > cpu7: PowerPC,e6500@14 {
> > device_type =3D "cpu";
> > reg =3D <14 15>;
> > + clocks =3D <&mux1>;
> > next-level-cache =3D <&L2_2>;
> > };
> > cpu8: PowerPC,e6500@16 {
> > device_type =3D "cpu";
> > reg =3D <16 17>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_3>;
> > };
> > cpu9: PowerPC,e6500@18 {
> > device_type =3D "cpu";
> > reg =3D <18 19>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_3>;
> > };
> > cpu10: PowerPC,e6500@20 {
> > device_type =3D "cpu";
> > reg =3D <20 21>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_3>;
> > };
> > cpu11: PowerPC,e6500@22 {
> > device_type =3D "cpu";
> > reg =3D <22 23>;
> > + clocks =3D <&mux2>;
> > next-level-cache =3D <&L2_3>;
> > };
> > };
> > --
> > 1.8.0
> >
> >
> > _______________________________________________
> > Linuxppc-dev mailing list
> > Linuxppc-dev@lists.ozlabs.org
> > https://lists.ozlabs.org/listinfo/linuxppc-dev
>=20
^ permalink raw reply
* Re: [PATCH 2/2] powerpc: Move local setup.h declarations to arch includes
From: Michael Ellerman @ 2013-10-28 1:28 UTC (permalink / raw)
To: Robert C Jennings; +Cc: linuxppc-dev
In-Reply-To: <1382729107-13560-3-git-send-email-rcj@linux.vnet.ibm.com>
On Fri, Oct 25, 2013 at 02:25:07PM -0500, Robert C Jennings wrote:
> Move the few declarations from arch/powerpc/kernel/setup.h
> into arch/powerpc/include/asm/setup.h. This resolves a
> sparse warning for arch/powerpc/mm/numa.c which defines
> do_init_bootmem() but can't include the setup.h header
> in the prior path.
>
> Resolves:
> arch/powerpc/mm/numa.c:998:13:
> warning: symbol 'do_init_bootmem' was not declared.
> Should it be static?
There's always a tension between too many well-focused-micro-headers,
and too few random-piles-of-junk headers. I tend towards the former, but
in this case I think you're right to drop setup.h.
> diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
> index d3ca855..5e24df0 100644
> --- a/arch/powerpc/include/asm/setup.h
> +++ b/arch/powerpc/include/asm/setup.h
> @@ -23,6 +23,11 @@ extern void reloc_got2(unsigned long);
>
> #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
>
> +extern void check_for_initrd(void);
> +extern void do_init_bootmem(void);
> +extern void setup_panic(void);
> +extern int do_early_xmon;
I don't see do_early_xmon used anywhere? Looks like I forgot to clean it
up in 47679283. Mind dropping it?
I think these days it's trendy to not use extern in headers.
cheers
^ permalink raw reply
* Re: [PATCH 1/3] powerpc: sync ppc64, ppc64e and pseries configs
From: Michael Ellerman @ 2013-10-28 1:09 UTC (permalink / raw)
To: Anton Blanchard; +Cc: paulus, linuxppc-dev
In-Reply-To: <20131022114450.296ae01d@kryten>
On Tue, Oct 22, 2013 at 11:44:50AM +1100, Anton Blanchard wrote:
>
> Run savedefconfig over the ppc64, ppc64e and pseries config
> -CONFIG_EXPERIMENTAL=y
This went way.
> -CONFIG_EFI_PARTITION=y
This became default y.
> -CONFIG_HOTPLUG_CPU=y
This isn't going away, it's selected by pseries, so doesn't need to be
in the defconfig.
> -CONFIG_PPC_DENORMALISATION=y
This is default y if POWERNV, so I guess that's why it isn't needed.
cheers
^ permalink raw reply
* Has anyone a ATMEL TPM Chip on PPC64 (CONFIG_TCG_ATMEL)?
From: Peter Hüwe @ 2013-10-27 22:06 UTC (permalink / raw)
To: linuxppc-dev, tpmdd-devel
Hi,
I was wondering if anyone here on this list still has a machine with an old=
=20
ATMEL TPM (trusted platform module) lying around?
=46rom the kconfig entry it becomes evident that it was only supported on p=
pc64=20
machines.
config TCG_ATMEL
tristate "Atmel TPM Interface"
depends on PPC64 || HAS_IOPORT
---help---
If you have a TPM security chip from Atmel say Yes and it=20
will be accessible from within Linux. To compile this driver=20
as a module, choose M here; the module will be called tpm_atmel.
The hardware/driver is pretty old and the driver might have contained a bug=
=20
that made it unusable for the last 6 years ;)
So if anyone still has this kind of hardware around, please reply.
Thanks,
Peter
^ permalink raw reply
* Re: [PATCH] [RFC] Emulate "lwsync" to run standard user land on e500 cores
From: Wolfgang Denk @ 2013-10-27 10:29 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <1382697373.3926.36.camel@aoeu.buserror.net>
Dear Scott,
In message <1382697373.3926.36.camel@aoeu.buserror.net> you wrote:
>
> Has anyone measured how much this slows things down with a typical
> userspace?
In the applications I found to trigger this issue the number of traps
is so small that I can't even reliably measure any difference.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
When it is incorrect, it is, at least *authoritatively* incorrect.
- Hitchiker's Guide To The Galaxy
^ permalink raw reply
* Re: [PATCH] [RFC] Emulate "lwsync" to run standard user land on e500 cores
From: Wolfgang Denk @ 2013-10-27 10:25 UTC (permalink / raw)
To: Kumar Gala; +Cc: Scott Wood, linuxppc-dev
In-Reply-To: <6BFC8EB0-1A75-41C3-985A-E3ED14846710@kernel.crashing.org>
Dear Kumar,
In message <6BFC8EB0-1A75-41C3-985A-E3ED14846710@kernel.crashing.org> you wrote:
>
> Fair enough
> >
> > I'm not too worried as long as we warn and account them.
>
> Than, I'd ask this be under a Kconfig option that is disabled by
> default. Users should have to explicitly enable this so they know what
> they are doing.
Is this really worth the effort? Under normal situations (users are
using a user space environment that has been properly buiult for the
processor variant they are using) nobody should ever run into this
situation. It happens only if you are already doing something wrong -
like using user space that has not been built for an E500 core on such
a machine.
In this situation, it seems more useful to me if a "standard" kernel
just works with a "standard" user space environment, even if this
includes some performance penalty - which actually should be
neglibale. In my tests (when running standard Debian for PPC on a
E500 only very few programs actually triggered this situation, and
none of them in a time-critical way. I doubt I would even be able to
measure the performance impact.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"...all the good computer designs are bootlegged; the formally
planned products, if they are built at all, are dogs!" - David E.
Lundstrom, "A Few Good Men From Univac", MIT Press, 1987
^ permalink raw reply
* Re: perf events ring buffer memory barrier on powerpc
From: Victor Kaplansky @ 2013-10-27 9:00 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Michael Neuling, Mathieu Desnoyers, linux-kernel, Linux PPC dev,
anton, Frederic Weisbecker
In-Reply-To: <20131025173749.GG19466@laptop.lan>
Peter Zijlstra <peterz@infradead.org> wrote on 10/25/2013 07:37:49 PM:
> I would argue for:
>
> READ ->data_tail READ ->data_head
> smp_rmb() (A) smp_rmb() (C)
> WRITE $data READ $data
> smp_wmb() (B) smp_mb() (D)
> STORE ->data_head WRITE ->data_tail
>
> Where A pairs with D, and B pairs with C.
1. I agree. My only concern is that architectures which do use atomic
operations
with memory barriers, will issue two consecutive barriers now, which is
sub-optimal.
2. I think the comment in "include/linux/perf_event.h" describing
"data_head" and
"data_tail" for user space need an update as well. Current version -
/*
* Control data for the mmap() data buffer.
*
* User-space reading the @data_head value should issue an rmb(),
on
* SMP capable platforms, after reading this value -- see
* perf_event_wakeup().
*
* When the mapping is PROT_WRITE the @data_tail value should be
* written by userspace to reflect the last read data. In this case
* the kernel will not over-write unread data.
*/
__u64 data_head; /* head in the data section */
__u64 data_tail; /* user-space written tail */
- say nothing about the need of memory barrier before "data_tail" write.
-- Victor
^ permalink raw reply
* [PATCH TRIVIAL] powerpc: Fix a typo in comments of va to pa conversion
From: Vaishnavi Bhat @ 2013-10-27 6:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus
This patch fixes typo in comments virtual to physical
address conversion.
Signed-off-by: Vaishnavi Bhat <vaishnavi@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/page.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index b9f4262..753c662 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -78,7 +78,7 @@ extern unsigned int HPAGE_SHIFT;
*
* Also, KERNELBASE >= PAGE_OFFSET and PHYSICAL_START >= MEMORY_START
*
- * There are two was to determine a physical address from a virtual one:
+ * There are two ways to determine a physical address from a virtual one:
* va = pa + PAGE_OFFSET - MEMORY_START
* va = pa + KERNELBASE - PHYSICAL_START
*
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH] ASoC: fsl_spdif: fix return value check in fsl_spdif_probe()
From: Mark Brown @ 2013-10-26 20:34 UTC (permalink / raw)
To: Wei Yongjun
Cc: alsa-devel, lgirdwood, tiwai, timur, rob.herring, perex,
yongjun_wei, grant.likely, linuxppc-dev
In-Reply-To: <CAPgLHd-2d+RLDq1U=wXR72nAEH1Hr6FDcWp0eAyEkrNmfjrEaA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 318 bytes --]
On Fri, Oct 25, 2013 at 05:29:25PM +0800, Wei Yongjun wrote:
> From: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
>
> In case of error, the function platform_get_resource() returns NULL
> pointer not ERR_PTR(). The IS_ERR() test in the return value check
> should be replaced with NULL test.
Applied, thanks.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH] [RFC] Emulate "lwsync" to run standard user land on e500 cores
From: Kumar Gala @ 2013-10-26 7:26 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Yang James-RA8135, David Laight, linuxppc-dev
In-Reply-To: <1382706165.9395.63.camel@pasglop>
On Oct 25, 2013, at 8:02 AM, Benjamin Herrenschmidt wrote:
> On Fri, 2013-10-25 at 10:58 +0100, David Laight wrote:
>>> This is not a distro issue. It's a libstdc++ portability issue. =
libstdc++
>>> hardcodes lwsync unless __NO_LWSYNC__ is explicitly defined,
>>> which you only get with -mcpu=3D8540/-mcpu=3D8548. When compiled
>>> for any powerpc target other than -mcpu=3D8540/-mcpu=3D8548, =
including
>>> the default -mcpu=3Dcommon, libstdc++ will end up containing =
lwsync.
>>> There is no way to explicitly request libstdc++ to be built without =
lwsync
>>> with an -mcpu target other than 8540/8548.
>>>=20
>>> The issue is easily demonstrated by running a program that throws a
>>> C++ exception: __cxa_throw() is called, which has an lwsync. This
>>> results in an illegal instruction exception when run on an =
e500v1/e500v2.
>>=20
>> Perhaps libstc++ should be working out at run time whether lwsync is =
valid?
>=20
> Do we have enough coats of paint on this bike shed yet ? :-)
>=20
> I'm personally tempted to take Scott's approach since that's what we =
do
> for other things as well, it just works and is simple.
>=20
> Cheers,
> Ben.
>=20
I give in, however some should test with CONFIG_PPC_EMULATED_STATS and =
fix what I'm guessing is a build breakage with either patch.
- k
^ permalink raw reply
* Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree
From: Grant Likely @ 2013-10-25 20:11 UTC (permalink / raw)
To: Yuantian.Tang, galak; +Cc: devicetree, linuxppc-dev, Tang Yuantian
In-Reply-To: <1381300704-4238-1-git-send-email-Yuantian.Tang@freescale.com>
On Wed, 9 Oct 2013 14:38:24 +0800, <Yuantian.Tang@freescale.com> wrote:
> From: Tang Yuantian <yuantian.tang@freescale.com>
>
> The following SoCs will be affected: p2041, p3041, p4080,
> p5020, p5040, b4420, b4860, t4240
>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> v5:
> - refine the binding document
> - update the compatible string
> v4:
> - add binding document
> - update compatible string
> - update the reg property
> v3:
> - fix typo
> v2:
> - add t4240, b4420, b4860 support
> - remove pll/4 clock from p2041, p3041 and p5020 board
>
> .../devicetree/bindings/clock/corenet-clock.txt | 111 ++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 35 +++++++
> arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 2 +
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 35 +++++++
> arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 4 +
> arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 60 +++++++++++
> arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 4 +
> arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 60 +++++++++++
> arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 4 +
> arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 112 +++++++++++++++++++++
> arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 8 ++
> arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 42 ++++++++
> arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 2 +
> arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 60 +++++++++++
> arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 4 +
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 85 ++++++++++++++++
> arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 12 +++
> 17 files changed, 640 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/corenet-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/corenet-clock.txt b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> new file mode 100644
> index 0000000..8efc62d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/corenet-clock.txt
> @@ -0,0 +1,111 @@
> +* Clock Block on Freescale CoreNet Platforms
> +
> +Freescale CoreNet chips take primary clocking input from the external
> +SYSCLK signal. The SYSCLK input (frequency) is multiplied using
> +multiple phase locked loops (PLL) to create a variety of frequencies
> +which can then be passed to a variety of internal logic, including
> +cores and peripheral IP blocks.
> +Please refer to the Reference Manual for details.
> +
> +1. Clock Block Binding
> +
> +Required properties:
> +- compatible: Should include one or more of the following:
> + - "fsl,<chip>-clockgen": for chip specific clock block
> + - "fsl,qoriq-clockgen-[1,2].x": for chassis 1.x and 2.x clock
> +- reg: Offset and length of the clock register set
> +- clock-frequency: Indicates input clock frequency of clock block.
> + Will be set by u-boot
> +
> +Recommended properties:
> +- #ddress-cells: Specifies the number of cells used to represent
typo
> + physical base addresses. Must be present if the device has
> + sub-nodes and set to 1 if present
> +- #size-cells: Specifies the number of cells used to represent
> + the size of an address. Must be present if the device has
> + sub-nodes and set to 1 if present
> +
> +2. Clock Provider/Consumer Binding
> +
> +Most of the binding are from the common clock binding[1].
> + [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Required properties:
> +- compatible : Should include one or more of the following:
> + - "fsl,qoriq-core-pll-[1,2].x": Indicates a core PLL clock device
> + - "fsl,qoriq-core-mux-[1,2].x": Indicates a core multiplexer clock
> + device; divided from the core PLL clock
> + - "fixed-clock": From common clock binding; indicates output clock
> + of oscillator
> + - "fsl,qoriq-sysclk-[1,2].x": Indicates input system clock
> +- #clock-cells: From common clock binding; indicates the number of
> + output clock. 0 is for one output clock; 1 for more than one clock
> +
> +Recommended properties:
> +- clocks: Should be the phandle of input parent clock
> +- clock-names: From common clock binding, indicates the clock name
> +- clock-output-names: From common clock binding, indicates the names of
> + output clocks
> +- reg: Should be the offset and length of clock block base address.
> + The length should be 4.
Binding looks reasonable to me.
g.
> +
> +Example for clock block and clock provider:
> +/ {
> + clockgen: global-utilities@e1000 {
> + compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> + reg = <0xe1000 0x1000>;
> + clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> + };
> + }
> +
> +Example for clock consumer:
> +
> +/ {
> + cpu0: PowerPC,e5500@0 {
> + ...
> + clocks = <&mux0>;
> + ...
> + };
> + }
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> index 5a6615d..e910e82 100644
> --- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
> @@ -86,6 +86,41 @@
>
> clockgen: global-utilities@e1000 {
> compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2", "pll1-div4";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
> + <&pll1 0>, <&pll1 1>, <&pll1 2>;
> + clock-names = "pll0_0", "pll0_1", "pll0_2",
> + "pll1_0", "pll1_1", "pll1_2";
> + clock-output-names = "cmux0";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> index 7b4426e..a11126b 100644
> --- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
> @@ -62,11 +62,13 @@
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> };
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> index e5cf6c8..5cfcfe4 100644
> --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
> @@ -130,6 +130,41 @@
>
> clockgen: global-utilities@e1000 {
> compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2", "pll1-div4";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
> + <&pll1 0>, <&pll1 1>, <&pll1 2>;
> + clock-names = "pll0_0", "pll0_1", "pll0_2",
> + "pll1_0", "pll1_1", "pll1_2";
> + clock-output-names = "cmux0";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> index 5263fa4..185a231 100644
> --- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
> @@ -62,21 +62,25 @@
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> cpu2: PowerPC,e6500@4 {
> device_type = "cpu";
> reg = <4 5>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> cpu3: PowerPC,e6500@6 {
> device_type = "cpu";
> reg = <6 7>;
> + clocks = <&mux0>;
> next-level-cache = <&L2>;
> };
> };
> diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> index dc6cc5a..f3f7f65 100644
> --- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
> @@ -308,6 +308,66 @@
> compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
> reg = <0xe1000 0x1000>;
> clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> +
> + mux2: mux2@40 {
> + #clock-cells = <0>;
> + reg = <0x40 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux2";
> + };
> +
> + mux3: mux3@60 {
> + #clock-cells = <0>;
> + reg = <0x60 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux3";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> index 7a2697d..22f3b14 100644
> --- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
> @@ -81,6 +81,7 @@
> cpu0: PowerPC,e500mc@0 {
> device_type = "cpu";
> reg = <0>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> next-level-cache = <&cpc>;
> @@ -89,6 +90,7 @@
> cpu1: PowerPC,e500mc@1 {
> device_type = "cpu";
> reg = <1>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> next-level-cache = <&cpc>;
> @@ -97,6 +99,7 @@
> cpu2: PowerPC,e500mc@2 {
> device_type = "cpu";
> reg = <2>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_2>;
> L2_2: l2-cache {
> next-level-cache = <&cpc>;
> @@ -105,6 +108,7 @@
> cpu3: PowerPC,e500mc@3 {
> device_type = "cpu";
> reg = <3>;
> + clocks = <&mux3>;
> next-level-cache = <&L2_3>;
> L2_3: l2-cache {
> next-level-cache = <&cpc>;
> diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> index 3fa1e22..9bab9c9 100644
> --- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
> @@ -335,6 +335,66 @@
> compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
> reg = <0xe1000 0x1000>;
> clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> +
> + mux2: mux2@40 {
> + #clock-cells = <0>;
> + reg = <0x40 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux2";
> + };
> +
> + mux3: mux3@60 {
> + #clock-cells = <0>;
> + reg = <0x60 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux3";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> index c9ca2c3..468e8be 100644
> --- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
> @@ -82,6 +82,7 @@
> cpu0: PowerPC,e500mc@0 {
> device_type = "cpu";
> reg = <0>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> next-level-cache = <&cpc>;
> @@ -90,6 +91,7 @@
> cpu1: PowerPC,e500mc@1 {
> device_type = "cpu";
> reg = <1>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> next-level-cache = <&cpc>;
> @@ -98,6 +100,7 @@
> cpu2: PowerPC,e500mc@2 {
> device_type = "cpu";
> reg = <2>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_2>;
> L2_2: l2-cache {
> next-level-cache = <&cpc>;
> @@ -106,6 +109,7 @@
> cpu3: PowerPC,e500mc@3 {
> device_type = "cpu";
> reg = <3>;
> + clocks = <&mux3>;
> next-level-cache = <&L2_3>;
> L2_3: l2-cache {
> next-level-cache = <&cpc>;
> diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> index 34769a7..2108269 100644
> --- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
> @@ -355,6 +355,118 @@
> compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
> reg = <0xe1000 0x1000>;
> clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + pll2: pll2@840 {
> + #clock-cells = <1>;
> + reg = <0x840 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll2", "pll2-div2";
> + };
> +
> + pll3: pll3@860 {
> + #clock-cells = <1>;
> + reg = <0x860 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll3", "pll3-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> +
> + mux2: mux2@40 {
> + #clock-cells = <0>;
> + reg = <0x40 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux2";
> + };
> +
> + mux3: mux3@60 {
> + #clock-cells = <0>;
> + reg = <0x60 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux3";
> + };
> +
> + mux4: mux4@80 {
> + #clock-cells = <0>;
> + reg = <0x80 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> + clock-output-names = "cmux4";
> + };
> +
> + mux5: mux5@a0 {
> + #clock-cells = <0>;
> + reg = <0xa0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> + clock-output-names = "cmux5";
> + };
> +
> + mux6: mux6@c0 {
> + #clock-cells = <0>;
> + reg = <0xc0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> + clock-output-names = "cmux6";
> + };
> +
> + mux7: mux7@e0 {
> + #clock-cells = <0>;
> + reg = <0xe0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
> + clock-names = "pll2_0", "pll2_1", "pll3_0", "pll3_1";
> + clock-output-names = "cmux7";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> index 493d9a0..0040b5a 100644
> --- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
> @@ -81,6 +81,7 @@
> cpu0: PowerPC,e500mc@0 {
> device_type = "cpu";
> reg = <0>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> next-level-cache = <&cpc>;
> @@ -89,6 +90,7 @@
> cpu1: PowerPC,e500mc@1 {
> device_type = "cpu";
> reg = <1>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> next-level-cache = <&cpc>;
> @@ -97,6 +99,7 @@
> cpu2: PowerPC,e500mc@2 {
> device_type = "cpu";
> reg = <2>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_2>;
> L2_2: l2-cache {
> next-level-cache = <&cpc>;
> @@ -105,6 +108,7 @@
> cpu3: PowerPC,e500mc@3 {
> device_type = "cpu";
> reg = <3>;
> + clocks = <&mux3>;
> next-level-cache = <&L2_3>;
> L2_3: l2-cache {
> next-level-cache = <&cpc>;
> @@ -113,6 +117,7 @@
> cpu4: PowerPC,e500mc@4 {
> device_type = "cpu";
> reg = <4>;
> + clocks = <&mux4>;
> next-level-cache = <&L2_4>;
> L2_4: l2-cache {
> next-level-cache = <&cpc>;
> @@ -121,6 +126,7 @@
> cpu5: PowerPC,e500mc@5 {
> device_type = "cpu";
> reg = <5>;
> + clocks = <&mux5>;
> next-level-cache = <&L2_5>;
> L2_5: l2-cache {
> next-level-cache = <&cpc>;
> @@ -129,6 +135,7 @@
> cpu6: PowerPC,e500mc@6 {
> device_type = "cpu";
> reg = <6>;
> + clocks = <&mux6>;
> next-level-cache = <&L2_6>;
> L2_6: l2-cache {
> next-level-cache = <&cpc>;
> @@ -137,6 +144,7 @@
> cpu7: PowerPC,e500mc@7 {
> device_type = "cpu";
> reg = <7>;
> + clocks = <&mux7>;
> next-level-cache = <&L2_7>;
> L2_7: l2-cache {
> next-level-cache = <&cpc>;
> diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> index bc3ae5a..e09f8cd 100644
> --- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
> @@ -340,6 +340,48 @@
> compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
> reg = <0xe1000 0x1000>;
> clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> index 8df47fc..fe1a2e6 100644
> --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
> @@ -88,6 +88,7 @@
> cpu0: PowerPC,e5500@0 {
> device_type = "cpu";
> reg = <0>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> next-level-cache = <&cpc>;
> @@ -96,6 +97,7 @@
> cpu1: PowerPC,e5500@1 {
> device_type = "cpu";
> reg = <1>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> next-level-cache = <&cpc>;
> diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> index a91897f..109f132 100644
> --- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
> @@ -300,6 +300,66 @@
> compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
> reg = <0xe1000 0x1000>;
> clock-frequency = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux1";
> + };
> +
> + mux2: mux2@40 {
> + #clock-cells = <0>;
> + reg = <0x40 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux2";
> + };
> +
> + mux3: mux3@60 {
> + #clock-cells = <0>;
> + reg = <0x60 0x4>;
> + compatible = "fsl,qoriq-core-mux-1.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
> + clock-names = "pll0_0", "pll0_1", "pll1_0", "pll1_1";
> + clock-output-names = "cmux3";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> index 40ca943..3674686 100644
> --- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
> @@ -81,6 +81,7 @@
> cpu0: PowerPC,e5500@0 {
> device_type = "cpu";
> reg = <0>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_0>;
> L2_0: l2-cache {
> next-level-cache = <&cpc>;
> @@ -89,6 +90,7 @@
> cpu1: PowerPC,e5500@1 {
> device_type = "cpu";
> reg = <1>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_1>;
> L2_1: l2-cache {
> next-level-cache = <&cpc>;
> @@ -97,6 +99,7 @@
> cpu2: PowerPC,e5500@2 {
> device_type = "cpu";
> reg = <2>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_2>;
> L2_2: l2-cache {
> next-level-cache = <&cpc>;
> @@ -105,6 +108,7 @@
> cpu3: PowerPC,e5500@3 {
> device_type = "cpu";
> reg = <3>;
> + clocks = <&mux3>;
> next-level-cache = <&L2_3>;
> L2_3: l2-cache {
> next-level-cache = <&cpc>;
> diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> index 510afa3..d45434f 100644
> --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> @@ -370,6 +370,91 @@
> clockgen: global-utilities@e1000 {
> compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
> reg = <0xe1000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + sysclk: sysclk {
> + #clock-cells = <0>;
> + compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
> + clock-output-names = "sysclk";
> + }
> +
> + pll0: pll0@800 {
> + #clock-cells = <1>;
> + reg = <0x800 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll0", "pll0-div2", "pll0-div4";
> + };
> +
> + pll1: pll1@820 {
> + #clock-cells = <1>;
> + reg = <0x820 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll1", "pll1-div2", "pll1-div4";
> + };
> +
> + pll2: pll2@840 {
> + #clock-cells = <1>;
> + reg = <0x840 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll2", "pll2-div2", "pll2-div4";
> + };
> +
> + pll3: pll3@860 {
> + #clock-cells = <1>;
> + reg = <0x860 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll3", "pll3-div2", "pll3-div4";
> + };
> +
> + pll4: pll4@880 {
> + #clock-cells = <1>;
> + reg = <0x880 0x4>;
> + compatible = "fsl,qoriq-core-pll-2.0";
> + clocks = <&sysclk>;
> + clock-output-names = "pll4", "pll4-div2", "pll4-div4";
> + };
> +
> + mux0: mux0@0 {
> + #clock-cells = <0>;
> + reg = <0x0 0x4>;
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
> + <&pll1 0>, <&pll1 1>, <&pll1 2>,
> + <&pll2 0>, <&pll2 1>, <&pll2 2>;
> + clock-names = "pll0_0", "pll0_1", "pll0_2",
> + "pll1_0", "pll1_1", "pll1_2",
> + "pll2_0", "pll2_1", "pll2_2";
> + clock-output-names = "cmux0";
> + };
> +
> + mux1: mux1@20 {
> + #clock-cells = <0>;
> + reg = <0x20 0x4>;
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
> + <&pll1 0>, <&pll1 1>, <&pll1 2>,
> + <&pll2 0>, <&pll2 1>, <&pll2 2>;
> + clock-names = "pll0_0", "pll0_1", "pll0_2",
> + "pll1_0", "pll1_1", "pll1_2",
> + "pll2_0", "pll2_1", "pll2_2";
> + clock-output-names = "cmux1";
> + };
> +
> + mux2: mux2@40 {
> + #clock-cells = <0>;
> + reg = <0x40 0x4>;
> + compatible = "fsl,qoriq-core-mux-2.0";
> + clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
> + <&pll4 0>, <&pll4 1>, <&pll4 2>;
> + clock-names = "pll3_0", "pll3_1", "pll3_2",
> + "pll4_0", "pll4_1", "pll4_2";
> + clock-output-names = "cmux2";
> + };
> };
>
> rcpm: global-utilities@e2000 {
> diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> index a93c55a..0b8ccc5 100644
> --- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
> @@ -67,61 +67,73 @@
> cpu0: PowerPC,e6500@0 {
> device_type = "cpu";
> reg = <0 1>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_1>;
> };
> cpu1: PowerPC,e6500@2 {
> device_type = "cpu";
> reg = <2 3>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_1>;
> };
> cpu2: PowerPC,e6500@4 {
> device_type = "cpu";
> reg = <4 5>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_1>;
> };
> cpu3: PowerPC,e6500@6 {
> device_type = "cpu";
> reg = <6 7>;
> + clocks = <&mux0>;
> next-level-cache = <&L2_1>;
> };
> cpu4: PowerPC,e6500@8 {
> device_type = "cpu";
> reg = <8 9>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_2>;
> };
> cpu5: PowerPC,e6500@10 {
> device_type = "cpu";
> reg = <10 11>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_2>;
> };
> cpu6: PowerPC,e6500@12 {
> device_type = "cpu";
> reg = <12 13>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_2>;
> };
> cpu7: PowerPC,e6500@14 {
> device_type = "cpu";
> reg = <14 15>;
> + clocks = <&mux1>;
> next-level-cache = <&L2_2>;
> };
> cpu8: PowerPC,e6500@16 {
> device_type = "cpu";
> reg = <16 17>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_3>;
> };
> cpu9: PowerPC,e6500@18 {
> device_type = "cpu";
> reg = <18 19>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_3>;
> };
> cpu10: PowerPC,e6500@20 {
> device_type = "cpu";
> reg = <20 21>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_3>;
> };
> cpu11: PowerPC,e6500@22 {
> device_type = "cpu";
> reg = <22 23>;
> + clocks = <&mux2>;
> next-level-cache = <&L2_3>;
> };
> };
> --
> 1.8.0
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: IBM OpenPower 720 ipr driver woes
From: Robert Knight @ 2013-10-25 21:16 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <525FFACB.8010303@princeton.edu>
On 10/17/2013 10:57 AM, Robert Knight wrote:
> Well, it's four months later and I'm trying to get Fedora 20 Alpha to
> install on that same machine. It appears to still have the same
> problem. Did that patch ever make it into the mainline?
>
> Strangely, the kernel from the installer (using DVD image) does NOT
> have the problem, only the installed system.
Just to follow up on this.
The problem does not appear to be the kernel. Installing on one disk
succeeds in producing a bootable system every time. Installing on all
four disks (two 73 GB disks and two 146 GB disks) never succeeds.
Although there are a storm of ipr driver messages as before, that is
likely not the problem.
I'm going to continue on #fedora-ppc and the corresponding mailing list.
^ permalink raw reply
* Re: perf events ring buffer memory barrier on powerpc
From: Michael Neuling @ 2013-10-25 20:31 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Mathieu Desnoyers, Frederic Weisbecker, linux-kernel,
Linux PPC dev, anton, Victor Kaplansky
In-Reply-To: <20131025173749.GG19466@laptop.lan>
> I would argue for:
>
> READ ->data_tail READ ->data_head
> smp_rmb() (A) smp_rmb() (C)
> WRITE $data READ $data
> smp_wmb() (B) smp_mb() (D)
> STORE ->data_head WRITE ->data_tail
>
> Where A pairs with D, and B pairs with C.
>
> I don't think A needs to be a full barrier because we won't in fact
> write data until we see the store from userspace. So we simply don't
> issue the data WRITE until we observe it.
>
> OTOH, D needs to be a full barrier since it separates the data READ from
> the tail WRITE.
>
> For B a WMB is sufficient since it separates two WRITEs, and for C an
> RMB is sufficient since it separates two READs.
FWIW the testing Victor did confirms WMB is good enough on powerpc.
Thanks,
Mikey
>
> ---
> kernel/events/ring_buffer.c | 29 ++++++++++++++++++++++++++---
> 1 file changed, 26 insertions(+), 3 deletions(-)
>
> diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c
> index cd55144270b5..c91274ef4e23 100644
> --- a/kernel/events/ring_buffer.c
> +++ b/kernel/events/ring_buffer.c
> @@ -87,10 +87,31 @@ static void perf_output_put_handle(struct perf_output_handle *handle)
> goto out;
>
> /*
> - * Publish the known good head. Rely on the full barrier implied
> - * by atomic_dec_and_test() order the rb->head read and this
> - * write.
> + * Since the mmap() consumer (userspace) can run on a different CPU:
> + *
> + * kernel user
> + *
> + * READ ->data_tail READ ->data_head
> + * smp_rmb() (A) smp_rmb() (C)
> + * WRITE $data READ $data
> + * smp_wmb() (B) smp_mb() (D)
> + * STORE ->data_head WRITE ->data_tail
> + *
> + * Where A pairs with D, and B pairs with C.
> + *
> + * I don't think A needs to be a full barrier because we won't in fact
> + * write data until we see the store from userspace. So we simply don't
> + * issue the data WRITE until we observe it.
> + *
> + * OTOH, D needs to be a full barrier since it separates the data READ
> + * from the tail WRITE.
> + *
> + * For B a WMB is sufficient since it separates two WRITEs, and for C
> + * an RMB is sufficient since it separates two READs.
> + *
> + * See perf_output_begin().
> */
> + smp_wmb();
> rb->user_page->data_head = head;
>
> /*
> @@ -154,6 +175,8 @@ int perf_output_begin(struct perf_output_handle *handle,
> * Userspace could choose to issue a mb() before updating the
> * tail pointer. So that all reads will be completed before the
> * write is issued.
> + *
> + * See perf_output_put_handle().
> */
> tail = ACCESS_ONCE(rb->user_page->data_tail);
> smp_rmb();
>
^ permalink raw reply
* [PATCH 2/2] powerpc: Move local setup.h declarations to arch includes
From: Robert C Jennings @ 2013-10-25 19:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Robert C Jennings
In-Reply-To: <1382729107-13560-1-git-send-email-rcj@linux.vnet.ibm.com>
Move the few declarations from arch/powerpc/kernel/setup.h
into arch/powerpc/include/asm/setup.h. This resolves a
sparse warning for arch/powerpc/mm/numa.c which defines
do_init_bootmem() but can't include the setup.h header
in the prior path.
Resolves:
arch/powerpc/mm/numa.c:998:13:
warning: symbol 'do_init_bootmem' was not declared.
Should it be static?
Signed-off-by: Robert C Jennings <rcj@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/setup.h | 5 +++++
arch/powerpc/kernel/module.c | 3 +--
arch/powerpc/kernel/module_32.c | 3 +--
arch/powerpc/kernel/module_64.c | 3 +--
arch/powerpc/kernel/setup-common.c | 2 --
arch/powerpc/kernel/setup.h | 9 ---------
arch/powerpc/kernel/setup_32.c | 2 --
arch/powerpc/kernel/setup_64.c | 2 --
arch/powerpc/kernel/vdso.c | 3 +--
9 files changed, 9 insertions(+), 23 deletions(-)
delete mode 100644 arch/powerpc/kernel/setup.h
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index d3ca855..5e24df0 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -23,6 +23,11 @@ extern void reloc_got2(unsigned long);
#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
+extern void check_for_initrd(void);
+extern void do_init_bootmem(void);
+extern void setup_panic(void);
+extern int do_early_xmon;
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_SETUP_H */
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c
index 2d27570..9547381 100644
--- a/arch/powerpc/kernel/module.c
+++ b/arch/powerpc/kernel/module.c
@@ -25,8 +25,7 @@
#include <asm/uaccess.h>
#include <asm/firmware.h>
#include <linux/sort.h>
-
-#include "setup.h"
+#include <asm/setup.h>
LIST_HEAD(module_bug_list);
diff --git a/arch/powerpc/kernel/module_32.c b/arch/powerpc/kernel/module_32.c
index 2e3200c..6cff040 100644
--- a/arch/powerpc/kernel/module_32.c
+++ b/arch/powerpc/kernel/module_32.c
@@ -26,8 +26,7 @@
#include <linux/cache.h>
#include <linux/bug.h>
#include <linux/sort.h>
-
-#include "setup.h"
+#include <asm/setup.h>
#if 0
#define DEBUGP printk
diff --git a/arch/powerpc/kernel/module_64.c b/arch/powerpc/kernel/module_64.c
index 6ee59a0..da082e8 100644
--- a/arch/powerpc/kernel/module_64.c
+++ b/arch/powerpc/kernel/module_64.c
@@ -26,8 +26,7 @@
#include <asm/firmware.h>
#include <asm/code-patching.h>
#include <linux/sort.h>
-
-#include "setup.h"
+#include <asm/setup.h>
/* FIXME: We don't do .init separately. To do this, we'd need to have
a separate r2 value in the init and core section, and stub between
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 3d261c0..febc804 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -62,8 +62,6 @@
#include <mm/mmu_decl.h>
#include <asm/fadump.h>
-#include "setup.h"
-
#ifdef DEBUG
#include <asm/udbg.h>
#define DBG(fmt...) udbg_printf(fmt)
diff --git a/arch/powerpc/kernel/setup.h b/arch/powerpc/kernel/setup.h
deleted file mode 100644
index 4c67ad7..0000000
--- a/arch/powerpc/kernel/setup.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _POWERPC_KERNEL_SETUP_H
-#define _POWERPC_KERNEL_SETUP_H
-
-void check_for_initrd(void);
-void do_init_bootmem(void);
-void setup_panic(void);
-extern int do_early_xmon;
-
-#endif /* _POWERPC_KERNEL_SETUP_H */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index a4bbcae..b903dc5 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -40,8 +40,6 @@
#include <asm/mmu_context.h>
#include <asm/epapr_hcalls.h>
-#include "setup.h"
-
#define DBG(fmt...)
extern void bootx_init(unsigned long r4, unsigned long phys);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 278ca93..4085aaa 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -68,8 +68,6 @@
#include <asm/hugetlb.h>
#include <asm/epapr_hcalls.h>
-#include "setup.h"
-
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
#else
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 1d9c926..094e45c 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -34,8 +34,7 @@
#include <asm/firmware.h>
#include <asm/vdso.h>
#include <asm/vdso_datapage.h>
-
-#include "setup.h"
+#include <asm/setup.h>
#undef DEBUG
--
1.8.1.2
^ permalink raw reply related
* [PATCH 1/2] powerpc: Fix warnings for arch/powerpc/mm/numa.c
From: Robert C Jennings @ 2013-10-25 19:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Robert C Jennings
In-Reply-To: <1382729107-13560-1-git-send-email-rcj@linux.vnet.ibm.com>
Simple fixes for sparse warnings in this file.
Resolves:
arch/powerpc/mm/numa.c:198:24:
warning: Using plain integer as NULL pointer
arch/powerpc/mm/numa.c:1157:5:
warning: symbol 'hot_add_node_scn_to_nid' was not declared.
Should it be static?
arch/powerpc/mm/numa.c:1238:28:
warning: Using plain integer as NULL pointer
arch/powerpc/mm/numa.c:1538:6:
warning: symbol 'topology_schedule_update' was not declared.
Should it be static?
Signed-off-by: Robert C Jennings <rcj@linux.vnet.ibm.com>
---
arch/powerpc/mm/numa.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index c916127..33d6784 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -195,7 +195,7 @@ static const __be32 *of_get_usable_memory(struct device_node *memory)
u32 len;
prop = of_get_property(memory, "linux,drconf-usable-memory", &len);
if (!prop || len < sizeof(unsigned int))
- return 0;
+ return NULL;
return prop;
}
@@ -1154,7 +1154,7 @@ static int hot_add_drconf_scn_to_nid(struct device_node *memory,
* represented in the device tree as a node (i.e. memory@XXXX) for
* each memblock.
*/
-int hot_add_node_scn_to_nid(unsigned long scn_addr)
+static int hot_add_node_scn_to_nid(unsigned long scn_addr)
{
struct device_node *memory;
int nid = -1;
@@ -1235,7 +1235,7 @@ static u64 hot_add_drconf_memory_max(void)
struct device_node *memory = NULL;
unsigned int drconf_cell_cnt = 0;
u64 lmb_size = 0;
- const __be32 *dm = 0;
+ const __be32 *dm = NULL;
memory = of_find_node_by_path("/ibm,dynamic-reconfiguration-memory");
if (memory) {
@@ -1535,7 +1535,7 @@ static void topology_work_fn(struct work_struct *work)
}
static DECLARE_WORK(topology_work, topology_work_fn);
-void topology_schedule_update(void)
+static void topology_schedule_update(void)
{
schedule_work(&topology_work);
}
--
1.8.1.2
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox