* RE: [V3 01/10] perf: New conditional branch filter criteria in branch stack sampling
From: mpe@ellerman.id.au @ 2013-11-26 6:06 UTC (permalink / raw)
To: linuxppc-dev, linux-kernel; +Cc: mikey, sukadev, eranian, michaele
In-Reply-To: <1381906617-11392-2-git-send-email-khandual@linux.vnet.ibm.com>
Ideally your commit subject would contain a verb, preferably in the present
tense.
I think simply "perf: Add PERF_SAMPLE_BRANCH_COND" would be clearer.
On Wed, 2013-16-10 at 06:56:48 UTC, Anshuman Khandual wrote:
> POWER8 PMU based BHRB supports filtering for conditional branches.
> This patch introduces new branch filter PERF_SAMPLE_BRANCH_COND which
> will extend the existing perf ABI. Other architectures can provide
> this functionality with either HW filtering support (if present) or
> with SW filtering of instructions.
>
> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> Reviewed-by: Stephane Eranian <eranian@google.com>
> ---
> include/uapi/linux/perf_event.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index 0b1df41..5da52b6 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -160,8 +160,9 @@ enum perf_branch_sample_type {
> PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */
> PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */
> PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */
> + PERF_SAMPLE_BRANCH_COND = 1U << 10, /* conditional branches */
>
> - PERF_SAMPLE_BRANCH_MAX = 1U << 10, /* non-ABI */
> + PERF_SAMPLE_BRANCH_MAX = 1U << 11, /* non-ABI */
> };
This no longer applies against Linus' tree, you'll need to rebase it.
cheers
^ permalink raw reply
* [PATCH] boot: enable support for bootindex
From: Alexey Kardashevskiy @ 2013-11-26 4:07 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy, Paul Mackerras, Nikunj A Dadhania
In-Reply-To: <1385364460-24332-1-git-send-email-aik@ozlabs.ru>
QEMU supports a bootindex property for every device in the command line.
With the respective support from the QEMU side, this change is enough
to make SLOF go through the list and try to boot.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
That seems to work but it also seems too easy. What do I miss here?
---
board-qemu/slof/qemu-bootlist.fs | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/board-qemu/slof/qemu-bootlist.fs b/board-qemu/slof/qemu-bootlist.fs
index 7e9482d..4778e16 100644
--- a/board-qemu/slof/qemu-bootlist.fs
+++ b/board-qemu/slof/qemu-bootlist.fs
@@ -26,6 +26,12 @@ defer add-boot-device
;
: qemu-read-bootlist ( -- )
+ \ See if QEMU has set exact boot device list
+ " qemu,boot-list" get-chosen IF
+ s" boot-device" $setenv
+ EXIT
+ THEN
+
0 0 set-boot-device
" qemu,boot-device" get-chosen not IF
--
1.8.4.rc4
^ permalink raw reply related
* Re: [PATCH 1/9 v2] pci:msi: add weak function for returning msi region info
From: Bjorn Helgaas @ 2013-11-25 23:36 UTC (permalink / raw)
To: Bharat Bhushan
Cc: linux-pci, joro, stuart.yoder, iommu, agraf, Bharat Bhushan,
alex.williamson, scottwood, linuxppc-dev, linux-kernel
In-Reply-To: <1384838233-24847-2-git-send-email-Bharat.Bhushan@freescale.com>
On Tue, Nov 19, 2013 at 10:47:05AM +0530, Bharat Bhushan wrote:
> In Aperture type of IOMMU (like FSL PAMU), VFIO-iommu system need to know
> the MSI region to map its window in h/w. This patch just defines the
> required weak functions only and will be used by followup patches.
>
> Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
> ---
> v1->v2
> - Added description on "struct msi_region"
>
> drivers/pci/msi.c | 22 ++++++++++++++++++++++
> include/linux/msi.h | 14 ++++++++++++++
> 2 files changed, 36 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index d5f90d6..2643a29 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -67,6 +67,28 @@ int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
> return chip->check_device(chip, dev, nvec, type);
> }
>
> +int __weak arch_msi_get_region_count(void)
> +{
> + return 0;
> +}
> +
> +int __weak arch_msi_get_region(int region_num, struct msi_region *region)
> +{
> + return 0;
> +}
> +
> +int msi_get_region_count(void)
> +{
> + return arch_msi_get_region_count();
> +}
> +EXPORT_SYMBOL(msi_get_region_count);
> +
> +int msi_get_region(int region_num, struct msi_region *region)
> +{
> + return arch_msi_get_region(region_num, region);
> +}
> +EXPORT_SYMBOL(msi_get_region);
> +
> int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
> {
> struct msi_desc *entry;
> diff --git a/include/linux/msi.h b/include/linux/msi.h
> index b17ead8..ade1480 100644
> --- a/include/linux/msi.h
> +++ b/include/linux/msi.h
> @@ -51,6 +51,18 @@ struct msi_desc {
> };
>
> /*
> + * This structure is used to get
> + * - physical address
> + * - size
> + * of a msi region
> + */
> +struct msi_region {
> + int region_num; /* MSI region number */
> + dma_addr_t addr; /* Address of MSI region */
> + size_t size; /* Size of MSI region */
> +};
> +
> +/*
> * The arch hooks to setup up msi irqs. Those functions are
> * implemented as weak symbols so that they /can/ be overriden by
> * architecture specific code if needed.
> @@ -64,6 +76,8 @@ void arch_restore_msi_irqs(struct pci_dev *dev, int irq);
>
> void default_teardown_msi_irqs(struct pci_dev *dev);
> void default_restore_msi_irqs(struct pci_dev *dev, int irq);
> +int arch_msi_get_region_count(void);
> +int arch_msi_get_region(int region_num, struct msi_region *region);
It doesn't look like any of this (struct msi_region, msi_get_region(),
msi_get_region_count()) is actually used by drivers/pci/msi.c, so I don't
think it needs to be declared in generic code. It looks like it's only
used in drivers/vfio/vfio_iommu_fsl_pamu.c, where you already know you have
an FSL IOMMU, and you can just call FSL-specific interfaces directly.
Bjorn
>
> struct msi_chip {
> struct module *owner;
> --
> 1.7.0.4
>
>
^ permalink raw reply
* [PATCH 3/3 v3] powerpc: cleanup panic_timeout
From: Jason Baron @ 2013-11-25 23:23 UTC (permalink / raw)
To: mingo; +Cc: felipe.contreras, linux-kernel, ralf, paulus, akpm, linuxppc-dev
In-Reply-To: <cover.1385418410.git.jbaron@akamai.com>
Default CONFIG_PANIC_TIMEOUT to 180 seconds on powerpc. The pSeries continue
to set the timeout to 10 seconds at run-time. Thus, there's a small window
where we don't have the correct value on pSeries, but if this is only run-time
discoverable we don't have a better option. In any case, if the user changes
the default setting of 180 seconds, we honor that user setting.
Signed-off-by: Jason Baron <jbaron@akamai.com>
---
arch/powerpc/Kconfig | 4 ++++
arch/powerpc/include/asm/setup.h | 1 +
arch/powerpc/kernel/setup_32.c | 3 ---
arch/powerpc/kernel/setup_64.c | 3 ---
arch/powerpc/platforms/pseries/setup.c | 2 +-
5 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b44b52c..b2be8e8 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -147,6 +147,10 @@ config EARLY_PRINTK
bool
default y
+config PANIC_TIMEOUT
+ int
+ default 180
+
config COMPAT
bool
default y if PPC64
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index 703a841..11ba86e 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -26,6 +26,7 @@ extern void reloc_got2(unsigned long);
void check_for_initrd(void);
void do_init_bootmem(void);
void setup_panic(void);
+#define ARCH_PANIC_TIMEOUT 180
#endif /* !__ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index b903dc5..2b0da27 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -296,9 +296,6 @@ void __init setup_arch(char **cmdline_p)
if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
ucache_bsize = icache_bsize = dcache_bsize;
- /* reboot on panic */
- panic_timeout = 180;
-
if (ppc_md.panic)
setup_panic();
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 4085aaa..856dd4e 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -588,9 +588,6 @@ void __init setup_arch(char **cmdline_p)
dcache_bsize = ppc64_caches.dline_size;
icache_bsize = ppc64_caches.iline_size;
- /* reboot on panic */
- panic_timeout = 180;
-
if (ppc_md.panic)
setup_panic();
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index c1f1908..6f76ae4 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -470,7 +470,7 @@ static long pseries_little_endian_exceptions(void)
static void __init pSeries_setup_arch(void)
{
- panic_timeout = 10;
+ set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
/* Discover PIC type and setup ppc_md accordingly */
pseries_discover_pic();
--
1.8.2
^ permalink raw reply related
* Re: [PATCH 01/12][v3] pci: fsl: derive the common PCI driver to drivers/pci/host
From: Bjorn Helgaas @ 2013-11-25 23:01 UTC (permalink / raw)
To: Minghuan Lian; +Cc: Scott Wood, linux-pci, linuxppc-dev, Zang Roy-R61911
In-Reply-To: <1382524894-15164-1-git-send-email-Minghuan.Lian@freescale.com>
On Wed, Oct 23, 2013 at 06:41:23PM +0800, Minghuan Lian wrote:
> The Freescale's Layerscape series processors will use ARM cores.
> The LS1's PCIe controllers is the same as T4240's. So it's better
> the PCIe controller driver can support PowerPC and ARM
> simultaneously. This patch is for this purpose. It derives
> the common functions from arch/powerpc/sysdev/fsl_pci.c to
> drivers/pci/host/pci-fsl-common.c and leaves the architecture
> specific functions which should be implemented in arch related files.
>
> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
It doesn't look like we have a consensus on how to proceed here, so I'm
ignoring this series for now. Let me know if there really *is* agreement,
or if there's some subset of this work that everybody can agree on. It'd
be good to make forward progress, even if it's not completely perfect yet.
Bjorn
> ---
> change log:
> v2-v3:
> no change
> v1-v2:
> 1. rename pci.h to pci-common.h
> 2. rename pci-fsl.c to pci-fsl-common.c
>
> Based on upstream master.
> Based on the discussion of RFC version here
> http://patchwork.ozlabs.org/patch/274487/
>
> arch/powerpc/sysdev/fsl_pci.c | 521 +-----------------
> arch/powerpc/sysdev/fsl_pci.h | 89 ----
> .../fsl_pci.c => drivers/pci/host/pci-fsl-common.c | 591 +--------------------
> .../fsl_pci.h => include/linux/fsl/pci-common.h | 45 +-
> 4 files changed, 7 insertions(+), 1239 deletions(-)
> copy arch/powerpc/sysdev/fsl_pci.c => drivers/pci/host/pci-fsl-common.c (54%)
> copy arch/powerpc/sysdev/fsl_pci.h => include/linux/fsl/pci-common.h (79%)
>
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
> index ccfb50d..26039e3 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/arch/powerpc/sysdev/fsl_pci.c
> @@ -27,6 +27,7 @@
> #include <linux/log2.h>
> #include <linux/slab.h>
> #include <linux/uaccess.h>
> +#include <linux/fsl/pci-common.h>
>
> #include <asm/io.h>
> #include <asm/prom.h>
> @@ -58,57 +59,8 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
> return;
> }
>
> -static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
> - int, int, u32 *);
> -
> -static int fsl_pcie_check_link(struct pci_controller *hose)
> -{
> - u32 val = 0;
> -
> - if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
> - if (hose->ops->read == fsl_indirect_read_config) {
> - struct pci_bus bus;
> - bus.number = hose->first_busno;
> - bus.sysdata = hose;
> - bus.ops = hose->ops;
> - indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
> - } else
> - early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
> - if (val < PCIE_LTSSM_L0)
> - return 1;
> - } else {
> - struct ccsr_pci __iomem *pci = hose->private_data;
> - /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
> - val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
> - >> PEX_CSR0_LTSSM_SHIFT;
> - if (val != PEX_CSR0_LTSSM_L0)
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> -static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
> - int offset, int len, u32 *val)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> -
> - if (fsl_pcie_check_link(hose))
> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> - else
> - hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> -
> - return indirect_read_config(bus, devfn, offset, len, val);
> -}
> -
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
>
> -static struct pci_ops fsl_indirect_pcie_ops =
> -{
> - .read = fsl_indirect_read_config,
> - .write = indirect_write_config,
> -};
> -
> #define MAX_PHYS_ADDR_BITS 40
> static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
>
> @@ -132,291 +84,6 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
> return 0;
> }
>
> -static int setup_one_atmu(struct ccsr_pci __iomem *pci,
> - unsigned int index, const struct resource *res,
> - resource_size_t offset)
> -{
> - resource_size_t pci_addr = res->start - offset;
> - resource_size_t phys_addr = res->start;
> - resource_size_t size = resource_size(res);
> - u32 flags = 0x80044000; /* enable & mem R/W */
> - unsigned int i;
> -
> - pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
> - (u64)res->start, (u64)size);
> -
> - if (res->flags & IORESOURCE_PREFETCH)
> - flags |= 0x10000000; /* enable relaxed ordering */
> -
> - for (i = 0; size > 0; i++) {
> - unsigned int bits = min(ilog2(size),
> - __ffs(pci_addr | phys_addr));
> -
> - if (index + i >= 5)
> - return -1;
> -
> - out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
> - out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
> - out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
> - out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
> -
> - pci_addr += (resource_size_t)1U << bits;
> - phys_addr += (resource_size_t)1U << bits;
> - size -= (resource_size_t)1U << bits;
> - }
> -
> - return i;
> -}
> -
> -/* atmu setup for fsl pci/pcie controller */
> -static void setup_pci_atmu(struct pci_controller *hose)
> -{
> - struct ccsr_pci __iomem *pci = hose->private_data;
> - int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
> - u64 mem, sz, paddr_hi = 0;
> - u64 offset = 0, paddr_lo = ULLONG_MAX;
> - u32 pcicsrbar = 0, pcicsrbar_sz;
> - u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
> - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
> - const char *name = hose->dn->full_name;
> - const u64 *reg;
> - int len;
> -
> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> - if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
> - win_idx = 2;
> - start_idx = 0;
> - end_idx = 3;
> - }
> - }
> -
> - /* Disable all windows (except powar0 since it's ignored) */
> - for(i = 1; i < 5; i++)
> - out_be32(&pci->pow[i].powar, 0);
> - for (i = start_idx; i < end_idx; i++)
> - out_be32(&pci->piw[i].piwar, 0);
> -
> - /* Setup outbound MEM window */
> - for(i = 0, j = 1; i < 3; i++) {
> - if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
> - continue;
> -
> - paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
> - paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
> -
> - /* We assume all memory resources have the same offset */
> - offset = hose->mem_offset[i];
> - n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
> -
> - if (n < 0 || j >= 5) {
> - pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
> - hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
> - } else
> - j += n;
> - }
> -
> - /* Setup outbound IO window */
> - if (hose->io_resource.flags & IORESOURCE_IO) {
> - if (j >= 5) {
> - pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
> - } else {
> - pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
> - "phy base 0x%016llx.\n",
> - (u64)hose->io_resource.start,
> - (u64)resource_size(&hose->io_resource),
> - (u64)hose->io_base_phys);
> - out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
> - out_be32(&pci->pow[j].potear, 0);
> - out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
> - /* Enable, IO R/W */
> - out_be32(&pci->pow[j].powar, 0x80088000
> - | (ilog2(hose->io_resource.end
> - - hose->io_resource.start + 1) - 1));
> - }
> - }
> -
> - /* convert to pci address space */
> - paddr_hi -= offset;
> - paddr_lo -= offset;
> -
> - if (paddr_hi == paddr_lo) {
> - pr_err("%s: No outbound window space\n", name);
> - return;
> - }
> -
> - if (paddr_lo == 0) {
> - pr_err("%s: No space for inbound window\n", name);
> - return;
> - }
> -
> - /* setup PCSRBAR/PEXCSRBAR */
> - early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
> - early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
> - pcicsrbar_sz = ~pcicsrbar_sz + 1;
> -
> - if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
> - (paddr_lo > 0x100000000ull))
> - pcicsrbar = 0x100000000ull - pcicsrbar_sz;
> - else
> - pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
> - early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
> -
> - paddr_lo = min(paddr_lo, (u64)pcicsrbar);
> -
> - pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
> -
> - /* Setup inbound mem window */
> - mem = memblock_end_of_DRAM();
> -
> - /*
> - * The msi-address-64 property, if it exists, indicates the physical
> - * address of the MSIIR register. Normally, this register is located
> - * inside CCSR, so the ATMU that covers all of CCSR is used. But if
> - * this property exists, then we normally need to create a new ATMU
> - * for it. For now, however, we cheat. The only entity that creates
> - * this property is the Freescale hypervisor, and the address is
> - * specified in the partition configuration. Typically, the address
> - * is located in the page immediately after the end of DDR. If so, we
> - * can avoid allocating a new ATMU by extending the DDR ATMU by one
> - * page.
> - */
> - reg = of_get_property(hose->dn, "msi-address-64", &len);
> - if (reg && (len == sizeof(u64))) {
> - u64 address = be64_to_cpup(reg);
> -
> - if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
> - pr_info("%s: extending DDR ATMU to cover MSIIR", name);
> - mem += PAGE_SIZE;
> - } else {
> - /* TODO: Create a new ATMU for MSIIR */
> - pr_warn("%s: msi-address-64 address of %llx is "
> - "unsupported\n", name, address);
> - }
> - }
> -
> - sz = min(mem, paddr_lo);
> - mem_log = ilog2(sz);
> -
> - /* PCIe can overmap inbound & outbound since RX & TX are separated */
> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> - /* Size window to exact size if power-of-two or one size up */
> - if ((1ull << mem_log) != mem) {
> - mem_log++;
> - if ((1ull << mem_log) > mem)
> - pr_info("%s: Setting PCI inbound window "
> - "greater than memory size\n", name);
> - }
> -
> - piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
> -
> - /* Setup inbound memory window */
> - out_be32(&pci->piw[win_idx].pitar, 0x00000000);
> - out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
> - out_be32(&pci->piw[win_idx].piwar, piwar);
> - win_idx--;
> -
> - hose->dma_window_base_cur = 0x00000000;
> - hose->dma_window_size = (resource_size_t)sz;
> -
> - /*
> - * if we have >4G of memory setup second PCI inbound window to
> - * let devices that are 64-bit address capable to work w/o
> - * SWIOTLB and access the full range of memory
> - */
> - if (sz != mem) {
> - mem_log = ilog2(mem);
> -
> - /* Size window up if we dont fit in exact power-of-2 */
> - if ((1ull << mem_log) != mem)
> - mem_log++;
> -
> - piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
> -
> - /* Setup inbound memory window */
> - out_be32(&pci->piw[win_idx].pitar, 0x00000000);
> - out_be32(&pci->piw[win_idx].piwbear,
> - pci64_dma_offset >> 44);
> - out_be32(&pci->piw[win_idx].piwbar,
> - pci64_dma_offset >> 12);
> - out_be32(&pci->piw[win_idx].piwar, piwar);
> -
> - /*
> - * install our own dma_set_mask handler to fixup dma_ops
> - * and dma_offset
> - */
> - ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
> -
> - pr_info("%s: Setup 64-bit PCI DMA window\n", name);
> - }
> - } else {
> - u64 paddr = 0;
> -
> - /* Setup inbound memory window */
> - out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
> - out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
> - out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
> - win_idx--;
> -
> - paddr += 1ull << mem_log;
> - sz -= 1ull << mem_log;
> -
> - if (sz) {
> - mem_log = ilog2(sz);
> - piwar |= (mem_log - 1);
> -
> - out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
> - out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
> - out_be32(&pci->piw[win_idx].piwar, piwar);
> - win_idx--;
> -
> - paddr += 1ull << mem_log;
> - }
> -
> - hose->dma_window_base_cur = 0x00000000;
> - hose->dma_window_size = (resource_size_t)paddr;
> - }
> -
> - if (hose->dma_window_size < mem) {
> -#ifdef CONFIG_SWIOTLB
> - ppc_swiotlb_enable = 1;
> -#else
> - pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
> - "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
> - name);
> -#endif
> - /* adjusting outbound windows could reclaim space in mem map */
> - if (paddr_hi < 0xffffffffull)
> - pr_warning("%s: WARNING: Outbound window cfg leaves "
> - "gaps in memory map. Adjusting the memory map "
> - "could reduce unnecessary bounce buffering.\n",
> - name);
> -
> - pr_info("%s: DMA window size is 0x%llx\n", name,
> - (u64)hose->dma_window_size);
> - }
> -}
> -
> -static void __init setup_pci_cmd(struct pci_controller *hose)
> -{
> - u16 cmd;
> - int cap_x;
> -
> - early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
> - cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
> - | PCI_COMMAND_IO;
> - early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
> -
> - cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
> - if (cap_x) {
> - int pci_x_cmd = cap_x + PCI_X_CMD;
> - cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
> - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
> - early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
> - } else {
> - early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
> - }
> -}
> -
> void fsl_pcibios_fixup_bus(struct pci_bus *bus)
> {
> struct pci_controller *hose = pci_bus_to_host(bus);
> @@ -454,112 +121,6 @@ void fsl_pcibios_fixup_bus(struct pci_bus *bus)
> }
> }
>
> -int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
> -{
> - int len;
> - struct pci_controller *hose;
> - struct resource rsrc;
> - const int *bus_range;
> - u8 hdr_type, progif;
> - struct device_node *dev;
> - struct ccsr_pci __iomem *pci;
> -
> - dev = pdev->dev.of_node;
> -
> - if (!of_device_is_available(dev)) {
> - pr_warning("%s: disabled\n", dev->full_name);
> - return -ENODEV;
> - }
> -
> - pr_debug("Adding PCI host bridge %s\n", dev->full_name);
> -
> - /* Fetch host bridge registers address */
> - if (of_address_to_resource(dev, 0, &rsrc)) {
> - printk(KERN_WARNING "Can't get pci register base!");
> - return -ENOMEM;
> - }
> -
> - /* Get bus range if any */
> - bus_range = of_get_property(dev, "bus-range", &len);
> - if (bus_range == NULL || len < 2 * sizeof(int))
> - printk(KERN_WARNING "Can't get bus-range for %s, assume"
> - " bus 0\n", dev->full_name);
> -
> - pci_add_flags(PCI_REASSIGN_ALL_BUS);
> - hose = pcibios_alloc_controller(dev);
> - if (!hose)
> - return -ENOMEM;
> -
> - /* set platform device as the parent */
> - hose->parent = &pdev->dev;
> - hose->first_busno = bus_range ? bus_range[0] : 0x0;
> - hose->last_busno = bus_range ? bus_range[1] : 0xff;
> -
> - pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
> - (u64)rsrc.start, (u64)resource_size(&rsrc));
> -
> - pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
> - if (!hose->private_data)
> - goto no_bridge;
> -
> - setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
> - PPC_INDIRECT_TYPE_BIG_ENDIAN);
> -
> - if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
> - hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
> -
> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> - /* use fsl_indirect_read_config for PCIe */
> - hose->ops = &fsl_indirect_pcie_ops;
> - /* For PCIE read HEADER_TYPE to identify controler mode */
> - early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
> - if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
> - goto no_bridge;
> -
> - } else {
> - /* For PCI read PROG to identify controller mode */
> - early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
> - if ((progif & 1) == 1)
> - goto no_bridge;
> - }
> -
> - setup_pci_cmd(hose);
> -
> - /* check PCI express link status */
> - if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
> - hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
> - PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
> - if (fsl_pcie_check_link(hose))
> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> - }
> -
> - printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
> - "Firmware bus number: %d->%d\n",
> - (unsigned long long)rsrc.start, hose->first_busno,
> - hose->last_busno);
> -
> - pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
> - hose, hose->cfg_addr, hose->cfg_data);
> -
> - /* Interpret the "ranges" property */
> - /* This also maps the I/O region and sets isa_io/mem_base */
> - pci_process_bridge_OF_ranges(hose, dev, is_primary);
> -
> - /* Setup PEX window registers */
> - setup_pci_atmu(hose);
> -
> - return 0;
> -
> -no_bridge:
> - iounmap(hose->private_data);
> - /* unmap cfg_data & cfg_addr separately if not on same page */
> - if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
> - ((unsigned long)hose->cfg_addr & PAGE_MASK))
> - iounmap(hose->cfg_data);
> - iounmap(hose->cfg_addr);
> - pcibios_free_controller(hose);
> - return -ENODEV;
> -}
> #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
>
> DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
> @@ -1029,26 +590,6 @@ int fsl_pci_mcheck_exception(struct pt_regs *regs)
> #endif
>
> #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> -static const struct of_device_id pci_ids[] = {
> - { .compatible = "fsl,mpc8540-pci", },
> - { .compatible = "fsl,mpc8548-pcie", },
> - { .compatible = "fsl,mpc8610-pci", },
> - { .compatible = "fsl,mpc8641-pcie", },
> - { .compatible = "fsl,qoriq-pcie-v2.1", },
> - { .compatible = "fsl,qoriq-pcie-v2.2", },
> - { .compatible = "fsl,qoriq-pcie-v2.3", },
> - { .compatible = "fsl,qoriq-pcie-v2.4", },
> - { .compatible = "fsl,qoriq-pcie-v3.0", },
> -
> - /*
> - * The following entries are for compatibility with older device
> - * trees.
> - */
> - { .compatible = "fsl,p1022-pcie", },
> - { .compatible = "fsl,p4080-pcie", },
> -
> - {},
> -};
>
> struct device_node *fsl_pci_primary;
>
> @@ -1083,64 +624,4 @@ void fsl_pci_assign_primary(void)
> }
> }
> }
> -
> -static int fsl_pci_probe(struct platform_device *pdev)
> -{
> - int ret;
> - struct device_node *node;
> -
> - node = pdev->dev.of_node;
> - ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
> -
> - mpc85xx_pci_err_probe(pdev);
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_PM
> -static int fsl_pci_resume(struct device *dev)
> -{
> - struct pci_controller *hose;
> - struct resource pci_rsrc;
> -
> - hose = pci_find_hose_for_OF_device(dev->of_node);
> - if (!hose)
> - return -ENODEV;
> -
> - if (of_address_to_resource(dev->of_node, 0, &pci_rsrc)) {
> - dev_err(dev, "Get pci register base failed.");
> - return -ENODEV;
> - }
> -
> - setup_pci_atmu(hose);
> -
> - return 0;
> -}
> -
> -static const struct dev_pm_ops pci_pm_ops = {
> - .resume = fsl_pci_resume,
> -};
> -
> -#define PCI_PM_OPS (&pci_pm_ops)
> -
> -#else
> -
> -#define PCI_PM_OPS NULL
> -
> -#endif
> -
> -static struct platform_driver fsl_pci_driver = {
> - .driver = {
> - .name = "fsl-pci",
> - .pm = PCI_PM_OPS,
> - .of_match_table = pci_ids,
> - },
> - .probe = fsl_pci_probe,
> -};
> -
> -static int __init fsl_pci_init(void)
> -{
> - return platform_driver_register(&fsl_pci_driver);
> -}
> -arch_initcall(fsl_pci_init);
> #endif
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
> index 8d455df..ce77aad 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/arch/powerpc/sysdev/fsl_pci.h
> @@ -21,95 +21,6 @@ struct platform_device;
> #define PCI_FSL_BRR1 0xbf8
> #define PCI_FSL_BRR1_VER 0xffff
>
> -#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> -#define PCIE_LTSSM_L0 0x16 /* L0 state */
> -#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
> -#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
> -#define PIWAR_EN 0x80000000 /* Enable */
> -#define PIWAR_PF 0x20000000 /* prefetch */
> -#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
> -#define PIWAR_READ_SNOOP 0x00050000
> -#define PIWAR_WRITE_SNOOP 0x00005000
> -#define PIWAR_SZ_MASK 0x0000003f
> -
> -/* PCI/PCI Express outbound window reg */
> -struct pci_outbound_window_regs {
> - __be32 potar; /* 0x.0 - Outbound translation address register */
> - __be32 potear; /* 0x.4 - Outbound translation extended address register */
> - __be32 powbar; /* 0x.8 - Outbound window base address register */
> - u8 res1[4];
> - __be32 powar; /* 0x.10 - Outbound window attributes register */
> - u8 res2[12];
> -};
> -
> -/* PCI/PCI Express inbound window reg */
> -struct pci_inbound_window_regs {
> - __be32 pitar; /* 0x.0 - Inbound translation address register */
> - u8 res1[4];
> - __be32 piwbar; /* 0x.8 - Inbound window base address register */
> - __be32 piwbear; /* 0x.c - Inbound window base extended address register */
> - __be32 piwar; /* 0x.10 - Inbound window attributes register */
> - u8 res2[12];
> -};
> -
> -/* PCI/PCI Express IO block registers for 85xx/86xx */
> -struct ccsr_pci {
> - __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
> - __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
> - __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
> - __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
> - __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
> - __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
> - __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
> - u8 res2[4];
> - __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
> - __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
> - __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
> - __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
> - u8 res3[3016];
> - __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
> - __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
> -
> -/* PCI/PCI Express outbound window 0-4
> - * Window 0 is the default window and is the only window enabled upon reset.
> - * The default outbound register set is used when a transaction misses
> - * in all of the other outbound windows.
> - */
> - struct pci_outbound_window_regs pow[5];
> - u8 res14[96];
> - struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
> - u8 res6[96];
> -/* PCI/PCI Express inbound window 3-0
> - * inbound window 1 supports only a 32-bit base address and does not
> - * define an inbound window base extended address register.
> - */
> - struct pci_inbound_window_regs piw[4];
> -
> - __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
> - u8 res21[4];
> - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
> - u8 res22[4];
> - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
> - u8 res23[12];
> - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
> - u8 res24[4];
> - __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
> - __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
> - __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
> - __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
> - u8 res_e38[200];
> - __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
> - u8 res_f04[16];
> - __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
> -#define PEX_CSR0_LTSSM_MASK 0xFC
> -#define PEX_CSR0_LTSSM_SHIFT 2
> -#define PEX_CSR0_LTSSM_L0 0x11
> - __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
> - u8 res_f1c[228];
> -
> -};
> -
> -extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
> extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
> extern int mpc83xx_add_bridge(struct device_node *dev);
> u64 fsl_pci_immrbar_base(struct pci_controller *hose);
> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/drivers/pci/host/pci-fsl-common.c
> similarity index 54%
> copy from arch/powerpc/sysdev/fsl_pci.c
> copy to drivers/pci/host/pci-fsl-common.c
> index ccfb50d..69d338b 100644
> --- a/arch/powerpc/sysdev/fsl_pci.c
> +++ b/drivers/pci/host/pci-fsl-common.c
> @@ -1,5 +1,5 @@
> /*
> - * MPC83xx/85xx/86xx PCI/PCIE support routing.
> + * 85xx/86xx/LS PCI/PCIE support routing.
> *
> * Copyright 2007-2012 Freescale Semiconductor, Inc.
> * Copyright 2008-2009 MontaVista Software, Inc.
> @@ -8,9 +8,6 @@
> * Recode: ZHANG WEI <wei.zhang@freescale.com>
> * Rewrite the routing for Frescale PCI and PCI Express
> * Roy Zang <tie-fei.zang@freescale.com>
> - * MPC83xx PCI-Express support:
> - * Tony Li <tony.li@freescale.com>
> - * Anton Vorontsov <avorontsov@ru.mvista.com>
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms of the GNU General Public License as published by the
> @@ -38,29 +35,6 @@
> #include <sysdev/fsl_soc.h>
> #include <sysdev/fsl_pci.h>
>
> -static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
> -
> -static void quirk_fsl_pcie_header(struct pci_dev *dev)
> -{
> - u8 hdr_type;
> -
> - /* if we aren't a PCIe don't bother */
> - if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
> - return;
> -
> - /* if we aren't in host mode don't bother */
> - pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
> - if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
> - return;
> -
> - dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> - fsl_pcie_bus_fixup = 1;
> - return;
> -}
> -
> -static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
> - int, int, u32 *);
> -
> static int fsl_pcie_check_link(struct pci_controller *hose)
> {
> u32 val = 0;
> @@ -109,29 +83,6 @@ static struct pci_ops fsl_indirect_pcie_ops =
> .write = indirect_write_config,
> };
>
> -#define MAX_PHYS_ADDR_BITS 40
> -static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
> -
> -static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
> -{
> - if (!dev->dma_mask || !dma_supported(dev, dma_mask))
> - return -EIO;
> -
> - /*
> - * Fixup PCI devices that are able to DMA to above the physical
> - * address width of the SoC such that we can address any internal
> - * SoC address from across PCI if needed
> - */
> - if ((dev->bus == &pci_bus_type) &&
> - dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
> - set_dma_ops(dev, &dma_direct_ops);
> - set_dma_offset(dev, pci64_dma_offset);
> - }
> -
> - *dev->dma_mask = dma_mask;
> - return 0;
> -}
> -
> static int setup_one_atmu(struct ccsr_pci __iomem *pci,
> unsigned int index, const struct resource *res,
> resource_size_t offset)
> @@ -417,43 +368,6 @@ static void __init setup_pci_cmd(struct pci_controller *hose)
> }
> }
>
> -void fsl_pcibios_fixup_bus(struct pci_bus *bus)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> - int i, is_pcie = 0, no_link;
> -
> - /* The root complex bridge comes up with bogus resources,
> - * we copy the PHB ones in.
> - *
> - * With the current generic PCI code, the PHB bus no longer
> - * has bus->resource[0..4] set, so things are a bit more
> - * tricky.
> - */
> -
> - if (fsl_pcie_bus_fixup)
> - is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
> - no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
> -
> - if (bus->parent == hose->bus && (is_pcie || no_link)) {
> - for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
> - struct resource *res = bus->resource[i];
> - struct resource *par;
> -
> - if (!res)
> - continue;
> - if (i == 0)
> - par = &hose->io_resource;
> - else if (i < 4)
> - par = &hose->mem_resources[i-1];
> - else par = NULL;
> -
> - res->start = par ? par->start : 0;
> - res->end = par ? par->end : 0;
> - res->flags = par ? par->flags : 0;
> - }
> - }
> -}
> -
> int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
> {
> int len;
> @@ -560,475 +474,7 @@ no_bridge:
> pcibios_free_controller(hose);
> return -ENODEV;
> }
> -#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
> -
> -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
> -
> -#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
> -struct mpc83xx_pcie_priv {
> - void __iomem *cfg_type0;
> - void __iomem *cfg_type1;
> - u32 dev_base;
> -};
> -
> -struct pex_inbound_window {
> - u32 ar;
> - u32 tar;
> - u32 barl;
> - u32 barh;
> -};
> -
> -/*
> - * With the convention of u-boot, the PCIE outbound window 0 serves
> - * as configuration transactions outbound.
> - */
> -#define PEX_OUTWIN0_BAR 0xCA4
> -#define PEX_OUTWIN0_TAL 0xCA8
> -#define PEX_OUTWIN0_TAH 0xCAC
> -#define PEX_RC_INWIN_BASE 0xE60
> -#define PEX_RCIWARn_EN 0x1
> -
> -static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> -
> - if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> - /*
> - * Workaround for the HW bug: for Type 0 configure transactions the
> - * PCI-E controller does not check the device number bits and just
> - * assumes that the device number bits are 0.
> - */
> - if (bus->number == hose->first_busno ||
> - bus->primary == hose->first_busno) {
> - if (devfn & 0xf8)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> - }
> -
> - if (ppc_md.pci_exclude_device) {
> - if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
> - return PCIBIOS_DEVICE_NOT_FOUND;
> - }
> -
> - return PCIBIOS_SUCCESSFUL;
> -}
> -
> -static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
> - unsigned int devfn, int offset)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> - struct mpc83xx_pcie_priv *pcie = hose->dn->data;
> - u32 dev_base = bus->number << 24 | devfn << 16;
> - int ret;
> -
> - ret = mpc83xx_pcie_exclude_device(bus, devfn);
> - if (ret)
> - return NULL;
> -
> - offset &= 0xfff;
> -
> - /* Type 0 */
> - if (bus->number == hose->first_busno)
> - return pcie->cfg_type0 + offset;
> -
> - if (pcie->dev_base == dev_base)
> - goto mapped;
> -
> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
> -
> - pcie->dev_base = dev_base;
> -mapped:
> - return pcie->cfg_type1 + offset;
> -}
> -
> -static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
> - int offset, int len, u32 *val)
> -{
> - void __iomem *cfg_addr;
> -
> - cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
> - if (!cfg_addr)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> -
> - switch (len) {
> - case 1:
> - *val = in_8(cfg_addr);
> - break;
> - case 2:
> - *val = in_le16(cfg_addr);
> - break;
> - default:
> - *val = in_le32(cfg_addr);
> - break;
> - }
> -
> - return PCIBIOS_SUCCESSFUL;
> -}
> -
> -static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
> - int offset, int len, u32 val)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> - void __iomem *cfg_addr;
> -
> - cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
> - if (!cfg_addr)
> - return PCIBIOS_DEVICE_NOT_FOUND;
> -
> - /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
> - if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
> - val &= 0xffffff00;
> -
> - switch (len) {
> - case 1:
> - out_8(cfg_addr, val);
> - break;
> - case 2:
> - out_le16(cfg_addr, val);
> - break;
> - default:
> - out_le32(cfg_addr, val);
> - break;
> - }
> -
> - return PCIBIOS_SUCCESSFUL;
> -}
> -
> -static struct pci_ops mpc83xx_pcie_ops = {
> - .read = mpc83xx_pcie_read_config,
> - .write = mpc83xx_pcie_write_config,
> -};
> -
> -static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
> - struct resource *reg)
> -{
> - struct mpc83xx_pcie_priv *pcie;
> - u32 cfg_bar;
> - int ret = -ENOMEM;
> -
> - pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
> - if (!pcie)
> - return ret;
> -
> - pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
> - if (!pcie->cfg_type0)
> - goto err0;
> -
> - cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
> - if (!cfg_bar) {
> - /* PCI-E isn't configured. */
> - ret = -ENODEV;
> - goto err1;
> - }
> -
> - pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
> - if (!pcie->cfg_type1)
> - goto err1;
> -
> - WARN_ON(hose->dn->data);
> - hose->dn->data = pcie;
> - hose->ops = &mpc83xx_pcie_ops;
> - hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
> -
> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
> - out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
> -
> - if (fsl_pcie_check_link(hose))
> - hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
> -
> - return 0;
> -err1:
> - iounmap(pcie->cfg_type0);
> -err0:
> - kfree(pcie);
> - return ret;
> -
> -}
> -
> -int __init mpc83xx_add_bridge(struct device_node *dev)
> -{
> - int ret;
> - int len;
> - struct pci_controller *hose;
> - struct resource rsrc_reg;
> - struct resource rsrc_cfg;
> - const int *bus_range;
> - int primary;
> -
> - is_mpc83xx_pci = 1;
> -
> - if (!of_device_is_available(dev)) {
> - pr_warning("%s: disabled by the firmware.\n",
> - dev->full_name);
> - return -ENODEV;
> - }
> - pr_debug("Adding PCI host bridge %s\n", dev->full_name);
> -
> - /* Fetch host bridge registers address */
> - if (of_address_to_resource(dev, 0, &rsrc_reg)) {
> - printk(KERN_WARNING "Can't get pci register base!\n");
> - return -ENOMEM;
> - }
> -
> - memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
> -
> - if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
> - printk(KERN_WARNING
> - "No pci config register base in dev tree, "
> - "using default\n");
> - /*
> - * MPC83xx supports up to two host controllers
> - * one at 0x8500 has config space registers at 0x8300
> - * one at 0x8600 has config space registers at 0x8380
> - */
> - if ((rsrc_reg.start & 0xfffff) == 0x8500)
> - rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
> - else if ((rsrc_reg.start & 0xfffff) == 0x8600)
> - rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
> - }
> - /*
> - * Controller at offset 0x8500 is primary
> - */
> - if ((rsrc_reg.start & 0xfffff) == 0x8500)
> - primary = 1;
> - else
> - primary = 0;
> -
> - /* Get bus range if any */
> - bus_range = of_get_property(dev, "bus-range", &len);
> - if (bus_range == NULL || len < 2 * sizeof(int)) {
> - printk(KERN_WARNING "Can't get bus-range for %s, assume"
> - " bus 0\n", dev->full_name);
> - }
> -
> - pci_add_flags(PCI_REASSIGN_ALL_BUS);
> - hose = pcibios_alloc_controller(dev);
> - if (!hose)
> - return -ENOMEM;
> -
> - hose->first_busno = bus_range ? bus_range[0] : 0;
> - hose->last_busno = bus_range ? bus_range[1] : 0xff;
> -
> - if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
> - ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
> - if (ret)
> - goto err0;
> - } else {
> - setup_indirect_pci(hose, rsrc_cfg.start,
> - rsrc_cfg.start + 4, 0);
> - }
> -
> - printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
> - "Firmware bus number: %d->%d\n",
> - (unsigned long long)rsrc_reg.start, hose->first_busno,
> - hose->last_busno);
> -
> - pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
> - hose, hose->cfg_addr, hose->cfg_data);
> -
> - /* Interpret the "ranges" property */
> - /* This also maps the I/O region and sets isa_io/mem_base */
> - pci_process_bridge_OF_ranges(hose, dev, primary);
> -
> - return 0;
> -err0:
> - pcibios_free_controller(hose);
> - return ret;
> -}
> -#endif /* CONFIG_PPC_83xx */
> -
> -u64 fsl_pci_immrbar_base(struct pci_controller *hose)
> -{
> -#ifdef CONFIG_PPC_83xx
> - if (is_mpc83xx_pci) {
> - struct mpc83xx_pcie_priv *pcie = hose->dn->data;
> - struct pex_inbound_window *in;
> - int i;
> -
> - /* Walk the Root Complex Inbound windows to match IMMR base */
> - in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
> - for (i = 0; i < 4; i++) {
> - /* not enabled, skip */
> - if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
> - continue;
> -
> - if (get_immrbase() == in_le32(&in[i].tar))
> - return (u64)in_le32(&in[i].barh) << 32 |
> - in_le32(&in[i].barl);
> - }
> -
> - printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
> - }
> -#endif
> -
> -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> - if (!is_mpc83xx_pci) {
> - u32 base;
> -
> - pci_bus_read_config_dword(hose->bus,
> - PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
> - return base;
> - }
> -#endif
> -
> - return 0;
> -}
>
> -#ifdef CONFIG_E500
> -static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
> -{
> - unsigned int rd, ra, rb, d;
> -
> - rd = get_rt(inst);
> - ra = get_ra(inst);
> - rb = get_rb(inst);
> - d = get_d(inst);
> -
> - switch (get_op(inst)) {
> - case 31:
> - switch (get_xop(inst)) {
> - case OP_31_XOP_LWZX:
> - case OP_31_XOP_LWBRX:
> - regs->gpr[rd] = 0xffffffff;
> - break;
> -
> - case OP_31_XOP_LWZUX:
> - regs->gpr[rd] = 0xffffffff;
> - regs->gpr[ra] += regs->gpr[rb];
> - break;
> -
> - case OP_31_XOP_LBZX:
> - regs->gpr[rd] = 0xff;
> - break;
> -
> - case OP_31_XOP_LBZUX:
> - regs->gpr[rd] = 0xff;
> - regs->gpr[ra] += regs->gpr[rb];
> - break;
> -
> - case OP_31_XOP_LHZX:
> - case OP_31_XOP_LHBRX:
> - regs->gpr[rd] = 0xffff;
> - break;
> -
> - case OP_31_XOP_LHZUX:
> - regs->gpr[rd] = 0xffff;
> - regs->gpr[ra] += regs->gpr[rb];
> - break;
> -
> - case OP_31_XOP_LHAX:
> - regs->gpr[rd] = ~0UL;
> - break;
> -
> - case OP_31_XOP_LHAUX:
> - regs->gpr[rd] = ~0UL;
> - regs->gpr[ra] += regs->gpr[rb];
> - break;
> -
> - default:
> - return 0;
> - }
> - break;
> -
> - case OP_LWZ:
> - regs->gpr[rd] = 0xffffffff;
> - break;
> -
> - case OP_LWZU:
> - regs->gpr[rd] = 0xffffffff;
> - regs->gpr[ra] += (s16)d;
> - break;
> -
> - case OP_LBZ:
> - regs->gpr[rd] = 0xff;
> - break;
> -
> - case OP_LBZU:
> - regs->gpr[rd] = 0xff;
> - regs->gpr[ra] += (s16)d;
> - break;
> -
> - case OP_LHZ:
> - regs->gpr[rd] = 0xffff;
> - break;
> -
> - case OP_LHZU:
> - regs->gpr[rd] = 0xffff;
> - regs->gpr[ra] += (s16)d;
> - break;
> -
> - case OP_LHA:
> - regs->gpr[rd] = ~0UL;
> - break;
> -
> - case OP_LHAU:
> - regs->gpr[rd] = ~0UL;
> - regs->gpr[ra] += (s16)d;
> - break;
> -
> - default:
> - return 0;
> - }
> -
> - return 1;
> -}
> -
> -static int is_in_pci_mem_space(phys_addr_t addr)
> -{
> - struct pci_controller *hose;
> - struct resource *res;
> - int i;
> -
> - list_for_each_entry(hose, &hose_list, list_node) {
> - if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
> - continue;
> -
> - for (i = 0; i < 3; i++) {
> - res = &hose->mem_resources[i];
> - if ((res->flags & IORESOURCE_MEM) &&
> - addr >= res->start && addr <= res->end)
> - return 1;
> - }
> - }
> - return 0;
> -}
> -
> -int fsl_pci_mcheck_exception(struct pt_regs *regs)
> -{
> - u32 inst;
> - int ret;
> - phys_addr_t addr = 0;
> -
> - /* Let KVM/QEMU deal with the exception */
> - if (regs->msr & MSR_GS)
> - return 0;
> -
> -#ifdef CONFIG_PHYS_64BIT
> - addr = mfspr(SPRN_MCARU);
> - addr <<= 32;
> -#endif
> - addr += mfspr(SPRN_MCAR);
> -
> - if (is_in_pci_mem_space(addr)) {
> - if (user_mode(regs)) {
> - pagefault_disable();
> - ret = get_user(regs->nip, &inst);
> - pagefault_enable();
> - } else {
> - ret = probe_kernel_address(regs->nip, inst);
> - }
> -
> - if (mcheck_handle_load(regs, inst)) {
> - regs->nip += 4;
> - return 1;
> - }
> - }
> -
> - return 0;
> -}
> -#endif
> -
> -#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
> static const struct of_device_id pci_ids[] = {
> { .compatible = "fsl,mpc8540-pci", },
> { .compatible = "fsl,mpc8548-pcie", },
> @@ -1050,40 +496,6 @@ static const struct of_device_id pci_ids[] = {
> {},
> };
>
> -struct device_node *fsl_pci_primary;
> -
> -void fsl_pci_assign_primary(void)
> -{
> - struct device_node *np;
> -
> - /* Callers can specify the primary bus using other means. */
> - if (fsl_pci_primary)
> - return;
> -
> - /* If a PCI host bridge contains an ISA node, it's primary. */
> - np = of_find_node_by_type(NULL, "isa");
> - while ((fsl_pci_primary = of_get_parent(np))) {
> - of_node_put(np);
> - np = fsl_pci_primary;
> -
> - if (of_match_node(pci_ids, np) && of_device_is_available(np))
> - return;
> - }
> -
> - /*
> - * If there's no PCI host bridge with ISA, arbitrarily
> - * designate one as primary. This can go away once
> - * various bugs with primary-less systems are fixed.
> - */
> - for_each_matching_node(np, pci_ids) {
> - if (of_device_is_available(np)) {
> - fsl_pci_primary = np;
> - of_node_put(np);
> - return;
> - }
> - }
> -}
> -
> static int fsl_pci_probe(struct platform_device *pdev)
> {
> int ret;
> @@ -1143,4 +555,3 @@ static int __init fsl_pci_init(void)
> return platform_driver_register(&fsl_pci_driver);
> }
> arch_initcall(fsl_pci_init);
> -#endif
> diff --git a/arch/powerpc/sysdev/fsl_pci.h b/include/linux/fsl/pci-common.h
> similarity index 79%
> copy from arch/powerpc/sysdev/fsl_pci.h
> copy to include/linux/fsl/pci-common.h
> index 8d455df..5e4f683 100644
> --- a/arch/powerpc/sysdev/fsl_pci.h
> +++ b/include/linux/fsl/pci-common.h
> @@ -1,5 +1,5 @@
> /*
> - * MPC85xx/86xx PCI Express structure define
> + * MPC85xx/86xx/LS PCI Express structure define
> *
> * Copyright 2007,2011 Freescale Semiconductor, Inc
> *
> @@ -11,15 +11,8 @@
> */
>
> #ifdef __KERNEL__
> -#ifndef __POWERPC_FSL_PCI_H
> -#define __POWERPC_FSL_PCI_H
> -
> -struct platform_device;
> -
> -
> -/* FSL PCI controller BRR1 register */
> -#define PCI_FSL_BRR1 0xbf8
> -#define PCI_FSL_BRR1_VER 0xffff
> +#ifndef __PCI_COMMON_H
> +#define __PCI_COMMON_H
>
> #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
> #define PCIE_LTSSM_L0 0x16 /* L0 state */
> @@ -52,7 +45,7 @@ struct pci_inbound_window_regs {
> u8 res2[12];
> };
>
> -/* PCI/PCI Express IO block registers for 85xx/86xx */
> +/* PCI/PCI Express IO block registers for 85xx/86xx/LS */
> struct ccsr_pci {
> __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
> __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
> @@ -109,33 +102,5 @@ struct ccsr_pci {
>
> };
>
> -extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
> -extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
> -extern int mpc83xx_add_bridge(struct device_node *dev);
> -u64 fsl_pci_immrbar_base(struct pci_controller *hose);
> -
> -extern struct device_node *fsl_pci_primary;
> -
> -#ifdef CONFIG_PCI
> -void fsl_pci_assign_primary(void);
> -#else
> -static inline void fsl_pci_assign_primary(void) {}
> -#endif
> -
> -#ifdef CONFIG_EDAC_MPC85XX
> -int mpc85xx_pci_err_probe(struct platform_device *op);
> -#else
> -static inline int mpc85xx_pci_err_probe(struct platform_device *op)
> -{
> - return -ENOTSUPP;
> -}
> -#endif
> -
> -#ifdef CONFIG_FSL_PCI
> -extern int fsl_pci_mcheck_exception(struct pt_regs *);
> -#else
> -static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
> -#endif
> -
> -#endif /* __POWERPC_FSL_PCI_H */
> +#endif /* __PCI_COMMON_H */
> #endif /* __KERNEL__ */
> --
> 1.8.1.2
>
>
^ permalink raw reply
* [PATCH 1/1] powerpc: Increase EEH recovery timeout for SR-IOV
From: Brian King @ 2013-11-25 22:27 UTC (permalink / raw)
To: benh; +Cc: brking, linuxppc-dev, shangw
In order to support concurrent adapter firmware download
to SR-IOV adapters on pSeries, each VF will see an EEH event
where the slot will remain in the unavailable state for
the duration of the adapter firmware update, which can take
as long as 5 minutes. Extend the EEH recovery timeout to
account for this.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh.c | 2 +-
arch/powerpc/kernel/eeh_driver.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff -puN arch/powerpc/kernel/eeh.c~eeh_sriov_vf_delay arch/powerpc/kernel/eeh.c
--- linux/arch/powerpc/kernel/eeh.c~eeh_sriov_vf_delay 2013-11-25 16:12:26.000000000 -0600
+++ linux-bjking1/arch/powerpc/kernel/eeh.c 2013-11-25 16:12:26.000000000 -0600
@@ -84,7 +84,7 @@
#define EEH_MAX_FAILS 2100000
/* Time to wait for a PCI slot to report status, in milliseconds */
-#define PCI_BUS_RESET_WAIT_MSEC (60*1000)
+#define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
/* Platform dependent EEH operations */
struct eeh_ops *eeh_ops = NULL;
diff -puN arch/powerpc/kernel/eeh_driver.c~eeh_sriov_vf_delay arch/powerpc/kernel/eeh_driver.c
--- linux/arch/powerpc/kernel/eeh_driver.c~eeh_sriov_vf_delay 2013-11-25 16:12:26.000000000 -0600
+++ linux-bjking1/arch/powerpc/kernel/eeh_driver.c 2013-11-25 16:12:26.000000000 -0600
@@ -468,7 +468,7 @@ static int eeh_reset_device(struct eeh_p
/* The longest amount of time to wait for a pci device
* to come back on line, in seconds.
*/
-#define MAX_WAIT_FOR_RECOVERY 150
+#define MAX_WAIT_FOR_RECOVERY 300
static void eeh_handle_normal_event(struct eeh_pe *pe)
{
_
^ permalink raw reply
* Re: [PATCH v5 08/17] spi: mpc512x: adjust to OF based clock lookup
From: Gerhard Sittig @ 2013-11-25 19:06 UTC (permalink / raw)
To: Mark Brown
Cc: Mike Turquette, Detlev Zundel, linux-spi, Scott Wood,
Anatolij Gustschin, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20131125173008.GQ14725@sirena.org.uk>
On Mon, Nov 25, 2013 at 17:30 +0000, Mark Brown wrote:
>
> On Mon, Nov 18, 2013 at 12:06:08AM +0100, Gerhard Sittig wrote:
> > after device tree based clock lookup became available, the peripheral
> > driver need no longer construct clock names which include the PSC index,
> > remove the "psc%d_mclk" template and unconditionally use 'mclk'
>
> Have there been other changes which make this happen?
Not yet in mainline. The patch you respond to is 08/17 within
the series, and depends on earlier patches in the series (namely
the introduction of CCF support for the MPC512x platform, making
the 'mclk' lookup against the PSC's OF node work while keeping
the global 'pscN_mclk' in place during migration).
This information was listed in the cover letter, but was not
duplicated within the individual patches. Patches were sent to
individual Cc: lists to not spam too many people, but the cover
letter was CC'ed to every recipient of any part of the series.
Please note that I will have to re-submit the series, since it no
longer cleanly applies against v3.13-rc1 (which was not available
when I sent v5). This patch won't change in its content, but may
experience changes in its context (catchup with changes between
v3.12 and v3.13-rc1).
Thank you for considering the patch, and for your feedback on
past versions!
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply
* Re: [PATCH v5 08/17] spi: mpc512x: adjust to OF based clock lookup
From: Mark Brown @ 2013-11-25 17:30 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Mike Turquette, Detlev Zundel, linux-spi, Scott Wood,
Anatolij Gustschin, linuxppc-dev, linux-arm-kernel
In-Reply-To: <1384729577-7336-9-git-send-email-gsi@denx.de>
[-- Attachment #1: Type: text/plain, Size: 332 bytes --]
On Mon, Nov 18, 2013 at 12:06:08AM +0100, Gerhard Sittig wrote:
> after device tree based clock lookup became available, the peripheral
> driver need no longer construct clock names which include the PSC index,
> remove the "psc%d_mclk" template and unconditionally use 'mclk'
Have there been other changes which make this happen?
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^ permalink raw reply
* Re: [PATCH 0/9 v2] vfio-pci: add support for Freescale IOMMU (PAMU)
From: Alex Williamson @ 2013-11-25 16:38 UTC (permalink / raw)
To: Bharat Bhushan
Cc: linux-pci@vger.kernel.org, agraf@suse.de, Stuart Yoder,
bhelgaas@google.com, iommu@lists.linux-foundation.org, Scott Wood,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <6A3DF150A5B70D4F9B66A25E3F7C888D0722C180@039-SN2MPN1-012.039d.mgd.msft.net>
On Mon, 2013-11-25 at 05:33 +0000, Bharat Bhushan wrote:
>
> > -----Original Message-----
> > From: Alex Williamson [mailto:alex.williamson@redhat.com]
> > Sent: Friday, November 22, 2013 2:31 AM
> > To: Wood Scott-B07421
> > Cc: Bhushan Bharat-R65777; linux-pci@vger.kernel.org; agraf@suse.de; Yoder
> > Stuart-B08248; iommu@lists.linux-foundation.org; bhelgaas@google.com; linuxppc-
> > dev@lists.ozlabs.org; linux-kernel@vger.kernel.org
> > Subject: Re: [PATCH 0/9 v2] vfio-pci: add support for Freescale IOMMU (PAMU)
> >
> > On Thu, 2013-11-21 at 14:47 -0600, Scott Wood wrote:
> > > On Thu, 2013-11-21 at 13:43 -0700, Alex Williamson wrote:
> > > > On Thu, 2013-11-21 at 11:20 +0000, Bharat Bhushan wrote:
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Alex Williamson [mailto:alex.williamson@redhat.com]
> > > > > > Sent: Thursday, November 21, 2013 12:17 AM
> > > > > > To: Bhushan Bharat-R65777
> > > > > > Cc: joro@8bytes.org; bhelgaas@google.com; agraf@suse.de; Wood
> > > > > > Scott-B07421; Yoder Stuart-B08248;
> > > > > > iommu@lists.linux-foundation.org; linux- pci@vger.kernel.org;
> > > > > > linuxppc-dev@lists.ozlabs.org; linux- kernel@vger.kernel.org;
> > > > > > Bhushan Bharat-R65777
> > > > > > Subject: Re: [PATCH 0/9 v2] vfio-pci: add support for Freescale
> > > > > > IOMMU (PAMU)
> > > > > >
> > > > > > Is VFIO_IOMMU_PAMU_GET_MSI_BANK_COUNT per aperture (ie. each
> > > > > > vfio user has $COUNT regions at their disposal exclusively)?
> > > > >
> > > > > Number of msi-bank count is system wide and not per aperture, But will be
> > setting windows for banks in the device aperture.
> > > > > So say if we are direct assigning 2 pci device (both have different iommu
> > group, so 2 aperture in iommu) to VM.
> > > > > Now qemu can make only one call to know how many msi-banks are there but
> > it must set sub-windows for all banks for both pci device in its respective
> > aperture.
> > > >
> > > > I'm still confused. What I want to make sure of is that the banks
> > > > are independent per aperture. For instance, if we have two separate
> > > > userspace processes operating independently and they both chose to
> > > > use msi bank zero for their device, that's bank zero within each
> > > > aperture and doesn't interfere. Or another way to ask is can a
> > > > malicious user interfere with other users by using the wrong bank.
> > > > Thanks,
> > >
> > > They can interfere.
>
> Want to be sure of how they can interfere?
What happens if more than one user selects the same MSI bank?
Minimally, wouldn't that result in the IOMMU blocking transactions from
the previous user once the new user activates their mapping?
> >> With this hardware, the only way to prevent that
> > > is to make sure that a bank is not shared by multiple protection contexts.
> > > For some of our users, though, I believe preventing this is less
> > > important than the performance benefit.
>
> So should we let this patch series in without protection?
No.
> >
> > I think we need some sort of ownership model around the msi banks then.
> > Otherwise there's nothing preventing another userspace from attempting an MSI
> > based attack on other users, or perhaps even on the host. VFIO can't allow
> > that. Thanks,
>
> We have very few (3 MSI bank on most of chips), so we can not assign
> one to each userspace. What we can do is host and userspace does not
> share a MSI bank while userspace will share a MSI bank.
Then you probably need VFIO to "own" the MSI bank and program devices
into it rather than exposing the MSI banks to userspace to let them have
direct access. Thanks,
Alex
^ permalink raw reply
* [PATCH v2 01/11] Add generic fixmap.h
From: Mark Salter @ 2013-11-25 16:13 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arch, linux-mips, Michal Simek, James Hogan, Russell King,
linux-hexagon, microblaze-uclinux, Richard Kuo, Mark Salter,
Paul Mackerras, linuxppc-dev, linux-metag, linux-arm-kernel
In-Reply-To: <1385396045-15852-1-git-send-email-msalter@redhat.com>
Many architectures provide an asm/fixmap.h which defines support for
compile-time 'special' virtual mappings which need to be made before
paging_init() has run. This support is also used for early ioremap
on x86. Much of this support is identical across the architectures.
This patch consolidates all of the common bits into asm-generic/fixmap.h
which is intended to be included from arch/*/include/asm/fixmap.h.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
CC: linux-arch@vger.kernel.org
CC: Russell King <linux@arm.linux.org.uk>
CC: linux-arm-kernel@lists.infradead.org
CC: Richard Kuo <rkuo@codeaurora.org>
CC: linux-hexagon@vger.kernel.org
CC: James Hogan <james.hogan@imgtec.com>
CC: linux-metag@vger.kernel.org
CC: Michal Simek <monstr@monstr.eu>
CC: microblaze-uclinux@itee.uq.edu.au
CC: linux-mips@linux-mips.org
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: linuxppc-dev@lists.ozlabs.org
---
include/asm-generic/fixmap.h | 97 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
create mode 100644 include/asm-generic/fixmap.h
diff --git a/include/asm-generic/fixmap.h b/include/asm-generic/fixmap.h
new file mode 100644
index 0000000..5a64ca4
--- /dev/null
+++ b/include/asm-generic/fixmap.h
@@ -0,0 +1,97 @@
+/*
+ * fixmap.h: compile-time virtual memory allocation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998 Ingo Molnar
+ *
+ * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
+ * x86_32 and x86_64 integration by Gustavo F. Padovan, February 2009
+ * Break out common bits to asm-generic by Mark Salter, November 2013
+ */
+
+#ifndef __ASM_GENERIC_FIXMAP_H
+#define __ASM_GENERIC_FIXMAP_H
+
+#include <linux/bug.h>
+
+#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
+
+#ifndef __ASSEMBLY__
+/*
+ * 'index to address' translation. If anyone tries to use the idx
+ * directly without translation, we catch the bug with a NULL-deference
+ * kernel oops. Illegal ranges of incoming indices are caught too.
+ */
+static __always_inline unsigned long fix_to_virt(const unsigned int idx)
+{
+ BUILD_BUG_ON(idx >= __end_of_fixed_addresses);
+ return __fix_to_virt(idx);
+}
+
+static inline unsigned long virt_to_fix(const unsigned long vaddr)
+{
+ BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
+ return __virt_to_fix(vaddr);
+}
+
+/*
+ * Provide some reasonable defaults for page flags.
+ * Not all architectures use all of these different types and some
+ * architectures use different names.
+ */
+#ifndef FIXMAP_PAGE_NORMAL
+#define FIXMAP_PAGE_NORMAL PAGE_KERNEL
+#endif
+#ifndef FIXMAP_PAGE_NOCACHE
+#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NOCACHE
+#endif
+#ifndef FIXMAP_PAGE_IO
+#define FIXMAP_PAGE_IO PAGE_KERNEL_IO
+#endif
+#ifndef FIXMAP_PAGE_CLEAR
+#define FIXMAP_PAGE_CLEAR __pgprot(0)
+#endif
+
+#ifndef set_fixmap
+#define set_fixmap(idx, phys) \
+ __set_fixmap(idx, phys, FIXMAP_PAGE_NORMAL)
+#endif
+
+#ifndef clear_fixmap
+#define clear_fixmap(idx) \
+ __set_fixmap(idx, 0, FIXMAP_PAGE_CLEAR)
+#endif
+
+/* Return a pointer with offset calculated */
+#define __set_fixmap_offset(idx, phys, flags) \
+({ \
+ unsigned long addr; \
+ __set_fixmap(idx, phys, flags); \
+ addr = fix_to_virt(idx) + ((phys) & (PAGE_SIZE - 1)); \
+ addr; \
+})
+
+#define set_fixmap_offset(idx, phys) \
+ __set_fixmap_offset(idx, phys, FIXMAP_PAGE_NORMAL)
+
+/*
+ * Some hardware wants to get fixmapped without caching.
+ */
+#define set_fixmap_nocache(idx, phys) \
+ __set_fixmap(idx, phys, FIXMAP_PAGE_NOCACHE)
+
+#define set_fixmap_offset_nocache(idx, phys) \
+ __set_fixmap_offset(idx, phys, FIXMAP_PAGE_NOCACHE)
+
+/*
+ * Some fixmaps are for IO
+ */
+#define set_fixmap_io(idx, phys) \
+ __set_fixmap(idx, phys, FIXMAP_PAGE_IO)
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_GENERIC_FIXMAP_H */
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 00/11] Consolidate asm/fixmap.h files
From: Mark Salter @ 2013-11-25 16:13 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arch, linux-mips, Michal Simek, James Hogan, Russell King,
Arnd Bergmann, linux-hexagon, microblaze-uclinux, Ralf Baechle,
Richard Kuo, Mark Salter, Paul Mackerras, linuxppc-dev,
linux-metag, linux-arm-kernel
Many architectures provide an asm/fixmap.h which defines support for
compile-time 'special' virtual mappings which need to be made before
paging_init() has run. This suport is also used for early ioremap
on x86. Much of this support is identical across the architectures.
This patch consolidates all of the common bits into asm-generic/fixmap.h
which is intended to be included from arch/*/include/asm/fixmap.h.
This has been compiled on x86, arm, powerpc, and sh, but tested
on x86 only.
This is version two of the patch series:
git://github.com/mosalter/linux.git#fixmap-v2
Version 1 is here:
git://github.com/mosalter/linux.git#fixmap
Changes from v1:
* Added acks from feedback.
* Use BUILD_BUG_ON in fix_to_virt()
* Fixed ARM patch to make FIXMAP_TOP inclusive of fixmap
range as is the case in the other architectures.
Mark Salter (11):
Add generic fixmap.h
x86: use generic fixmap.h
arm: use generic fixmap.h
hexagon: use generic fixmap.h
metag: use generic fixmap.h
microblaze: use generic fixmap.h
mips: use generic fixmap.h
powerpc: use generic fixmap.h
sh: use generic fixmap.h
tile: use generic fixmap.h
um: use generic fixmap.h
arch/arm/include/asm/fixmap.h | 29 +++--------
arch/arm/mm/init.c | 2 +-
arch/hexagon/include/asm/fixmap.h | 40 +--------------
arch/metag/include/asm/fixmap.h | 32 +-----------
arch/microblaze/include/asm/fixmap.h | 44 +---------------
arch/mips/include/asm/fixmap.h | 33 +-----------
arch/powerpc/include/asm/fixmap.h | 44 +---------------
arch/sh/include/asm/fixmap.h | 39 +--------------
arch/tile/include/asm/fixmap.h | 33 +-----------
arch/um/include/asm/fixmap.h | 40 +--------------
arch/x86/include/asm/fixmap.h | 59 +---------------------
include/asm-generic/fixmap.h | 97 ++++++++++++++++++++++++++++++++++++
12 files changed, 118 insertions(+), 374 deletions(-)
create mode 100644 include/asm-generic/fixmap.h
--
1.8.3.1
^ permalink raw reply
* [PATCH v2 08/11] powerpc: use generic fixmap.h
From: Mark Salter @ 2013-11-25 16:14 UTC (permalink / raw)
To: linux-kernel; +Cc: Paul Mackerras, linuxppc-dev, Mark Salter
In-Reply-To: <1385396045-15852-1-git-send-email-msalter@redhat.com>
Signed-off-by: Mark Salter <msalter@redhat.com>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/fixmap.h | 44 ++-------------------------------------
1 file changed, 2 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/include/asm/fixmap.h b/arch/powerpc/include/asm/fixmap.h
index 5c2c023..90f604b 100644
--- a/arch/powerpc/include/asm/fixmap.h
+++ b/arch/powerpc/include/asm/fixmap.h
@@ -58,52 +58,12 @@ enum fixed_addresses {
extern void __set_fixmap (enum fixed_addresses idx,
phys_addr_t phys, pgprot_t flags);
-#define set_fixmap(idx, phys) \
- __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
- __set_fixmap(idx, phys, PAGE_KERNEL_NCG)
-
-#define clear_fixmap(idx) \
- __set_fixmap(idx, 0, __pgprot(0))
-
#define __FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
-#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static __always_inline unsigned long fix_to_virt(const unsigned int idx)
-{
- /*
- * this branch gets completely eliminated after inlining,
- * except when someone tries to use fixaddr indices in an
- * illegal way. (such as mixing up address types or using
- * out-of-range indices).
- *
- * If it doesn't get removed, the linker will complain
- * loudly with a reasonably clear error message..
- */
- if (idx >= __end_of_fixed_addresses)
- __this_fixmap_does_not_exist();
-
- return __fix_to_virt(idx);
-}
+#define FIXMAP_PAGE_NOCACHE PAGE_KERNEL_NCG
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
- BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
- return __virt_to_fix(vaddr);
-}
+#include <asm-generic/fixmap.h>
#endif /* !__ASSEMBLY__ */
#endif
--
1.8.3.1
^ permalink raw reply related
* Re: [PATCH] powerpc/4xx: Fix warning in kilauea.dtb
From: Josh Boyer @ 2013-11-25 12:47 UTC (permalink / raw)
To: Ian Campbell, Benjamin Herrenschmidt
Cc: open list:OPEN FIRMWARE AND..., Tirumala R Marri, Rupjyoti Sarmah,
Linux-Kernel@Vger. Kernel. Org, Paul Mackerras, linuxppc-dev
In-Reply-To: <1385372437-20958-1-git-send-email-ian.campbell@citrix.com>
On Mon, Nov 25, 2013 at 4:40 AM, Ian Campbell <ian.campbell@citrix.com> wrote:
> Currently I see:
> DTC arch/powerpc/boot/kilauea.dtb
> Warning (reg_format): "reg" property in /plb/ppc4xx-msi@C10000000 has invalid length (12 bytes) (#address-cells == 1, #size-cells == 1)
>
> It appears that unlike the other platforms handled by 3fb7933850fa
> "powerpc/4xx: Adding PCIe MSI support" this platform does not use address-cells=2.
>
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> Acked-by: Josh Boyer <jwboyer@gmail.com>
> Cc: Rupjyoti Sarmah <rsarmah@apm.com>
> Cc: Tirumala R Marri <tmarri@apm.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND...)
> Cc: linuxppc-dev@lists.ozlabs.org
> Cc: linux-kernel@vger.kernel.org
> ---
> Resending, this hasn't been picked up since June
> http://patchwork.ozlabs.org/patch/248234/
Ben, please pick this up.
josh
> ---
> arch/powerpc/boot/dts/kilauea.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
> index 1613d6e..5ba7f01 100644
> --- a/arch/powerpc/boot/dts/kilauea.dts
> +++ b/arch/powerpc/boot/dts/kilauea.dts
> @@ -406,7 +406,7 @@
>
> MSI: ppc4xx-msi@C10000000 {
> compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
> - reg = < 0x0 0xEF620000 0x100>;
> + reg = <0xEF620000 0x100>;
> sdr-base = <0x4B0>;
> msi-data = <0x00000000>;
> msi-mask = <0x44440000>;
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* [PATCH] powerpc/4xx: Fix warning in kilauea.dtb
From: Ian Campbell @ 2013-11-25 9:40 UTC (permalink / raw)
To: linuxppc-dev
Cc: open list:OPEN FIRMWARE AND..., Ian Campbell, Tirumala R Marri,
Rupjyoti Sarmah, linux-kernel, Paul Mackerras
Currently I see:
DTC arch/powerpc/boot/kilauea.dtb
Warning (reg_format): "reg" property in /plb/ppc4xx-msi@C10000000 has invalid length (12 bytes) (#address-cells == 1, #size-cells == 1)
It appears that unlike the other platforms handled by 3fb7933850fa
"powerpc/4xx: Adding PCIe MSI support" this platform does not use address-cells=2.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Josh Boyer <jwboyer@gmail.com>
Cc: Rupjyoti Sarmah <rsarmah@apm.com>
Cc: Tirumala R Marri <tmarri@apm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND...)
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
---
Resending, this hasn't been picked up since June
http://patchwork.ozlabs.org/patch/248234/
---
arch/powerpc/boot/dts/kilauea.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 1613d6e..5ba7f01 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -406,7 +406,7 @@
MSI: ppc4xx-msi@C10000000 {
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
- reg = < 0x0 0xEF620000 0x100>;
+ reg = <0xEF620000 0x100>;
sdr-base = <0x4B0>;
msi-data = <0x00000000>;
msi-mask = <0x44440000>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH] powerpc/dts/virtex440: declare address/size-cells for phy device
From: Ian Campbell @ 2013-11-25 9:42 UTC (permalink / raw)
To: linuxppc-dev
Cc: devicetree, Ian Campbell, linux-kernel, Paul Mackerras,
Gernot Vormayr
This fixes a warning:
DTC arch/powerpc/boot/virtex440-ml507.dtb
Warning (reg_format): "reg" property in /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7
Warning (avoid_default_addr_size): Relying on default #size-cells value for /plb@0/xps-ll-temac@81c00000/ethernet@81c00000/phy@7
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Gernot Vormayr <gvormayr@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
---
No reply since June. http://patchwork.ozlabs.org/patch/248235/
---
arch/powerpc/boot/dts/virtex440-ml507.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/boot/dts/virtex440-ml507.dts b/arch/powerpc/boot/dts/virtex440-ml507.dts
index fc7073b..391a4e2 100644
--- a/arch/powerpc/boot/dts/virtex440-ml507.dts
+++ b/arch/powerpc/boot/dts/virtex440-ml507.dts
@@ -257,6 +257,8 @@
#size-cells = <1>;
compatible = "xlnx,compound";
ethernet@81c00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "xlnx,xps-ll-temac-1.01.b";
device_type = "network";
interrupt-parent = <&xps_intc_0>;
--
1.7.10.4
^ permalink raw reply related
* [PATCH 24/24] asm-generic: Rename int-ll64.h to types.h
From: Geert Uytterhoeven @ 2013-11-25 8:55 UTC (permalink / raw)
To: Arnd Bergmann, linux-arch
Cc: linux-mips, linux-ia64, linux-s390, linux-xtensa, linux-sh,
linux-kernel, linux-kbuild, Geert Uytterhoeven, linux-alpha,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <1385369734-24893-1-git-send-email-geert@linux-m68k.org>
Since kernelspace always uses "(unsigned) long long" for 64-bit integer
values ("u64" and "s64"), rename include/asm-generic/int-ll64.h to
include/asm-generic/types.h, as suggested by Arnd Bergmann.
Userspace still has both include/uapi/asm-generic/int-l64.h and
include/uapi/asm-generic/int-ll64.h, as int-l64.h may still be used for
userspace on existing 64-bit platforms (alpha, ia64, mips, and powerpc).
Note: While arch/alpha/include/asm/types.h just includes
asm-generic/types.h, don't be tempted to use Kbuild logic to provide it!
arch/*/include/asm/Kbuild applies to both arch/*/include/asm and
arch/*/include/uapi/asm, while alpha has its own <uapi/asm/types.h>.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: linux-alpha@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-ia64@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: linux-s390@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: linux-xtensa@linux-xtensa.org
Cc: linux-kbuild@vger.kernel.org
---
Question: Is the arch/*/include/asm/Kbuild behavior intentional?
arch/alpha/include/asm/types.h | 2 +-
arch/arm/include/asm/types.h | 2 +-
arch/ia64/include/asm/types.h | 2 +-
arch/mips/include/asm/types.h | 2 +-
arch/powerpc/include/asm/types.h | 2 +-
arch/s390/include/asm/types.h | 2 +-
arch/sh/include/asm/types.h | 2 +-
arch/xtensa/include/asm/types.h | 2 +-
include/asm-generic/io-64-nonatomic-hi-lo.h | 2 +-
include/asm-generic/io-64-nonatomic-lo-hi.h | 2 +-
include/asm-generic/{int-ll64.h => types.h} | 8 ++++----
11 files changed, 14 insertions(+), 14 deletions(-)
rename include/asm-generic/{int-ll64.h => types.h} (85%)
diff --git a/arch/alpha/include/asm/types.h b/arch/alpha/include/asm/types.h
index 4cb4b6d3452c..b86fb65c5b10 100644
--- a/arch/alpha/include/asm/types.h
+++ b/arch/alpha/include/asm/types.h
@@ -1,6 +1,6 @@
#ifndef _ALPHA_TYPES_H
#define _ALPHA_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#endif /* _ALPHA_TYPES_H */
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index a53cdb8f068c..09e15a8a40b1 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -1,7 +1,7 @@
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
/*
* The C99 types uintXX_t that are usually defined in 'stdint.h' are not as
diff --git a/arch/ia64/include/asm/types.h b/arch/ia64/include/asm/types.h
index 4c351b169da2..6bc2e8acadd7 100644
--- a/arch/ia64/include/asm/types.h
+++ b/arch/ia64/include/asm/types.h
@@ -13,7 +13,7 @@
#ifndef _ASM_IA64_TYPES_H
#define _ASM_IA64_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#include <uapi/asm/types.h>
#ifdef __ASSEMBLY__
diff --git a/arch/mips/include/asm/types.h b/arch/mips/include/asm/types.h
index 4d5ce4c9c924..0d6729329a6a 100644
--- a/arch/mips/include/asm/types.h
+++ b/arch/mips/include/asm/types.h
@@ -11,7 +11,7 @@
#ifndef _ASM_TYPES_H
#define _ASM_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
/*
* These aren't exported outside the kernel to avoid name space clashes
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index 4b9c3530bb12..69d42a918e0e 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -13,7 +13,7 @@
#ifndef _ASM_POWERPC_TYPES_H
#define _ASM_POWERPC_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#include <uapi/asm/types.h>
#ifndef __ASSEMBLY__
diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h
index a5c7e829dbc3..abb93c7f0125 100644
--- a/arch/s390/include/asm/types.h
+++ b/arch/s390/include/asm/types.h
@@ -6,7 +6,7 @@
#ifndef _S390_TYPES_H
#define _S390_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#include <uapi/asm/types.h>
/*
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index 062324be5cd6..ef745dcfd926 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -1,7 +1,7 @@
#ifndef __ASM_SH_TYPES_H
#define __ASM_SH_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
/*
* These aren't exported outside the kernel to avoid name space clashes
diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h
index d873cb17d944..20ffdf440e4f 100644
--- a/arch/xtensa/include/asm/types.h
+++ b/arch/xtensa/include/asm/types.h
@@ -10,7 +10,7 @@
#ifndef _XTENSA_TYPES_H
#define _XTENSA_TYPES_H
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#include <uapi/asm/types.h>
#endif /* _XTENSA_TYPES_H */
diff --git a/include/asm-generic/io-64-nonatomic-hi-lo.h b/include/asm-generic/io-64-nonatomic-hi-lo.h
index a6806a94250d..414d2c49d53c 100644
--- a/include/asm-generic/io-64-nonatomic-hi-lo.h
+++ b/include/asm-generic/io-64-nonatomic-hi-lo.h
@@ -2,7 +2,7 @@
#define _ASM_IO_64_NONATOMIC_HI_LO_H_
#include <linux/io.h>
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
diff --git a/include/asm-generic/io-64-nonatomic-lo-hi.h b/include/asm-generic/io-64-nonatomic-lo-hi.h
index ca546b1ff8b5..9bc5a3393ca1 100644
--- a/include/asm-generic/io-64-nonatomic-lo-hi.h
+++ b/include/asm-generic/io-64-nonatomic-lo-hi.h
@@ -2,7 +2,7 @@
#define _ASM_IO_64_NONATOMIC_LO_HI_H_
#include <linux/io.h>
-#include <asm-generic/int-ll64.h>
+#include <asm-generic/types.h>
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
diff --git a/include/asm-generic/int-ll64.h b/include/asm-generic/types.h
similarity index 85%
rename from include/asm-generic/int-ll64.h
rename to include/asm-generic/types.h
index 4cd84855cb46..b9542bb3d991 100644
--- a/include/asm-generic/int-ll64.h
+++ b/include/asm-generic/types.h
@@ -1,11 +1,11 @@
/*
- * asm-generic/int-ll64.h
+ * asm-generic/types.h
*
* Integer declarations for architectures which use "long long"
* for 64-bit types.
*/
-#ifndef _ASM_GENERIC_INT_LL64_H
-#define _ASM_GENERIC_INT_LL64_H
+#ifndef _ASM_GENERIC_TYPES_H
+#define _ASM_GENERIC_TYPES_H
#include <uapi/asm-generic/int-ll64.h>
@@ -46,4 +46,4 @@ typedef unsigned long long u64;
#endif /* __ASSEMBLY__ */
-#endif /* _ASM_GENERIC_INT_LL64_H */
+#endif /* _ASM_GENERIC_TYPES_H */
--
1.7.9.5
^ permalink raw reply related
* [PATCH 21/24] powerpc: Separate kernel/userspace inclusion of <asm-generic/int-ll64.h>
From: Geert Uytterhoeven @ 2013-11-25 8:55 UTC (permalink / raw)
To: Arnd Bergmann, linux-arch
Cc: linuxppc-dev, Geert Uytterhoeven, linux-kernel, Paul Mackerras
In-Reply-To: <1385369734-24893-1-git-send-email-geert@linux-m68k.org>
This allows to rename the kernelspace version later.
Now arch/powerpc/include/asm/types.h includes the kernelspace version,
while arch/powerpc/include/uapi/asm/types.h includes the userspace version.
As arch/powerpc/include/uapi/asm/types.h is also included for kernelspace,
its inclusion of <asm-generic/int-ll64.h> needs to be protected by #ifndef
__KERNEL__.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/include/asm/types.h | 1 +
arch/powerpc/include/uapi/asm/types.h | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/types.h b/arch/powerpc/include/asm/types.h
index bfb6ded38ffa..4b9c3530bb12 100644
--- a/arch/powerpc/include/asm/types.h
+++ b/arch/powerpc/include/asm/types.h
@@ -13,6 +13,7 @@
#ifndef _ASM_POWERPC_TYPES_H
#define _ASM_POWERPC_TYPES_H
+#include <asm-generic/int-ll64.h>
#include <uapi/asm/types.h>
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/uapi/asm/types.h b/arch/powerpc/include/uapi/asm/types.h
index 4b8ab990a3c1..7f8847b61d03 100644
--- a/arch/powerpc/include/uapi/asm/types.h
+++ b/arch/powerpc/include/uapi/asm/types.h
@@ -21,11 +21,13 @@
* However, some user programs are fine with this. They can
* flag __SANE_USERSPACE_TYPES__ to get int-ll64.h here.
*/
-#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__) && !defined(__KERNEL__)
+#ifndef __KERNEL__
+#if !defined(__SANE_USERSPACE_TYPES__) && defined(__powerpc64__)
# include <asm-generic/int-l64.h>
#else
# include <asm-generic/int-ll64.h>
#endif
+#endif
#ifndef __ASSEMBLY__
--
1.7.9.5
^ permalink raw reply related
* [PATCH v4] KVM: PPC: vfio kvm device: support spapr tce
From: Alexey Kardashevskiy @ 2013-11-25 8:49 UTC (permalink / raw)
To: linuxppc-dev
Cc: Alexey Kardashevskiy, Alex Williamson, kvm-ppc, linux-kernel, kvm
In addition to the external VFIO user API, a VFIO KVM device
has been introduced recently.
sPAPR TCE IOMMU is para-virtualized and the guest does map/unmap
via hypercalls which take a logical bus id (LIOBN) as a target IOMMU
identifier. LIOBNs are made up and linked to IOMMU groups by the user
space. In order to accelerate IOMMU operations in the KVM, we need
to tell KVM the information about LIOBN-to-group mapping.
For that, a new KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN parameter
is added. It accepts a pair of a VFIO group fd and LIOBN.
This also adds a new kvm_vfio_find_group_by_liobn() function which
receives kvm struct, LIOBN and a callback. As it increases the IOMMU
group use counter, the KVMr is required to pass a callback which
called when the VFIO group is about to be removed VFIO-KVM tracking so
the KVM is able to call iommu_group_put() to release the IOMMU group.
The KVM uses kvm_vfio_find_group_by_liobn() once per KVM run and caches
the result in kvm_arch. iommu_group_put() for all groups will be called
when KVM finishes (in the SPAPR TCE in KVM enablement patch).
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v4:
* fixed few bugs
* changed kvm_vfio_find_group_by_liobn() to return informative errors
v3:
* total rework
* added a release callback into kvm_vfio_find_group_by_liobn so now
the user of the API can get a notification if the group is about to
disappear
---
Documentation/virtual/kvm/devices/vfio.txt | 19 ++++-
arch/powerpc/kvm/Kconfig | 1 +
arch/powerpc/kvm/Makefile | 3 +
include/linux/kvm_host.h | 18 +++++
include/uapi/linux/kvm.h | 7 ++
virt/kvm/vfio.c | 116 ++++++++++++++++++++++++++++-
6 files changed, 161 insertions(+), 3 deletions(-)
diff --git a/Documentation/virtual/kvm/devices/vfio.txt b/Documentation/virtual/kvm/devices/vfio.txt
index ef51740..7ecb3b2 100644
--- a/Documentation/virtual/kvm/devices/vfio.txt
+++ b/Documentation/virtual/kvm/devices/vfio.txt
@@ -16,7 +16,22 @@ Groups:
KVM_DEV_VFIO_GROUP attributes:
KVM_DEV_VFIO_GROUP_ADD: Add a VFIO group to VFIO-KVM device tracking
+ kvm_device_attr.addr points to an int32_t file descriptor
+ for the VFIO group.
+
KVM_DEV_VFIO_GROUP_DEL: Remove a VFIO group from VFIO-KVM device tracking
+ kvm_device_attr.addr points to an int32_t file descriptor
+ for the VFIO group.
+
+ KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN: sets a liobn for a VFIO group
+ kvm_device_attr.addr points to a struct:
+ struct kvm_vfio_spapr_tce_liobn {
+ __u32 argsz;
+ __u32 fd;
+ __u32 liobn;
+ };
+ where
+ @argsz is a struct size;
+ @fd is a file descriptor for a VFIO group;
+ @liobn is a logical bus id to be associated with the group.
-For each, kvm_device_attr.addr points to an int32_t file descriptor
-for the VFIO group.
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 9a50d82..f463958 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -60,6 +60,7 @@ config KVM_BOOK3S_64
select KVM_BOOK3S_64_HANDLER
select KVM
select SPAPR_TCE_IOMMU if IOMMU_SUPPORT
+ select KVM_VFIO
---help---
Support running unmodified book3s_64 and book3s_32 guest kernels
in virtual machines on book3s_64 host processors.
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 6646c95..2438d2e 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -87,6 +87,9 @@ kvm-book3s_64-builtin-objs-$(CONFIG_KVM_BOOK3S_64_HV) := \
kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
book3s_xics.o
+kvm-book3s_64-objs-$(CONFIG_KVM_VFIO) += \
+ $(KVM)/vfio.o \
+
kvm-book3s_64-module-objs := \
$(KVM)/kvm_main.o \
$(KVM)/eventfd.o \
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 88ff96a..1d2ad5e 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1112,5 +1112,23 @@ static inline bool kvm_vcpu_eligible_for_directed_yield(struct kvm_vcpu *vcpu)
}
#endif /* CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT */
+
+typedef void (*kvm_vfio_release_group_callback)(struct kvm *kvm,
+ unsigned long liobn);
+
+#if defined(CONFIG_KVM_VFIO) && defined(CONFIG_SPAPR_TCE_IOMMU)
+
+extern struct iommu_group *kvm_vfio_find_group_by_liobn(struct kvm *kvm,
+ unsigned long liobn, kvm_vfio_release_group_callback cb);
+
+#else
+
+static inline struct iommu_group *kvm_vfio_find_group_by_liobn(struct kvm *kvm,
+ unsigned long liobn, ikvm_vfio_release_group_callback cb)
+{
+ return NULL;
+}
+#endif /* CONFIG_KVM_VFIO && CONFIG_SPAPR_TCE_IOMMU */
+
#endif
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 7c1a349..51d5464 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -847,6 +847,13 @@ struct kvm_device_attr {
#define KVM_DEV_VFIO_GROUP 1
#define KVM_DEV_VFIO_GROUP_ADD 1
#define KVM_DEV_VFIO_GROUP_DEL 2
+#define KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN 3
+
+struct kvm_vfio_spapr_tce_liobn {
+ __u32 argsz;
+ __s32 fd;
+ __u32 liobn;
+};
/*
* ioctls for VM fds
diff --git a/virt/kvm/vfio.c b/virt/kvm/vfio.c
index ca4260e..ddc945d 100644
--- a/virt/kvm/vfio.c
+++ b/virt/kvm/vfio.c
@@ -22,6 +22,12 @@
struct kvm_vfio_group {
struct list_head node;
struct vfio_group *vfio_group;
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+ struct {
+ unsigned long liobn;
+ kvm_vfio_release_group_callback cb;
+ } spapr_tce;
+#endif
};
struct kvm_vfio {
@@ -59,6 +65,51 @@ static void kvm_vfio_group_put_external_user(struct vfio_group *vfio_group)
symbol_put(vfio_group_put_external_user);
}
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+struct iommu_group *kvm_vfio_find_group_by_liobn(struct kvm *kvm,
+ unsigned long liobn, kvm_vfio_release_group_callback cb)
+{
+ struct kvm_vfio_group *kvg;
+ int group_id;
+ struct iommu_group *grp;
+ struct kvm_vfio *kv = NULL;
+ struct kvm_device *tmp;
+
+ if (!cb)
+ return ERR_PTR(-EINVAL);
+
+ /* Find a VFIO KVM device */
+ list_for_each_entry(tmp, &kvm->devices, vm_node) {
+ if (tmp->ops != &kvm_vfio_ops)
+ continue;
+
+ kv = tmp->private;
+ break;
+ }
+
+ if (!kv)
+ return ERR_PTR(-EIO);
+
+ /* Find a group */
+ list_for_each_entry(kvg, &kv->group_list, node) {
+ if (kvg->spapr_tce.liobn != liobn)
+ continue;
+
+ if (kvg->spapr_tce.cb)
+ return ERR_PTR(-EBUSY);
+
+ kvg->spapr_tce.cb = cb;
+ group_id = vfio_external_user_iommu_id(kvg->vfio_group);
+ grp = iommu_group_get_by_id(group_id);
+
+ return grp;
+ }
+
+ return ERR_PTR(-ENODEV);
+}
+EXPORT_SYMBOL_GPL(kvm_vfio_find_group_by_liobn);
+#endif
+
/*
* Groups can use the same or different IOMMU domains. If the same then
* adding a new group may change the coherency of groups we've previously
@@ -140,7 +191,9 @@ static int kvm_vfio_set_group(struct kvm_device *dev, long attr, u64 arg)
list_add_tail(&kvg->node, &kv->group_list);
kvg->vfio_group = vfio_group;
-
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+ kvg->spapr_tce.liobn = -1;
+#endif
mutex_unlock(&kv->lock);
kvm_vfio_update_coherency(dev);
@@ -170,6 +223,11 @@ static int kvm_vfio_set_group(struct kvm_device *dev, long attr, u64 arg)
continue;
list_del(&kvg->node);
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+ if (kvg->spapr_tce.cb)
+ kvg->spapr_tce.cb(dev->kvm,
+ kvg->spapr_tce.liobn);
+#endif
kvm_vfio_group_put_external_user(kvg->vfio_group);
kfree(kvg);
ret = 0;
@@ -183,6 +241,59 @@ static int kvm_vfio_set_group(struct kvm_device *dev, long attr, u64 arg)
kvm_vfio_update_coherency(dev);
return ret;
+
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+ case KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN: {
+ struct kvm_vfio_spapr_tce_liobn param;
+ unsigned long minsz;
+ struct kvm_vfio *kv = dev->private;
+ struct vfio_group *vfio_group;
+ struct kvm_vfio_group *kvg;
+ struct fd f;
+
+ minsz = offsetofend(struct kvm_vfio_spapr_tce_liobn, liobn);
+
+ if (copy_from_user(¶m, (void __user *)arg, minsz))
+ return -EFAULT;
+
+ if (param.argsz < minsz)
+ return -EINVAL;
+
+ f = fdget(param.fd);
+ if (!f.file)
+ return -EBADF;
+
+ vfio_group = kvm_vfio_group_get_external_user(f.file);
+ fdput(f);
+
+ if (IS_ERR(vfio_group))
+ return PTR_ERR(vfio_group);
+
+ ret = -ENOENT;
+
+ mutex_lock(&kv->lock);
+
+ list_for_each_entry(kvg, &kv->group_list, node) {
+ if (kvg->vfio_group != vfio_group)
+ continue;
+
+ if (kvg->spapr_tce.liobn != -1) {
+ ret = -EBUSY;
+ break;
+ }
+
+ kvg->spapr_tce.liobn = param.liobn;
+ ret = 0;
+ break;
+ }
+
+ mutex_unlock(&kv->lock);
+
+ kvm_vfio_group_put_external_user(vfio_group);
+
+ return ret;
+ }
+#endif /* CONFIG_SPAPR_TCE_IOMMU */
}
return -ENXIO;
@@ -207,6 +318,9 @@ static int kvm_vfio_has_attr(struct kvm_device *dev,
switch (attr->attr) {
case KVM_DEV_VFIO_GROUP_ADD:
case KVM_DEV_VFIO_GROUP_DEL:
+#ifdef CONFIG_SPAPR_TCE_IOMMU
+ case KVM_DEV_VFIO_GROUP_SET_SPAPR_TCE_LIOBN:
+#endif
return 0;
}
--
1.8.4.rc4
^ permalink raw reply related
* [PATCH v2] PPC64: Adding symbols in vmcoreinfo to facilitate dump filtering
From: Hari Bathini @ 2013-11-25 6:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev; +Cc: Mahesh J Salgaonkar
When CONFIG_SPARSEMEM_VMEMMAP option is set in kernel, makedumpfile
tool fails to filter vmcore dump as it fails to do translations for
vmemmap addresses that are mapped outside zone normal. For vmemmap
adress translation support in this scenario, few kernel symbols are
needed by dump filtering tool. This patch adds those symbols to
vmcoreinfo, which a dump filtering tool can use for filtering the
kernel dump. This changes are tested successfully with makedumpfile
tool that supports vmemmap to physical address translation outside
zone normal.
Changes from v1:
Updated patch decription and removed #ifdef around extern.
Signed-off-by: Hari Bathini <hbathini@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/pgalloc-64.h | 2 ++
arch/powerpc/kernel/machine_kexec.c | 12 ++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index f65e27b..3973e62 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -17,6 +17,8 @@ struct vmemmap_backing {
unsigned long virt_addr;
};
+extern struct vmemmap_backing *vmemmap_list;
+
/*
* Functions that deal with pagetables that could be at any level of
* the table need to be passed an "index_size" so they know how to
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index e1ec57e..88a7fb4 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -18,6 +18,7 @@
#include <linux/ftrace.h>
#include <asm/machdep.h>
+#include <asm/pgalloc.h>
#include <asm/prom.h>
#include <asm/sections.h>
@@ -75,6 +76,17 @@ void arch_crash_save_vmcoreinfo(void)
#ifndef CONFIG_NEED_MULTIPLE_NODES
VMCOREINFO_SYMBOL(contig_page_data);
#endif
+#if defined(CONFIG_PPC64) && defined(CONFIG_SPARSEMEM_VMEMMAP)
+ VMCOREINFO_SYMBOL(vmemmap_list);
+ VMCOREINFO_SYMBOL(mmu_vmemmap_psize);
+ VMCOREINFO_SYMBOL(mmu_psize_defs);
+ VMCOREINFO_STRUCT_SIZE(vmemmap_backing);
+ VMCOREINFO_OFFSET(vmemmap_backing, list);
+ VMCOREINFO_OFFSET(vmemmap_backing, phys);
+ VMCOREINFO_OFFSET(vmemmap_backing, virt_addr);
+ VMCOREINFO_STRUCT_SIZE(mmu_psize_def);
+ VMCOREINFO_OFFSET(mmu_psize_def, shift);
+#endif
}
/*
^ permalink raw reply related
* [PATCH] phy: Add Vitesse 8514 phy ID
From: shh.xie @ 2013-11-25 4:40 UTC (permalink / raw)
To: linux-kernel, davem; +Cc: netdev, linuxppc-dev, Shaohui Xie
From: Shaohui Xie <Shaohui.Xie@freescale.com>
Phy is compatible with Vitesse 82xx
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
---
drivers/net/phy/vitesse.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 508e435..14372c6 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -64,6 +64,7 @@
#define PHY_ID_VSC8234 0x000fc620
#define PHY_ID_VSC8244 0x000fc6c0
+#define PHY_ID_VSC8514 0x00070670
#define PHY_ID_VSC8574 0x000704a0
#define PHY_ID_VSC8662 0x00070660
#define PHY_ID_VSC8221 0x000fc550
@@ -131,6 +132,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
err = phy_write(phydev, MII_VSC8244_IMASK,
(phydev->drv->phy_id == PHY_ID_VSC8234 ||
phydev->drv->phy_id == PHY_ID_VSC8244 ||
+ phydev->drv->phy_id == PHY_ID_VSC8514 ||
phydev->drv->phy_id == PHY_ID_VSC8574) ?
MII_VSC8244_IMASK_MASK :
MII_VSC8221_IMASK_MASK);
@@ -246,6 +248,18 @@ static struct phy_driver vsc82xx_driver[] = {
.config_intr = &vsc82xx_config_intr,
.driver = { .owner = THIS_MODULE,},
}, {
+ .phy_id = PHY_ID_VSC8514,
+ .name = "Vitesse VSC8514",
+ .phy_id_mask = 0x000ffff0,
+ .features = PHY_GBIT_FEATURES,
+ .flags = PHY_HAS_INTERRUPT,
+ .config_init = &vsc824x_config_init,
+ .config_aneg = &vsc82x4_config_aneg,
+ .read_status = &genphy_read_status,
+ .ack_interrupt = &vsc824x_ack_interrupt,
+ .config_intr = &vsc82xx_config_intr,
+ .driver = { .owner = THIS_MODULE,},
+}, {
.phy_id = PHY_ID_VSC8574,
.name = "Vitesse VSC8574",
.phy_id_mask = 0x000ffff0,
@@ -315,6 +329,7 @@ module_exit(vsc82xx_exit);
static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
{ PHY_ID_VSC8234, 0x000ffff0 },
{ PHY_ID_VSC8244, 0x000fffc0 },
+ { PHY_ID_VSC8514, 0x000ffff0 },
{ PHY_ID_VSC8574, 0x000ffff0 },
{ PHY_ID_VSC8662, 0x000ffff0 },
{ PHY_ID_VSC8221, 0x000ffff0 },
--
1.8.4.1
^ permalink raw reply related
* RE: [PATCH 0/9 v2] vfio-pci: add support for Freescale IOMMU (PAMU)
From: Bharat Bhushan @ 2013-11-25 5:33 UTC (permalink / raw)
To: Alex Williamson, Scott Wood
Cc: linux-pci@vger.kernel.org, agraf@suse.de, Stuart Yoder,
iommu@lists.linux-foundation.org, bhelgaas@google.com,
linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <1385067648.2879.421.camel@ul30vt.home>
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Cg0K
^ permalink raw reply
* Re: [PATCH v7 0/4] Add dual-fifo mode support of i.MX ssi
From: Shawn Guo @ 2013-11-25 2:11 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
vinod.koul, s.hauer, swarren, timur, rob.herring, linux-kernel,
broonie, dmaengine, dan.j.williams, ijc+devicetree, linuxppc-dev,
linux-arm-kernel
In-Reply-To: <20131122163132.GB17344@MrMyself>
On Sat, Nov 23, 2013 at 12:31:32AM +0800, Nicolin Chen wrote:
> Hi all,
>
> I'm sorry to push this. But this series has been an orphan for a while.
> Could any one please receive and foster it?
Vinod,
I expect you will pick up the series. But otherwise, I can apply it via
IMX tree with your ACKs on the first two patches.
Shawn
^ permalink raw reply
* [PATCH] powerpc/signals: Improved mark VSX not saved with small contexts fix
From: Michael Neuling @ 2013-11-25 0:12 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Carlos O'Donell, Steve Best, linuxppc-dev, Michael Neuling,
Haren Myneni
In a recent patch:
commit c13f20ac48328b05cd3b8c19e31ed6c132b44b42
Author: Michael Neuling <mikey@neuling.org>
powerpc/signals: Mark VSX not saved with small contexts
We fixed an issue but an improved solution was later discussed after the patch
was merged.
Firstly, this patch doesn't handle the 64bit signals case, which could also hit
this issue (but has never been reported).
Secondly, the original patch isn't clear what MSR VSX should be set to. The
new approach below always clears the MSR VSX bit (to indicate no VSX is in the
context) and sets it only in the specific case where VSX is available (ie. when
VSX has been used and the signal context passed has space to provide the
state).
This reverts the original patch and replaces it with the improved solution. It
also adds a 64 bit version.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Cc: stable@vger.kernel.org
---
arch/powerpc/kernel/signal_32.c | 16 +++++++---------
arch/powerpc/kernel/signal_64.c | 6 ++++++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 1844298..68027bf 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -445,6 +445,12 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
#endif /* CONFIG_ALTIVEC */
if (copy_fpr_to_user(&frame->mc_fregs, current))
return 1;
+
+ /*
+ * Clear the MSR VSX bit to indicate there is no valid state attached
+ * to this context, except in the specific case below where we set it.
+ */
+ msr &= ~MSR_VSX;
#ifdef CONFIG_VSX
/*
* Copy VSR 0-31 upper half from thread_struct to local
@@ -457,15 +463,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
if (copy_vsx_to_user(&frame->mc_vsregs, current))
return 1;
msr |= MSR_VSX;
- } else if (!ctx_has_vsx_region)
- /*
- * With a small context structure we can't hold the VSX
- * registers, hence clear the MSR value to indicate the state
- * was not saved.
- */
- msr &= ~MSR_VSX;
-
-
+ }
#endif /* CONFIG_VSX */
#ifdef CONFIG_SPE
/* save spe registers */
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index e66f67b..4299104 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -122,6 +122,12 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs,
flush_fp_to_thread(current);
/* copy fpr regs and fpscr */
err |= copy_fpr_to_user(&sc->fp_regs, current);
+
+ /*
+ * Clear the MSR VSX bit to indicate there is no valid state attached
+ * to this context, except in the specific case below where we set it.
+ */
+ msr &= ~MSR_VSX;
#ifdef CONFIG_VSX
/*
* Copy VSX low doubleword to local buffer for formatting,
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH v5 00/17] add COMMON_CLK support for PowerPC MPC512x
From: Gerhard Sittig @ 2013-11-24 18:39 UTC (permalink / raw)
To: linuxppc-dev, linux-arm-kernel, Anatolij Gustschin,
Mike Turquette
Cc: Mark Rutland, Detlev Zundel, Artem Bityutskiy, linux-mtd,
Jiri Slaby, linux-serial, Wolfgang Grandegger, linux-media,
devicetree, Ian Campbell, Pawel Moll, Stephen Warren, Rob Herring,
linux-can, Mark Brown, Marc Kleine-Budde, Scott Wood,
Greg Kroah-Hartman, linux-usb, linux-spi, Paul Mackerras,
David Woodhouse, Mauro Carvalho Chehab
In-Reply-To: <1384729577-7336-1-git-send-email-gsi@denx.de>
On Mon, Nov 18, 2013 at 00:06 +0100, Gerhard Sittig wrote:
>
> the series is based on v3.12, but I'll rebase against v3.13-rc1
> (when available) or any other subtree upon request
Now that v3.13-rc1 is out, I noticed that the series no longer
applies cleanly (minor context changes and conflicts) and needs
minor adjustment.
Compilation of 4/17 requires <linux/of_address.h> which no longer
is included implicitly.
PPC_CLOCK removal in 7/17 should remove <asm/clk_interface.h> as
well after all references to this header file have gone. (And
the context of the patch has changed.)
The context of 16/17 for DIU initialization has changed.
I'll wait for a few more days whether there is more feedback for
v5 (especially on the device tree backwards compat approach),
then will rebase and send out v6 of the series.
virtually yours
Gerhard Sittig
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply
* Re: Build regressions/improvements in v3.13-rc1
From: Geert Uytterhoeven @ 2013-11-24 9:17 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org
Cc: sparclinux, linux-xtensa@linux-xtensa.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1385233105-20026-1-git-send-email-geert@linux-m68k.org>
On Sat, Nov 23, 2013 at 7:58 PM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> 8 regressions:
> + /scratch/kisskb/src/arch/sparc/kernel/kgdb_64.c: error: implicit declaration of function 'exception_enter' [-Werror=implicit-function-declaration]: => 162:7
> + /scratch/kisskb/src/arch/sparc/kernel/kgdb_64.c: error: implicit declaration of function 'exception_exit' [-Werror=implicit-function-declaration]: => 176:2
sparc64-allmodconfig
> + /scratch/kisskb/src/kernel/bounds.c: error: -mcall-aixdesc must be big endian: => 1:0
> + /scratch/kisskb/src/scripts/mod/devicetable-offsets.c: error: -mcall-aixdesc must be big endian: => 1:0
> + /scratch/kisskb/src/scripts/mod/empty.c: error: -mcall-aixdesc must be big endian: => 1:0
> + <stdin>: error: -mcall-aixdesc must be big endian: => 1:0
powerpc-allmodconfig
powerpc-allyesconfig
> + error: drivers/built-in.o: undefined reference to `i2c_register_driver': => .init.literal+0xd88)
> + error: sram.c: undefined reference to `devm_regmap_init_i2c': => .text+0x58ef8)
xtensa-allmodconfig
sparc-allmodconfig
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
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