* Re: [PATCH] This patch adds support to read error logs from OPAL and export them
From: Mahesh Jagannath Salgaonkar @ 2013-12-16 9:56 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt; +Cc: Vasant Hegde, Mamatha Inamdar
In-Reply-To: <20131216051720.30807.40785.stgit@mars.in.ibm.com>
On 12/16/2013 10:47 AM, Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
>
> to userspace through sysfs interface /sys/firmware/opa/opal-elog.
>
> This patch buffers 128 error log records until it is consumed by userspace
> tool. This patch provides an sysfs interface '/sys/firmware/opa/opal-elog-ack'
> to user to receive an acknowledgement of successful log consumption.
>
> This is what user space tool would do:
> - Read error log from /sys/firmware/opa/opal-elog.
> - Save it to the disk.
> - Send an acknowledgement on successful consumption by writing error log
> id to /sys/firmware/opa/opal-elog-ack.
>
> Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com>
> Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
> Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
Please ignore this patch. I messed up the subject line, I dunno how.. My
bad. I will resend this patch with correct subject.
Thanks,
-Mahesh.
^ permalink raw reply
* [PATCH] powerpc/powernv: Read opal error log and export it through sysfs interface.
From: Mahesh J Salgaonkar @ 2013-12-16 9:58 UTC (permalink / raw)
To: linuxppc-dev, Benjamin Herrenschmidt; +Cc: Vasant Hegde, Mamatha Inamdar
From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
This patch adds support to read error logs from OPAL and export them
to userspace through sysfs interface /sys/firmware/opa/opal-elog.
This patch buffers 128 error log records until it is consumed by userspace
tool. This patch provides an sysfs interface '/sys/firmware/opa/opal-elog-ack'
to user to receive an acknowledgement of successful log consumption.
This is what user space tool would do:
- Read error log from /sys/firmware/opa/opal-elog.
- Save it to the disk.
- Send an acknowledgement on successful consumption by writing error log
id to /sys/firmware/opa/opal-elog-ack.
Signed-off-by: Mamatha Inamdar <mamatha4@linux.vnet.ibm.com>
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/opal.h | 11 +
arch/powerpc/platforms/powernv/Makefile | 2
arch/powerpc/platforms/powernv/opal-elog.c | 309 ++++++++++++++++++++++++
arch/powerpc/platforms/powernv/opal-wrappers.S | 5
arch/powerpc/platforms/powernv/opal.c | 2
5 files changed, 328 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/platforms/powernv/opal-elog.c
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 5462fa7..723a7db 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -129,6 +129,11 @@ extern int opal_enter_rtas(struct rtas_args *args,
#define OPAL_LPC_READ 67
#define OPAL_LPC_WRITE 68
#define OPAL_RETURN_CPU 69
+#define OPAL_ELOG_READ 71
+#define OPAL_ELOG_WRITE 72
+#define OPAL_ELOG_ACK 73
+#define OPAL_ELOG_RESEND 74
+#define OPAL_ELOG_SIZE 75
#define OPAL_FLASH_VALIDATE 76
#define OPAL_FLASH_MANAGE 77
#define OPAL_FLASH_UPDATE 78
@@ -727,6 +732,11 @@ int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
uint32_t addr, uint32_t data, uint32_t sz);
int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
uint32_t addr, uint32_t *data, uint32_t sz);
+int64_t opal_read_elog(uint64_t buffer, size_t size, uint64_t log_id);
+int64_t opal_get_elog_size(uint64_t *log_id, size_t *size, uint64_t *elog_type);
+int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
+int64_t opal_send_ack_elog(uint64_t log_id);
+void opal_resend_pending_logs(void);
int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
int64_t opal_manage_flash(uint8_t op);
int64_t opal_update_flash(uint64_t blk_list);
@@ -761,6 +771,7 @@ extern void opal_get_rtc_time(struct rtc_time *tm);
extern unsigned long opal_get_boot_time(void);
extern void opal_nvram_init(void);
extern void opal_flash_init(void);
+extern int opal_elog_init(void);
extern int opal_machine_check(struct pt_regs *regs);
extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index 873fa13..0f692eb 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -1,6 +1,6 @@
obj-y += setup.o opal-takeover.o opal-wrappers.o opal.o
obj-y += opal-rtc.o opal-nvram.o opal-lpc.o opal-flash.o
-obj-y += rng.o
+obj-y += rng.o opal-elog.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_PCI) += pci.o pci-p5ioc2.o pci-ioda.o
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c b/arch/powerpc/platforms/powernv/opal-elog.c
new file mode 100644
index 0000000..fc891ae
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/opal-elog.c
@@ -0,0 +1,309 @@
+/*
+ * Error log support on PowerNV.
+ *
+ * Copyright 2013 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/fs.h>
+#include <linux/vmalloc.h>
+#include <linux/fcntl.h>
+#include <asm/uaccess.h>
+#include <asm/opal.h>
+
+/* Maximum size of a single log on FSP is 16KB */
+#define OPAL_MAX_ERRLOG_SIZE 16384
+
+/* maximu number of records powernv can hold */
+#define MAX_NUM_RECORD 128
+
+struct opal_err_log {
+ struct list_head link;
+ uint64_t opal_log_id;
+ size_t opal_log_size;
+ uint8_t data[OPAL_MAX_ERRLOG_SIZE];
+};
+
+/* Pre-allocated temp buffer to pull error log from opal. */
+static uint8_t err_log_data[OPAL_MAX_ERRLOG_SIZE];
+/* Protect err_log_data buf */
+static DEFINE_MUTEX(err_log_data_mutex);
+
+static uint64_t total_log_size;
+static bool opal_log_available;
+static LIST_HEAD(elog_list);
+static LIST_HEAD(elog_ack_list);
+
+/* lock to protect elog_list and elog-ack_list. */
+static DEFINE_SPINLOCK(opal_elog_lock);
+
+static DECLARE_WAIT_QUEUE_HEAD(opal_log_wait);
+
+/*
+ * Interface for user to acknowledge the error log.
+ *
+ * Once user acknowledge the log, we delete that record entry from the
+ * list and move it ack list.
+ */
+void opal_elog_ack(uint64_t ack_id)
+{
+ unsigned long flags;
+ struct opal_err_log *record, *next;
+ bool found = false;
+
+ printk(KERN_INFO "OPAL Log ACK=%llx", ack_id);
+
+ /* once user acknowledge a log delete record from list */
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ list_for_each_entry_safe(record, next, &elog_list, link) {
+ if (ack_id == record->opal_log_id) {
+ list_del(&record->link);
+ list_add(&record->link, &elog_ack_list);
+ total_log_size -= OPAL_MAX_ERRLOG_SIZE;
+ found = true;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+
+ /* Send acknowledgement to FSP */
+ if (found)
+ opal_send_ack_elog(ack_id);
+ return;
+}
+
+
+static ssize_t elog_ack_store(struct kobject *kobj,
+ struct kobj_attribute *attr,
+ const char *buf, size_t count)
+{
+ uint32_t log_ack_id;
+ log_ack_id = *(uint32_t *) buf;
+
+ /* send acknowledgment to FSP */
+ opal_elog_ack(log_ack_id);
+ return 0;
+}
+
+/*
+ * Show error log records to user.
+ */
+static ssize_t opal_elog_show(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr, char *buf,
+ loff_t pos, size_t count)
+{
+ unsigned long flags;
+ struct opal_err_log *record, *next;
+ size_t size = 0;
+ size_t data_to_copy = 0;
+ int error = 0;
+
+ /* Display one log at a time. */
+ if (count > OPAL_MAX_ERRLOG_SIZE)
+ count = OPAL_MAX_ERRLOG_SIZE;
+
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ /* Align the pos to point within total errlog size. */
+ if (total_log_size && pos > total_log_size)
+ pos = pos % total_log_size;
+
+ /*
+ * if pos goes beyond total_log_size then we know we don't have any
+ * new record to show.
+ */
+ if (total_log_size == 0 || pos >= total_log_size) {
+ opal_log_available = 0;
+ if (filp->f_flags & O_NONBLOCK) {
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+ error = -EAGAIN;
+ goto out;
+ }
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+ pos = 0;
+
+ /* Wait until we get log from sapphire */
+ error = wait_event_interruptible(opal_log_wait,
+ opal_log_available);
+ if (error)
+ goto out;
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ }
+
+ /*
+ * Show log record one by one through /sys/firmware/opal/opal_elog
+ */
+ list_for_each_entry_safe(record, next, &elog_list, link) {
+ if ((pos >= size) && (pos < (size + OPAL_MAX_ERRLOG_SIZE))) {
+ data_to_copy = OPAL_MAX_ERRLOG_SIZE - (pos - size);
+ if (count > data_to_copy)
+ count = data_to_copy;
+ memcpy(buf, record->data + (pos - size), count);
+ error = count;
+ break;
+ }
+ size += OPAL_MAX_ERRLOG_SIZE;
+ }
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+out:
+ return error;
+}
+
+/* Interface to read log from OPAL */
+static void opal_elog_read(void)
+{
+ struct opal_err_log *record;
+ size_t elog_size;
+ uint64_t log_id;
+ uint64_t elog_type;
+
+ unsigned long flags;
+ int rc = 0;
+
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ if (list_empty(&elog_ack_list)) {
+ /*
+ * We have no more room to read logs. Ignore it for now,
+ * will read it later when we have enough space.
+ */
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+ return;
+ }
+
+ /* Pull out the free node. */
+ record = list_entry(elog_ack_list.next, struct opal_err_log, link);
+ list_del(&record->link);
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+
+ /* read log size and log ID from OPAL */
+ rc = opal_get_elog_size(&log_id, &elog_size, &elog_type);
+ if (rc != OPAL_SUCCESS) {
+ pr_err("ELOG: Opal log read failed\n");
+ return;
+ }
+ if (elog_size >= OPAL_MAX_ERRLOG_SIZE)
+ elog_size = OPAL_MAX_ERRLOG_SIZE;
+
+ record->opal_log_id = log_id;
+ record->opal_log_size = elog_size;
+ memset(record->data, 0, sizeof(record->data));
+
+ mutex_lock(&err_log_data_mutex);
+ rc = opal_read_elog(__pa(err_log_data), elog_size, log_id);
+ if (rc != OPAL_SUCCESS) {
+ mutex_unlock(&err_log_data_mutex);
+ pr_err("ELOG: log read failed for log-id=%llx\n", log_id);
+ /* put back the free node. */
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ list_add(&record->link, &elog_ack_list);
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+ return;
+ }
+ memcpy(record->data, err_log_data, elog_size);
+ mutex_unlock(&err_log_data_mutex);
+
+ spin_lock_irqsave(&opal_elog_lock, flags);
+ list_add_tail(&record->link, &elog_list);
+ total_log_size += OPAL_MAX_ERRLOG_SIZE;
+ spin_unlock_irqrestore(&opal_elog_lock, flags);
+
+ opal_log_available = 1;
+ wake_up_interruptible(&opal_log_wait);
+ return;
+}
+
+static void elog_work_fn(struct work_struct *work)
+{
+ opal_elog_read();
+}
+
+static DECLARE_WORK(elog_work, elog_work_fn);
+
+static int elog_event(struct notifier_block *nb,
+ unsigned long events, void *change)
+{
+ /* check for error log event */
+ if (events & OPAL_EVENT_ERROR_LOG_AVAIL)
+ schedule_work(&elog_work);
+ return 0;
+}
+
+/* Initialize sysfs file */
+static struct kobj_attribute opal_elog_ack_attr = __ATTR(opal_elog_ack,
+ 0200, NULL, elog_ack_store);
+
+static struct notifier_block elog_nb = {
+ .notifier_call = elog_event,
+ .next = NULL,
+ .priority = 0
+};
+
+static struct bin_attribute opal_elog_attr = {
+ .attr = {.name = "opal_elog", .mode = 0400},
+ .read = opal_elog_show,
+};
+
+/*
+ * Pre-allocate a buffer to hold handful of error logs until user space
+ * consumes it.
+ */
+static int init_err_log_buffer(void)
+{
+ int i = 0;
+ struct opal_err_log *buf_ptr;
+
+ buf_ptr = vmalloc(sizeof(struct opal_err_log) * MAX_NUM_RECORD);
+ if (!buf_ptr) {
+ printk(KERN_ERR "ELOG: failed to allocate memory.\n");
+ return -ENOMEM;
+ }
+ memset(buf_ptr, 0, sizeof(struct opal_err_log) * MAX_NUM_RECORD);
+
+ /* Initialize ack list will all free nodes. */
+ for (i = 0; i < MAX_NUM_RECORD; i++, buf_ptr++)
+ list_add(&buf_ptr->link, &elog_ack_list);
+ return 0;
+}
+
+/* Initialize error logging */
+int __init opal_elog_init(void)
+{
+ int rc = 0;
+
+ rc = init_err_log_buffer();
+ if (rc)
+ return rc;
+
+ rc = sysfs_create_bin_file(opal_kobj, &opal_elog_attr);
+ if (rc) {
+ printk(KERN_ERR "ELOG: unable to create sysfs file"
+ "opal_elog (%d)\n", rc);
+ return rc;
+ }
+
+ rc = sysfs_create_file(opal_kobj, &opal_elog_ack_attr.attr);
+ if (rc) {
+ printk(KERN_ERR "ELOG: unable to create sysfs file"
+ " opal_elog_ack (%d)\n", rc);
+ return rc;
+ }
+
+ rc = opal_notifier_register(&elog_nb);
+ if (rc) {
+ pr_err("%s: Can't register OPAL event notifier (%d)\n",
+ __func__, rc);
+ return rc;
+ }
+
+ /* We are now ready to pull error logs from opal. */
+ opal_resend_pending_logs();
+
+ return 0;
+}
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index e780650..a040b02 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -123,6 +123,11 @@ OPAL_CALL(opal_xscom_write, OPAL_XSCOM_WRITE);
OPAL_CALL(opal_lpc_read, OPAL_LPC_READ);
OPAL_CALL(opal_lpc_write, OPAL_LPC_WRITE);
OPAL_CALL(opal_return_cpu, OPAL_RETURN_CPU);
+OPAL_CALL(opal_read_elog, OPAL_ELOG_READ);
+OPAL_CALL(opal_send_ack_elog, OPAL_ELOG_ACK);
+OPAL_CALL(opal_get_elog_size, OPAL_ELOG_SIZE);
+OPAL_CALL(opal_resend_pending_logs, OPAL_ELOG_RESEND);
+OPAL_CALL(opal_write_elog, OPAL_ELOG_WRITE);
OPAL_CALL(opal_validate_flash, OPAL_FLASH_VALIDATE);
OPAL_CALL(opal_manage_flash, OPAL_FLASH_MANAGE);
OPAL_CALL(opal_update_flash, OPAL_FLASH_UPDATE);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 31053be..20e1834 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -475,6 +475,8 @@ static int __init opal_init(void)
/* Create "opal" kobject under /sys/firmware */
rc = opal_sysfs_init();
if (rc == 0) {
+ /* Setup error log interface */
+ rc = opal_elog_init();
/* Setup code update interface */
opal_flash_init();
}
^ permalink raw reply related
* [PATCH 2/2] drivers: tty: Mark the function hvc_poll_init() as static in hvc_console.c
From: Rashika Kheria @ 2013-12-16 11:01 UTC (permalink / raw)
To: linux-kernel
Cc: Greg Kroah-Hartman, linuxppc-dev, josh, Rashika Kheria,
Hendrik Brueckner, Jiri Slaby
In-Reply-To: <0d40902c95942d272a70b1d85b4e311d0cc7afa4.1387191158.git.rashika.kheria@gmail.com>
Mark the function hvc_poll_init() as static in hvc/hvc_console.c because
it is not used outside this file.
This eliminates the following warning in hvc/hvc_console.c:
drivers/tty/hvc/hvc_console.c:791:5: warning: no previous prototype for ‘hvc_poll_init’ [-Wmissing-prototypes]
Signed-off-by: Rashika Kheria <rashika.kheria@gmail.com>
---
drivers/tty/hvc/hvc_console.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_console.c
index 9eba119..50b4688 100644
--- a/drivers/tty/hvc/hvc_console.c
+++ b/drivers/tty/hvc/hvc_console.c
@@ -788,7 +788,7 @@ static int hvc_tiocmset(struct tty_struct *tty,
}
#ifdef CONFIG_CONSOLE_POLL
-int hvc_poll_init(struct tty_driver *driver, int line, char *options)
+static int hvc_poll_init(struct tty_driver *driver, int line, char *options)
{
return 0;
}
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH 2/2] drivers: tty: Mark the function hvc_poll_init() as static in hvc_console.c
From: Josh Triplett @ 2013-12-16 11:11 UTC (permalink / raw)
To: Rashika Kheria
Cc: Greg Kroah-Hartman, Hendrik Brueckner, Jiri Slaby, linux-kernel,
linuxppc-dev
In-Reply-To: <0dc41f5b30bf9b5c94e658387ffaf092736c26b2.1387191158.git.rashika.kheria@gmail.com>
On Mon, Dec 16, 2013 at 04:31:28PM +0530, Rashika Kheria wrote:
> Mark the function hvc_poll_init() as static in hvc/hvc_console.c becaus=
e
> it is not used outside this file.
>=20
> This eliminates the following warning in hvc/hvc_console.c:
> drivers/tty/hvc/hvc_console.c:791:5: warning: no previous prototype for=
=E2=80=98hvc_poll_init=E2=80=99 [-Wmissing-prototypes]
>=20
> Signed-off-by: Rashika Kheria <rashika.kheria@gmail.com>
Reviewed-by: Josh Triplett <josh@joshtriplett.org>
> drivers/tty/hvc/hvc_console.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/tty/hvc/hvc_console.c b/drivers/tty/hvc/hvc_consol=
e.c
> index 9eba119..50b4688 100644
> --- a/drivers/tty/hvc/hvc_console.c
> +++ b/drivers/tty/hvc/hvc_console.c
> @@ -788,7 +788,7 @@ static int hvc_tiocmset(struct tty_struct *tty,
> }
> =20
> #ifdef CONFIG_CONSOLE_POLL
> -int hvc_poll_init(struct tty_driver *driver, int line, char *options)
> +static int hvc_poll_init(struct tty_driver *driver, int line, char *op=
tions)
> {
> return 0;
> }
> --=20
> 1.7.9.5
>=20
^ permalink raw reply
* [PATCH v2] powerpc/powernv: Framework to log critical errors on powernv.
From: Deepthi Dharwar @ 2013-12-16 12:30 UTC (permalink / raw)
To: PowerPC email list
This patch provides error logging interfaces to report critical
powernv error to FSP.
All the required information to dump the error is collected
at POWERNV level through error log interfaces
and then pushed on to FSP.
This also supports synchronous error logging in cases of
PANIC, by passing OPAL_ERROR_PANIC as severity in
elog_create() call.
Signed-off-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/opal.h | 125 ++++++++++++++++++++++++
arch/powerpc/platforms/powernv/opal-elog.c | 60 +++++++++++-
arch/powerpc/platforms/powernv/opal-wrappers.S | 1
3 files changed, 185 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 0f01308..1c5440a 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -168,6 +168,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
#define OPAL_GET_MSG 85
#define OPAL_CHECK_ASYNC_COMPLETION 86
#define OPAL_SYNC_HOST_REBOOT 87
+#define OPAL_ELOG_SEND 88
#ifndef __ASSEMBLY__
@@ -260,6 +261,122 @@ enum OpalMessageType {
OPAL_MSG_TYPE_MAX,
};
+/* Classification of Error/Events reporting type classification
+ * Platform Events/Errors: Report Machine Check Interrupt
+ * INPUT_OUTPUT: Report all I/O related events/errors
+ * RESOURCE_DEALLOC: Hotplug events and errors
+ * MISC: Miscellanous error
+ * Field: error_events_type
+ */
+enum error_events {
+ OPAL_PLATFORM,
+ OPAL_INPUT_OUTPUT,
+ OPAL_RESOURCE_DEALLOC,
+ OPAL_MISC,
+};
+
+/* OPAL Subsystem IDs listed for reporting events/errors
+ * Field: subsystem_id
+ */
+
+#define OPAL_PROCESSOR_SUBSYSTEM 0x10
+#define OPAL_MEMORY_SUBSYSTEM 0x20
+#define OPAL_IO_SUBSYSTEM 0x30
+#define OPAL_IO_DEVICES 0x40
+#define OPAL_CEC_HARDWARE 0x50
+#define OPAL_POWER_COOLING 0x60
+#define OPAL_MISC_SUBSYSTEM 0x70
+#define OPAL_SURVEILLANCE_ERR 0x7A
+#define OPAL_PLATFORM_FIRMWARE 0x80
+#define OPAL_SOFTWARE 0x90
+#define OPAL_EXTERNAL_ENV 0xA0
+
+/* During reporting an event/error the following represents
+ * how serious the logged event/error is. (Severity)
+ * Field: event_sev
+ */
+#define OPAL_INFO 0x00
+#define OPAL_RECOVERED_ERR_GENERAL 0x10
+
+/* 0x2X series is to denote set of Predictive Error
+ * 0x20 Generic predictive error
+ * 0x21 Predictive error, degraded performance
+ * 0x22 Predictive error, fault may be corrected after reboot
+ * 0x23 Predictive error, fault may be corrected after reboot,
+ * degraded performance
+ * 0x24 Predictive error, loss of redundancy
+ */
+#define OPAL_PREDICTIVE_ERR_GENERAL 0x20
+#define OPAL_PREDICTIVE_ERR_DEGRADED_PERF 0x21
+#define OPAL_PREDICTIVE_ERR_FAULT_RECTIFY_REBOOT 0x22
+#define OPAL_PREDICTIVE_ERR_FAULT_RECTIFY_BOOT_DEGRADE_PERF 0x23
+#define OPAL_PREDICTIVE_ERR_LOSS_OF_REDUNDANCY 0x24
+
+/* 0x4X series for Unrecoverable Error
+ * 0x40 Generic Unrecoverable error
+ * 0x41 Unrecoverable error bypassed with degraded performance
+ * 0x44 Unrecoverable error bypassed with loss of redundancy
+ * 0x45 Unrecoverable error bypassed with loss of redundancy and performance
+ * 0x48 Unrecoverable error bypassed with loss of function
+ */
+#define OPAL_UNRECOVERABLE_ERR_GENERAL 0x40
+#define OPAL_UNRECOVERABLE_ERR_DEGRADE_PERF 0x41
+#define OPAL_UNRECOVERABLE_ERR_LOSS_REDUNDANCY 0x44
+#define OPAL_UNRECOVERABLE_ERR_LOSS_REDUNDANCY_PERF 0x45
+#define OPAL_UNRECOVERABLE_ERR_LOSS_OF_FUNCTION 0x48
+#define OPAL_ERROR_PANIC 0x50
+
+/* Event Sub-type
+ * This field provides additional information on the non-error
+ * event type
+ * Field: event_subtype
+ */
+#define OPAL_NA 0x00
+#define OPAL_MISCELLANEOUS_INFO_ONLY 0x01
+#define OPAL_PREV_REPORTED_ERR_RECTIFIED 0x10
+#define OPAL_SYS_RESOURCES_DECONFIG_BY_USER 0x20
+#define OPAL_SYS_RESOURCE_DECONFIG_PRIOR_ERR 0x21
+#define OPAL_RESOURCE_DEALLOC_EVENT_NOTIFY 0x22
+#define OPAL_CONCURRENT_MAINTENANCE_EVENT 0x40
+#define OPAL_CAPACITY_UPGRADE_EVENT 0x60
+#define OPAL_RESOURCE_SPARING_EVENT 0x70
+#define OPAL_DYNAMIC_RECONFIG_EVENT 0x80
+#define OPAL_NORMAL_SYS_PLATFORM_SHUTDOWN 0xD0
+#define OPAL_ABNORMAL_POWER_OFF 0xE0
+
+/* Max user dump size is 14K */
+#define OPAL_LOG_MAX_DUMP 14336
+
+/* Multiple user data sections */
+struct opal_usr_data_scn {
+ uint32_t tag;
+ uint16_t size;
+ uint16_t component_id;
+ char data_dump[4];
+};
+
+/* All the information regarding an error/event to be reported
+ * needs to populate this structure using pre-defined interfaces
+ * only
+ */
+struct opal_errorlog {
+
+ uint16_t component_id;
+ uint8_t error_events_type:3;
+ uint8_t subsystem_id;
+
+ uint8_t event_sev;
+ uint8_t event_subtype;
+ uint8_t usr_scn_count; /* User section count */
+ uint8_t elog_origin;
+
+ uint32_t usr_scn_size; /* User section size */
+ uint32_t reason_code;
+ uint32_t additional_info[4];
+
+ char usr_data_dump[OPAL_LOG_MAX_DUMP];
+};
+
/* Machine check related definitions */
enum OpalMCE_Version {
OpalMCE_V1 = 1,
@@ -853,6 +970,14 @@ int64_t opal_dump_ack(uint32_t dump_id);
int64_t opal_get_msg(uint64_t buffer, size_t size);
int64_t opal_check_completion(uint64_t buffer, size_t size, uint64_t token);
int64_t opal_sync_host_reboot(void);
+struct opal_errorlog *elog_create(uint8_t err_evt_type, uint16_t component_id,
+ uint8_t subsystem_id, uint8_t event_sev, uint8_t event_subtype,
+ uint32_t reason_code, uint32_t info0, uint32_t info1,
+ uint32_t info2, uint32_t info3);
+int update_user_dump(struct opal_errorlog *buf, unsigned char *data,
+ uint32_t tag, uint16_t size);
+void commit_errorlog_to_fsp(struct opal_errorlog *buf);
+int opal_commit_log_to_fsp(void *buf);
/* Internal functions */
extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c b/arch/powerpc/platforms/powernv/opal-elog.c
index 58849d0..ade1e58 100644
--- a/arch/powerpc/platforms/powernv/opal-elog.c
+++ b/arch/powerpc/platforms/powernv/opal-elog.c
@@ -15,6 +15,7 @@
#include <linux/sysfs.h>
#include <linux/fs.h>
#include <linux/vmalloc.h>
+#include <linux/mm.h>
#include <linux/fcntl.h>
#include <asm/uaccess.h>
#include <asm/opal.h>
@@ -22,7 +23,9 @@
/* Maximum size of a single log on FSP is 16KB */
#define OPAL_MAX_ERRLOG_SIZE 16384
-/* maximu number of records powernv can hold */
+#define USR_CHAR_ARRAY_FIXED_SIZE 4
+
+/* Maximum number of records powernv can hold */
#define MAX_NUM_RECORD 128
struct opal_err_log {
@@ -272,6 +275,61 @@ static int init_err_log_buffer(void)
return 0;
}
+/* Interface to be used by POWERNV to push the logs to FSP via Sapphire */
+struct opal_errorlog *elog_create(uint8_t err_evt_type, uint16_t component_id,
+ uint8_t subsystem_id, uint8_t event_sev, uint8_t event_subtype,
+ uint32_t reason_code, uint32_t info0, uint32_t info1,
+ uint32_t info2, uint32_t info3)
+{
+ struct opal_errorlog *buf;
+
+ buf = kzalloc(sizeof(struct opal_errorlog), GFP_KERNEL);
+ if (!buf) {
+ printk(KERN_ERR "ELOG: failed to allocate memory.\n");
+ return NULL;
+ }
+
+ buf->error_events_type = err_evt_type;
+ buf->component_id = component_id;
+ buf->subsystem_id = subsystem_id;
+ buf->event_sev = event_sev;
+ buf->event_subtype = event_subtype;
+ buf->reason_code = reason_code;
+ buf->additional_info[0] = info0;
+ buf->additional_info[1] = info1;
+ buf->additional_info[2] = info2;
+ buf->additional_info[3] = info3;
+ return buf;
+}
+
+int update_user_dump(struct opal_errorlog *buf, unsigned char *data,
+ uint32_t tag, uint16_t size)
+{
+ char *buffer = (char *)buf->usr_data_dump + buf->usr_scn_size;
+ struct opal_usr_data_scn *tmp;
+
+ if ((buf->usr_scn_size + size) > OPAL_LOG_MAX_DUMP) {
+ printk(KERN_ERR "ELOG: Size of dump data overruns buffer");
+ return -1;
+ }
+
+ tmp = (struct opal_usr_data_scn *)buffer;
+ tmp->tag = tag;
+ tmp->size = size + sizeof(struct opal_usr_data_scn)
+ - USR_CHAR_ARRAY_FIXED_SIZE;
+ memcpy(tmp->data_dump, data, size);
+
+ buf->usr_scn_size += tmp->size;
+ buf->usr_scn_count++;
+ return 0;
+}
+
+void commit_errorlog_to_fsp(struct opal_errorlog *buf)
+{
+ opal_commit_log_to_fsp((void *)(vmalloc_to_pfn(buf) << PAGE_SHIFT));
+ kfree(buf);
+}
+
/* Initialize error logging */
static int __init opal_elog_init(void)
{
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index ad318d8..821d8a2 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -133,3 +133,4 @@ OPAL_CALL(opal_dump_ack, OPAL_DUMP_ACK);
OPAL_CALL(opal_get_msg, OPAL_GET_MSG);
OPAL_CALL(opal_check_completion, OPAL_CHECK_ASYNC_COMPLETION);
OPAL_CALL(opal_sync_host_reboot, OPAL_SYNC_HOST_REBOOT);
+OPAL_CALL(opal_commit_log_to_fsp, OPAL_ELOG_SEND);
Regards,
Deepthi
^ permalink raw reply related
* Re: [PATCH 10/10] Kconfig: cleanup SERIO_I8042 dependencies
From: Ralf Baechle @ 2013-12-16 16:23 UTC (permalink / raw)
To: Mark Salter
Cc: linux-mips, linux-ia64, linux-sh, Paul Mackerras, H. Peter Anvin,
sparclinux, Guan Xuetao, Russell King, x86, Ingo Molnar,
Fenghua Yu, Thomas Gleixner, linux-arm-kernel, Richard Henderson,
Tony Luck, Dmitry Torokhov, linux-kernel, Paul Mundt, linux-alpha,
linuxppc-dev, David S. Miller
In-Reply-To: <1387040376-26906-11-git-send-email-msalter@redhat.com>
On Sat, Dec 14, 2013 at 11:59:36AM -0500, Mark Salter wrote:
> - depends on !PARISC && (!ARM || FOOTBRIDGE_HOST) && \
> - (!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN && !S390 && \
> - !ARC
> + depends on ARCH_MIGHT_HAVE_PC_SERIO
Most dependencies on an architecture's kconfig symbol outside arch/
should probably be treated as a bug.
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Ralf
^ permalink raw reply
* Re: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Scott Wood @ 2013-12-16 18:26 UTC (permalink / raw)
To: Wang Dongsheng-B40534
Cc: Bhushan Bharat-R65777, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <0ba4966fa6b54478b2885a0b97f4c2bf@BY2PR03MB191.namprd03.prod.outlook.com>
On Sun, 2013-12-15 at 23:53 -0600, Wang Dongsheng-B40534 wrote:
>
> > -----Original Message-----
> > From: Bhushan Bharat-R65777
> > Sent: Monday, November 11, 2013 12:11 PM
> > To: Wang Dongsheng-B40534; Wood Scott-B07421
> > Cc: linuxppc-dev@lists.ozlabs.org
> > Subject: RE: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altivec
> > idle
> >
> > > > Those codes just for discuss with Bharat. He want to make one flow at
> > > > "show_pw20_wait_time"/" show_altivec_idle_wait_time" function. If we
> > > > do that, we need to initialize pw20_wt/altivec_idle_wt.
> > > >
> > > I will keep this stuff at "show_pw20_wait_time"/"show_altivec_idle_wait_time"
> > > and add a comment before our discussion.
> > >
> > > /*
> > > * If the "value" less than 10, this will overflow.
> > > * From benchmark test, the default wait bit will not be set less than 10bit.
> > > * Because 10 bit corresponds to the wait entry time is 439375573401999609(ns),
> > > * for wait-entry-idle time this value looks too long, and we cannot use those
> > > * "long" time as a default wait-entry time. So overflow could not have
> > happened
> > > * and we use this calculation method to get wait-entry-idle time.
> > > */
> >
> > I think now we will use same calculation code for default value and user set
> > value, so adding the comment is not sufficient, we should error out from the
> > code if value is less than 10. As default value is not less than 10 so this will
> > always work with default value but if user tries to set less than 10 then error
> > out and ask user to try more than 9.
> >
> Again, once the user has set up a time, the code will go to another branch.
>
> else {
> time = pw20_wt;
> }
>
> We do so much for this a little function processing is not worth it. If we can't
> agree on this sys interface. I will change this sys interface to show_pw20_wait_bit. :)
Please don't change it.
-Scott
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
From: Scott Wood @ 2013-12-16 18:37 UTC (permalink / raw)
To: Hongbo Zhang; +Cc: linuxppc-dev@lists.ozlabs.org, Liu Shengzhou-B36685
In-Reply-To: <52AEC40C.6000008@freescale.com>
On Mon, 2013-12-16 at 17:12 +0800, Hongbo Zhang wrote:
> On 12/13/2013 01:43 PM, Liu Shengzhou-B36685 wrote:
> >
> >> -----Original Message-----
> >> From: Hongbo Zhang [mailto:hongbo.zhang@freescale.com]
> >> Sent: Thursday, December 12, 2013 5:57 PM
> >> To: Liu Shengzhou-B36685; linuxppc-dev@lists.ozlabs.org; Wood Scott-
> >> B07421
> >> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
> >>
> >> Shengzhou,
> >> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
> >> original wrong elo3-dma-2.dtsi hadn't been merged.
> >> But please pay attention to comments from Scott about my changes of
> >> adding 208 for some interrupts, and take some actions if needed, or
> >> further discussions.
> >>
> >> Below comments form Scott:
> >> "The FSL MPIC binding should be updated to point out how this works.
> >> Technically it's not a change to the binding itself, since it's defined
> >> in terms of register offset, but the explanatory text says "So interrupt
> >> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
> >> not accurate for these new high interrupt numbers."
> >>
> > Hongbo,
> > Could you update FSL MPIC binding as Scott pointed out?
>
> We only need to add more explanatory text after the sentence Scott
> pointed out, like:
> "But for some hardwares, the MPIC registers for interrupts are not
> continuous in address, in such cases, an offset can be added to the
> interrupt number to skip the registers which is not for interrupts."
>
> Scott, is that OK?
Actually, I misread what that sentence actually says, and it's correct
as is -- but not as helpful as it could be.
I'd add this new paragraph instead:
For example, internal interrupt 0 is at offset 0x200 and thus is
interrupt 16 in the device tree. MSI bank A interrupt 0 is at offset
0x1c00, and thus is interrupt 224. MPIC v4.3 adds a new discontiguous
address range for internal interrupts, so internal interrupt 160 is at
offset 0x3000, and thus is interrupt 384.
-Scott
^ permalink raw reply
* Re: [PATCH v2] powerpc 8xx: Loading kernels over 8Mbytes without CONFIG_PIN_TLB
From: Scott Wood @ 2013-12-16 22:57 UTC (permalink / raw)
To: leroy christophe; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <52A7A58F.8090705@c-s.fr>
On Wed, 2013-12-11 at 00:36 +0100, leroy christophe wrote:
> Le 11/12/2013 00:18, Scott Wood a écrit :
> > There wasn't previously an ifdef specifically around the setting of
> > SPRN_MD_CTR. That's new. There was an ifdef around the entire block,
> > which has gone away because you are now trying to map more than 8M
> > regardless of CONFIG_PIN_TLB, but that has nothing to do with whether
> > there should be an ifdef around SPRN_MD_CTR.
> >
> >
> Euh, ok, but then we have to fix it in the whole function, not only in
> this block. Do you think it is worth doing it ?
Fix what in the whole function? I was asking what harm there would be
if you just remove all the CONFIG_PIN_TLB ifdefs except around the
actual RSV4I setting -- do we really care what value goes in MD_CTR for
the non-pinned case, as long as it's different for each entry?
-Scott
^ permalink raw reply
* Re: [PATCH 2/8] IBM Akebono: Add a SDHCI platform driver
From: Alistair Popple @ 2013-12-17 1:11 UTC (permalink / raw)
To: linuxppc-dev, Chris Ball, linux-mmc; +Cc: linuxppc-dev
In-Reply-To: <1385086116-10972-2-git-send-email-alistair@popple.id.au>
Hi,
I originally sent this to the linuxppc-dev list thinking Ben H might ta=
ke it,=20
however it should go through the appropriate subsystem. Can someone ple=
ase=20
merge it into the appropriate tree (unless the are problems with it)?
Thanks.
Regards,
Alistair
On Fri, 22 Nov 2013 13:08:30 Alistair Popple wrote:
> This patch adds a SDHCI platform driver for the new IBM PPC476GTR SoC=
> which is on the Akebono board.
>=20
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> Cc: Chris Ball <cjb@laptop.org>
> Cc: linux-mmc@vger.kernel.org
> ---
> drivers/mmc/host/Kconfig | 12 ++++++++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-476gtr.c | 60
> ++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+=
)
> create mode 100644 drivers/mmc/host/sdhci-of-476gtr.c
>=20
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 7fc5099..14210df 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -130,6 +130,18 @@ config MMC_SDHCI_OF_HLWD
>=20
> =09 If unsure, say N.
>=20
> +config MMC_SDHCI_OF_476GTR
> +=09tristate "SDHCI OF support for the IBM PPC476GTR SoC"
> +=09depends on MMC_SDHCI_PLTFM
> +=09depends on PPC_OF
> +=09help
> +=09 This selects the Secure Digital Host Controller Interface (SDHC=
I)
> +=09 found on the PPC476GTR SoC.
> +
> +=09 If you have a controller with this interface, say Y or M here.
> +
> +=09 If unsure, say N.
> +
> config MMC_SDHCI_CNS3XXX
> =09tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
> =09depends on ARCH_CNS3XXX
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index c41d0c3..92beff3 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -59,6 +59,7 @@ obj-$(CONFIG_MMC_SDHCI_DOVE)=09=09+=3D sdhci-dove.o=
> obj-$(CONFIG_MMC_SDHCI_TEGRA)=09=09+=3D sdhci-tegra.o
> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)=09+=3D sdhci-of-esdhc.o
> obj-$(CONFIG_MMC_SDHCI_OF_HLWD)=09=09+=3D sdhci-of-hlwd.o
> +obj-$(CONFIG_MMC_SDHCI_OF_476GTR)=09+=3D sdhci-of-476gtr.o
> obj-$(CONFIG_MMC_SDHCI_BCM_KONA)=09+=3D sdhci-bcm-kona.o
> obj-$(CONFIG_MMC_SDHCI_BCM2835)=09=09+=3D sdhci-bcm2835.o
>=20
> diff --git a/drivers/mmc/host/sdhci-of-476gtr.c
> b/drivers/mmc/host/sdhci-of-476gtr.c new file mode 100644
> index 0000000..1310f8c
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-476gtr.c
> @@ -0,0 +1,60 @@
> +/*
> + * drivers/mmc/host/sdhci-of-476gtr.c
> + *
> + * Copyright =A9 2013 Alistair Popple <alistair@popple.id.au> IBM Co=
rporation
> + *
> + * Based on sdhci-of-hlwd.c
> + *
> + * Copyright (C) 2009 The GameCube Linux Team
> + * Copyright (C) 2009 Albert Herranz
> + *
> + * This program is free software; you can redistribute it and/or mod=
ify
> + * it under the terms of the GNU General Public License as published=
by
> + * the Free Software Foundation; either version 2 of the License, or=
(at
> + * your option) any later version.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/mmc/host.h>
> +#include "sdhci-pltfm.h"
> +
> +static const struct sdhci_ops sdhci_476gtr_ops =3D {
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_476gtr_pdata =3D {
> +=09.ops =3D &sdhci_476gtr_ops,
> +};
> +
> +static int sdhci_476gtr_probe(struct platform_device *pdev)
> +{
> +=09return sdhci_pltfm_register(pdev, &sdhci_476gtr_pdata, 0);
> +}
> +
> +static int sdhci_476gtr_remove(struct platform_device *pdev)
> +{
> +=09return sdhci_pltfm_unregister(pdev);
> +}
> +
> +static const struct of_device_id sdhci_476gtr_of_match[] =3D {
> +=09{ .compatible =3D "ibm,476gtr-sdhci" },
> +=09{ }
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_476gtr_of_match);
> +
> +static struct platform_driver sdhci_476gtr_driver =3D {
> +=09.driver =3D {
> +=09=09.name =3D "sdhci-476gtr",
> +=09=09.owner =3D THIS_MODULE,
> +=09=09.of_match_table =3D sdhci_476gtr_of_match,
> +=09=09.pm =3D SDHCI_PLTFM_PMOPS,
> +=09},
> +=09.probe =3D sdhci_476gtr_probe,
> +=09.remove =3D sdhci_476gtr_remove,
> +};
> +
> +module_platform_driver(sdhci_476gtr_driver);
> +
> +MODULE_DESCRIPTION("PPC476GTR SDHCI OF driver");
> +MODULE_AUTHOR("Alistair Popple");
> +MODULE_LICENSE("GPL v2");
^ permalink raw reply
* Re: [PATCH 6/9] powerpc/pci: Use dev_is_pci() to check whether it is pci device
From: Wei Yang @ 2013-12-17 2:02 UTC (permalink / raw)
To: Yijing Wang
Cc: Wei Yang, Hanjun Guo, linux-kernel, Scott Wood, Paul Mackerras,
linux-pci, Bjorn Helgaas, linuxppc-dev
In-Reply-To: <52AEC241.1040507@huawei.com>
On Mon, Dec 16, 2013 at 05:05:05PM +0800, Yijing Wang wrote:
>On 2013/12/16 15:13, Wei Yang wrote:
>> Yijing,
>>
>> This one looks good.
>>
>> While I take a look at the source code, there are around 20 places with
>> similar style. Do you think it would be good to change all these places
>> in one patch?
>
>I sent the other similar changes to related maillist, some of them (David, Greg )has been accepted,
>and other is not. :)
>
>eg.
>http://article.gmane.org/gmane.linux.kernel/1608341/match=dev_is_pci
Ah, I see. Thanks :-)
>
>Thanks!
>Yijing.
>
>>
>> On Thu, Dec 05, 2013 at 08:01:20PM +0800, Yijing Wang wrote:
>>> Use PCI standard marco dev_is_pci() instead of directly compare
>>> pci_bus_type to check whether it is pci device.
>>>
>>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>>> ---
>>> arch/powerpc/sysdev/fsl_pci.c | 2 +-
>>> 1 files changed, 1 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
>>> index 4dfd61d..7066e52 100644
>>> --- a/arch/powerpc/sysdev/fsl_pci.c
>>> +++ b/arch/powerpc/sysdev/fsl_pci.c
>>> @@ -122,7 +122,7 @@ static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
>>> * address width of the SoC such that we can address any internal
>>> * SoC address from across PCI if needed
>>> */
>>> - if ((dev->bus == &pci_bus_type) &&
>>> + if ((dev_is_pci(dev)) &&
>>> dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) {
>>> set_dma_ops(dev, &dma_direct_ops);
>>> set_dma_offset(dev, pci64_dma_offset);
>>> --
>>> 1.7.1
>>>
>>>
>>> _______________________________________________
>>> Linuxppc-dev mailing list
>>> Linuxppc-dev@lists.ozlabs.org
>>> https://lists.ozlabs.org/listinfo/linuxppc-dev
>>
>
>
>--
>Thanks!
>Yijing
--
Richard Yang
Help you, Help me
^ permalink raw reply
* Re: [PATCH 0/4] Minor fixes and improvements for kexec
From: WANG Chao @ 2013-12-17 5:37 UTC (permalink / raw)
To: Geoff Levand
Cc: linux-sh, kexec, Paul Mundt, Paul Mackerras, Eric Biederman,
linuxppc-dev
In-Reply-To: <cover.1386807069.git.geoff@infradead.org>
On 12/12/13 at 12:18am, Geoff Levand wrote:
> Hi Eric,
>
> Here are a few minor fixes and improvements for kexec. Please consider.
>
> -Geoff
>
> The following changes since commit 374b105797c3d4f29c685f3be535c35f5689b30e:
>
> Linux 3.13-rc3 (2013-12-06 09:34:04 -0800)
>
> are available in the git repository at:
>
> git://git.linaro.org/people/geoff.levand/linux-kexec.git for-kexec
>
> for you to fetch changes up to 594a3d26aac66e9668edc81d7bfb4e801575514f:
>
> sh/kexec: Fix kexec build warning (2013-12-11 16:03:27 -0800)
>
> ----------------------------------------------------------------
> Geoff Levand (4):
> kexec: Simplify conditional
> kexec: Add IND_FLAGS macro
> powerpc/kexec: Use global IND_FLAGS macro
> sh/kexec: Fix kexec build warning
For this series (besides 4/4 v2):
Acked-by: WANG Chao <chaowang@redhat.com>
>
> arch/powerpc/kernel/machine_kexec_64.c | 2 --
> arch/sh/kernel/machine_kexec.c | 2 +-
> include/linux/kexec.h | 1 +
> kernel/kexec.c | 17 ++++++++++-------
> 4 files changed, 12 insertions(+), 10 deletions(-)
>
> --
> 1.8.1.2
>
>
> _______________________________________________
> kexec mailing list
> kexec@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kexec
^ permalink raw reply
* Re: [PATCH v2] powerpc 8xx: Loading kernels over 8Mbytes without CONFIG_PIN_TLB
From: leroy christophe @ 2013-12-17 5:54 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <1387234621.10013.408.camel@snotra.buserror.net>
Le 16/12/2013 23:57, Scott Wood a écrit :
> On Wed, 2013-12-11 at 00:36 +0100, leroy christophe wrote:
>> Le 11/12/2013 00:18, Scott Wood a écrit :
>>> There wasn't previously an ifdef specifically around the setting of
>>> SPRN_MD_CTR. That's new. There was an ifdef around the entire block,
>>> which has gone away because you are now trying to map more than 8M
>>> regardless of CONFIG_PIN_TLB, but that has nothing to do with whether
>>> there should be an ifdef around SPRN_MD_CTR.
>>>
>>>
>> Euh, ok, but then we have to fix it in the whole function, not only in
>> this block. Do you think it is worth doing it ?
> Fix what in the whole function? I was asking what harm there would be
> if you just remove all the CONFIG_PIN_TLB ifdefs except around the
> actual RSV4I setting -- do we really care what value goes in MD_CTR for
> the non-pinned case, as long as it's different for each entry?
>
>
MD_CTR is decremented after each entry added.
However, the function populates entry 28, then 29, then 30, then 31. At
the end MD_CTR has then value 30, ready to overide entry 30 then 29 then
28 then 27 .....
So I will remove all the CONFIG_PIN_TLB, but I'll also have to fix the
value set in MD_CTR to start from 31, won't I ?
Do you have any comment/recommendation on my tentative v3 patch where I
have tried to implement based on the use of r7 as you recommended ?
Christophe
^ permalink raw reply
* commit e38c0a1f breaks powerpc boards with uli1575 chip
From: Nikita Yushchenko @ 2013-12-17 7:35 UTC (permalink / raw)
To: Arnd Bergmann, Thierry Reding, Rob Herring, Grant Likely,
devicetree-discuss, linuxppc-dev, Kumar Gala
Cc: Alexey Lugovskoy, linux-kernel, Dmitry Krivoschekov
Hi
While trying to make freescale p2020ds and mpc8572ds boards working with mainline kernel, I faced that commit
e38c0a1f (Handle #address-cells > 2 specially) breaks things with these boards.
Both these boards have uli1575 chip.
Corresponding part in device tree is something like
uli1575@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#size-cells = <2>;
#address-cells = <3>;
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
0x0 0x20000000
0x1000000 0x0 0x0
0x1000000 0x0 0x0
0x0 0x10000>;
isa@1e {
...
I.e. it has #address-cells = <3>
With commit e38c0a1f reverted, devices under uli1575 are registered correctly, e.g. for rtc
OF: ** translation for device /pcie@ffe09000/pcie@0/uli1575@0/isa@1e/rtc@70 **
OF: bus is isa (na=2, ns=1) on /pcie@ffe09000/pcie@0/uli1575@0/isa@1e
OF: translating address: 00000001 00000070
OF: parent bus is default (na=3, ns=2) on /pcie@ffe09000/pcie@0/uli1575@0
OF: walking ranges...
OF: ISA map, cp=0, s=1000, da=70
OF: parent translation for: 01000000 00000000 00000000
OF: with offset: 70
OF: one level translation: 00000000 00000000 00000070
OF: parent bus is pci (na=3, ns=2) on /pcie@ffe09000/pcie@0
OF: walking ranges...
OF: default map, cp=a0000000, s=20000000, da=70
OF: default map, cp=0, s=10000, da=70
OF: parent translation for: 01000000 00000000 00000000
OF: with offset: 70
OF: one level translation: 01000000 00000000 00000070
OF: parent bus is pci (na=3, ns=2) on /pcie@ffe09000
OF: walking ranges...
OF: PCI map, cp=0, s=10000, da=70
OF: parent translation for: 01000000 00000000 00000000
OF: with offset: 70
OF: one level translation: 01000000 00000000 00000070
OF: parent bus is default (na=2, ns=2) on /
OF: walking ranges...
OF: PCI map, cp=0, s=10000, da=70
OF: parent translation for: 00000000 ffc10000
OF: with offset: 70
OF: one level translation: 00000000 ffc10070
OF: reached root node
With commit e38c0a1f in place, address translation fails:
OF: ** translation for device /pcie@ffe09000/pcie@0/uli1575@0/isa@1e/rtc@70 **
OF: bus is isa (na=2, ns=1) on /pcie@ffe09000/pcie@0/uli1575@0/isa@1e
OF: translating address: 00000001 00000070
OF: parent bus is default (na=3, ns=2) on /pcie@ffe09000/pcie@0/uli1575@0
OF: walking ranges...
OF: ISA map, cp=0, s=1000, da=70
OF: parent translation for: 01000000 00000000 00000000
OF: with offset: 70
OF: one level translation: 00000000 00000000 00000070
OF: parent bus is pci (na=3, ns=2) on /pcie@ffe09000/pcie@0
OF: walking ranges...
OF: default map, cp=a0000000, s=20000000, da=70
OF: default map, cp=0, s=10000, da=70
OF: not found !
Either e38c0a1f should be reverted, or uli1575 (and perhaps other similar devices) have to be described in device
trees differently.
Could someone please comment on this?
^ permalink raw reply
* [PATCH v6 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
From: Dongsheng Wang @ 2013-12-17 8:16 UTC (permalink / raw)
To: scottwood, Bharat.Bhushan; +Cc: linuxppc-dev, Wang Dongsheng
From: Wang Dongsheng <dongsheng.wang@freescale.com>
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Add bit definitions for PWRMGTCR0.
arch/powerpc/include/asm/reg.h | 2 ++
arch/powerpc/include/asm/reg_booke.h | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 64264bf..d4160ca 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1053,6 +1053,8 @@
#define PVR_8560 0x80200000
#define PVR_VER_E500V1 0x8020
#define PVR_VER_E500V2 0x8021
+#define PVR_VER_E6500 0x8040
+
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index ed8f836..4a6457e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -170,6 +170,7 @@
#define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
+#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
#define SPRN_SVR 0x3FF /* System Version Register */
/*
@@ -216,6 +217,14 @@
#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
#define CCR1_TCS 0x00000080 /* Timer Clock Select */
+/* Bit definitions for PWRMGTCR0. */
+#define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */
+#define PWRMGTCR0_PW20_ENT_SHIFT 8
+#define PWRMGTCR0_PW20_ENT 0x3F00
+#define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */
+#define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
+#define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
+
/* Bit definitions for the MCSR. */
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
--
1.8.0
^ permalink raw reply related
* [PATCH v6 2/4] powerpc/85xx: add hardware automatically enter altivec idle state
From: Dongsheng Wang @ 2013-12-17 8:17 UTC (permalink / raw)
To: scottwood, Bharat.Bhushan; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1387268222-9703-1-git-send-email-dongsheng.wang@freescale.com>
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Each core's AltiVec unit may be placed into a power savings mode
by turning off power to the unit. Core hardware will automatically
power down the AltiVec unit after no AltiVec instructions have
executed in N cycles. The AltiVec power-control is triggered by hardware.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Assembly code instead of C code.
*v2:
Remove:
delete setup_idle_hw_governor function.
delete "Fix erratum" for rev1.
Move:
move setup_* into __setup/restore_cpu_e6500.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index bfb18c7..4789056 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,11 +53,31 @@ _GLOBAL(__e500_dcache_setup)
isync
blr
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
+ * value for AV_WAIT_IDLE_BIT.
+ */
+#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_altivec_idle)
+ mfspr r3, SPRN_PWRMGTCR0
+
+ /* Enable Altivec Idle */
+ oris r3, r3, PWRMGTCR0_AV_IDLE_PD_EN@h
+ li r11, AV_WAIT_IDLE_BIT
+
+ /* Set Automatic AltiVec Idle Count */
+ rlwimi r3, r11, PWRMGTCR0_AV_IDLE_CNT_SHIFT, PWRMGTCR0_AV_IDLE_CNT
+
+ mtspr SPRN_PWRMGTCR0, r3
+
+ blr
+
_GLOBAL(__setup_cpu_e6500)
mflr r6
#ifdef CONFIG_PPC64
bl .setup_altivec_ivors
#endif
+ bl setup_altivec_idle
bl __setup_cpu_e5500
mtlr r6
blr
@@ -119,6 +139,7 @@ _GLOBAL(__setup_cpu_e5500)
_GLOBAL(__restore_cpu_e6500)
mflr r5
bl .setup_altivec_ivors
+ bl .setup_altivec_idle
bl __restore_cpu_e5500
mtlr r5
blr
--
1.8.0
^ permalink raw reply related
* [PATCH v6 3/4] powerpc/85xx: add hardware automatically enter pw20 state
From: Dongsheng Wang @ 2013-12-17 8:17 UTC (permalink / raw)
To: scottwood, Bharat.Bhushan; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1387268222-9703-1-git-send-email-dongsheng.wang@freescale.com>
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Using hardware features make core automatically enter PW20 state.
Set a TB count to hardware, the effective count begins when PW10
is entered. When the effective period has expired, the core will
proceed from PW10 to PW20 if no exit conditions have occurred during
the period.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v3:
Assembly code instead of C code.
*v2:
Remove:
delete setup_idle_hw_governor function.
delete "Fix erratum" for rev1.
Move:
move setup_* into __setup/restore_cpu_e6500.
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 4789056..49e738e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -55,6 +55,25 @@ _GLOBAL(__e500_dcache_setup)
/*
* FIXME - we haven't yet done testing to determine a reasonable default
+ * value for PW20_WAIT_IDLE_BIT.
+ */
+#define PW20_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
+_GLOBAL(setup_pw20_idle)
+ mfspr r3, SPRN_PWRMGTCR0
+
+ /* Set PW20_WAIT bit, enable pw20 state*/
+ ori r3, r3, PWRMGTCR0_PW20_WAIT
+ li r11, PW20_WAIT_IDLE_BIT
+
+ /* Set Automatic PW20 Core Idle Count */
+ rlwimi r3, r11, PWRMGTCR0_PW20_ENT_SHIFT, PWRMGTCR0_PW20_ENT
+
+ mtspr SPRN_PWRMGTCR0, r3
+
+ blr
+
+/*
+ * FIXME - we haven't yet done testing to determine a reasonable default
* value for AV_WAIT_IDLE_BIT.
*/
#define AV_WAIT_IDLE_BIT 50 /* 1ms, TB frequency is 41.66MHZ */
@@ -77,6 +96,7 @@ _GLOBAL(__setup_cpu_e6500)
#ifdef CONFIG_PPC64
bl .setup_altivec_ivors
#endif
+ bl setup_pw20_idle
bl setup_altivec_idle
bl __setup_cpu_e5500
mtlr r6
@@ -139,6 +159,7 @@ _GLOBAL(__setup_cpu_e5500)
_GLOBAL(__restore_cpu_e6500)
mflr r5
bl .setup_altivec_ivors
+ bl .setup_pw20_idle
bl .setup_altivec_idle
bl __restore_cpu_e5500
mtlr r5
--
1.8.0
^ permalink raw reply related
* [PATCH v6 4/4] powerpc/85xx: add sysfs for pw20 state and altivec idle
From: Dongsheng Wang @ 2013-12-17 8:17 UTC (permalink / raw)
To: scottwood, Bharat.Bhushan; +Cc: linuxppc-dev, Wang Dongsheng
In-Reply-To: <1387268222-9703-1-git-send-email-dongsheng.wang@freescale.com>
From: Wang Dongsheng <dongsheng.wang@freescale.com>
Add a sys interface to enable/diable pw20 state or altivec idle, and
control the wait entry time.
Enable/Disable interface:
0, disable. 1, enable.
/sys/devices/system/cpu/cpuX/pw20_state
/sys/devices/system/cpu/cpuX/altivec_idle
Set wait time interface:(Nanosecond)
/sys/devices/system/cpu/cpuX/pw20_wait_time
/sys/devices/system/cpu/cpuX/altivec_idle_wait_time
Example: Base on TBfreq is 41MHZ.
1~48(ns): TB[63]
49~97(ns): TB[62]
98~195(ns): TB[61]
196~390(ns): TB[60]
391~780(ns): TB[59]
781~1560(ns): TB[58]
...
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
---
*v6:
Change show_pw20_wait_time/show_altivec_idle_wait_time functions implementation.
*v5:
Change get_idle_ticks_bit function implementation.
*v4:
Move code from 85xx/common.c to kernel/sysfs.c.
Remove has_pw20_altivec_idle function.
Change wait "entry_bit" to wait time.
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index b4e6676..6c92e23 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -86,6 +86,304 @@ __setup("smt-snooze-delay=", setup_smt_snooze_delay);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT 63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns)
+{
+ u64 cycle;
+
+ if (ns >= 10000)
+ cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
+ else
+ cycle = div_u64(ns * tb_ticks_per_usec, 1000);
+
+ if (!cycle)
+ return 0;
+
+ return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val)
+{
+ u32 *value = val;
+
+ *value = mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+ value &= PWRMGTCR0_PW20_WAIT;
+
+ return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_pw20_state(void *val)
+{
+ u32 *value = val;
+ u32 pw20_state;
+
+ pw20_state = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
+ pw20_state |= PWRMGTCR0_PW20_WAIT;
+ else
+ pw20_state &= ~PWRMGTCR0_PW20_WAIT;
+
+ mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ if (kstrtou32(buf, 0, &value))
+ return -EINVAL;
+
+ if (value > 1)
+ return -EINVAL;
+
+ smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
+
+ return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ u64 tb_cycle = 1;
+ u64 time;
+
+ unsigned int cpu = dev->id;
+
+ if (!pw20_wt) {
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+ value = (value & PWRMGTCR0_PW20_ENT) >>
+ PWRMGTCR0_PW20_ENT_SHIFT;
+
+ tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
+ /* convert ms to ns */
+ if (tb_ticks_per_usec > 1000) {
+ time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
+ } else {
+ u32 rem_us;
+
+ time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
+ &rem_us);
+ time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
+ }
+ } else {
+ time = pw20_wt;
+ }
+
+ return sprintf(buf, "%llu\n", time > 0 ? time : 0);
+}
+
+static void set_pw20_wait_entry_bit(void *val)
+{
+ u32 *value = val;
+ u32 pw20_idle;
+
+ pw20_idle = mfspr(SPRN_PWRMGTCR0);
+
+ /* Set Automatic PW20 Core Idle Count */
+ /* clear count */
+ pw20_idle &= ~PWRMGTCR0_PW20_ENT;
+
+ /* set count */
+ pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
+
+ mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 entry_bit;
+ u64 value;
+
+ unsigned int cpu = dev->id;
+
+ if (kstrtou64(buf, 0, &value))
+ return -EINVAL;
+
+ if (!value)
+ return -EINVAL;
+
+ entry_bit = get_idle_ticks_bit(value);
+ if (entry_bit > MAX_BIT)
+ return -EINVAL;
+
+ pw20_wt = value;
+
+ smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+ &entry_bit, 1);
+
+ return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+ value &= PWRMGTCR0_AV_IDLE_PD_EN;
+
+ return sprintf(buf, "%u\n", value ? 1 : 0);
+}
+
+static void do_store_altivec_idle(void *val)
+{
+ u32 *value = val;
+ u32 altivec_idle;
+
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+ if (*value)
+ altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
+ else
+ altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
+
+ mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 value;
+ unsigned int cpu = dev->id;
+
+ if (kstrtou32(buf, 0, &value))
+ return -EINVAL;
+
+ if (value > 1)
+ return -EINVAL;
+
+ smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
+
+ return count;
+}
+
+static ssize_t show_altivec_idle_wait_time(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 value;
+ u64 tb_cycle = 1;
+ u64 time;
+
+ unsigned int cpu = dev->id;
+
+ if (!altivec_idle_wt) {
+ smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+ value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
+ PWRMGTCR0_AV_IDLE_CNT_SHIFT;
+
+ tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
+ /* convert ms to ns */
+ if (tb_ticks_per_usec > 1000) {
+ time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
+ } else {
+ u32 rem_us;
+
+ time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
+ &rem_us);
+ time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
+ }
+ } else {
+ time = altivec_idle_wt;
+ }
+
+ return sprintf(buf, "%llu\n", time > 0 ? time : 0);
+}
+
+static void set_altivec_idle_wait_entry_bit(void *val)
+{
+ u32 *value = val;
+ u32 altivec_idle;
+
+ altivec_idle = mfspr(SPRN_PWRMGTCR0);
+
+ /* Set Automatic AltiVec Idle Count */
+ /* clear count */
+ altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
+
+ /* set count */
+ altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
+
+ mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle_wait_time(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 entry_bit;
+ u64 value;
+
+ unsigned int cpu = dev->id;
+
+ if (kstrtou64(buf, 0, &value))
+ return -EINVAL;
+
+ if (!value)
+ return -EINVAL;
+
+ entry_bit = get_idle_ticks_bit(value);
+ if (entry_bit > MAX_BIT)
+ return -EINVAL;
+
+ altivec_idle_wt = value;
+
+ smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
+ &entry_bit, 1);
+
+ return count;
+}
+
+/*
+ * Enable/Disable interface:
+ * 0, disable. 1, enable.
+ */
+static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
+static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
+
+/*
+ * Set wait time interface:(Nanosecond)
+ * Example: Base on TBfreq is 41MHZ.
+ * 1~48(ns): TB[63]
+ * 49~97(ns): TB[62]
+ * 98~195(ns): TB[61]
+ * 196~390(ns): TB[60]
+ * 391~780(ns): TB[59]
+ * 781~1560(ns): TB[58]
+ * ...
+ */
+static DEVICE_ATTR(pw20_wait_time, 0600,
+ show_pw20_wait_time,
+ store_pw20_wait_time);
+static DEVICE_ATTR(altivec_idle_wait_time, 0600,
+ show_altivec_idle_wait_time,
+ store_altivec_idle_wait_time);
+#endif
+
/*
* Enabling PMCs will slow partition context switch times so we only do
* it the first time we write to the PMCs.
@@ -421,6 +719,15 @@ static void register_cpu_online(unsigned int cpu)
device_create_file(s, &dev_attr_pir);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+ if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+ device_create_file(s, &dev_attr_pw20_state);
+ device_create_file(s, &dev_attr_pw20_wait_time);
+
+ device_create_file(s, &dev_attr_altivec_idle);
+ device_create_file(s, &dev_attr_altivec_idle_wait_time);
+ }
+#endif
cacheinfo_cpu_online(cpu);
}
@@ -493,6 +800,15 @@ static void unregister_cpu_online(unsigned int cpu)
device_remove_file(s, &dev_attr_pir);
#endif /* CONFIG_PPC64 */
+#ifdef CONFIG_FSL_SOC
+ if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
+ device_remove_file(s, &dev_attr_pw20_state);
+ device_remove_file(s, &dev_attr_pw20_wait_time);
+
+ device_remove_file(s, &dev_attr_altivec_idle);
+ device_remove_file(s, &dev_attr_altivec_idle_wait_time);
+ }
+#endif
cacheinfo_cpu_offline(cpu);
}
--
1.8.5
^ permalink raw reply related
* Re: [PATCH] DTS: DMA: Fix DMA3 interrupts
From: Li Yang @ 2013-12-17 8:48 UTC (permalink / raw)
To: Scott Wood; +Cc: Hongbo Zhang, linuxppc-dev, lkml
In-Reply-To: <1386700403.10013.109.camel@snotra.buserror.net>
On Wed, Dec 11, 2013 at 2:33 AM, Scott Wood <scottwood@freescale.com> wrote:
> On Tue, 2013-12-10 at 18:33 +0800, Hongbo Zhang wrote:
>> Scott,
>> This issue is due to the non-continuous MPIC register, I think there is
>> two ways to fix it.
>>
>> The first one is as what we are discussing, in fact the Bman/Qman DT
>> author had introduced this way, and I had to follow it, it is a trick,
>> adding 208 is a bit ugly I think, and even difficult to explain it to
>> customers etc, but this way changes less codes.
>>
>> The second one is editing MPIC related codes without adding 208 to high
>> interrupts. The point of translate interrupt number to MPIC register
>> address is a so called 'isu' mechanism, we can do like the following
>> example codes, then the tricky adding 208 isn't needed any more.
>>
>> Which one do you prefer?
>> In fact I myself prefer the second, if the idea is acceptable, I will
>> send a patch instead of this one. (and also alone with the internal
>> patch decreasing 208 for the Bman/Qman)
>>
>> void __init corenet_ds_pic_init(void)
>> {
>> ......
>>
>> mpic = mpic_alloc(NULL, 0, flags, 0, 512, "OpenPIC");
>> BUG_ON(mpic == NULL);
>>
>> // Add this start
>> for (i = 0; i < 17; i++) {
>> if (i < 11)
>> addr_off = 0x10000 + 0x20 * 16 * i;
>> else
>> addr_off = 0x13000 + 0x20 * 16 * (i - 11); /* scape the
>> address not for interrupts */
>> mpic_assign_isu(mpic, i, mpic->paddr + addr_off);
>> }
>> // Add this end
>>
>> mpic_init(mpic);
>> }
>
> NACK
>
> We already have a binding that states that the interrupt number is based
> on the register offset, rather than whatever arbitrary numbers hardware
> documenters decide to use next week.
>
> While I'm not terribly happy with the usability of this, especially now
> that it's not a simple "add 16", redefining the existing binding is not
> OK (and in any case the code above seems obfuscatory). If we decide to
> do something other than continue with register offset divided by 32,
> then we need to define a new interrupt type (similar to current defined
> types of error interrupt, timer, and IPI) for the new numberspace -- and
> it should be handled when decoding that type of interrupt specifier,
> rather than with the isu mechanism.
I had to say that the current binding is terribly confusing. I know a
lot of people who were confused while looking into the device tree and
I had to help them out now and then. I even got confused for some
time at the very beginning. :( If we want to keep the current
binding, a big warning message is well deserved at the very beginning
of the binding document to clarify that the interrupt number used in
device tree has nothing to do with the interrupt number mentioned in
the silicon reference manuals. I think we should even mention the
"add 16" magic rule also to make it more intuitive.
Adding a new interrupt type for external interrupts is good to make
the interrupt number consistent with the Reference Manuals. But doing
that requires changing all the device trees that used the previous
binding, and we need a mechanism of judging which binding a device
tree is complying to.
Hongbo's proposal is not a complete fix for the readability issue.
But it makes the "add 16" magic rule continue to work, instead of
making it even worse by introducing the "+208" interrupts. The DMA3
patch is the first time that we add the "+208" interrupts in the
device trees of mainline kernel. It is a good time now to prevent us
making the readability even worse while not breaking things out there.
ISU is a standard mechanism in MPIC to deal with sparse configuration
register space, and IMO a good fit for this situation.
Regards,
Leo
^ permalink raw reply
* Chip Select register with 8bit bus size...
From: neorf3k @ 2013-12-17 8:58 UTC (permalink / raw)
To: linuxppc-dev
We have a problem to communicate with a register, CS4, at at 0x10020000. =
In U-boot that reg has the value 0x45fab3c1, but when we try to access =
it we get: 0x10101010 and we are not able to write too.
With CS3 everything seems ok, we can read and write. CS3 is at: =
0x10000000.
The main/only differences between cs3 and cs4 are:
Chip Select: Lp_cs3
Bus size: 32 bit
Bus control: 2 wait state R/W ACK disabled
Allocated size 32Kbyte
Chip Select: Lp_cs4
Bus size: 8 bit
Bus control: 2 wait state R/W ACK disabled
Allocated size: 4 KByte
In userspace we use:
/*=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=
=97=97=97=97=97=97=97=97*/
//code from memedit.c
int fd;
fd =3D open("/dev/mem", O_SYNC | O_RDWR);
mem =3D mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, fd, offset =
& (~4095));
printf("/dev/mem[0x%08x] =3D 0x%08x", offset, *(unsigned =
int*)&mem[offset & 4095]);
//to write
*((unsigned int *)&mem[offset & 4095]) =3D input;
/*=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=
=97=97=97=97=97=97=97=97*/
In our kernel module:
/*=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=
=97=97=97=97=97=97=97=97*/
#define CS4_START 0x10020000U
#define CS4_STOP 0x10040000U
#define CS4_SIZE 0x00020000U
#define CS3_START 0x10000000U
#define CS3_STOP 0x10020000U
#define CS3_SIZE 0x00020000U
void __iomem *cs3_ioaddr =3D ioremap ((volatile unsigned =
long)(CS3_START), CS3_SIZE);
printk("We read value at CS3: %x \n\n\n",in_be32(cs3_ioaddr+0x0018));
out_be32(cs3_ioaddr+0x0018,0x00000001);
printk("We read written value: %x \n\n\n",in_be32(cs3_ioaddr+0x0018));
/*=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=97=
=97=97=97=97=97=97=97=97*/
Platform is based on mpc5200b CPU and fpga is a Xilinx Virtex4.
Kernel we use: 2.6.33
Thanks again in advance=85
Lorenzo=
^ permalink raw reply
* [PATCH v2 05/10] powerpc: select ARCH_MIGHT_HAVE_PC_SERIO
From: Mark Salter @ 2013-12-17 15:48 UTC (permalink / raw)
To: linux-kernel; +Cc: linuxppc-dev, Paul Mackerras, Mark Salter
In-Reply-To: <1387295333-24684-1-git-send-email-msalter@redhat.com>
Architectures which might use an i8042 for serial IO to keyboard,
mouse, etc should select ARCH_MIGHT_HAVE_PC_SERIO.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: linuxppc-dev@lists.ozlabs.org
---
arch/powerpc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index b44b52c..fb75485 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -86,6 +86,7 @@ config PPC
bool
default y
select ARCH_MIGHT_HAVE_PC_PARPORT
+ select ARCH_MIGHT_HAVE_PC_SERIO
select BINFMT_ELF
select OF
select OF_EARLY_FLATTREE
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 00/10] Kconfig: cleanup SERIO_I8042 dependencies
From: Mark Salter @ 2013-12-17 15:48 UTC (permalink / raw)
To: linux-kernel
Cc: Fenghua Yu, Tony Luck, Russell King, linux-mips, linux-sh,
Dmitry Torokhov, x86, Ingo Molnar, Paul Mundt, Paul Mackerras,
Mark Salter, linux-alpha, sparclinux, linux-ia64, Thomas Gleixner,
Guan Xuetao, linuxppc-dev, David S. Miller, linux-arm-kernel,
Richard Henderson
This patch series removes the messy dependencies from SERIO_I8042
by having it depend on one variable (ARCH_MAY_HAVE_PC_SERIO) and
having architectures which need it select that variable in
arch/*/Kconfig.
New architectures are unlikely to need SERIO_I8042, so this avoids
having an ever growing list of architectures to exclude. If an
architecture without i8042 support isn't excluded through the
dependency list for SERIO_I8042 or through explicit disabling in
a config, it will likely panic on boot with something similar to
this (from arm64):
[ 27.426181] [<ffffffc000403b1c>] i8042_flush+0x88/0x10c
[ 27.426251] [<ffffffc00084cc2c>] i8042_init+0x58/0xe8
[ 27.426320] [<ffffffc000080bec>] do_one_initcall+0xc4/0x14c
[ 27.426404] [<ffffffc000820970>] kernel_init_freeable+0x1a4/0x244
[ 27.426480] [<ffffffc0005a894c>] kernel_init+0x18/0x148
[ 27.426561] Code: d2800c82 f2bf7c02 f2dff7e2 f2ffffe2 (39400042)
[ 27.426789] ---[ end trace ac076843cf0f383e ]---
[ 27.426875] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
This is v2 of the patch series. Changes from version 1:
o Added acks. arm, ia64, and sh are only ones without acks.
o Moved select of ARCH_MIGHT_HAVE_PC_SERIO to board-specific
Kconfigs for arm and sh.
A tree with these patches is at:
git://github.com/mosalter/linux.git (serio-i8042-v2 branch)
Mark Salter (10):
alpha: select ARCH_MIGHT_HAVE_PC_SERIO
arm: select ARCH_MIGHT_HAVE_PC_SERIO
ia64: select ARCH_MIGHT_HAVE_PC_SERIO
mips: select ARCH_MIGHT_HAVE_PC_SERIO
powerpc: select ARCH_MIGHT_HAVE_PC_SERIO
sh: select ARCH_MIGHT_HAVE_PC_SERIO for SH_CAYMAN
sparc: select ARCH_MIGHT_HAVE_PC_SERIO
unicore32: select ARCH_MIGHT_HAVE_PC_SERIO
x86: select ARCH_MIGHT_HAVE_PC_SERIO
Kconfig: cleanup SERIO_I8042 dependencies
arch/alpha/Kconfig | 1 +
arch/arm/mach-footbridge/Kconfig | 1 +
arch/ia64/Kconfig | 1 +
arch/mips/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/sh/boards/Kconfig | 1 +
arch/sparc/Kconfig | 1 +
arch/unicore32/Kconfig | 1 +
arch/x86/Kconfig | 1 +
drivers/input/serio/Kconfig | 11 ++++++++---
10 files changed, 17 insertions(+), 3 deletions(-)
--
1.8.3.1
^ permalink raw reply
* [PATCH v2 10/10] Kconfig: cleanup SERIO_I8042 dependencies
From: Mark Salter @ 2013-12-17 15:48 UTC (permalink / raw)
To: linux-kernel
Cc: Fenghua Yu, Tony Luck, Russell King, linux-mips, linux-sh,
Dmitry Torokhov, x86, Ingo Molnar, Paul Mundt, Paul Mackerras,
Mark Salter, linux-alpha, sparclinux, linux-ia64, Thomas Gleixner,
Guan Xuetao, linuxppc-dev, David S. Miller, linux-arm-kernel,
Richard Henderson
In-Reply-To: <1387295333-24684-1-git-send-email-msalter@redhat.com>
Remove messy dependencies from SERIO_I8042 by having it depend on one
Kconfig symbol (ARCH_MIGHT_HAVE_PC_SERIO) and having architectures
which need it select ARCH_MIGHT_HAVE_PC_SERIO in arch/*/Kconfig.
New architectures are unlikely to need SERIO_I8042, so this avoids
having an ever growing list of architectures to exclude.
Signed-off-by: Mark Salter <msalter@redhat.com>
Acked-by: "H. Peter Anvin" <hpa@zytor.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Dmitry Torokhov <dmitry.torokhov@gmail.com>
CC: Richard Henderson <rth@twiddle.net>
CC: linux-alpha@vger.kernel.org
CC: Russell King <linux@arm.linux.org.uk>
CC: linux-arm-kernel@lists.infradead.org
CC: Tony Luck <tony.luck@intel.com>
CC: Fenghua Yu <fenghua.yu@intel.com>
CC: linux-ia64@vger.kernel.org
CC: linux-mips@linux-mips.org
CC: Paul Mackerras <paulus@samba.org>
CC: linuxppc-dev@lists.ozlabs.org
CC: Paul Mundt <lethal@linux-sh.org>
CC: linux-sh@vger.kernel.org
CC: "David S. Miller" <davem@davemloft.net>
CC: sparclinux@vger.kernel.org
CC: Guan Xuetao <gxt@mprc.pku.edu.cn>
CC: Ingo Molnar <mingo@redhat.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: x86@kernel.org
---
drivers/input/serio/Kconfig | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig
index 8541f94..1f5cec2 100644
--- a/drivers/input/serio/Kconfig
+++ b/drivers/input/serio/Kconfig
@@ -16,14 +16,19 @@ config SERIO
To compile this driver as a module, choose M here: the
module will be called serio.
+config ARCH_MIGHT_HAVE_PC_SERIO
+ bool
+ help
+ Select this config option from the architecture Kconfig if
+ the architecture might use a PC serio device (i8042) to
+ communicate with keyboard, mouse, etc.
+
if SERIO
config SERIO_I8042
tristate "i8042 PC Keyboard controller"
default y
- depends on !PARISC && (!ARM || FOOTBRIDGE_HOST) && \
- (!SUPERH || SH_CAYMAN) && !M68K && !BLACKFIN && !S390 && \
- !ARC
+ depends on ARCH_MIGHT_HAVE_PC_SERIO
help
i8042 is the chip over which the standard AT keyboard and PS/2
mouse are connected to the computer. If you use these devices,
--
1.8.3.1
^ permalink raw reply related
* [PATCH] of/irq: Fix device_node refcount in of_irq_parse_raw()
From: Cédric Le Goater @ 2013-12-17 17:32 UTC (permalink / raw)
To: grant.likely; +Cc: Cédric Le Goater, linuxppc-dev, devicetree
Commit 2361613206e6, "of/irq: Refactor interrupt-map parsing" changed
the refcount on the device_node causing an error in of_node_put():
ERROR: Bad of_node_put() on /pci@800000020000000
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.13.0-rc3-dirty #2
Call Trace:
[c00000003e403500] [c0000000000144fc] .show_stack+0x7c/0x1f0 (unreliable)
[c00000003e4035d0] [c00000000070f250] .dump_stack+0x88/0xb4
[c00000003e403650] [c0000000005e8768] .of_node_release+0xd8/0xf0
[c00000003e4036e0] [c0000000005eeafc] .of_irq_parse_one+0x10c/0x280
[c00000003e4037a0] [c0000000005efd4c] .of_irq_parse_pci+0x3c/0x1d0
[c00000003e403840] [c000000000038240] .pcibios_setup_device+0xa0/0x2e0
[c00000003e403910] [c0000000000398f0] .pcibios_setup_bus_devices+0x60/0xd0
[c00000003e403990] [c00000000003b3a4] .__of_scan_bus+0x1a4/0x2b0
[c00000003e403a80] [c00000000003a62c] .pcibios_scan_phb+0x30c/0x410
[c00000003e403b60] [c0000000009fe430] .pcibios_init+0x7c/0xd4
This patch adjusts the refcount in the walk of the interrupt tree.
When a match is found, there is no need to increase the refcount
on 'out_irq->np' as 'newpar' is already holding a ref. The refcount
balance between 'ipar' and 'newpar' is maintained in the skiplevel:
goto label.
This patch also removes the usage of the device_node variable 'old'
which seems useless after the latest changes.
Signed-off-by: Cédric Le Goater <clg@fr.ibm.com>
---
This patch was tested on powerpc, pseries and powernv. This is a
new area for me so I might have missed a path. Please take a look.
We could now introduce an helper routine to look for #address-cells in
of_irq_parse_raw(). This can be the subject of another patch.
Thanks,
C.
drivers/of/irq.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 786b0b47fae4..27212402c532 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -165,7 +165,6 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
if (of_get_property(ipar, "interrupt-controller", NULL) !=
NULL) {
pr_debug(" -> got it !\n");
- of_node_put(old);
return 0;
}
@@ -250,8 +249,7 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
* Successfully parsed an interrrupt-map translation; copy new
* interrupt specifier into the out_irq structure
*/
- of_node_put(out_irq->np);
- out_irq->np = of_node_get(newpar);
+ out_irq->np = newpar;
match_array = imap - newaddrsize - newintsize;
for (i = 0; i < newintsize; i++)
@@ -268,7 +266,6 @@ int of_irq_parse_raw(const __be32 *addr, struct of_phandle_args *out_irq)
}
fail:
of_node_put(ipar);
- of_node_put(out_irq->np);
of_node_put(newpar);
return -EINVAL;
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH] DTS: DMA: Fix DMA3 interrupts
From: Scott Wood @ 2013-12-17 19:45 UTC (permalink / raw)
To: Li Yang; +Cc: Hongbo Zhang, linuxppc-dev, lkml
In-Reply-To: <CADRPPNRy9SLauRPy0Ucm-xffuAhA7bMsA+9X4a=8XNRaJVMH5A@mail.gmail.com>
On Tue, 2013-12-17 at 16:48 +0800, Li Yang wrote:
> On Wed, Dec 11, 2013 at 2:33 AM, Scott Wood <scottwood@freescale.com> wrote:
> > On Tue, 2013-12-10 at 18:33 +0800, Hongbo Zhang wrote:
> >> Scott,
> >> This issue is due to the non-continuous MPIC register, I think there is
> >> two ways to fix it.
> >>
> >> The first one is as what we are discussing, in fact the Bman/Qman DT
> >> author had introduced this way, and I had to follow it, it is a trick,
> >> adding 208 is a bit ugly I think, and even difficult to explain it to
> >> customers etc, but this way changes less codes.
> >>
> >> The second one is editing MPIC related codes without adding 208 to high
> >> interrupts. The point of translate interrupt number to MPIC register
> >> address is a so called 'isu' mechanism, we can do like the following
> >> example codes, then the tricky adding 208 isn't needed any more.
> >>
> >> Which one do you prefer?
> >> In fact I myself prefer the second, if the idea is acceptable, I will
> >> send a patch instead of this one. (and also alone with the internal
> >> patch decreasing 208 for the Bman/Qman)
> >>
> >> void __init corenet_ds_pic_init(void)
> >> {
> >> ......
> >>
> >> mpic = mpic_alloc(NULL, 0, flags, 0, 512, "OpenPIC");
> >> BUG_ON(mpic == NULL);
> >>
> >> // Add this start
> >> for (i = 0; i < 17; i++) {
> >> if (i < 11)
> >> addr_off = 0x10000 + 0x20 * 16 * i;
> >> else
> >> addr_off = 0x13000 + 0x20 * 16 * (i - 11); /* scape the
> >> address not for interrupts */
> >> mpic_assign_isu(mpic, i, mpic->paddr + addr_off);
> >> }
> >> // Add this end
> >>
> >> mpic_init(mpic);
> >> }
> >
> > NACK
> >
> > We already have a binding that states that the interrupt number is based
> > on the register offset, rather than whatever arbitrary numbers hardware
> > documenters decide to use next week.
> >
> > While I'm not terribly happy with the usability of this, especially now
> > that it's not a simple "add 16", redefining the existing binding is not
> > OK (and in any case the code above seems obfuscatory). If we decide to
> > do something other than continue with register offset divided by 32,
> > then we need to define a new interrupt type (similar to current defined
> > types of error interrupt, timer, and IPI) for the new numberspace -- and
> > it should be handled when decoding that type of interrupt specifier,
> > rather than with the isu mechanism.
>
> I had to say that the current binding is terribly confusing. I know a
> lot of people who were confused while looking into the device tree and
> I had to help them out now and then. I even got confused for some
> time at the very beginning. :( If we want to keep the current
> binding, a big warning message is well deserved at the very beginning
> of the binding document to clarify that the interrupt number used in
> device tree has nothing to do with the interrupt number mentioned in
> the silicon reference manuals. I think we should even mention the
> "add 16" magic rule also to make it more intuitive.
I suggested some explanatory text in another thread.
> Adding a new interrupt type for external interrupts is good to make
> the interrupt number consistent with the Reference Manuals. But doing
> that requires changing all the device trees that used the previous
> binding,
We may want to change them all for clarity, but there's no compatibility
issue. Old device trees must continue to be supported.
> and we need a mechanism of judging which binding a device
> tree is complying to.
If it uses the new interrupt type number, then it's the new binding.
Otherwise, it's the old. The binding would only be added to, not
changed.
I'm not convinced it's worth adding at this point, though -- let's add
some helpful text to the binding and see how much that helps.
-Scott
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