* [PATCH 0/3] ppc:Set runlatch bits correctly for offline threads and vcpus
From: Preeti U Murthy @ 2014-04-11 10:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: paulus, linux-kernel, srivatsa.bhat
The runlatch bits with their value indicated by CTRL_RUNLATCH are set and
cleared in the SPRN_CTRL registers to indicate a busy and idle cpu
respectively. This is currently being done in the cpuidle path of the host.
But needs to be taken care of in hotplug and kvm scenarios. This patchset
is aimed at ensuring that the runlatch bits are consisten with the
utilization of a CPU under all circumstances.
---
Preeti U Murthy (3):
ppc/powernv: Set the runlatch bits correctly for offline cpus
ppc/kvm: Set the runlatch bit of a CPU just before starting guest
ppc/kvm: Clear the runlatch bit of a vcpu before napping
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 18 +++++++++++++++++-
arch/powerpc/platforms/powernv/smp.c | 3 +++
2 files changed, 20 insertions(+), 1 deletion(-)
--
^ permalink raw reply
* Re: [PATCH v3 6/8] DMA: Freescale: change descriptor release process for supporting async_tx
From: Hongbo Zhang @ 2014-04-11 8:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <5347A12F.8040006@freescale.com>
On 04/11/2014 04:00 PM, Hongbo Zhang wrote:
>
> On 04/10/2014 07:56 PM, Andy Shevchenko wrote:
>> On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
>>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>>
>>> Fix the potential risk when enable config NET_DMA and ASYNC_TX.
>>> Async_tx is
>>> lack of support in current release process of dma descriptor, all
>>> descriptors
>>> will be released whatever is acked or no-acked by async_tx, so there
>>> is a
>>> potential race condition when dma engine is uesd by others clients
>>> (e.g. when
>>> enable NET_DMA to offload TCP).
>>>
>>> In our case, a race condition which is raised when use both of
>>> talitos and
>>> dmaengine to offload xor is because napi scheduler will sync all
>>> pending
>>> requests in dma channels, it affects the process of raid operations
>>> due to
>>> ack_tx is not checked in fsl dma. The no-acked descriptor is freed
>>> which is
>>> submitted just now, as a dependent tx, this freed descriptor trigger
>>> BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit().
>>>
>>> TASK = ee1a94a0[1390] 'md0_raid5' THREAD: ecf40000 CPU: 0
>>> GPR00: 00000001 ecf41ca0 ee44/921a94a0 0000003f 00000001 c00593e4
>>> 00000000 00000001
>>> GPR08: 00000000 a7a7a7a7 00000001 045/920000002 42028042 100a38d4
>>> ed576d98 00000000
>>> GPR16: ed5a11b0 00000000 2b162000 00000200 046/920000000 2d555000
>>> ed3015e8 c15a7aa0
>>> GPR24: 00000000 c155fc40 00000000 ecb63220 ecf41d28 e47/92f640bb0
>>> ef640c30 ecf41ca0
>>> NIP [c02b048c] async_tx_submit+0x6c/0x2b4
>>> LR [c02b068c] async_tx_submit+0x26c/0x2b4
>>> Call Trace:
>>> [ecf41ca0] [c02b068c] async_tx_submit+0x26c/0x2b448/92 (unreliable)
>>> [ecf41cd0] [c02b0a4c] async_memcpy+0x240/0x25c
>>> [ecf41d20] [c0421064] async_copy_data+0xa0/0x17c
>>> [ecf41d70] [c0421cf4] __raid_run_ops+0x874/0xe10
>>> [ecf41df0] [c0426ee4] handle_stripe+0x820/0x25e8
>>> [ecf41e90] [c0429080] raid5d+0x3d4/0x5b4
>>> [ecf41f40] [c04329b8] md_thread+0x138/0x16c
>>> [ecf41f90] [c008277c] kthread+0x8c/0x90
>>> [ecf41ff0] [c0011630] kernel_thread+0x4c/0x68
>>>
>>> Another modification in this patch is the change of completed
>>> descriptors,
>>> there is a potential risk which caused by exception interrupt, all
>>> descriptors
>>> in ld_running list are seemed completed when an interrupt raised, it
>>> works fine
>>> under normal condition, but if there is an exception occured, it
>>> cannot work as
>>> our excepted. Hardware should not be depend on s/w list, the right
>>> way is to
>>> read current descriptor address register to find the last completed
>>> descriptor.
>>> If an interrupt is raised by an error, all descriptors in ld_running
>>> should not
>>> be seemed finished, or these unfinished descriptors in ld_running
>>> will be
>>> released wrongly.
>>>
>>> A simple way to reproduce:
>>> Enable dmatest first, then insert some bad descriptors which can
>>> trigger
>>> Programming Error interrupts before the good descriptors. Last, the
>>> good
>>> descriptors will be freed before they are processsed because of the
>>> exception
>>> intrerrupt.
>>>
>>> Note: the bad descriptors are only for simulating an exception
>>> interrupt. This
>>> case can illustrate the potential risk in current fsl-dma very well.
>>>
>>> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
>>> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
>>> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
>>> ---
>>> drivers/dma/fsldma.c | 195
>>> ++++++++++++++++++++++++++++++++++++--------------
>>> drivers/dma/fsldma.h | 17 ++++-
>>> 2 files changed, 158 insertions(+), 54 deletions(-)
>>>
>>> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
>>> index 968877f..f8eee60 100644
>>> --- a/drivers/dma/fsldma.c
>>> +++ b/drivers/dma/fsldma.c
>>> @@ -459,6 +459,87 @@ static struct fsl_desc_sw
>>> *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
>>> }
>>> /**
>>> + * fsldma_clean_completed_descriptor - free all descriptors which
>>> + * has been completed and acked
>> IIRC the summary should be oneliner.
>> Check the rest of the code as well.
>
> I don't think so.
> See this Documentation/kernel-doc-nano-HOWTO.txt, and you can find
> this sentence "The short description following the subject can span
> multiple lines"
>
>>> + * @chan: Freescale DMA channel
>>> + *
>>> + * This function is used on all completed and acked descriptors.
>>> + * All descriptors should only be freed in this function.
>>> + */
>>> +static void fsldma_clean_completed_descriptor(struct fsldma_chan
>>> *chan)
>>> +{
>>> + struct fsl_desc_sw *desc, *_desc;
>>> +
>>> + /* Run the callback for each descriptor, in order */
>>> + list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
>>> + if (async_tx_test_ack(&desc->async_tx))
>>> + fsl_dma_free_descriptor(chan, desc);
>>> +}
>>> +
>>> +/**
>>> + * fsldma_run_tx_complete_actions - cleanup a single link descriptor
>>> + * @chan: Freescale DMA channel
>>> + * @desc: descriptor to cleanup and free
>>> + * @cookie: Freescale DMA transaction identifier
>>> + *
>>> + * This function is used on a descriptor which has been executed by
>>> the DMA
>>> + * controller. It will run any callbacks, submit any dependencies.
>>> + */
>>> +static dma_cookie_t fsldma_run_tx_complete_actions(struct
>>> fsldma_chan *chan,
>>> + struct fsl_desc_sw *desc, dma_cookie_t cookie)
>> Maybe you could use cookie as local variable?
>
> Yes.. it doesn't seem good to set a value to input parameter.
>
>>> +{
>>> + struct dma_async_tx_descriptor *txd = &desc->async_tx;
>>> +
>>> + BUG_ON(txd->cookie < 0);
>>> +
>>> + if (txd->cookie > 0) {
>>> + cookie = txd->cookie;
>>> +
>>> + /* Run the link descriptor callback function */
>>> + if (txd->callback) {
>>> + chan_dbg(chan, "LD %p callback\n", desc);
>>> + txd->callback(txd->callback_param);
>>> + }
>>> + }
>>> +
>>> + /* Run any dependencies */
>>> + dma_run_dependencies(txd);
>>> +
>>> + return cookie;
>>> +}
>>> +
>>> +/**
>>> + * fsldma_clean_running_descriptor - move the completed descriptor
>>> from
>>> + * ld_running to ld_completed
>>> + * @chan: Freescale DMA channel
>>> + * @desc: the descriptor which is completed
>>> + *
>>> + * Free the descriptor directly if acked by async_tx api, or move
>>> it to
>>> + * queue ld_completed.
>>> + */
>>> +static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
>>> + struct fsl_desc_sw *desc)
>>> +{
>>> + /* Remove from the list of transactions */
>>> + list_del(&desc->node);
>>> +
>>> + /*
>>> + * the client is allowed to attach dependent operations
>> Capital letter first?
>
> Better to do so, thanks.
>
>>> + * until 'ack' is set
>>> + */
>>> + if (!async_tx_test_ack(&desc->async_tx)) {
>>> + /*
>>> + * Move this descriptor to the list of descriptors which is
>>> + * completed, but still awaiting the 'ack' bit to be set.
>>> + */
>>> + list_add_tail(&desc->node, &chan->ld_completed);
>>> + return;
>>> + }
>>> +
>>> + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
>>> +}
>>> +
>>> +/**
>>> * fsl_chan_xfer_ld_queue - transfer any pending transactions
>>> * @chan : Freescale DMA channel
>>> *
>>> @@ -526,30 +607,58 @@ static void fsl_chan_xfer_ld_queue(struct
>>> fsldma_chan *chan)
>>> }
>>> /**
>>> - * fsldma_cleanup_descriptor - cleanup and free a single link
>>> descriptor
>>> + * fsldma_cleanup_descriptors - cleanup link descriptors which are
>>> completed
>>> + * and move them to ld_completed to free until flag 'ack' is set
>>> * @chan: Freescale DMA channel
>>> - * @desc: descriptor to cleanup and free
>>> *
>>> - * This function is used on a descriptor which has been executed by
>>> the DMA
>>> - * controller. It will run any callbacks, submit any dependencies,
>>> and then
>>> - * free the descriptor.
>>> + * This function is used on descriptors which have been executed by
>>> the DMA
>>> + * controller. It will run any callbacks, submit any dependencies,
>>> then
>>> + * free these descriptors if flag 'ack' is set.
>>> */
>>> -static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
>>> - struct fsl_desc_sw *desc)
>>> +static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
>>> {
>>> - struct dma_async_tx_descriptor *txd = &desc->async_tx;
>>> + struct fsl_desc_sw *desc, *_desc;
>>> + dma_cookie_t cookie = 0;
>>> + dma_addr_t curr_phys = get_cdar(chan);
>>> + int seen_current = 0;
>>> +
>>> + fsldma_clean_completed_descriptor(chan);
>>> +
>>> + /* Run the callback for each descriptor, in order */
>>> + list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
>>> + /*
>>> + * do not advance past the current descriptor loaded into the
>> Capital letter first.
>>
>>> + * hardware channel, subsequent descriptors are either in
>>> + * process or have not been submitted
>> Dot at the eol. Check in all comments.
>
> Even though I saw there are other comments without the dots, I think
> it is better to have it.
> Thanks, all.
>
Hmm... think it again, it it really necessary to have it?
Even I have it in my patch, there are already so many comments exists
without it.
>>
>>> + */
>>> + if (seen_current)
>>> + break;
>>> +
>>> + /*
>>> + * stop the search if we reach the current descriptor and the
>>> + * channel is busy
>>> + */
>>> + if (desc->async_tx.phys == curr_phys) {
>>> + seen_current = 1;
>>> + if (!dma_is_idle(chan))
>>> + break;
>>> + }
>>> +
>>> + cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
>>> - /* Run the link descriptor callback function */
>>> - if (txd->callback) {
>>> - chan_dbg(chan, "LD %p callback\n", desc);
>>> - txd->callback(txd->callback_param);
>>> + fsldma_clean_running_descriptor(chan, desc);
>>> }
>>> - /* Run any dependencies */
>>> - dma_run_dependencies(txd);
>>> + /*
>>> + * Start any pending transactions automatically
>> Dot at the end of the line.
>>
>>> + *
>>> + * In the ideal case, we keep the DMA controller busy while we go
>>> + * ahead and free the descriptors below.
>>> + */
>>> + fsl_chan_xfer_ld_queue(chan);
>>> - dma_descriptor_unmap(txd);
>>> - fsl_dma_free_descriptor(chan, desc);
>>> + if (cookie > 0)
>>
>>> + chan->common.completed_cookie = cookie;
>>> }
>>> /**
>>> @@ -620,8 +729,10 @@ static void fsl_dma_free_chan_resources(struct
>>> dma_chan *dchan)
>>> chan_dbg(chan, "free all channel resources\n");
>>> spin_lock_irqsave(&chan->desc_lock, flags);
>>> + fsldma_cleanup_descriptors(chan);
>>> fsldma_free_desc_list(chan, &chan->ld_pending);
>>> fsldma_free_desc_list(chan, &chan->ld_running);
>>> + fsldma_free_desc_list(chan, &chan->ld_completed);
>>> spin_unlock_irqrestore(&chan->desc_lock, flags);
>>> dma_pool_destroy(chan->desc_pool);
>>> @@ -859,6 +970,7 @@ static int fsl_dma_device_control(struct
>>> dma_chan *dchan,
>>> /* Remove and free all of the descriptors in the LD queue */
>>> fsldma_free_desc_list(chan, &chan->ld_pending);
>>> fsldma_free_desc_list(chan, &chan->ld_running);
>>> + fsldma_free_desc_list(chan, &chan->ld_completed);
>>> chan->idle = true;
>>> spin_unlock_irqrestore(&chan->desc_lock, flags);
>>> @@ -918,6 +1030,17 @@ static enum dma_status fsl_tx_status(struct
>>> dma_chan *dchan,
>>> dma_cookie_t cookie,
>>> struct dma_tx_state *txstate)
>>> {
>>> + struct fsldma_chan *chan = to_fsl_chan(dchan);
>>> + enum dma_status ret;
>>> +
>>> + ret = dma_cookie_status(dchan, cookie, txstate);
>>> + if (ret == DMA_COMPLETE)
>>> + return ret;
>>> +
>>> + spin_lock_bh(&chan->desc_lock);
>>> + fsldma_cleanup_descriptors(chan);
>>> + spin_unlock_bh(&chan->desc_lock);
>>> +
>>> return dma_cookie_status(dchan, cookie, txstate);
>>> }
>>> @@ -995,52 +1118,19 @@ static irqreturn_t fsldma_chan_irq(int irq,
>>> void *data)
>>> static void dma_do_tasklet(unsigned long data)
>>> {
>>> struct fsldma_chan *chan = (struct fsldma_chan *)data;
>>> - struct fsl_desc_sw *desc, *_desc;
>>> - LIST_HEAD(ld_cleanup);
>>> unsigned long flags;
>>> chan_dbg(chan, "tasklet entry\n");
>>> spin_lock_irqsave(&chan->desc_lock, flags);
>>> - /* update the cookie if we have some descriptors to cleanup */
>>> - if (!list_empty(&chan->ld_running)) {
>>> - dma_cookie_t cookie;
>>> -
>>> - desc = to_fsl_desc(chan->ld_running.prev);
>>> - cookie = desc->async_tx.cookie;
>>> - dma_cookie_complete(&desc->async_tx);
>>> -
>>> - chan_dbg(chan, "completed_cookie=%d\n", cookie);
>>> - }
>>> -
>>> - /*
>>> - * move the descriptors to a temporary list so we can drop the
>>> lock
>>> - * during the entire cleanup operation
>>> - */
>>> - list_splice_tail_init(&chan->ld_running, &ld_cleanup);
>>> -
>>> /* the hardware is now idle and ready for more */
>>> chan->idle = true;
>>> - /*
>>> - * Start any pending transactions automatically
>>> - *
>>> - * In the ideal case, we keep the DMA controller busy while we go
>>> - * ahead and free the descriptors below.
>>> - */
>>> - fsl_chan_xfer_ld_queue(chan);
>>> - spin_unlock_irqrestore(&chan->desc_lock, flags);
>>> + /* Run all cleanup for descriptors which have been completed */
>>> + fsldma_cleanup_descriptors(chan);
>>> - /* Run the callback for each descriptor, in order */
>>> - list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
>>> -
>>> - /* Remove from the list of transactions */
>>> - list_del(&desc->node);
>>> -
>>> - /* Run all cleanup for this descriptor */
>>> - fsldma_cleanup_descriptor(chan, desc);
>>> - }
>>> + spin_unlock_irqrestore(&chan->desc_lock, flags);
>>> chan_dbg(chan, "tasklet exit\n");
>>> }
>>> @@ -1224,6 +1314,7 @@ static int fsl_dma_chan_probe(struct
>>> fsldma_device *fdev,
>>> spin_lock_init(&chan->desc_lock);
>>> INIT_LIST_HEAD(&chan->ld_pending);
>>> INIT_LIST_HEAD(&chan->ld_running);
>>> + INIT_LIST_HEAD(&chan->ld_completed);
>>> chan->idle = true;
>>> chan->common.device = &fdev->common;
>>> diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
>>> index d56e835..ec19517 100644
>>> --- a/drivers/dma/fsldma.h
>>> +++ b/drivers/dma/fsldma.h
>>> @@ -138,8 +138,21 @@ struct fsldma_chan {
>>> char name[8]; /* Channel name */
>>> struct fsldma_chan_regs __iomem *regs;
>>> spinlock_t desc_lock; /* Descriptor operation lock */
>>> - struct list_head ld_pending; /* Link descriptors queue */
>>> - struct list_head ld_running; /* Link descriptors queue */
>>> + /*
>>> + * Descriptors which are queued to run, but have not yet been
>>> + * submitted to the hardware for execution
>>> + */
>>> + struct list_head ld_pending;
>>> + /*
>>> + * Descriptors which are currently being executed by the hardware
>>> + */
>>> + struct list_head ld_running;
>>> + /*
>>> + * Descriptors which have finished execution by the hardware.
>>> These
>>> + * descriptors have already had their cleanup actions run. They
>>> are
>>> + * waiting for the ACK bit to be set by the async_tx API.
>>> + */
>>> + struct list_head ld_completed; /* Link descriptors queue */
>>> struct dma_chan common; /* DMA common channel */
>>> struct dma_pool *desc_pool; /* Descriptors pool */
>>> struct device *dev; /* Channel device */
>>
>
^ permalink raw reply
* RE: [PATCH v2] fix wrong usage of dmaengine_unmap_put in async_xxx
From: Xuelin Shi @ 2014-04-11 8:31 UTC (permalink / raw)
To: Dan Williams; +Cc: Koul, Vinod, dmaengine@vger.kernel.org, linuxppc-dev
In-Reply-To: <CAA9_cmcJ0Zb-X--d9_maTssWNYFd5j_hBHSx8cJiOJgkM_91FQ@mail.gmail.com>
SGkgRGFuLA0KDQpXaXRoIGh0dHBzOi8vcGF0Y2h3b3JrLmtlcm5lbC5vcmcvcGF0Y2gvMzg2Mzcx
MS8gYXBwbGllZCwgdGhlIGlzc3VlIGRpc2FwcGVhcmVkLg0KDQpUaGFua3MsDQpYdWVsaW4gU2hp
DQoNCi0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQpGcm9tOiBkYW4uai53aWxsaWFtc0BnbWFp
bC5jb20gW21haWx0bzpkYW4uai53aWxsaWFtc0BnbWFpbC5jb21dIE9uIEJlaGFsZiBPZiBEYW4g
V2lsbGlhbXMNClNlbnQ6IDIwMTTE6jTUwjEwyNUgMTI6MDINClRvOiBTaGkgWHVlbGluLUIyOTIz
Nw0KQ2M6IEtvdWwsIFZpbm9kOyBkbWFlbmdpbmVAdmdlci5rZXJuZWwub3JnOyBsaW51eHBwYy1k
ZXYNClN1YmplY3Q6IFJlOiBbUEFUQ0ggdjJdIGZpeCB3cm9uZyB1c2FnZSBvZiBkbWFlbmdpbmVf
dW5tYXBfcHV0IGluIGFzeW5jX3h4eA0KDQpPbiBUaHUsIE1hciAyMCwgMjAxNCBhdCAxOjE2IEFN
LCAgPHh1ZWxpbi5zaGlAZnJlZXNjYWxlLmNvbT4gd3JvdGU6DQo+IEZyb206IFh1ZWxpbiBTaGkg
PHh1ZWxpbi5zaGlAZnJlZXNjYWxlLmNvbT4NCj4NCj4gZG1hZW5naW5lX3VubWFwX3B1dCBkb2Vz
IGJlbG93IHR3byB0aGluZ3M6DQo+IGEpIHVubWFwIHBhZ2VzIGZvciBzcmNzIGFuZCBkZXN0cw0K
PiBiKSBmcmVlIHVubWFwIHN0cnVjdA0KPg0KPiBUaGUgdW5tYXAgc3RydWN0IGRhdGEgaXMgZ2Vu
ZXJhdGVkIGJ1dCBvbmx5IGluaXRpYWxpemVkIHdoaWxlIG90aGVyIA0KPiBzb21lIGRtYSBjb250
aW9ucyBhcmUgbWV0LCBsaWtlIGRtYSBhbGlnbm1lbnQgZXRjLg0KPiBJZiB0aGUgdW5tYXAgZGF0
YSBpcyBub3QgaW5pdGlhbGl6ZWQsIGNhbGwgZG1hZW5naW5lX3VubWFwX3B1dCB3aWxsIA0KPiB1
bm1hcCBzb21lIHJhbmRvbSBkYXRhIGluIHVubWFwLT5hZGRyWy4uLl0NCg0KQWN0dWFsbHksIHRo
aXMgc2hvdWxkIGJlIGZpeGVkIGJ5IHlvdXIgb3RoZXIgcGF0Y2g6DQoNCmh0dHBzOi8vcGF0Y2h3
b3JrLmtlcm5lbC5vcmcvcGF0Y2gvMzg2MzcxMS8NCg0KQmVjYXVzZSB0aGUgdG9fY250LCBmcm9t
X2NudCwgYXJlIHByb3Blcmx5IGluaXRpYWxpemVkIHRvIHplcm8uICBUaGUgb25seSBpc3N1ZSB3
YXMgdGhhdCB0aGUgdW5tYXAgcG9vbCB3YXMgbm90IHNwZWNpZmllZC4NCg0KQ2FuIHlvdSB2ZXJp
ZnkgdGhhdCB0aGUgcHJvYmxlbSBzdGlsbCBleGlzdHMgd2l0aCB0aGF0IHBhdGNoIGFwcGxpZWQ/
DQpJJ2xsIG1hcmsgaXQgZm9yIC1zdGFibGUuDQoNCj4gQWxzbyBjYWxsIGRtYWVuZ2luZV9nZXRf
dW5tYXBfZGF0YSBpbW1lZGlhdGFsbHkgYWZ0ZXIgZ2VuZXJhdGluZyB0eCBpcyANCj4gbm90IGNv
cnJlY3QuIE1heWJlIHRoZSB0eCBoYXMgbm90IGJlZW4gZmluaXNoZWQgYnkgRE1BIGhhcmR3YXJl
IHlldCANCj4gYnV0IHRoZSBzcmNzIGFuZCBkZXN0cyBhcmUgZG1hIHVubWFwcGVkLg0KDQpJIGRp
c2FncmVlLiAgSXQgaXMgY29ycmVjdCBiZWNhdXNlIHRoZSB1bm1hcCBkYXRhIGlzIHJlZmVyZW5j
ZSBjb3VudGVkLiAgSWYgdGhlIERNQSBoYXJkd2FyZSBpcyBzdGlsbCB1c2luZyB0aGUgYnVmZmVy
cyB0aGVuIGl0IG11c3QgaG9sZCBhIHJlZmVyZW5jZSBvbiB0aGUgdW5tYXAgZGF0YS4gIFRoZSBk
bWFlbmdpbmVfcHV0X3VubWFwX2RhdGEoKSBpbnN0YW5jZXMgeW91ciBhcmUgcmVtb3ZpbmcgYXJl
IHRoZSBvbmVzIHRoYXQgZHJvcCB0aGUgaW5pdGlhbCByZWZlcmVuY2UgY291bnQgc2V0IGluIGRt
YWVuZ2luZV9nZXRfdW5tYXBfZGF0YSgpLg0KDQo=
^ permalink raw reply
* [PATCH v3] dmaengine: driver support for FSL RaidEngine device.
From: xuelin.shi @ 2014-04-11 7:41 UTC (permalink / raw)
To: dan.j.williams, vinod.koul
Cc: Harninder Rai, andriy.shevchenko, Naveen Burmi, dmaengine,
Xuelin Shi, linuxppc-dev
From: Xuelin Shi <xuelin.shi@freescale.com>
The RaidEngine is a new FSL hardware used for Raid5/6 acceration.
This patch enables the RaidEngine functionality and provides
hardware offloading capability for memcpy, xor and pq computation.
It works with async_tx.
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Signed-off-by: Naveen Burmi <naveenburmi@freescale.com>
Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com>
---
changes for v3:
- fix memory allocation flag GFP_xxx usage.
- add re_jr_issue_pending call in cleanup.
- remove unnecessary dma_run_dependencies(...).
- use dma_cookie_complete(...) instead of direct updating cookie.
drivers/dma/Kconfig | 11 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl_raid.c | 878 +++++++++++++++++++++++++++++++++++++++++++++++++
drivers/dma/fsl_raid.h | 308 +++++++++++++++++
4 files changed, 1198 insertions(+)
create mode 100644 drivers/dma/fsl_raid.c
create mode 100644 drivers/dma/fsl_raid.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016..829f41c 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -100,6 +100,17 @@ config FSL_DMA
EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
some Txxx and Bxxx parts.
+config FSL_RAID
+ tristate "Freescale RAID engine Support"
+ depends on FSL_SOC && !FSL_DMA
+ select DMA_ENGINE
+ select DMA_ENGINE_RAID
+ ---help---
+ Enable support for Freescale RAID Engine. RAID Engine is
+ available on some QorIQ SoCs (like P5020). It has
+ the capability to offload memcpy, xor and pq computation
+ for raid5/6.
+
config MPC512X_DMA
tristate "Freescale MPC512x built-in DMA engine support"
depends on PPC_MPC512x || PPC_MPC831x
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a029d0f4..60b163b 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_K3_DMA) += k3dma.o
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
+obj-$(CONFIG_FSL_RAID) += fsl_raid.o
diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c
new file mode 100644
index 0000000..4b389b1
--- /dev/null
+++ b/drivers/dma/fsl_raid.c
@@ -0,0 +1,878 @@
+/*
+ * drivers/dma/fsl_raid.c
+ *
+ * Freescale RAID Engine device driver
+ *
+ * Author:
+ * Harninder Rai <harninder.rai@freescale.com>
+ * Naveen Burmi <naveenburmi@freescale.com>
+ *
+ * Rewrite:
+ * Xuelin Shi <xuelin.shi@freescale.com>
+ *
+ * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Theory of operation:
+ *
+ * General capabilities:
+ * RAID Engine (RE) block is capable of offloading XOR, memcpy and P/Q
+ * calculations required in RAID5 and RAID6 operations. RE driver
+ * registers with Linux's ASYNC layer as dma driver. RE hardware
+ * maintains strict ordering of the requests through chained
+ * command queueing.
+ *
+ * Data flow:
+ * Software RAID layer of Linux (MD layer) maintains RAID partitions,
+ * strips, stripes etc. It sends requests to the underlying AYSNC layer
+ * which further passes it to RE driver. ASYNC layer decides which request
+ * goes to which job ring of RE hardware. For every request processed by
+ * RAID Engine, driver gets an interrupt unless coalescing is set. The
+ * per job ring interrupt handler checks the status register for errors,
+ * clears the interrupt and leave the post interrupt processing to the irq
+ * thread.
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/dmaengine.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "dmaengine.h"
+#include "fsl_raid.h"
+
+#define MAX_XOR_SRCS 16
+#define MAX_PQ_SRCS 16
+#define MAX_INITIAL_DESCS 256
+#define MAX_DESCS_LIMIT (4 * MAX_INITIAL_DESCS)
+#define FRAME_FORMAT 0x1
+#define MAX_DATA_LENGTH (1024*1024)
+
+#define to_fsl_re_dma_desc(tx) container_of(tx, \
+ struct fsl_re_dma_async_tx_desc, async_tx)
+
+/* Add descriptors into per jr software queue - submit_q */
+static dma_cookie_t re_jr_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct re_jr *jr;
+ dma_cookie_t cookie;
+ unsigned long flags;
+
+ desc = to_fsl_re_dma_desc(tx);
+ jr = container_of(tx->chan, struct re_jr, chan);
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ cookie = dma_cookie_assign(tx);
+ list_add_tail(&desc->node, &jr->submit_q);
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+
+ return cookie;
+}
+
+/* Copy descriptor from per jr software queue into hardware job ring */
+static void re_jr_issue_pending(struct dma_chan *chan)
+{
+ struct re_jr *jr;
+ int avail;
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ unsigned long flags;
+
+ jr = container_of(chan, struct re_jr, chan);
+
+ avail = RE_JR_INB_SLOT_AVAIL(in_be32(&jr->jrregs->inbring_slot_avail));
+ if (!avail)
+ return;
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ list_for_each_entry_safe(desc, _desc, &jr->submit_q, node) {
+ if (!avail)
+ break;
+
+ list_move_tail(&desc->node, &jr->active_q);
+
+ memcpy(&jr->inb_ring_virt_addr[jr->inb_count], &desc->hwdesc,
+ sizeof(struct jr_hw_desc));
+
+ jr->inb_count = (jr->inb_count + 1) & RING_SIZE_MASK;
+
+ /* add one job into job ring */
+ out_be32(&jr->jrregs->inbring_add_job, RE_JR_INB_JOB_ADD(1));
+ avail--;
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+}
+
+static void re_jr_desc_done(struct fsl_re_dma_async_tx_desc *desc)
+{
+ dma_async_tx_callback callback;
+ void *callback_param;
+
+ dma_cookie_complete(&desc->async_tx);
+
+ callback = desc->async_tx.callback;
+ callback_param = desc->async_tx.callback_param;
+ if (callback)
+ callback(callback_param);
+
+ dma_descriptor_unmap(&desc->async_tx);
+}
+
+static void re_jr_dequeue(struct re_jr *jr)
+{
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ struct jr_hw_desc *hwdesc;
+ unsigned int count;
+ u32 sw_high, done_high;
+ int found;
+
+ count = RE_JR_OUB_SLOT_FULL(in_be32(&jr->jrregs->oubring_slot_full));
+ while (count--) {
+ found = 0;
+ hwdesc = &jr->oub_ring_virt_addr[jr->oub_count];
+ list_for_each_entry_safe(desc, _desc, &jr->active_q, node) {
+ /* compare the hw dma addr to find the completed */
+ sw_high = desc->hwdesc.lbea32 & HWDESC_ADDR_HIGH_MASK;
+ done_high = hwdesc->lbea32 & HWDESC_ADDR_HIGH_MASK;
+ if (sw_high == done_high &&
+ desc->hwdesc.addr_low == hwdesc->addr_low) {
+ found = 1;
+ break;
+ }
+ }
+
+ BUG_ON(!found);
+ re_jr_desc_done(desc);
+ list_move_tail(&desc->node, &jr->ack_q);
+
+ jr->oub_count = (jr->oub_count + 1) & RING_SIZE_MASK;
+ out_be32(&jr->jrregs->oubring_job_rmvd, RE_JR_OUB_JOB_RMVD(1));
+ }
+}
+
+static void re_jr_cleanup_descs(struct re_jr *jr)
+{
+ struct fsl_re_dma_async_tx_desc *desc, *_desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&jr->desc_lock, flags);
+ re_jr_dequeue(jr);
+ list_for_each_entry_safe(desc, _desc, &jr->ack_q, node) {
+ if (async_tx_test_ack(&desc->async_tx))
+ list_move_tail(&desc->node, &jr->free_q);
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, flags);
+
+ re_jr_issue_pending(&jr->chan);
+}
+
+static irqreturn_t re_jr_isr_thread(int irq, void *data)
+{
+ struct re_jr *jr = (struct re_jr *)data;
+
+ re_jr_cleanup_descs(jr);
+
+ return IRQ_HANDLED;
+}
+
+/* Per Job Ring interrupt handler */
+static irqreturn_t re_jr_isr(int irq, void *data)
+{
+ struct re_jr *jr = (struct re_jr *)data;
+
+ u32 irqstate, status;
+ irqstate = in_be32(&jr->jrregs->jr_interrupt_status);
+ if (!irqstate)
+ return IRQ_NONE;
+
+ /*
+ * There's no way in upper layer (read MD layer) to recover from
+ * error conditions except restart everything. In long term we
+ * need to do something more than just crashing
+ */
+ if (irqstate & RE_JR_ERROR) {
+ status = in_be32(&jr->jrregs->jr_status);
+ dev_err(jr->dev, "jr error irqstate: %x, status: %x\n",
+ irqstate, status);
+ }
+
+ /* Clear interrupt */
+ out_be32(&jr->jrregs->jr_interrupt_status, RE_JR_CLEAR_INT);
+ return IRQ_WAKE_THREAD;
+}
+
+static enum dma_status re_jr_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie, struct dma_tx_state *txstate)
+{
+ enum dma_status ret;
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+
+ if (ret != DMA_COMPLETE) {
+ re_jr_cleanup_descs(jr);
+ ret = dma_cookie_status(chan, cookie, txstate);
+ }
+
+ return ret;
+}
+
+void fill_cfd_frame(struct cmpnd_frame *cf, u8 index,
+ size_t length, dma_addr_t addr, bool final)
+{
+ u32 efrl = length & CF_LENGTH_MASK;
+ efrl |= final << CF_FINAL_SHIFT;
+ cf[index].efrl32 = efrl;
+ cf[index].addr_high = (addr >> 32) & HWDESC_ADDR_HIGH_MASK;
+ cf[index].addr_low = (u32)addr;
+}
+
+static struct fsl_re_dma_async_tx_desc *re_jr_init_desc(struct re_jr *jr,
+ struct fsl_re_dma_async_tx_desc *desc, void *cf, dma_addr_t paddr)
+{
+ desc->jr = jr;
+ desc->async_tx.tx_submit = re_jr_tx_submit;
+ dma_async_tx_descriptor_init(&desc->async_tx, &jr->chan);
+ INIT_LIST_HEAD(&desc->node);
+
+ desc->hwdesc.fmt32 = FRAME_FORMAT << HWDESC_FMT_SHIFT;
+ desc->hwdesc.lbea32 = (paddr >> 32) & HWDESC_ADDR_HIGH_MASK;
+ desc->hwdesc.addr_low = (u32)paddr;
+ desc->cf_addr = cf;
+ desc->cf_paddr = paddr;
+
+ desc->cdb_addr = (void *)(cf + RE_CF_DESC_SIZE);
+ desc->cdb_paddr = paddr + RE_CF_DESC_SIZE;
+
+ return desc;
+}
+
+static struct fsl_re_dma_async_tx_desc *re_jr_alloc_desc(struct re_jr *jr,
+ unsigned long flags)
+{
+ struct fsl_re_dma_async_tx_desc *desc = NULL;
+ void *cf;
+ dma_addr_t paddr;
+ unsigned long lock_flag;
+
+ re_jr_cleanup_descs(jr);
+
+ spin_lock_irqsave(&jr->desc_lock, lock_flag);
+ if (!list_empty(&jr->free_q)) {
+ /* take one desc from free_q */
+ desc = list_first_entry(&jr->free_q,
+ struct fsl_re_dma_async_tx_desc, node);
+ list_del(&desc->node);
+
+ desc->async_tx.flags = flags;
+ }
+ spin_unlock_irqrestore(&jr->desc_lock, lock_flag);
+
+ if (!desc) {
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ cf = dma_pool_alloc(jr->re_dev->cf_desc_pool, GFP_NOWAIT,
+ &paddr);
+ if (!desc || !cf) {
+ kfree(desc);
+ return NULL;
+ }
+
+ desc = re_jr_init_desc(jr, desc, cf, paddr);
+ desc->async_tx.flags = flags;
+
+ spin_lock_irqsave(&jr->desc_lock, lock_flag);
+ jr->alloc_count++;
+ spin_unlock_irqrestore(&jr->desc_lock, lock_flag);
+ }
+
+ return desc;
+}
+
+static struct dma_async_tx_descriptor *re_jr_prep_genq(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
+ unsigned int src_cnt, const unsigned char *scf, size_t len,
+ unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct xor_cdb *xor;
+ struct cmpnd_frame *cf;
+ u32 cdb;
+ unsigned int i, j;
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ jr = container_of(chan, struct re_jr, chan);
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling xor CDB */
+ cdb = RE_XOR_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= (src_cnt - 1) << RE_CDB_NRCS_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= INTERRUPT_ON_ERROR << RE_CDB_ERROR_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+ xor = desc->cdb_addr;
+ xor->cdb32 = cdb;
+
+ if (scf != NULL) {
+ /* compute q = src0*coef0^src1*coef1^..., * is GF(8) mult */
+ for (i = 0; i < src_cnt; i++)
+ xor->gfm[i] = scf[i];
+ } else {
+ /* compute P, that is XOR all srcs */
+ for (i = 0; i < src_cnt; i++)
+ xor->gfm[i] = 1;
+ }
+
+ /* Filling frame 0 of compound frame descriptor with CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct xor_cdb), desc->cdb_paddr, 0);
+
+ /* Fill CFD's 1st frame with dest buffer */
+ fill_cfd_frame(cf, 1, len, dest, 0);
+
+ /* Fill CFD's rest of the frames with source buffers */
+ for (i = 2, j = 0; j < src_cnt; i++, j++)
+ fill_cfd_frame(cf, i, len, src[j], 0);
+
+ /* Setting the final bit in the last source buffer frame in CFD */
+ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT;
+
+ return &desc->async_tx;
+}
+
+/*
+ * Prep function for P parity calculation.In RAID Engine terminology,
+ * XOR calculation is called GenQ calculation done through GenQ command
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_dma_xor(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
+ unsigned int src_cnt, size_t len, unsigned long flags)
+{
+ /* NULL let genq take all coef as 1 */
+ return re_jr_prep_genq(chan, dest, src, src_cnt, NULL, len, flags);
+}
+
+/*
+ * Prep function for P/Q parity calculation.In RAID Engine terminology,
+ * P/Q calculation is called GenQQ done through GenQQ command
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_pq(
+ struct dma_chan *chan, dma_addr_t *dest, dma_addr_t *src,
+ unsigned int src_cnt, const unsigned char *scf, size_t len,
+ unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ struct pq_cdb *pq;
+ struct cmpnd_frame *cf;
+ u32 cdb;
+ u8 *p;
+ int gfmq_len, i, j;
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ /*
+ * RE requires at least 2 sources, if given only one source, we pass the
+ * second source same as the first one.
+ * With only one source, generating P is meaningless, only generate Q.
+ */
+ if (src_cnt == 1) {
+ struct dma_async_tx_descriptor *tx;
+ dma_addr_t dma_src[2];
+ unsigned char coef[2];
+
+ dma_src[0] = *src;
+ coef[0] = *scf;
+ dma_src[1] = *src;
+ coef[1] = 0;
+ tx = re_jr_prep_genq(chan, dest[1], dma_src, 2, coef, len,
+ flags);
+ if (tx)
+ desc = to_fsl_re_dma_desc(tx);
+
+ return tx;
+ }
+
+ /*
+ * During RAID6 array creation, Linux's MD layer gets P and Q
+ * calculated separately in two steps. But our RAID Engine has
+ * the capability to calculate both P and Q with a single command
+ * Hence to merge well with MD layer, we need to provide a hook
+ * here and call re_jq_prep_genq() function
+ */
+
+ if (flags & DMA_PREP_PQ_DISABLE_P)
+ return re_jr_prep_genq(chan, dest[1], src, src_cnt,
+ scf, len, flags);
+
+ jr = container_of(chan, struct re_jr, chan);
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling GenQQ CDB */
+ cdb = RE_PQ_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= (src_cnt - 1) << RE_CDB_NRCS_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= BUFFERABLE_OUTPUT << RE_CDB_BUFFER_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+
+ pq = desc->cdb_addr;
+ pq->cdb32 = cdb;
+
+ p = pq->gfm_q1;
+ /* Init gfm_q1[] */
+ for (i = 0; i < src_cnt; i++)
+ p[i] = 1;
+
+ /* Align gfm[] to 32bit */
+ gfmq_len = ALIGN(src_cnt, 4);
+
+ /* Init gfm_q2[] */
+ p += gfmq_len;
+ for (i = 0; i < src_cnt; i++)
+ p[i] = scf[i];
+
+ /* Filling frame 0 of compound frame descriptor with CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct pq_cdb), desc->cdb_paddr, 0);
+
+ /* Fill CFD's 1st & 2nd frame with dest buffers */
+ for (i = 1, j = 0; i < 3; i++, j++)
+ fill_cfd_frame(cf, i, len, dest[j], 0);
+
+ /* Fill CFD's rest of the frames with source buffers */
+ for (i = 3, j = 0; j < src_cnt; i++, j++)
+ fill_cfd_frame(cf, i, len, src[j], 0);
+
+ /* Setting the final bit in the last source buffer frame in CFD */
+ cf[i - 1].efrl32 |= 1 << CF_FINAL_SHIFT;
+
+ return &desc->async_tx;
+}
+
+/*
+ * Prep function for memcpy. In RAID Engine, memcpy is done through MOVE
+ * command. Logic of this function will need to be modified once multipage
+ * support is added in Linux's MD/ASYNC Layer
+ */
+static struct dma_async_tx_descriptor *re_jr_prep_memcpy(
+ struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ size_t len, unsigned long flags)
+{
+ struct re_jr *jr;
+ struct fsl_re_dma_async_tx_desc *desc;
+ size_t length;
+ struct cmpnd_frame *cf;
+ struct move_cdb *move;
+ u32 cdb;
+
+ jr = container_of(chan, struct re_jr, chan);
+
+ if (len > MAX_DATA_LENGTH) {
+ pr_err("Length greater than %d not supported\n",
+ MAX_DATA_LENGTH);
+ return NULL;
+ }
+
+ desc = re_jr_alloc_desc(jr, flags);
+ if (desc <= 0)
+ return NULL;
+
+ /* Filling move CDB */
+ cdb = RE_MOVE_OPCODE << RE_CDB_OPCODE_SHIFT;
+ cdb |= RE_BLOCK_SIZE << RE_CDB_BLKSIZE_SHIFT;
+ cdb |= INTERRUPT_ON_ERROR << RE_CDB_ERROR_SHIFT;
+ cdb |= DATA_DEPENDENCY << RE_CDB_DEPEND_SHIFT;
+
+ move = desc->cdb_addr;
+ move->cdb32 = cdb;
+
+ /* Filling frame 0 of CFD with move CDB */
+ cf = desc->cf_addr;
+ fill_cfd_frame(cf, 0, sizeof(struct move_cdb), desc->cdb_paddr, 0);
+
+ length = min_t(size_t, len, MAX_DATA_LENGTH);
+
+ /* Fill CFD's 1st frame with dest buffer */
+ fill_cfd_frame(cf, 1, length, dest, 0);
+
+ /* Fill CFD's 2nd frame with src buffer */
+ fill_cfd_frame(cf, 2, length, src, 1);
+
+ return &desc->async_tx;
+}
+
+static int re_jr_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+ struct fsl_re_dma_async_tx_desc *desc;
+ void *cf;
+ dma_addr_t paddr;
+
+ int i;
+
+ for (i = 0; i < MAX_DESCS_LIMIT; i++) {
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ cf = dma_pool_alloc(jr->re_dev->cf_desc_pool, GFP_KERNEL,
+ &paddr);
+ if (!desc || !cf) {
+ kfree(desc);
+ break;
+ }
+
+ INIT_LIST_HEAD(&desc->node);
+ re_jr_init_desc(jr, desc, cf, paddr);
+
+ list_add_tail(&desc->node, &jr->free_q);
+ jr->alloc_count++;
+ }
+ return jr->alloc_count;
+}
+
+static void re_jr_free_chan_resources(struct dma_chan *chan)
+{
+ struct re_jr *jr = container_of(chan, struct re_jr, chan);
+ struct fsl_re_dma_async_tx_desc *desc;
+
+ while (jr->alloc_count--) {
+ desc = list_first_entry(&jr->free_q,
+ struct fsl_re_dma_async_tx_desc,
+ node);
+
+ list_del(&desc->node);
+ dma_pool_free(jr->re_dev->cf_desc_pool, desc->cf_addr,
+ desc->cf_paddr);
+ kfree(desc);
+ }
+
+ BUG_ON(!list_empty(&jr->free_q));
+}
+
+int re_jr_probe(struct platform_device *ofdev,
+ struct device_node *np, u8 q, u32 off)
+{
+ struct device *dev;
+ struct re_drv_private *repriv;
+ struct re_jr *jr;
+ struct dma_device *dma_dev;
+ u32 ptr;
+ u32 status;
+ int ret = 0, rc;
+ struct platform_device *jr_ofdev;
+
+ dev = &ofdev->dev;
+ repriv = dev_get_drvdata(dev);
+ dma_dev = &repriv->dma_dev;
+
+ jr = devm_kzalloc(dev, sizeof(*jr), GFP_KERNEL);
+ if (!jr) {
+ dev_err(dev, "No free memory for allocating JR struct\n");
+ return -ENOMEM;
+ }
+
+ /* create platform device for jr node */
+ jr_ofdev = of_platform_device_create(np, NULL, dev);
+ if (jr_ofdev == NULL) {
+ dev_err(dev, "Not able to create ofdev for jr %d\n", q);
+ ret = -EINVAL;
+ goto err_free;
+ }
+ dev_set_drvdata(&jr_ofdev->dev, jr);
+
+ /* read reg property from dts */
+ rc = of_property_read_u32(np, "reg", &ptr);
+ if (rc) {
+ dev_err(dev, "Reg property not found in JR number %d\n", q);
+ ret = -ENODEV;
+ goto err_free;
+ }
+
+ jr->jrregs = (struct jr_config_regs *)((u8 *)repriv->re_regs +
+ off + ptr);
+
+ /* read irq property from dts */
+ jr->irq = irq_of_parse_and_map(np, 0);
+ if (jr->irq == NO_IRQ) {
+ dev_err(dev, "No IRQ defined for JR %d\n", q);
+ ret = -ENODEV;
+ goto err_free;
+ }
+
+ ret = devm_request_threaded_irq(&jr_ofdev->dev, jr->irq, re_jr_isr,
+ re_jr_isr_thread, 0, jr->name, jr);
+
+ if (ret) {
+ dev_err(dev, "Unable to register JR interrupt for JR %d\n", q);
+ ret = -EINVAL;
+ goto err_free;
+ }
+
+ snprintf(jr->name, sizeof(jr->name), "re_jr%02d", q);
+
+ repriv->re_jrs[q] = jr;
+ jr->chan.device = dma_dev;
+ jr->chan.private = jr;
+ jr->dev = &jr_ofdev->dev;
+ jr->re_dev = repriv;
+
+ spin_lock_init(&jr->desc_lock);
+ INIT_LIST_HEAD(&jr->ack_q);
+ INIT_LIST_HEAD(&jr->active_q);
+ INIT_LIST_HEAD(&jr->submit_q);
+ INIT_LIST_HEAD(&jr->free_q);
+
+ list_add_tail(&jr->chan.device_node, &dma_dev->channels);
+ dma_dev->chancnt++;
+
+ jr->inb_ring_virt_addr = dma_pool_alloc(jr->re_dev->hw_desc_pool,
+ GFP_KERNEL, &jr->inb_phys_addr);
+
+ if (!jr->inb_ring_virt_addr) {
+ dev_err(dev, "No dma memory for inb_ring_virt_addr\n");
+ ret = -ENOMEM;
+ goto err_free;
+ }
+
+ jr->oub_ring_virt_addr = dma_pool_alloc(jr->re_dev->hw_desc_pool,
+ GFP_KERNEL, &jr->oub_phys_addr);
+
+ if (!jr->oub_ring_virt_addr) {
+ dev_err(dev, "No dma memory for oub_ring_virt_addr\n");
+ ret = -ENOMEM;
+ goto err_free_1;
+ }
+
+ jr->inb_count = 0;
+ jr->oub_count = 0;
+ jr->alloc_count = 0;
+
+ /* Program the Inbound/Outbound ring base addresses and size */
+ out_be32(&jr->jrregs->inbring_base_h,
+ jr->inb_phys_addr & RE_JR_ADDRESS_BIT_MASK);
+ out_be32(&jr->jrregs->oubring_base_h,
+ jr->oub_phys_addr & RE_JR_ADDRESS_BIT_MASK);
+ out_be32(&jr->jrregs->inbring_base_l,
+ jr->inb_phys_addr >> RE_JR_ADDRESS_BIT_SHIFT);
+ out_be32(&jr->jrregs->oubring_base_l,
+ jr->oub_phys_addr >> RE_JR_ADDRESS_BIT_SHIFT);
+ out_be32(&jr->jrregs->inbring_size, RING_SIZE << RING_SIZE_SHIFT);
+ out_be32(&jr->jrregs->oubring_size, RING_SIZE << RING_SIZE_SHIFT);
+
+ /* Read LIODN value from u-boot */
+ status = in_be32(&jr->jrregs->jr_config_1) & RE_JR_REG_LIODN_MASK;
+
+ /* Program the CFG reg */
+ out_be32(&jr->jrregs->jr_config_1,
+ RE_JR_CFG1_CBSI | RE_JR_CFG1_CBS0 | status);
+
+ /* Enable RE/JR */
+ out_be32(&jr->jrregs->jr_command, RE_JR_ENABLE);
+
+ return 0;
+
+err_free_1:
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->inb_ring_virt_addr,
+ jr->inb_phys_addr);
+err_free:
+ return ret;
+}
+
+/* Probe function for RAID Engine */
+static int raide_probe(struct platform_device *ofdev)
+{
+ struct re_drv_private *repriv;
+ struct device_node *np;
+ struct device_node *child;
+ u32 off;
+ u8 ridx = 0;
+ struct dma_device *dma_dev;
+ struct resource *res;
+ int rc;
+ struct device *dev = &ofdev->dev;
+
+ dev_info(dev, "Freescale RAID Engine driver\n");
+
+ repriv = devm_kzalloc(dev, sizeof(*repriv), GFP_KERNEL);
+ if (!repriv)
+ return -ENOMEM;
+
+ res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ /* IOMAP the entire RAID Engine region */
+ repriv->re_regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (!repriv->re_regs)
+ return -EBUSY;
+
+ dev_set_drvdata(dev, repriv);
+
+ /* Print the RE version */
+ dev_info(dev, "Ver = %x\n", in_be32(&repriv->re_regs->re_version_id));
+
+ /* Program the RE mode */
+ out_be32(&repriv->re_regs->global_config, RE_NON_DPAA_MODE);
+ dev_info(dev, "RE mode is %x\n",
+ in_be32(&repriv->re_regs->global_config));
+
+ /* Program Galois Field polynomial */
+ out_be32(&repriv->re_regs->galois_field_config, RE_GFM_POLY);
+ dev_info(dev, "Galois Field Polynomial is %x\n",
+ in_be32(&repriv->re_regs->galois_field_config));
+
+ dma_dev = &repriv->dma_dev;
+ dma_dev->dev = dev;
+ INIT_LIST_HEAD(&dma_dev->channels);
+ dma_set_mask(dev, DMA_BIT_MASK(40));
+
+ dma_dev->device_alloc_chan_resources = re_jr_alloc_chan_resources;
+ dma_dev->device_tx_status = re_jr_tx_status;
+ dma_dev->device_issue_pending = re_jr_issue_pending;
+
+ dma_dev->max_xor = MAX_XOR_SRCS;
+ dma_dev->device_prep_dma_xor = re_jr_prep_dma_xor;
+ dma_cap_set(DMA_XOR, dma_dev->cap_mask);
+
+ dma_dev->max_pq = MAX_PQ_SRCS;
+ dma_dev->device_prep_dma_pq = re_jr_prep_pq;
+ dma_cap_set(DMA_PQ, dma_dev->cap_mask);
+
+ dma_dev->device_prep_dma_memcpy = re_jr_prep_memcpy;
+ dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
+
+ dma_dev->device_free_chan_resources = re_jr_free_chan_resources;
+
+ repriv->total_jrs = 0;
+
+ repriv->cf_desc_pool = dmam_pool_create("re_cf_desc_pool", dev,
+ RE_CF_CDB_SIZE,
+ RE_CF_CDB_ALIGN, 0);
+
+ if (!repriv->cf_desc_pool) {
+ pr_err("No memory for dma desc pool\n");
+ return -ENOMEM;
+ }
+
+ repriv->hw_desc_pool = dmam_pool_create("re_hw_desc_pool", dev,
+ sizeof(struct jr_hw_desc) * RING_SIZE,
+ FRAME_DESC_ALIGNMENT, 0);
+ if (!repriv->hw_desc_pool) {
+ pr_err("No memory for hw desc pool\n");
+ return -ENOMEM;
+ }
+
+ /* Parse Device tree to find out the total number of JQs present */
+ for_each_compatible_node(np, NULL, "fsl,raideng-v1.0-job-queue") {
+ rc = of_property_read_u32(np, "reg", &off);
+ if (rc) {
+ dev_err(dev, "Reg property not found in JQ node\n");
+ return -ENODEV;
+ }
+ /* Find out the Job Rings present under each JQ */
+ for_each_child_of_node(np, child) {
+ rc = of_device_is_compatible(child,
+ "fsl,raideng-v1.0-job-ring");
+ if (rc) {
+ re_jr_probe(ofdev, child, ridx++, off);
+ repriv->total_jrs++;
+ }
+ }
+ }
+
+ dma_async_device_register(dma_dev);
+
+ return 0;
+}
+
+static void release_jr(struct re_jr *jr)
+{
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->inb_ring_virt_addr,
+ jr->inb_phys_addr);
+
+ dma_pool_free(jr->re_dev->hw_desc_pool, jr->oub_ring_virt_addr,
+ jr->oub_phys_addr);
+}
+
+static int raide_remove(struct platform_device *ofdev)
+{
+ struct re_drv_private *repriv;
+ struct device *dev;
+ int i;
+
+ dev = &ofdev->dev;
+ repriv = dev_get_drvdata(dev);
+
+ /* Cleanup JR related memory areas */
+ for (i = 0; i < repriv->total_jrs; i++)
+ release_jr(repriv->re_jrs[i]);
+
+ /* Unregister the driver */
+ dma_async_device_unregister(&repriv->dma_dev);
+
+ return 0;
+}
+
+static struct of_device_id raide_ids[] = {
+ { .compatible = "fsl,raideng-v1.0", },
+ {}
+};
+
+static struct platform_driver raide_driver = {
+ .driver = {
+ .name = "fsl-raideng",
+ .owner = THIS_MODULE,
+ .of_match_table = raide_ids,
+ },
+ .probe = raide_probe,
+ .remove = raide_remove,
+};
+
+module_platform_driver(raide_driver);
+
+MODULE_AUTHOR("Harninder Rai <harninder.rai@freescale.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Freescale RAID Engine Device Driver");
diff --git a/drivers/dma/fsl_raid.h b/drivers/dma/fsl_raid.h
new file mode 100644
index 0000000..10c2dba
--- /dev/null
+++ b/drivers/dma/fsl_raid.h
@@ -0,0 +1,308 @@
+/*
+ * drivers/dma/fsl_raid.h
+ *
+ * Freescale RAID Engine device driver
+ *
+ * Author:
+ * Harninder Rai <harninder.rai@freescale.com>
+ * Naveen Burmi <naveenburmi@freescale.com>
+ *
+ * Rewrite:
+ * Xuelin Shi <xuelin.shi@freescale.com>
+
+ * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define MAX_RE_JRS 4
+
+#define RE_DPAA_MODE (1 << 30)
+#define RE_NON_DPAA_MODE (1 << 31)
+#define RE_GFM_POLY 0x1d000000
+#define RE_JR_INB_JOB_ADD(x) ((x) << 16)
+#define RE_JR_OUB_JOB_RMVD(x) ((x) << 16)
+#define RE_JR_CFG1_CBSI 0x08000000
+#define RE_JR_CFG1_CBS0 0x00080000
+#define RE_JR_OUB_SLOT_FULL_SHIFT 8
+#define RE_JR_OUB_SLOT_FULL(x) ((x) >> RE_JR_OUB_SLOT_FULL_SHIFT)
+#define RE_JR_INB_SLOT_AVAIL_SHIFT 8
+#define RE_JR_INB_SLOT_AVAIL(x) ((x) >> RE_JR_INB_SLOT_AVAIL_SHIFT)
+#define RE_PQ_OPCODE 0x1B
+#define RE_XOR_OPCODE 0x1A
+#define RE_MOVE_OPCODE 0x8
+#define FRAME_DESC_ALIGNMENT 16
+#define RE_BLOCK_SIZE 0x3 /* 4096 bytes */
+#define CACHEABLE_INPUT_OUTPUT 0x0
+#define BUFFERABLE_OUTPUT 0x0
+#define INTERRUPT_ON_ERROR 0x1
+#define DATA_DEPENDENCY 0x1
+#define ENABLE_DPI 0x0
+#define RING_SIZE 0x400
+#define RING_SIZE_MASK (RING_SIZE - 1)
+#define RING_SIZE_SHIFT 8
+#define RE_JR_ADDRESS_BIT_SHIFT 4
+#define RE_JR_ADDRESS_BIT_MASK ((1 << RE_JR_ADDRESS_BIT_SHIFT) - 1)
+#define RE_JR_ERROR 0x40000000
+#define RE_JR_INTERRUPT 0x80000000
+#define RE_JR_CLEAR_INT 0x80000000
+#define RE_JR_PAUSE 0x80000000
+#define RE_JR_ENABLE 0x80000000
+
+#define RE_JR_REG_LIODN_MASK 0x00000FFF
+#define RE_CF_CDB_ALIGN 64
+
+#define RE_CDB_OPCODE_MASK 0xF8000000
+#define RE_CDB_OPCODE_SHIFT 27
+#define RE_CDB_EXCLEN_MASK 0x03000000
+#define RE_CDB_EXCLEN_SHIFT 24
+#define RE_CDB_EXCLQ1_MASK 0x00F00000
+#define RE_CDB_EXCLQ1_SHIFT 20
+#define RE_CDB_EXCLQ2_MASK 0x000F0000
+#define RE_CDB_EXCLQ2_SHIFT 16
+#define RE_CDB_BLKSIZE_MASK 0x0000C000
+#define RE_CDB_BLKSIZE_SHIFT 14
+#define RE_CDB_CACHE_MASK 0x00003000
+#define RE_CDB_CACHE_SHIFT 12
+#define RE_CDB_BUFFER_MASK 0x00000800
+#define RE_CDB_BUFFER_SHIFT 11
+#define RE_CDB_ERROR_MASK 0x00000400
+#define RE_CDB_ERROR_SHIFT 10
+#define RE_CDB_NRCS_MASK 0x0000003C
+#define RE_CDB_NRCS_SHIFT 6
+#define RE_CDB_DEPEND_MASK 0x00000008
+#define RE_CDB_DEPEND_SHIFT 3
+#define RE_CDB_DPI_MASK 0x00000004
+#define RE_CDB_DPI_SHIFT 2
+
+/*
+ * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes.
+ * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes.
+ * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block
+ * 320+180=500, align to 64bytes, that is 512 bytes.
+ */
+#define RE_CF_DESC_SIZE 320
+#define RE_CF_CDB_SIZE 512
+
+struct re_ctrl {
+ /* General Configuration Registers */
+ __be32 global_config; /* Global Configuration Register */
+ u8 rsvd1[4];
+ __be32 galois_field_config; /* Galois Field Configuration Register */
+ u8 rsvd2[4];
+ __be32 jq_wrr_config; /* WRR Configuration register */
+ u8 rsvd3[4];
+ __be32 crc_config; /* CRC Configuration register */
+ u8 rsvd4[228];
+ __be32 system_reset; /* System Reset Register */
+ u8 rsvd5[252];
+ __be32 global_status; /* Global Status Register */
+ u8 rsvd6[832];
+ __be32 re_liodn_base; /* LIODN Base Register */
+ u8 rsvd7[1712];
+ __be32 re_version_id; /* Version ID register of RE */
+ __be32 re_version_id_2; /* Version ID 2 register of RE */
+ u8 rsvd8[512];
+ __be32 host_config; /* Host I/F Configuration Register */
+};
+
+struct jr_config_regs {
+ /* Registers for JR interface */
+ __be32 jr_config_0; /* Job Queue Configuration 0 Register */
+ __be32 jr_config_1; /* Job Queue Configuration 1 Register */
+ __be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
+ u8 rsvd1[4];
+ __be32 jr_command; /* Job Queue Command Register */
+ u8 rsvd2[4];
+ __be32 jr_status; /* Job Queue Status Register */
+ u8 rsvd3[228];
+
+ /* Input Ring */
+ __be32 inbring_base_h; /* Inbound Ring Base Address Register - High */
+ __be32 inbring_base_l; /* Inbound Ring Base Address Register - Low */
+ __be32 inbring_size; /* Inbound Ring Size Register */
+ u8 rsvd4[4];
+ __be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
+ u8 rsvd5[4];
+ __be32 inbring_add_job; /* Inbound Ring Add Job Register */
+ u8 rsvd6[4];
+ __be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
+ u8 rsvd7[220];
+
+ /* Output Ring */
+ __be32 oubring_base_h; /* Outbound Ring Base Address Register - High */
+ __be32 oubring_base_l; /* Outbound Ring Base Address Register - Low */
+ __be32 oubring_size; /* Outbound Ring Size Register */
+ u8 rsvd8[4];
+ __be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
+ u8 rsvd9[4];
+ __be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
+ u8 rsvd10[4];
+ __be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
+};
+
+/*
+ * Command Descriptor Block (CDB) for unicast move command.
+ * In RAID Engine terms, memcpy is done through move command
+ */
+struct move_cdb {
+ __be32 cdb32;
+};
+
+/* Data protection/integrity related fields */
+#define DPI_APPS_MASK 0xC0000000
+#define DPI_APPS_SHIFT 30
+#define DPI_REF_MASK 0x30000000
+#define DPI_REF_SHIFT 28
+#define DPI_GUARD_MASK 0x0C000000
+#define DPI_GUARD_SHIFT 26
+#define DPI_ATTR_MASK 0x03000000
+#define DPI_ATTR_SHIFT 24
+#define DPI_META_MASK 0x0000FFFF
+
+struct dpi_related {
+ __be32 dpi32;
+ __be32 ref;
+};
+
+/*
+ * CDB for GenQ command. In RAID Engine terminology, XOR is
+ * done through this command
+ */
+struct xor_cdb {
+ __be32 cdb32;
+ u8 gfm[16];
+ struct dpi_related dpi_dest_spec;
+ struct dpi_related dpi_src_spec[16];
+};
+
+/* CDB for no-op command */
+struct noop_cdb {
+ __be32 cdb32;
+};
+
+/*
+ * CDB for GenQQ command. In RAID Engine terminology, P/Q is
+ * done through this command
+ */
+struct pq_cdb {
+ __be32 cdb32;
+ u8 gfm_q1[16];
+ u8 gfm_q2[16];
+ struct dpi_related dpi_dest_spec[2];
+ struct dpi_related dpi_src_spec[16];
+};
+
+/* Compound frame */
+#define CF_ADDR_HIGH_MASK 0x000000FF
+#define CF_EXT_MASK 0x80000000
+#define CF_EXT_SHIFT 31
+#define CF_FINAL_MASK 0x40000000
+#define CF_FINAL_SHIFT 30
+#define CF_LENGTH_MASK 0x000FFFFF
+#define CF_BPID_MASK 0x00FF0000
+#define CF_BPID_SHIFT 16
+#define CF_OFFSET_MASK 0x00001FFF
+
+struct cmpnd_frame {
+ __be32 addr_high;
+ __be32 addr_low;
+ __be32 efrl32;
+ __be32 rbro32;
+};
+
+/* Frame descriptor */
+#define HWDESC_LIODN_MASK 0x3F000000
+#define HWDESC_LIODN_SHIFT 24
+#define HWDESC_BPID_MASK 0x00FF0000
+#define HWDESC_BPID_SHIFT 16
+#define HWDESC_ELIODN_MASK 0x0000F000
+#define HWDESC_ELIODN_SHIFT 12
+#define HWDESC_ADDR_HIGH_MASK 0x000000FF
+#define HWDESC_FMT_SHIFT 29
+#define HWDESC_FMT_MASK (0x3 << HWDESC_FMT_SHIFT)
+
+struct jr_hw_desc {
+ __be32 lbea32;
+ __be32 addr_low;
+ __be32 fmt32;
+ __be32 status;
+};
+
+/* Raid Engine device private data */
+struct re_drv_private {
+ u8 total_jrs;
+ struct dma_device dma_dev;
+ struct re_ctrl *re_regs;
+ struct re_jr *re_jrs[MAX_RE_JRS];
+ struct dma_pool *cf_desc_pool;
+ struct dma_pool *hw_desc_pool;
+};
+
+/* Per job ring data structure */
+struct re_jr {
+ char name[16];
+ spinlock_t desc_lock; /* queue lock */
+ struct list_head ack_q; /* wait to acked queue */
+ struct list_head active_q; /* already issued on hw, not completed */
+ struct list_head submit_q;
+ struct list_head free_q; /* alloc available queue */
+ struct device *dev;
+ struct re_drv_private *re_dev;
+ struct dma_chan chan;
+ struct jr_config_regs *jrregs;
+ int irq;
+ u32 alloc_count;
+
+ /* hw descriptor ring for inbound queue*/
+ dma_addr_t inb_phys_addr;
+ struct jr_hw_desc *inb_ring_virt_addr;
+ u32 inb_count;
+
+ /* hw descriptor ring for outbound queue */
+ dma_addr_t oub_phys_addr;
+ struct jr_hw_desc *oub_ring_virt_addr;
+ u32 oub_count;
+};
+
+/* Async transaction descriptor */
+struct fsl_re_dma_async_tx_desc {
+ struct dma_async_tx_descriptor async_tx;
+ struct list_head node;
+ struct jr_hw_desc hwdesc;
+ struct re_jr *jr;
+
+ /* hwdesc will point to cf_addr */
+ void *cf_addr;
+ dma_addr_t cf_paddr;
+
+ void *cdb_addr;
+ dma_addr_t cdb_paddr;
+ int status;
+};
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH v3 4/8] DMA: Freescale: add fsl_dma_free_descriptor() to reduce code duplication
From: Hongbo Zhang @ 2014-04-11 8:14 UTC (permalink / raw)
To: Andy Shevchenko
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397129361.11914.96.camel@smile.fi.intel.com>
On 04/10/2014 07:29 PM, Andy Shevchenko wrote:
> On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>
>> There are several places where descriptors are freed using identical code.
>> This patch puts this code into a function to reduce code duplication.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
>> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
>> ---
>> drivers/dma/fsldma.c | 30 ++++++++++++++++++------------
>> 1 file changed, 18 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
>> index b71cc04..b5a0ffa 100644
>> --- a/drivers/dma/fsldma.c
>> +++ b/drivers/dma/fsldma.c
>> @@ -418,6 +418,19 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
>> }
>>
>> /**
>> + * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
>> + * @chan : Freescale DMA channel
>> + * @desc: descriptor to be freed
>> + */
>> +static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
>> + struct fsl_desc_sw *desc)
>> +{
>> + list_del(&desc->node);
>> + chan_dbg(chan, "LD %p free\n", desc);
>> + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
>> +}
>> +
>> +/**
>> * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
>> * @chan : Freescale DMA channel
>> *
>> @@ -489,11 +502,8 @@ static void fsldma_free_desc_list(struct fsldma_chan *chan,
>> {
>> struct fsl_desc_sw *desc, *_desc;
>>
>> - list_for_each_entry_safe(desc, _desc, list, node) {
>> - list_del(&desc->node);
>> - chan_dbg(chan, "LD %p free\n", desc);
>> - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
>> - }
>> + list_for_each_entry_safe(desc, _desc, list, node)
>> + fsl_dma_free_descriptor(chan, desc);
>> }
>>
>> static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
>> @@ -501,11 +511,8 @@ static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
>> {
>> struct fsl_desc_sw *desc, *_desc;
>>
>> - list_for_each_entry_safe_reverse(desc, _desc, list, node) {
>> - list_del(&desc->node);
>> - chan_dbg(chan, "LD %p free\n", desc);
>> - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
>> - }
>> + list_for_each_entry_safe_reverse(desc, _desc, list, node)
>> + fsl_dma_free_descriptor(chan, desc);
>> }
>>
>> /**
>> @@ -819,8 +826,7 @@ static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
>> dma_run_dependencies(txd);
>>
>> dma_descriptor_unmap(txd);
>> - chan_dbg(chan, "LD %p free\n", desc);
>> - dma_pool_free(chan->desc_pool, desc, txd->phys);
>> + fsl_dma_free_descriptor(chan, desc);
> Here is no list_del() call since it's been called in dma_do_tasklet().
> What will be the result of double list_del() against the same node?
Not clear with your point.
This patch is only introducing a common fsl_dma_free_descriptor() to
reduce code duplication. And later in the patch 6/8 the
fsldma_cleanup_descriptor() is replaced by fsldma_cleanup_descriptorS().
>> }
>>
>> /**
>
^ permalink raw reply
* Re: [PATCH v3 6/8] DMA: Freescale: change descriptor release process for supporting async_tx
From: Hongbo Zhang @ 2014-04-11 8:00 UTC (permalink / raw)
To: Andy Shevchenko
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397131003.11914.108.camel@smile.fi.intel.com>
On 04/10/2014 07:56 PM, Andy Shevchenko wrote:
> On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>
>> Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
>> lack of support in current release process of dma descriptor, all descriptors
>> will be released whatever is acked or no-acked by async_tx, so there is a
>> potential race condition when dma engine is uesd by others clients (e.g. when
>> enable NET_DMA to offload TCP).
>>
>> In our case, a race condition which is raised when use both of talitos and
>> dmaengine to offload xor is because napi scheduler will sync all pending
>> requests in dma channels, it affects the process of raid operations due to
>> ack_tx is not checked in fsl dma. The no-acked descriptor is freed which is
>> submitted just now, as a dependent tx, this freed descriptor trigger
>> BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit().
>>
>> TASK = ee1a94a0[1390] 'md0_raid5' THREAD: ecf40000 CPU: 0
>> GPR00: 00000001 ecf41ca0 ee44/921a94a0 0000003f 00000001 c00593e4 00000000 00000001
>> GPR08: 00000000 a7a7a7a7 00000001 045/920000002 42028042 100a38d4 ed576d98 00000000
>> GPR16: ed5a11b0 00000000 2b162000 00000200 046/920000000 2d555000 ed3015e8 c15a7aa0
>> GPR24: 00000000 c155fc40 00000000 ecb63220 ecf41d28 e47/92f640bb0 ef640c30 ecf41ca0
>> NIP [c02b048c] async_tx_submit+0x6c/0x2b4
>> LR [c02b068c] async_tx_submit+0x26c/0x2b4
>> Call Trace:
>> [ecf41ca0] [c02b068c] async_tx_submit+0x26c/0x2b448/92 (unreliable)
>> [ecf41cd0] [c02b0a4c] async_memcpy+0x240/0x25c
>> [ecf41d20] [c0421064] async_copy_data+0xa0/0x17c
>> [ecf41d70] [c0421cf4] __raid_run_ops+0x874/0xe10
>> [ecf41df0] [c0426ee4] handle_stripe+0x820/0x25e8
>> [ecf41e90] [c0429080] raid5d+0x3d4/0x5b4
>> [ecf41f40] [c04329b8] md_thread+0x138/0x16c
>> [ecf41f90] [c008277c] kthread+0x8c/0x90
>> [ecf41ff0] [c0011630] kernel_thread+0x4c/0x68
>>
>> Another modification in this patch is the change of completed descriptors,
>> there is a potential risk which caused by exception interrupt, all descriptors
>> in ld_running list are seemed completed when an interrupt raised, it works fine
>> under normal condition, but if there is an exception occured, it cannot work as
>> our excepted. Hardware should not be depend on s/w list, the right way is to
>> read current descriptor address register to find the last completed descriptor.
>> If an interrupt is raised by an error, all descriptors in ld_running should not
>> be seemed finished, or these unfinished descriptors in ld_running will be
>> released wrongly.
>>
>> A simple way to reproduce:
>> Enable dmatest first, then insert some bad descriptors which can trigger
>> Programming Error interrupts before the good descriptors. Last, the good
>> descriptors will be freed before they are processsed because of the exception
>> intrerrupt.
>>
>> Note: the bad descriptors are only for simulating an exception interrupt. This
>> case can illustrate the potential risk in current fsl-dma very well.
>>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
>> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
>> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
>> ---
>> drivers/dma/fsldma.c | 195 ++++++++++++++++++++++++++++++++++++--------------
>> drivers/dma/fsldma.h | 17 ++++-
>> 2 files changed, 158 insertions(+), 54 deletions(-)
>>
>> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
>> index 968877f..f8eee60 100644
>> --- a/drivers/dma/fsldma.c
>> +++ b/drivers/dma/fsldma.c
>> @@ -459,6 +459,87 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
>> }
>>
>> /**
>> + * fsldma_clean_completed_descriptor - free all descriptors which
>> + * has been completed and acked
> IIRC the summary should be oneliner.
> Check the rest of the code as well.
I don't think so.
See this Documentation/kernel-doc-nano-HOWTO.txt, and you can find this
sentence "The short description following the subject can span multiple
lines"
>> + * @chan: Freescale DMA channel
>> + *
>> + * This function is used on all completed and acked descriptors.
>> + * All descriptors should only be freed in this function.
>> + */
>> +static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
>> +{
>> + struct fsl_desc_sw *desc, *_desc;
>> +
>> + /* Run the callback for each descriptor, in order */
>> + list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
>> + if (async_tx_test_ack(&desc->async_tx))
>> + fsl_dma_free_descriptor(chan, desc);
>> +}
>> +
>> +/**
>> + * fsldma_run_tx_complete_actions - cleanup a single link descriptor
>> + * @chan: Freescale DMA channel
>> + * @desc: descriptor to cleanup and free
>> + * @cookie: Freescale DMA transaction identifier
>> + *
>> + * This function is used on a descriptor which has been executed by the DMA
>> + * controller. It will run any callbacks, submit any dependencies.
>> + */
>> +static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
>> + struct fsl_desc_sw *desc, dma_cookie_t cookie)
> Maybe you could use cookie as local variable?
Yes.. it doesn't seem good to set a value to input parameter.
>> +{
>> + struct dma_async_tx_descriptor *txd = &desc->async_tx;
>> +
>> + BUG_ON(txd->cookie < 0);
>> +
>> + if (txd->cookie > 0) {
>> + cookie = txd->cookie;
>> +
>> + /* Run the link descriptor callback function */
>> + if (txd->callback) {
>> + chan_dbg(chan, "LD %p callback\n", desc);
>> + txd->callback(txd->callback_param);
>> + }
>> + }
>> +
>> + /* Run any dependencies */
>> + dma_run_dependencies(txd);
>> +
>> + return cookie;
>> +}
>> +
>> +/**
>> + * fsldma_clean_running_descriptor - move the completed descriptor from
>> + * ld_running to ld_completed
>> + * @chan: Freescale DMA channel
>> + * @desc: the descriptor which is completed
>> + *
>> + * Free the descriptor directly if acked by async_tx api, or move it to
>> + * queue ld_completed.
>> + */
>> +static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
>> + struct fsl_desc_sw *desc)
>> +{
>> + /* Remove from the list of transactions */
>> + list_del(&desc->node);
>> +
>> + /*
>> + * the client is allowed to attach dependent operations
> Capital letter first?
Better to do so, thanks.
>> + * until 'ack' is set
>> + */
>> + if (!async_tx_test_ack(&desc->async_tx)) {
>> + /*
>> + * Move this descriptor to the list of descriptors which is
>> + * completed, but still awaiting the 'ack' bit to be set.
>> + */
>> + list_add_tail(&desc->node, &chan->ld_completed);
>> + return;
>> + }
>> +
>> + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
>> +}
>> +
>> +/**
>> * fsl_chan_xfer_ld_queue - transfer any pending transactions
>> * @chan : Freescale DMA channel
>> *
>> @@ -526,30 +607,58 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
>> }
>>
>> /**
>> - * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
>> + * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
>> + * and move them to ld_completed to free until flag 'ack' is set
>> * @chan: Freescale DMA channel
>> - * @desc: descriptor to cleanup and free
>> *
>> - * This function is used on a descriptor which has been executed by the DMA
>> - * controller. It will run any callbacks, submit any dependencies, and then
>> - * free the descriptor.
>> + * This function is used on descriptors which have been executed by the DMA
>> + * controller. It will run any callbacks, submit any dependencies, then
>> + * free these descriptors if flag 'ack' is set.
>> */
>> -static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
>> - struct fsl_desc_sw *desc)
>> +static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
>> {
>> - struct dma_async_tx_descriptor *txd = &desc->async_tx;
>> + struct fsl_desc_sw *desc, *_desc;
>> + dma_cookie_t cookie = 0;
>> + dma_addr_t curr_phys = get_cdar(chan);
>> + int seen_current = 0;
>> +
>> + fsldma_clean_completed_descriptor(chan);
>> +
>> + /* Run the callback for each descriptor, in order */
>> + list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
>> + /*
>> + * do not advance past the current descriptor loaded into the
> Capital letter first.
>
>> + * hardware channel, subsequent descriptors are either in
>> + * process or have not been submitted
> Dot at the eol. Check in all comments.
Even though I saw there are other comments without the dots, I think it
is better to have it.
Thanks, all.
>
>> + */
>> + if (seen_current)
>> + break;
>> +
>> + /*
>> + * stop the search if we reach the current descriptor and the
>> + * channel is busy
>> + */
>> + if (desc->async_tx.phys == curr_phys) {
>> + seen_current = 1;
>> + if (!dma_is_idle(chan))
>> + break;
>> + }
>> +
>> + cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
>>
>> - /* Run the link descriptor callback function */
>> - if (txd->callback) {
>> - chan_dbg(chan, "LD %p callback\n", desc);
>> - txd->callback(txd->callback_param);
>> + fsldma_clean_running_descriptor(chan, desc);
>> }
>>
>> - /* Run any dependencies */
>> - dma_run_dependencies(txd);
>> + /*
>> + * Start any pending transactions automatically
> Dot at the end of the line.
>
>> + *
>> + * In the ideal case, we keep the DMA controller busy while we go
>> + * ahead and free the descriptors below.
>> + */
>> + fsl_chan_xfer_ld_queue(chan);
>>
>> - dma_descriptor_unmap(txd);
>> - fsl_dma_free_descriptor(chan, desc);
>> + if (cookie > 0)
>
>> + chan->common.completed_cookie = cookie;
>> }
>>
>> /**
>> @@ -620,8 +729,10 @@ static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
>>
>> chan_dbg(chan, "free all channel resources\n");
>> spin_lock_irqsave(&chan->desc_lock, flags);
>> + fsldma_cleanup_descriptors(chan);
>> fsldma_free_desc_list(chan, &chan->ld_pending);
>> fsldma_free_desc_list(chan, &chan->ld_running);
>> + fsldma_free_desc_list(chan, &chan->ld_completed);
>> spin_unlock_irqrestore(&chan->desc_lock, flags);
>>
>> dma_pool_destroy(chan->desc_pool);
>> @@ -859,6 +970,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
>> /* Remove and free all of the descriptors in the LD queue */
>> fsldma_free_desc_list(chan, &chan->ld_pending);
>> fsldma_free_desc_list(chan, &chan->ld_running);
>> + fsldma_free_desc_list(chan, &chan->ld_completed);
>> chan->idle = true;
>>
>> spin_unlock_irqrestore(&chan->desc_lock, flags);
>> @@ -918,6 +1030,17 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
>> dma_cookie_t cookie,
>> struct dma_tx_state *txstate)
>> {
>> + struct fsldma_chan *chan = to_fsl_chan(dchan);
>> + enum dma_status ret;
>> +
>> + ret = dma_cookie_status(dchan, cookie, txstate);
>> + if (ret == DMA_COMPLETE)
>> + return ret;
>> +
>> + spin_lock_bh(&chan->desc_lock);
>> + fsldma_cleanup_descriptors(chan);
>> + spin_unlock_bh(&chan->desc_lock);
>> +
>> return dma_cookie_status(dchan, cookie, txstate);
>> }
>>
>> @@ -995,52 +1118,19 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
>> static void dma_do_tasklet(unsigned long data)
>> {
>> struct fsldma_chan *chan = (struct fsldma_chan *)data;
>> - struct fsl_desc_sw *desc, *_desc;
>> - LIST_HEAD(ld_cleanup);
>> unsigned long flags;
>>
>> chan_dbg(chan, "tasklet entry\n");
>>
>> spin_lock_irqsave(&chan->desc_lock, flags);
>>
>> - /* update the cookie if we have some descriptors to cleanup */
>> - if (!list_empty(&chan->ld_running)) {
>> - dma_cookie_t cookie;
>> -
>> - desc = to_fsl_desc(chan->ld_running.prev);
>> - cookie = desc->async_tx.cookie;
>> - dma_cookie_complete(&desc->async_tx);
>> -
>> - chan_dbg(chan, "completed_cookie=%d\n", cookie);
>> - }
>> -
>> - /*
>> - * move the descriptors to a temporary list so we can drop the lock
>> - * during the entire cleanup operation
>> - */
>> - list_splice_tail_init(&chan->ld_running, &ld_cleanup);
>> -
>> /* the hardware is now idle and ready for more */
>> chan->idle = true;
>>
>> - /*
>> - * Start any pending transactions automatically
>> - *
>> - * In the ideal case, we keep the DMA controller busy while we go
>> - * ahead and free the descriptors below.
>> - */
>> - fsl_chan_xfer_ld_queue(chan);
>> - spin_unlock_irqrestore(&chan->desc_lock, flags);
>> + /* Run all cleanup for descriptors which have been completed */
>> + fsldma_cleanup_descriptors(chan);
>>
>> - /* Run the callback for each descriptor, in order */
>> - list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
>> -
>> - /* Remove from the list of transactions */
>> - list_del(&desc->node);
>> -
>> - /* Run all cleanup for this descriptor */
>> - fsldma_cleanup_descriptor(chan, desc);
>> - }
>> + spin_unlock_irqrestore(&chan->desc_lock, flags);
>>
>> chan_dbg(chan, "tasklet exit\n");
>> }
>> @@ -1224,6 +1314,7 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
>> spin_lock_init(&chan->desc_lock);
>> INIT_LIST_HEAD(&chan->ld_pending);
>> INIT_LIST_HEAD(&chan->ld_running);
>> + INIT_LIST_HEAD(&chan->ld_completed);
>> chan->idle = true;
>>
>> chan->common.device = &fdev->common;
>> diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
>> index d56e835..ec19517 100644
>> --- a/drivers/dma/fsldma.h
>> +++ b/drivers/dma/fsldma.h
>> @@ -138,8 +138,21 @@ struct fsldma_chan {
>> char name[8]; /* Channel name */
>> struct fsldma_chan_regs __iomem *regs;
>> spinlock_t desc_lock; /* Descriptor operation lock */
>> - struct list_head ld_pending; /* Link descriptors queue */
>> - struct list_head ld_running; /* Link descriptors queue */
>> + /*
>> + * Descriptors which are queued to run, but have not yet been
>> + * submitted to the hardware for execution
>> + */
>> + struct list_head ld_pending;
>> + /*
>> + * Descriptors which are currently being executed by the hardware
>> + */
>> + struct list_head ld_running;
>> + /*
>> + * Descriptors which have finished execution by the hardware. These
>> + * descriptors have already had their cleanup actions run. They are
>> + * waiting for the ACK bit to be set by the async_tx API.
>> + */
>> + struct list_head ld_completed; /* Link descriptors queue */
>> struct dma_chan common; /* DMA common channel */
>> struct dma_pool *desc_pool; /* Descriptors pool */
>> struct device *dev; /* Channel device */
>
^ permalink raw reply
* Re: [PATCH v3 8/8] DMA: Freescale: add suspend resume functions for DMA driver
From: Hongbo Zhang @ 2014-04-11 7:42 UTC (permalink / raw)
To: Andy Shevchenko
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397131557.11914.113.camel@smile.fi.intel.com>
On 04/10/2014 08:05 PM, Andy Shevchenko wrote:
> On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
>> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>>
>> This patch adds suspend resume functions for Freescale DMA driver.
>> .prepare callback is used to stop further descriptors from being added into the
>> pending queue, and also issue pending queues into execution if there is any.
>> .suspend callback makes sure all the pending jobs are cleaned up and all the
>> channels are idle, and save the mode registers.
>> .resume callback re-initializes the channels by restore the mode registers.
> Like we discussed with Vinod [1] the DMA controller drivers should go to
> suspend after users and come back before them.
>
> After you reconsider this point the patch logic might be modified a lot.
Looked through that discussions, I really had thought such problem for a
while.
For the dma-controller and dma-user, we don't know which .suspend
callback is executed firstly, so the idea would be: which ever is called
earlier, the dma-controller driver suspend function should be as robust
as possible.
It is better the dma-user .suspend callback is called earlier, some
clean-ups should be done here such as stop dma request, but we cannot
make sure every dma-user has a .suspend callback, some dma-users don't
pay attention to or even don't care the suspend at all for some reason.
So even the suspend_late is used, we cannot assume every dma-user's
activity is cleaned up neatly, dma-controller driver should be robust to
handle this gracefully, that was my design target.
In the prepare() function, clean up the pending queue and stop receive
new coming request, and in the suspend() function I do some register
saving works. I don't think my code needs to be modified much, a
possible change according to Vinod's idea would be:
use .suspend instead of my current .prepare
use . suspend_late instead of my current .suspend
e.g. postpone all my functions to be executed later, this method works
and seems better for client/low-level module drivers.
The reason I didn't use the above functions was that I had read this
Documentation/power/devices.txt, search the definitions of prepare,
suspend, suspend_late and suspend_noirq, I think my usage complies with
that definitions strictly, I can do the modification above if the
maintainer like and if nobody says I break this law.
> (Moreover, you abuse your own position to use only setters/getters to
> access to the DMAc registers)
My shame, I will update it.
(reason is the setters/getters patch isn't merged into our internal
tree, but this suspend patch has been done. I am trying to sync our
internal kernel and the community now)
> [1] http://www.spinics.net/lists/kernel/msg1650974.html
>
>
>> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
>> ---
>> drivers/dma/fsldma.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> drivers/dma/fsldma.h | 16 ++++++++
>> 2 files changed, 116 insertions(+)
>>
>> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
>> index c9bf54a..d6da222 100644
>> --- a/drivers/dma/fsldma.c
>> +++ b/drivers/dma/fsldma.c
>> @@ -400,6 +400,14 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
>>
>> spin_lock_bh(&chan->desc_lock);
>>
>> +#ifdef CONFIG_PM
>> + if (unlikely(chan->pm_state != RUNNING)) {
>> + chan_dbg(chan, "cannot submit due to suspend\n");
>> + spin_unlock_bh(&chan->desc_lock);
>> + return -1;
>> + }
>> +#endif
>> +
>> /*
>> * assign cookies to all of the software descriptors
>> * that make up this transaction
>> @@ -1311,6 +1319,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
>> INIT_LIST_HEAD(&chan->ld_running);
>> INIT_LIST_HEAD(&chan->ld_completed);
>> chan->idle = true;
>> +#ifdef CONFIG_PM
>> + chan->pm_state = RUNNING;
>> +#endif
>>
>> chan->common.device = &fdev->common;
>> dma_cookie_init(&chan->common);
>> @@ -1450,6 +1461,92 @@ static int fsldma_of_remove(struct platform_device *op)
>> return 0;
>> }
>>
>> +#ifdef CONFIG_PM
>> +static int fsldma_prepare(struct device *dev)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
>> + struct fsldma_chan *chan;
>> + int i;
>> +
>> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
>> + chan = fdev->chan[i];
>> + if (!chan)
>> + continue;
>> +
>> + spin_lock_bh(&chan->desc_lock);
>> + chan->pm_state = SUSPENDING;
>> + if (!list_empty(&chan->ld_pending))
>> + fsl_chan_xfer_ld_queue(chan);
>> + spin_unlock_bh(&chan->desc_lock);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int fsldma_suspend(struct device *dev)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
>> + struct fsldma_chan *chan;
>> + int i;
>> +
>> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
>> + chan = fdev->chan[i];
>> + if (!chan)
>> + continue;
>> +
>> + spin_lock_bh(&chan->desc_lock);
>> + if (!chan->idle)
>> + goto out;
>> + chan->regs_save.mr = DMA_IN(chan, &chan->regs->mr, 32);
>> + chan->pm_state = SUSPENDED;
>> + spin_unlock_bh(&chan->desc_lock);
>> + }
>> + return 0;
>> +
>> +out:
>> + for (; i >= 0; i--) {
>> + chan = fdev->chan[i];
>> + if (!chan)
>> + continue;
>> + chan->pm_state = RUNNING;
>> + spin_unlock_bh(&chan->desc_lock);
>> + }
>> + return -EBUSY;
>> +}
>> +
>> +static int fsldma_resume(struct device *dev)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
>> + struct fsldma_chan *chan;
>> + u32 mode;
>> + int i;
>> +
>> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
>> + chan = fdev->chan[i];
>> + if (!chan)
>> + continue;
>> +
>> + spin_lock_bh(&chan->desc_lock);
>> + mode = chan->regs_save.mr
>> + & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
>> + DMA_OUT(chan, &chan->regs->mr, mode, 32);
>> + chan->pm_state = RUNNING;
>> + spin_unlock_bh(&chan->desc_lock);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct dev_pm_ops fsldma_pm_ops = {
>> + .prepare = fsldma_prepare,
>> + .suspend = fsldma_suspend,
>> + .resume = fsldma_resume,
>> +};
>> +#endif
>> +
>> static const struct of_device_id fsldma_of_ids[] = {
>> { .compatible = "fsl,elo3-dma", },
>> { .compatible = "fsl,eloplus-dma", },
>> @@ -1462,6 +1559,9 @@ static struct platform_driver fsldma_of_driver = {
>> .name = "fsl-elo-dma",
>> .owner = THIS_MODULE,
>> .of_match_table = fsldma_of_ids,
>> +#ifdef CONFIG_PM
>> + .pm = &fsldma_pm_ops,
>> +#endif
>> },
>> .probe = fsldma_of_probe,
>> .remove = fsldma_of_remove,
>> diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
>> index ec19517..eecaf9e 100644
>> --- a/drivers/dma/fsldma.h
>> +++ b/drivers/dma/fsldma.h
>> @@ -134,6 +134,18 @@ struct fsldma_device {
>> #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
>> #define FSL_DMA_CHAN_START_EXT 0x00002000
>>
>> +#ifdef CONFIG_PM
>> +struct fsldma_chan_regs_save {
>> + u32 mr;
>> +};
>> +
>> +enum fsldma_pm_state {
>> + RUNNING = 0,
>> + SUSPENDING,
>> + SUSPENDED,
>> +};
>> +#endif
>> +
>> struct fsldma_chan {
>> char name[8]; /* Channel name */
>> struct fsldma_chan_regs __iomem *regs;
>> @@ -161,6 +173,10 @@ struct fsldma_chan {
>> struct tasklet_struct tasklet;
>> u32 feature;
>> bool idle; /* DMA controller is idle */
>> +#ifdef CONFIG_PM
>> + struct fsldma_chan_regs_save regs_save;
>> + enum fsldma_pm_state pm_state;
>> +#endif
>>
>> void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
>> void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
>
^ permalink raw reply
* Re: [PATCH 5/7] powerpc/ppc64: Do not turn AIL (reloc-on interrupts) too early
From: Michael Neuling @ 2014-04-11 6:52 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1395974192-820-5-git-send-email-benh@kernel.crashing.org>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> Turn them on at the same time as we allow MSR_IR/DR in the paca
> kernel MSR, ie, after the MMU has been setup enough to be able
> to handle relocated access to the linear mapping.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> arch/powerpc/kernel/cpu_setup_power.S | 2 --
> arch/powerpc/kernel/setup_64.c | 18 +++++++++++++++---
> 2 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index 37d1bb0..1557e7c 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -56,7 +56,6 @@ _GLOBAL(__setup_cpu_power8)
> li r0,0
> mtspr SPRN_LPID,r0
> mfspr r3,SPRN_LPCR
> - oris r3, r3, LPCR_AIL_3@h
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power8
> @@ -75,7 +74,6 @@ _GLOBAL(__restore_cpu_power8)
> li r0,0
> mtspr SPRN_LPID,r0
> mfspr r3,SPRN_LPCR
> - oris r3, r3, LPCR_AIL_3@h
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power8
BTW with this we can put the "mfspr r3,SPRN_LPCR" in __init_LPCR
and clean this code up bit.
Mikey
> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
> index 1d33e81..3d7a50a 100644
> --- a/arch/powerpc/kernel/setup_64.c
> +++ b/arch/powerpc/kernel/setup_64.c
> @@ -195,6 +195,18 @@ static void fixup_boot_paca(void)
> get_paca()->data_offset = 0;
> }
>
> +static void cpu_ready_for_interrupts(void)
> +{
> + /* Set IR and DR in PACA MSR */
> + get_paca()->kernel_msr = MSR_KERNEL;
> +
> + /* Enable AIL if supported */
> + if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
> + unsigned long lpcr = mfspr(SPRN_LPCR);
> + mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
> + }
> +}
> +
> /*
> * Early initialization entry point. This is called by head.S
> * with MMU translation disabled. We rely on the "feature" of
> @@ -264,9 +276,9 @@ void __init early_setup(unsigned long dt_ptr)
> /*
> * At this point, we can let interrupts switch to virtual mode
> * (the MMU has been setup), so adjust the MSR in the PACA to
> - * have IR and DR set.
> + * have IR and DR set and enable AIL if it exists
> */
> - get_paca()->kernel_msr = MSR_KERNEL;
> + cpu_ready_for_interrupts();
>
> /* Reserve large chunks of memory for use by CMA for KVM */
> kvm_cma_reserve();
> @@ -307,7 +319,7 @@ void early_setup_secondary(void)
> * (the MMU has been setup), so adjust the MSR in the PACA to
> * have IR and DR set.
> */
> - get_paca()->kernel_msr = MSR_KERNEL;
> + cpu_ready_for_interrupts();
> }
>
> #endif /* CONFIG_SMP */
> --
> 1.8.3.2
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH] powerpc: Don't try to set LPCR unless we're in hypervisor mode
From: Paul Mackerras @ 2014-04-11 6:43 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev
Commit 8f619b5429d9 ("powerpc/ppc64: Do not turn AIL (reloc-on
interrupts) too early") added code to set the AIL bit in the LPCR
without checking whether the kernel is running in hypervisor mode.
The result is that when the kernel is running as a guest (i.e.,
under PowerKVM or PowerVM), the processor takes a privileged
instruction interrupt at that point, causing a panic. The visible
result is that the kernel hangs after printing "returning from
prom_init".
This fixes it by checking for hypervisor mode being available
before setting LPCR. If we are not in hypervisor mode, we enable
relocation-on interrupts later in pSeries_setup_arch using the
H_SET_MODE hcall.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
Linus, Ben asked me to send this to you since he's about to be on
vacation, and this bug stops the kernel from booting under a
hypervisor on POWER8 machines. He would like it to go in before rc1.
arch/powerpc/kernel/setup_64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 3d7a50a..fbe2437 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -201,7 +201,8 @@ static void cpu_ready_for_interrupts(void)
get_paca()->kernel_msr = MSR_KERNEL;
/* Enable AIL if supported */
- if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
+ if (cpu_has_feature(CPU_FTR_HVMODE) &&
+ cpu_has_feature(CPU_FTR_ARCH_207S)) {
unsigned long lpcr = mfspr(SPRN_LPCR);
mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
}
--
1.9.rc1
^ permalink raw reply related
* Re: [PATCH v6] ASoC: fsl_sai: Add clock controls for SAI
From: Mark Brown @ 2014-04-10 22:36 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo, rob,
galak, shawn.guo, linuxppc-dev
In-Reply-To: <1397143575-10426-1-git-send-email-Guangyu.Chen@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 238 bytes --]
On Thu, Apr 10, 2014 at 11:26:15PM +0800, Nicolin Chen wrote:
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
Applied, thanks.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* [PATCH] hugetlb: ensure hugepage access is denied if hugepages are not supported
From: Nishanth Aravamudan @ 2014-04-10 23:07 UTC (permalink / raw)
To: Andrew Morton
Cc: linux-mm, Paul Mackerras, Aneesh Kumar K.V, Nadia Yvette Chambers,
linuxppc-dev, Mel Gorman, Anton Blanchard
In KVM guests on Power, in a guest not backed by hugepages, we see the
following:
AnonHugePages: 0 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 64 kB
HPAGE_SHIFT == 0 in this configuration, which indicates that hugepages
are not supported at boot-time, but this is only checked in
hugetlb_init(). Extract the check to a helper function, and use it in a
few relevant places.
Without this change, I am seeing the following when I `mount -t
hugetlbfs /none /dev/hugetlbfs`, and then simply do a `ls
/dev/hugetlbfs`. I think it's related to the fact that hugetlbfs is
properly not correctly setting itself up in this state?:
Unable to handle kernel paging request for data at address 0x00000031
Faulting instruction address: 0xc000000000245710
Oops: Kernel access of bad area, sig: 11 [#1]
SMP NR_CPUS=2048 NUMA pSeries
Modules linked in: pseries_rng rng_core virtio_net virtio_pci
virtio_ring virtio
CPU: 0 PID: 1807 Comm: ls Not tainted 3.14.0-rc7-00066-g774868c-dirty
task: c00000007e804520 ti: c00000007aed4000 task.ti: c00000007aed4000
NIP: c000000000245710 LR: c00000000024586c CTR: 0000000000000000
REGS: c00000007aed74f0 TRAP: 0300 Not tainted
+(3.14.0-rc7-00066-g774868c-dirty)
MSR: 8000000000009033 <SF,EE,ME,IR,DR,RI,LE> CR: 24002484 XER: 00000000
CFAR: 00003fff91037760 DAR: 0000000000000031 DSISR: 40000000 SOFTE: 1
GPR00: c00000000024586c c00000007aed7770 c000000000d85420 c00000007d7a0010
GPR04: c000000000abcf20 c000000000ed7c78 0000000000000020 c000000000cbc880
GPR08: 0000000000000000 0000000000000000 0000000080000000 0000000000000002
GPR12: 0000000044002484 c00000000fe40000 0000000000000000 00000000100232f0
GPR16: 0000000000000001 0000000000000000 0000000000000000 c00000007d794a40
GPR20: 0000000000000000 0000000000000024 c00000007a49a200 c00000007a2bd000
GPR24: c00000007aed7bb8 c00000007d7a0090 0000000000014800 0000000000000000
GPR28: c00000007d7a0010 c00000007a49a210 c00000007d7a0150 0000000000000001
NIP [c000000000245710] .time_out_leases+0x30/0x100
LR [c00000000024586c] .__break_lease+0x8c/0x480
Call Trace:
[c00000007aed7770] [c0000000002434c0] .lease_alloc+0x20/0xe0 (unreliable)
[c00000007aed77f0] [c00000000024586c] .__break_lease+0x8c/0x480
[c00000007aed78e0] [c0000000001e0374] .do_dentry_open.isra.14+0xf4/0x370
[c00000007aed7980] [c0000000001e0624] .finish_open+0x34/0x60
[c00000007aed7a00] [c0000000001f519c] .do_last+0x56c/0xe40
[c00000007aed7b20] [c0000000001f5b68] .path_openat+0xf8/0x800
[c00000007aed7c40] [c0000000001f7810] .do_filp_open+0x40/0xb0
[c00000007aed7d70] [c0000000001e1f08] .do_sys_open+0x198/0x2e0
[c00000007aed7e30] [c00000000000a158] syscall_exit+0x0/0x98
Additionally, using hugepages in such guests eventually crashes the
guest kerenl, as hugepages aren't actually supported and we end up
corrupting various lists in the core MM.
This does make hugetlbfs not supported in this environment. I believe
this is fine, as there are no valid hugepages and that won't change at
runtime.
Signed-off-by: Nishanth Aravamudan <nacc@linux.vnet.ibm.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Acked-by: Mel Gorman <mgorman@suse.de>
---
v1 -> v2: removed RFC
v2 -> v3: updated changelog to include hugetlbfs crash and other error
information, change hugetlbfs printk to KERN_INFO
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index 2040275..ea8d677 100644
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
@@ -1030,6 +1030,11 @@ static int __init init_hugetlbfs_fs(void)
int error;
int i;
+ if (!hugepages_supported()) {
+ printk(KERN_INFO "hugetlbfs: Disabling because there are no supported hugepage sizes\n");
+ return -ENOTSUPP;
+ }
+
error = bdi_init(&hugetlbfs_backing_dev_info);
if (error)
return error;
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 5b337cf..b0f0a1c 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -460,4 +460,14 @@ static inline spinlock_t *huge_pte_lock(struct hstate *h,
return ptl;
}
+static inline bool hugepages_supported(void)
+{
+ /*
+ * Some platform decide whether they support huge pages at boot
+ * time. On these, such as powerpc, HPAGE_SHIFT is set to 0 when
+ * there is no such support
+ */
+ return HPAGE_SHIFT != 0;
+}
+
#endif /* _LINUX_HUGETLB_H */
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index dd30f22..fd43528 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -1980,11 +1980,7 @@ static int __init hugetlb_init(void)
{
int i;
- /* Some platform decide whether they support huge pages at boot
- * time. On these, such as powerpc, HPAGE_SHIFT is set to 0 when
- * there is no such support
- */
- if (HPAGE_SHIFT == 0)
+ if (!hugepages_supported())
return 0;
if (!size_to_hstate(default_hstate_size)) {
@@ -2111,6 +2107,9 @@ static int hugetlb_sysctl_handler_common(bool obey_mempolicy,
unsigned long tmp;
int ret;
+ if (!hugepages_supported())
+ return -ENOTSUPP;
+
tmp = h->max_huge_pages;
if (write && h->order >= MAX_ORDER)
@@ -2164,6 +2163,9 @@ int hugetlb_overcommit_handler(struct ctl_table *table, int write,
unsigned long tmp;
int ret;
+ if (!hugepages_supported())
+ return -ENOTSUPP;
+
tmp = h->nr_overcommit_huge_pages;
if (write && h->order >= MAX_ORDER)
@@ -2189,6 +2191,8 @@ out:
void hugetlb_report_meminfo(struct seq_file *m)
{
struct hstate *h = &default_hstate;
+ if (!hugepages_supported())
+ return;
seq_printf(m,
"HugePages_Total: %5lu\n"
"HugePages_Free: %5lu\n"
@@ -2205,6 +2209,8 @@ void hugetlb_report_meminfo(struct seq_file *m)
int hugetlb_report_node_meminfo(int nid, char *buf)
{
struct hstate *h = &default_hstate;
+ if (!hugepages_supported())
+ return 0;
return sprintf(buf,
"Node %d HugePages_Total: %5u\n"
"Node %d HugePages_Free: %5u\n"
@@ -2219,6 +2225,9 @@ void hugetlb_show_meminfo(void)
struct hstate *h;
int nid;
+ if (!hugepages_supported())
+ return;
+
for_each_node_state(nid, N_MEMORY)
for_each_hstate(h)
pr_info("Node %d hugepages_total=%u hugepages_free=%u hugepages_surp=%u hugepages_size=%lukB\n",
^ permalink raw reply related
* Re: [PATCH] Fix 3bc95598 'powerpc/PCI: Use list_for_each_entry() for bus traversal'
From: Benjamin Herrenschmidt @ 2014-04-10 20:55 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Yijing Wang, linuxppc-dev, Mike Qiu, anton, paulus@samba.org
In-Reply-To: <CAErSpo6U7W+Nph3kCOBXcBTN7SeR9pVc5cfdQKTBDedWNnV8jg@mail.gmail.com>
On Thu, 2014-04-10 at 09:27 -0600, Bjorn Helgaas wrote:
> Ben, I'll pick this up for v3.15 since the original change
> (3bc955987fb3) went through my tree, unless you want to handle it.
Nah, go for it, I'm about to go on vacation for a week :-)
Thanks !
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] gpio: ge: Convert to platform driver
From: Alexander Shiyan @ 2014-04-10 16:37 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-gpio@vger.kernel.org, linuxppc-dev@lists.ozlabs.org list,
Alexandre Courbot
In-Reply-To: <CACRpkdZMabAQuribdmt=bK_1RF1_oSOeiEquXAuxyq3adtE8-g@mail.gmail.com>
VGh1LCAxMCBBcHIgMjAxNCAxODozMDoxNiArMDIwMCDQvtGCIExpbnVzIFdhbGxlaWogPGxpbnVz
LndhbGxlaWpAbGluYXJvLm9yZz46Cj4gT24gU3VuLCBNYXIgMzAsIDIwMTQgYXQgNzoxNCBBTSwg
QWxleGFuZGVyIFNoaXlhbiA8c2hjX3dvcmtAbWFpbC5ydT4gd3JvdGU6Cj4gCj4gPiBUaGlzIHBh
dGNoIGNvbnZlcnRzIEdFIEkvTyBGUEdBIEdQSU8gZHJpdmVyIHRvIHBsYXRmb3JtIGRyaXZlci4K
PiA+Cj4gPiBTaWduZWQtb2ZmLWJ5OiBBbGV4YW5kZXIgU2hpeWFuIDxzaGNfd29ya0BtYWlsLnJ1
Pgo+ID4gLS0tCj4gPiBPbmx5IGNvbXBpbGUgdGVzdGVkLgo+IAo+IElzbid0IGl0IG5lY2Vzc2Fy
eSB0byBhbHNvIHBhdGNoIGFmZmVjdGVkIHBsYXRmb3JtcyB0byBhZGQgdGhpcwo+IGRldmljZSBl
aXRoZXIgYXMgcGxhdGZvcm0gZGV2aWNlIG9yIGluIHRoZWlyIGRldmljZSB0cmVlcz8KClRoZSBk
ZXZpY2UgaXMgYWxyZWFkeSBpbiB0aGUgdHJlZSwgYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL2dlKi5k
dHMgZm9yIGV4YW1wbGUuCkluIGFueSBjYXNlLCBhcyBJIGhhdmUgc2FpZCwgSSB3aWxsIGRvIGEg
c2Vjb25kIHZlcnNpb24sIGFzIHRoaXMgY29udGFpbnMgc29tZQppbmNvbnNpc3RlbmNpZXMuCgot
LS0KCg==
^ permalink raw reply
* Re: [PATCH] gpio: ge: Convert to platform driver
From: Linus Walleij @ 2014-04-10 16:30 UTC (permalink / raw)
To: Alexander Shiyan
Cc: linux-gpio@vger.kernel.org, linuxppc-dev@lists.ozlabs.org list,
Alexandre Courbot
In-Reply-To: <1396156455-4225-1-git-send-email-shc_work@mail.ru>
On Sun, Mar 30, 2014 at 7:14 AM, Alexander Shiyan <shc_work@mail.ru> wrote:
> This patch converts GE I/O FPGA GPIO driver to platform driver.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
> ---
> Only compile tested.
Isn't it necessary to also patch affected platforms to add this
device either as platform device or in their device trees?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] Fix 3bc95598 'powerpc/PCI: Use list_for_each_entry() for bus traversal'
From: Bjorn Helgaas @ 2014-04-10 15:27 UTC (permalink / raw)
To: Mike Qiu; +Cc: Yijing Wang, linuxppc-dev, anton, paulus@samba.org
In-Reply-To: <1397112695-3945-1-git-send-email-qiudayu@linux.vnet.ibm.com>
On Thu, Apr 10, 2014 at 12:51 AM, Mike Qiu <qiudayu@linux.vnet.ibm.com> wrote:
> Unable to handle kernel paging request for data at address 0x00000000
> Faulting instruction address: 0xc000000000041d78
> Oops: Kernel access of bad area, sig: 11 [#1]
> ...
> NIP [c000000000041d78] .sys_pciconfig_iobase+0x68/0x1f0
> LR [c000000000041e0c] .sys_pciconfig_iobase+0xfc/0x1f0
> Call Trace:
> [c0000003b4787db0] [c000000000041e0c] .sys_pciconfig_iobase+0xfc/0x1f0 (unreliable)
> [c0000003b4787e30] [c000000000009ed8] syscall_exit+0x0/0x98
>
> This bug was introduced by commit 3bc955987fb377f3c95bc29deb498e96819b8451
> The root cause was the 'bus' has been set to null while try to access
> bus->next.
>
> Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/pci_64.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
> index 2a47790..7b6c1ae 100644
> --- a/arch/powerpc/kernel/pci_64.c
> +++ b/arch/powerpc/kernel/pci_64.c
> @@ -209,6 +209,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
> {
> struct pci_controller* hose;
> struct pci_bus *bus = NULL;
> + struct pci_bus *tmp_bus = NULL;
> struct device_node *hose_node;
>
> /* Argh ! Please forgive me for that hack, but that's the
> @@ -229,10 +230,12 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
> * used on pre-domains setup. We return the first match
> */
>
> - list_for_each_entry(bus, &pci_root_buses, node) {
> - if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
> + list_for_each_entry(tmp_bus, &pci_root_buses, node) {
> + if (in_bus >= tmp_bus->number &&
> + in_bus <= tmp_bus->busn_res.end) {
> + bus = tmp_bus;
> break;
> - bus = NULL;
> + }
Good fix, thanks. Sorry we didn't catch it before you tripped over
it. Your code is much cleaner than the previous "clear out 'bus' if
we didn't match" style.
Nit: I don't think you need to initialize tmp_bus to NULL.
Ben, I'll pick this up for v3.15 since the original change
(3bc955987fb3) went through my tree, unless you want to handle it.
Bjorn
> }
> if (bus == NULL || bus->dev.of_node == NULL)
> return -ENODEV;
> --
> 1.8.0.1
>
^ permalink raw reply
* [PATCH v6] ASoC: fsl_sai: Add clock controls for SAI
From: Nicolin Chen @ 2014-04-10 15:26 UTC (permalink / raw)
To: broonie
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo, rob,
galak, shawn.guo, linuxppc-dev
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
---
Changelog
v6:
* Dropped the dtsi change since it's no more demanded with this patch.
* Removed Shawn's ACK since we no long change dtsi in this case.
v5:
* Dropped mclk preparing and enabling since we are not using them currecntly.
* Made the change compatible to the old DTB.
* Added returned error value print.
v4:
* Merged into single patch.
* Fixed bus clock ID on vf610.
v3:
* Use int type for ret instead of u32.
* Added Acked-by and Tested-by from Xiubo Li.
v2:
* Appended two extra mclks to the driver since SAI actually has three.
* Renamed clock name to 'bus' and 'mclk' according to the reference manual.
.../devicetree/bindings/sound/fsl-sai.txt | 9 +++--
sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++--
sound/soc/fsl/fsl_sai.h | 4 +++
3 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 35c09fe..0f4e238 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -10,7 +10,8 @@ Required properties:
- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
- reg: Offset and length of the register set for the device.
- clocks: Must contain an entry for each entry in clock-names.
-- clock-names : Must include the "sai" entry.
+- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
+ "mclk3" for bit clock and frame clock providing.
- dmas : Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names : Two dmas have to be defined, "tx" and "rx".
@@ -30,8 +31,10 @@ sai2: sai@40031000 {
reg = <0x40031000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2_1>;
- clocks = <&clks VF610_CLK_SAI2>;
- clock-names = "sai";
+ clocks = <&clks VF610_CLK_PLATFORM_BUS>,
+ <&clks VF610_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index db9f75e..5fff2e1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -401,7 +401,15 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ struct device *dev = &sai->pdev->dev;
u32 reg;
+ int ret;
+
+ ret = clk_prepare_enable(sai->bus_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable bus clock: %d\n", ret);
+ return ret;
+ }
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = FSL_SAI_TCR3;
@@ -427,6 +435,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
~FSL_SAI_CR3_TRCE);
+
+ clk_disable_unprepare(sai->bus_clk);
}
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
@@ -559,7 +569,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
struct fsl_sai *sai;
struct resource *res;
void __iomem *base;
- int irq, ret;
+ char tmp[8];
+ int irq, ret, i;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
@@ -582,12 +593,35 @@ static int fsl_sai_probe(struct platform_device *pdev)
return PTR_ERR(base);
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
- "sai", base, &fsl_sai_regmap_config);
+ "bus", base, &fsl_sai_regmap_config);
+
+ /* Compatible with old DTB cases */
+ if (IS_ERR(sai->regmap))
+ sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "sai", base, &fsl_sai_regmap_config);
if (IS_ERR(sai->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(sai->regmap);
}
+ /* No error out for old DTB cases but only mark the clock NULL */
+ sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(sai->bus_clk)) {
+ dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
+ PTR_ERR(sai->bus_clk));
+ sai->bus_clk = NULL;
+ }
+
+ for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
+ sprintf(tmp, "mclk%d", i + 1);
+ sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(sai->mclk_clk[i])) {
+ dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
+ i + 1, PTR_ERR(sai->mclk_clk[i]));
+ sai->mclk_clk[i] = NULL;
+ }
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 677670d..0e6c9f5 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -119,6 +119,8 @@
#define FSL_SAI_CLK_MAST2 2
#define FSL_SAI_CLK_MAST3 3
+#define FSL_SAI_MCLK_MAX 3
+
/* SAI data transfer numbers per DMA request */
#define FSL_SAI_MAXBURST_TX 6
#define FSL_SAI_MAXBURST_RX 6
@@ -126,6 +128,8 @@
struct fsl_sai {
struct platform_device *pdev;
struct regmap *regmap;
+ struct clk *bus_clk;
+ struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_regs;
bool big_endian_data;
--
1.8.4
^ permalink raw reply related
* [PATCH v6] ASoC: fsl_sai: Add clock controls for SAI
From: Nicolin Chen @ 2014-04-10 15:18 UTC (permalink / raw)
To: broonie
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo, rob,
galak, shawn.guo, linuxppc-dev
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
---
Changelog
v6:
* Dropped the dtsi change since it's no more demanded with this patch.
* Removed Shawn's ACK since we no long change dtsi in this case.
v5:
* Dropped mclk preparing and enabling since we are not using them currecntly.
* Made the change compatible to the old DTB.
* Added returned error value print.
v4:
* Merged into single patch.
* Fixed bus clock ID on vf610.
v3:
* Use int type for ret instead of u32.
* Added Acked-by and Tested-by from Xiubo Li.
v2:
* Appended two extra mclks to the driver since SAI actually has three.
* Renamed clock name to 'bus' and 'mclk' according to the reference manual.
.../devicetree/bindings/sound/fsl-sai.txt | 9 +++--
sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++--
sound/soc/fsl/fsl_sai.h | 4 +++
3 files changed, 46 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 35c09fe..0f4e238 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -10,7 +10,8 @@ Required properties:
- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
- reg: Offset and length of the register set for the device.
- clocks: Must contain an entry for each entry in clock-names.
-- clock-names : Must include the "sai" entry.
+- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
+ "mclk3" for bit clock and frame clock providing.
- dmas : Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names : Two dmas have to be defined, "tx" and "rx".
@@ -30,8 +31,10 @@ sai2: sai@40031000 {
reg = <0x40031000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2_1>;
- clocks = <&clks VF610_CLK_SAI2>;
- clock-names = "sai";
+ clocks = <&clks VF610_CLK_PLATFORM_BUS>,
+ <&clks VF610_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index db9f75e..5fff2e1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -401,7 +401,15 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ struct device *dev = &sai->pdev->dev;
u32 reg;
+ int ret;
+
+ ret = clk_prepare_enable(sai->bus_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable bus clock: %d\n", ret);
+ return ret;
+ }
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = FSL_SAI_TCR3;
@@ -427,6 +435,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
~FSL_SAI_CR3_TRCE);
+
+ clk_disable_unprepare(sai->bus_clk);
}
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
@@ -559,7 +569,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
struct fsl_sai *sai;
struct resource *res;
void __iomem *base;
- int irq, ret;
+ char tmp[8];
+ int irq, ret, i;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
@@ -582,12 +593,35 @@ static int fsl_sai_probe(struct platform_device *pdev)
return PTR_ERR(base);
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
- "sai", base, &fsl_sai_regmap_config);
+ "bus", base, &fsl_sai_regmap_config);
+
+ /* Compatible with old DTB cases */
+ if (IS_ERR(sai->regmap))
+ sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "sai", base, &fsl_sai_regmap_config);
if (IS_ERR(sai->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(sai->regmap);
}
+ /* No error out for old DTB cases but only mark the clock NULL */
+ sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(sai->bus_clk)) {
+ dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
+ PTR_ERR(sai->bus_clk));
+ sai->bus_clk = NULL;
+ }
+
+ for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
+ sprintf(tmp, "mclk%d", i + 1);
+ sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(sai->mclk_clk[i])) {
+ dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
+ i + 1, PTR_ERR(sai->mclk_clk[i]));
+ sai->mclk_clk[i] = NULL;
+ }
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 677670d..0e6c9f5 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -119,6 +119,8 @@
#define FSL_SAI_CLK_MAST2 2
#define FSL_SAI_CLK_MAST3 3
+#define FSL_SAI_MCLK_MAX 3
+
/* SAI data transfer numbers per DMA request */
#define FSL_SAI_MAXBURST_TX 6
#define FSL_SAI_MAXBURST_RX 6
@@ -126,6 +128,8 @@
struct fsl_sai {
struct platform_device *pdev;
struct regmap *regmap;
+ struct clk *bus_clk;
+ struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_regs;
bool big_endian_data;
--
1.8.4
^ permalink raw reply related
* Re: [PATCH v3 2/3] devcietree: bindings: add some MFD Keymile FPGAs
From: Rob Herring @ 2014-04-10 15:06 UTC (permalink / raw)
To: Scott Wood; +Cc: Valentin Longchamp, linuxppc-dev, devicetree@vger.kernel.org
In-Reply-To: <1397004291.32034.327.camel@snotra.buserror.net>
On Tue, Apr 8, 2014 at 7:44 PM, Scott Wood <scottwood@freescale.com> wrote:
> On Tue, 2014-03-25 at 14:41 +0100, Valentin Longchamp wrote:
>> These are the bindings for 2 MFD devices used on some of the Keymile boards.
>> The first one is the chassis managmenet bfticu FPGA.
>> The second one is the board controller (reset, LEDs, GPIOs) QRIO CPDL.
>> These FPGAs are used in the kmcoge4 board.
>>
>> This patch also add KEYMILE to the vendor-prefixes.
You can drop the keymile addition. I have that queued up.
[snip]
>> +Required properties:
>> +- compatible: "keymile,bfticu"
>> +- interrupt-controller: the bfticu FPGA is an interrupt controller
>> +- interrupts: the main IRQ line to signal the collected IRQs
>> +- #interrupt-cells : is 2
>> + - The 1st cell is the local IRQ number on the bfticu
>> + - The 2nd cell is the type of the IRQ (IRQ_TYPE_xxx)
>
> Device tree bindings should not depend on the content of Linux headers.
> One is stable ABI, and the other isn't.
>
> If you want you can make the values the same for convenience, as is done
> by IPIC, CPM PIC, etc -- but the values need to be explicitly stated in
> the binding. It'll still break if the Linux values change (so it may
> not be a good idea to try to keep the values the same), but at least the
> fix would be in Linux code rather than an ABI change.
You can simply refer to
Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
Rob
^ permalink raw reply
* Re: [PATCH v5] ASoC: fsl_sai: Add clock controls for SAI
From: Nicolin Chen @ 2014-04-10 14:39 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
broonie, ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo,
rob, galak, linuxppc-dev
In-Reply-To: <20140410140745.GE28420@dragon>
On Thu, Apr 10, 2014 at 10:07:47PM +0800, Shawn Guo wrote:
> On Thu, Apr 10, 2014 at 07:23:12PM +0800, Nicolin Chen wrote:
> > The SAI mainly has the following clocks:
> > bus clock
> > control and configure registers and to generate synchronous
> > interrupts and DMA requests.
> >
> > mclk1, mclk2, mclk3
> > to generate the bit clock when the receiver or transmitter is
> > configured for an internally generated bit clock.
> >
> > So this patch adds these clocks and their clock controls to the driver,
> > meanwhile, corrects the existing DTS accordingly so those platforms can
> > benifit from the further feature with different clock sources.
> >
> > [ To concern the old DTB cases, I've added a bit of extra code to make
> > the driver compatible with them. And by marking clock NULL if failed
> > to get, the clk_prepare() or clk_get_rate() would easily return 0
> > so no further path should be broken. -- by Nicolin ]
>
> In this case, the arch/arm/boot/dts/vf610.dtsi can just go via IMX tree,
> since nothing should be broken on sound tree even without dts change?
You are right...I'll send the v6.
Thank you,
Nicolin
----
>
> Shawn
>
> >
> > Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
> > Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
> > Acked-by: Shawn Guo <shawn.guo@linaro.org>
> > ---
> >
> > Changelog
> > v5:
> > * Dropped mclk preparing and enabling since we are not using them currecntly.
> > * Made the change compatible to the old DTB.
> > * Added returned error value print.
> > v4:
> > * Merged into single patch.
> > * Fixed bus clock ID on vf610.
> > v3:
> > * Use int type for ret instead of u32.
> > * Added Acked-by and Tested-by from Xiubo Li.
> > v2:
> > * Appended two extra mclks to the driver since SAI actually has three.
> > * Renamed clock name to 'bus' and 'mclk' according to the reference manual.
> >
> > .../devicetree/bindings/sound/fsl-sai.txt | 9 +++--
> > arch/arm/boot/dts/vf610.dtsi | 6 ++--
> > sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++--
> > sound/soc/fsl/fsl_sai.h | 4 +++
> > 4 files changed, 50 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> > index 35c09fe..0f4e238 100644
> > --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
> > +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> > @@ -10,7 +10,8 @@ Required properties:
> > - compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
> > - reg: Offset and length of the register set for the device.
> > - clocks: Must contain an entry for each entry in clock-names.
> > -- clock-names : Must include the "sai" entry.
> > +- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
> > + "mclk3" for bit clock and frame clock providing.
> > - dmas : Generic dma devicetree binding as described in
> > Documentation/devicetree/bindings/dma/dma.txt.
> > - dma-names : Two dmas have to be defined, "tx" and "rx".
> > @@ -30,8 +31,10 @@ sai2: sai@40031000 {
> > reg = <0x40031000 0x1000>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_sai2_1>;
> > - clocks = <&clks VF610_CLK_SAI2>;
> > - clock-names = "sai";
> > + clocks = <&clks VF610_CLK_PLATFORM_BUS>,
> > + <&clks VF610_CLK_SAI2>,
> > + <&clks 0>, <&clks 0>;
> > + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> > dma-names = "tx", "rx";
> > dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
> > <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
> > diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
> > index d31ce1b..4c3cd59 100644
> > --- a/arch/arm/boot/dts/vf610.dtsi
> > +++ b/arch/arm/boot/dts/vf610.dtsi
> > @@ -139,8 +139,10 @@
> > compatible = "fsl,vf610-sai";
> > reg = <0x40031000 0x1000>;
> > interrupts = <0 86 0x04>;
> > - clocks = <&clks VF610_CLK_SAI2>;
> > - clock-names = "sai";
> > + clocks = <&clks VF610_CLK_PLATFORM_BUS>,
> > + <&clks VF610_CLK_SAI2>,
> > + <&clks 0>, <&clks 0>;
> > + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> > status = "disabled";
> > };
> >
> > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> > index db9f75e..5fff2e1 100644
> > --- a/sound/soc/fsl/fsl_sai.c
> > +++ b/sound/soc/fsl/fsl_sai.c
> > @@ -401,7 +401,15 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
> > struct snd_soc_dai *cpu_dai)
> > {
> > struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
> > + struct device *dev = &sai->pdev->dev;
> > u32 reg;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(sai->bus_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to enable bus clock: %d\n", ret);
> > + return ret;
> > + }
> >
> > if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> > reg = FSL_SAI_TCR3;
> > @@ -427,6 +435,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
> >
> > regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
> > ~FSL_SAI_CR3_TRCE);
> > +
> > + clk_disable_unprepare(sai->bus_clk);
> > }
> >
> > static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
> > @@ -559,7 +569,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
> > struct fsl_sai *sai;
> > struct resource *res;
> > void __iomem *base;
> > - int irq, ret;
> > + char tmp[8];
> > + int irq, ret, i;
> >
> > sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
> > if (!sai)
> > @@ -582,12 +593,35 @@ static int fsl_sai_probe(struct platform_device *pdev)
> > return PTR_ERR(base);
> >
> > sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> > - "sai", base, &fsl_sai_regmap_config);
> > + "bus", base, &fsl_sai_regmap_config);
> > +
> > + /* Compatible with old DTB cases */
> > + if (IS_ERR(sai->regmap))
> > + sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> > + "sai", base, &fsl_sai_regmap_config);
> > if (IS_ERR(sai->regmap)) {
> > dev_err(&pdev->dev, "regmap init failed\n");
> > return PTR_ERR(sai->regmap);
> > }
> >
> > + /* No error out for old DTB cases but only mark the clock NULL */
> > + sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
> > + if (IS_ERR(sai->bus_clk)) {
> > + dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
> > + PTR_ERR(sai->bus_clk));
> > + sai->bus_clk = NULL;
> > + }
> > +
> > + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
> > + sprintf(tmp, "mclk%d", i + 1);
> > + sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
> > + if (IS_ERR(sai->mclk_clk[i])) {
> > + dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
> > + i + 1, PTR_ERR(sai->mclk_clk[i]));
> > + sai->mclk_clk[i] = NULL;
> > + }
> > + }
> > +
> > irq = platform_get_irq(pdev, 0);
> > if (irq < 0) {
> > dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> > diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
> > index 677670d..0e6c9f5 100644
> > --- a/sound/soc/fsl/fsl_sai.h
> > +++ b/sound/soc/fsl/fsl_sai.h
> > @@ -119,6 +119,8 @@
> > #define FSL_SAI_CLK_MAST2 2
> > #define FSL_SAI_CLK_MAST3 3
> >
> > +#define FSL_SAI_MCLK_MAX 3
> > +
> > /* SAI data transfer numbers per DMA request */
> > #define FSL_SAI_MAXBURST_TX 6
> > #define FSL_SAI_MAXBURST_RX 6
> > @@ -126,6 +128,8 @@
> > struct fsl_sai {
> > struct platform_device *pdev;
> > struct regmap *regmap;
> > + struct clk *bus_clk;
> > + struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
> >
> > bool big_endian_regs;
> > bool big_endian_data;
> > --
> > 1.8.4
> >
> >
>
^ permalink raw reply
* Re: [PATCH v5] ASoC: fsl_sai: Add clock controls for SAI
From: Shawn Guo @ 2014-04-10 14:07 UTC (permalink / raw)
To: Nicolin Chen
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
broonie, ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo,
rob, galak, linuxppc-dev
In-Reply-To: <1397128992-3609-1-git-send-email-Guangyu.Chen@freescale.com>
On Thu, Apr 10, 2014 at 07:23:12PM +0800, Nicolin Chen wrote:
> The SAI mainly has the following clocks:
> bus clock
> control and configure registers and to generate synchronous
> interrupts and DMA requests.
>
> mclk1, mclk2, mclk3
> to generate the bit clock when the receiver or transmitter is
> configured for an internally generated bit clock.
>
> So this patch adds these clocks and their clock controls to the driver,
> meanwhile, corrects the existing DTS accordingly so those platforms can
> benifit from the further feature with different clock sources.
>
> [ To concern the old DTB cases, I've added a bit of extra code to make
> the driver compatible with them. And by marking clock NULL if failed
> to get, the clk_prepare() or clk_get_rate() would easily return 0
> so no further path should be broken. -- by Nicolin ]
In this case, the arch/arm/boot/dts/vf610.dtsi can just go via IMX tree,
since nothing should be broken on sound tree even without dts change?
Shawn
>
> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
> Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
> Acked-by: Shawn Guo <shawn.guo@linaro.org>
> ---
>
> Changelog
> v5:
> * Dropped mclk preparing and enabling since we are not using them currecntly.
> * Made the change compatible to the old DTB.
> * Added returned error value print.
> v4:
> * Merged into single patch.
> * Fixed bus clock ID on vf610.
> v3:
> * Use int type for ret instead of u32.
> * Added Acked-by and Tested-by from Xiubo Li.
> v2:
> * Appended two extra mclks to the driver since SAI actually has three.
> * Renamed clock name to 'bus' and 'mclk' according to the reference manual.
>
> .../devicetree/bindings/sound/fsl-sai.txt | 9 +++--
> arch/arm/boot/dts/vf610.dtsi | 6 ++--
> sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++--
> sound/soc/fsl/fsl_sai.h | 4 +++
> 4 files changed, 50 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> index 35c09fe..0f4e238 100644
> --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
> @@ -10,7 +10,8 @@ Required properties:
> - compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
> - reg: Offset and length of the register set for the device.
> - clocks: Must contain an entry for each entry in clock-names.
> -- clock-names : Must include the "sai" entry.
> +- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
> + "mclk3" for bit clock and frame clock providing.
> - dmas : Generic dma devicetree binding as described in
> Documentation/devicetree/bindings/dma/dma.txt.
> - dma-names : Two dmas have to be defined, "tx" and "rx".
> @@ -30,8 +31,10 @@ sai2: sai@40031000 {
> reg = <0x40031000 0x1000>;
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_sai2_1>;
> - clocks = <&clks VF610_CLK_SAI2>;
> - clock-names = "sai";
> + clocks = <&clks VF610_CLK_PLATFORM_BUS>,
> + <&clks VF610_CLK_SAI2>,
> + <&clks 0>, <&clks 0>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> dma-names = "tx", "rx";
> dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
> <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
> diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
> index d31ce1b..4c3cd59 100644
> --- a/arch/arm/boot/dts/vf610.dtsi
> +++ b/arch/arm/boot/dts/vf610.dtsi
> @@ -139,8 +139,10 @@
> compatible = "fsl,vf610-sai";
> reg = <0x40031000 0x1000>;
> interrupts = <0 86 0x04>;
> - clocks = <&clks VF610_CLK_SAI2>;
> - clock-names = "sai";
> + clocks = <&clks VF610_CLK_PLATFORM_BUS>,
> + <&clks VF610_CLK_SAI2>,
> + <&clks 0>, <&clks 0>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> status = "disabled";
> };
>
> diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> index db9f75e..5fff2e1 100644
> --- a/sound/soc/fsl/fsl_sai.c
> +++ b/sound/soc/fsl/fsl_sai.c
> @@ -401,7 +401,15 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
> struct snd_soc_dai *cpu_dai)
> {
> struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
> + struct device *dev = &sai->pdev->dev;
> u32 reg;
> + int ret;
> +
> + ret = clk_prepare_enable(sai->bus_clk);
> + if (ret) {
> + dev_err(dev, "failed to enable bus clock: %d\n", ret);
> + return ret;
> + }
>
> if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> reg = FSL_SAI_TCR3;
> @@ -427,6 +435,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
>
> regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
> ~FSL_SAI_CR3_TRCE);
> +
> + clk_disable_unprepare(sai->bus_clk);
> }
>
> static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
> @@ -559,7 +569,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
> struct fsl_sai *sai;
> struct resource *res;
> void __iomem *base;
> - int irq, ret;
> + char tmp[8];
> + int irq, ret, i;
>
> sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
> if (!sai)
> @@ -582,12 +593,35 @@ static int fsl_sai_probe(struct platform_device *pdev)
> return PTR_ERR(base);
>
> sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> - "sai", base, &fsl_sai_regmap_config);
> + "bus", base, &fsl_sai_regmap_config);
> +
> + /* Compatible with old DTB cases */
> + if (IS_ERR(sai->regmap))
> + sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
> + "sai", base, &fsl_sai_regmap_config);
> if (IS_ERR(sai->regmap)) {
> dev_err(&pdev->dev, "regmap init failed\n");
> return PTR_ERR(sai->regmap);
> }
>
> + /* No error out for old DTB cases but only mark the clock NULL */
> + sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
> + if (IS_ERR(sai->bus_clk)) {
> + dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
> + PTR_ERR(sai->bus_clk));
> + sai->bus_clk = NULL;
> + }
> +
> + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
> + sprintf(tmp, "mclk%d", i + 1);
> + sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
> + if (IS_ERR(sai->mclk_clk[i])) {
> + dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
> + i + 1, PTR_ERR(sai->mclk_clk[i]));
> + sai->mclk_clk[i] = NULL;
> + }
> + }
> +
> irq = platform_get_irq(pdev, 0);
> if (irq < 0) {
> dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
> diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
> index 677670d..0e6c9f5 100644
> --- a/sound/soc/fsl/fsl_sai.h
> +++ b/sound/soc/fsl/fsl_sai.h
> @@ -119,6 +119,8 @@
> #define FSL_SAI_CLK_MAST2 2
> #define FSL_SAI_CLK_MAST3 3
>
> +#define FSL_SAI_MCLK_MAX 3
> +
> /* SAI data transfer numbers per DMA request */
> #define FSL_SAI_MAXBURST_TX 6
> #define FSL_SAI_MAXBURST_RX 6
> @@ -126,6 +128,8 @@
> struct fsl_sai {
> struct platform_device *pdev;
> struct regmap *regmap;
> + struct clk *bus_clk;
> + struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
>
> bool big_endian_regs;
> bool big_endian_data;
> --
> 1.8.4
>
>
^ permalink raw reply
* [PATCH] PCI/hotplug/rphahp: Fix endianess issues
From: Laurent Dufour @ 2014-04-10 13:02 UTC (permalink / raw)
To: Bjorn Helgaas, linux-pci, linuxppc-dev; +Cc: mdroth
Numerical values stored in the device tree are encoded in Big Endian and
should be byte swapped when running in Little Endian.
RPA hot plug module should convert those values as well.
Note that in rpaphp_get_drc_props the comparison between indexes[i+1] and
*index is done using the BE values (whatever is the current endianess).
This doesn't matter since we are checking for equality here. This way only
the returned value is byte swapped.
RPA also made RTAS calls which implies BE values to be used. According to
the patch done in RTAS (http://patchwork.ozlabs.org/patch/336865), no
additional conversion is required in RPA.
Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
---
drivers/pci/hotplug/rpaphp_core.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/hotplug/rpaphp_core.c b/drivers/pci/hotplug/rpaphp_core.c
index 4796c15..984d708 100644
--- a/drivers/pci/hotplug/rpaphp_core.c
+++ b/drivers/pci/hotplug/rpaphp_core.c
@@ -223,16 +223,16 @@ int rpaphp_get_drc_props(struct device_node *dn, int *drc_index,
type_tmp = (char *) &types[1];
/* Iterate through parent properties, looking for my-drc-index */
- for (i = 0; i < indexes[0]; i++) {
+ for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
if ((unsigned int) indexes[i + 1] == *my_index) {
if (drc_name)
*drc_name = name_tmp;
if (drc_type)
*drc_type = type_tmp;
if (drc_index)
- *drc_index = *my_index;
+ *drc_index = be32_to_cpu(*my_index);
if (drc_power_domain)
- *drc_power_domain = domains[i+1];
+ *drc_power_domain = be32_to_cpu(domains[i+1]);
return 0;
}
name_tmp += (strlen(name_tmp) + 1);
@@ -321,16 +321,19 @@ int rpaphp_add_slot(struct device_node *dn)
/* register PCI devices */
name = (char *) &names[1];
type = (char *) &types[1];
- for (i = 0; i < indexes[0]; i++) {
+ for (i = 0; i < be32_to_cpu(indexes[0]); i++) {
+ int index;
- slot = alloc_slot_struct(dn, indexes[i + 1], name, power_domains[i + 1]);
+ index = be32_to_cpu(indexes[i + 1]);
+ slot = alloc_slot_struct(dn, index, name,
+ be32_to_cpu(power_domains[i + 1]));
if (!slot)
return -ENOMEM;
slot->type = simple_strtoul(type, NULL, 10);
dbg("Found drc-index:0x%x drc-name:%s drc-type:%s\n",
- indexes[i + 1], name, type);
+ index, name, type);
retval = rpaphp_enable_slot(slot);
if (!retval)
^ permalink raw reply related
* Re: [PATCH v3 8/8] DMA: Freescale: add suspend resume functions for DMA driver
From: Andy Shevchenko @ 2014-04-10 12:05 UTC (permalink / raw)
To: hongbo.zhang
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397113805-24171-9-git-send-email-hongbo.zhang@freescale.com>
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>
> This patch adds suspend resume functions for Freescale DMA driver.
> .prepare callback is used to stop further descriptors from being added into the
> pending queue, and also issue pending queues into execution if there is any.
> .suspend callback makes sure all the pending jobs are cleaned up and all the
> channels are idle, and save the mode registers.
> .resume callback re-initializes the channels by restore the mode registers.
Like we discussed with Vinod [1] the DMA controller drivers should go to
suspend after users and come back before them.
After you reconsider this point the patch logic might be modified a lot.
(Moreover, you abuse your own position to use only setters/getters to
access to the DMAc registers)
[1] http://www.spinics.net/lists/kernel/msg1650974.html
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
> ---
> drivers/dma/fsldma.c | 100 ++++++++++++++++++++++++++++++++++++++++++++++++++
> drivers/dma/fsldma.h | 16 ++++++++
> 2 files changed, 116 insertions(+)
>
> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
> index c9bf54a..d6da222 100644
> --- a/drivers/dma/fsldma.c
> +++ b/drivers/dma/fsldma.c
> @@ -400,6 +400,14 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
>
> spin_lock_bh(&chan->desc_lock);
>
> +#ifdef CONFIG_PM
> + if (unlikely(chan->pm_state != RUNNING)) {
> + chan_dbg(chan, "cannot submit due to suspend\n");
> + spin_unlock_bh(&chan->desc_lock);
> + return -1;
> + }
> +#endif
> +
> /*
> * assign cookies to all of the software descriptors
> * that make up this transaction
> @@ -1311,6 +1319,9 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
> INIT_LIST_HEAD(&chan->ld_running);
> INIT_LIST_HEAD(&chan->ld_completed);
> chan->idle = true;
> +#ifdef CONFIG_PM
> + chan->pm_state = RUNNING;
> +#endif
>
> chan->common.device = &fdev->common;
> dma_cookie_init(&chan->common);
> @@ -1450,6 +1461,92 @@ static int fsldma_of_remove(struct platform_device *op)
> return 0;
> }
>
> +#ifdef CONFIG_PM
> +static int fsldma_prepare(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
> + struct fsldma_chan *chan;
> + int i;
> +
> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
> + chan = fdev->chan[i];
> + if (!chan)
> + continue;
> +
> + spin_lock_bh(&chan->desc_lock);
> + chan->pm_state = SUSPENDING;
> + if (!list_empty(&chan->ld_pending))
> + fsl_chan_xfer_ld_queue(chan);
> + spin_unlock_bh(&chan->desc_lock);
> + }
> +
> + return 0;
> +}
> +
> +static int fsldma_suspend(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
> + struct fsldma_chan *chan;
> + int i;
> +
> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
> + chan = fdev->chan[i];
> + if (!chan)
> + continue;
> +
> + spin_lock_bh(&chan->desc_lock);
> + if (!chan->idle)
> + goto out;
> + chan->regs_save.mr = DMA_IN(chan, &chan->regs->mr, 32);
> + chan->pm_state = SUSPENDED;
> + spin_unlock_bh(&chan->desc_lock);
> + }
> + return 0;
> +
> +out:
> + for (; i >= 0; i--) {
> + chan = fdev->chan[i];
> + if (!chan)
> + continue;
> + chan->pm_state = RUNNING;
> + spin_unlock_bh(&chan->desc_lock);
> + }
> + return -EBUSY;
> +}
> +
> +static int fsldma_resume(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct fsldma_device *fdev = platform_get_drvdata(pdev);
> + struct fsldma_chan *chan;
> + u32 mode;
> + int i;
> +
> + for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
> + chan = fdev->chan[i];
> + if (!chan)
> + continue;
> +
> + spin_lock_bh(&chan->desc_lock);
> + mode = chan->regs_save.mr
> + & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
> + DMA_OUT(chan, &chan->regs->mr, mode, 32);
> + chan->pm_state = RUNNING;
> + spin_unlock_bh(&chan->desc_lock);
> + }
> +
> + return 0;
> +}
> +
> +static const struct dev_pm_ops fsldma_pm_ops = {
> + .prepare = fsldma_prepare,
> + .suspend = fsldma_suspend,
> + .resume = fsldma_resume,
> +};
> +#endif
> +
> static const struct of_device_id fsldma_of_ids[] = {
> { .compatible = "fsl,elo3-dma", },
> { .compatible = "fsl,eloplus-dma", },
> @@ -1462,6 +1559,9 @@ static struct platform_driver fsldma_of_driver = {
> .name = "fsl-elo-dma",
> .owner = THIS_MODULE,
> .of_match_table = fsldma_of_ids,
> +#ifdef CONFIG_PM
> + .pm = &fsldma_pm_ops,
> +#endif
> },
> .probe = fsldma_of_probe,
> .remove = fsldma_of_remove,
> diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
> index ec19517..eecaf9e 100644
> --- a/drivers/dma/fsldma.h
> +++ b/drivers/dma/fsldma.h
> @@ -134,6 +134,18 @@ struct fsldma_device {
> #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000
> #define FSL_DMA_CHAN_START_EXT 0x00002000
>
> +#ifdef CONFIG_PM
> +struct fsldma_chan_regs_save {
> + u32 mr;
> +};
> +
> +enum fsldma_pm_state {
> + RUNNING = 0,
> + SUSPENDING,
> + SUSPENDED,
> +};
> +#endif
> +
> struct fsldma_chan {
> char name[8]; /* Channel name */
> struct fsldma_chan_regs __iomem *regs;
> @@ -161,6 +173,10 @@ struct fsldma_chan {
> struct tasklet_struct tasklet;
> u32 feature;
> bool idle; /* DMA controller is idle */
> +#ifdef CONFIG_PM
> + struct fsldma_chan_regs_save regs_save;
> + enum fsldma_pm_state pm_state;
> +#endif
>
> void (*toggle_ext_pause)(struct fsldma_chan *fsl_chan, int enable);
> void (*toggle_ext_start)(struct fsldma_chan *fsl_chan, int enable);
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* Re: [PATCH v3 6/8] DMA: Freescale: change descriptor release process for supporting async_tx
From: Andy Shevchenko @ 2014-04-10 11:56 UTC (permalink / raw)
To: hongbo.zhang
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397113805-24171-7-git-send-email-hongbo.zhang@freescale.com>
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>
> Fix the potential risk when enable config NET_DMA and ASYNC_TX. Async_tx is
> lack of support in current release process of dma descriptor, all descriptors
> will be released whatever is acked or no-acked by async_tx, so there is a
> potential race condition when dma engine is uesd by others clients (e.g. when
> enable NET_DMA to offload TCP).
>
> In our case, a race condition which is raised when use both of talitos and
> dmaengine to offload xor is because napi scheduler will sync all pending
> requests in dma channels, it affects the process of raid operations due to
> ack_tx is not checked in fsl dma. The no-acked descriptor is freed which is
> submitted just now, as a dependent tx, this freed descriptor trigger
> BUG_ON(async_tx_test_ack(depend_tx)) in async_tx_submit().
>
> TASK = ee1a94a0[1390] 'md0_raid5' THREAD: ecf40000 CPU: 0
> GPR00: 00000001 ecf41ca0 ee44/921a94a0 0000003f 00000001 c00593e4 00000000 00000001
> GPR08: 00000000 a7a7a7a7 00000001 045/920000002 42028042 100a38d4 ed576d98 00000000
> GPR16: ed5a11b0 00000000 2b162000 00000200 046/920000000 2d555000 ed3015e8 c15a7aa0
> GPR24: 00000000 c155fc40 00000000 ecb63220 ecf41d28 e47/92f640bb0 ef640c30 ecf41ca0
> NIP [c02b048c] async_tx_submit+0x6c/0x2b4
> LR [c02b068c] async_tx_submit+0x26c/0x2b4
> Call Trace:
> [ecf41ca0] [c02b068c] async_tx_submit+0x26c/0x2b448/92 (unreliable)
> [ecf41cd0] [c02b0a4c] async_memcpy+0x240/0x25c
> [ecf41d20] [c0421064] async_copy_data+0xa0/0x17c
> [ecf41d70] [c0421cf4] __raid_run_ops+0x874/0xe10
> [ecf41df0] [c0426ee4] handle_stripe+0x820/0x25e8
> [ecf41e90] [c0429080] raid5d+0x3d4/0x5b4
> [ecf41f40] [c04329b8] md_thread+0x138/0x16c
> [ecf41f90] [c008277c] kthread+0x8c/0x90
> [ecf41ff0] [c0011630] kernel_thread+0x4c/0x68
>
> Another modification in this patch is the change of completed descriptors,
> there is a potential risk which caused by exception interrupt, all descriptors
> in ld_running list are seemed completed when an interrupt raised, it works fine
> under normal condition, but if there is an exception occured, it cannot work as
> our excepted. Hardware should not be depend on s/w list, the right way is to
> read current descriptor address register to find the last completed descriptor.
> If an interrupt is raised by an error, all descriptors in ld_running should not
> be seemed finished, or these unfinished descriptors in ld_running will be
> released wrongly.
>
> A simple way to reproduce:
> Enable dmatest first, then insert some bad descriptors which can trigger
> Programming Error interrupts before the good descriptors. Last, the good
> descriptors will be freed before they are processsed because of the exception
> intrerrupt.
>
> Note: the bad descriptors are only for simulating an exception interrupt. This
> case can illustrate the potential risk in current fsl-dma very well.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
> ---
> drivers/dma/fsldma.c | 195 ++++++++++++++++++++++++++++++++++++--------------
> drivers/dma/fsldma.h | 17 ++++-
> 2 files changed, 158 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
> index 968877f..f8eee60 100644
> --- a/drivers/dma/fsldma.c
> +++ b/drivers/dma/fsldma.c
> @@ -459,6 +459,87 @@ static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
> }
>
> /**
> + * fsldma_clean_completed_descriptor - free all descriptors which
> + * has been completed and acked
IIRC the summary should be oneliner.
Check the rest of the code as well.
> + * @chan: Freescale DMA channel
> + *
> + * This function is used on all completed and acked descriptors.
> + * All descriptors should only be freed in this function.
> + */
> +static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
> +{
> + struct fsl_desc_sw *desc, *_desc;
> +
> + /* Run the callback for each descriptor, in order */
> + list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
> + if (async_tx_test_ack(&desc->async_tx))
> + fsl_dma_free_descriptor(chan, desc);
> +}
> +
> +/**
> + * fsldma_run_tx_complete_actions - cleanup a single link descriptor
> + * @chan: Freescale DMA channel
> + * @desc: descriptor to cleanup and free
> + * @cookie: Freescale DMA transaction identifier
> + *
> + * This function is used on a descriptor which has been executed by the DMA
> + * controller. It will run any callbacks, submit any dependencies.
> + */
> +static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
> + struct fsl_desc_sw *desc, dma_cookie_t cookie)
Maybe you could use cookie as local variable?
> +{
> + struct dma_async_tx_descriptor *txd = &desc->async_tx;
> +
> + BUG_ON(txd->cookie < 0);
> +
> + if (txd->cookie > 0) {
> + cookie = txd->cookie;
> +
> + /* Run the link descriptor callback function */
> + if (txd->callback) {
> + chan_dbg(chan, "LD %p callback\n", desc);
> + txd->callback(txd->callback_param);
> + }
> + }
> +
> + /* Run any dependencies */
> + dma_run_dependencies(txd);
> +
> + return cookie;
> +}
> +
> +/**
> + * fsldma_clean_running_descriptor - move the completed descriptor from
> + * ld_running to ld_completed
> + * @chan: Freescale DMA channel
> + * @desc: the descriptor which is completed
> + *
> + * Free the descriptor directly if acked by async_tx api, or move it to
> + * queue ld_completed.
> + */
> +static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
> + struct fsl_desc_sw *desc)
> +{
> + /* Remove from the list of transactions */
> + list_del(&desc->node);
> +
> + /*
> + * the client is allowed to attach dependent operations
Capital letter first?
> + * until 'ack' is set
> + */
> + if (!async_tx_test_ack(&desc->async_tx)) {
> + /*
> + * Move this descriptor to the list of descriptors which is
> + * completed, but still awaiting the 'ack' bit to be set.
> + */
> + list_add_tail(&desc->node, &chan->ld_completed);
> + return;
> + }
> +
> + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> +}
> +
> +/**
> * fsl_chan_xfer_ld_queue - transfer any pending transactions
> * @chan : Freescale DMA channel
> *
> @@ -526,30 +607,58 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
> }
>
> /**
> - * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
> + * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
> + * and move them to ld_completed to free until flag 'ack' is set
> * @chan: Freescale DMA channel
> - * @desc: descriptor to cleanup and free
> *
> - * This function is used on a descriptor which has been executed by the DMA
> - * controller. It will run any callbacks, submit any dependencies, and then
> - * free the descriptor.
> + * This function is used on descriptors which have been executed by the DMA
> + * controller. It will run any callbacks, submit any dependencies, then
> + * free these descriptors if flag 'ack' is set.
> */
> -static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
> - struct fsl_desc_sw *desc)
> +static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
> {
> - struct dma_async_tx_descriptor *txd = &desc->async_tx;
> + struct fsl_desc_sw *desc, *_desc;
> + dma_cookie_t cookie = 0;
> + dma_addr_t curr_phys = get_cdar(chan);
> + int seen_current = 0;
> +
> + fsldma_clean_completed_descriptor(chan);
> +
> + /* Run the callback for each descriptor, in order */
> + list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
> + /*
> + * do not advance past the current descriptor loaded into the
Capital letter first.
> + * hardware channel, subsequent descriptors are either in
> + * process or have not been submitted
Dot at the eol. Check in all comments.
> + */
> + if (seen_current)
> + break;
> +
> + /*
> + * stop the search if we reach the current descriptor and the
> + * channel is busy
> + */
> + if (desc->async_tx.phys == curr_phys) {
> + seen_current = 1;
> + if (!dma_is_idle(chan))
> + break;
> + }
> +
> + cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
>
> - /* Run the link descriptor callback function */
> - if (txd->callback) {
> - chan_dbg(chan, "LD %p callback\n", desc);
> - txd->callback(txd->callback_param);
> + fsldma_clean_running_descriptor(chan, desc);
> }
>
> - /* Run any dependencies */
> - dma_run_dependencies(txd);
> + /*
> + * Start any pending transactions automatically
Dot at the end of the line.
> + *
> + * In the ideal case, we keep the DMA controller busy while we go
> + * ahead and free the descriptors below.
> + */
> + fsl_chan_xfer_ld_queue(chan);
>
> - dma_descriptor_unmap(txd);
> - fsl_dma_free_descriptor(chan, desc);
> + if (cookie > 0)
> + chan->common.completed_cookie = cookie;
> }
>
> /**
> @@ -620,8 +729,10 @@ static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
>
> chan_dbg(chan, "free all channel resources\n");
> spin_lock_irqsave(&chan->desc_lock, flags);
> + fsldma_cleanup_descriptors(chan);
> fsldma_free_desc_list(chan, &chan->ld_pending);
> fsldma_free_desc_list(chan, &chan->ld_running);
> + fsldma_free_desc_list(chan, &chan->ld_completed);
> spin_unlock_irqrestore(&chan->desc_lock, flags);
>
> dma_pool_destroy(chan->desc_pool);
> @@ -859,6 +970,7 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
> /* Remove and free all of the descriptors in the LD queue */
> fsldma_free_desc_list(chan, &chan->ld_pending);
> fsldma_free_desc_list(chan, &chan->ld_running);
> + fsldma_free_desc_list(chan, &chan->ld_completed);
> chan->idle = true;
>
> spin_unlock_irqrestore(&chan->desc_lock, flags);
> @@ -918,6 +1030,17 @@ static enum dma_status fsl_tx_status(struct dma_chan *dchan,
> dma_cookie_t cookie,
> struct dma_tx_state *txstate)
> {
> + struct fsldma_chan *chan = to_fsl_chan(dchan);
> + enum dma_status ret;
> +
> + ret = dma_cookie_status(dchan, cookie, txstate);
> + if (ret == DMA_COMPLETE)
> + return ret;
> +
> + spin_lock_bh(&chan->desc_lock);
> + fsldma_cleanup_descriptors(chan);
> + spin_unlock_bh(&chan->desc_lock);
> +
> return dma_cookie_status(dchan, cookie, txstate);
> }
>
> @@ -995,52 +1118,19 @@ static irqreturn_t fsldma_chan_irq(int irq, void *data)
> static void dma_do_tasklet(unsigned long data)
> {
> struct fsldma_chan *chan = (struct fsldma_chan *)data;
> - struct fsl_desc_sw *desc, *_desc;
> - LIST_HEAD(ld_cleanup);
> unsigned long flags;
>
> chan_dbg(chan, "tasklet entry\n");
>
> spin_lock_irqsave(&chan->desc_lock, flags);
>
> - /* update the cookie if we have some descriptors to cleanup */
> - if (!list_empty(&chan->ld_running)) {
> - dma_cookie_t cookie;
> -
> - desc = to_fsl_desc(chan->ld_running.prev);
> - cookie = desc->async_tx.cookie;
> - dma_cookie_complete(&desc->async_tx);
> -
> - chan_dbg(chan, "completed_cookie=%d\n", cookie);
> - }
> -
> - /*
> - * move the descriptors to a temporary list so we can drop the lock
> - * during the entire cleanup operation
> - */
> - list_splice_tail_init(&chan->ld_running, &ld_cleanup);
> -
> /* the hardware is now idle and ready for more */
> chan->idle = true;
>
> - /*
> - * Start any pending transactions automatically
> - *
> - * In the ideal case, we keep the DMA controller busy while we go
> - * ahead and free the descriptors below.
> - */
> - fsl_chan_xfer_ld_queue(chan);
> - spin_unlock_irqrestore(&chan->desc_lock, flags);
> + /* Run all cleanup for descriptors which have been completed */
> + fsldma_cleanup_descriptors(chan);
>
> - /* Run the callback for each descriptor, in order */
> - list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
> -
> - /* Remove from the list of transactions */
> - list_del(&desc->node);
> -
> - /* Run all cleanup for this descriptor */
> - fsldma_cleanup_descriptor(chan, desc);
> - }
> + spin_unlock_irqrestore(&chan->desc_lock, flags);
>
> chan_dbg(chan, "tasklet exit\n");
> }
> @@ -1224,6 +1314,7 @@ static int fsl_dma_chan_probe(struct fsldma_device *fdev,
> spin_lock_init(&chan->desc_lock);
> INIT_LIST_HEAD(&chan->ld_pending);
> INIT_LIST_HEAD(&chan->ld_running);
> + INIT_LIST_HEAD(&chan->ld_completed);
> chan->idle = true;
>
> chan->common.device = &fdev->common;
> diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
> index d56e835..ec19517 100644
> --- a/drivers/dma/fsldma.h
> +++ b/drivers/dma/fsldma.h
> @@ -138,8 +138,21 @@ struct fsldma_chan {
> char name[8]; /* Channel name */
> struct fsldma_chan_regs __iomem *regs;
> spinlock_t desc_lock; /* Descriptor operation lock */
> - struct list_head ld_pending; /* Link descriptors queue */
> - struct list_head ld_running; /* Link descriptors queue */
> + /*
> + * Descriptors which are queued to run, but have not yet been
> + * submitted to the hardware for execution
> + */
> + struct list_head ld_pending;
> + /*
> + * Descriptors which are currently being executed by the hardware
> + */
> + struct list_head ld_running;
> + /*
> + * Descriptors which have finished execution by the hardware. These
> + * descriptors have already had their cleanup actions run. They are
> + * waiting for the ACK bit to be set by the async_tx API.
> + */
> + struct list_head ld_completed; /* Link descriptors queue */
> struct dma_chan common; /* DMA common channel */
> struct dma_pool *desc_pool; /* Descriptors pool */
> struct device *dev; /* Channel device */
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* Re: [PATCH v3 4/8] DMA: Freescale: add fsl_dma_free_descriptor() to reduce code duplication
From: Andy Shevchenko @ 2014-04-10 11:29 UTC (permalink / raw)
To: hongbo.zhang
Cc: leo.li, vkoul, linux-kernel, scottwood, dmaengine, dan.j.williams,
linuxppc-dev
In-Reply-To: <1397113805-24171-5-git-send-email-hongbo.zhang@freescale.com>
On Thu, 2014-04-10 at 15:10 +0800, hongbo.zhang@freescale.com wrote:
> From: Hongbo Zhang <hongbo.zhang@freescale.com>
>
> There are several places where descriptors are freed using identical code.
> This patch puts this code into a function to reduce code duplication.
>
> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
> Signed-off-by: Qiang Liu <qiang.liu@freescale.com>
> ---
> drivers/dma/fsldma.c | 30 ++++++++++++++++++------------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
> index b71cc04..b5a0ffa 100644
> --- a/drivers/dma/fsldma.c
> +++ b/drivers/dma/fsldma.c
> @@ -418,6 +418,19 @@ static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
> }
>
> /**
> + * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
> + * @chan : Freescale DMA channel
> + * @desc: descriptor to be freed
> + */
> +static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
> + struct fsl_desc_sw *desc)
> +{
> + list_del(&desc->node);
> + chan_dbg(chan, "LD %p free\n", desc);
> + dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> +}
> +
> +/**
> * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
> * @chan : Freescale DMA channel
> *
> @@ -489,11 +502,8 @@ static void fsldma_free_desc_list(struct fsldma_chan *chan,
> {
> struct fsl_desc_sw *desc, *_desc;
>
> - list_for_each_entry_safe(desc, _desc, list, node) {
> - list_del(&desc->node);
> - chan_dbg(chan, "LD %p free\n", desc);
> - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> - }
> + list_for_each_entry_safe(desc, _desc, list, node)
> + fsl_dma_free_descriptor(chan, desc);
> }
>
> static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
> @@ -501,11 +511,8 @@ static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
> {
> struct fsl_desc_sw *desc, *_desc;
>
> - list_for_each_entry_safe_reverse(desc, _desc, list, node) {
> - list_del(&desc->node);
> - chan_dbg(chan, "LD %p free\n", desc);
> - dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
> - }
> + list_for_each_entry_safe_reverse(desc, _desc, list, node)
> + fsl_dma_free_descriptor(chan, desc);
> }
>
> /**
> @@ -819,8 +826,7 @@ static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
> dma_run_dependencies(txd);
>
> dma_descriptor_unmap(txd);
> - chan_dbg(chan, "LD %p free\n", desc);
> - dma_pool_free(chan->desc_pool, desc, txd->phys);
> + fsl_dma_free_descriptor(chan, desc);
Here is no list_del() call since it's been called in dma_do_tasklet().
What will be the result of double list_del() against the same node?
> }
>
> /**
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
^ permalink raw reply
* [PATCH v5] ASoC: fsl_sai: Add clock controls for SAI
From: Nicolin Chen @ 2014-04-10 11:23 UTC (permalink / raw)
To: broonie, shawn.guo
Cc: mark.rutland, devicetree, alsa-devel, pawel.moll, linux-doc,
ijc+devicetree, linux-kernel, robh+dt, timur, Li.Xiubo, rob,
galak, linuxppc-dev
The SAI mainly has the following clocks:
bus clock
control and configure registers and to generate synchronous
interrupts and DMA requests.
mclk1, mclk2, mclk3
to generate the bit clock when the receiver or transmitter is
configured for an internally generated bit clock.
So this patch adds these clocks and their clock controls to the driver,
meanwhile, corrects the existing DTS accordingly so those platforms can
benifit from the further feature with different clock sources.
[ To concern the old DTB cases, I've added a bit of extra code to make
the driver compatible with them. And by marking clock NULL if failed
to get, the clk_prepare() or clk_get_rate() would easily return 0
so no further path should be broken. -- by Nicolin ]
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
---
Changelog
v5:
* Dropped mclk preparing and enabling since we are not using them currecntly.
* Made the change compatible to the old DTB.
* Added returned error value print.
v4:
* Merged into single patch.
* Fixed bus clock ID on vf610.
v3:
* Use int type for ret instead of u32.
* Added Acked-by and Tested-by from Xiubo Li.
v2:
* Appended two extra mclks to the driver since SAI actually has three.
* Renamed clock name to 'bus' and 'mclk' according to the reference manual.
.../devicetree/bindings/sound/fsl-sai.txt | 9 +++--
arch/arm/boot/dts/vf610.dtsi | 6 ++--
sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++--
sound/soc/fsl/fsl_sai.h | 4 +++
4 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 35c09fe..0f4e238 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -10,7 +10,8 @@ Required properties:
- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
- reg: Offset and length of the register set for the device.
- clocks: Must contain an entry for each entry in clock-names.
-- clock-names : Must include the "sai" entry.
+- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
+ "mclk3" for bit clock and frame clock providing.
- dmas : Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
- dma-names : Two dmas have to be defined, "tx" and "rx".
@@ -30,8 +31,10 @@ sai2: sai@40031000 {
reg = <0x40031000 0x1000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2_1>;
- clocks = <&clks VF610_CLK_SAI2>;
- clock-names = "sai";
+ clocks = <&clks VF610_CLK_PLATFORM_BUS>,
+ <&clks VF610_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "tx", "rx";
dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index d31ce1b..4c3cd59 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -139,8 +139,10 @@
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <0 86 0x04>;
- clocks = <&clks VF610_CLK_SAI2>;
- clock-names = "sai";
+ clocks = <&clks VF610_CLK_PLATFORM_BUS>,
+ <&clks VF610_CLK_SAI2>,
+ <&clks 0>, <&clks 0>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
status = "disabled";
};
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index db9f75e..5fff2e1 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -401,7 +401,15 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ struct device *dev = &sai->pdev->dev;
u32 reg;
+ int ret;
+
+ ret = clk_prepare_enable(sai->bus_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable bus clock: %d\n", ret);
+ return ret;
+ }
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
reg = FSL_SAI_TCR3;
@@ -427,6 +435,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, reg, FSL_SAI_CR3_TRCE,
~FSL_SAI_CR3_TRCE);
+
+ clk_disable_unprepare(sai->bus_clk);
}
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
@@ -559,7 +569,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
struct fsl_sai *sai;
struct resource *res;
void __iomem *base;
- int irq, ret;
+ char tmp[8];
+ int irq, ret, i;
sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
if (!sai)
@@ -582,12 +593,35 @@ static int fsl_sai_probe(struct platform_device *pdev)
return PTR_ERR(base);
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
- "sai", base, &fsl_sai_regmap_config);
+ "bus", base, &fsl_sai_regmap_config);
+
+ /* Compatible with old DTB cases */
+ if (IS_ERR(sai->regmap))
+ sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
+ "sai", base, &fsl_sai_regmap_config);
if (IS_ERR(sai->regmap)) {
dev_err(&pdev->dev, "regmap init failed\n");
return PTR_ERR(sai->regmap);
}
+ /* No error out for old DTB cases but only mark the clock NULL */
+ sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
+ if (IS_ERR(sai->bus_clk)) {
+ dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
+ PTR_ERR(sai->bus_clk));
+ sai->bus_clk = NULL;
+ }
+
+ for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
+ sprintf(tmp, "mclk%d", i + 1);
+ sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(sai->mclk_clk[i])) {
+ dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
+ i + 1, PTR_ERR(sai->mclk_clk[i]));
+ sai->mclk_clk[i] = NULL;
+ }
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 677670d..0e6c9f5 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -119,6 +119,8 @@
#define FSL_SAI_CLK_MAST2 2
#define FSL_SAI_CLK_MAST3 3
+#define FSL_SAI_MCLK_MAX 3
+
/* SAI data transfer numbers per DMA request */
#define FSL_SAI_MAXBURST_TX 6
#define FSL_SAI_MAXBURST_RX 6
@@ -126,6 +128,8 @@
struct fsl_sai {
struct platform_device *pdev;
struct regmap *regmap;
+ struct clk *bus_clk;
+ struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
bool big_endian_regs;
bool big_endian_data;
--
1.8.4
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