* Re: [PATCH 1/3] cpufreq: ppc: Add missing #include <asm/smp.h>
From: Viresh Kumar @ 2014-04-21 5:51 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: linuxppc-dev@lists.ozlabs.org, Rafael J. Wysocki,
Linux Kernel Mailing List, cpufreq@vger.kernel.org,
linux-pm@vger.kernel.org
In-Reply-To: <1397728407-13909-1-git-send-email-geert+renesas@glider.be>
On 17 April 2014 15:23, Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> If CONFIG_SMP=n, <linux/smp.h> does not include <asm/smp.h>, causing:
>
> drivers/cpufreq/ppc-corenet-cpufreq.c: In function 'corenet_cpufreq_cpu_init':
> drivers/cpufreq/ppc-corenet-cpufreq.c:173:3: error: implicit declaration of function 'get_hard_smp_processor_id' [-Werror=implicit-function-declaration]
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> drivers/cpufreq/ppc-corenet-cpufreq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c
> index b7e677be1df0..e78f9c806de4 100644
> --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
> +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c
> @@ -22,6 +22,8 @@
> #include <linux/smp.h>
> #include <sysdev/fsl_soc.h>
>
> +#include <asm/smp.h>
> +
Probably similar to what Srivatsa did:
+#include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
??
^ permalink raw reply
* Re: [PATCH] powerpc/mm: Fix tlbie to add AVAL fields for 64K pages
From: Benjamin Herrenschmidt @ 2014-04-21 5:25 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, paulus
In-Reply-To: <1398056856-17891-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Mon, 2014-04-21 at 10:37 +0530, Aneesh Kumar K.V wrote:
> The if condition check was based on a draft ISA doc. Remove the same.
Is this a real bug ? Do we need to send that back to stable ?
Ben.
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/mm/hash_native_64.c | 38 ++++++++++++++++----------------------
> 1 file changed, 16 insertions(+), 22 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index 3ea26c25590b..cf1d325eae8b 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -82,17 +82,14 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
> va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> - /* Add AVAL part */
> - if (psize != apsize) {
> - /*
> - * MPSS, 64K base page size and 16MB parge page size
> - * We don't need all the bits, but rest of the bits
> - * must be ignored by the processor.
> - * vpn cover upto 65 bits of va. (0...65) and we need
> - * 58..64 bits of va.
> - */
> - va |= (vpn & 0xfe);
> - }
> + /*
> + * AVAL bits:
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
> + */
> + va |= (vpn & 0xfe); /* AVAL */
> va |= 1; /* L */
> asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
> : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
> @@ -133,17 +130,14 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
> va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
> va |= penc << 12;
> va |= ssize << 8;
> - /* Add AVAL part */
> - if (psize != apsize) {
> - /*
> - * MPSS, 64K base page size and 16MB parge page size
> - * We don't need all the bits, but rest of the bits
> - * must be ignored by the processor.
> - * vpn cover upto 65 bits of va. (0...65) and we need
> - * 58..64 bits of va.
> - */
> - va |= (vpn & 0xfe);
> - }
> + /*
> + * AVAL bits:
> + * We don't need all the bits, but rest of the bits
> + * must be ignored by the processor.
> + * vpn cover upto 65 bits of va. (0...65) and we need
> + * 58..64 bits of va.
> + */
> + va |= (vpn & 0xfe);
> va |= 1; /* L */
> asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
> : : "r"(va) : "memory");
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/powernc: revert part of commit d905c5df(PPC: POWERNV: move iommu_add_device earlier)
From: Wei Yang @ 2014-04-21 5:22 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: aik, linuxppc-dev, gwshan
In-Reply-To: <1398051452.19682.15.camel@pasglop>
On Mon, Apr 21, 2014 at 01:37:32PM +1000, Benjamin Herrenschmidt wrote:
>On Mon, 2014-04-21 at 10:25 +0800, Wei Yang wrote:
>> Here is a draft call flow:
>>
>> pci_device_add
>> pcibios_add_device
>> pci_dma_dev_setup
>> pnv_pci_dma_dev_setup
>> pnv_pci_ioda_dma_dev_setup
>> set_iommu_table_base_and_group <--- here
>> device_add
>>
>> When set_iommu_table_base_and_group() is invoked int
>> pnv_pci_ioda_dma_dev_setup(), the dev->kobj->sd is not initialized. The
>> dev->kobj->sd is initialized in device_add().
>>
>> After applying this patch, the error
>> iommu_tce: 0003:05:00.0 has not been added, ret=-14
>> is cleared.
>>
>> This patch revert the change for pnv_pci_ioda_dma_dev_setup() from commit
>> d905c5df(PPC: POWERNV: move iommu_add_device earlier).
>
>But in that case, is the group still set ?
I think so.
iommu_add_device() will be invoked when device_add() notify the pci bus.
>
>Alexey, is that correct ?
>
>Cheers,
>Ben.
>
>> Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
>> ---
>> arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
>> index fc4edda..b5d8f73 100644
>> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
>> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
>> @@ -1425,7 +1425,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
>>
>> pe = &phb->ioda.pe_array[pdn->pe_number];
>> WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
>> - set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
>> + set_iommu_table_base(&pdev->dev, &pe->tce32_table);
>> }
>>
>> static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
>
--
Richard Yang
Help you, Help me
^ permalink raw reply
* [PATCH] powerpc/mm: Fix tlbie to add AVAL fields for 64K pages
From: Aneesh Kumar K.V @ 2014-04-21 5:07 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev, Aneesh Kumar K.V
The if condition check was based on a draft ISA doc. Remove the same.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/mm/hash_native_64.c | 38 ++++++++++++++++----------------------
1 file changed, 16 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 3ea26c25590b..cf1d325eae8b 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -82,17 +82,14 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
va |= penc << 12;
va |= ssize << 8;
- /* Add AVAL part */
- if (psize != apsize) {
- /*
- * MPSS, 64K base page size and 16MB parge page size
- * We don't need all the bits, but rest of the bits
- * must be ignored by the processor.
- * vpn cover upto 65 bits of va. (0...65) and we need
- * 58..64 bits of va.
- */
- va |= (vpn & 0xfe);
- }
+ /*
+ * AVAL bits:
+ * We don't need all the bits, but rest of the bits
+ * must be ignored by the processor.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 58..64 bits of va.
+ */
+ va |= (vpn & 0xfe); /* AVAL */
va |= 1; /* L */
asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
: : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
@@ -133,17 +130,14 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
va |= penc << 12;
va |= ssize << 8;
- /* Add AVAL part */
- if (psize != apsize) {
- /*
- * MPSS, 64K base page size and 16MB parge page size
- * We don't need all the bits, but rest of the bits
- * must be ignored by the processor.
- * vpn cover upto 65 bits of va. (0...65) and we need
- * 58..64 bits of va.
- */
- va |= (vpn & 0xfe);
- }
+ /*
+ * AVAL bits:
+ * We don't need all the bits, but rest of the bits
+ * must be ignored by the processor.
+ * vpn cover upto 65 bits of va. (0...65) and we need
+ * 58..64 bits of va.
+ */
+ va |= (vpn & 0xfe);
va |= 1; /* L */
asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
: : "r"(va) : "memory");
--
1.9.1
^ permalink raw reply related
* Re: [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: punnaiah choudary kalluri @ 2014-04-21 4:53 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: linux-usb, michal.simek@xilinx.com, balbi,
linux-kernel@vger.kernel.org, Punnaiah Choudary, Peter Chen,
Punnaiah Choudary Kalluri, linuxppc-dev, linux-arm-kernel
In-Reply-To: <5354175B.3070109@pengutronix.de>
On Mon, Apr 21, 2014 at 12:22 AM, Marc Kleine-Budde <mkl@pengutronix.de> wrote:
> On 04/20/2014 06:27 PM, Punnaiah Choudary Kalluri wrote:
>> Zynq soc contains a dual role usb controller and this IP is from synopsys. We
>> observed that there is driver available for this controller from freescale and
>> decided to reuse this driver for zynq use.
>
> Have a look drivers/usb/chipidea. It's maintained by Peter Chen (Cc'ed)
> and is in better shape than the freescale driver.
Thanks. I will check this implementation and also check with Peter Chen if
i have any concerns about this implementation.
Punnaiah.
>
> Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Industrial Linux Solutions | Phone: +49-231-2826-924 |
> Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
> Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
>
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/powernc: revert part of commit d905c5df(PPC: POWERNV: move iommu_add_device earlier)
From: Benjamin Herrenschmidt @ 2014-04-21 3:37 UTC (permalink / raw)
To: Wei Yang; +Cc: aik, linuxppc-dev, gwshan
In-Reply-To: <1398047119-6861-2-git-send-email-weiyang@linux.vnet.ibm.com>
On Mon, 2014-04-21 at 10:25 +0800, Wei Yang wrote:
> Here is a draft call flow:
>
> pci_device_add
> pcibios_add_device
> pci_dma_dev_setup
> pnv_pci_dma_dev_setup
> pnv_pci_ioda_dma_dev_setup
> set_iommu_table_base_and_group <--- here
> device_add
>
> When set_iommu_table_base_and_group() is invoked int
> pnv_pci_ioda_dma_dev_setup(), the dev->kobj->sd is not initialized. The
> dev->kobj->sd is initialized in device_add().
>
> After applying this patch, the error
> iommu_tce: 0003:05:00.0 has not been added, ret=-14
> is cleared.
>
> This patch revert the change for pnv_pci_ioda_dma_dev_setup() from commit
> d905c5df(PPC: POWERNV: move iommu_add_device earlier).
But in that case, is the group still set ?
Alexey, is that correct ?
Cheers,
Ben.
> Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index fc4edda..b5d8f73 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -1425,7 +1425,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
>
> pe = &phb->ioda.pe_array[pdn->pe_number];
> WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
> - set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
> + set_iommu_table_base(&pdev->dev, &pe->tce32_table);
> }
>
> static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/powernv: clear the refcount for pci_dev on powernv platform
From: Benjamin Herrenschmidt @ 2014-04-21 3:35 UTC (permalink / raw)
To: Wei Yang; +Cc: aik, linuxppc-dev, gwshan, Gavin Shan
In-Reply-To: <1398047119-6861-1-git-send-email-weiyang@linux.vnet.ibm.com>
On Mon, 2014-04-21 at 10:25 +0800, Wei Yang wrote:
> When pcibios_remove_pci_devices() is removing pci devices, it will release
> pci device respectively. When the refcount of the device is 0, the pci_dev
> structure will be destroyed.
>
> On PowerNV platform, the pci_dev will not be destroyed since the refcount is
> not 0.
>
> After applying the patch, this warning is cleared during the EEH hotplug
> event.
You have to be careful here. We take a reference to the device in the
structure eeh_dev, that means we might access it after it's freed if
we don't increase the refcount.
Cheers,
Ben.
> [ 204.123609] ------------[ cut here ]------------
> [ 204.123645] WARNING: at arch/powerpc/kernel/iommu.c:1125
> [ 204.123680] Modules linked in: xt_CHECKSUM nf_conntrack_netbios_ns nf_conntrack_broadcast ipt_MASQUERADE ip6t_REJECT bnep bluetooth 6lowpan_iphc rfkill xt_conntrack ebtable_nat ebtable_broute bridge stp llc mlx4_ib ib_sa ib_mad ib_core ib_addr ebtable_filter ebtables ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle iptable_security iptable_raw bnx2x tg3 mlx4_core nfsd ptp mdio ses libcrc32c nfs_acl enclosure be2net pps_core shpchp lockd kvm uinput sunrpc binfmt_misc lpfc scsi_transport_fc ipr scsi_tgt
> [ 204.124356] CPU: 18 PID: 650 Comm: eehd Not tainted 3.14.0-rc5yw+ #102
> [ 204.124400] task: c0000027ed485670 ti: c0000027ed50c000 task.ti: c0000027ed50c000
> [ 204.124453] NIP: c00000000003cf80 LR: c00000000006c648 CTR: c00000000006c5c0
> [ 204.124506] REGS: c0000027ed50f440 TRAP: 0700 Not tainted (3.14.0-rc5yw+)
> [ 204.124558] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 88008084 XER: 20000000
> [ 204.124682] CFAR: c00000000006c644 SOFTE: 1
> GPR00: c00000000006c648 c0000027ed50f6c0 c000000001398380 c0000027ec260300
> GPR04: c0000027ea92c000 c00000000006ad00 c0000000016e41b0 0000000000000110
> GPR08: c0000000012cd4c0 0000000000000001 c0000027ec2602ff 0000000000000062
> GPR12: 0000000028008084 c00000000fdca200 c0000000000d1d90 c0000027ec281a80
> GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000001
> GPR24: 000000005342697b 0000000000002906 c000001fe6ac9800 c000001fe6ac9800
> GPR28: 0000000000000000 c0000000016e3a80 c0000027ea92c090 c0000027ea92c000
> [ 204.125353] NIP [c00000000003cf80] .iommu_add_device+0x30/0x1f0
> [ 204.125399] LR [c00000000006c648] .pnv_pci_ioda_dma_dev_setup+0x88/0xb0
> [ 204.125443] Call Trace:
> [ 204.125464] [c0000027ed50f6c0] [c0000027ed50f750] 0xc0000027ed50f750 (unreliable)
> [ 204.125526] [c0000027ed50f750] [c00000000006c648] .pnv_pci_ioda_dma_dev_setup+0x88/0xb0
> [ 204.125588] [c0000027ed50f7d0] [c000000000069cc8] .pnv_pci_dma_dev_setup+0x78/0x340
> [ 204.125650] [c0000027ed50f870] [c000000000044408] .pcibios_setup_device+0x88/0x2f0
> [ 204.125712] [c0000027ed50f940] [c000000000046040] .pcibios_setup_bus_devices+0x60/0xd0
> [ 204.125774] [c0000027ed50f9c0] [c000000000043acc] .pcibios_add_pci_devices+0xdc/0x1c0
> [ 204.125837] [c0000027ed50fa50] [c00000000086f970] .eeh_reset_device+0x36c/0x4f0
> [ 204.125939] [c0000027ed50fb20] [c00000000003a2d8] .eeh_handle_normal_event+0x448/0x480
> [ 204.126068] [c0000027ed50fbc0] [c00000000003a35c] .eeh_handle_event+0x4c/0x340
> [ 204.126192] [c0000027ed50fc80] [c00000000003a74c] .eeh_event_handler+0xfc/0x1b0
> [ 204.126319] [c0000027ed50fd30] [c0000000000d1ea0] .kthread+0x110/0x130
> [ 204.126430] [c0000027ed50fe30] [c00000000000a460] .ret_from_kernel_thread+0x5c/0x7c
> [ 204.126556] Instruction dump:
> [ 204.126610] 7c0802a6 fba1ffe8 fbc1fff0 fbe1fff8 f8010010 f821ff71 7c7e1b78 60000000
> [ 204.126787] 60000000 e87e0298 3143ffff 7d2a1910 <0b090000> 2fa90000 40de00c8 ebfe0218
> [ 204.126966] ---[ end trace 6e7aefd80add2973 ]---
>
> This patch clear the step to get reference.
>
> Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/powernv/pci-ioda.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index e2270f4..fc4edda 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -561,7 +561,6 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
> pci_name(dev));
> continue;
> }
> - pci_dev_get(dev);
> pdn->pcidev = dev;
> pdn->pe_number = pe->pe_number;
> pe->dma_weight += pnv_ioda_dma_weight(dev);
^ permalink raw reply
* [PATCH 1/2] powerpc/powernv: clear the refcount for pci_dev on powernv platform
From: Wei Yang @ 2014-04-21 2:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Wei Yang, aik, gwshan
When pcibios_remove_pci_devices() is removing pci devices, it will release
pci device respectively. When the refcount of the device is 0, the pci_dev
structure will be destroyed.
On PowerNV platform, the pci_dev will not be destroyed since the refcount is
not 0.
After applying the patch, this warning is cleared during the EEH hotplug
event.
[ 204.123609] ------------[ cut here ]------------
[ 204.123645] WARNING: at arch/powerpc/kernel/iommu.c:1125
[ 204.123680] Modules linked in: xt_CHECKSUM nf_conntrack_netbios_ns nf_conntrack_broadcast ipt_MASQUERADE ip6t_REJECT bnep bluetooth 6lowpan_iphc rfkill xt_conntrack ebtable_nat ebtable_broute bridge stp llc mlx4_ib ib_sa ib_mad ib_core ib_addr ebtable_filter ebtables ip6table_nat nf_conntrack_ipv6 nf_defrag_ipv6 nf_nat_ipv6 ip6table_mangle ip6table_security ip6table_raw ip6table_filter ip6_tables iptable_nat nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_nat nf_conntrack iptable_mangle iptable_security iptable_raw bnx2x tg3 mlx4_core nfsd ptp mdio ses libcrc32c nfs_acl enclosure be2net pps_core shpchp lockd kvm uinput sunrpc binfmt_misc lpfc scsi_transport_fc ipr scsi_tgt
[ 204.124356] CPU: 18 PID: 650 Comm: eehd Not tainted 3.14.0-rc5yw+ #102
[ 204.124400] task: c0000027ed485670 ti: c0000027ed50c000 task.ti: c0000027ed50c000
[ 204.124453] NIP: c00000000003cf80 LR: c00000000006c648 CTR: c00000000006c5c0
[ 204.124506] REGS: c0000027ed50f440 TRAP: 0700 Not tainted (3.14.0-rc5yw+)
[ 204.124558] MSR: 9000000000029032 <SF,HV,EE,ME,IR,DR,RI> CR: 88008084 XER: 20000000
[ 204.124682] CFAR: c00000000006c644 SOFTE: 1
GPR00: c00000000006c648 c0000027ed50f6c0 c000000001398380 c0000027ec260300
GPR04: c0000027ea92c000 c00000000006ad00 c0000000016e41b0 0000000000000110
GPR08: c0000000012cd4c0 0000000000000001 c0000027ec2602ff 0000000000000062
GPR12: 0000000028008084 c00000000fdca200 c0000000000d1d90 c0000027ec281a80
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000001
GPR24: 000000005342697b 0000000000002906 c000001fe6ac9800 c000001fe6ac9800
GPR28: 0000000000000000 c0000000016e3a80 c0000027ea92c090 c0000027ea92c000
[ 204.125353] NIP [c00000000003cf80] .iommu_add_device+0x30/0x1f0
[ 204.125399] LR [c00000000006c648] .pnv_pci_ioda_dma_dev_setup+0x88/0xb0
[ 204.125443] Call Trace:
[ 204.125464] [c0000027ed50f6c0] [c0000027ed50f750] 0xc0000027ed50f750 (unreliable)
[ 204.125526] [c0000027ed50f750] [c00000000006c648] .pnv_pci_ioda_dma_dev_setup+0x88/0xb0
[ 204.125588] [c0000027ed50f7d0] [c000000000069cc8] .pnv_pci_dma_dev_setup+0x78/0x340
[ 204.125650] [c0000027ed50f870] [c000000000044408] .pcibios_setup_device+0x88/0x2f0
[ 204.125712] [c0000027ed50f940] [c000000000046040] .pcibios_setup_bus_devices+0x60/0xd0
[ 204.125774] [c0000027ed50f9c0] [c000000000043acc] .pcibios_add_pci_devices+0xdc/0x1c0
[ 204.125837] [c0000027ed50fa50] [c00000000086f970] .eeh_reset_device+0x36c/0x4f0
[ 204.125939] [c0000027ed50fb20] [c00000000003a2d8] .eeh_handle_normal_event+0x448/0x480
[ 204.126068] [c0000027ed50fbc0] [c00000000003a35c] .eeh_handle_event+0x4c/0x340
[ 204.126192] [c0000027ed50fc80] [c00000000003a74c] .eeh_event_handler+0xfc/0x1b0
[ 204.126319] [c0000027ed50fd30] [c0000000000d1ea0] .kthread+0x110/0x130
[ 204.126430] [c0000027ed50fe30] [c00000000000a460] .ret_from_kernel_thread+0x5c/0x7c
[ 204.126556] Instruction dump:
[ 204.126610] 7c0802a6 fba1ffe8 fbc1fff0 fbe1fff8 f8010010 f821ff71 7c7e1b78 60000000
[ 204.126787] 60000000 e87e0298 3143ffff 7d2a1910 <0b090000> 2fa90000 40de00c8 ebfe0218
[ 204.126966] ---[ end trace 6e7aefd80add2973 ]---
This patch clear the step to get reference.
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/pci-ioda.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index e2270f4..fc4edda 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -561,7 +561,6 @@ static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
pci_name(dev));
continue;
}
- pci_dev_get(dev);
pdn->pcidev = dev;
pdn->pe_number = pe->pe_number;
pe->dma_weight += pnv_ioda_dma_weight(dev);
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/2] powerpc/powernc: revert part of commit d905c5df(PPC: POWERNV: move iommu_add_device earlier)
From: Wei Yang @ 2014-04-21 2:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Wei Yang, aik, gwshan
In-Reply-To: <1398047119-6861-1-git-send-email-weiyang@linux.vnet.ibm.com>
Here is a draft call flow:
pci_device_add
pcibios_add_device
pci_dma_dev_setup
pnv_pci_dma_dev_setup
pnv_pci_ioda_dma_dev_setup
set_iommu_table_base_and_group <--- here
device_add
When set_iommu_table_base_and_group() is invoked int
pnv_pci_ioda_dma_dev_setup(), the dev->kobj->sd is not initialized. The
dev->kobj->sd is initialized in device_add().
After applying this patch, the error
iommu_tce: 0003:05:00.0 has not been added, ret=-14
is cleared.
This patch revert the change for pnv_pci_ioda_dma_dev_setup() from commit
d905c5df(PPC: POWERNV: move iommu_add_device earlier).
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index fc4edda..b5d8f73 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1425,7 +1425,7 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
pe = &phb->ioda.pe_array[pdn->pe_number];
WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
- set_iommu_table_base_and_group(&pdev->dev, &pe->tce32_table);
+ set_iommu_table_base(&pdev->dev, &pe->tce32_table);
}
static int pnv_pci_ioda_dma_set_mask(struct pnv_phb *phb,
--
1.7.9.5
^ permalink raw reply related
* Re: [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: Marc Kleine-Budde @ 2014-04-20 18:52 UTC (permalink / raw)
To: Punnaiah Choudary Kalluri, leoli, balbi, michal.simek
Cc: linux-usb, linux-kernel, Peter Chen, kalluripunnaiahchoudary,
kpc528, Punnaiah Choudary Kalluri, linuxppc-dev, linux-arm-kernel
In-Reply-To: <7aed4ee6-69e7-4f9f-9f45-675bc695089c@CO9EHSMHS031.ehs.local>
[-- Attachment #1: Type: text/plain, Size: 678 bytes --]
On 04/20/2014 06:27 PM, Punnaiah Choudary Kalluri wrote:
> Zynq soc contains a dual role usb controller and this IP is from synopsys. We
> observed that there is driver available for this controller from freescale and
> decided to reuse this driver for zynq use.
Have a look drivers/usb/chipidea. It's maintained by Peter Chen (Cc'ed)
and is in better shape than the freescale driver.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Industrial Linux Solutions | Phone: +49-231-2826-924 |
Vertretung West/Dortmund | Fax: +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 242 bytes --]
^ permalink raw reply
* Re: [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: Alan Stern @ 2014-04-20 17:56 UTC (permalink / raw)
To: Punnaiah Choudary Kalluri
Cc: linux-usb, michal.simek, balbi, linux-kernel,
kalluripunnaiahchoudary, kpc528, Punnaiah Choudary Kalluri,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <7aed4ee6-69e7-4f9f-9f45-675bc695089c@CO9EHSMHS031.ehs.local>
On Sun, 20 Apr 2014, Punnaiah Choudary Kalluri wrote:
> Zynq soc contains a dual role usb controller and this IP is from synopsys. We
> observed that there is driver available for this controller from freescale and
> decided to reuse this driver for zynq use.
>
> Here is the link for zynq soc TRM. Please refer chapter 15 for usb controller
> related information.
> http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
>
> The following series of patches add initial support for zynq soc in fsl gadget controller
> driver and fsl host controller driver.
>
> Based on these patches, I have the following concerns and sugesstions
>
> Since the freescale usb driver is for synopsys IP, Please consider rebranding
> this driver name and config options to reflect that it is a sysnopsys IP. So
> that other vendors who using this IP can reuse thie driver.
>
> Also the ehci-fsl.c is for powerpc based soc's, and zynq is ARM based, i have
> protected the code which is specifc to freescale with CONFIG_FSL_SOC. Please
> suggest if there is a better way of doing this?
Filling the code with #ifdef lines is definitely not a good way to go.
Ordinary "if" statements would be a lot better, if you can't figure out
a reasonable way to encapsulate the differences.
Alan Stern
^ permalink raw reply
* Re: [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: Greg KH @ 2014-04-20 16:58 UTC (permalink / raw)
To: Punnaiah Choudary Kalluri
Cc: linux-usb, michal.simek, balbi, linux-kernel,
kalluripunnaiahchoudary, kpc528, Punnaiah Choudary Kalluri,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <7aed4ee6-69e7-4f9f-9f45-675bc695089c@CO9EHSMHS031.ehs.local>
On Sun, Apr 20, 2014 at 09:57:03PM +0530, Punnaiah Choudary Kalluri wrote:
> Zynq soc contains a dual role usb controller and this IP is from synopsys. We
> observed that there is driver available for this controller from freescale and
> decided to reuse this driver for zynq use.
>
> Here is the link for zynq soc TRM. Please refer chapter 15 for usb controller
> related information.
> http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
>
> The following series of patches add initial support for zynq soc in fsl gadget controller
> driver and fsl host controller driver.
>
> Based on these patches, I have the following concerns and sugesstions
>
> Since the freescale usb driver is for synopsys IP, Please consider rebranding
> this driver name and config options to reflect that it is a sysnopsys IP. So
> that other vendors who using this IP can reuse thie driver.
The config options can be edited to show the new hardware support, but
we don't usually rename kernel drivers, sorry. That just gets messy in
the end, and the "first one here gets to name it" is usually enforced.
No users ever see a kernel driver name, especially for a gadget driver,
so it shouldn't ever really matter.
thanks,
greg k-h
^ permalink raw reply
* [RFC PATCH 2/2] usb: ehci-fsl: Add support for zynq usb host controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:27 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: linux-usb, linux-kernel, kalluripunnaiahchoudary, kpc528,
Punnaiah Choudary Kalluri, linuxppc-dev, linux-arm-kernel
In-Reply-To: <1398011225-19835-1-git-send-email-punnaia@xilinx.com>
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-fsl.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 3d9e540..295274e 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -117,7 +117,7 @@ config XPS_USB_HCD_XILINX
config USB_EHCI_FSL
bool "Support for Freescale PPC on-chip EHCI USB controller"
- depends on FSL_SOC
+ depends on FSL_SOC || ARCH_ZYNQ
select USB_EHCI_ROOT_HUB_TT
select USB_FSL_MPH_DR_OF if OF
---help---
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6f2c8d3..54db34f 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -23,11 +23,13 @@
* Anton Vorontsov <avorontsov@ru.mvista.com>.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/err.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
@@ -86,6 +88,15 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
}
irq = res->start;
+#ifdef CONFIG_ARCH_ZYNQ
+ pdata->clk = devm_clk_get(pdev->dev.parent, NULL);
+ if (IS_ERR(pdata->clk))
+ return PTR_ERR(pdata->clk);
+
+ retval = clk_prepare_enable(pdata->clk);
+ if (retval)
+ return retval;
+#endif
hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
if (!hcd) {
retval = -ENOMEM;
@@ -121,9 +132,11 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
goto err2;
}
+#ifdef CONFIG_FSL_SOC
/* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
+#endif
/* Don't need to set host mode here. It will be done by tdi_reset() */
@@ -159,6 +172,9 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
err2:
usb_put_hcd(hcd);
err1:
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable_unprepare(pdata->clk);
+#endif
dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
if (pdata->exit)
pdata->exit(pdev);
@@ -203,6 +219,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
{
u32 portsc;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+#ifdef CONFIG_FSL_SOC
void __iomem *non_ehci = hcd->regs;
struct device *dev = hcd->self.controller;
struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
@@ -211,18 +228,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
dev_warn(hcd->self.controller, "Could not get controller version\n");
return -ENODEV;
}
+#endif
portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
switch (phy_mode) {
case FSL_USB2_PHY_ULPI:
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
setbits32(non_ehci + FSL_SOC_USB_CTRL,
ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
}
+#endif
portsc |= PORT_PTS_ULPI;
break;
case FSL_USB2_PHY_SERIAL:
@@ -232,6 +252,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
@@ -242,12 +263,14 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
if (pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL,
CTRL_UTMI_PHY_EN);
+#endif
portsc |= PORT_PTS_UTMI;
break;
case FSL_USB2_PHY_NONE:
break;
}
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver &&
(phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
@@ -258,11 +281,14 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
return -EINVAL;
}
}
+#endif
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
+#ifdef CONFIG_FSL_SOC
if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
+#endif
return 0;
}
@@ -271,10 +297,13 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
+#ifdef CONFIG_FSL_SOC
void __iomem *non_ehci = hcd->regs;
+#endif
pdata = dev_get_platdata(hcd->self.controller);
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs) {
/*
* Turn on cache snooping hardware, since some PowerPC platforms
@@ -287,6 +316,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
/* SNOOP2 starts from 0x80000000, size 2G */
out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
}
+#endif
if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
(pdata->operating_mode == FSL_USB2_DR_OTG))
@@ -294,6 +324,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
+#ifdef CONFIG_FSL_SOC
unsigned int chip, rev, svr;
svr = mfspr(SPRN_SVR);
@@ -304,6 +335,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
ehci->has_fsl_port_bug = 1;
+#endif
if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
return -EINVAL;
@@ -313,6 +345,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
}
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs) {
#ifdef CONFIG_FSL_SOC_BOOKE
out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
@@ -323,6 +356,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
}
+#endif
return 0;
}
@@ -346,8 +380,10 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
dev = hcd->self.controller;
pdata = dev_get_platdata(hcd->self.controller);
+#ifdef FSL_SOC
ehci->big_endian_desc = pdata->big_endian_desc;
ehci->big_endian_mmio = pdata->big_endian_mmio;
+#endif
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
@@ -537,18 +573,25 @@ static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
}
#endif /* CONFIG_PPC_MPC512x */
+#ifdef CONFIG_FSL_SOC
static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
return container_of(ehci, struct ehci_fsl, ehci);
}
+#endif
static int ehci_fsl_drv_suspend(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
+#ifdef CONFIG_FSL_SOC
struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
void __iomem *non_ehci = hcd->regs;
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
+#endif
if (of_device_is_compatible(dev->parent->of_node,
"fsl,mpc5121-usb2-dr")) {
@@ -557,33 +600,51 @@ static int ehci_fsl_drv_suspend(struct device *dev)
ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
device_may_wakeup(dev));
+#ifdef CONFIG_FSL_SOC
if (!fsl_deep_sleep())
return 0;
ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable(pdata->clk);
+#endif
return 0;
}
static int ehci_fsl_drv_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
- struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+#ifdef CONFIG_FSL_SOC
+ struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
void __iomem *non_ehci = hcd->regs;
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
+#endif
+
if (of_device_is_compatible(dev->parent->of_node,
"fsl,mpc5121-usb2-dr")) {
return ehci_fsl_mpc512x_drv_resume(dev);
}
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable(pdata->clk);
+#endif
ehci_prepare_ports_for_controller_resume(ehci);
+#ifdef CONFIG_FSL_SOC
if (!fsl_deep_sleep())
return 0;
+#endif
usb_root_hub_lost_power(hcd->self.root_hub);
+#ifdef CONFIG_FSL_SOC
/* Restore USB PHY settings and enable the controller. */
out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
+#endif
ehci_reset(ehci);
ehci_fsl_reinit(ehci);
--
1.7.4
^ permalink raw reply related
* [RFC PATCH 1/2] usb: gadget: fsl_udc: Add support for zynq usb device controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:27 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: linux-usb, linux-kernel, kalluripunnaiahchoudary, kpc528,
Punnaiah Choudary Kalluri, linuxppc-dev, linux-arm-kernel
In-Reply-To: <1398011225-19835-1-git-send-email-punnaia@xilinx.com>
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
drivers/usb/gadget/Kconfig | 2 +-
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/fsl_mxc_udc.c | 21 +++++++++++++++++++++
drivers/usb/gadget/fsl_udc_core.c | 5 +++++
drivers/usb/gadget/fsl_usb2_udc.h | 2 +-
drivers/usb/host/fsl-mph-dr-of.c | 9 +++++++++
6 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 3557c7e..7f18ab47 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -186,7 +186,7 @@ config USB_BCM63XX_UDC
config USB_FSL_USB2
tristate "Freescale Highspeed USB DR Peripheral Controller"
- depends on FSL_SOC || ARCH_MXC
+ depends on FSL_SOC || ARCH_MXC || ARCH_ZYNQ
select USB_FSL_MPH_DR_OF if OF
help
Some of Freescale PowerPC and i.MX processors have a High Speed
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5f150bc..38b009f 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_USB_BCM63XX_UDC) += bcm63xx_udc.o
obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
fsl_usb2_udc-y := fsl_udc_core.o
fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o
+fsl_usb2_udc-$(CONFIG_ARCH_ZYNQ) += fsl_mxc_udc.o
obj-$(CONFIG_USB_M66592) += m66592-udc.o
obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 9b140fc..181245c 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -19,8 +19,10 @@
#include <linux/io.h>
static struct clk *mxc_ahb_clk;
+#ifndef CONFIG_ARCH_ZYNQ
static struct clk *mxc_per_clk;
static struct clk *mxc_ipg_clk;
+#endif
/* workaround ENGcm09152 for i.MX35 */
#define MX35_USBPHYCTRL_OFFSET 0x600
@@ -30,6 +32,7 @@ static struct clk *mxc_ipg_clk;
int fsl_udc_clk_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata;
+#ifndef CONFIG_ARCH_ZYNQ
unsigned long freq;
int ret;
@@ -76,10 +79,21 @@ eclkrate:
clk_disable_unprepare(mxc_per_clk);
mxc_per_clk = NULL;
return ret;
+#else
+ pdata = dev_get_platdata(&pdev->dev);
+ mxc_ahb_clk = devm_clk_get(pdev->dev.parent, NULL);
+ if (IS_ERR(mxc_ahb_clk))
+ return PTR_ERR(mxc_ahb_clk);
+
+ clk_prepare_enable(mxc_ahb_clk);
+
+ return 0;
+#endif
}
int fsl_udc_clk_finalize(struct platform_device *pdev)
{
+#ifndef CONFIG_ARCH_ZYNQ
struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
int ret = 0;
@@ -112,12 +126,19 @@ ioremap_err:
}
return ret;
+#else
+ return 0;
+#endif
}
void fsl_udc_clk_release(void)
{
+#ifndef CONFIG_ARCH_ZYNQ
if (mxc_per_clk)
clk_disable_unprepare(mxc_per_clk);
clk_disable_unprepare(mxc_ahb_clk);
clk_disable_unprepare(mxc_ipg_clk);
+#else
+ clk_disable_unprepare(mxc_ahb_clk);
+#endif
}
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 15960af..c3ff3fb 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -2492,6 +2492,9 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
goto err_free_irq;
}
+#ifdef CONFIG_ARCH_ZYNQ
+ udc_controller->vbus_active = 1;
+#endif
ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
fsl_udc_release);
if (ret)
@@ -2661,8 +2664,10 @@ static const struct platform_device_id fsl_udc_devtype[] = {
MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
static struct platform_driver udc_driver = {
.remove = __exit_p(fsl_udc_remove),
+#ifndef CONFIG_ARCH_ZYNQ
/* Just for FSL i.mx SoC currently */
.id_table = fsl_udc_devtype,
+#endif
/* these suspend and resume are not usb suspend and resume */
.suspend = fsl_udc_suspend,
.resume = fsl_udc_resume,
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index c6703bb..6394138 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -590,7 +590,7 @@ static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep)
}
struct platform_device;
-#ifdef CONFIG_ARCH_MXC
+#if defined CONFIG_ARCH_MXC || defined CONFIG_ARCH_ZYNQ
int fsl_udc_clk_init(struct platform_device *pdev);
int fsl_udc_clk_finalize(struct platform_device *pdev);
void fsl_udc_clk_release(void);
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 9162d1b..7d89415 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -42,6 +42,10 @@ static struct fsl_usb2_dev_data dr_mode_data[] = {
},
};
+#ifdef CONFIG_ARCH_ZYNQ
+static u64 dma_mask = 0xFFFFFFF0;
+#endif
+
static struct fsl_usb2_dev_data *get_dr_mode_data(struct device_node *np)
{
const unsigned char *prop;
@@ -94,7 +98,11 @@ static struct platform_device *fsl_usb2_device_register(
pdev->dev.parent = &ofdev->dev;
pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
+#ifndef CONFIG_ARCH_ZYNQ
*pdev->dev.dma_mask = *ofdev->dev.dma_mask;
+#else
+ pdev->dev.dma_mask = &dma_mask;
+#endif
retval = platform_device_add_data(pdev, pdata, sizeof(*pdata));
if (retval)
@@ -320,6 +328,7 @@ static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
#ifdef CONFIG_PPC_MPC512x
{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
#endif
+ { .compatible = "synopsys,usb2-dr-2.20a", },
{},
};
--
1.7.4
^ permalink raw reply related
* [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:27 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: linux-usb, linux-kernel, kalluripunnaiahchoudary, kpc528,
Punnaiah Choudary Kalluri, linuxppc-dev, linux-arm-kernel
Zynq soc contains a dual role usb controller and this IP is from synopsys. We
observed that there is driver available for this controller from freescale and
decided to reuse this driver for zynq use.
Here is the link for zynq soc TRM. Please refer chapter 15 for usb controller
related information.
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
The following series of patches add initial support for zynq soc in fsl gadget controller
driver and fsl host controller driver.
Based on these patches, I have the following concerns and sugesstions
Since the freescale usb driver is for synopsys IP, Please consider rebranding
this driver name and config options to reflect that it is a sysnopsys IP. So
that other vendors who using this IP can reuse thie driver.
Also the ehci-fsl.c is for powerpc based soc's, and zynq is ARM based, i have
protected the code which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig | 2 +-
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/fsl_mxc_udc.c | 21 ++++++++++++
drivers/usb/gadget/fsl_udc_core.c | 5 +++
drivers/usb/gadget/fsl_usb2_udc.h | 2 +-
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-fsl.c | 63 ++++++++++++++++++++++++++++++++++++-
drivers/usb/host/fsl-mph-dr-of.c | 9 +++++
8 files changed, 101 insertions(+), 4 deletions(-)
--
1.7.4
^ permalink raw reply
* [RFC PATCH 0/2] usb: Reuse fsl driver code for synopsys usb controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:23 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: Punnaiah Choudary Kalluri, linux-usb, linuxppc-dev, linux-kernel,
linux-arm-kernel
Zynq soc contains a dual role usb controller and this IP is from synopsys. We
observed that there is driver available for this controller from freescale and
decided to reuse this driver for zynq use.
Here is the link for zynq soc TRM. Please refer chapter 15 for usb controller
related information.
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
The following series of patches add initial support for zynq soc in fsl gadget controller
driver and fsl host controller driver.
Based on these patches, I have the following concerns and sugesstions
Since the freescale usb driver is for synopsys IP, Please consider rebranding
this driver name and config options to reflect that it is a sysnopsys IP. So
that other vendors who using this IP can reuse thie driver.
Also the ehci-fsl.c is for powerpc based soc's, and zynq is ARM based, i have
protected the code which is specifc to freescale with CONFIG_FSL_SOC. Please
suggest if there is a better way of doing this?
Punnaiah Choudary Kalluri (2):
usb: gadget: fsl_udc: Add support for zynq usb device controller
usb: ehci-fsl: Add support for zynq usb host controller
drivers/usb/gadget/Kconfig | 2 +-
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/fsl_mxc_udc.c | 21 ++++++++++++
drivers/usb/gadget/fsl_udc_core.c | 5 +++
drivers/usb/gadget/fsl_usb2_udc.h | 2 +-
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-fsl.c | 63 ++++++++++++++++++++++++++++++++++++-
drivers/usb/host/fsl-mph-dr-of.c | 9 +++++
8 files changed, 101 insertions(+), 4 deletions(-)
--
1.7.4
^ permalink raw reply
* [RFC PATCH 2/2] usb: ehci-fsl: Add support for zynq usb host controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:23 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: Punnaiah Choudary Kalluri, linux-usb, linuxppc-dev, linux-kernel,
linux-arm-kernel
In-Reply-To: <1398011009-10978-1-git-send-email-punnaia@xilinx.com>
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/ehci-fsl.c | 63 ++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 3d9e540..295274e 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -117,7 +117,7 @@ config XPS_USB_HCD_XILINX
config USB_EHCI_FSL
bool "Support for Freescale PPC on-chip EHCI USB controller"
- depends on FSL_SOC
+ depends on FSL_SOC || ARCH_ZYNQ
select USB_EHCI_ROOT_HUB_TT
select USB_FSL_MPH_DR_OF if OF
---help---
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6f2c8d3..54db34f 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -23,11 +23,13 @@
* Anton Vorontsov <avorontsov@ru.mvista.com>.
*/
+#include <linux/clk.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/err.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>
@@ -86,6 +88,15 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
}
irq = res->start;
+#ifdef CONFIG_ARCH_ZYNQ
+ pdata->clk = devm_clk_get(pdev->dev.parent, NULL);
+ if (IS_ERR(pdata->clk))
+ return PTR_ERR(pdata->clk);
+
+ retval = clk_prepare_enable(pdata->clk);
+ if (retval)
+ return retval;
+#endif
hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
if (!hcd) {
retval = -ENOMEM;
@@ -121,9 +132,11 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
goto err2;
}
+#ifdef CONFIG_FSL_SOC
/* Enable USB controller, 83xx or 8536 */
if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
+#endif
/* Don't need to set host mode here. It will be done by tdi_reset() */
@@ -159,6 +172,9 @@ static int usb_hcd_fsl_probe(const struct hc_driver *driver,
err2:
usb_put_hcd(hcd);
err1:
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable_unprepare(pdata->clk);
+#endif
dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
if (pdata->exit)
pdata->exit(pdev);
@@ -203,6 +219,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
{
u32 portsc;
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+#ifdef CONFIG_FSL_SOC
void __iomem *non_ehci = hcd->regs;
struct device *dev = hcd->self.controller;
struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
@@ -211,18 +228,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
dev_warn(hcd->self.controller, "Could not get controller version\n");
return -ENODEV;
}
+#endif
portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
switch (phy_mode) {
case FSL_USB2_PHY_ULPI:
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
setbits32(non_ehci + FSL_SOC_USB_CTRL,
ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
}
+#endif
portsc |= PORT_PTS_ULPI;
break;
case FSL_USB2_PHY_SERIAL:
@@ -232,6 +252,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
portsc |= PORT_PTS_PTW;
/* fall through */
case FSL_USB2_PHY_UTMI:
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
@@ -242,12 +263,14 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
if (pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL,
CTRL_UTMI_PHY_EN);
+#endif
portsc |= PORT_PTS_UTMI;
break;
case FSL_USB2_PHY_NONE:
break;
}
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs && pdata->controller_ver &&
(phy_mode == FSL_USB2_PHY_ULPI)) {
/* check PHY_CLK_VALID to get phy clk valid */
@@ -258,11 +281,14 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
return -EINVAL;
}
}
+#endif
ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
+#ifdef CONFIG_FSL_SOC
if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
+#endif
return 0;
}
@@ -271,10 +297,13 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
{
struct usb_hcd *hcd = ehci_to_hcd(ehci);
struct fsl_usb2_platform_data *pdata;
+#ifdef CONFIG_FSL_SOC
void __iomem *non_ehci = hcd->regs;
+#endif
pdata = dev_get_platdata(hcd->self.controller);
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs) {
/*
* Turn on cache snooping hardware, since some PowerPC platforms
@@ -287,6 +316,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
/* SNOOP2 starts from 0x80000000, size 2G */
out_be32(non_ehci + FSL_SOC_USB_SNOOP2, 0x80000000 | SNOOP_SIZE_2GB);
}
+#endif
if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
(pdata->operating_mode == FSL_USB2_DR_OTG))
@@ -294,6 +324,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
+#ifdef CONFIG_FSL_SOC
unsigned int chip, rev, svr;
svr = mfspr(SPRN_SVR);
@@ -304,6 +335,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
ehci->has_fsl_port_bug = 1;
+#endif
if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
return -EINVAL;
@@ -313,6 +345,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
return -EINVAL;
}
+#ifdef CONFIG_FSL_SOC
if (pdata->have_sysif_regs) {
#ifdef CONFIG_FSL_SOC_BOOKE
out_be32(non_ehci + FSL_SOC_USB_PRICTRL, 0x00000008);
@@ -323,6 +356,7 @@ static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
#endif
out_be32(non_ehci + FSL_SOC_USB_SICTRL, 0x00000001);
}
+#endif
return 0;
}
@@ -346,8 +380,10 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
dev = hcd->self.controller;
pdata = dev_get_platdata(hcd->self.controller);
+#ifdef FSL_SOC
ehci->big_endian_desc = pdata->big_endian_desc;
ehci->big_endian_mmio = pdata->big_endian_mmio;
+#endif
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
@@ -537,18 +573,25 @@ static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
}
#endif /* CONFIG_PPC_MPC512x */
+#ifdef CONFIG_FSL_SOC
static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
return container_of(ehci, struct ehci_fsl, ehci);
}
+#endif
static int ehci_fsl_drv_suspend(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
+#ifdef CONFIG_FSL_SOC
struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
void __iomem *non_ehci = hcd->regs;
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
+#endif
if (of_device_is_compatible(dev->parent->of_node,
"fsl,mpc5121-usb2-dr")) {
@@ -557,33 +600,51 @@ static int ehci_fsl_drv_suspend(struct device *dev)
ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
device_may_wakeup(dev));
+#ifdef CONFIG_FSL_SOC
if (!fsl_deep_sleep())
return 0;
ehci_fsl->usb_ctrl = in_be32(non_ehci + FSL_SOC_USB_CTRL);
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable(pdata->clk);
+#endif
return 0;
}
static int ehci_fsl_drv_resume(struct device *dev)
{
struct usb_hcd *hcd = dev_get_drvdata(dev);
- struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+#ifdef CONFIG_FSL_SOC
+ struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
void __iomem *non_ehci = hcd->regs;
+#endif
+#ifdef CONFIG_ARCH_ZYNQ
+ struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
+#endif
+
if (of_device_is_compatible(dev->parent->of_node,
"fsl,mpc5121-usb2-dr")) {
return ehci_fsl_mpc512x_drv_resume(dev);
}
+#ifdef CONFIG_ARCH_ZYNQ
+ clk_disable(pdata->clk);
+#endif
ehci_prepare_ports_for_controller_resume(ehci);
+#ifdef CONFIG_FSL_SOC
if (!fsl_deep_sleep())
return 0;
+#endif
usb_root_hub_lost_power(hcd->self.root_hub);
+#ifdef CONFIG_FSL_SOC
/* Restore USB PHY settings and enable the controller. */
out_be32(non_ehci + FSL_SOC_USB_CTRL, ehci_fsl->usb_ctrl);
+#endif
ehci_reset(ehci);
ehci_fsl_reinit(ehci);
--
1.7.4
^ permalink raw reply related
* [RFC PATCH 1/2] usb: gadget: fsl_udc: Add support for zynq usb device controller
From: Punnaiah Choudary Kalluri @ 2014-04-20 16:23 UTC (permalink / raw)
To: leoli, balbi, michal.simek
Cc: Punnaiah Choudary Kalluri, linux-usb, linuxppc-dev, linux-kernel,
linux-arm-kernel
In-Reply-To: <1398011009-10978-1-git-send-email-punnaia@xilinx.com>
Since zynq soc usb controller is a synopsys IP and there is a driver
available for this controller from freescale in opensource, reusing this
driver for zynq use.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
---
drivers/usb/gadget/Kconfig | 2 +-
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/fsl_mxc_udc.c | 21 +++++++++++++++++++++
drivers/usb/gadget/fsl_udc_core.c | 5 +++++
drivers/usb/gadget/fsl_usb2_udc.h | 2 +-
drivers/usb/host/fsl-mph-dr-of.c | 9 +++++++++
6 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 3557c7e..7f18ab47 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -186,7 +186,7 @@ config USB_BCM63XX_UDC
config USB_FSL_USB2
tristate "Freescale Highspeed USB DR Peripheral Controller"
- depends on FSL_SOC || ARCH_MXC
+ depends on FSL_SOC || ARCH_MXC || ARCH_ZYNQ
select USB_FSL_MPH_DR_OF if OF
help
Some of Freescale PowerPC and i.MX processors have a High Speed
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 5f150bc..38b009f 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_USB_BCM63XX_UDC) += bcm63xx_udc.o
obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o
fsl_usb2_udc-y := fsl_udc_core.o
fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o
+fsl_usb2_udc-$(CONFIG_ARCH_ZYNQ) += fsl_mxc_udc.o
obj-$(CONFIG_USB_M66592) += m66592-udc.o
obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index 9b140fc..181245c 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -19,8 +19,10 @@
#include <linux/io.h>
static struct clk *mxc_ahb_clk;
+#ifndef CONFIG_ARCH_ZYNQ
static struct clk *mxc_per_clk;
static struct clk *mxc_ipg_clk;
+#endif
/* workaround ENGcm09152 for i.MX35 */
#define MX35_USBPHYCTRL_OFFSET 0x600
@@ -30,6 +32,7 @@ static struct clk *mxc_ipg_clk;
int fsl_udc_clk_init(struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata;
+#ifndef CONFIG_ARCH_ZYNQ
unsigned long freq;
int ret;
@@ -76,10 +79,21 @@ eclkrate:
clk_disable_unprepare(mxc_per_clk);
mxc_per_clk = NULL;
return ret;
+#else
+ pdata = dev_get_platdata(&pdev->dev);
+ mxc_ahb_clk = devm_clk_get(pdev->dev.parent, NULL);
+ if (IS_ERR(mxc_ahb_clk))
+ return PTR_ERR(mxc_ahb_clk);
+
+ clk_prepare_enable(mxc_ahb_clk);
+
+ return 0;
+#endif
}
int fsl_udc_clk_finalize(struct platform_device *pdev)
{
+#ifndef CONFIG_ARCH_ZYNQ
struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
int ret = 0;
@@ -112,12 +126,19 @@ ioremap_err:
}
return ret;
+#else
+ return 0;
+#endif
}
void fsl_udc_clk_release(void)
{
+#ifndef CONFIG_ARCH_ZYNQ
if (mxc_per_clk)
clk_disable_unprepare(mxc_per_clk);
clk_disable_unprepare(mxc_ahb_clk);
clk_disable_unprepare(mxc_ipg_clk);
+#else
+ clk_disable_unprepare(mxc_ahb_clk);
+#endif
}
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 15960af..c3ff3fb 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -2492,6 +2492,9 @@ static int __init fsl_udc_probe(struct platform_device *pdev)
goto err_free_irq;
}
+#ifdef CONFIG_ARCH_ZYNQ
+ udc_controller->vbus_active = 1;
+#endif
ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
fsl_udc_release);
if (ret)
@@ -2661,8 +2664,10 @@ static const struct platform_device_id fsl_udc_devtype[] = {
MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
static struct platform_driver udc_driver = {
.remove = __exit_p(fsl_udc_remove),
+#ifndef CONFIG_ARCH_ZYNQ
/* Just for FSL i.mx SoC currently */
.id_table = fsl_udc_devtype,
+#endif
/* these suspend and resume are not usb suspend and resume */
.suspend = fsl_udc_suspend,
.resume = fsl_udc_resume,
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index c6703bb..6394138 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -590,7 +590,7 @@ static inline struct ep_queue_head *get_qh_by_ep(struct fsl_ep *ep)
}
struct platform_device;
-#ifdef CONFIG_ARCH_MXC
+#if defined CONFIG_ARCH_MXC || defined CONFIG_ARCH_ZYNQ
int fsl_udc_clk_init(struct platform_device *pdev);
int fsl_udc_clk_finalize(struct platform_device *pdev);
void fsl_udc_clk_release(void);
diff --git a/drivers/usb/host/fsl-mph-dr-of.c b/drivers/usb/host/fsl-mph-dr-of.c
index 9162d1b..7d89415 100644
--- a/drivers/usb/host/fsl-mph-dr-of.c
+++ b/drivers/usb/host/fsl-mph-dr-of.c
@@ -42,6 +42,10 @@ static struct fsl_usb2_dev_data dr_mode_data[] = {
},
};
+#ifdef CONFIG_ARCH_ZYNQ
+static u64 dma_mask = 0xFFFFFFF0;
+#endif
+
static struct fsl_usb2_dev_data *get_dr_mode_data(struct device_node *np)
{
const unsigned char *prop;
@@ -94,7 +98,11 @@ static struct platform_device *fsl_usb2_device_register(
pdev->dev.parent = &ofdev->dev;
pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
+#ifndef CONFIG_ARCH_ZYNQ
*pdev->dev.dma_mask = *ofdev->dev.dma_mask;
+#else
+ pdev->dev.dma_mask = &dma_mask;
+#endif
retval = platform_device_add_data(pdev, pdata, sizeof(*pdata));
if (retval)
@@ -320,6 +328,7 @@ static const struct of_device_id fsl_usb2_mph_dr_of_match[] = {
#ifdef CONFIG_PPC_MPC512x
{ .compatible = "fsl,mpc5121-usb2-dr", .data = &fsl_usb2_mpc5121_pd, },
#endif
+ { .compatible = "synopsys,usb2-dr-2.20a", },
{},
};
--
1.7.4
^ permalink raw reply related
* [PATCH] powerpc: legacy_serial support MVME5100 UARTS with shifted registers
From: Stephen Chivers @ 2014-04-19 23:43 UTC (permalink / raw)
To: benh; +Cc: schivers, linuxppc-dev, cproctor
This patch adds support to legacy serial for
UARTS with shifted registers.
The MVME5100 Single Board Computer is a PowerPC platform
that has 16550 style UARTS with register addresses that are
16 bytes apart (shifted by 4).
Commit 309257484cc1a592e8ac5fbdd8cd661be2b80bf8
"powerpc: Cleanup udbg_16550 and add support for LPC PIO-only UARTs"
added support to udbg_16550 for shifted registers by adding a "stride"
parameter to the initialisation operations for Programmed IO and
Memory Mapped IO.
As a consequence it is now possible to use the services of legacy serial
to provide early serial console messages for the MVME5100.
An added benefit of this is that the serial console will always be
"ttyS0" irrespective of whether the computer is fitted with extra
PCI 8250 interface boards or not.
I have tested this patch using the four PowerPC platforms available to me:
MVME5100 - shifted registers,
SAM440EP - unshifted registers,
MPC8349 - unshifted registers,
MVME4100 - unshifted registers.
Signed-off-by: Stephen Chivers <schivers@csc.com>
---
arch/powerpc/kernel/legacy_serial.c | 21 +++++++++++++++------
arch/powerpc/platforms/embedded6xx/Kconfig | 1 +
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/legacy_serial.c b/arch/powerpc/kernel/legacy_serial.c
index 40bd7bd..85fb16e 100644
--- a/arch/powerpc/kernel/legacy_serial.c
+++ b/arch/powerpc/kernel/legacy_serial.c
@@ -71,8 +71,9 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
phys_addr_t taddr, unsigned long irq,
upf_t flags, int irq_check_parent)
{
- const __be32 *clk, *spd;
+ const __be32 *clk, *spd, *rs;
u32 clock = BASE_BAUD * 16;
+ u32 shift = 0;
int index;
/* get clock freq. if present */
@@ -83,6 +84,11 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
/* get default speed if present */
spd = of_get_property(np, "current-speed", NULL);
+ /* get register shift if present */
+ rs = of_get_property(np, "reg-shift", NULL);
+ if (rs && *rs)
+ shift = be32_to_cpup(rs);
+
/* If we have a location index, then try to use it */
if (want_index >= 0 && want_index < MAX_LEGACY_SERIAL_PORTS)
index = want_index;
@@ -126,6 +132,7 @@ static int __init add_legacy_port(struct device_node *np, int want_index,
legacy_serial_ports[index].uartclk = clock;
legacy_serial_ports[index].irq = irq;
legacy_serial_ports[index].flags = flags;
+ legacy_serial_ports[index].regshift = shift;
legacy_serial_infos[index].taddr = taddr;
legacy_serial_infos[index].np = of_node_get(np);
legacy_serial_infos[index].clock = clock;
@@ -163,9 +170,8 @@ static int __init add_legacy_soc_port(struct device_node *np,
if (of_get_property(np, "clock-frequency", NULL) == NULL)
return -1;
- /* if reg-shift or offset, don't try to use it */
- if ((of_get_property(np, "reg-shift", NULL) != NULL) ||
- (of_get_property(np, "reg-offset", NULL) != NULL))
+ /* if reg-offset don't try to use it */
+ if ((of_get_property(np, "reg-offset", NULL) != NULL))
return -1;
/* if rtas uses this device, don't try to use it as well */
@@ -315,17 +321,20 @@ static void __init setup_legacy_serial_console(int console)
struct legacy_serial_info *info = &legacy_serial_infos[console];
struct plat_serial8250_port *port = &legacy_serial_ports[console];
void __iomem *addr;
+ unsigned int stride;
+
+ stride = 1 << port->regshift;
/* Check if a translated MMIO address has been found */
if (info->taddr) {
addr = ioremap(info->taddr, 0x1000);
if (addr == NULL)
return;
- udbg_uart_init_mmio(addr, 1);
+ udbg_uart_init_mmio(addr, stride);
} else {
/* Check if it's PIO and we support untranslated PIO */
if (port->iotype == UPIO_PORT && isa_io_special)
- udbg_uart_init_pio(port->iobase, 1);
+ udbg_uart_init_pio(port->iobase, stride);
else
return;
}
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index 2a7024d..a25f496 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -65,6 +65,7 @@ config MVME5100
select PPC_INDIRECT_PCI
select PPC_I8259
select PPC_NATIVE
+ select PPC_UDBG_16550
help
This option enables support for the Motorola (now Emerson) MVME5100
board.
^ permalink raw reply related
* Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
From: Leif Lindholm @ 2014-04-19 0:36 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree@vger.kernel.org, linuxppc-dev,
linux-kernel@vger.kernel.org, Linaro Patches
In-Reply-To: <CAL_Jsq+L14rgYq5swC3H109DThiyDajmTJpO=y562jcE97K-fg@mail.gmail.com>
On Fri, Apr 18, 2014 at 04:28:17PM -0500, Rob Herring wrote:
> >> > Apart from the current code permitting recreating a 15+ year old
> >> > firmware bug into completely new platform ports?
> >>
> >> I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here.
> >
> > In addition to, or instead of, the QUIRK ifdef?
>
> Instead of because I don't see how you handle the ARM board
> compatibility with the ifdef. (And please, no ifdef for that board).
Umm, according to my memory as well as my sent mail folder, I cc:d you
on v2 of part 3. Could you have a look at that, please?
A WARN_ON would still mean this ancient workaround for a specific ppc32
platform remains enabled on ~10 architectures that don't use it.
> >> Really, I would like to see quirks like this fixed up out of line from
> >> the normal flow somewhat like how PCI quirks are handled. So in this
> >> example, we would just add the missing property to the dtb for the
> >> broken platform before doing the memory scan. That does then require
> >> libfdt which is something I'm working on.
> >
> > Getting rid of all this handling from generic code would clearly be
> > preferable. Is that code going in in the near future, or could we add
> > the quirk as a stopgap?
>
> Some sort of quirk infrastructure is not going to happen soon. It's
> just an idea bouncing in my head ATM.
Mmm...
> > What would be the effect of the UEFI code adding all its memblocks,
> > minus the reserved areas, and then the DT code doing a memblock_add
> > of all RAM (including reserved areas)? Would memblock_reserve()s on
> > the protected regions suffice to prevent crazy stuff from happening?
>
> So use UEFI to add the memory, but then add reserved areas with DT?
No, to add memory and reserved areas based on UEFI memory map.
And then add any memory@0/!type nodes as well, if they're left around.
> I'm not sure I follow, but even if I did I don't know memblock code
> well enough to say what it would do.
If we did end up with stray memory@0/!type nodes, we could initialise
memblock multiple times with overlapping but incompatible areas.
And I don't know if that would be a problem. Which makes me a little
bit nervous.
/
Leif
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: Updated device trees for platforms with corenet version 2
From: Scott Wood @ 2014-04-18 22:07 UTC (permalink / raw)
To: Diana Craciun; +Cc: linuxppc-dev
In-Reply-To: <1397834470-12844-1-git-send-email-diana.craciun@freescale.com>
On Fri, 2014-04-18 at 18:21 +0300, Diana Craciun wrote:
> From: Diana Craciun <Diana.Craciun@freescale.com>
>
> Updated the device trees according to the corenet-cf
> binding definition.
>
> Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
> ---
> arch/powerpc/boot/dts/b4860emu.dts | 2 +-
> arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 4 ----
> arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 4 ----
> arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 2 +-
> arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 2 +-
> arch/powerpc/boot/dts/t4240emu.dts | 2 +-
> 6 files changed, 4 insertions(+), 12 deletions(-)
Could you update the corenet version 1 trees as well?
-Scott
^ permalink raw reply
* Re: [PATCH v2] powerpc/fsl: Added binding for Freescale CoreNet coherency fabric (CCF)
From: Scott Wood @ 2014-04-18 21:33 UTC (permalink / raw)
To: Diana Craciun; +Cc: devicetree, linuxppc-dev
In-Reply-To: <1397833917-12611-1-git-send-email-diana.craciun@freescale.com>
On Fri, 2014-04-18 at 18:11 +0300, Diana Craciun wrote:
> From: Diana Craciun <Diana.Craciun@freescale.com>
>
> The CoreNet coherency fabric is a fabric-oriented, conectivity
> infrastructure that enables the implementation of coherent, multicore
> systems. The CCF acts as a central interconnect for cores,
> platform-level caches, memory subsystem, peripheral devices and I/O host
> bridges in the system.
>
> Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
> ---
> .../devicetree/bindings/powerpc/fsl/ccf.txt | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
>
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
> new file mode 100644
> index 0000000..f0b7143
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/ccf.txt
> @@ -0,0 +1,36 @@
> +Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
> +
> +DESCRIPTION
> +
> +The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
> +that enables the implementation of coherent, multicore systems.
> +
> +Required properties:
> +
> +- compatible : <string>
> + Must include "fsl,corenetX-cf", "fsl,corenet-cf" - CoreNet coherency
> + fabric version X
Specify "fsl,corenet1-cf" and "fsl,corenet2-cf" rather than
"fsl,corenetX-cf" (given there's nothing in a chip manual that you can
correlate with the value of X), and provide example chips for each.
Also specify that "fsl,corenet-cf" represents the registers that are
common between the two versions (not arbitrary "fsl,corenetX-cf" -- if
there's ever an "fsl,corenet3-cf" it may not be compatible with this),
and is retained for compatibility reasons.
-Scott
^ permalink raw reply
* Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
From: Rob Herring @ 2014-04-18 21:28 UTC (permalink / raw)
To: Leif Lindholm
Cc: Mark Rutland, devicetree@vger.kernel.org, linuxppc-dev,
linux-kernel@vger.kernel.org, Linaro Patches
In-Reply-To: <20140418201313.GG5904@bivouac.eciton.net>
On Fri, Apr 18, 2014 at 3:13 PM, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Fri, Apr 18, 2014 at 10:37:58AM -0500, Rob Herring wrote:
>> >> But why do you need this?
>> >
>> > Apart from the current code permitting recreating a 15+ year old
>> > firmware bug into completely new platform ports?
>>
>> I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here.
>
> In addition to, or instead of, the QUIRK ifdef?
Instead of because I don't see how you handle the ARM board
compatibility with the ifdef. (And please, no ifdef for that board).
>> Really, I would like to see quirks like this fixed up out of line from
>> the normal flow somewhat like how PCI quirks are handled. So in this
>> example, we would just add the missing property to the dtb for the
>> broken platform before doing the memory scan. That does then require
>> libfdt which is something I'm working on.
>
> Getting rid of all this handling from generic code would clearly be
> preferable. Is that code going in in the near future, or could we add
> the quirk as a stopgap?
Some sort of quirk infrastructure is not going to happen soon. It's
just an idea bouncing in my head ATM.
>> > Because the UEFI stub for arm/arm64 needs to delete all of the "memory"
>> > nodes from the DT. And it would be nice to at least not have to compile
>> > the "and also delete anything called memory@0" into the arm64 image. Or
>> > any image not including support for affected platforms.
>>
>> I don't see why you would handle that in the EFI stub. Given our lack
>> of validation, I can see there is a chance this happens but I think it
>> is pretty small. Given we only have a ARM board, I'd say we are doing
>> surprisingly well.
>
> I'm not too bothered personally, but Mark Rutland handed me a patch to
> improve the memory node handling in the stub, and he seemed to really
> want this there. You guys can fight it out :)
Simply put, we shouldn't put work-arounds in new code for new platforms.
> What would be the effect of the UEFI code adding all its memblocks,
> minus the reserved areas, and then the DT code doing a memblock_add
> of all RAM (including reserved areas)? Would memblock_reserve()s on
> the protected regions suffice to prevent crazy stuff from happening?
So use UEFI to add the memory, but then add reserved areas with DT?
I'm not sure I follow, but even if I did I don't know memblock code
well enough to say what it would do.
Rob
^ permalink raw reply
* Re: [PATCH 0/3] of: dts: enable memory@0 quirk for PPC32 only
From: Leif Lindholm @ 2014-04-18 20:13 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree@vger.kernel.org, linuxppc-dev,
linux-kernel@vger.kernel.org, Linaro Patches
In-Reply-To: <CAL_JsqKdFyhHfkcC1E9QuKjQTrXwoELYG+CFTpgf2-jqDvxGmA@mail.gmail.com>
On Fri, Apr 18, 2014 at 10:37:58AM -0500, Rob Herring wrote:
> >> But why do you need this?
> >
> > Apart from the current code permitting recreating a 15+ year old
> > firmware bug into completely new platform ports?
>
> I would prefer to see a "WARN_ON(!IS_ENABLED(CONFIG_PPC32));" added here.
In addition to, or instead of, the QUIRK ifdef?
> Really, I would like to see quirks like this fixed up out of line from
> the normal flow somewhat like how PCI quirks are handled. So in this
> example, we would just add the missing property to the dtb for the
> broken platform before doing the memory scan. That does then require
> libfdt which is something I'm working on.
Getting rid of all this handling from generic code would clearly be
preferable. Is that code going in in the near future, or could we add
the quirk as a stopgap?
> > Because the UEFI stub for arm/arm64 needs to delete all of the "memory"
> > nodes from the DT. And it would be nice to at least not have to compile
> > the "and also delete anything called memory@0" into the arm64 image. Or
> > any image not including support for affected platforms.
>
> I don't see why you would handle that in the EFI stub. Given our lack
> of validation, I can see there is a chance this happens but I think it
> is pretty small. Given we only have a ARM board, I'd say we are doing
> surprisingly well.
I'm not too bothered personally, but Mark Rutland handed me a patch to
improve the memory node handling in the stub, and he seemed to really
want this there. You guys can fight it out :)
What would be the effect of the UEFI code adding all its memblocks,
minus the reserved areas, and then the DT code doing a memblock_add
of all RAM (including reserved areas)? Would memblock_reserve()s on
the protected regions suffice to prevent crazy stuff from happening?
/
Leif
^ permalink raw reply
* [PATCH] powerpc/mpc85xx: Remove P1023 RDS support
From: Lijun Pan @ 2014-04-18 17:18 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Lijun Pan, Emilian.Medve
P1023RDS is no longer supported by Freescale while P1023RDB is still supported.
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com>
---
arch/powerpc/boot/dts/p1023rds.dts | 219 ---------------------
arch/powerpc/configs/mpc85xx_defconfig | 1 -
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 -
arch/powerpc/platforms/85xx/Kconfig | 6 +-
arch/powerpc/platforms/85xx/Makefile | 2 +-
.../platforms/85xx/{p1023_rds.c => p1023_rdb.c} | 36 +---
6 files changed, 10 insertions(+), 255 deletions(-)
delete mode 100644 arch/powerpc/boot/dts/p1023rds.dts
rename arch/powerpc/platforms/85xx/{p1023_rds.c => p1023_rdb.c} (75%)
diff --git a/arch/powerpc/boot/dts/p1023rds.dts b/arch/powerpc/boot/dts/p1023rds.dts
deleted file mode 100644
index beb6cb1..0000000
--- a/arch/powerpc/boot/dts/p1023rds.dts
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * P1023 RDS Device Tree Source
- *
- * Copyright 2010-2011 Freescale Semiconductor Inc.
- *
- * Author: Roy Zang <tie-fei.zang@freescale.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Freescale Semiconductor nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/include/ "fsl/p1023si-pre.dtsi"
-
-/ {
- model = "fsl,P1023";
- compatible = "fsl,P1023RDS";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
-
- memory {
- device_type = "memory";
- };
-
- soc: soc@ff600000 {
- ranges = <0x0 0x0 0xff600000 0x200000>;
-
- i2c@3000 {
- rtc@68 {
- compatible = "dallas,ds1374";
- reg = <0x68>;
- };
- };
-
- spi@7000 {
- fsl_dataflash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "atmel,at45db081d";
- reg = <0>;
- spi-max-frequency = <40000000>; /* input clock */
- partition@u-boot {
- /* 512KB for u-boot Bootloader Image */
- label = "u-boot-spi";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
- partition@dtb {
- /* 512KB for DTB Image */
- label = "dtb-spi";
- reg = <0x00080000 0x00080000>;
- read-only;
- };
- };
- };
-
- usb@22000 {
- dr_mode = "host";
- phy_type = "ulpi";
- };
- };
-
- lbc: localbus@ff605000 {
- reg = <0 0xff605000 0 0x1000>;
-
- /* NOR Flash, BCSR */
- ranges = <0x0 0x0 0x0 0xee000000 0x02000000
- 0x1 0x0 0x0 0xe0000000 0x00008000>;
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x02000000>;
- bank-width = <2>;
- device-width = <1>;
- partition@0 {
- label = "ramdisk";
- reg = <0x00000000 0x01c00000>;
- };
- partition@1c00000 {
- label = "kernel";
- reg = <0x01c00000 0x002e0000>;
- };
- partiton@1ee0000 {
- label = "dtb";
- reg = <0x01ee0000 0x00020000>;
- };
- partition@1f00000 {
- label = "firmware";
- reg = <0x01f00000 0x00080000>;
- read-only;
- };
- partition@1f80000 {
- label = "u-boot";
- reg = <0x01f80000 0x00080000>;
- read-only;
- };
- };
-
- fpga@1,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,p1023rds-fpga";
- reg = <1 0 0x8000>;
- ranges = <0 1 0 0x8000>;
-
- bcsr@20 {
- compatible = "fsl,p1023rds-bcsr";
- reg = <0x20 0x20>;
- };
- };
- };
-
- pci0: pcie@ff60a000 {
- reg = <0 0xff60a000 0 0x1000>;
- ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
- pcie@0 {
- /* IRQ[0:3] are pulled up on board, set to active-low */
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 0 1 0 0
- 0000 0 0 2 &mpic 1 1 0 0
- 0000 0 0 3 &mpic 2 1 0 0
- 0000 0 0 4 &mpic 3 1 0 0
- >;
- ranges = <0x2000000 0x0 0xc0000000
- 0x2000000 0x0 0xc0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-
- board_pci1: pci1: pcie@ff609000 {
- reg = <0 0xff609000 0 0x1000>;
- ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
- pcie@0 {
- /*
- * IRQ[4:6] only for PCIe, set to active-high,
- * IRQ[7] is pulled up on board, set to active-low
- */
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 4 2 0 0
- 0000 0 0 2 &mpic 5 2 0 0
- 0000 0 0 3 &mpic 6 2 0 0
- 0000 0 0 4 &mpic 7 1 0 0
- >;
- ranges = <0x2000000 0x0 0xa0000000
- 0x2000000 0x0 0xa0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-
- pci2: pcie@ff60b000 {
- reg = <0 0xff60b000 0 0x1000>;
- ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
- 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
- pcie@0 {
- /*
- * IRQ[8:10] are pulled up on board, set to active-low
- * IRQ[11] only for PCIe, set to active-high,
- */
- interrupt-map-mask = <0xf800 0 0 7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0 0 1 &mpic 8 1 0 0
- 0000 0 0 2 &mpic 9 1 0 0
- 0000 0 0 3 &mpic 10 1 0 0
- 0000 0 0 4 &mpic 11 2 0 0
- >;
- ranges = <0x2000000 0x0 0x80000000
- 0x2000000 0x0 0x80000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x100000>;
- };
- };
-};
-
-/include/ "fsl/p1023si-post.dtsi"
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 19f0fbe..55765c8 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -32,7 +32,6 @@ CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
CONFIG_P1023_RDB=y
-CONFIG_P1023_RDS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 062312e..5c6ecdc 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -35,7 +35,6 @@ CONFIG_P1010_RDB=y
CONFIG_P1022_DS=y
CONFIG_P1022_RDK=y
CONFIG_P1023_RDB=y
-CONFIG_P1023_RDS=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_XES_MPC85xx=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index c17aae8..f049c2a 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -117,11 +117,11 @@ config P1022_RDK
This option enables support for the Freescale / iVeia P1022RDK
reference board.
-config P1023_RDS
- bool "Freescale P1023 RDS/RDB"
+config P1023_RDB
+ bool "Freescale P1023 RDB"
select DEFAULT_UIMAGE
help
- This option enables support for the P1023 RDS and RDB boards
+ This option enables support for the P1023 RDB board.
config TWR_P102x
bool "Freescale TWR-P102x"
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 25cebe7..822103e 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -17,7 +17,7 @@ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
obj-$(CONFIG_P1022_DS) += p1022_ds.o
obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
-obj-$(CONFIG_P1023_RDS) += p1023_rds.o
+obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
obj-$(CONFIG_TWR_P102x) += twr_p102x.o
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
diff --git a/arch/powerpc/platforms/85xx/p1023_rds.c b/arch/powerpc/platforms/85xx/p1023_rdb.c
similarity index 75%
rename from arch/powerpc/platforms/85xx/p1023_rds.c
rename to arch/powerpc/platforms/85xx/p1023_rdb.c
index 0e61400..d5b7509 100644
--- a/arch/powerpc/platforms/85xx/p1023_rds.c
+++ b/arch/powerpc/platforms/85xx/p1023_rdb.c
@@ -4,7 +4,7 @@
* Author: Roy Zang <tie-fei.zang@freescale.com>
*
* Description:
- * P1023 RDS Board Setup
+ * P1023 RDB Board Setup
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -41,12 +41,12 @@
* Setup the architecture
*
*/
-static void __init mpc85xx_rds_setup_arch(void)
+static void __init mpc85xx_rdb_setup_arch(void)
{
struct device_node *np;
if (ppc_md.progress)
- ppc_md.progress("p1023_rds_setup_arch()", 0);
+ ppc_md.progress("p1023_rdb_setup_arch()", 0);
/* Map BCSR area */
np = of_find_node_by_name(NULL, "bcsr");
@@ -85,10 +85,9 @@ static void __init mpc85xx_rds_setup_arch(void)
fsl_pci_assign_primary();
}
-machine_arch_initcall(p1023_rds, mpc85xx_common_publish_devices);
machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
-static void __init mpc85xx_rds_pic_init(void)
+static void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
MPIC_SINGLE_DEST_CPU,
@@ -99,14 +98,6 @@ static void __init mpc85xx_rds_pic_init(void)
mpic_init(mpic);
}
-static int __init p1023_rds_probe(void)
-{
- unsigned long root = of_get_flat_dt_root();
-
- return of_flat_dt_is_compatible(root, "fsl,P1023RDS");
-
-}
-
static int __init p1023_rdb_probe(void)
{
unsigned long root = of_get_flat_dt_root();
@@ -115,26 +106,11 @@ static int __init p1023_rdb_probe(void)
}
-define_machine(p1023_rds) {
- .name = "P1023 RDS",
- .probe = p1023_rds_probe,
- .setup_arch = mpc85xx_rds_setup_arch,
- .init_IRQ = mpc85xx_rds_pic_init,
- .get_irq = mpic_get_irq,
- .restart = fsl_rstcr_restart,
- .calibrate_decr = generic_calibrate_decr,
- .progress = udbg_progress,
-#ifdef CONFIG_PCI
- .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
- .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
-#endif
-};
-
define_machine(p1023_rdb) {
.name = "P1023 RDB",
.probe = p1023_rdb_probe,
- .setup_arch = mpc85xx_rds_setup_arch,
- .init_IRQ = mpc85xx_rds_pic_init,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
.get_irq = mpic_get_irq,
.restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
--
1.8.5.3
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox