* [PATCH V2] KVM: PPC: BOOK3S: PR: Fix PURR and SPURR emulation
From: Aneesh Kumar K.V @ 2014-06-04 11:17 UTC (permalink / raw)
To: agraf, benh, paulus; +Cc: linuxppc-dev, kvm, kvm-ppc, Aneesh Kumar K.V
We use time base for PURR and SPURR emulation with PR KVM since we
are emulating a single threaded core. When using time base
we need to make sure that we don't accumulate time spent in the host
in PURR and SPURR value.
Also we don't need to emulate mtspr because both the registers are
hypervisor resource.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
Changes from V1:
Move the purr/spurr update to happen only once in case of exit with preemption enabled.
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.c | 16 ++++++++--------
arch/powerpc/kvm/book3s_pr.c | 11 +++++++++++
4 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index f52f65694527..a20cc0bbd048 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -83,8 +83,6 @@ struct kvmppc_vcpu_book3s {
u64 sdr1;
u64 hior;
u64 msr_mask;
- u64 purr_offset;
- u64 spurr_offset;
#ifdef CONFIG_PPC_BOOK3S_32
u32 vsid_pool[VSID_POOL_SIZE];
u32 vsid_next;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index bb66d8b8efdf..4a58731a0a72 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -503,8 +503,8 @@ struct kvm_vcpu_arch {
#ifdef CONFIG_BOOKE
u32 decar;
#endif
- u32 tbl;
- u32 tbu;
+ /* Time base value when we entered the guest */
+ u64 entry_tb;
u32 tcr;
ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
u32 ivor[64];
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 3f295269af37..3565e775b61b 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -439,12 +439,6 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
(mfmsr() & MSR_HV))
vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
break;
- case SPRN_PURR:
- to_book3s(vcpu)->purr_offset = spr_val - get_tb();
- break;
- case SPRN_SPURR:
- to_book3s(vcpu)->spurr_offset = spr_val - get_tb();
- break;
case SPRN_GQR0:
case SPRN_GQR1:
case SPRN_GQR2:
@@ -572,10 +566,16 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
*spr_val = 0;
break;
case SPRN_PURR:
- *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
+ /*
+ * On exit we would have updated purr
+ */
+ *spr_val = vcpu->arch.purr;
break;
case SPRN_SPURR:
- *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
+ /*
+ * On exit we would have updated spurr
+ */
+ *spr_val = vcpu->arch.spurr;
break;
case SPRN_GQR0:
case SPRN_GQR1:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 23367a7e44c3..ff15f8e31a27 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -120,6 +120,11 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
#ifdef CONFIG_PPC_BOOK3S_64
svcpu->shadow_fscr = vcpu->arch.shadow_fscr;
#endif
+ /*
+ * Now also save the current time base value. We use this
+ * to find the guest purr and spurr value.
+ */
+ vcpu->arch.entry_tb = get_tb();
svcpu->in_use = true;
}
@@ -166,6 +171,12 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
#ifdef CONFIG_PPC_BOOK3S_64
vcpu->arch.shadow_fscr = svcpu->shadow_fscr;
#endif
+ /*
+ * Update purr and spurr using time base on exit.
+ */
+ vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
+ vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
+
svcpu->in_use = false;
out:
--
1.9.1
^ permalink raw reply related
* [PATCH v2 2/2] powerpc/powernv: Enable POWER8 doorbell IPIs
From: Michael Neuling @ 2014-06-04 11:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Preeti U Murthy, Paul Mackerras, linuxppc-dev, Anton Blanchard
In-Reply-To: <1401868995.9903.4.camel@concordia>
This patch enables POWER8 doorbell IPIs on powernv.
Since doorbells can only IPI within a core, we test to see when we can use
doorbells and if not we fall back to XICS. This also enables hypervisor
doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit.
Based on tests by Anton, the best case IPI latency between two threads drop=
ped
from 894ns to 512ns.
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
v2:
Adds select of PPC_DOORBELL for PSERIES and POWERNV as suggested by mpe.
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cp=
u_setup_power.S
index 1557e7c..4673353 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
li r0,0
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
+ ori r3, r3, LPCR_PECEDH
bl __init_LPCR
bl __init_HFSCR
bl __init_tlb_power8
@@ -74,6 +75,7 @@ _GLOBAL(__restore_cpu_power8)
li r0,0
mtspr SPRN_LPID,r0
mfspr r3,SPRN_LPCR
+ ori r3, r3, LPCR_PECEDH
bl __init_LPCR
bl __init_HFSCR
bl __init_tlb_power8
diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platform=
s/powernv/Kconfig
index c252ee9..45a8ed0 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -17,6 +17,7 @@ config PPC_POWERNV
select CPU_FREQ_GOV_USERSPACE
select CPU_FREQ_GOV_ONDEMAND
select CPU_FREQ_GOV_CONSERVATIVE
+ select PPC_DOORBELL
default y
=20
config PPC_POWERNV_RTAS
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/=
powernv/smp.c
index 0062a43..5fcfcf4 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -32,6 +32,7 @@
#include <asm/opal.h>
#include <asm/runlatch.h>
#include <asm/code-patching.h>
+#include <asm/dbell.h>
=20
#include "powernv.h"
=20
@@ -46,6 +47,11 @@ static void pnv_smp_setup_cpu(int cpu)
{
if (cpu !=3D boot_cpuid)
xics_setup_cpu();
+
+#ifdef CONFIG_PPC_DOORBELL
+ if (cpu_has_feature(CPU_FTR_DBELL))
+ doorbell_setup_this_cpu();
+#endif
}
=20
int pnv_smp_kick_cpu(int nr)
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platform=
s/pseries/Kconfig
index 2cb8b77..756b482 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -21,6 +21,7 @@ config PPC_PSERIES
select HAVE_CONTEXT_TRACKING
select HOTPLUG_CPU if SMP
select ARCH_RANDOM
+ select PPC_DOORBELL
default y
=20
config PPC_SPLPAR
diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xi=
cs/icp-native.c
index 9dee470..de8d948 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -26,6 +26,7 @@
#include <asm/errno.h>
#include <asm/xics.h>
#include <asm/kvm_ppc.h>
+#include <asm/dbell.h>
=20
struct icp_ipl {
union {
@@ -145,7 +146,13 @@ static unsigned int icp_native_get_irq(void)
static void icp_native_cause_ipi(int cpu, unsigned long data)
{
kvmppc_set_host_ipi(cpu, 1);
- icp_native_set_qirr(cpu, IPI_PRIORITY);
+#ifdef CONFIG_PPC_DOORBELL
+ if (cpu_has_feature(CPU_FTR_DBELL) &&
+ (cpumask_test_cpu(cpu, cpu_sibling_mask(smp_processor_id()))))
+ doorbell_cause_ipi(cpu, data);
+ else
+#endif
+ icp_native_set_qirr(cpu, IPI_PRIORITY);
}
=20
void xics_wake_cpu(int cpu)
^ permalink raw reply related
* Re: [PATCH] KVM: PPC: BOOK3S: PR: Fix PURR and SPURR emulation
From: Aneesh Kumar K.V @ 2014-06-04 10:45 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, agraf, kvm-ppc, kvm
In-Reply-To: <20140604041547.GA32223@drongo>
Paul Mackerras <paulus@samba.org> writes:
> On Tue, Jun 03, 2014 at 05:46:11PM +0530, Aneesh Kumar K.V wrote:
>> We use time base for PURR and SPURR emulation with PR KVM since we
>> are emulating a single threaded core. When using time base
>> we need to make sure that we don't accumulate time spent in the host
>> in PURR and SPURR value.
>
> Mostly looks good except for this...
>
>> @@ -170,6 +175,11 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
>>
>> out:
>> preempt_enable();
>> + /*
>> + * Update purr and spurr using time base
>> + */
>> + vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
>> + vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
>
> You need to do those updates before the "out:" label. Otherwise if
> this function gets called with !svcpu->in_use (which can happen if
> CONFIG_PREEMPT is enabled) we would do these updates a second time for
> one guest exit. The thing is that kvmppc_copy_from_svcpu() can get
> called from kvmppc_core_vcpu_put_pr() if the vcpu task gets preempted
> on the way out from the guest before we get to the regular call of
> kvmppc_copy_from_svcpu(). It would then get called again when the
> task gets to run, but this time it does nothing because svcpu->in_use
> is false.
Looking at the code, since we enable MSR.EE early now, we might possibly
end up calling this function late in the guest exit path. That
implies, we may account that time (time spent after a preempt immediately
following a guest exit) in purr/spurr. I guess that amount of inaccuracy is
ok, because that is the best we could do here ?
-aneesh
^ permalink raw reply
* Re: [PATCH] PPC: BOOK3S: Disable/Enable TM looking at the ibm, pa-features device tree entry
From: Aneesh Kumar K.V @ 2014-06-04 10:36 UTC (permalink / raw)
To: Michael Neuling; +Cc: linuxppc-dev, paulus
In-Reply-To: <871twcbvyn.fsf@linux.vnet.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
>
>> Michael Neuling <mikey@neuling.org> writes:
>>
>>> Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> wrote:
>>>
>>>> Runtime disable transactional memory feature looking at pa-features
>>>> device tree entry. This provides a mechanism to disable TM on P8
>>>> systems.
>>>
>>> What are we actually achieving with this?
>>
>> PAPR compliance :) ? Also I wanted to disable guest kernel from doing
>> TM related save restore. Guest kernel already look at the cpu feature
>> before doing that. Hence needed a mechanism to disable the feature.
>>
>> Things like
>>
>> static inline void __switch_to_tm(struct task_struct *prev)
>> {
>> if (cpu_has_feature(CPU_FTR_TM)) {
>> tm_enable();
>> tm_reclaim_task(prev);
>> }
>> }
>>
>>
>>>
>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>>>> ---
>>>> arch/powerpc/kernel/prom.c | 5 +++++
>>>> 1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
>>>> index 668aa4791fd7..537bd7e7db0b 100644
>>>> --- a/arch/powerpc/kernel/prom.c
>>>> +++ b/arch/powerpc/kernel/prom.c
>>>> @@ -161,6 +161,11 @@ static struct ibm_pa_feature {
>>>> {CPU_FTR_NODSISRALIGN, 0, 0, 1, 1, 1},
>>>> {0, MMU_FTR_CI_LARGE_PAGE, 0, 1, 2, 0},
>>>> {CPU_FTR_REAL_LE, PPC_FEATURE_TRUE_LE, 5, 0, 0},
>>>> + /*
>>>> + * We should use CPU_FTR_TM_COMP so that if we disable TM, it won't get
>>>> + * enabled via device tree
>>>> + */
>>>> + {CPU_FTR_TM_COMP, 0, 0, 22, 0, 0},
>>>
>>> What does this do to guests? Will it turn TM unavailable into an
>>> illegal instruction?
>>>
>>
>> Good suggestion. I guess it should be facility unavailable interrupt ?
>> I should also make the sure __init_HFSCR only set HFSCR_TM only if the
>> cpu feature is enabled ?
>
> I looked at this and I guess we don't need to update HFSCR considering
> that the guest kernel (privileged) access to TM always happen within
> if (cpu_has_feature(CPU_FTR_TM)) conditional block. Also we want to
> disable this per guest and there is no easy way to suggest hypervisor
> that disable TM in HFSCR.
>
> BTW we already do this for guest problme state. We do in guest kernel
>
> if (cpu_has_feature(CPU_FTR_TM))
> regs->msr |= MSR_TM;
>
> IIUC that should result in facility unavailable interrupt when problem
> state try to access TM ?
>
> I will try to run some test with the patch and update here.
This will actually result in illegal instruction.
-aneesh
^ permalink raw reply
* Re: [PATCH 1/1] powerpc: correct DSCR during TM context switch
From: Michael Neuling @ 2014-06-04 10:03 UTC (permalink / raw)
To: Michael Ellerman; +Cc: aik, benh, linuxppc-dev, Sam Bobroff, khandual
In-Reply-To: <1401867077.9903.3.camel@concordia>
On Wed, 2014-06-04 at 17:31 +1000, Michael Ellerman wrote:
> Hi Sam,
>=20
> Comments inline ..
Ditto....
>=20
> On Wed, 2014-06-04 at 13:33 +1000, Sam Bobroff wrote:
> > Correct the DSCR SPR becoming temporarily corrupted when a task is
> > context switched when within a transaction. It is corrected when
> > the transaction is aborted (which will happen after a context switch)
> > but if the task has suspended (TSUSPEND) the transaction the incorrect
> > value can be seen.
>=20
> I don't quite follow this description. How is it corrected when the trans=
action
> is aborted, and when does that usually happen? If that happens the task c=
an't
> ever see the corrupted value?
>=20
> To hit the suspended case, the task starts a transaction, suspends it, is=
then
> context switched out and back in, and at that point it can see the wrong =
value?
Yep, that's it and it's corrupted until the transaction is rolled back
(normally at the tresume). At the tresume it gets rolled back to the
checkpointed value at tbegin and is no longer corrupt.
> > The problem is caused by saving a thread's DSCR afterNo it's lost at th=
at point as we've not saved it and it was overwritten when we did the trecl=
aim. it has already
> > been reverted to the CPU's default value:
> >=20
> > __switch_to() calls __switch_to_tm()
> > which calls tm_reclaim_task()
> > which calls tm_reclaim_thread()
> > which calls tm_reclaim() where the DSCR is reset
>=20
> Where the DSCR is set to DSCR_DEFAULT ? Or now PACA_DSCR since your previ=
ous
> patches?
>=20
> Could we instead fix the bug there by reverting to the thread's DSCR valu=
e?
We really need to save it earlier, before the treclaim which will
override it.
> > __switch_to() calls _switch
> > _switch() saves the DSCR to thread.dscrTBEGIN
> >=20
> > The fix is to treat the DSCR similarly to the TAR and save it early
> > in __switch_to().
> >=20
> > The program below will expose the problem:
>=20
>=20
> Can you drop this in tools/testing/selftests/powerpc/tm ?
>=20
> You'll need to create that directory, you can ape the Makefile from the p=
mu
> directory, it should be fairly obvious. See the pmu tests for how to inte=
grate
> with the test harness etc., or bug me if it's not straight forward.
>=20
>=20
> > diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/includ=
e/asm/switch_to.h
> > index 2737f46..3efd0e5 100644
> > --- a/arch/powerpc/include/asm/switch_to.h
> > +++ b/arch/powerpc/include/asm/switch_to.h
> > @@ -16,13 +16,15 @@ struct thread_struct;
> > extern struct task_struct *_switch(struct thread_struct *prev,
> > struct thread_struct *next);
> > #ifdef CONFIG_PPC_BOOK3S_64
> > -static inline void save_tar(struct thread_struct *prev)
> > +static inline void save_early_sprs(struct thread_struct *prev)
> > {
> > if (cpu_has_feature(CPU_FTR_ARCH_207S))
> > prev->tar =3D mfspr(SPRN_TAR);
> > + if (cpu_has_feature(CPU_FTR_DSCR))
> > + prev->dscr =3D mfspr(SPRN_DSCR);
> > }
>=20
> Are we going to end up saving more SPRs in this code? What makes the TAR =
& DSCR
> special vs everything else?
There are only a limited set of SPRs that TM checkpoints. The full list
is CR, LR, CTR, FPSCR, AMR, PPR, VRSAVE, VSCR, DSCR, and TAR. =20
http://www.scribd.com/doc/142877680/PowerISA-v2-07#outer_page_826
CR, LR, CTR, PPR are handled really early in the exception handler
FPSCR, VSCR are done in the FP/VMX/VSX code.
AMR we don't care about.
That just leaves the DSCR and the TAR for here....
... and the VRSAVE. Sam: did you have a patch to save that one early
too? I think we talked about it but forgot, or did we decide that it's
always broken anyway so we don't care? :-D
Mikey
> The nice thing about doing this in asm is it's nop'ed out for cpus that d=
on't
> have the DSCR. What does the generated code for this look like?
>=20
> > diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry=
_64.S
> > index 662c6dd..a107f4a 100644
> > --- a/arch/powerpc/kernel/entry_64.S
> > +++ b/arch/powerpc/kernel/entry_64.S
> > @@ -432,12 +432,6 @@ BEGIN_FTR_SECTION
> > std r24,THREAD_VRSAVE(r3)
> > END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
> > #endif /* CONFIG_ALTIVEC */
> > -#ifdef CONFIG_PPC64
> > -BEGIN_FTR_SECTION
> > - mfspr r25,SPRN_DSCR
> > - std r25,THREAD_DSCR(r3)
> > -END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
> > -#endif
> > and. r0,r0,r22
> > beq+ 1f
> > andc r22,r22,r0
>=20
>=20
> cheers
>=20
>=20
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/powernv: Enable POWER8 doorbell IPIs
From: Michael Neuling @ 2014-06-04 9:38 UTC (permalink / raw)
To: Michael Ellerman
Cc: Preeti U Murthy, linuxppc-dev, Anton Blanchard, Paul Mackerras
In-Reply-To: <1401868995.9903.4.camel@concordia>
On Wed, 2014-06-04 at 18:03 +1000, Michael Ellerman wrote:
> On Mon, 2014-06-02 at 16:57 +1000, Michael Neuling wrote:
> > This patch enables POWER8 doorbell IPIs on powernv.
> >=20
> > Since doorbells can only IPI within a core, we test to see when we can =
use
> > doorbells and if not we fall back to XICS. This also enables hyperviso=
r
> > doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit.
> >=20
> > Based on tests by Anton, the best case IPI latency between two threads =
dropped
> > from 894ns to 512ns.
> >=20
> > Signed-off-by: Michael Neuling <mikey@neuling.org>
> > ---
> > arch/powerpc/kernel/cpu_setup_power.S | 2 ++
> > arch/powerpc/platforms/powernv/smp.c | 6 ++++++
> > arch/powerpc/sysdev/xics/icp-native.c | 9 ++++++++-
> > 3 files changed, 16 insertions(+), 1 deletion(-)
> >=20
> > diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kerne=
l/cpu_setup_power.S
> > index 1557e7c..4673353 100644
> > --- a/arch/powerpc/kernel/cpu_setup_power.S
> > +++ b/arch/powerpc/kernel/cpu_setup_power.S
> > @@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
> > li r0,0
> > mtspr SPRN_LPID,r0
> > mfspr r3,SPRN_LPCR
> > + ori r3, r3, LPCR_PECEDH
> > bl __init_LPCR
> > bl __init_HFSCR
> > bl __init_tlb_power8
> > @@ -74,6 +75,7 @@ _GLOBAL(__restore_cpu_power8)
> > li r0,0
> > mtspr SPRN_LPID,r0
> > mfspr r3,SPRN_LPCR
> > + ori r3, r3, LPCR_PECEDH
> > bl __init_LPCR
> > bl __init_HFSCR
> > bl __init_tlb_power8
> > diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platfo=
rms/powernv/smp.c
> > index 0062a43..5fcfcf4 100644
> > --- a/arch/powerpc/platforms/powernv/smp.c
> > +++ b/arch/powerpc/platforms/powernv/smp.c
> > @@ -32,6 +32,7 @@
> > #include <asm/opal.h>
> > #include <asm/runlatch.h>
> > #include <asm/code-patching.h>
> > +#include <asm/dbell.h>
> > =20
> > #include "powernv.h"
> > =20
> > @@ -46,6 +47,11 @@ static void pnv_smp_setup_cpu(int cpu)
> > {
> > if (cpu !=3D boot_cpuid)
> > xics_setup_cpu();
> > +
> > +#ifdef CONFIG_PPC_DOORBELL
> > + if (cpu_has_feature(CPU_FTR_DBELL))
> > + doorbell_setup_this_cpu();
> > +#endif
> > }
>=20
> Where does CONFIG_PPC_DOORBELL get set?
No where.
> It looks like the only place you can be getting it is from CONFIG_PPC_PSE=
RIES.
> If you build a POWERNV only kernel it will get disabled, which I don't th=
ink is
> what we want.
>=20
> I think we should select it for POWERNV as well as PSERIES. That would me=
an
> it's always enabled for any build of the files you touch, so you shouldn'=
t need
> the #ifdefs.
Ok, I'll add and resend.
Mikey
^ permalink raw reply
* Re: [PATCH] powerpc, xmon: Enable hardware instruction breakpoint support on POWER8
From: Anshuman Khandual @ 2014-06-04 8:48 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: Michael Ellerman, linuxppc-dev, mikey
In-Reply-To: <538D654E.8040205@linux.vnet.ibm.com>
On 06/03/2014 11:33 AM, Anshuman Khandual wrote:
> On 05/30/2014 07:12 PM, Aneesh Kumar K.V wrote:
>> > Anshuman Khandual <khandual@linux.vnet.ibm.com> writes:
>> >
>>> >> This patch enables support for hardware instruction breakpoints on POWER8 with
>>> >> the help of a new register called CIABR (Completed Instruction Address Breakpoint
>>> >> Register). With this patch, single hardware instruction breakpoint can be added
>>> >> and cleared during any active xmon debug session. This hardware based instruction
>>> >> breakpoint mechanism works correctly along with the existing TRAP based instruction
>>> >> breakpoints available on xmon. Example usage as follows.
>>> >>
>>> >> (A) Start xmon:
>>> >> $echo x > /proc/sysrq-trigger
>>> >> SysRq : Entering xmon
>>> >> cpu 0x0: Vector: 0 at [c000001f6c67f960]
>>> >> pc: c000000000072078: .sysrq_handle_xmon+0x58/0x60
>>> >> lr: c000000000072078: .sysrq_handle_xmon+0x58/0x60
>>> >> sp: c000001f6c67fac0
>>> >> msr: 9000000000009032
>>> >> current = 0xc000001f6e709ac0
>>> >> paca = 0xc00000000fffa000 softe: 0 irq_happened: 0x00
>>> >> pid = 3250, comm = bash
>>> >> enter ? for help
>>> >> 0:mon> b
>>> >> type address
>>> >>
>>> >> (B) Set the breakpoint:
>>> >> 0:mon> ls .power_pmu_add
>>> >> .power_pmu_add: c000000000078f50
>>> >> 0:mon> bi c000000000078f50
>>> >> 0:mon> b
>>> >> type address
>>> >> 1 inst c000000000078f50 .power_pmu_add+0x0/0x2e0
>>> >> 0:mon> ls .perf_event_interrupt
>>> >> .perf_event_interrupt: c00000000007aee0
>>> >> 0:mon> bi c00000000007aee0
>>> >> One instruction breakpoint possible with CIABR
>>> >> 0:mon> x
>>> >>
>>> >> (C) Run the workload (with the breakpoint):
>>> >> $./perf record ls
>>> >> cpu 0x2: Vector: d00 (Single Step) at [c000001f718133a0]
>>> >> pc: c000000000078f54: .power_pmu_add+0x4/0x2e0
>>> >> lr: c000000000155be0: .event_sched_in+0x90/0x1d0
>>> >> sp: c000001f71813620
>>> >> msr: 9000000040109032
>>> >> current = 0xc000001f6ce30000
>>> >> paca = 0xc00000000fffa600 softe: 0 irq_happened: 0x01
>>> >> pid = 3270, comm = ls
>>> >> std r22,-80(r1)
>>> >> enter ? for help
>>> >>
>>> >> (D) Clear the breakpoint:
>>> >> 2:mon> bc
>>> >> All breakpoints cleared
>>> >> 2:mon> x
>>> >> [ perf record: Woken up 1 times to write data ]
>>> >> [ perf record: Captured and wrote 0.002 MB perf.data (~66 samples) ]
>>> >>
>>> >> (E) Run the workload again (without any breakpoints):
>>> >> $./perf record ls
>>> >> [ perf record: Woken up 1 times to write data ]
>>> >> [ perf record: Captured and wrote 0.001 MB perf.data (~61 samples) ]
>>> >>
>>> >> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
>>> >> ---
>>> >> arch/powerpc/xmon/xmon.c | 62 ++++++++++++++++++++++++++++++++++++++++++++----
>>> >> 1 file changed, 58 insertions(+), 4 deletions(-)
>>> >>
>>> >> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>>> >> index 3fd1d9a..f74ec83 100644
>>> >> --- a/arch/powerpc/xmon/xmon.c
>>> >> +++ b/arch/powerpc/xmon/xmon.c
>>> >> @@ -48,6 +48,7 @@
>>> >> #ifdef CONFIG_PPC64
>>> >> #include <asm/hvcall.h>
>>> >> #include <asm/paca.h>
>>> >> +#include <asm/plpar_wrappers.h>
>>> >> #endif
>>> >>
>>> >> #include "nonstdio.h"
>>> >> @@ -89,6 +90,7 @@ struct bpt {
>>> >> /* Bits in bpt.enabled */
>>> >> #define BP_IABR_TE 1 /* IABR translation enabled */
>>> >> #define BP_IABR 2
>>> >> +#define BP_CIABR 4
>>> >> #define BP_TRAP 8
>>> >> #define BP_DABR 0x10
>>> >>
>>> >> @@ -97,6 +99,7 @@ static struct bpt bpts[NBPTS];
>>> >> static struct bpt dabr;
>>> >> static struct bpt *iabr;
>>> >> static unsigned bpinstr = 0x7fe00008; /* trap */
>>> >> +static bool ciabr_used = false; /* CIABR instruction breakpoint */
>>> >>
>>> >> #define BP_NUM(bp) ((bp) - bpts + 1)
>>> >>
>>> >> @@ -269,6 +272,34 @@ static inline void cinval(void *p)
>>> >> asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
>>> >> }
>>> >>
>>> >> +static void write_ciabr(unsigned long ciabr)
>>> >> +{
>>> >> + if (cpu_has_feature(CPU_FTR_HVMODE)) {
>>> >> + mtspr(SPRN_CIABR, ciabr);
>>> >> + return;
>>> >> + }
>>> >> +
>>> >> +#ifdef CONFIG_PPC64
>>> >> + plapr_set_ciabr(ciabr);
>>> >> +#endif
>>> >> +}
>>> >> +
>>> >> +static void set_ciabr(unsigned long addr)
>>> >> +{
>>> >> + addr &= ~CIABR_PRIV;
>>> >> + if (cpu_has_feature(CPU_FTR_HVMODE))
>>> >> + addr |= CIABR_PRIV_HYPER;
>>> >> + else
>>> >> + addr |= CIABR_PRIV_SUPER;
>>> >> + write_ciabr(addr);
>>> >> +}
>>> >> +
>>> >> +static void clear_ciabr(void)
>>> >> +{
>>> >> + if (cpu_has_feature(CPU_FTR_ARCH_207S))
>>> >> + write_ciabr(0);
>>> >> +}
>>> >> +
>>> >> /*
>>> >> * Disable surveillance (the service processor watchdog function)
>>> >> * while we are in xmon.
>>> >> @@ -764,6 +795,9 @@ static void insert_cpu_bpts(void)
>>> >> if (iabr && cpu_has_feature(CPU_FTR_IABR))
>>> >> mtspr(SPRN_IABR, iabr->address
>>> >> | (iabr->enabled & (BP_IABR|BP_IABR_TE)));
>>> >> +
>>> >> + if (iabr && cpu_has_feature(CPU_FTR_ARCH_207S))
>>> >> + set_ciabr(iabr->address);
>>> >> }
>>> >>
>>> >> static void remove_bpts(void)
>>> >> @@ -791,6 +825,7 @@ static void remove_cpu_bpts(void)
>>> >> hw_breakpoint_disable();
>>> >> if (cpu_has_feature(CPU_FTR_IABR))
>>> >> mtspr(SPRN_IABR, 0);
>>> >> + clear_ciabr();
>>> >> }
>>> >>
>>> >> /* Command interpreting routine */
>>> >> @@ -1124,7 +1159,7 @@ static char *breakpoint_help_string =
>>> >> "b <addr> [cnt] set breakpoint at given instr addr\n"
>>> >> "bc clear all breakpoints\n"
>>> >> "bc <n/addr> clear breakpoint number n or at addr\n"
>>> >> - "bi <addr> [cnt] set hardware instr breakpoint (POWER3/RS64 only)\n"
>>> >> + "bi <addr> [cnt] set hardware instr breakpoint (POWER3/RS64/POWER8 only)\n"
>>> >> "bd <addr> [cnt] set hardware data breakpoint\n"
>>> >> "";
>>> >>
>>> >> @@ -1163,11 +1198,20 @@ bpt_cmds(void)
>>> >> break;
>>> >>
>>> >> case 'i': /* bi - hardware instr breakpoint */
>>> >> - if (!cpu_has_feature(CPU_FTR_IABR)) {
>>> >> + if (!cpu_has_feature(CPU_FTR_IABR) && !cpu_has_feature(CPU_FTR_ARCH_207S)) {
>>> >> printf("Hardware instruction breakpoint "
>>> >> "not supported on this cpu\n");
>>> >> break;
>>> >> }
>>> >> +
>>> >> + if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
>>> >> + if (ciabr_used) {
>>> >> + printf("One instruction breakpoint "
>>> >> + "possible with CIABR\n");
>>> >> + break;
>>> >> + }
>> >
>> > We don't seem to do that with iabr ? Why keep ciabr different
> Right now with the IABR implementation if we try to set hardware instruction
> breakpoint while one is already there, it just get overridden with the new
> address without complaining. I thought with this at least for CIABR cases,
> it will complain about it and require the user to clear the breakpoint
> explicitly before allowing a new breakpoint. Okay will remove this.
>
I tried removing the "ciabr_used" variable and all related checks/assignments on it.
Then I was able to add all these three address as hardware instruction breakpoint
and xmon never complained that it might override the existing actual checkpoint
implemented with CIABR. It accepted all the three addresses which can later be
listed as below.
0:mon> b
type address
1 inst c0000000000830d0 .power_pmu_add+0x0/0x2e0
2 inst c000000000084690 .power_pmu_del+0x0/0x3a0
3 inst c000000000085060 .perf_event_interrupt+0x0/0x480
But in reality, only perf_event_interrupt function's address got written into CIABR
register and got triggered with the workload. I dont have a system which has IABR
support to test it's behaviour for this situation. But this does not sound okay,
we should explicitly inform the user that the hardware instruction breakpoint has
been overridden with the latest command or reject the attempt. Looking for some
suggestions in this regard. Thank you.
^ permalink raw reply
* RE: [RESEND PATCH] memory: Freescale CoreNet Coherency Fabric error reporting driver
From: Bharat.Bhushan @ 2014-06-04 8:17 UTC (permalink / raw)
To: Scott Wood, Greg Kroah-Hartman
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org
In-Reply-To: <20140530222743.GA6918@home.buserror.net>
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^ permalink raw reply
* Re: [PATCH 2/2] powerpc/powernv: Enable POWER8 doorbell IPIs
From: Michael Ellerman @ 2014-06-04 8:03 UTC (permalink / raw)
To: Michael Neuling
Cc: Preeti U Murthy, linuxppc-dev, Anton Blanchard, Paul Mackerras
In-Reply-To: <1401692223-28337-2-git-send-email-mikey@neuling.org>
On Mon, 2014-06-02 at 16:57 +1000, Michael Neuling wrote:
> This patch enables POWER8 doorbell IPIs on powernv.
>
> Since doorbells can only IPI within a core, we test to see when we can use
> doorbells and if not we fall back to XICS. This also enables hypervisor
> doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit.
>
> Based on tests by Anton, the best case IPI latency between two threads dropped
> from 894ns to 512ns.
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
> ---
> arch/powerpc/kernel/cpu_setup_power.S | 2 ++
> arch/powerpc/platforms/powernv/smp.c | 6 ++++++
> arch/powerpc/sysdev/xics/icp-native.c | 9 ++++++++-
> 3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index 1557e7c..4673353 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -56,6 +56,7 @@ _GLOBAL(__setup_cpu_power8)
> li r0,0
> mtspr SPRN_LPID,r0
> mfspr r3,SPRN_LPCR
> + ori r3, r3, LPCR_PECEDH
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power8
> @@ -74,6 +75,7 @@ _GLOBAL(__restore_cpu_power8)
> li r0,0
> mtspr SPRN_LPID,r0
> mfspr r3,SPRN_LPCR
> + ori r3, r3, LPCR_PECEDH
> bl __init_LPCR
> bl __init_HFSCR
> bl __init_tlb_power8
> diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
> index 0062a43..5fcfcf4 100644
> --- a/arch/powerpc/platforms/powernv/smp.c
> +++ b/arch/powerpc/platforms/powernv/smp.c
> @@ -32,6 +32,7 @@
> #include <asm/opal.h>
> #include <asm/runlatch.h>
> #include <asm/code-patching.h>
> +#include <asm/dbell.h>
>
> #include "powernv.h"
>
> @@ -46,6 +47,11 @@ static void pnv_smp_setup_cpu(int cpu)
> {
> if (cpu != boot_cpuid)
> xics_setup_cpu();
> +
> +#ifdef CONFIG_PPC_DOORBELL
> + if (cpu_has_feature(CPU_FTR_DBELL))
> + doorbell_setup_this_cpu();
> +#endif
> }
Where does CONFIG_PPC_DOORBELL get set?
It looks like the only place you can be getting it is from CONFIG_PPC_PSERIES.
If you build a POWERNV only kernel it will get disabled, which I don't think is
what we want.
I think we should select it for POWERNV as well as PSERIES. That would mean
it's always enabled for any build of the files you touch, so you shouldn't need
the #ifdefs.
cheers
^ permalink raw reply
* [PATCH v2 2/2] powerpc/powernv: Set memory_block_size_bytes to 256MB
From: Anton Blanchard @ 2014-06-04 7:52 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
In-Reply-To: <20140604175047.35b116b3@kryten>
powerpc sets a low SECTION_SIZE_BITS to accomodate small pseries
boxes. We default to 16MB memory blocks, and boxes with a lot
of memory end up with enormous numbers of sysfs memory nodes.
Set a more reasonable default for powernv of 256MB.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/platforms/powernv/setup.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 865aab4..8c16a5f 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -244,6 +244,13 @@ static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
}
#endif /* CONFIG_KEXEC */
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+static unsigned long pnv_memory_block_size(void)
+{
+ return 256UL * 1024 * 1024;
+}
+#endif
+
static void __init pnv_setup_machdep_opal(void)
{
ppc_md.get_boot_time = opal_get_boot_time;
@@ -326,4 +333,7 @@ define_machine(powernv) {
#ifdef CONFIG_KEXEC
.kexec_cpu_down = pnv_kexec_cpu_down,
#endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+ .memory_block_size = pnv_memory_block_size,
+#endif
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 1/2] powerpc: Allow ppc_md platform hook to override memory_block_size_bytes
From: Anton Blanchard @ 2014-06-04 7:50 UTC (permalink / raw)
To: benh, paulus; +Cc: linuxppc-dev
The pseries platform code unconditionally overrides
memory_block_size_bytes regardless of the running platform.
Create a ppc_md hook that so each platform can choose to
do what it wants.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
arch/powerpc/include/asm/machdep.h | 3 +++
arch/powerpc/kernel/setup_64.c | 10 ++++++++++
arch/powerpc/platforms/pseries/hotplug-memory.c | 17 +++--------------
arch/powerpc/platforms/pseries/pseries.h | 2 ++
arch/powerpc/platforms/pseries/setup.c | 3 +++
5 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 374abc2..f92b0b5 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -98,6 +98,9 @@ struct machdep_calls {
void (*iommu_save)(void);
void (*iommu_restore)(void);
#endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+ unsigned long (*memory_block_size)(void);
+#endif
#endif /* CONFIG_PPC64 */
void (*pci_dma_dev_setup)(struct pci_dev *dev);
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 90b532a..ee082d7 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -36,6 +36,7 @@
#include <linux/lockdep.h>
#include <linux/memblock.h>
#include <linux/hugetlb.h>
+#include <linux/memory.h>
#include <asm/io.h>
#include <asm/kdump.h>
@@ -780,6 +781,15 @@ void __init setup_per_cpu_areas(void)
}
#endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+unsigned long memory_block_size_bytes(void)
+{
+ if (ppc_md.memory_block_size)
+ return ppc_md.memory_block_size();
+
+ return MIN_MEMORY_BLOCK_SIZE;
+}
+#endif
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
struct ppc_pci_io ppc_pci_io;
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index 7f75c94..7995135 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -21,7 +21,7 @@
#include <asm/prom.h>
#include <asm/sparsemem.h>
-static unsigned long get_memblock_size(void)
+unsigned long pseries_memory_block_size(void)
{
struct device_node *np;
unsigned int memblock_size = MIN_MEMORY_BLOCK_SIZE;
@@ -64,17 +64,6 @@ static unsigned long get_memblock_size(void)
return memblock_size;
}
-/* WARNING: This is going to override the generic definition whenever
- * pseries is built-in regardless of what platform is active at boot
- * time. This is fine for now as this is the only "option" and it
- * should work everywhere. If not, we'll have to turn this into a
- * ppc_md. callback
- */
-unsigned long memory_block_size_bytes(void)
-{
- return get_memblock_size();
-}
-
#ifdef CONFIG_MEMORY_HOTREMOVE
static int pseries_remove_memory(u64 start, u64 size)
{
@@ -105,7 +94,7 @@ static int pseries_remove_memblock(unsigned long base, unsigned int memblock_siz
if (!pfn_valid(start_pfn))
goto out;
- block_sz = memory_block_size_bytes();
+ block_sz = pseries_memory_block_size();
sections_per_block = block_sz / MIN_MEMORY_BLOCK_SIZE;
nid = memory_add_physaddr_to_nid(base);
@@ -201,7 +190,7 @@ static int pseries_update_drconf_memory(struct of_prop_reconfig *pr)
u32 *p;
int i, rc = -EINVAL;
- memblock_size = get_memblock_size();
+ memblock_size = pseries_memory_block_size();
if (!memblock_size)
return -EINVAL;
diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
index 9921953..361add6 100644
--- a/arch/powerpc/platforms/pseries/pseries.h
+++ b/arch/powerpc/platforms/pseries/pseries.h
@@ -64,4 +64,6 @@ extern int dlpar_detach_node(struct device_node *);
struct pci_host_bridge;
int pseries_root_bridge_prepare(struct pci_host_bridge *bridge);
+unsigned long pseries_memory_block_size(void);
+
#endif /* _PSERIES_PSERIES_H */
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 215c3c2..adc21a0 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -810,4 +810,7 @@ define_machine(pseries) {
#ifdef CONFIG_KEXEC
.machine_kexec = pSeries_machine_kexec,
#endif
+#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
+ .memory_block_size = pseries_memory_block_size,
+#endif
};
--
1.9.1
^ permalink raw reply related
* [PATCH] powerpc/powernv: Fix killed EEH event
From: Gavin Shan @ 2014-06-04 7:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
On PowerNV platform, EEH errors are reported by IO accessors or poller
driven by interrupt. After the PE is isolated, we won't produce EEH
event for the PE. The current implementation has possibility of EEH
event lost in this way:
The interrupt handler queues one "special" event, which drives the poller.
EEH thread doesn't pick the special event yet. IO accessors kicks in, the
frozen PE is marked as "isolated" and EEH event is queued to the list.
EEH thread runs because of special event and purge all existing EEH events.
However, we never produce an other EEH event for the frozen PE. Eventually,
the PE is marked as "isolated" and we don't have EEH event to recover it.
The patch fixes the issue to keep EEH events for PEs that have been
marked as "isolated" with the help of additional "force" help to
eeh_remove_event().
Reported-by: Rolf Brudeseth <rolfb@us.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/eeh_event.h | 2 +-
arch/powerpc/kernel/eeh_driver.c | 4 ++--
arch/powerpc/kernel/eeh_event.c | 21 +++++++++++++++------
arch/powerpc/platforms/powernv/eeh-ioda.c | 2 +-
4 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
index 89d5670..1e551a2 100644
--- a/arch/powerpc/include/asm/eeh_event.h
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -33,7 +33,7 @@ struct eeh_event {
int eeh_event_init(void);
int eeh_send_failure_event(struct eeh_pe *pe);
-void eeh_remove_event(struct eeh_pe *pe);
+void eeh_remove_event(struct eeh_pe *pe, bool force);
void eeh_handle_event(struct eeh_pe *pe);
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index 8bb40e7..420da61 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -770,7 +770,7 @@ static void eeh_handle_special_event(void)
eeh_serialize_lock(&flags);
/* Purge all events */
- eeh_remove_event(NULL);
+ eeh_remove_event(NULL, true);
list_for_each_entry(hose, &hose_list, list_node) {
phb_pe = eeh_phb_pe_get(hose);
@@ -789,7 +789,7 @@ static void eeh_handle_special_event(void)
eeh_serialize_lock(&flags);
/* Purge all events of the PHB */
- eeh_remove_event(pe);
+ eeh_remove_event(pe, true);
if (rc == EEH_NEXT_ERR_DEAD_PHB)
eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
diff --git a/arch/powerpc/kernel/eeh_event.c b/arch/powerpc/kernel/eeh_event.c
index 72d748b..4eefb6e 100644
--- a/arch/powerpc/kernel/eeh_event.c
+++ b/arch/powerpc/kernel/eeh_event.c
@@ -152,24 +152,33 @@ int eeh_send_failure_event(struct eeh_pe *pe)
/**
* eeh_remove_event - Remove EEH event from the queue
* @pe: Event binding to the PE
+ * @force: Event will be removed unconditionally
*
* On PowerNV platform, we might have subsequent coming events
* is part of the former one. For that case, those subsequent
* coming events are totally duplicated and unnecessary, thus
* they should be removed.
*/
-void eeh_remove_event(struct eeh_pe *pe)
+void eeh_remove_event(struct eeh_pe *pe, bool force)
{
unsigned long flags;
struct eeh_event *event, *tmp;
+ /*
+ * If we have NULL PE passed in, we have dead IOC
+ * or we're sure we can report all existing errors
+ * by the caller.
+ *
+ * With "force", the event with associated PE that
+ * have been isolated, the event won't be removed
+ * to avoid event lost.
+ */
spin_lock_irqsave(&eeh_eventlist_lock, flags);
list_for_each_entry_safe(event, tmp, &eeh_eventlist, list) {
- /*
- * If we don't have valid PE passed in, that means
- * we already have event corresponding to dead IOC
- * and all events should be purged.
- */
+ if (!force && event->pe &&
+ (event->pe->state & EEH_PE_ISOLATED))
+ continue;
+
if (!pe) {
list_del(&event->list);
kfree(event);
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
index cab3e62..f1f089d 100644
--- a/arch/powerpc/platforms/powernv/eeh-ioda.c
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -797,7 +797,7 @@ static int ioda_eeh_next_error(struct eeh_pe **pe)
* And we should keep the cached OPAL notifier event sychronized
* between the kernel and firmware.
*/
- eeh_remove_event(NULL);
+ eeh_remove_event(NULL, false);
opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
list_for_each_entry(hose, &hose_list, list_node) {
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH 1/1] powerpc: correct DSCR during TM context switch
From: Michael Ellerman @ 2014-06-04 7:31 UTC (permalink / raw)
To: Sam Bobroff; +Cc: aik, mikey, benh, linuxppc-dev, khandual
In-Reply-To: <f1ddc3bc4b970a480367a45cdca51e879cb14df0.1401852531.git.sam.bobroff@au1.ibm.com>
Hi Sam,
Comments inline ..
On Wed, 2014-06-04 at 13:33 +1000, Sam Bobroff wrote:
> Correct the DSCR SPR becoming temporarily corrupted when a task is
> context switched when within a transaction. It is corrected when
> the transaction is aborted (which will happen after a context switch)
> but if the task has suspended (TSUSPEND) the transaction the incorrect
> value can be seen.
I don't quite follow this description. How is it corrected when the transaction
is aborted, and when does that usually happen? If that happens the task can't
ever see the corrupted value?
To hit the suspended case, the task starts a transaction, suspends it, is then
context switched out and back in, and at that point it can see the wrong value?
> The problem is caused by saving a thread's DSCR after it has already
> been reverted to the CPU's default value:
>
> __switch_to() calls __switch_to_tm()
> which calls tm_reclaim_task()
> which calls tm_reclaim_thread()
> which calls tm_reclaim() where the DSCR is reset
Where the DSCR is set to DSCR_DEFAULT ? Or now PACA_DSCR since your previous
patches?
Could we instead fix the bug there by reverting to the thread's DSCR value?
> __switch_to() calls _switch
> _switch() saves the DSCR to thread.dscr
>
> The fix is to treat the DSCR similarly to the TAR and save it early
> in __switch_to().
>
> The program below will expose the problem:
Can you drop this in tools/testing/selftests/powerpc/tm ?
You'll need to create that directory, you can ape the Makefile from the pmu
directory, it should be fairly obvious. See the pmu tests for how to integrate
with the test harness etc., or bug me if it's not straight forward.
> diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
> index 2737f46..3efd0e5 100644
> --- a/arch/powerpc/include/asm/switch_to.h
> +++ b/arch/powerpc/include/asm/switch_to.h
> @@ -16,13 +16,15 @@ struct thread_struct;
> extern struct task_struct *_switch(struct thread_struct *prev,
> struct thread_struct *next);
> #ifdef CONFIG_PPC_BOOK3S_64
> -static inline void save_tar(struct thread_struct *prev)
> +static inline void save_early_sprs(struct thread_struct *prev)
> {
> if (cpu_has_feature(CPU_FTR_ARCH_207S))
> prev->tar = mfspr(SPRN_TAR);
> + if (cpu_has_feature(CPU_FTR_DSCR))
> + prev->dscr = mfspr(SPRN_DSCR);
> }
Are we going to end up saving more SPRs in this code? What makes the TAR & DSCR
special vs everything else?
The nice thing about doing this in asm is it's nop'ed out for cpus that don't
have the DSCR. What does the generated code for this look like?
> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> index 662c6dd..a107f4a 100644
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -432,12 +432,6 @@ BEGIN_FTR_SECTION
> std r24,THREAD_VRSAVE(r3)
> END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
> #endif /* CONFIG_ALTIVEC */
> -#ifdef CONFIG_PPC64
> -BEGIN_FTR_SECTION
> - mfspr r25,SPRN_DSCR
> - std r25,THREAD_DSCR(r3)
> -END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
> -#endif
> and. r0,r0,r22
> beq+ 1f
> andc r22,r22,r0
cheers
^ permalink raw reply
* [PATCH] powerpc/powernv: Fix endian issues in memory error handling code
From: Anton Blanchard @ 2014-06-04 4:48 UTC (permalink / raw)
To: benh, paulus, mahesh; +Cc: linuxppc-dev
struct OpalMemoryErrorData is passed to us from firmware, so we
have to byteswap it.
Signed-off-by: Anton Blanchard <anton@samba.org>
---
Having enums in a firmware interface concerns me, but that cleanup
can be in a subsequent patch.
Mahesh, could you give this a test to see if it works?
Index: b/arch/powerpc/include/asm/opal.h
===================================================================
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -482,7 +482,7 @@ enum OpalMemErr_DynErrType {
struct OpalMemoryErrorData {
enum OpalMemErr_Version version:8; /* 0x00 */
enum OpalMemErrType type:8; /* 0x01 */
- uint16_t flags; /* 0x02 */
+ __be16 flags; /* 0x02 */
uint8_t reserved_1[4]; /* 0x04 */
union {
@@ -490,15 +490,15 @@ struct OpalMemoryErrorData {
struct {
enum OpalMemErr_ResilErrType resil_err_type:8;
uint8_t reserved_1[7];
- uint64_t physical_address_start;
- uint64_t physical_address_end;
+ __be64 physical_address_start;
+ __be64 physical_address_end;
} resilience;
/* Dynamic memory deallocation error info */
struct {
enum OpalMemErr_DynErrType dyn_err_type:8;
uint8_t reserved_1[7];
- uint64_t physical_address_start;
- uint64_t physical_address_end;
+ __be64 physical_address_start;
+ __be64 physical_address_end;
} dyn_dealloc;
} u;
};
Index: b/arch/powerpc/platforms/powernv/opal-memory-errors.c
===================================================================
--- a/arch/powerpc/platforms/powernv/opal-memory-errors.c
+++ b/arch/powerpc/platforms/powernv/opal-memory-errors.c
@@ -47,12 +47,12 @@ static void handle_memory_error_event(st
__func__, merr_evt->type);
switch (merr_evt->type) {
case OPAL_MEM_ERR_TYPE_RESILIENCE:
- paddr_start = merr_evt->u.resilience.physical_address_start;
- paddr_end = merr_evt->u.resilience.physical_address_end;
+ paddr_start = be64_to_cpu(merr_evt->u.resilience.physical_address_start);
+ paddr_end = be64_to_cpu(merr_evt->u.resilience.physical_address_end);
break;
case OPAL_MEM_ERR_TYPE_DYN_DALLOC:
- paddr_start = merr_evt->u.dyn_dealloc.physical_address_start;
- paddr_end = merr_evt->u.dyn_dealloc.physical_address_end;
+ paddr_start = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_start);
+ paddr_end = be64_to_cpu(merr_evt->u.dyn_dealloc.physical_address_end);
break;
default:
return;
^ permalink raw reply
* Re: [PATCH] KVM: PPC: BOOK3S: PR: Fix PURR and SPURR emulation
From: Paul Mackerras @ 2014-06-04 4:15 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, agraf, kvm-ppc, kvm
In-Reply-To: <1401797771-25606-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Tue, Jun 03, 2014 at 05:46:11PM +0530, Aneesh Kumar K.V wrote:
> We use time base for PURR and SPURR emulation with PR KVM since we
> are emulating a single threaded core. When using time base
> we need to make sure that we don't accumulate time spent in the host
> in PURR and SPURR value.
Mostly looks good except for this...
> @@ -170,6 +175,11 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
>
> out:
> preempt_enable();
> + /*
> + * Update purr and spurr using time base
> + */
> + vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
> + vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
You need to do those updates before the "out:" label. Otherwise if
this function gets called with !svcpu->in_use (which can happen if
CONFIG_PREEMPT is enabled) we would do these updates a second time for
one guest exit. The thing is that kvmppc_copy_from_svcpu() can get
called from kvmppc_core_vcpu_put_pr() if the vcpu task gets preempted
on the way out from the guest before we get to the regular call of
kvmppc_copy_from_svcpu(). It would then get called again when the
task gets to run, but this time it does nothing because svcpu->in_use
is false.
Paul.
^ permalink raw reply
* [PATCH 1/1] powerpc: correct DSCR during TM context switch
From: Sam Bobroff @ 2014-06-04 3:33 UTC (permalink / raw)
To: benh; +Cc: aik, mikey, linuxppc-dev, khandual
Correct the DSCR SPR becoming temporarily corrupted when a task is
context switched when within a transaction. It is corrected when
the transaction is aborted (which will happen after a context switch)
but if the task has suspended (TSUSPEND) the transaction the incorrect
value can be seen.
The problem is caused by saving a thread's DSCR after it has already
been reverted to the CPU's default value:
__switch_to() calls __switch_to_tm()
which calls tm_reclaim_task()
which calls tm_reclaim_thread()
which calls tm_reclaim() where the DSCR is reset
__switch_to() calls _switch
_switch() saves the DSCR to thread.dscr
The fix is to treat the DSCR similarly to the TAR and save it early
in __switch_to().
The program below will expose the problem:
#include <inttypes.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <asm/tm.h>
#define TBEGIN ".long 0x7C00051D ;"
#define TEND ".long 0x7C00055D ;"
#define TCHECK ".long 0x7C00059C ;"
#define TSUSPEND ".long 0x7C0005DD ;"
#define TRESUME ".long 0x7C2005DD ;"
#define SPRN_TEXASR 0x82
#define SPRN_DSCR 0x03
int main(void) {
uint64_t i = 0, rv, dscr1 = 1, dscr2, texasr;
for (;;) {
rv = 1;
asm __volatile__ (
"ld 3, %[dscr1];"
"mtspr %[sprn_dscr], 3;"
TBEGIN
"beq 1f;"
TSUSPEND
"2: ;"
TCHECK
"bc 4, 0, 2b;"
"mfspr 3, %[sprn_dscr];"
"std 3, %[dscr2];"
"mfspr 3, %[sprn_texasr];"
"std 3, %[texasr];"
TRESUME
TEND
"li %[rv], 0;"
"1: ;"
: [rv]"=r"(rv), [dscr2]"=m"(dscr2), [texasr]"=m"(texasr)
: [dscr1]"m"(dscr1)
, [sprn_dscr]"i"(SPRN_DSCR), [sprn_texasr]"i"(SPRN_TEXASR)
: "memory", "r3"
);
assert(rv);
if ((texasr >> 56) == TM_CAUSE_RESCHED) {
putchar('!');
fflush(stdout);
i++;
}
else {
putchar('.');
fflush(stdout);
}
if (dscr2 != dscr1) {
printf("\n==== DSCR incorrect: 0x%lx (expecting 0x%lx)\n", dscr2, dscr1);
exit(EXIT_FAILURE);
}
if (i > 10) {
printf("\n==== DSCR TM context switching seems OK.\n");
exit(EXIT_SUCCESS);
}
}
}
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
---
arch/powerpc/include/asm/switch_to.h | 6 ++++--
arch/powerpc/kernel/entry_64.S | 6 ------
arch/powerpc/kernel/process.c | 8 ++++----
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 2737f46..3efd0e5 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -16,13 +16,15 @@ struct thread_struct;
extern struct task_struct *_switch(struct thread_struct *prev,
struct thread_struct *next);
#ifdef CONFIG_PPC_BOOK3S_64
-static inline void save_tar(struct thread_struct *prev)
+static inline void save_early_sprs(struct thread_struct *prev)
{
if (cpu_has_feature(CPU_FTR_ARCH_207S))
prev->tar = mfspr(SPRN_TAR);
+ if (cpu_has_feature(CPU_FTR_DSCR))
+ prev->dscr = mfspr(SPRN_DSCR);
}
#else
-static inline void save_tar(struct thread_struct *prev) {}
+static inline void save_early_sprs(struct thread_struct *prev) {}
#endif
extern void enable_kernel_fp(void);
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 662c6dd..a107f4a 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -432,12 +432,6 @@ BEGIN_FTR_SECTION
std r24,THREAD_VRSAVE(r3)
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
#endif /* CONFIG_ALTIVEC */
-#ifdef CONFIG_PPC64
-BEGIN_FTR_SECTION
- mfspr r25,SPRN_DSCR
- std r25,THREAD_DSCR(r3)
-END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
-#endif
and. r0,r0,r22
beq+ 1f
andc r22,r22,r0
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index e247898..8d2065e 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -771,15 +771,15 @@ struct task_struct *__switch_to(struct task_struct *prev,
WARN_ON(!irqs_disabled());
- /* Back up the TAR across context switches.
+ /* Back up the TAR and DSCR across context switches.
* Note that the TAR is not available for use in the kernel. (To
* provide this, the TAR should be backed up/restored on exception
* entry/exit instead, and be in pt_regs. FIXME, this should be in
* pt_regs anyway (for debug).)
- * Save the TAR here before we do treclaim/trecheckpoint as these
- * will change the TAR.
+ * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
+ * these will change them.
*/
- save_tar(&prev->thread);
+ save_early_sprs(&prev->thread);
__switch_to_tm(prev);
--
1.7.10.4
^ permalink raw reply related
* [PATCH] powerpc/eeh: skip eeh sysfs when eeh is disabled
From: Wei Yang @ 2014-06-04 1:49 UTC (permalink / raw)
To: benh, linuxppc-dev, gwshan; +Cc: Wei Yang
When eeh is not enabled, and hotplug two pci devices on the same bus, eeh
related sysfs would be added twice for the first added pci device. Since the
eeh_dev is not created when eeh is not enabled.
This patch adds the check, if eeh is not enabled, eeh sysfs will not be
created.
After applying this patch, following warnings are reduced:
sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:00.0/eeh_mode'
sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:00.0/eeh_config_addr'
sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:00.0/eeh_pe_config_addr'
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/kernel/eeh_sysfs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/eeh_sysfs.c b/arch/powerpc/kernel/eeh_sysfs.c
index 5d753d4..e2595ba 100644
--- a/arch/powerpc/kernel/eeh_sysfs.c
+++ b/arch/powerpc/kernel/eeh_sysfs.c
@@ -59,6 +59,9 @@ void eeh_sysfs_add_device(struct pci_dev *pdev)
struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
int rc=0;
+ if (!eeh_enabled())
+ return;
+
if (edev && (edev->mode & EEH_DEV_SYSFS))
return;
--
1.7.9.5
^ permalink raw reply related
* [PATCH] powerpc: 64bit sendfile is capped at 2GB
From: Anton Blanchard @ 2014-06-04 0:48 UTC (permalink / raw)
To: benh, paulus, catalin.marinas, azanella, arnd, viro, akpm
Cc: linuxppc-dev, linux-kernel
commit 8f9c0119d7ba (compat: fs: Generic compat_sys_sendfile
implementation) changed the PowerPC 64bit sendfile call from
sys_sendile64 to sys_sendfile.
Unfortunately this broke sendfile of lengths greater than 2G because
sys_sendfile caps at MAX_NON_LFS. Restore what we had previously which
fixes the bug.
Cc: stable@vger.kernel.org
Signed-off-by: Anton Blanchard <anton@samba.org>
---
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index ac062f5..35f8f2f 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -190,7 +190,7 @@ SYSCALL_SPU(getcwd)
SYSCALL_SPU(capget)
SYSCALL_SPU(capset)
COMPAT_SYS(sigaltstack)
-COMPAT_SYS_SPU(sendfile)
+SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
SYSCALL(ni_syscall)
SYSCALL(ni_syscall)
PPC_SYS(vfork)
^ permalink raw reply related
* Re: [PATCH] powerpc, kexec: Fix "Processor X is stuck" issue during kexec from ST mode
From: Benjamin Herrenschmidt @ 2014-06-03 22:09 UTC (permalink / raw)
To: Srivatsa S. Bhat
Cc: ego, matt, mahesh, kexec, linux-kernel, suzuki, ebiederm, paulus,
linuxppc-dev, Vivek Goyal
In-Reply-To: <538E2FF8.8060707@linux.vnet.ibm.com>
On Wed, 2014-06-04 at 01:58 +0530, Srivatsa S. Bhat wrote:
> Yep, that makes sense. But unfortunately I don't have enough insight into
> why exactly powerpc has to online the CPUs before doing a kexec. I just
> know from the commit log and the comment mentioned above (and from my own
> experiments) that the CPUs will get stuck if they were offline. Perhaps
> somebody more knowledgeable can explain this in detail and suggest a proper
> long-term solution.
>
> Matt, Ben, any thoughts on this?
The problem is with our "soft offline" which we do on some platforms. When we
offline we don't actually send the CPUs back to firmware or anything like that.
We put them into a very low low power loop inside Linux.
The new kernel has no way to extract them from that loop. So we must re-"online"
them before we kexec so they can be passed to the new kernel normally (or returned
to firmware like we do on powernv).
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc, kexec: Fix "Processor X is stuck" issue during kexec from ST mode
From: Srivatsa S. Bhat @ 2014-06-03 20:28 UTC (permalink / raw)
To: Vivek Goyal
Cc: ego, matt, kexec, linux-kernel, suzuki, ebiederm, mahesh, paulus,
linuxppc-dev
In-Reply-To: <20140528133143.GK14863@redhat.com>
On 05/28/2014 07:01 PM, Vivek Goyal wrote:
> On Tue, May 27, 2014 at 04:25:34PM +0530, Srivatsa S. Bhat wrote:
>> If we try to perform a kexec when the machine is in ST (Single-Threaded) mode
>> (ppc64_cpu --smt=off), the kexec operation doesn't succeed properly, and we
>> get the following messages during boot:
>>
>> [ 0.089866] POWER8 performance monitor hardware support registered
>> [ 0.089985] power8-pmu: PMAO restore workaround active.
>> [ 5.095419] Processor 1 is stuck.
>> [ 10.097933] Processor 2 is stuck.
>> [ 15.100480] Processor 3 is stuck.
>> [ 20.102982] Processor 4 is stuck.
>> [ 25.105489] Processor 5 is stuck.
>> [ 30.108005] Processor 6 is stuck.
>> [ 35.110518] Processor 7 is stuck.
>> [ 40.113369] Processor 9 is stuck.
>> [ 45.115879] Processor 10 is stuck.
>> [ 50.118389] Processor 11 is stuck.
>> [ 55.120904] Processor 12 is stuck.
>> [ 60.123425] Processor 13 is stuck.
>> [ 65.125970] Processor 14 is stuck.
>> [ 70.128495] Processor 15 is stuck.
>> [ 75.131316] Processor 17 is stuck.
>>
>> Note that only the sibling threads are stuck, while the primary threads (0, 8,
>> 16 etc) boot just fine. Looking closer at the previous step of kexec, we observe
>> that kexec tries to wakeup (bring online) the sibling threads of all the cores,
>> before performing kexec:
>>
>> [ 9464.131231] Starting new kernel
>> [ 9464.148507] kexec: Waking offline cpu 1.
>> [ 9464.148552] kexec: Waking offline cpu 2.
>> [ 9464.148600] kexec: Waking offline cpu 3.
>> [ 9464.148636] kexec: Waking offline cpu 4.
>> [ 9464.148671] kexec: Waking offline cpu 5.
>> [ 9464.148708] kexec: Waking offline cpu 6.
>> [ 9464.148743] kexec: Waking offline cpu 7.
>> [ 9464.148779] kexec: Waking offline cpu 9.
>> [ 9464.148815] kexec: Waking offline cpu 10.
>> [ 9464.148851] kexec: Waking offline cpu 11.
>> [ 9464.148887] kexec: Waking offline cpu 12.
>> [ 9464.148922] kexec: Waking offline cpu 13.
>> [ 9464.148958] kexec: Waking offline cpu 14.
>> [ 9464.148994] kexec: Waking offline cpu 15.
>> [ 9464.149030] kexec: Waking offline cpu 17.
>>
>> Instrumenting this piece of code revealed that the cpu_up() operation actually
>> fails with -EBUSY. Thus, only the primary threads of all the cores are online
>> during kexec, and hence this is a sure-shot receipe for disaster, as explained
>> in commit e8e5c2155b (powerpc/kexec: Fix orphaned offline CPUs across kexec),
>> as well as in the comment above wake_offline_cpus().
>>
>> It turns out that cpu_up() was returning -EBUSY because the variable
>> 'cpu_hotplug_disabled' was set to 1; and this disabling of CPU hotplug was done
>> by migrate_to_reboot_cpu() inside kernel_kexec().
>>
>> Now, migrate_to_reboot_cpu() was originally written with the assumption that
>> any further code will not need to perform CPU hotplug, since we are anyway in
>> the reboot path. However, kexec is clearly not such a case, since we depend on
>> onlining CPUs, atleast on powerpc.
>>
>> So re-enable cpu-hotplug after returning from migrate_to_reboot_cpu() in the
>> kexec path, to fix this regression in kexec on powerpc.
>>
>> Also, wrap the cpu_up() in powerpc kexec code within a WARN_ON(), so that we
>> can catch such issues more easily in the future.
>>
>> Fixes: c97102ba963 (kexec: migrate to reboot cpu)
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com>
>> ---
>>
>> arch/powerpc/kernel/machine_kexec_64.c | 2 +-
>> kernel/kexec.c | 8 ++++++++
>> 2 files changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
>> index 59d229a..879b3aa 100644
>> --- a/arch/powerpc/kernel/machine_kexec_64.c
>> +++ b/arch/powerpc/kernel/machine_kexec_64.c
>> @@ -237,7 +237,7 @@ static void wake_offline_cpus(void)
>> if (!cpu_online(cpu)) {
>> printk(KERN_INFO "kexec: Waking offline cpu %d.\n",
>> cpu);
>> - cpu_up(cpu);
>> + WARN_ON(cpu_up(cpu));
>> }
>> }
>> }
>> diff --git a/kernel/kexec.c b/kernel/kexec.c
>> index c8380ad..28c5706 100644
>> --- a/kernel/kexec.c
>> +++ b/kernel/kexec.c
>> @@ -1683,6 +1683,14 @@ int kernel_kexec(void)
>> kexec_in_progress = true;
>> kernel_restart_prepare(NULL);
>> migrate_to_reboot_cpu();
>> +
>> + /*
>> + * migrate_to_reboot_cpu() disables CPU hotplug assuming that
>> + * no further code needs to use CPU hotplug (which is true in
>> + * the reboot case). However, the kexec path depends on using
>> + * CPU hotplug again; so re-enable it here.
>> + */
>> + cpu_hotplug_enable();
>> printk(KERN_EMERG "Starting new kernel\n");
>> machine_shutdown();
>
> After migrate_to_reboot_cpu(), we are calling machine_shutdown() which
> calls disable_nonboot_cpus() and which in turn calls _cpu_down().
>
Hmm? I see only 'arm' calling disable_nonboot_cpus() from machine_shutdown().
None of the other architectures call it. Is that a leftover in arm?
> So it is kind of odd that we first migrate to boot cpu, and then disable
> all non-boot cpus and after that powerpc goes ahead and onlines all
> cpus.
>
> I think this is not a good idea. For whatever reason if powerpc has to
> online all cpus, then it should happne earlier and not in machine_kexec().
>
> In fact I think generic code expects that all non-boot cpus are disabled
> so that generic code can use all the RAM as it wants to. Now if powerpc
> breaks that assumption, it will lead to various kind of issues.
>
> So I think we need to go back and see if we can find a way where we
> don't have to online all cpus in first kernel. And second kernel needs
> to have a way to detect it and online things.
>
Yep, that makes sense. But unfortunately I don't have enough insight into
why exactly powerpc has to online the CPUs before doing a kexec. I just
know from the commit log and the comment mentioned above (and from my own
experiments) that the CPUs will get stuck if they were offline. Perhaps
somebody more knowledgeable can explain this in detail and suggest a proper
long-term solution.
Matt, Ben, any thoughts on this?
Regards,
Srivatsa S. Bhat
^ permalink raw reply
* Re: FMD15 and t104x
From: Scott Wood @ 2014-06-03 18:29 UTC (permalink / raw)
To: Tony; +Cc: linuxppc-dev
In-Reply-To: <CAE1uq6sUdG3fFYSdagSdROUpdNeRi8Prg5mfr088jxg5SWM3LQ@mail.gmail.com>
On Tue, 2014-06-03 at 12:13 +0530, Tony wrote:
> Hi,
>
> I am working with 3.0.x kernel with fmd15. I could bringup the
> t1040qsd but the ethernet is not getting detected. Is t104x devices
> required backporting of FMD19 ? OR modifying the dts file is enough ?
Please use support@freescale.com or https://community.freescale.com/ for
support of the QorIQ SDK.
That said, I'm pretty sure the FMan code from any 3.0-based SDK will not
work with t1040.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc/85xx: Add T4240RDB board support
From: Scott Wood @ 2014-06-03 16:12 UTC (permalink / raw)
To: Chunhe Lan; +Cc: linuxppc-dev, Chunhe Lan
In-Reply-To: <538D8E15.5070506@freescale.com>
On Tue, 2014-06-03 at 16:57 +0800, Chunhe Lan wrote:
> On 05/31/2014 05:25 AM, Scott Wood wrote:
> > On Wed, 2014-05-28 at 16:11 +0800, Chunhe Lan wrote:
> >> diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
> >> index 8e4b1e1..2f50526 100644
> >> --- a/arch/powerpc/platforms/85xx/corenet_generic.c
> >> +++ b/arch/powerpc/platforms/85xx/corenet_generic.c
> >> @@ -119,6 +119,7 @@ static const char * const boards[] __initconst = {
> >> "fsl,P5020DS",
> >> "fsl,P5040DS",
> >> "fsl,T4240QDS",
> >> + "fsl,T4240RDB",
> >> "fsl,B4860QDS",
> >> "fsl,B4420QDS",
> >> "fsl,B4220QDS",
> > What about hv_boards?
> Does not have hv boards. So does not support hv.
This isn't about a physical "hv board". Topaz appends -hv to the board
compatible. I wish we had just made a single "Topaz e500 platform" like
we did for qemu e500, but oh well.
-Scott
^ permalink raw reply
* Re: [PATCH v2] powerpc/booke64: wrap tlb lock and search in htw miss with FTR_SMT
From: Tudor Laurentiu @ 2014-06-03 14:49 UTC (permalink / raw)
To: Scott Wood; +Cc: Laurentiu Tudor, linuxppc-dev
In-Reply-To: <1401727559.6603.227.camel@snotra.buserror.net>
On 06/02/2014 07:45 PM, Scott Wood wrote:
> On Mon, 2014-06-02 at 15:48 +0300, Tudor Laurentiu wrote:
>> On 05/31/2014 01:45 AM, Scott Wood wrote:
>>> From: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
>>> - resent since the original didn't make it to the list archives
>>> or patchwork.
>>
>> The only thing i can think of is that maybe i've misspelled the mailing
>> list address ...
>
> It looks right to me. Did you get a bounce?
>
Strangely, no. I'm out of ideas.
---
Best Regards, Laurentiu
^ permalink raw reply
* [PATCH] KVM: PPC: BOOK3S: PR: Fix PURR and SPURR emulation
From: Aneesh Kumar K.V @ 2014-06-03 12:16 UTC (permalink / raw)
To: agraf, benh, paulus; +Cc: linuxppc-dev, kvm, kvm-ppc, Aneesh Kumar K.V
We use time base for PURR and SPURR emulation with PR KVM since we
are emulating a single threaded core. When using time base
we need to make sure that we don't accumulate time spent in the host
in PURR and SPURR value.
Also we don't need to emulate mtspr because both the registers are
hypervisor resource.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/kvm_book3s.h | 2 --
arch/powerpc/include/asm/kvm_host.h | 4 ++--
arch/powerpc/kvm/book3s_emulate.c | 16 ++++++++--------
arch/powerpc/kvm/book3s_pr.c | 10 ++++++++++
4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index f52f65694527..a20cc0bbd048 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -83,8 +83,6 @@ struct kvmppc_vcpu_book3s {
u64 sdr1;
u64 hior;
u64 msr_mask;
- u64 purr_offset;
- u64 spurr_offset;
#ifdef CONFIG_PPC_BOOK3S_32
u32 vsid_pool[VSID_POOL_SIZE];
u32 vsid_next;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index bb66d8b8efdf..4a58731a0a72 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -503,8 +503,8 @@ struct kvm_vcpu_arch {
#ifdef CONFIG_BOOKE
u32 decar;
#endif
- u32 tbl;
- u32 tbu;
+ /* Time base value when we entered the guest */
+ u64 entry_tb;
u32 tcr;
ulong tsr; /* we need to perform set/clr_bits() which requires ulong */
u32 ivor[64];
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c
index 3f295269af37..3565e775b61b 100644
--- a/arch/powerpc/kvm/book3s_emulate.c
+++ b/arch/powerpc/kvm/book3s_emulate.c
@@ -439,12 +439,6 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
(mfmsr() & MSR_HV))
vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
break;
- case SPRN_PURR:
- to_book3s(vcpu)->purr_offset = spr_val - get_tb();
- break;
- case SPRN_SPURR:
- to_book3s(vcpu)->spurr_offset = spr_val - get_tb();
- break;
case SPRN_GQR0:
case SPRN_GQR1:
case SPRN_GQR2:
@@ -572,10 +566,16 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val
*spr_val = 0;
break;
case SPRN_PURR:
- *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
+ /*
+ * On exit we would have updated purr
+ */
+ *spr_val = vcpu->arch.purr;
break;
case SPRN_SPURR:
- *spr_val = get_tb() + to_book3s(vcpu)->purr_offset;
+ /*
+ * On exit we would have updated spurr
+ */
+ *spr_val = vcpu->arch.spurr;
break;
case SPRN_GQR0:
case SPRN_GQR1:
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 23367a7e44c3..c71ce784a72f 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -121,6 +121,11 @@ void kvmppc_copy_to_svcpu(struct kvmppc_book3s_shadow_vcpu *svcpu,
svcpu->shadow_fscr = vcpu->arch.shadow_fscr;
#endif
svcpu->in_use = true;
+ /*
+ * Now also save the current time base value. We use this
+ * to find the guest purr and spurr value.
+ */
+ vcpu->arch.entry_tb = get_tb();
}
/* Copy data touched by real-mode code from shadow vcpu back to vcpu */
@@ -170,6 +175,11 @@ void kvmppc_copy_from_svcpu(struct kvm_vcpu *vcpu,
out:
preempt_enable();
+ /*
+ * Update purr and spurr using time base
+ */
+ vcpu->arch.purr += get_tb() - vcpu->arch.entry_tb;
+ vcpu->arch.spurr += get_tb() - vcpu->arch.entry_tb;
}
static int kvmppc_core_check_requests_pr(struct kvm_vcpu *vcpu)
--
1.9.1
^ permalink raw reply related
* [PATCH v3] powerpc/85xx: Add T4240RDB board support
From: Chunhe Lan @ 2014-06-03 10:25 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, Chunhe Lan
T4240RDB board Specification
----------------------------
Memory subsystem:
6GB DDR3
128MB NOR flash
2GB NAND flash
Ethernet:
Eight 1G SGMII ports
Four 10Gbps SFP+ ports
PCIe:
Two PCIe slots
USB:
Two USB2.0 Type A ports
SDHC:
One SD-card port
SATA:
One SATA port
UART:
Dual RJ45 ports
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
---
arch/powerpc/boot/dts/t4240rdb.dts | 186 +++++++++++++++++++++++++
arch/powerpc/configs/corenet64_smp_defconfig | 4 +
arch/powerpc/platforms/85xx/Kconfig | 2 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +
4 files changed, 193 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/t4240rdb.dts
diff --git a/arch/powerpc/boot/dts/t4240rdb.dts b/arch/powerpc/boot/dts/t4240rdb.dts
new file mode 100644
index 0000000..53761d4
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240rdb.dts
@@ -0,0 +1,186 @@
+/*
+ * T4240RDB Device Tree Source
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/t4240si-pre.dtsi"
+
+/ {
+ model = "fsl,T4240RDB";
+ compatible = "fsl,T4240RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&mpic>;
+
+ ifc: localbus@ffe124000 {
+ reg = <0xf 0xfe124000 0 0x2000>;
+ ranges = <0 0 0xf 0xe8000000 0x08000000
+ 2 0 0xf 0xff800000 0x00010000
+ 3 0 0xf 0xffdf0000 0x00008000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,ifc-nand";
+ reg = <0x2 0x0 0x10000>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ dcsr: dcsr@f00000000 {
+ ranges = <0x00000000 0xf 0x00000000 0x01072000>;
+ };
+
+ soc: soc@ffe000000 {
+ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+ reg = <0xf 0xfe000000 0 0x00001000>;
+ spi@110000 {
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf040";
+ reg = <0>;
+ spi-max-frequency = <40000000>; /* input clock */
+ };
+ };
+
+ i2c@118000 {
+ eeprom@52 {
+ compatible = "at24,24c256";
+ reg = <0x52>;
+ };
+ eeprom@54 {
+ compatible = "at24,24c256";
+ reg = <0x54>;
+ };
+ eeprom@56 {
+ compatible = "at24,24c256";
+ reg = <0x56>;
+ };
+ rtc@68 {
+ compatible = "dallas,ds1374";
+ reg = <0x68>;
+ interrupts = <0x1 0x1 0 0>;
+ };
+ };
+
+ sdhc@114000 {
+ voltage-ranges = <1800 1800 3300 3300>;
+ };
+ };
+
+ pci0: pcie@ffe240000 {
+ reg = <0xf 0xfe240000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci1: pcie@ffe250000 {
+ reg = <0xf 0xfe250000 0 0x10000>;
+ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci2: pcie@ffe260000 {
+ reg = <0xf 0xfe260000 0 0x1000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ pci3: pcie@ffe270000 {
+ reg = <0xf 0xfe270000 0 0x10000>;
+ ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
+ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+ pcie@0 {
+ ranges = <0x02000000 0 0xe0000000
+ 0x02000000 0 0xe0000000
+ 0 0x20000000
+
+ 0x01000000 0 0x00000000
+ 0x01000000 0 0x00000000
+ 0 0x00010000>;
+ };
+ };
+
+ rio: rapidio@ffe0c0000 {
+ reg = <0xf 0xfe0c0000 0 0x11000>;
+
+ port1 {
+ ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+ };
+ port2 {
+ ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+ };
+ };
+};
+
+/include/ "fsl/t4240si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 5c7fa19..4f17b3d 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -96,6 +96,8 @@ CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
CONFIG_E1000E=y
+CONFIG_PHYLIB=y
+CONFIG_VITESSE_PHY=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
@@ -125,6 +127,8 @@ CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1374=y
CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y
CONFIG_EXT2_FS=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index c17aae8..d66321e 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -265,7 +265,7 @@ config CORENET_GENERIC
For 32bit kernel, the following boards are supported:
P2041 RDB, P3041 DS and P4080 DS
For 64bit kernel, the following boards are supported:
- T4240 QDS and B4 QDS
+ T4240 QDS/RDB and B4 QDS
The following boards are supported for both 32bit and 64bit kernel:
P5020 DS and P5040 DS
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8e4b1e1..3d91a26 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -119,6 +119,7 @@ static const char * const boards[] __initconst = {
"fsl,P5020DS",
"fsl,P5040DS",
"fsl,T4240QDS",
+ "fsl,T4240RDB",
"fsl,B4860QDS",
"fsl,B4420QDS",
"fsl,B4220QDS",
@@ -132,6 +133,7 @@ static const char * const hv_boards[] __initconst = {
"fsl,P5020DS-hv",
"fsl,P5040DS-hv",
"fsl,T4240QDS-hv",
+ "fsl,T4240RDB-hv",
"fsl,B4860QDS-hv",
"fsl,B4420QDS-hv",
"fsl,B4220QDS-hv",
--
1.7.6.5
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