* [PATCH v3 01/10] tools/perf: support parsing parameterized events
From: Sukadev Bhattiprolu @ 2014-09-17 18:51 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: Michael Ellerman, linux-kernel, dev, linuxppc-dev,
Anshuman Khandual
In-Reply-To: <1410979923-7722-1-git-send-email-sukadev@linux.vnet.ibm.com>
From: Cody P Schafer <cody@linux.vnet.ibm.com>
Enable event specification like:
pmu/event_name,param1=0x1,param2=0x4/
Assuming that
/sys/bus/event_source/devices/pmu/events/event_name
Contains something like
param2=foo,bar=1,param1=baz
Changelog[v6]:
[Jiri Olsa] If the sysfs event file specifies 'param=val', make the
usage 'hv_24x7/event,param=123/' rather than 'hv_24x7/event,val=123/'.
[Sukadev Bhattiprolu] If verbose option is set, print help message
if a required parameter is missing or invalid parameter is specified.
CC: Haren Myneni <hbabu@us.ibm.com>
CC: Cody P Schafer <dev@codyps.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
---
tools/perf/util/parse-events.h | 1 +
tools/perf/util/pmu.c | 64 +++++++++++++++++++++++++++++++++-------
2 files changed, 54 insertions(+), 11 deletions(-)
diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h
index df094b4..9d7d2d5 100644
--- a/tools/perf/util/parse-events.h
+++ b/tools/perf/util/parse-events.h
@@ -59,6 +59,7 @@ struct parse_events_term {
int type_val;
int type_term;
struct list_head list;
+ bool used;
};
struct parse_events_evlist {
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 9bf5827..8c7c4a1 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -504,30 +504,67 @@ static __u64 pmu_format_value(unsigned long *format, __u64 value)
}
/*
+ * Term is a string term, and might be a param-term. Try to look up it's value
+ * in the remaining terms.
+ * - We have a term like "base-or-format-term=param-term",
+ * - We need to find the value supplied for "param-term" (with param-term named
+ * in a config string) later on in the term list.
+ */
+static int pmu_resolve_param_term(struct parse_events_term *term,
+ struct list_head *head_terms,
+ __u64 *value)
+{
+ struct parse_events_term *t;
+
+ list_for_each_entry(t, head_terms, list) {
+ if (t->type_val == PARSE_EVENTS__TERM_TYPE_NUM) {
+ if (!strcmp(t->config, term->config)) {
+ t->used = true;
+ *value = t->val.num;
+ return 0;
+ }
+ }
+ }
+
+ if (verbose)
+ printf("Required parameter '%s' not specified\n", term->config);
+
+ return -1;
+}
+
+/*
* Setup one of config[12] attr members based on the
* user input data - term parameter.
*/
static int pmu_config_term(struct list_head *formats,
struct perf_event_attr *attr,
- struct parse_events_term *term)
+ struct parse_events_term *term,
+ struct list_head *head_terms)
{
struct perf_pmu_format *format;
__u64 *vp;
+ __u64 val;
+
+ /*
+ * If this is a parameter we've already used for parameterized-eval,
+ * skip it in normal eval.
+ */
+ if (term->used)
+ return 0;
/*
- * Support only for hardcoded and numnerial terms.
* Hardcoded terms should be already in, so nothing
* to be done for them.
*/
if (parse_events__is_hardcoded_term(term))
return 0;
- if (term->type_val != PARSE_EVENTS__TERM_TYPE_NUM)
- return -EINVAL;
-
format = pmu_find_format(formats, term->config);
- if (!format)
+ if (!format) {
+ if (verbose)
+ printf("Invalid event/parameter '%s'\n", term->config);
return -EINVAL;
+ }
switch (format->value) {
case PERF_PMU_FORMAT_VALUE_CONFIG:
@@ -544,11 +581,16 @@ static int pmu_config_term(struct list_head *formats,
}
/*
- * XXX If we ever decide to go with string values for
- * non-hardcoded terms, here's the place to translate
- * them into value.
+ * Either directly use a numeric term, or try to translate string terms
+ * using event parameters.
*/
- *vp |= pmu_format_value(format->bits, term->val.num);
+ if (term->type_val == PARSE_EVENTS__TERM_TYPE_NUM)
+ val = term->val.num;
+ else
+ if (pmu_resolve_param_term(term, head_terms, &val))
+ return -EINVAL;
+
+ *vp |= pmu_format_value(format->bits, val);
return 0;
}
@@ -559,7 +601,7 @@ int perf_pmu__config_terms(struct list_head *formats,
struct parse_events_term *term;
list_for_each_entry(term, head_terms, list)
- if (pmu_config_term(formats, attr, term))
+ if (pmu_config_term(formats, attr, term, head_terms))
return -EINVAL;
return 0;
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 02/10] tools/perf: extend format_alias() to include event parameters
From: Sukadev Bhattiprolu @ 2014-09-17 18:51 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: Michael Ellerman, linux-kernel, dev, linuxppc-dev,
Anshuman Khandual
In-Reply-To: <1410979923-7722-1-git-send-email-sukadev@linux.vnet.ibm.com>
From: Cody P Schafer <cody@linux.vnet.ibm.com>
This causes `perf list pmu` to show parameters for parameterized events
like follows:
pmu/event_name,param1=?,param2=?/ [Kernel PMU event]
An example:
hv_gpci/dispatch_timebase_by_processor_processor_time_in_timebase_cycles,phys_processor_idx=?/ [Kernel PMU event]
Changelog[v6]
[Jir Olsa] If the parameter for an event in sysfs is 'param=val',
have perf-list show the event as 'param=?' rather than 'val=?'.
CC: Haren Myneni <hbabu@us.ibm.com>
CC: Cody P Schafer <dev@codyps.com>
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
tools/perf/util/pmu.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 8c7c4a1..0756917 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -748,10 +748,33 @@ void perf_pmu__set_format(unsigned long *bits, long from, long to)
set_bit(b, bits);
}
+static int sub_non_neg(int a, int b)
+{
+ if (b > a)
+ return 0;
+ return a - b;
+}
+
static char *format_alias(char *buf, int len, struct perf_pmu *pmu,
struct perf_pmu_alias *alias)
{
- snprintf(buf, len, "%s/%s/", pmu->name, alias->name);
+ struct parse_events_term *term;
+ int used = snprintf(buf, len, "%s/%s", pmu->name, alias->name);
+
+ list_for_each_entry(term, &alias->terms, list)
+ if (term->type_val == PARSE_EVENTS__TERM_TYPE_STR)
+ used += snprintf(buf + used, sub_non_neg(len, used),
+ ",%s=?", term->config);
+
+ if (sub_non_neg(len, used) > 0) {
+ buf[used] = '/';
+ used++;
+ }
+ if (sub_non_neg(len, used) > 0) {
+ buf[used] = '\0';
+ used++;
+ } else
+ buf[len - 1] = '\0';
return buf;
}
@@ -802,6 +825,7 @@ void print_pmu_events(const char *event_glob, bool name_only)
if (is_cpu && !name_only)
aliases[j] = format_alias_or(buf, sizeof(buf),
pmu, alias);
+
aliases[j] = strdup(aliases[j]);
j++;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 00/10] Add support for parameterized events from sysfs
From: Sukadev Bhattiprolu @ 2014-09-17 18:51 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: Michael Ellerman, linux-kernel, dev, linuxppc-dev,
Anshuman Khandual
What this patchset does:
- the first patch (override sysfs in tools/perf via SYSFS_PATH) was sent out
previously, but needed a resend anyhow. Having it is useful for testing the
later changes to tools/perf.
- the second patch is a bugfix to the powerpc hv-24x7 code which was
previously sent out, which is a good idea to have when testing these patches
on POWER8 hardware.
- document perf sysfs and the changes to add parameterized events
- semi-notably: removes the growing list of specific POWER cpu events and
begins documenting them generically, much like the docs for
/sys/modules/MODULENAME do for modules.
- tools/perf changes to support parameterized events
- export some parameterized events from the powerpc pmus hv_24x7 and hv_gpci
Description of "event parameters" from the documentation patch:
Event parameters are a basic way for partial events to be specified in
sysfs with per-event names given to the fields that need to be filled in
when using a particular event.
It is intended for supporting cases where the single 'cpu' parameter is
insufficient. For example, POWER 8 has events for physical
sockets/cores/cpus that are accessible from with virtual machines. To
keep using the single 'cpu' parameter we'd need to perform a mapping
between Linux's cpus and the physical machine's cpus (in this case
Linux is running under a hypervisor). This isn't possible because
bindings between our cpus and physical cpus may not be fixed, and we
probably won't have a "cpu" on each physical cpu.
Description of the sysfs contents when events are parameterized (copied from an
included patch):
Examples:
domain=0x1,offset=0x8,starting_index=phys_cpu
In the case of the last example, a value replacing "phys_cpu"
would need to be provided by the user selecting the particular
event. This is refered to as "event parameterization". All
non-numerical values indicate an event parameter.
Notes on how perf-list displays parameterized events (and how to use them,
again culled from an included patch):
PARAMETERIZED EVENTS
--------------------
Some pmu events listed by 'perf-list' will be displayed with '?' in
them. For example:
hv_gpci/dtbp_ptitc,phys_processor_idx=?/
This means that when provided as an event, a value for
phys_processor_idx must also be supplied. For example:
perf stat -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
Changelog[v3]
- [Jiri Olsa] Changed the event parameters are specified. If
event file specifes 'param=val' make the usage 'param=123'
rather than 'val=123'. (patch 1,2/10)
- Shortened event names using "PHYS" and "VCPU" (patch 4/10)
- Print help message if invalid parameter is specified or required
parameter is missing.
- Moved 3 patches that are unrelated to parametrized events into
a separate patchset.
- Reordered patches so code changes come first.
Changelog[v2]
- [Joe Perches, David Laight] Use beNN_to_cpu() instead of guessing
the size from type.
- Use kmem_cache_free() to free page allocated with kmem_cache_alloc().
- Rebase to recent kernel
*** BLURB HERE ***
Cody P Schafer (10):
tools/perf: support parsing parameterized events
tools/perf: extend format_alias() to include event parameters
perf: provide sysfs_show for struct perf_pmu_events_attr
powerpc/perf/hv-24x7: parse catalog and populate sysfs with events
perf: add PMU_EVENT_ATTR_STRING() helper
powerpc/perf/{hv-gpci,hv-common}: generate requests with counters
annotated
powerpc/perf/hv-gpci: add the remaining gpci requests
perf Documentation: add event parameters
tools/perf: Document parameterized and symbolic events
powerpc/perf/hv-24x7: Document sysfs event description entries
.../testing/sysfs-bus-event_source-devices-events | 6 +
.../testing/sysfs-bus-event_source-devices-hv_24x7 | 22 +
arch/powerpc/perf/hv-24x7-catalog.h | 25 +
arch/powerpc/perf/hv-24x7-domains.h | 28 +
arch/powerpc/perf/hv-24x7.c | 787 +++++++++++++++++++-
arch/powerpc/perf/hv-24x7.h | 12 +-
arch/powerpc/perf/hv-common.c | 10 +-
arch/powerpc/perf/hv-gpci-requests.h | 262 +++++++
arch/powerpc/perf/hv-gpci.c | 8 +
arch/powerpc/perf/hv-gpci.h | 37 +-
arch/powerpc/perf/req-gen/_begin.h | 13 +
arch/powerpc/perf/req-gen/_clear.h | 5 +
arch/powerpc/perf/req-gen/_end.h | 4 +
arch/powerpc/perf/req-gen/_request-begin.h | 15 +
arch/powerpc/perf/req-gen/_request-end.h | 8 +
arch/powerpc/perf/req-gen/perf.h | 155 ++++
include/linux/perf_event.h | 10 +
kernel/events/core.c | 8 +
tools/perf/Documentation/perf-list.txt | 13 +
tools/perf/Documentation/perf-record.txt | 12 +
tools/perf/Documentation/perf-stat.txt | 20 +-
tools/perf/util/parse-events.h | 1 +
tools/perf/util/pmu.c | 90 ++-
23 files changed, 1491 insertions(+), 60 deletions(-)
create mode 100644 arch/powerpc/perf/hv-24x7-domains.h
create mode 100644 arch/powerpc/perf/hv-gpci-requests.h
create mode 100644 arch/powerpc/perf/req-gen/_begin.h
create mode 100644 arch/powerpc/perf/req-gen/_clear.h
create mode 100644 arch/powerpc/perf/req-gen/_end.h
create mode 100644 arch/powerpc/perf/req-gen/_request-begin.h
create mode 100644 arch/powerpc/perf/req-gen/_request-end.h
create mode 100644 arch/powerpc/perf/req-gen/perf.h
--
1.7.9.5
^ permalink raw reply
* [PATCH 3/4] perf Documentation: sysfs events/ interfaces
From: Sukadev Bhattiprolu @ 2014-09-17 18:33 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: linuxppc-dev, dev, linux-kernel, Michael Ellerman,
Anshuman Khandual
In-Reply-To: <1410978787-7375-1-git-send-email-sukadev@linux.vnet.ibm.com>
From: Cody P Schafer <cody@linux.vnet.ibm.com>
Add documentation for the <event>, <event>.scale, and <event>.unit
files in sysfs.
<event>.scale and <event>.unit were undocumented.
<event> was previously documented only for specific powerpc pmu events.
CC: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
CC: Haren Myneni <hbabu@us.ibm.com>
CC: Cody P Schafer <dev@codyps.com>
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
---
.../testing/sysfs-bus-event_source-devices-events | 60 ++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
index 7b40a3c..a5226f0 100644
--- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
+++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
@@ -599,3 +599,63 @@ Description: POWER-systems specific performance monitoring events
Further, multiple terms like 'event=0xNNNN' can be specified
and separated with comma. All available terms are defined in
the /sys/bus/event_source/devices/<dev>/format file.
+
+What: /sys/bus/event_source/devices/<pmu>/events/<event>
+Date: 2014/02/24
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description: Per-pmu performance monitoring events specific to the running system
+
+ Each file (except for some of those with a '.' in them, '.unit'
+ and '.scale') in the 'events' directory describes a single
+ performance monitoring event supported by the <pmu>. The name
+ of the file is the name of the event.
+
+ File contents:
+
+ <term>[=<value>][,<term>[=<value>]]...
+
+ Where <term> is one of the terms listed under
+ /sys/bus/event_source/devices/<pmu>/format/ and <value> is
+ a number is base-16 format with a '0x' prefix (lowercase only).
+ If a <term> is specified alone (without an assigned value), it
+ is implied that 0x1 is assigned to that <term>.
+
+ Examples (each of these lines would be in a seperate file):
+
+ event=0x2abc
+ event=0x423,inv,cmask=0x3
+ domain=0x1,offset=0x8,starting_index=0xffff
+
+ Each of the assignments indicates a value to be assigned to a
+ particular set of bits (as defined by the format file
+ corresponding to the <term>) in the perf_event structure passed
+ to the perf_open syscall.
+
+What: /sys/bus/event_source/devices/<pmu>/events/<event>.unit
+Date: 2014/02/24
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description: Perf event units
+
+ A string specifying the English plural numerical unit that <event>
+ (once multiplied by <event>.scale) represents.
+
+ Example:
+
+ Joules
+
+What: /sys/bus/event_source/devices/<pmu>/events/<event>.scale
+Date: 2014/02/24
+Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
+Description: Perf event scaling factors
+
+ A string representing a floating point value expressed in
+ scientific notation to be multiplied by the event count
+ recieved from the kernel to match the unit specified in the
+ <event>.unit file.
+
+ Example:
+
+ 2.3283064365386962890625e-10
+
+ This is provided to avoid performing floating point arithmetic
+ in the kernel.
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/4] perf Documentation: remove duplicated docs for powerpc cpu specific events
From: Sukadev Bhattiprolu @ 2014-09-17 18:33 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: linuxppc-dev, dev, linux-kernel, Michael Ellerman,
Anshuman Khandual
In-Reply-To: <1410978787-7375-1-git-send-email-sukadev@linux.vnet.ibm.com>
From: Cody P Schafer <cody@linux.vnet.ibm.com>
Listing specific events doesn't actually help us at all here because:
- these events actually vary between different ppc processors, they
aren't garunteed to be present.
- the documentation of the (generic) file contents is now superceded by the
docs for arbitrary event file contents.
CC: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
CC: Haren Myneni <hbabu@us.ibm.com>
CC: Cody P Schafer <dev@codyps.com>
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
---
.../testing/sysfs-bus-event_source-devices-events | 573 --------------------
1 file changed, 573 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
index a5226f0..20979f8 100644
--- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
+++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-events
@@ -27,579 +27,6 @@ Description: Generic performance monitoring events
"basename".
-What: /sys/devices/cpu/events/PM_1PLUS_PPC_CMPL
- /sys/devices/cpu/events/PM_BRU_FIN
- /sys/devices/cpu/events/PM_BR_MPRED
- /sys/devices/cpu/events/PM_CMPLU_STALL
- /sys/devices/cpu/events/PM_CMPLU_STALL_BRU
- /sys/devices/cpu/events/PM_CMPLU_STALL_DCACHE_MISS
- /sys/devices/cpu/events/PM_CMPLU_STALL_DFU
- /sys/devices/cpu/events/PM_CMPLU_STALL_DIV
- /sys/devices/cpu/events/PM_CMPLU_STALL_ERAT_MISS
- /sys/devices/cpu/events/PM_CMPLU_STALL_FXU
- /sys/devices/cpu/events/PM_CMPLU_STALL_IFU
- /sys/devices/cpu/events/PM_CMPLU_STALL_LSU
- /sys/devices/cpu/events/PM_CMPLU_STALL_REJECT
- /sys/devices/cpu/events/PM_CMPLU_STALL_SCALAR
- /sys/devices/cpu/events/PM_CMPLU_STALL_SCALAR_LONG
- /sys/devices/cpu/events/PM_CMPLU_STALL_STORE
- /sys/devices/cpu/events/PM_CMPLU_STALL_THRD
- /sys/devices/cpu/events/PM_CMPLU_STALL_VECTOR
- /sys/devices/cpu/events/PM_CMPLU_STALL_VECTOR_LONG
- /sys/devices/cpu/events/PM_CYC
- /sys/devices/cpu/events/PM_GCT_NOSLOT_BR_MPRED
- /sys/devices/cpu/events/PM_GCT_NOSLOT_BR_MPRED_IC_MISS
- /sys/devices/cpu/events/PM_GCT_NOSLOT_CYC
- /sys/devices/cpu/events/PM_GCT_NOSLOT_IC_MISS
- /sys/devices/cpu/events/PM_GRP_CMPL
- /sys/devices/cpu/events/PM_INST_CMPL
- /sys/devices/cpu/events/PM_LD_MISS_L1
- /sys/devices/cpu/events/PM_LD_REF_L1
- /sys/devices/cpu/events/PM_RUN_CYC
- /sys/devices/cpu/events/PM_RUN_INST_CMPL
- /sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_ALL
- /sys/devices/cpu/events/PM_GCT_UTIL_7_TO_10_SLOTS
- /sys/devices/cpu/events/PM_PMC2_SAVED
- /sys/devices/cpu/events/PM_VSU0_16FLOP
- /sys/devices/cpu/events/PM_MRK_LSU_DERAT_MISS
- /sys/devices/cpu/events/PM_MRK_ST_CMPL
- /sys/devices/cpu/events/PM_NEST_PAIR3_ADD
- /sys/devices/cpu/events/PM_L2_ST_DISP
- /sys/devices/cpu/events/PM_L2_CASTOUT_MOD
- /sys/devices/cpu/events/PM_ISEG
- /sys/devices/cpu/events/PM_MRK_INST_TIMEO
- /sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_ADDR
- /sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM
- /sys/devices/cpu/events/PM_IERAT_WR_64K
- /sys/devices/cpu/events/PM_MRK_DTLB_MISS_16M
- /sys/devices/cpu/events/PM_IERAT_MISS
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_LMEM
- /sys/devices/cpu/events/PM_FLOP
- /sys/devices/cpu/events/PM_THRD_PRIO_4_5_CYC
- /sys/devices/cpu/events/PM_BR_PRED_TA
- /sys/devices/cpu/events/PM_EXT_INT
- /sys/devices/cpu/events/PM_VSU_FSQRT_FDIV
- /sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC
- /sys/devices/cpu/events/PM_LSU1_LDF
- /sys/devices/cpu/events/PM_IC_WRITE_ALL
- /sys/devices/cpu/events/PM_LSU0_SRQ_STFWD
- /sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR
- /sys/devices/cpu/events/PM_DATA_FROM_L21_MOD
- /sys/devices/cpu/events/PM_VSU1_SCAL_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_VSU0_8FLOP
- /sys/devices/cpu/events/PM_POWER_EVENT1
- /sys/devices/cpu/events/PM_DISP_CLB_HELD_BAL
- /sys/devices/cpu/events/PM_VSU1_2FLOP
- /sys/devices/cpu/events/PM_LWSYNC_HELD
- /sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_INST_FROM_L21_MOD
- /sys/devices/cpu/events/PM_IERAT_XLATE_WR_16MPLUS
- /sys/devices/cpu/events/PM_IC_REQ_ALL
- /sys/devices/cpu/events/PM_DSLB_MISS
- /sys/devices/cpu/events/PM_L3_MISS
- /sys/devices/cpu/events/PM_LSU0_L1_PREF
- /sys/devices/cpu/events/PM_VSU_SCALAR_SINGLE_ISSUED
- /sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE
- /sys/devices/cpu/events/PM_L2_INST
- /sys/devices/cpu/events/PM_VSU0_FRSP
- /sys/devices/cpu/events/PM_FLUSH_DISP
- /sys/devices/cpu/events/PM_PTEG_FROM_L2MISS
- /sys/devices/cpu/events/PM_VSU1_DQ_ISSUED
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM
- /sys/devices/cpu/events/PM_LSU_FLUSH_ULD
- /sys/devices/cpu/events/PM_PTEG_FROM_LMEM
- /sys/devices/cpu/events/PM_MRK_DERAT_MISS_16M
- /sys/devices/cpu/events/PM_THRD_ALL_RUN_CYC
- /sys/devices/cpu/events/PM_MEM0_PREFETCH_DISP
- /sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC_COUNT
- /sys/devices/cpu/events/PM_DATA_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_VSU_FRSP
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD
- /sys/devices/cpu/events/PM_PMC1_OVERFLOW
- /sys/devices/cpu/events/PM_VSU0_SINGLE
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3MISS
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_SHR
- /sys/devices/cpu/events/PM_VSU0_VECTOR_SP_ISSUED
- /sys/devices/cpu/events/PM_VSU1_FEST
- /sys/devices/cpu/events/PM_MRK_INST_DISP
- /sys/devices/cpu/events/PM_VSU0_COMPLEX_ISSUED
- /sys/devices/cpu/events/PM_LSU1_FLUSH_UST
- /sys/devices/cpu/events/PM_FXU_IDLE
- /sys/devices/cpu/events/PM_LSU0_FLUSH_ULD
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC
- /sys/devices/cpu/events/PM_LSU1_REJECT_LMQ_FULL
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_MOD
- /sys/devices/cpu/events/PM_INST_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_SHL_CREATED
- /sys/devices/cpu/events/PM_L2_ST_HIT
- /sys/devices/cpu/events/PM_DATA_FROM_DMEM
- /sys/devices/cpu/events/PM_L3_LD_MISS
- /sys/devices/cpu/events/PM_FXU1_BUSY_FXU0_IDLE
- /sys/devices/cpu/events/PM_DISP_CLB_HELD_RES
- /sys/devices/cpu/events/PM_L2_SN_SX_I_DONE
- /sys/devices/cpu/events/PM_STCX_CMPL
- /sys/devices/cpu/events/PM_VSU0_2FLOP
- /sys/devices/cpu/events/PM_L3_PREF_MISS
- /sys/devices/cpu/events/PM_LSU_SRQ_SYNC_CYC
- /sys/devices/cpu/events/PM_LSU_REJECT_ERAT_MISS
- /sys/devices/cpu/events/PM_L1_ICACHE_MISS
- /sys/devices/cpu/events/PM_LSU1_FLUSH_SRQ
- /sys/devices/cpu/events/PM_LD_REF_L1_LSU0
- /sys/devices/cpu/events/PM_VSU0_FEST
- /sys/devices/cpu/events/PM_VSU_VECTOR_SINGLE_ISSUED
- /sys/devices/cpu/events/PM_FREQ_UP
- /sys/devices/cpu/events/PM_DATA_FROM_LMEM
- /sys/devices/cpu/events/PM_LSU1_LDX
- /sys/devices/cpu/events/PM_PMC3_OVERFLOW
- /sys/devices/cpu/events/PM_MRK_BR_MPRED
- /sys/devices/cpu/events/PM_SHL_MATCH
- /sys/devices/cpu/events/PM_MRK_BR_TAKEN
- /sys/devices/cpu/events/PM_ISLB_MISS
- /sys/devices/cpu/events/PM_DISP_HELD_THERMAL
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_LSU1_SRQ_STFWD
- /sys/devices/cpu/events/PM_PTEG_FROM_DMEM
- /sys/devices/cpu/events/PM_VSU_2FLOP
- /sys/devices/cpu/events/PM_GCT_FULL_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L3_CYC
- /sys/devices/cpu/events/PM_LSU_SRQ_S0_ALLOC
- /sys/devices/cpu/events/PM_MRK_DERAT_MISS_4K
- /sys/devices/cpu/events/PM_BR_MPRED_TA
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L2MISS
- /sys/devices/cpu/events/PM_DPU_HELD_POWER
- /sys/devices/cpu/events/PM_MRK_VSU_FIN
- /sys/devices/cpu/events/PM_LSU_SRQ_S0_VALID
- /sys/devices/cpu/events/PM_GCT_EMPTY_CYC
- /sys/devices/cpu/events/PM_IOPS_DISP
- /sys/devices/cpu/events/PM_RUN_SPURR
- /sys/devices/cpu/events/PM_PTEG_FROM_L21_MOD
- /sys/devices/cpu/events/PM_VSU0_1FLOP
- /sys/devices/cpu/events/PM_SNOOP_TLBIE
- /sys/devices/cpu/events/PM_DATA_FROM_L3MISS
- /sys/devices/cpu/events/PM_VSU_SINGLE
- /sys/devices/cpu/events/PM_DTLB_MISS_16G
- /sys/devices/cpu/events/PM_FLUSH
- /sys/devices/cpu/events/PM_L2_LD_HIT
- /sys/devices/cpu/events/PM_NEST_PAIR2_AND
- /sys/devices/cpu/events/PM_VSU1_1FLOP
- /sys/devices/cpu/events/PM_IC_PREF_REQ
- /sys/devices/cpu/events/PM_L3_LD_HIT
- /sys/devices/cpu/events/PM_DISP_HELD
- /sys/devices/cpu/events/PM_L2_LD
- /sys/devices/cpu/events/PM_LSU_FLUSH_SRQ
- /sys/devices/cpu/events/PM_BC_PLUS_8_CONV
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD_CYC
- /sys/devices/cpu/events/PM_L2_RCST_BUSY_RC_FULL
- /sys/devices/cpu/events/PM_TB_BIT_TRANS
- /sys/devices/cpu/events/PM_THERMAL_MAX
- /sys/devices/cpu/events/PM_LSU1_FLUSH_ULD
- /sys/devices/cpu/events/PM_LSU1_REJECT_LHS
- /sys/devices/cpu/events/PM_LSU_LRQ_S0_ALLOC
- /sys/devices/cpu/events/PM_L3_CO_L31
- /sys/devices/cpu/events/PM_POWER_EVENT4
- /sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
- /sys/devices/cpu/events/PM_BR_UNCOND
- /sys/devices/cpu/events/PM_LSU1_DC_PREF_STREAM_ALLOC
- /sys/devices/cpu/events/PM_PMC4_REWIND
- /sys/devices/cpu/events/PM_L2_RCLD_DISP
- /sys/devices/cpu/events/PM_THRD_PRIO_2_3_CYC
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2MISS
- /sys/devices/cpu/events/PM_IC_DEMAND_L2_BHT_REDIRECT
- /sys/devices/cpu/events/PM_DATA_FROM_L31_SHR
- /sys/devices/cpu/events/PM_IC_PREF_CANCEL_L2
- /sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC_COUNT
- /sys/devices/cpu/events/PM_BR_PRED_CCACHE
- /sys/devices/cpu/events/PM_GCT_UTIL_1_TO_2_SLOTS
- /sys/devices/cpu/events/PM_MRK_ST_CMPL_INT
- /sys/devices/cpu/events/PM_LSU_TWO_TABLEWALK_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L3MISS
- /sys/devices/cpu/events/PM_LSU_SET_MPRED
- /sys/devices/cpu/events/PM_FLUSH_DISP_TLBIE
- /sys/devices/cpu/events/PM_VSU1_FCONV
- /sys/devices/cpu/events/PM_DERAT_MISS_16G
- /sys/devices/cpu/events/PM_INST_FROM_LMEM
- /sys/devices/cpu/events/PM_IC_DEMAND_L2_BR_REDIRECT
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L2
- /sys/devices/cpu/events/PM_PTEG_FROM_L2
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR_CYC
- /sys/devices/cpu/events/PM_MRK_DTLB_MISS_4K
- /sys/devices/cpu/events/PM_VSU0_FPSCR
- /sys/devices/cpu/events/PM_VSU1_VECT_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_MEM0_RQ_DISP
- /sys/devices/cpu/events/PM_L2_LD_MISS
- /sys/devices/cpu/events/PM_VMX_RESULT_SAT_1
- /sys/devices/cpu/events/PM_L1_PREF
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM_CYC
- /sys/devices/cpu/events/PM_GRP_IC_MISS_NONSPEC
- /sys/devices/cpu/events/PM_PB_NODE_PUMP
- /sys/devices/cpu/events/PM_SHL_MERGED
- /sys/devices/cpu/events/PM_NEST_PAIR1_ADD
- /sys/devices/cpu/events/PM_DATA_FROM_L3
- /sys/devices/cpu/events/PM_LSU_FLUSH
- /sys/devices/cpu/events/PM_LSU_SRQ_SYNC_COUNT
- /sys/devices/cpu/events/PM_PMC2_OVERFLOW
- /sys/devices/cpu/events/PM_LSU_LDF
- /sys/devices/cpu/events/PM_POWER_EVENT3
- /sys/devices/cpu/events/PM_DISP_WT
- /sys/devices/cpu/events/PM_IC_BANK_CONFLICT
- /sys/devices/cpu/events/PM_BR_MPRED_CR_TA
- /sys/devices/cpu/events/PM_L2_INST_MISS
- /sys/devices/cpu/events/PM_NEST_PAIR2_ADD
- /sys/devices/cpu/events/PM_MRK_LSU_FLUSH
- /sys/devices/cpu/events/PM_L2_LDST
- /sys/devices/cpu/events/PM_INST_FROM_L31_SHR
- /sys/devices/cpu/events/PM_VSU0_FIN
- /sys/devices/cpu/events/PM_VSU1_FCONV
- /sys/devices/cpu/events/PM_INST_FROM_RMEM
- /sys/devices/cpu/events/PM_DISP_CLB_HELD_TLBIE
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DMEM_CYC
- /sys/devices/cpu/events/PM_BR_PRED_CR
- /sys/devices/cpu/events/PM_LSU_REJECT
- /sys/devices/cpu/events/PM_GCT_UTIL_3_TO_6_SLOTS
- /sys/devices/cpu/events/PM_CMPLU_STALL_END_GCT_NOSLOT
- /sys/devices/cpu/events/PM_LSU0_REJECT_LMQ_FULL
- /sys/devices/cpu/events/PM_VSU_FEST
- /sys/devices/cpu/events/PM_NEST_PAIR0_AND
- /sys/devices/cpu/events/PM_PTEG_FROM_L3
- /sys/devices/cpu/events/PM_POWER_EVENT2
- /sys/devices/cpu/events/PM_IC_PREF_CANCEL_PAGE
- /sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV
- /sys/devices/cpu/events/PM_MRK_GRP_CMPL
- /sys/devices/cpu/events/PM_VSU0_SCAL_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_GRP_DISP
- /sys/devices/cpu/events/PM_LSU0_LDX
- /sys/devices/cpu/events/PM_DATA_FROM_L2
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_VSU0_VECT_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_VSU1_2FLOP_DOUBLE
- /sys/devices/cpu/events/PM_THRD_PRIO_6_7_CYC
- /sys/devices/cpu/events/PM_BC_PLUS_8_RSLV_TAKEN
- /sys/devices/cpu/events/PM_BR_MPRED_CR
- /sys/devices/cpu/events/PM_L3_CO_MEM
- /sys/devices/cpu/events/PM_DATA_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_LSU_SRQ_FULL_CYC
- /sys/devices/cpu/events/PM_TABLEWALK_CYC
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_RMEM
- /sys/devices/cpu/events/PM_LSU_SRQ_STFWD
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_RMEM
- /sys/devices/cpu/events/PM_FXU0_FIN
- /sys/devices/cpu/events/PM_LSU1_L1_SW_PREF
- /sys/devices/cpu/events/PM_PTEG_FROM_L31_MOD
- /sys/devices/cpu/events/PM_PMC5_OVERFLOW
- /sys/devices/cpu/events/PM_LD_REF_L1_LSU1
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L21_SHR
- /sys/devices/cpu/events/PM_DATA_FROM_RMEM
- /sys/devices/cpu/events/PM_VSU0_SCAL_SINGLE_ISSUED
- /sys/devices/cpu/events/PM_BR_MPRED_LSTACK
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_MOD_CYC
- /sys/devices/cpu/events/PM_LSU0_FLUSH_UST
- /sys/devices/cpu/events/PM_LSU_NCST
- /sys/devices/cpu/events/PM_BR_TAKEN
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_LMEM
- /sys/devices/cpu/events/PM_DTLB_MISS_4K
- /sys/devices/cpu/events/PM_PMC4_SAVED
- /sys/devices/cpu/events/PM_VSU1_PERMUTE_ISSUED
- /sys/devices/cpu/events/PM_SLB_MISS
- /sys/devices/cpu/events/PM_LSU1_FLUSH_LRQ
- /sys/devices/cpu/events/PM_DTLB_MISS
- /sys/devices/cpu/events/PM_VSU1_FRSP
- /sys/devices/cpu/events/PM_VSU_VECTOR_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_L2_CASTOUT_SHR
- /sys/devices/cpu/events/PM_DATA_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_VSU1_STF
- /sys/devices/cpu/events/PM_ST_FIN
- /sys/devices/cpu/events/PM_PTEG_FROM_L21_SHR
- /sys/devices/cpu/events/PM_L2_LOC_GUESS_WRONG
- /sys/devices/cpu/events/PM_MRK_STCX_FAIL
- /sys/devices/cpu/events/PM_LSU0_REJECT_LHS
- /sys/devices/cpu/events/PM_IC_PREF_CANCEL_HIT
- /sys/devices/cpu/events/PM_L3_PREF_BUSY
- /sys/devices/cpu/events/PM_MRK_BRU_FIN
- /sys/devices/cpu/events/PM_LSU1_NCLD
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_MOD
- /sys/devices/cpu/events/PM_LSU_NCLD
- /sys/devices/cpu/events/PM_LSU_LDX
- /sys/devices/cpu/events/PM_L2_LOC_GUESS_CORRECT
- /sys/devices/cpu/events/PM_THRESH_TIMEO
- /sys/devices/cpu/events/PM_L3_PREF_ST
- /sys/devices/cpu/events/PM_DISP_CLB_HELD_SYNC
- /sys/devices/cpu/events/PM_VSU_SIMPLE_ISSUED
- /sys/devices/cpu/events/PM_VSU1_SINGLE
- /sys/devices/cpu/events/PM_DATA_TABLEWALK_CYC
- /sys/devices/cpu/events/PM_L2_RC_ST_DONE
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_MOD
- /sys/devices/cpu/events/PM_LARX_LSU1
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM
- /sys/devices/cpu/events/PM_DISP_CLB_HELD
- /sys/devices/cpu/events/PM_DERAT_MISS_4K
- /sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_ADDR
- /sys/devices/cpu/events/PM_SEG_EXCEPTION
- /sys/devices/cpu/events/PM_FLUSH_DISP_SB
- /sys/devices/cpu/events/PM_L2_DC_INV
- /sys/devices/cpu/events/PM_PTEG_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_DSEG
- /sys/devices/cpu/events/PM_BR_PRED_LSTACK
- /sys/devices/cpu/events/PM_VSU0_STF
- /sys/devices/cpu/events/PM_LSU_FX_FIN
- /sys/devices/cpu/events/PM_DERAT_MISS_16M
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_GCT_UTIL_11_PLUS_SLOTS
- /sys/devices/cpu/events/PM_INST_FROM_L3
- /sys/devices/cpu/events/PM_MRK_IFU_FIN
- /sys/devices/cpu/events/PM_ITLB_MISS
- /sys/devices/cpu/events/PM_VSU_STF
- /sys/devices/cpu/events/PM_LSU_FLUSH_UST
- /sys/devices/cpu/events/PM_L2_LDST_MISS
- /sys/devices/cpu/events/PM_FXU1_FIN
- /sys/devices/cpu/events/PM_SHL_DEALLOCATED
- /sys/devices/cpu/events/PM_L2_SN_M_WR_DONE
- /sys/devices/cpu/events/PM_LSU_REJECT_SET_MPRED
- /sys/devices/cpu/events/PM_L3_PREF_LD
- /sys/devices/cpu/events/PM_L2_SN_M_RD_DONE
- /sys/devices/cpu/events/PM_MRK_DERAT_MISS_16G
- /sys/devices/cpu/events/PM_VSU_FCONV
- /sys/devices/cpu/events/PM_ANY_THRD_RUN_CYC
- /sys/devices/cpu/events/PM_LSU_LMQ_FULL_CYC
- /sys/devices/cpu/events/PM_MRK_LSU_REJECT_LHS
- /sys/devices/cpu/events/PM_MRK_LD_MISS_L1_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L2_CYC
- /sys/devices/cpu/events/PM_INST_IMC_MATCH_DISP
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RMEM_CYC
- /sys/devices/cpu/events/PM_VSU0_SIMPLE_ISSUED
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_VSU_FMA_DOUBLE
- /sys/devices/cpu/events/PM_VSU_4FLOP
- /sys/devices/cpu/events/PM_VSU1_FIN
- /sys/devices/cpu/events/PM_NEST_PAIR1_AND
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_RL2L3_MOD
- /sys/devices/cpu/events/PM_PTEG_FROM_RMEM
- /sys/devices/cpu/events/PM_LSU_LRQ_S0_VALID
- /sys/devices/cpu/events/PM_LSU0_LDF
- /sys/devices/cpu/events/PM_FLUSH_COMPLETION
- /sys/devices/cpu/events/PM_ST_MISS_L1
- /sys/devices/cpu/events/PM_L2_NODE_PUMP
- /sys/devices/cpu/events/PM_INST_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_MRK_STALL_CMPLU_CYC
- /sys/devices/cpu/events/PM_VSU1_DENORM
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_SHR_CYC
- /sys/devices/cpu/events/PM_NEST_PAIR0_ADD
- /sys/devices/cpu/events/PM_INST_FROM_L3MISS
- /sys/devices/cpu/events/PM_EE_OFF_EXT_INT
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_DMEM
- /sys/devices/cpu/events/PM_INST_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_PMC6_OVERFLOW
- /sys/devices/cpu/events/PM_VSU_2FLOP_DOUBLE
- /sys/devices/cpu/events/PM_TLB_MISS
- /sys/devices/cpu/events/PM_FXU_BUSY
- /sys/devices/cpu/events/PM_L2_RCLD_DISP_FAIL_OTHER
- /sys/devices/cpu/events/PM_LSU_REJECT_LMQ_FULL
- /sys/devices/cpu/events/PM_IC_RELOAD_SHR
- /sys/devices/cpu/events/PM_GRP_MRK
- /sys/devices/cpu/events/PM_MRK_ST_NEST
- /sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV
- /sys/devices/cpu/events/PM_LSU0_FLUSH_LRQ
- /sys/devices/cpu/events/PM_LARX_LSU0
- /sys/devices/cpu/events/PM_IBUF_FULL_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR_CYC
- /sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_ALLOC
- /sys/devices/cpu/events/PM_GRP_MRK_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR_CYC
- /sys/devices/cpu/events/PM_L2_GLOB_GUESS_CORRECT
- /sys/devices/cpu/events/PM_LSU_REJECT_LHS
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_LMEM
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L3
- /sys/devices/cpu/events/PM_FREQ_DOWN
- /sys/devices/cpu/events/PM_PB_RETRY_NODE_PUMP
- /sys/devices/cpu/events/PM_INST_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_MRK_INST_ISSUED
- /sys/devices/cpu/events/PM_PTEG_FROM_L3MISS
- /sys/devices/cpu/events/PM_RUN_PURR
- /sys/devices/cpu/events/PM_MRK_GRP_IC_MISS
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L3
- /sys/devices/cpu/events/PM_PTEG_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_LSU_FLUSH_LRQ
- /sys/devices/cpu/events/PM_MRK_DERAT_MISS_64K
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_MOD
- /sys/devices/cpu/events/PM_L2_ST_MISS
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L21_SHR
- /sys/devices/cpu/events/PM_LWSYNC
- /sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE
- /sys/devices/cpu/events/PM_MRK_LSU_FLUSH_LRQ
- /sys/devices/cpu/events/PM_INST_IMC_MATCH_CMPL
- /sys/devices/cpu/events/PM_NEST_PAIR3_AND
- /sys/devices/cpu/events/PM_PB_RETRY_SYS_PUMP
- /sys/devices/cpu/events/PM_MRK_INST_FIN
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_INST_FROM_L31_MOD
- /sys/devices/cpu/events/PM_MRK_DTLB_MISS_64K
- /sys/devices/cpu/events/PM_LSU_FIN
- /sys/devices/cpu/events/PM_MRK_LSU_REJECT
- /sys/devices/cpu/events/PM_L2_CO_FAIL_BUSY
- /sys/devices/cpu/events/PM_MEM0_WQ_DISP
- /sys/devices/cpu/events/PM_DATA_FROM_L31_MOD
- /sys/devices/cpu/events/PM_THERMAL_WARN
- /sys/devices/cpu/events/PM_VSU0_4FLOP
- /sys/devices/cpu/events/PM_BR_MPRED_CCACHE
- /sys/devices/cpu/events/PM_L1_DEMAND_WRITE
- /sys/devices/cpu/events/PM_FLUSH_BR_MPRED
- /sys/devices/cpu/events/PM_MRK_DTLB_MISS_16G
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_DMEM
- /sys/devices/cpu/events/PM_L2_RCST_DISP
- /sys/devices/cpu/events/PM_LSU_PARTIAL_CDF
- /sys/devices/cpu/events/PM_DISP_CLB_HELD_SB
- /sys/devices/cpu/events/PM_VSU0_FMA_DOUBLE
- /sys/devices/cpu/events/PM_FXU0_BUSY_FXU1_IDLE
- /sys/devices/cpu/events/PM_IC_DEMAND_CYC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_SHR
- /sys/devices/cpu/events/PM_MRK_LSU_FLUSH_UST
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L3MISS
- /sys/devices/cpu/events/PM_VSU_DENORM
- /sys/devices/cpu/events/PM_MRK_LSU_PARTIAL_CDF
- /sys/devices/cpu/events/PM_INST_FROM_L21_SHR
- /sys/devices/cpu/events/PM_IC_PREF_WRITE
- /sys/devices/cpu/events/PM_BR_PRED
- /sys/devices/cpu/events/PM_INST_FROM_DMEM
- /sys/devices/cpu/events/PM_IC_PREF_CANCEL_ALL
- /sys/devices/cpu/events/PM_LSU_DC_PREF_STREAM_CONFIRM
- /sys/devices/cpu/events/PM_MRK_LSU_FLUSH_SRQ
- /sys/devices/cpu/events/PM_MRK_FIN_STALL_CYC
- /sys/devices/cpu/events/PM_L2_RCST_DISP_FAIL_OTHER
- /sys/devices/cpu/events/PM_VSU1_DD_ISSUED
- /sys/devices/cpu/events/PM_PTEG_FROM_L31_SHR
- /sys/devices/cpu/events/PM_DATA_FROM_L21_SHR
- /sys/devices/cpu/events/PM_LSU0_NCLD
- /sys/devices/cpu/events/PM_VSU1_4FLOP
- /sys/devices/cpu/events/PM_VSU1_8FLOP
- /sys/devices/cpu/events/PM_VSU_8FLOP
- /sys/devices/cpu/events/PM_LSU_LMQ_SRQ_EMPTY_CYC
- /sys/devices/cpu/events/PM_DTLB_MISS_64K
- /sys/devices/cpu/events/PM_THRD_CONC_RUN_INST
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L2
- /sys/devices/cpu/events/PM_PB_SYS_PUMP
- /sys/devices/cpu/events/PM_VSU_FIN
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L31_MOD
- /sys/devices/cpu/events/PM_THRD_PRIO_0_1_CYC
- /sys/devices/cpu/events/PM_DERAT_MISS_64K
- /sys/devices/cpu/events/PM_PMC2_REWIND
- /sys/devices/cpu/events/PM_INST_FROM_L2
- /sys/devices/cpu/events/PM_GRP_BR_MPRED_NONSPEC
- /sys/devices/cpu/events/PM_INST_DISP
- /sys/devices/cpu/events/PM_MEM0_RD_CANCEL_TOTAL
- /sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_CONFIRM
- /sys/devices/cpu/events/PM_L1_DCACHE_RELOAD_VALID
- /sys/devices/cpu/events/PM_VSU_SCALAR_DOUBLE_ISSUED
- /sys/devices/cpu/events/PM_L3_PREF_HIT
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L31_MOD
- /sys/devices/cpu/events/PM_MRK_FXU_FIN
- /sys/devices/cpu/events/PM_PMC4_OVERFLOW
- /sys/devices/cpu/events/PM_MRK_PTEG_FROM_L3
- /sys/devices/cpu/events/PM_LSU0_LMQ_LHR_MERGE
- /sys/devices/cpu/events/PM_BTAC_HIT
- /sys/devices/cpu/events/PM_L3_RD_BUSY
- /sys/devices/cpu/events/PM_LSU0_L1_SW_PREF
- /sys/devices/cpu/events/PM_INST_FROM_L2MISS
- /sys/devices/cpu/events/PM_LSU0_DC_PREF_STREAM_ALLOC
- /sys/devices/cpu/events/PM_L2_ST
- /sys/devices/cpu/events/PM_VSU0_DENORM
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_BR_PRED_CR_TA
- /sys/devices/cpu/events/PM_VSU0_FCONV
- /sys/devices/cpu/events/PM_MRK_LSU_FLUSH_ULD
- /sys/devices/cpu/events/PM_BTAC_MISS
- /sys/devices/cpu/events/PM_MRK_LD_MISS_EXPOSED_CYC_COUNT
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L2
- /sys/devices/cpu/events/PM_LSU_DCACHE_RELOAD_VALID
- /sys/devices/cpu/events/PM_VSU_FMA
- /sys/devices/cpu/events/PM_LSU0_FLUSH_SRQ
- /sys/devices/cpu/events/PM_LSU1_L1_PREF
- /sys/devices/cpu/events/PM_IOPS_CMPL
- /sys/devices/cpu/events/PM_L2_SYS_PUMP
- /sys/devices/cpu/events/PM_L2_RCLD_BUSY_RC_FULL
- /sys/devices/cpu/events/PM_LSU_LMQ_S0_ALLOC
- /sys/devices/cpu/events/PM_FLUSH_DISP_SYNC
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_DL2L3_MOD_CYC
- /sys/devices/cpu/events/PM_L2_IC_INV
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L21_MOD_CYC
- /sys/devices/cpu/events/PM_L3_PREF_LDST
- /sys/devices/cpu/events/PM_LSU_SRQ_EMPTY_CYC
- /sys/devices/cpu/events/PM_LSU_LMQ_S0_VALID
- /sys/devices/cpu/events/PM_FLUSH_PARTIAL
- /sys/devices/cpu/events/PM_VSU1_FMA_DOUBLE
- /sys/devices/cpu/events/PM_1PLUS_PPC_DISP
- /sys/devices/cpu/events/PM_DATA_FROM_L2MISS
- /sys/devices/cpu/events/PM_SUSPENDED
- /sys/devices/cpu/events/PM_VSU0_FMA
- /sys/devices/cpu/events/PM_STCX_FAIL
- /sys/devices/cpu/events/PM_VSU0_FSQRT_FDIV_DOUBLE
- /sys/devices/cpu/events/PM_DC_PREF_DST
- /sys/devices/cpu/events/PM_VSU1_SCAL_SINGLE_ISSUED
- /sys/devices/cpu/events/PM_L3_HIT
- /sys/devices/cpu/events/PM_L2_GLOB_GUESS_WRONG
- /sys/devices/cpu/events/PM_MRK_DFU_FIN
- /sys/devices/cpu/events/PM_INST_FROM_L1
- /sys/devices/cpu/events/PM_IC_DEMAND_REQ
- /sys/devices/cpu/events/PM_VSU1_FSQRT_FDIV_DOUBLE
- /sys/devices/cpu/events/PM_VSU1_FMA
- /sys/devices/cpu/events/PM_MRK_LD_MISS_L1
- /sys/devices/cpu/events/PM_VSU0_2FLOP_DOUBLE
- /sys/devices/cpu/events/PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_L31_SHR
- /sys/devices/cpu/events/PM_MRK_LSU_REJECT_ERAT_MISS
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_L2MISS
- /sys/devices/cpu/events/PM_DATA_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_INST_FROM_PREF
- /sys/devices/cpu/events/PM_VSU1_SQ
- /sys/devices/cpu/events/PM_L2_LD_DISP
- /sys/devices/cpu/events/PM_L2_DISP_ALL
- /sys/devices/cpu/events/PM_THRD_GRP_CMPL_BOTH_CYC
- /sys/devices/cpu/events/PM_VSU_FSQRT_FDIV_DOUBLE
- /sys/devices/cpu/events/PM_INST_PTEG_FROM_DL2L3_SHR
- /sys/devices/cpu/events/PM_VSU_1FLOP
- /sys/devices/cpu/events/PM_HV_CYC
- /sys/devices/cpu/events/PM_MRK_LSU_FIN
- /sys/devices/cpu/events/PM_MRK_DATA_FROM_RL2L3_SHR
- /sys/devices/cpu/events/PM_DTLB_MISS_16M
- /sys/devices/cpu/events/PM_LSU1_LMQ_LHR_MERGE
- /sys/devices/cpu/events/PM_IFU_FIN
- /sys/devices/cpu/events/PM_1THRD_CON_RUN_INSTR
- /sys/devices/cpu/events/PM_CMPLU_STALL_COUNT
- /sys/devices/cpu/events/PM_MEM0_PB_RD_CL
- /sys/devices/cpu/events/PM_THRD_1_RUN_CYC
- /sys/devices/cpu/events/PM_THRD_2_CONC_RUN_INSTR
- /sys/devices/cpu/events/PM_THRD_2_RUN_CYC
- /sys/devices/cpu/events/PM_THRD_3_CONC_RUN_INST
- /sys/devices/cpu/events/PM_THRD_3_RUN_CYC
- /sys/devices/cpu/events/PM_THRD_4_CONC_RUN_INST
- /sys/devices/cpu/events/PM_THRD_4_RUN_CYC
-
-Date: 2013/01/08
-
-Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
- Linux Powerpc mailing list <linuxppc-dev@ozlabs.org>
-
-Description: POWER-systems specific performance monitoring events
-
- A collection of performance monitoring events that may be
- supported by the POWER CPU. These events can be monitored
- using the 'perf(1)' tool.
-
- These events may not be supported by other CPUs.
-
- The contents of each file would look like:
-
- event=0xNNNN
-
- where 'N' is a hex digit and the number '0xNNNN' shows the
- "raw code" for the perf event identified by the file's
- "basename".
-
- Further, multiple terms like 'event=0xNNNN' can be specified
- and separated with comma. All available terms are defined in
- the /sys/bus/event_source/devices/<dev>/format file.
-
What: /sys/bus/event_source/devices/<pmu>/events/<event>
Date: 2014/02/24
Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
--
1.7.9.5
^ permalink raw reply related
* [PATCH 2/4] Simplify catalog_read()
From: Sukadev Bhattiprolu @ 2014-09-17 18:33 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: linuxppc-dev, dev, linux-kernel, Michael Ellerman,
Anshuman Khandual
In-Reply-To: <1410978787-7375-1-git-send-email-sukadev@linux.vnet.ibm.com>
catalog_read() implements the read interface for the sysfs file
/sys/bus/event_source/devices/hv_24x7/interface/catalog
It essentially takes a buffer, an offset and count as parameters
to the read() call. It makes a hypervisor call to read a specific
page from the catalog and copy the required bytes into the given
buffer. Each call to catalog_read() returns at most one 4K page.
Given these requirements, we should be able to simplify the
catalog_read().
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/hv-24x7.c | 92 +++++--------------------------------------
1 file changed, 10 insertions(+), 82 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 2f2215c..9427ef7 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -75,86 +75,6 @@ static struct attribute_group format_group = {
static struct kmem_cache *hv_page_cache;
-/*
- * read_offset_data - copy data from one buffer to another while treating the
- * source buffer as a small view on the total avaliable
- * source data.
- *
- * @dest: buffer to copy into
- * @dest_len: length of @dest in bytes
- * @requested_offset: the offset within the source data we want. Must be > 0
- * @src: buffer to copy data from
- * @src_len: length of @src in bytes
- * @source_offset: the offset in the sorce data that (src,src_len) refers to.
- * Must be > 0
- *
- * returns the number of bytes copied.
- *
- * The following ascii art shows the various buffer possitioning we need to
- * handle, assigns some arbitrary varibles to points on the buffer, and then
- * shows how we fiddle with those values to get things we care about (copy
- * start in src and copy len)
- *
- * s = @src buffer
- * d = @dest buffer
- * '.' areas in d are written to.
- *
- * u
- * x w v z
- * d |.........|
- * s |----------------------|
- *
- * u
- * x w z v
- * d |........------|
- * s |------------------|
- *
- * x w u,z,v
- * d |........|
- * s |------------------|
- *
- * x,w u,v,z
- * d |..................|
- * s |------------------|
- *
- * x u
- * w v z
- * d |........|
- * s |------------------|
- *
- * x z w v
- * d |------|
- * s |------|
- *
- * x = source_offset
- * w = requested_offset
- * z = source_offset + src_len
- * v = requested_offset + dest_len
- *
- * w_offset_in_s = w - x = requested_offset - source_offset
- * z_offset_in_s = z - x = src_len
- * v_offset_in_s = v - x = request_offset + dest_len - src_len
- */
-static ssize_t read_offset_data(void *dest, size_t dest_len,
- loff_t requested_offset, void *src,
- size_t src_len, loff_t source_offset)
-{
- size_t w_offset_in_s = requested_offset - source_offset;
- size_t z_offset_in_s = src_len;
- size_t v_offset_in_s = requested_offset + dest_len - src_len;
- size_t u_offset_in_s = min(z_offset_in_s, v_offset_in_s);
- size_t copy_len = u_offset_in_s - w_offset_in_s;
-
- if (requested_offset < 0 || source_offset < 0)
- return -EINVAL;
-
- if (z_offset_in_s <= w_offset_in_s)
- return 0;
-
- memcpy(dest, src + w_offset_in_s, copy_len);
- return copy_len;
-}
-
static unsigned long h_get_24x7_catalog_page_(unsigned long phys_4096,
unsigned long version,
unsigned long index)
@@ -185,6 +105,8 @@ static ssize_t catalog_read(struct file *filp, struct kobject *kobj,
ssize_t ret = 0;
size_t catalog_len = 0, catalog_page_len = 0, page_count = 0;
loff_t page_offset = 0;
+ loff_t offset_in_page;
+ size_t copy_len;
uint64_t catalog_version_num = 0;
void *page = kmem_cache_alloc(hv_page_cache, GFP_USER);
struct hv_24x7_catalog_page_0 *page_0 = page;
@@ -203,6 +125,7 @@ static ssize_t catalog_read(struct file *filp, struct kobject *kobj,
page_offset = offset / 4096;
page_count = count / 4096;
+ offset_in_page = count % 4096;
if (page_offset >= catalog_page_len)
goto e_free;
@@ -216,8 +139,13 @@ static ssize_t catalog_read(struct file *filp, struct kobject *kobj,
}
}
- ret = read_offset_data(buf, count, offset,
- page, 4096, page_offset * 4096);
+ copy_len = 4096 - offset_in_page;
+ if (copy_len > count)
+ copy_len = count;
+
+ memcpy(buf, page+offset_in_page, copy_len);
+ ret = copy_len;
+
e_free:
if (hret)
pr_err("h_get_24x7_catalog_page(ver=%lld, page=%lld) failed:"
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/4] powerpc/perf/hv-24x7: use kmem_cache instead of aligned stack allocations
From: Sukadev Bhattiprolu @ 2014-09-17 18:33 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: linuxppc-dev, dev, linux-kernel, Michael Ellerman,
Anshuman Khandual
In-Reply-To: <1410978787-7375-1-git-send-email-sukadev@linux.vnet.ibm.com>
From: Cody P Schafer <cody@linux.vnet.ibm.com>
Ian pointed out the use of __aligned(4096) caused rather large stack
consumption in single_24x7_request(), so use the kmem_cache
hv_page_cache (which we've already got set up for other allocations)
insead of allocating locally.
CC: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
CC: Haren Myneni <hbabu@us.ibm.com>
CC: Cody P Schafer <dev@codyps.com>
Reported-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Cody P Schafer <cody@linux.vnet.ibm.com>
---
arch/powerpc/perf/hv-24x7.c | 52 ++++++++++++++++++++++++++++++-------------
1 file changed, 37 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 70d4f74..2f2215c 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -294,7 +294,7 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
u16 lpar, u64 *res,
bool success_expected)
{
- unsigned long ret;
+ unsigned long ret = -ENOMEM;
/*
* request_buffer and result_buffer are not required to be 4k aligned,
@@ -304,7 +304,27 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
struct reqb {
struct hv_24x7_request_buffer buf;
struct hv_24x7_request req;
- } __packed __aligned(4096) request_buffer = {
+ } __packed * request_buffer;
+ struct resb {
+ struct hv_24x7_data_result_buffer buf;
+ struct hv_24x7_result res;
+ struct hv_24x7_result_element elem;
+ __be64 result;
+ } __packed * result_buffer;
+
+ BUILD_BUG_ON(sizeof(*request_buffer) > 4096);
+ BUILD_BUG_ON(sizeof(*result_buffer) > 4096);
+
+ request_buffer = kmem_cache_alloc(hv_page_cache, GFP_USER);
+
+ if (!request_buffer)
+ goto out_reqb;
+
+ result_buffer = kmem_cache_zalloc(hv_page_cache, GFP_USER);
+ if (!result_buffer)
+ goto out_resb;
+
+ *request_buffer = (struct reqb) {
.buf = {
.interface_version = HV_24X7_IF_VERSION_CURRENT,
.num_requests = 1,
@@ -320,28 +340,30 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
}
};
- struct resb {
- struct hv_24x7_data_result_buffer buf;
- struct hv_24x7_result res;
- struct hv_24x7_result_element elem;
- __be64 result;
- } __packed __aligned(4096) result_buffer = {};
-
ret = plpar_hcall_norets(H_GET_24X7_DATA,
- virt_to_phys(&request_buffer), sizeof(request_buffer),
- virt_to_phys(&result_buffer), sizeof(result_buffer));
+ virt_to_phys(request_buffer), sizeof(*request_buffer),
+ virt_to_phys(result_buffer), sizeof(*result_buffer));
if (ret) {
if (success_expected)
pr_err_ratelimited("hcall failed: %d %#x %#x %d => 0x%lx (%ld) detail=0x%x failing ix=%x\n",
domain, offset, ix, lpar,
ret, ret,
- result_buffer.buf.detailed_rc,
- result_buffer.buf.failing_request_ix);
- return ret;
+ result_buffer->buf.detailed_rc,
+ result_buffer->buf.failing_request_ix);
+ goto out_hcall;
}
- *res = be64_to_cpu(result_buffer.result);
+ *res = be64_to_cpu(result_buffer->result);
+ kfree(result_buffer);
+ kfree(request_buffer);
+ return ret;
+
+out_hcall:
+ kfree(result_buffer);
+out_resb:
+ kfree(request_buffer);
+out_reqb:
return ret;
}
--
1.7.9.5
^ permalink raw reply related
* [PATCH 0/4] powerpc/perf: Miscellaneous fixes
From: Sukadev Bhattiprolu @ 2014-09-17 18:33 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, ak, Jiri Olsa, peterz, eranian,
Paul Mackerras
Cc: linuxppc-dev, dev, linux-kernel, Michael Ellerman,
Anshuman Khandual
Miscellaenous fixes for perf and 24x7 counters in powerpc.
Patches 1,3,4 were submitted earlier as a part of the parametrized
events for 24x7 counters. But they are not directly related to the
parametrized events.
Patch 2 simplifies and fixes a bug in catalog_read() which causes the
catalog file to not read first page.
Cody P Schafer (3):
powerpc/perf/hv-24x7: use kmem_cache instead of aligned stack
allocations
perf Documentation: sysfs events/ interfaces
perf Documentation: remove duplicated docs for powerpc cpu specific
events
Sukadev Bhattiprolu (1):
Simplify catalog_read()
.../testing/sysfs-bus-event_source-devices-events | 611 ++------------------
arch/powerpc/perf/hv-24x7.c | 144 ++---
2 files changed, 96 insertions(+), 659 deletions(-)
--
1.7.9.5
^ permalink raw reply
* Re: [PATCH V4] ASoC: fsl_ssi: refine ipg clock usage in this module
From: Mark Brown @ 2014-09-17 18:30 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, lgirdwood, tiwai, linux-kernel, timur, perex,
nicoleotsuka, Li.Xiubo, mpa, linuxppc-dev
In-Reply-To: <5dc0f13cdb62904ae0f104f9112faec672adea6f.1410833402.git.shengjiu.wang@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 390 bytes --]
On Tue, Sep 16, 2014 at 10:13:16AM +0800, Shengjiu Wang wrote:
> Check if ipg clock is in clock-names property, then we can move the
> ipg clock enable and disable operation to startup and shutdown, that
> is only enable ipg clock when ssi is working and keep clock is disabled
> when ssi is in idle.
> But when the checking is failed, remain the clock control as before.
Applied, thanks.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply
* Re: [PATCH V4] ASoC: fsl_ssi: refine ipg clock usage in this module
From: Nicolin Chen @ 2014-09-17 17:42 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, lgirdwood, tiwai, Li.Xiubo, timur, perex, broonie,
mpa, linuxppc-dev, linux-kernel
In-Reply-To: <5dc0f13cdb62904ae0f104f9112faec672adea6f.1410833402.git.shengjiu.wang@freescale.com>
On Tue, Sep 16, 2014 at 10:13:16AM +0800, Shengjiu Wang wrote:
> Check if ipg clock is in clock-names property, then we can move the
> ipg clock enable and disable operation to startup and shutdown, that
> is only enable ipg clock when ssi is working and keep clock is disabled
> when ssi is in idle.
> But when the checking is failed, remain the clock control as before.
>
> Tested-by: Markus Pargmann <mpa@pengutronix.de>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> v4 change log:
> fix the code indent issue.
>
> sound/soc/fsl/fsl_ssi.c | 53 ++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 45 insertions(+), 8 deletions(-)
>
> diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
> index 2fc3e66..16a1361 100644
> --- a/sound/soc/fsl/fsl_ssi.c
> +++ b/sound/soc/fsl/fsl_ssi.c
> @@ -169,6 +169,7 @@ struct fsl_ssi_private {
> u8 i2s_mode;
> bool use_dma;
> bool use_dual_fifo;
> + bool has_ipg_clk_name;
> unsigned int fifo_depth;
> struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
>
> @@ -530,6 +531,11 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
> struct snd_soc_pcm_runtime *rtd = substream->private_data;
> struct fsl_ssi_private *ssi_private =
> snd_soc_dai_get_drvdata(rtd->cpu_dai);
> + int ret;
> +
> + ret = clk_prepare_enable(ssi_private->clk);
> + if (ret)
> + return ret;
>
> /* When using dual fifo mode, it is safer to ensure an even period
> * size. If appearing to an odd number while DMA always starts its
> @@ -544,6 +550,21 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream,
> }
>
> /**
> + * fsl_ssi_shutdown: shutdown the SSI
> + *
> + */
> +static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_pcm_runtime *rtd = substream->private_data;
> + struct fsl_ssi_private *ssi_private =
> + snd_soc_dai_get_drvdata(rtd->cpu_dai);
> +
> + clk_disable_unprepare(ssi_private->clk);
> +
> +}
> +
> +/**
> * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
> *
> * Note: This function can be only called when using SSI as DAI master
> @@ -1043,6 +1064,7 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
>
> static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
> .startup = fsl_ssi_startup,
> + .shutdown = fsl_ssi_shutdown,
> .hw_params = fsl_ssi_hw_params,
> .hw_free = fsl_ssi_hw_free,
> .set_fmt = fsl_ssi_set_dai_fmt,
> @@ -1168,17 +1190,22 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
> u32 dmas[4];
> int ret;
>
> - ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
> + if (ssi_private->has_ipg_clk_name)
> + ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
> + else
> + ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
> if (IS_ERR(ssi_private->clk)) {
> ret = PTR_ERR(ssi_private->clk);
> dev_err(&pdev->dev, "could not get clock: %d\n", ret);
> return ret;
> }
>
> - ret = clk_prepare_enable(ssi_private->clk);
> - if (ret) {
> - dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
> - return ret;
> + if (!ssi_private->has_ipg_clk_name) {
> + ret = clk_prepare_enable(ssi_private->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
> + return ret;
> + }
> }
>
> /* For those SLAVE implementations, we ingore non-baudclk cases
> @@ -1236,8 +1263,9 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev,
> return 0;
>
> error_pcm:
> - clk_disable_unprepare(ssi_private->clk);
>
> + if (!ssi_private->has_ipg_clk_name)
> + clk_disable_unprepare(ssi_private->clk);
> return ret;
> }
>
> @@ -1246,7 +1274,8 @@ static void fsl_ssi_imx_clean(struct platform_device *pdev,
> {
> if (!ssi_private->use_dma)
> imx_pcm_fiq_exit(pdev);
> - clk_disable_unprepare(ssi_private->clk);
> + if (!ssi_private->has_ipg_clk_name)
> + clk_disable_unprepare(ssi_private->clk);
> }
>
> static int fsl_ssi_probe(struct platform_device *pdev)
> @@ -1321,8 +1350,16 @@ static int fsl_ssi_probe(struct platform_device *pdev)
> return -ENOMEM;
> }
>
> - ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
> + ret = of_property_match_string(np, "clock-names", "ipg");
> + if (ret < 0) {
> + ssi_private->has_ipg_clk_name = false;
> + ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
> &fsl_ssi_regconfig);
> + } else {
> + ssi_private->has_ipg_clk_name = true;
> + ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
> + "ipg", iomem, &fsl_ssi_regconfig);
> + }
> if (IS_ERR(ssi_private->regs)) {
> dev_err(&pdev->dev, "Failed to init register map\n");
> return PTR_ERR(ssi_private->regs);
> --
> 1.7.9.5
>
^ permalink raw reply
* Re: [PATCH v4 04/11] drivers: base: support cpu cache information interface to userspace via sysfs
From: Sudeep Holla @ 2014-09-17 17:25 UTC (permalink / raw)
To: LKML
Cc: linux-s390@vger.kernel.org, Lorenzo Pieralisi,
linux-ia64@vger.kernel.org, Greg Kroah-Hartman, Sudeep Holla,
Heiko Carstens, x86@kernel.org, linux-api@vger.kernel.org,
linux390@de.ibm.com, linuxppc-dev@lists.ozlabs.org, Stephen Boyd,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1409763617-17074-5-git-send-email-sudeep.holla@arm.com>
Hi Greg,
On 03/09/14 18:00, Sudeep Holla wrote:
> From: Sudeep Holla <sudeep.holla@arm.com>
>
> This patch adds initial support for providing processor cache information
> to userspace through sysfs interface. This is based on already existing
> implementations(x86, ia64, s390 and powerpc) and hence the interface is
> intended to be fully compatible.
>
> The main purpose of this generic support is to avoid further code
> duplication to support new architectures and also to unify all the existi=
ng
> different implementations.
>
> This implementation maintains the hierarchy of cache objects which reflec=
ts
> the system's cache topology. Cache devices are instantiated as needed as
> CPUs come online. The cache information is replicated per-cpu even if the=
y are
> shared. A per-cpu array of cache information maintained is used mainly fo=
r
> sysfs-related book keeping.
>
> It also implements the shared_cpu_map attribute, which is essential for
> enabling both kernel and user-space to discover the system's overall cach=
e
> topology.
>
> This patch also add the missing ABI documentation for the cacheinfo sysfs
> interface already, which is well defined and widely used.
>
Can you review the first 4 patches in this series please ?
Regards,
Sudeep
^ permalink raw reply
* Re: [2/5] pseries: Export drc_[acquire|release]_drc() routines
From: Nathan Fontenot @ 2014-09-17 16:50 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
In-Reply-To: <1410937625.27681.10.camel@concordia>
On 09/17/2014 02:07 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:30 -0500, Nathan Fontenot wrote:
>> diff --git a/arch/powerpc/platforms/pseries/pseries.h b/arch/powerpc/platforms/pseries/pseries.h
>> index 361add6..b94516b 100644
>> --- a/arch/powerpc/platforms/pseries/pseries.h
>> +++ b/arch/powerpc/platforms/pseries/pseries.h
>> @@ -59,6 +59,8 @@ extern void dlpar_free_cc_property(struct property *);
>> extern struct device_node *dlpar_configure_connector(u32, struct device_node *);
>> extern int dlpar_attach_node(struct device_node *);
>> extern int dlpar_detach_node(struct device_node *);
>> +extern int dlpar_acquire_drc(u32);
>> +extern int dlpar_release_drc(u32);
>
> Please name the parameters.
Will do.
>
> And don't bother with extern.
I was following the convention used in the file, droppping the
extern is fine with me though.
-Nathan
^ permalink raw reply
* Re: [1/5] pseries: Define rtas hotplug event sections
From: Nathan Fontenot @ 2014-09-17 16:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1410937582.27681.9.camel@concordia>
On 09/17/2014 02:06 AM, Michael Ellerman wrote:
>
> On Mon, 2014-09-15 at 15:29 -0500, Nathan Fontenot wrote:
>> diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
>> index b390f55..a01879e 100644
>> --- a/arch/powerpc/include/asm/rtas.h
>> +++ b/arch/powerpc/include/asm/rtas.h
>> @@ -273,6 +273,7 @@ inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log)
>> #define PSERIES_ELOG_SECT_ID_MANUFACT_INFO (('M' << 8) | 'I')
>> #define PSERIES_ELOG_SECT_ID_CALL_HOME (('C' << 8) | 'H')
>> #define PSERIES_ELOG_SECT_ID_USER_DEF (('U' << 8) | 'D')
>> +#define PSERIES_ELOG_SECT_ID_HOTPLUG (('H' << 8) | 'P')
>>
>> /* Vendor specific Platform Event Log Format, Version 6, section header */
>> struct pseries_errorlog {
>> @@ -296,6 +297,31 @@ inline uint16_t pseries_errorlog_length(struct pseries_errorlog *sect)
>> return be16_to_cpu(sect->length);
>> }
>>
>> +/* RTAS pseries hotplug errorlog section */
>> +struct pseries_hp_errorlog {
>> + uint8_t resource;
>> + uint8_t action;
>> + uint8_t id_type;
>> + uint8_t reserved;
>
> These should be u8.
ok.
>
>> + union {
>> + __be32 drc_index;
>> + __be32 drc_count;
>> + char drc_name[1];
>
> I don't see drc_name used?
I don't use drc_name in this patch set but the drc_name piece is
part of the rtas hotplug section definition and I wanted to provide
a complete definition of the section.
-Nathan
>
>> + } _drc_u;
>> +};
>
> cheers
>
>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>
^ permalink raw reply
* Re: [PATCH v3 00/21] powerpc/8xx: Optimise MMU TLB handling and add support of 16k pages
From: Scott Wood @ 2014-09-17 16:40 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <20140917163656.E09D81AB026@localhost.localdomain>
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
> This patchset:
> 1) provides several MMU TLB handling optimisation on MPC8xx.
> 2) adds support of 16k pages on MPC8xx.
> All changes have been successfully tested on a custom board equipped with MPC885
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr>
I've already applied patches 1, 2, 4, 5, 6, 9, and 10 from the previous
patchset -- have they changed?
-Scott
^ permalink raw reply
* [PATCH v3 20/21] powerpc/8xx: Use DAR to save r3 for CPU6 ERRATA
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v3:
- New
linux/arch/powerpc/kernel/head_8xx.S | 33 +++++++++++++++------------------
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/linux/arch/powerpc/kernel/head_8xx.S b/linux/arch/powerpc/kernel/head_8xx.S
index e21f0b2..3e8e341 100644
--- a/linux/arch/powerpc/kernel/head_8xx.S
+++ b/linux/arch/powerpc/kernel/head_8xx.S
@@ -83,13 +83,6 @@ _ENTRY(_start);
* 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
* the "internal" processor registers before MMU_init is called.
*
- * The TLB code currently contains a major hack. Since I use the condition
- * code register, I have to save and restore it. I am out of registers, so
- * I just store it in memory location 0 (the TLB handlers are not reentrant).
- * To avoid making any decisions, I need to use the "segment" valid bit
- * in the first level table, but that would require many changes to the
- * Linux page directory/table functions that I don't want to do right now.
- *
* -- Dan
*/
.globl __start
@@ -304,7 +297,7 @@ SystemCall:
*/
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
- stw r3, 8(r0)
+ mtspr SPRN_DAR, r3
#endif
EXCEPTION_PROLOG_0
mtspr SPRN_SPRG_SCRATCH2, r10
@@ -349,7 +342,10 @@ InstructionTLBMiss:
#ifdef CONFIG_SWAP
andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
+ li r11, RPN_PATTERN
bne- cr0, 2f
+#else
+ li r11, RPN_PATTERN
#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21 and 28 must be clear.
@@ -357,28 +353,29 @@ InstructionTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- li r11, RPN_PATTERN
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
+ mfspr r3, SPRN_DAR
+ mtspr SPRN_DAR, r11 /* Tag DAR */
#endif
mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi
2:
- mfspr r11, SPRN_SRR1
+ mfspr r10, SPRN_SRR1
/* clear all error bits as TLB Miss
* sets a few unconditionally
*/
- rlwinm r11, r11, 0, 0xffff
- mtspr SPRN_SRR1, r11
+ rlwinm r10, r10, 0, 0xffff
+ mtspr SPRN_SRR1, r10
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
+ mfspr r3, SPRN_DAR
+ mtspr SPRN_DAR, r11 /* Tag DAR */
#endif
mfspr r10, SPRN_SPRG_SCRATCH2
b InstructionTLBError1
@@ -386,7 +383,7 @@ InstructionTLBMiss:
. = 0x1200
DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
- stw r3, 8(r0)
+ mtspr SPRN_DAR, r3
#endif
EXCEPTION_PROLOG_0
mtspr SPRN_SPRG_SCRATCH2, r10
@@ -457,7 +454,7 @@ DataStoreTLBMiss:
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
+ mfspr r3, SPRN_DAR
#endif
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r10, SPRN_SPRG_SCRATCH2
@@ -527,7 +524,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
#define NO_SELF_MODIFYING_CODE
FixupDAR:/* Entry point for dcbx workaround. */
#ifdef CONFIG_8xx_CPU6
- stw r3, 8(r0)
+ mtspr SPRN_DAR, r3
#endif
mtspr SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */
@@ -546,7 +543,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwzx r11, r10, r11 /* Get the pte */
#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0) /* restore r3 from memory */
+ mfspr r3, SPRN_DAR
#endif
/* concat physical page address(r11) and page offset(r10) */
mfspr r10, SPRN_SRR0
--
2.1.0
^ permalink raw reply related
* [PATCH v3 16/21] powerpc/8xx: Better readibility of ERRATA CPU6 handling
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 29 ++++++++++++++++-------------
1 files changed, 16 insertions(+), 13 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 4dd6be0..a7af26e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -33,12 +33,19 @@
/* Macro to make the code more readable. */
#ifdef CONFIG_8xx_CPU6
-#define DO_8xx_CPU6(val, reg) \
- li reg, val; \
- stw reg, 12(r0); \
- lwz reg, 12(r0);
+#define SPRN_MI_TWC_ADDR 0x2b80
+#define SPRN_MI_RPN_ADDR 0x2d80
+#define SPRN_MD_TWC_ADDR 0x3b80
+#define SPRN_MD_RPN_ADDR 0x3d80
+
+#define MTSPR_CPU6(spr, reg, treg) \
+ li treg, spr##_ADDR; \
+ stw treg, 12(r0); \
+ lwz treg, 12(r0); \
+ mtspr spr, reg
#else
-#define DO_8xx_CPU6(val, reg)
+#define MTSPR_CPU6(spr, reg, treg) \
+ mtspr spr, reg
#endif
/*
@@ -334,8 +341,7 @@ InstructionTLBMiss:
* for this "segment."
*/
ori r11,r11,1 /* Set valid bit */
- DO_8xx_CPU6(0x2b80, r3)
- mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
+ MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
/* Extract level 2 index */
rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
@@ -354,8 +360,7 @@ InstructionTLBMiss:
*/
li r11, RPN_PATTERN
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
- DO_8xx_CPU6(0x2d80, r3)
- mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
+ MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
@@ -424,8 +429,7 @@ DataStoreTLBMiss:
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
rlwimi r11, r10, 32-5, 30, 30
- DO_8xx_CPU6(0x3b80, r3)
- mtspr SPRN_MD_TWC, r11
+ MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
* We also need to know if the insn is a load/store, so:
@@ -458,8 +462,7 @@ DataStoreTLBMiss:
*/
2: li r11, RPN_PATTERN
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
- DO_8xx_CPU6(0x3d80, r3)
- mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
+ MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
--
1.7.1
^ permalink raw reply related
* [PATCH v3 21/21] powerpc/8xx: Invalidate non present TLB as early as possible
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm doesn't.
Commit 5efab4a02c89c252fb4cce097aafde5f8208dbfe was invalidating them in
arch/powerpc/mm/fault.c.
This patch does the invalidation earlier in order to free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v3:
- New
linux/arch/powerpc/kernel/head_8xx.S | 15 ++++++++++-----
linux/arch/powerpc/mm/fault.c | 7 -------
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/linux/arch/powerpc/kernel/head_8xx.S b/linux/arch/powerpc/kernel/head_8xx.S
index 3e8e341..3b96862 100644
--- a/linux/arch/powerpc/kernel/head_8xx.S
+++ b/linux/arch/powerpc/kernel/head_8xx.S
@@ -473,7 +473,10 @@ InstructionTLBError1:
EXCEPTION_PROLOG_2
mr r4,r12
mr r5,r9
- EXC_XFER_LITE(0x1300, handle_page_fault)
+ andis. r10,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: EXC_XFER_LITE(0x1300, handle_page_fault)
/* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We bail out to
@@ -489,11 +492,13 @@ DataTLBError:
DARFixed:/* Return from dcbx instruction bug workaround */
EXCEPTION_PROLOG_1
EXCEPTION_PROLOG_2
- mfspr r10,SPRN_DSISR
- stw r10,_DSISR(r11)
- mr r5,r10
+ mfspr r5,SPRN_DSISR
+ stw r5,_DSISR(r11)
mfspr r4,SPRN_DAR
- li r10,RPN_PATTERN
+ andis. r10,r5,0x4000
+ beq+ 1f
+ tlbie r4
+1: li r10,RPN_PATTERN
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
EXC_XFER_LITE(0x1400, handle_page_fault)
diff --git a/linux/arch/powerpc/mm/fault.c b/linux/arch/powerpc/mm/fault.c
index adc084b..6f4f731 100644
--- a/linux/arch/powerpc/mm/fault.c
+++ b/linux/arch/powerpc/mm/fault.c
@@ -43,7 +43,6 @@
#include <asm/tlbflush.h>
#include <asm/siginfo.h>
#include <asm/debug.h>
-#include <mm/mmu_decl.h>
#include "icswx.h"
@@ -368,12 +367,6 @@ good_area:
goto bad_area;
#endif /* CONFIG_6xx */
#if defined(CONFIG_8xx)
- /* 8xx sometimes need to load a invalid/non-present TLBs.
- * These must be invalidated separately as linux mm don't.
- */
- if (error_code & 0x40000000) /* no translation? */
- _tlbil_va(address, 0, 0, 0);
-
/* The MPC8xx seems to always set 0x80000000, which is
* "undefined". Of those that can be set, this is the only
* one which seems bad.
--
2.1.0
^ permalink raw reply related
* [PATCH v3 18/21] powerpc/8xx: _PMD_PRESENT already set in level 1 entries
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 48d3de8..bb7c816 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -340,7 +340,6 @@ InstructionTLBMiss:
/* We have a pte table, so load the MI_TWC with the attributes
* for this "segment."
*/
- ori r11,r11,1 /* Set valid bit */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
/* Extract level 2 index */
@@ -417,7 +416,6 @@ DataStoreTLBMiss:
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
lwz r10, 0(r10) /* Get the pte */
- ori r11, r11, 1 /* Set valid bit in physical L2 page */
/* Insert the Guarded flag into the TWC from the Linux PTE.
* It is bit 27 of both the Linux PTE and the TWC (at least
* I got that right :-). It will be better when we can put
--
1.7.1
^ permalink raw reply related
* [PATCH v3 19/21] powerpc/8xx: Don't restore regs to save them again.
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 8 +++++---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index bb7c816..e21f0b2 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -381,8 +381,7 @@ InstructionTLBMiss:
lwz r3, 8(r0)
#endif
mfspr r10, SPRN_SPRG_SCRATCH2
- EXCEPTION_EPILOG_0
- b InstructionTLBError
+ b InstructionTLBError1
. = 0x1200
DataStoreTLBMiss:
@@ -471,7 +470,10 @@ DataStoreTLBMiss:
*/
. = 0x1300
InstructionTLBError:
- EXCEPTION_PROLOG
+ EXCEPTION_PROLOG_0
+InstructionTLBError1:
+ EXCEPTION_PROLOG_1
+ EXCEPTION_PROLOG_2
mr r4,r12
mr r5,r9
EXC_XFER_LITE(0x1300, handle_page_fault)
--
1.7.1
^ permalink raw reply related
* [PATCH v3 17/21] powerpc/8xx: set PTE bit 22 off TLBmiss
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
arch/powerpc/include/asm/pgtable-ppc32.h | 20 ++++++++++++++++++++
arch/powerpc/include/asm/pte-8xx.h | 7 +++++--
arch/powerpc/kernel/head_8xx.S | 10 ++--------
3 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 47edde8..35a9b44 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -172,6 +172,25 @@ static inline unsigned long pte_update(pte_t *p,
#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp;
+#ifdef CONFIG_PPC_8xx
+ unsigned long tmp2;
+
+ __asm__ __volatile__("\
+1: lwarx %0,0,%4\n\
+ andc %1,%0,%5\n\
+ or %1,%1,%6\n\
+ /* 0x200 == Extended encoding, bit 22 */ \
+ /* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
+ rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
+ rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
+ or %1,%3,%1\n\
+ xori %1,%1,0x200\n"
+" stwcx. %1,0,%4\n\
+ bne- 1b"
+ : "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
+ : "r" (p), "r" (clr), "r" (set), "m" (*p)
+ : "cc" );
+#else /* CONFIG_PPC_8xx */
__asm__ __volatile__("\
1: lwarx %0,0,%3\n\
andc %1,%0,%4\n\
@@ -182,6 +201,7 @@ static inline unsigned long pte_update(pte_t *p,
: "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" );
+#endif /* CONFIG_PPC_8xx */
#else /* PTE_ATOMIC_UPDATES */
unsigned long old = pte_val(*p);
*p = __pte((old & ~clr) | set);
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index d44826e..daa4616 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -48,19 +48,22 @@
*/
#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
#define _PAGE_USER 0x0800 /* msb PP bits */
+/* set when neither _PAGE_USER nor _PAGE_RW are set */
+#define _PAGE_KNLRO 0x0200
#define _PMD_PRESENT 0x0001
#define _PMD_BAD 0x0ff0
#define _PMD_PAGE_MASK 0x000c
#define _PMD_PAGE_8M 0x000c
-#define _PTE_NONE_MASK _PAGE_ACCESSED
+#define _PTE_NONE_MASK _PAGE_KNLRO
/* Until my rework is finished, 8xx still needs atomic PTE updates */
#define PTE_ATOMIC_UPDATES 1
/* We need to add _PAGE_SHARED to kernel pages */
-#define _PAGE_KERNEL_RO (_PAGE_SHARED)
+#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_KNLRO)
+#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_KNLRO)
#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a7af26e..48d3de8 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -445,14 +445,8 @@ DataStoreTLBMiss:
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
#endif
- /* Honour kernel RO, User NA */
- /* 0x200 == Extended encoding, bit 22 */
- rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */
- /* r11 = (r10 & _PAGE_RW) >> 1 */
- rlwinm r11, r10, 32-1, 0x200
- or r10, r11, r10
- /* invert RW and 0x200 bits */
- xori r10, r10, _PAGE_RW | 0x200
+ /* invert RW */
+ xori r10, r10, _PAGE_RW
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
--
2.1.0
^ permalink raw reply related
* [PATCH v3 15/21] powerpc/8xx: Implement 16k pages
From: Christophe Leroy @ 2014-09-17 16:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/mmu-8xx.h | 2 ++
arch/powerpc/kernel/head_8xx.S | 4 ++++
3 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 5f44d3b..dc5f64e 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -518,7 +518,7 @@ config PPC_4K_PAGES
bool "4k page size"
config PPC_16K_PAGES
- bool "16k page size" if 44x
+ bool "16k page size" if 44x || PPC_8xx
config PPC_64K_PAGES
bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/mmu-8xx.h
index 3d11d3c..986b9e1 100644
--- a/arch/powerpc/include/asm/mmu-8xx.h
+++ b/arch/powerpc/include/asm/mmu-8xx.h
@@ -56,6 +56,7 @@
* additional information from the MI_EPN, and MI_TWC registers.
*/
#define SPRN_MI_RPN 790
+#define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
/* Define an RPN value for mapping kernel memory to large virtual
* pages for boot initialization. This has real page number of 0,
@@ -129,6 +130,7 @@
* additional information from the MD_EPN, and MD_TWC registers.
*/
#define SPRN_MD_RPN 798
+#define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
/* This is a temporary storage register that could be used to save
* a processor working register during a tablewalk.
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 8966262..4dd6be0 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -45,7 +45,11 @@
* Value for the bits that have fixed value in RPN entries.
* Also used for tagging DAR for DTLBerror.
*/
+#ifdef CONFIG_PPC_16K_PAGES
+#define RPN_PATTERN (0x00f0 | MD_SPS16K)
+#else
#define RPN_PATTERN 0x00f0
+#endif
__HEAD
_ENTRY(_stext);
--
1.7.1
^ permalink raw reply related
* [PATCH v3 06/21] powerpc/8xx: No need to save r10 and r3 when not calling FixupDAR
From: Christophe Leroy @ 2014-09-17 16:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 27 +++++++++++++--------------
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 171c6ef..845abf8 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -482,20 +482,12 @@ InstructionTLBError:
*/
. = 0x1400
DataTLBError:
-#ifdef CONFIG_8xx_CPU6
- stw r3, 8(r0)
-#endif
EXCEPTION_PROLOG_0
- mtspr SPRN_SPRG_SCRATCH2, r10
- mfspr r10, SPRN_DAR
- cmpwi cr0, r10, 0x00f0
+ mfspr r11, SPRN_DAR
+ cmpwi cr0, r11, 0x00f0
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround */
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0)
-#endif
- mfspr r10,SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
b DataAccess
@@ -525,6 +517,10 @@ DARFixed:/* Return from dcbx instruction bug workaround */
/* define if you don't want to use self modifying code */
#define NO_SELF_MODIFYING_CODE
FixupDAR:/* Entry point for dcbx workaround. */
+#ifdef CONFIG_8xx_CPU6
+ stw r3, 8(r0)
+#endif
+ mtspr SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */
mfspr r10, SPRN_SRR0
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
@@ -540,6 +536,9 @@ FixupDAR:/* Entry point for dcbx workaround. */
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r11, 0(r11) /* Get the pte */
+#ifdef CONFIG_8xx_CPU6
+ lwz r3, 8(r0) /* restore r3 from memory */
+#endif
/* concat physical page address(r11) and page offset(r10) */
rlwimi r11, r10, 0, 20, 31
lwz r11,0(r11)
@@ -560,15 +559,13 @@ FixupDAR:/* Entry point for dcbx workaround. */
beq+ 142f
cmpwi cr0, r10, 1964 /* Is icbi? */
beq+ 142f
-141: b DARFixed /* Nope, go back to normal TLB processing */
+141: mfspr r10,SPRN_SPRG_SCRATCH2
+ b DARFixed /* Nope, go back to normal TLB processing */
144: mfspr r10, SPRN_DSISR
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
mtspr SPRN_DSISR, r10
142: /* continue, it was a dcbx, dcbi instruction. */
-#ifdef CONFIG_8xx_CPU6
- lwz r3, 8(r0) /* restore r3 from memory */
-#endif
#ifndef NO_SELF_MODIFYING_CODE
andis. r10,r11,0x1f /* test if reg RA is r0 */
li r10,modified_instr@l
@@ -587,6 +584,7 @@ modified_instr:
bne+ 143f
subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
143: mtdar r10 /* store faulting EA in DAR */
+ mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Go back to normal TLB handling */
#else
mfctr r10
@@ -640,6 +638,7 @@ modified_instr:
mfdar r11
mtctr r11 /* restore ctr reg from DAR */
mtdar r10 /* save fault EA to DAR */
+ mfspr r10,SPRN_SPRG_SCRATCH2
b DARFixed /* Go back to normal TLB handling */
/* special handling for r10,r11 since these are modified already */
--
1.7.1
^ permalink raw reply related
* [PATCH v3 11/21] powerpc/8xx: Use M_TW instead of M_TWB
From: Christophe Leroy @ 2014-09-17 16:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 48 ++++++++++++++++++---------------
1 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 4a49ff3..ad15070 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -276,8 +276,8 @@ SystemCall:
. = 0x1100
/*
* For the MPC8xx, this is a software tablewalk to load the instruction
- * TLB. It is modelled after the example in the Motorola manual. The task
- * switch loads the M_TWB register with the pointer to the first level table.
+ * TLB. The task switch loads the M_TW register with the pointer to the first
+ * level table.
* If we discover there is no second level table (value is zero) or if there
* is an invalid pte, we load that into the TLB, which causes another fault
* into the TLB Error interrupt where we can handle such problems.
@@ -299,7 +299,6 @@ InstructionTLBMiss:
#endif
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
- mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
@@ -307,14 +306,17 @@ InstructionTLBMiss:
#ifdef CONFIG_MODULES
/* Only modules will cause ITLB Misses as we always
* pin the first 8MB of kernel memory */
- andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
+ andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
+#endif
+ mfspr r11, SPRN_M_TW /* Get level 1 table base address */
+#ifdef CONFIG_MODULES
beq 3f
- lis r11, swapper_pg_dir@h
- ori r11, r11, swapper_pg_dir@l
- rlwimi r10, r11, 0, 2, 19
+ lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
+ ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
3:
#endif
- lwz r11, 0(r10) /* Get the level 1 entry */
+ rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
+ lwzx r11, r10, r11 /* Get the level 1 entry */
rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
@@ -375,18 +377,19 @@ DataStoreTLBMiss:
#endif
EXCEPTION_PROLOG_0
mtspr SPRN_SPRG_SCRATCH2, r10
- mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
+ mfspr r10, SPRN_MD_EPN
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
- andi. r11, r10, 0x0800
+ andis. r11, r10, 0x8000
+ mfspr r11, SPRN_M_TW /* Get level 1 table base address */
beq 3f
- lis r11, swapper_pg_dir@h
- ori r11, r11, swapper_pg_dir@l
- rlwimi r10, r11, 0, 2, 19
+ lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
+ ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
3:
- lwz r11, 0(r10) /* Get the level 1 entry */
+ rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
+ lwzx r11, r10, r11 /* Get the level 1 entry */
rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
@@ -523,12 +526,12 @@ FixupDAR:/* Entry point for dcbx workaround. */
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10
- mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
+ mfspr r11, SPRN_M_TW /* Get level 1 table base address */
beq- 3f /* Branch if user space */
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
- rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
-3: lwz r11, 0(r11) /* Get the level 1 entry */
+3: rlwinm r10, r10, 12, 20, 29 /* Extract level 1 index */
+ lwzx r11, r10, r11 /* Get the level 1 entry */
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
@@ -537,6 +540,7 @@ FixupDAR:/* Entry point for dcbx workaround. */
lwz r3, 8(r0) /* restore r3 from memory */
#endif
/* concat physical page address(r11) and page offset(r10) */
+ mfspr r10, SPRN_SRR0
rlwimi r11, r10, 0, 20, 31
lwz r11,0(r11)
/* Check if it really is a dcbx instruction. */
@@ -692,11 +696,11 @@ start_here:
#ifdef CONFIG_8xx_CPU6
lis r4, cpu6_errata_word@h
ori r4, r4, cpu6_errata_word@l
- li r3, 0x3980
+ li r3, 0x3f80
stw r3, 12(r4)
lwz r3, 12(r4)
#endif
- mtspr SPRN_M_TWB, r6
+ mtspr SPRN_M_TW, r6
lis r4,2f@h
ori r4,r4,2f@l
tophys(r4,r4)
@@ -870,10 +874,10 @@ _GLOBAL(set_context)
lis r6, cpu6_errata_word@h
ori r6, r6, cpu6_errata_word@l
tophys (r4, r4)
- li r7, 0x3980
+ li r7, 0x3f80
stw r7, 12(r6)
lwz r7, 12(r6)
- mtspr SPRN_M_TWB, r4 /* Update MMU base address */
+ mtspr SPRN_M_TW, r4 /* Update MMU base address */
li r7, 0x3380
stw r7, 12(r6)
lwz r7, 12(r6)
@@ -881,7 +885,7 @@ _GLOBAL(set_context)
#else
mtspr SPRN_M_CASID,r3 /* Update context */
tophys (r4, r4)
- mtspr SPRN_M_TWB, r4 /* and pgd */
+ mtspr SPRN_M_TW, r4 /* and pgd */
#endif
SYNC
blr
--
1.7.1
^ permalink raw reply related
* [PATCH v3 08/21] powerpc/8xx: No need to restore registers and save them again.
From: Christophe Leroy @ 2014-09-17 16:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 5f04d5f..e5a250c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -478,8 +478,8 @@ DataTLBError:
cmpwi cr0, r11, 0x00f0
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround */
- EXCEPTION_EPILOG_0
- EXCEPTION_PROLOG
+ EXCEPTION_PROLOG_1
+ EXCEPTION_PROLOG_2
mfspr r10,SPRN_DSISR
stw r10,_DSISR(r11)
mr r5,r10
--
1.7.1
^ permalink raw reply related
* [PATCH v3 14/21] powerpc/8xx: Const for TLB RPN forced value
From: Christophe Leroy @ 2014-09-17 16:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 19 +++++++++++++------
1 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index dcaee9f..8966262 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -40,6 +40,13 @@
#else
#define DO_8xx_CPU6(val, reg)
#endif
+
+/*
+ * Value for the bits that have fixed value in RPN entries.
+ * Also used for tagging DAR for DTLBerror.
+ */
+#define RPN_PATTERN 0x00f0
+
__HEAD
_ENTRY(_stext);
_ENTRY(_start);
@@ -211,7 +218,7 @@ MachineCheck:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
- li r5,0x00f0
+ li r5,RPN_PATTERN
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
@@ -237,7 +244,7 @@ Alignment:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
- li r5,0x00f0
+ li r5,RPN_PATTERN
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
@@ -341,7 +348,7 @@ InstructionTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
- li r11, 0x00f0
+ li r11, RPN_PATTERN
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
DO_8xx_CPU6(0x2d80, r3)
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
@@ -445,7 +452,7 @@ DataStoreTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
-2: li r11, 0x00f0
+2: li r11, RPN_PATTERN
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -479,7 +486,7 @@ DataTLBError:
EXCEPTION_PROLOG_0
mfspr r11, SPRN_DAR
- cmpwi cr0, r11, 0x00f0
+ cmpwi cr0, r11, RPN_PATTERN
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround */
EXCEPTION_PROLOG_1
@@ -488,7 +495,7 @@ DARFixed:/* Return from dcbx instruction bug workaround */
stw r10,_DSISR(r11)
mr r5,r10
mfspr r4,SPRN_DAR
- li r10,0x00f0
+ li r10,RPN_PATTERN
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
EXC_XFER_LITE(0x1400, handle_page_fault)
--
1.7.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox