* Re: [PATCH v3 00/27] Use MSI chip framework to configure MSI/MSI-X in all platforms
From: Bjorn Helgaas @ 2014-10-23 5:43 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-1-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:48AM +0800, Yijing Wang wrote:
> Now there are a lot of weak arch functions in MSI code.
> Thierry Reding Introduced MSI chip framework to configure MSI/MSI-X in arm,
> that's a better solution than overriding lots of existing weak arch functionsin.
> This series use MSI chip framework to refactor MSI code across all platforms
> to eliminate weak arch functions. Then all MSI irqs will be managed in a
> unified framework. Because this series changed a lot of ARCH MSI code,
> so tests in the related platforms are warmly welcomed!
>
> And you may access it at:
> https://github.com/YijingWang/msi-chip-v3.git master
>
> v2->v3:
> 1. For patch "x86/xen/MSI: Eliminate...", introduce a new global flag "pci_msi_ignore_mask"
> to control the msi mask instead of replacing the irqchip->mask with nop function,
> the latter method has problem pointed out by Konrad Rzeszutek Wilk.
> 2. Save msi chip in arch pci sysdata instead of associating msi chip to pci bus.
> Because pci devices under same host share the same msi chip, so I think associate
> msi chip to pci host/pci sysdata is better than to bother every pci bus/devices.
> A better solution suggested by Liviu is to rip out pci_host_bridge from pci_create_root_bus(),
> then we can save some pci host common attributes like domain_nr, msi_chip, resources,
> into the generic pci_host_bridge. Because this changes to pci host bridge is also
> a large series, so I think we should go step by step, I will try to post it in another
> series later.
> 4. Clean up arm pcibios_add_bus() and pcibios_remove_bus() which were used to associate
> msi chip to pci bus.
>
> v1->v2:
> Add a patch to make s390 MSI code build happy between patch "x86/xen/MSI: E.."
> and "s390/MSI: Use MSI..". Fix several typo problems found by Lucas.
>
> RFC->v1:
> Updated "[patch 4/21] x86/xen/MSI: Eliminate...", export msi_chip instead
> of #ifdef to fix MSI bug in xen running in x86.
> Rename arch_get_match_msi_chip() to arch_find_msi_chip().
> Drop use struct device as the msi_chip argument, we will do that
> later in another patchset.
>
> Yijing Wang (27):
This is a lot of stuff, and it's not all related, so putting it all
together in one series makes it hard for me to deal with it.
> MSI: Remove the redundant irq_set_chip_data()
This doesn't seem related to eliminating weak functions.
> x86/xen/MSI: Eliminate arch_msix_mask_irq() and arch_msi_mask_irq()
> s390/MSI: Use __msi_mask_irq() instead of default_msi_mask_irq()
These two seem to go together.
> arm/MSI: Save MSI chip in pci_sys_data
> PCI: tegra: Save msi chip in pci_sys_data
> PCI: designware: Save msi chip in pci_sys_data
> PCI: rcar: Save msi chip in pci_sys_data
> PCI: mvebu: Save msi chip in pci_sys_data
> arm/PCI: Clean unused pcibios_add_bus() and pcibios_remove_bus()
> PCI/MSI: Remove useless bus->msi assignment
These seem to go together (it'd be nice if they were all capitalized the
same).
I don't like the "msi_chip" name because the "chip" part doesn't convey
much information, other than telling us that apparently some sort of
semiconductor integrated circuit is involved. I sort of assumed that
much :)
Something like "msi_controller" would be more descriptive since we're
talking about an interrupt controller that accepts writes from a device and
turns them into CPU interrupts, e.g., a LAPIC.
> PCI/MSI: Refactor struct msi_chip to make it become more common
> x86/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> x86/xen/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> Irq_remapping/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> x86/MSI: Remove unused MSI weak arch functions
> Mips/MSI: Save msi chip in pci sysdata
> MIPS/Octeon/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> MIPS/Xlp: Remove the dead function destroy_irq() to fix build error
> MIPS/Xlp/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> MIPS/Xlr/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> Powerpc/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> s390/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> arm/iop13xx/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> IA64/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> Sparc/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> tile/MSI: Use MSI chip framework to configure MSI/MSI-X irq
> PCI/MSI: Clean up unused MSI arch functions
>
> arch/arm/include/asm/mach/pci.h | 10 +-
> arch/arm/include/asm/pci.h | 9 ++
> arch/arm/kernel/bios32.c | 19 +---
> arch/arm/mach-iop13xx/include/mach/pci.h | 4 +
> arch/arm/mach-iop13xx/iq81340mc.c | 3 +
> arch/arm/mach-iop13xx/iq81340sc.c | 5 +-
> arch/arm/mach-iop13xx/msi.c | 11 ++-
> arch/ia64/include/asm/pci.h | 10 ++
> arch/ia64/kernel/msi_ia64.c | 14 ++-
> arch/ia64/pci/pci.c | 1 +
> arch/mips/include/asm/netlogic/xlp-hal/pcibus.h | 1 +
> arch/mips/include/asm/octeon/pci-octeon.h | 4 +
> arch/mips/include/asm/pci.h | 14 +++
> arch/mips/pci/msi-octeon.c | 31 +++---
> arch/mips/pci/msi-xlp.c | 15 ++-
> arch/mips/pci/pci-octeon.c | 3 +
> arch/mips/pci/pci-xlp.c | 3 +
> arch/mips/pci/pci-xlr.c | 17 +++-
> arch/powerpc/include/asm/pci-bridge.h | 15 +++
> arch/powerpc/kernel/msi.c | 12 ++-
> arch/powerpc/kernel/pci-common.c | 3 +
> arch/s390/include/asm/pci.h | 9 ++
> arch/s390/pci/pci.c | 16 ++-
> arch/sparc/kernel/pci.c | 14 ++-
> arch/sparc/kernel/pci_impl.h | 12 ++
> arch/tile/include/asm/pci.h | 10 ++
> arch/tile/kernel/pci_gx.c | 13 ++-
> arch/x86/include/asm/pci.h | 18 +++-
> arch/x86/include/asm/x86_init.h | 7 --
> arch/x86/kernel/apic/io_apic.c | 12 ++-
> arch/x86/kernel/x86_init.c | 34 ------
> arch/x86/pci/acpi.c | 1 +
> arch/x86/pci/common.c | 3 +
> arch/x86/pci/xen.c | 72 +++++++------
> drivers/iommu/irq_remapping.c | 13 ++-
> drivers/pci/host/pci-mvebu.c | 10 +--
> drivers/pci/host/pci-tegra.c | 13 +--
> drivers/pci/host/pcie-designware.c | 15 +--
> drivers/pci/host/pcie-rcar.c | 13 +--
> drivers/pci/msi.c | 133 ++++++++++-------------
> drivers/pci/probe.c | 1 -
> include/linux/msi.h | 24 ++---
> include/linux/pci.h | 1 +
> 43 files changed, 379 insertions(+), 269 deletions(-)
Huh. I was hoping this was going to simplify things, and maybe it does
somehow, but it's unfortunate that it adds 110 lines of code overall. Does
that seem right to you? Why does it add code?
Who do you want to apply this? I can take it if that makes the most sense,
but I'd like acks from the architecture folks for their pieces, and
especially one from Thomas for the overall direction and the x86 parts.
If you want me to take this, can you refresh it to be based on v3.18-rc1?
I tried to apply it on v3.18-rc1, but [15/27] didn't apply because of
conflicts in arch/x86/kernel/apic/io_apic.c.
I'll look at these more tomorrow, I'm getting bleary-eyed tonight.
Bjorn
^ permalink raw reply
* Re: [PATCH v3 10/27] PCI/MSI: Remove useless bus->msi assignment
From: Bjorn Helgaas @ 2014-10-23 5:41 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-11-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:58AM +0800, Yijing Wang wrote:
> Now msi chip is saved in pci_sys_data in arm,
> we could clean the bus->msi assignment in
> pci core.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> CC: Thierry Reding <thierry.reding@gmail.com>
> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
> drivers/pci/probe.c | 1 -
> 1 files changed, 0 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index efa48dc..98bf4c3 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -682,7 +682,6 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
>
> child->parent = parent;
> child->ops = parent->ops;
> - child->msi = parent->msi;
This needs an explanation of why ARM was the only arch to depend on this.
> child->sysdata = parent->sysdata;
> child->bus_flags = parent->bus_flags;
>
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 09/27] arm/PCI: Clean unused pcibios_add_bus() and pcibios_remove_bus()
From: Bjorn Helgaas @ 2014-10-23 5:38 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-10-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:57AM +0800, Yijing Wang wrote:
> MSI chip will be saved in pci_sys_data, now we can
> clean up pcibios_add_bus() and pcibios_remove_bus()
> in arm, and use pci_find_msi_chip() to get msi chip
> in core MSI code.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
> arch/arm/include/asm/mach/pci.h | 4 ----
> arch/arm/kernel/bios32.c | 16 ----------------
> drivers/pci/msi.c | 11 +++--------
> 3 files changed, 3 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
> index 59b0d87..230b2c9 100644
> --- a/arch/arm/include/asm/mach/pci.h
> +++ b/arch/arm/include/asm/mach/pci.h
> @@ -39,8 +39,6 @@ struct hw_pci {
> resource_size_t start,
> resource_size_t size,
> resource_size_t align);
> - void (*add_bus)(struct pci_bus *bus);
> - void (*remove_bus)(struct pci_bus *bus);
> };
>
> /*
> @@ -71,8 +69,6 @@ struct pci_sys_data {
> resource_size_t start,
> resource_size_t size,
> resource_size_t align);
> - void (*add_bus)(struct pci_bus *bus);
> - void (*remove_bus)(struct pci_bus *bus);
> void *private_data; /* platform controller private data */
> };
>
> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> index a19038d..b1b872e 100644
> --- a/arch/arm/kernel/bios32.c
> +++ b/arch/arm/kernel/bios32.c
> @@ -360,20 +360,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
> }
> EXPORT_SYMBOL(pcibios_fixup_bus);
>
> -void pcibios_add_bus(struct pci_bus *bus)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - if (sys->add_bus)
> - sys->add_bus(bus);
> -}
> -
> -void pcibios_remove_bus(struct pci_bus *bus)
> -{
> - struct pci_sys_data *sys = bus->sysdata;
> - if (sys->remove_bus)
> - sys->remove_bus(bus);
> -}
> -
> /*
> * Swizzle the device pin each time we cross a bridge. If a platform does
> * not provide a swizzle function, we perform the standard PCI swizzling.
> @@ -478,8 +464,6 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
> sys->swizzle = hw->swizzle;
> sys->map_irq = hw->map_irq;
> sys->align_resource = hw->align_resource;
> - sys->add_bus = hw->add_bus;
> - sys->remove_bus = hw->remove_bus;
> INIT_LIST_HEAD(&sys->resources);
>
> if (hw->private_data)
What do the core changes below have to do with the ARM changes above?
They should be a separate patch unless they can't be separated.
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index f11108c..56e54ad 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -32,12 +32,10 @@ int pci_msi_ignore_mask;
>
> int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
> {
> - struct msi_chip *chip = dev->bus->msi;
> + struct msi_chip *chip;
> int err;
>
> - if (!chip)
> - chip = pci_msi_chip(dev->bus);
> -
> + chip = pci_msi_chip(dev->bus);
> if (!chip || !chip->setup_irq)
> return -EINVAL;
>
> @@ -51,10 +49,7 @@ int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
> void __weak arch_teardown_msi_irq(unsigned int irq)
> {
> struct msi_desc *entry = irq_get_msi_desc(irq);
> - struct msi_chip *chip = entry->dev->bus->msi;
> -
> - if (!chip)
> - chip = pci_msi_chip(entry->dev->bus);
> + struct msi_chip *chip = pci_msi_chip(entry->dev->bus);
>
> if (!chip || !chip->teardown_irq)
> return;
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 04/27] arm/MSI: Save MSI chip in pci_sys_data
From: Bjorn Helgaas @ 2014-10-23 5:35 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-5-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:52AM +0800, Yijing Wang wrote:
> Saving msi chip in pci_sys_data can make pci bus and
> devices don't need to know msi chip detail, it also
> make pci enumeration code be decoupled from msi chip.
> In fact, all pci devices under the same pci hostbridge
> share same msi chip. So msi chip should be seen as one
> of resources or attributes to be initialized in pci host
> bridge driver. Currently, pci hostbridge drivers create
> pci_host_bridge in pci_create_root_bus(), and pass arch
> specific pci sysdata to core pci scan functions. So pci
> arch sysdata is good place to save msi chip.
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
> arch/arm/include/asm/mach/pci.h | 6 ++++++
> arch/arm/include/asm/pci.h | 9 +++++++++
> arch/arm/kernel/bios32.c | 3 +++
> drivers/pci/msi.c | 6 ++++++
> include/linux/pci.h | 9 +++++++++
> 5 files changed, 33 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
> index 7fc4278..59b0d87 100644
> --- a/arch/arm/include/asm/mach/pci.h
> +++ b/arch/arm/include/asm/mach/pci.h
> @@ -22,6 +22,9 @@ struct hw_pci {
> #ifdef CONFIG_PCI_DOMAINS
> int domain;
> #endif
> +#ifdef CONFIG_PCI_MSI
> + struct msi_chip *msi_chip;
> +#endif
> struct pci_ops *ops;
> int nr_controllers;
> void **private_data;
> @@ -47,6 +50,9 @@ struct pci_sys_data {
> #ifdef CONFIG_PCI_DOMAINS
> int domain;
> #endif
> +#ifdef CONFIG_PCI_MSI
> + struct msi_chip *msi_chip;
> +#endif
> struct list_head node;
> int busnr; /* primary bus number */
> u64 mem_offset; /* bus->cpu memory mapping offset */
> diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
> index 7e95d85..b562c09 100644
> --- a/arch/arm/include/asm/pci.h
> +++ b/arch/arm/include/asm/pci.h
> @@ -31,6 +31,15 @@ static inline int pci_proc_domain(struct pci_bus *bus)
> }
> #endif /* CONFIG_PCI_DOMAINS */
>
> +#ifdef CONFIG_PCI_MSI
> +static inline struct msi_chip *pci_msi_chip(struct pci_bus *bus)
> +{
> + struct pci_sys_data *root = bus->sysdata;
> +
> + return root->msi_chip;
> +}
> +#endif
> +
> /*
> * The PCI address space does equal the physical memory address space.
> * The networking and block device layers use this boolean for bounce
> diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
> index 17a26c1..a19038d 100644
> --- a/arch/arm/kernel/bios32.c
> +++ b/arch/arm/kernel/bios32.c
> @@ -471,6 +471,9 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
> #ifdef CONFIG_PCI_DOMAINS
> sys->domain = hw->domain;
> #endif
> +#ifdef CONFIG_PCI_MSI
> + sys->msi_chip = hw->msi_chip;
> +#endif
> sys->busnr = busnr;
> sys->swizzle = hw->swizzle;
> sys->map_irq = hw->map_irq;
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index 22e413c..f11108c 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -35,6 +35,9 @@ int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
> struct msi_chip *chip = dev->bus->msi;
> int err;
>
> + if (!chip)
> + chip = pci_msi_chip(dev->bus);
> +
> if (!chip || !chip->setup_irq)
> return -EINVAL;
>
> @@ -50,6 +53,9 @@ void __weak arch_teardown_msi_irq(unsigned int irq)
> struct msi_desc *entry = irq_get_msi_desc(irq);
> struct msi_chip *chip = entry->dev->bus->msi;
>
> + if (!chip)
> + chip = pci_msi_chip(entry->dev->bus);
> +
> if (!chip || !chip->teardown_irq)
> return;
>
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 9cd2721..7a48b40 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -1433,6 +1433,15 @@ static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
>
> #include <asm/pci.h>
>
> +/* Just avoid compile error, will be clean up later */
> +#ifdef CONFIG_PCI_MSI
> +
> +#ifndef pci_msi_chip
> +#define pci_msi_chip(bus) NULL
> +#endif
> +#endif
I don't like the mixture of ARM changes and PCI core changes in the same
patch. Can you split this into a core patch that does something like this:
struct msi_chip * __weak pcibios_msi_controller(struct pci_bus *bus)
{
return NULL;
}
struct msi_chip *pci_msi_controller(struct pci_bus *bus)
{
msi_chip *controller = bus->msi;
if (controller)
return controller;
return pcibios_msi_controller(bus);
}
followed by an ARM patch that puts the msi_chip pointer in struct hw_pci
and implements pcibios_msi_controller()?
I know you're trying to *remove* weak functions, and this adds one, but
this section of the series is more about getting rid of the ARM
pcibios_add_bus() because all it was used for was setting the bus->msi
pointer.
Eventually we might have a way to stash an MSI controller pointer in the
generic pci_host_bridge struct, and then the pcibios_msi_controller()
interface could go away.
> +
> /* these helpers provide future and backwards compatibility
> * for accessing popular PCI BAR info */
> #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
> --
> 1.7.1
>
^ permalink raw reply
* Re: [PATCH v3 05/27] PCI: tegra: Save msi chip in pci_sys_data
From: Bjorn Helgaas @ 2014-10-23 5:18 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-6-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:53AM +0800, Yijing Wang wrote:
> Save msi chip in pci_sys_data instead of assign
> msi chip to every pci bus in .add_bus().
>
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
> drivers/pci/host/pci-tegra.c | 13 +++----------
> 1 files changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 3d43874..5af0525 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -694,15 +694,6 @@ static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
> return irq;
> }
>
> -static void tegra_pcie_add_bus(struct pci_bus *bus)
> -{
> - if (IS_ENABLED(CONFIG_PCI_MSI)) {
> - struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
> -
> - bus->msi = &pcie->msi.chip;
> - }
> -}
> -
> static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> {
> struct tegra_pcie *pcie = sys_to_pcie(sys);
> @@ -1881,11 +1872,13 @@ static int tegra_pcie_enable(struct tegra_pcie *pcie)
>
> memset(&hw, 0, sizeof(hw));
>
> +#ifdef CONFIG_PCI_MSI
> + hw.msi_chip = &pcie->msi.chip;
> +#endif
Why did you use "#ifdef CONFIG_PCI_MSI" instead of the
"IS_ENABLED(CONFIG_PCI_MSI)" used previously?
It's true that CONFIG_PCI_MSI will never be a tristate symbol, so we don't
really *need* the extra smarts of IS_ENABLED(), but I'm fairly sympathetic
to James' argument [1] that we should just use IS_ENABLED() all the time
because it's simpler overall.
If you want to change the #ifdef to IS_ENABLED(), that should be a separate
patch from your msi_chip change, and we can debate the merits of that by
itself.
[1] http://lkml.iu.edu//hypermail/linux/kernel/1204.3/00081.html
> hw.nr_controllers = 1;
> hw.private_data = (void **)&pcie;
> hw.setup = tegra_pcie_setup;
> hw.map_irq = tegra_pcie_map_irq;
> - hw.add_bus = tegra_pcie_add_bus;
> hw.scan = tegra_pcie_scan_bus;
> hw.ops = &tegra_pcie_ops;
>
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: [PATCH v3 02/27] x86/xen/MSI: Eliminate arch_msix_mask_irq() and arch_msi_mask_irq()
From: Yijing Wang @ 2014-10-23 4:44 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <20141023042535.GA11770@google.com>
On 2014/10/23 12:25, Bjorn Helgaas wrote:
> On Wed, Oct 15, 2014 at 11:06:50AM +0800, Yijing Wang wrote:
>> Commit 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()")
>> introduced two __weak arch functions arch_msix_mask_irq() and
>> arch_msi_mask_irq() to work around a bug when running xen in x86.
>> These two functions made msi code more complex. This patch reverts
>> the commit and introduces a global flag to control msi mask action to
>> avoid the bug. The patch is also preparation for using MSI chip framework
>> instead of weak arch MSI functions in all platforms. Keep default_msi_mask_irq()
>> and default_msix_mask_irq() in linux/msi.h to make s390 MSI code compile
>> happy, they will be removed in the later patch.
>
> This patch is basically a revert of 0e4ccb1505a9 intermingled with the
> addition of the new pci_msi_ignore_mask technique.
>
> Can you please split this into two patches:
>
> - Add the pci_msi_ignore_mask stuff (alongside the existing way)
> - Revert 0e4ccb1505a9
>
> I think that will make it easier to see what's going on.
OK, I will do it, thanks.
Thanks!
Yijing.
>
>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>> CC: David Vrabel <david.vrabel@citrix.com>
>> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
>> ---
>> Hi David and Konrad,
>> I dropped the Acked-by and tested-by, because this version has a
>> lot changes compared to last. So, I guess you may want to check it again.
>> ---
>> arch/x86/include/asm/x86_init.h | 3 ---
>> arch/x86/kernel/x86_init.c | 10 ----------
>> arch/x86/pci/xen.c | 14 ++------------
>> drivers/pci/msi.c | 29 ++++++++++++-----------------
>> include/linux/msi.h | 8 ++++++--
>> 5 files changed, 20 insertions(+), 44 deletions(-)
>>
>> diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
>> index e45e4da..f58a9c7 100644
>> --- a/arch/x86/include/asm/x86_init.h
>> +++ b/arch/x86/include/asm/x86_init.h
>> @@ -172,7 +172,6 @@ struct x86_platform_ops {
>>
>> struct pci_dev;
>> struct msi_msg;
>> -struct msi_desc;
>>
>> struct x86_msi_ops {
>> int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
>> @@ -183,8 +182,6 @@ struct x86_msi_ops {
>> void (*teardown_msi_irqs)(struct pci_dev *dev);
>> void (*restore_msi_irqs)(struct pci_dev *dev);
>> int (*setup_hpet_msi)(unsigned int irq, unsigned int id);
>> - u32 (*msi_mask_irq)(struct msi_desc *desc, u32 mask, u32 flag);
>> - u32 (*msix_mask_irq)(struct msi_desc *desc, u32 flag);
>> };
>>
>> struct IO_APIC_route_entry;
>> diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
>> index e48b674..234b072 100644
>> --- a/arch/x86/kernel/x86_init.c
>> +++ b/arch/x86/kernel/x86_init.c
>> @@ -116,8 +116,6 @@ struct x86_msi_ops x86_msi = {
>> .teardown_msi_irqs = default_teardown_msi_irqs,
>> .restore_msi_irqs = default_restore_msi_irqs,
>> .setup_hpet_msi = default_setup_hpet_msi,
>> - .msi_mask_irq = default_msi_mask_irq,
>> - .msix_mask_irq = default_msix_mask_irq,
>> };
>>
>> /* MSI arch specific hooks */
>> @@ -140,14 +138,6 @@ void arch_restore_msi_irqs(struct pci_dev *dev)
>> {
>> x86_msi.restore_msi_irqs(dev);
>> }
>> -u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> -{
>> - return x86_msi.msi_mask_irq(desc, mask, flag);
>> -}
>> -u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
>> -{
>> - return x86_msi.msix_mask_irq(desc, flag);
>> -}
>> #endif
>>
>> struct x86_io_apic_ops x86_io_apic_ops = {
>> diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
>> index 093f5f4..e5b8b78 100644
>> --- a/arch/x86/pci/xen.c
>> +++ b/arch/x86/pci/xen.c
>> @@ -394,14 +394,6 @@ static void xen_teardown_msi_irq(unsigned int irq)
>> {
>> xen_destroy_irq(irq);
>> }
>> -static u32 xen_nop_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> -{
>> - return 0;
>> -}
>> -static u32 xen_nop_msix_mask_irq(struct msi_desc *desc, u32 flag)
>> -{
>> - return 0;
>> -}
>> #endif
>>
>> int __init pci_xen_init(void)
>> @@ -425,8 +417,7 @@ int __init pci_xen_init(void)
>> x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
>> x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
>> x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
>> - x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
>> - x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
>> + pci_msi_ignore_mask = 1;
>> #endif
>> return 0;
>> }
>> @@ -506,8 +497,7 @@ int __init pci_xen_initial_domain(void)
>> x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
>> x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
>> x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
>> - x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
>> - x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
>> + pci_msi_ignore_mask = 1;
>> #endif
>> xen_setup_acpi_sci();
>> __acpi_register_gsi = acpi_register_gsi_xen;
>> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>> index ecb92a5..22e413c 100644
>> --- a/drivers/pci/msi.c
>> +++ b/drivers/pci/msi.c
>> @@ -23,6 +23,7 @@
>> #include "pci.h"
>>
>> static int pci_msi_enable = 1;
>> +int pci_msi_ignore_mask;
>>
>> #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
>>
>> @@ -162,11 +163,11 @@ static inline __attribute_const__ u32 msi_mask(unsigned x)
>> * reliably as devices without an INTx disable bit will then generate a
>> * level IRQ which will never be cleared.
>> */
>> -u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> +u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> {
>> u32 mask_bits = desc->masked;
>>
>> - if (!desc->msi_attrib.maskbit)
>> + if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
>> return 0;
>>
>> mask_bits &= ~mask;
>> @@ -176,14 +177,9 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> return mask_bits;
>> }
>>
>> -__weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> -{
>> - return default_msi_mask_irq(desc, mask, flag);
>> -}
>> -
>> static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> {
>> - desc->masked = arch_msi_mask_irq(desc, mask, flag);
>> + desc->masked = __msi_mask_irq(desc, mask, flag);
>> }
>>
>> /*
>> @@ -193,11 +189,15 @@ static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
>> * file. This saves a few milliseconds when initialising devices with lots
>> * of MSI-X interrupts.
>> */
>> -u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
>> +u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
>> {
>> u32 mask_bits = desc->masked;
>> unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
>> PCI_MSIX_ENTRY_VECTOR_CTRL;
>> +
>> + if (pci_msi_ignore_mask)
>> + return 0;
>> +
>> mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
>> if (flag)
>> mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
>> @@ -206,14 +206,9 @@ u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
>> return mask_bits;
>> }
>>
>> -__weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
>> -{
>> - return default_msix_mask_irq(desc, flag);
>> -}
>> -
>> static void msix_mask_irq(struct msi_desc *desc, u32 flag)
>> {
>> - desc->masked = arch_msix_mask_irq(desc, flag);
>> + desc->masked = __msix_mask_irq(desc, flag);
>> }
>>
>> static void msi_set_mask_bit(struct irq_data *data, u32 flag)
>> @@ -866,7 +861,7 @@ void pci_msi_shutdown(struct pci_dev *dev)
>> /* Return the device with MSI unmasked as initial states */
>> mask = msi_mask(desc->msi_attrib.multi_cap);
>> /* Keep cached state to be restored */
>> - arch_msi_mask_irq(desc, mask, ~mask);
>> + __msi_mask_irq(desc, mask, ~mask);
>>
>> /* Restore dev->irq to its default pin-assertion irq */
>> dev->irq = desc->msi_attrib.default_irq;
>> @@ -964,7 +959,7 @@ void pci_msix_shutdown(struct pci_dev *dev)
>> /* Return the device with MSI-X masked as initial states */
>> list_for_each_entry(entry, &dev->msi_list, list) {
>> /* Keep cached states to be restored */
>> - arch_msix_mask_irq(entry, 1);
>> + __msix_mask_irq(entry, 1);
>> }
>>
>> msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
>> diff --git a/include/linux/msi.h b/include/linux/msi.h
>> index 44f4746..9ac1e3b 100644
>> --- a/include/linux/msi.h
>> +++ b/include/linux/msi.h
>> @@ -10,6 +10,8 @@ struct msi_msg {
>> u32 data; /* 16 bits of msi message data */
>> };
>>
>> +extern int pci_msi_ignore_mask;
>> +
>> /* Helper functions */
>> struct irq_data;
>> struct msi_desc;
>> @@ -21,6 +23,8 @@ void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
>> void read_msi_msg(unsigned int irq, struct msi_msg *msg);
>> void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
>> void write_msi_msg(unsigned int irq, struct msi_msg *msg);
>> +u32 __msix_mask_irq(struct msi_desc *desc, u32 flag);
>> +u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
>>
>> struct msi_desc {
>> struct {
>> @@ -61,8 +65,8 @@ void arch_restore_msi_irqs(struct pci_dev *dev);
>>
>> void default_teardown_msi_irqs(struct pci_dev *dev);
>> void default_restore_msi_irqs(struct pci_dev *dev);
>> -u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
>> -u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
>> +#define default_msi_mask_irq __msi_mask_irq
>> +#define default_msix_mask_irq __msix_mask_irq
>>
>> struct msi_chip {
>> struct module *owner;
>> --
>> 1.7.1
>>
>
> .
>
--
Thanks!
Yijing
^ permalink raw reply
* Re: [PATCH V2 1/2] mm: Update generic gup implementation to handle hugepage directory
From: Aneesh Kumar K.V @ 2014-10-23 4:28 UTC (permalink / raw)
To: Andrew Morton
Cc: Andrea Arcangeli, linux-arch, Steve Capper, linux-kernel,
linux-mm, linuxppc-dev
In-Reply-To: <20141022160224.9c2268795e55d5a2eff5b94d@linux-foundation.org>
Andrew Morton <akpm@linux-foundation.org> writes:
> On Fri, 17 Oct 2014 10:08:06 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
>
>> Update generic gup implementation with powerpc specific details.
>> On powerpc at pmd level we can have hugepte, normal pmd pointer
>> or a pointer to the hugepage directory.
>>
>> ...
>>
>> --- a/arch/arm/include/asm/pgtable.h
>> +++ b/arch/arm/include/asm/pgtable.h
>> @@ -181,6 +181,8 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
>> /* to find an entry in a kernel page-table-directory */
>> #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
>>
>> +#define pgd_huge(pgd) (0)
>> +
>> #define pmd_none(pmd) (!pmd_val(pmd))
>> #define pmd_present(pmd) (pmd_val(pmd))
>>
>> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
>> index cefd3e825612..ed8f42497ac4 100644
>> --- a/arch/arm64/include/asm/pgtable.h
>> +++ b/arch/arm64/include/asm/pgtable.h
>> @@ -464,6 +464,8 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
>> extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
>> extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
>>
>> +#define pgd_huge(pgd) (0)
>> +
>
> So only arm, arm64 and powerpc implement CONFIG_HAVE_GENERIC_RCU_GUP
> and only powerpc impements pgd_huge().
>
> Could we get a bit of documentation in place for pgd_huge() so that
> people who aren't familiar with powerpc can understand what's going
> on?
Will update
>
>> /*
>> * Encode and decode a swap entry:
>> * bits 0-1: present (must be zero)
>> diff --git a/include/linux/mm.h b/include/linux/mm.h
>> index 02d11ee7f19d..f97732412cb4 100644
>> --- a/include/linux/mm.h
>> +++ b/include/linux/mm.h
>> @@ -1219,6 +1219,32 @@ long get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
>> struct vm_area_struct **vmas);
>> int get_user_pages_fast(unsigned long start, int nr_pages, int write,
>> struct page **pages);
>> +
>> +#ifdef CONFIG_HAVE_GENERIC_RCU_GUP
>> +#ifndef is_hugepd
>
> And is_hugepd is a bit of a mystery. Let's get some description in
> place for this as well? Why it exists, what its role is. Also,
> specifically which arch header file is responsible for defining it.
>
> It takes a hugepd_t argument, but hugepd_t is defined later in this
> header file. This is weird because any preceding implementation of
> is_hugepd() can't actually be implemented because it hasn't seen the
> hugepd_t definition yet! So any is_hugepd() implementation is forced
> to be a simple macro which punts to a C function which *has* seen the
> hugepd_t definition. What a twisty maze.
arch can definitely do
#defne is_hugepd is_hugepd
typedef struct { unsigned long pd; } hugepd_t;
static inline int is_hugepd(hugepd_t hpd)
{
}
I wanted to make sure arch can have their own definition of hugepd_t .
>
> It all seems messy, confusing and poorly documented. Can we clean this
> up?
>
>> +/*
>> + * Some architectures support hugepage directory format that is
>> + * required to support different hugetlbfs sizes.
>> + */
>> +typedef struct { unsigned long pd; } hugepd_t;
>> +#define is_hugepd(hugepd) (0)
>> +#define __hugepd(x) ((hugepd_t) { (x) })
>
> What's this.
macro that is used to convert value to type hugepd_t. We use that style
already for __pte() etc.
>
>> +static inline int gup_hugepd(hugepd_t hugepd, unsigned long addr,
>> + unsigned pdshift, unsigned long end,
>> + int write, struct page **pages, int *nr)
>> +{
>> + return 0;
>> +}
>> +#else
>> +extern int gup_hugepd(hugepd_t hugepd, unsigned long addr,
>> + unsigned pdshift, unsigned long end,
>> + int write, struct page **pages, int *nr);
>> +#endif
>> +extern int gup_huge_pte(pte_t orig, pte_t *ptep, unsigned long addr,
>> + unsigned long sz, unsigned long end, int write,
>> + struct page **pages, int *nr);
>> +#endif
-aneesh
^ permalink raw reply
* Re: [PATCH v3 02/27] x86/xen/MSI: Eliminate arch_msix_mask_irq() and arch_msi_mask_irq()
From: Bjorn Helgaas @ 2014-10-23 4:25 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-3-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:06:50AM +0800, Yijing Wang wrote:
> Commit 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()")
> introduced two __weak arch functions arch_msix_mask_irq() and
> arch_msi_mask_irq() to work around a bug when running xen in x86.
> These two functions made msi code more complex. This patch reverts
> the commit and introduces a global flag to control msi mask action to
> avoid the bug. The patch is also preparation for using MSI chip framework
> instead of weak arch MSI functions in all platforms. Keep default_msi_mask_irq()
> and default_msix_mask_irq() in linux/msi.h to make s390 MSI code compile
> happy, they will be removed in the later patch.
This patch is basically a revert of 0e4ccb1505a9 intermingled with the
addition of the new pci_msi_ignore_mask technique.
Can you please split this into two patches:
- Add the pci_msi_ignore_mask stuff (alongside the existing way)
- Revert 0e4ccb1505a9
I think that will make it easier to see what's going on.
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> CC: David Vrabel <david.vrabel@citrix.com>
> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
> ---
> Hi David and Konrad,
> I dropped the Acked-by and tested-by, because this version has a
> lot changes compared to last. So, I guess you may want to check it again.
> ---
> arch/x86/include/asm/x86_init.h | 3 ---
> arch/x86/kernel/x86_init.c | 10 ----------
> arch/x86/pci/xen.c | 14 ++------------
> drivers/pci/msi.c | 29 ++++++++++++-----------------
> include/linux/msi.h | 8 ++++++--
> 5 files changed, 20 insertions(+), 44 deletions(-)
>
> diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
> index e45e4da..f58a9c7 100644
> --- a/arch/x86/include/asm/x86_init.h
> +++ b/arch/x86/include/asm/x86_init.h
> @@ -172,7 +172,6 @@ struct x86_platform_ops {
>
> struct pci_dev;
> struct msi_msg;
> -struct msi_desc;
>
> struct x86_msi_ops {
> int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
> @@ -183,8 +182,6 @@ struct x86_msi_ops {
> void (*teardown_msi_irqs)(struct pci_dev *dev);
> void (*restore_msi_irqs)(struct pci_dev *dev);
> int (*setup_hpet_msi)(unsigned int irq, unsigned int id);
> - u32 (*msi_mask_irq)(struct msi_desc *desc, u32 mask, u32 flag);
> - u32 (*msix_mask_irq)(struct msi_desc *desc, u32 flag);
> };
>
> struct IO_APIC_route_entry;
> diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
> index e48b674..234b072 100644
> --- a/arch/x86/kernel/x86_init.c
> +++ b/arch/x86/kernel/x86_init.c
> @@ -116,8 +116,6 @@ struct x86_msi_ops x86_msi = {
> .teardown_msi_irqs = default_teardown_msi_irqs,
> .restore_msi_irqs = default_restore_msi_irqs,
> .setup_hpet_msi = default_setup_hpet_msi,
> - .msi_mask_irq = default_msi_mask_irq,
> - .msix_mask_irq = default_msix_mask_irq,
> };
>
> /* MSI arch specific hooks */
> @@ -140,14 +138,6 @@ void arch_restore_msi_irqs(struct pci_dev *dev)
> {
> x86_msi.restore_msi_irqs(dev);
> }
> -u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> -{
> - return x86_msi.msi_mask_irq(desc, mask, flag);
> -}
> -u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
> -{
> - return x86_msi.msix_mask_irq(desc, flag);
> -}
> #endif
>
> struct x86_io_apic_ops x86_io_apic_ops = {
> diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
> index 093f5f4..e5b8b78 100644
> --- a/arch/x86/pci/xen.c
> +++ b/arch/x86/pci/xen.c
> @@ -394,14 +394,6 @@ static void xen_teardown_msi_irq(unsigned int irq)
> {
> xen_destroy_irq(irq);
> }
> -static u32 xen_nop_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> -{
> - return 0;
> -}
> -static u32 xen_nop_msix_mask_irq(struct msi_desc *desc, u32 flag)
> -{
> - return 0;
> -}
> #endif
>
> int __init pci_xen_init(void)
> @@ -425,8 +417,7 @@ int __init pci_xen_init(void)
> x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
> x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
> x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs;
> - x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
> - x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
> + pci_msi_ignore_mask = 1;
> #endif
> return 0;
> }
> @@ -506,8 +497,7 @@ int __init pci_xen_initial_domain(void)
> x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs;
> x86_msi.teardown_msi_irq = xen_teardown_msi_irq;
> x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
> - x86_msi.msi_mask_irq = xen_nop_msi_mask_irq;
> - x86_msi.msix_mask_irq = xen_nop_msix_mask_irq;
> + pci_msi_ignore_mask = 1;
> #endif
> xen_setup_acpi_sci();
> __acpi_register_gsi = acpi_register_gsi_xen;
> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
> index ecb92a5..22e413c 100644
> --- a/drivers/pci/msi.c
> +++ b/drivers/pci/msi.c
> @@ -23,6 +23,7 @@
> #include "pci.h"
>
> static int pci_msi_enable = 1;
> +int pci_msi_ignore_mask;
>
> #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
>
> @@ -162,11 +163,11 @@ static inline __attribute_const__ u32 msi_mask(unsigned x)
> * reliably as devices without an INTx disable bit will then generate a
> * level IRQ which will never be cleared.
> */
> -u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> +u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> {
> u32 mask_bits = desc->masked;
>
> - if (!desc->msi_attrib.maskbit)
> + if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
> return 0;
>
> mask_bits &= ~mask;
> @@ -176,14 +177,9 @@ u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> return mask_bits;
> }
>
> -__weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> -{
> - return default_msi_mask_irq(desc, mask, flag);
> -}
> -
> static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> {
> - desc->masked = arch_msi_mask_irq(desc, mask, flag);
> + desc->masked = __msi_mask_irq(desc, mask, flag);
> }
>
> /*
> @@ -193,11 +189,15 @@ static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
> * file. This saves a few milliseconds when initialising devices with lots
> * of MSI-X interrupts.
> */
> -u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
> +u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
> {
> u32 mask_bits = desc->masked;
> unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
> PCI_MSIX_ENTRY_VECTOR_CTRL;
> +
> + if (pci_msi_ignore_mask)
> + return 0;
> +
> mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
> if (flag)
> mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
> @@ -206,14 +206,9 @@ u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
> return mask_bits;
> }
>
> -__weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
> -{
> - return default_msix_mask_irq(desc, flag);
> -}
> -
> static void msix_mask_irq(struct msi_desc *desc, u32 flag)
> {
> - desc->masked = arch_msix_mask_irq(desc, flag);
> + desc->masked = __msix_mask_irq(desc, flag);
> }
>
> static void msi_set_mask_bit(struct irq_data *data, u32 flag)
> @@ -866,7 +861,7 @@ void pci_msi_shutdown(struct pci_dev *dev)
> /* Return the device with MSI unmasked as initial states */
> mask = msi_mask(desc->msi_attrib.multi_cap);
> /* Keep cached state to be restored */
> - arch_msi_mask_irq(desc, mask, ~mask);
> + __msi_mask_irq(desc, mask, ~mask);
>
> /* Restore dev->irq to its default pin-assertion irq */
> dev->irq = desc->msi_attrib.default_irq;
> @@ -964,7 +959,7 @@ void pci_msix_shutdown(struct pci_dev *dev)
> /* Return the device with MSI-X masked as initial states */
> list_for_each_entry(entry, &dev->msi_list, list) {
> /* Keep cached states to be restored */
> - arch_msix_mask_irq(entry, 1);
> + __msix_mask_irq(entry, 1);
> }
>
> msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
> diff --git a/include/linux/msi.h b/include/linux/msi.h
> index 44f4746..9ac1e3b 100644
> --- a/include/linux/msi.h
> +++ b/include/linux/msi.h
> @@ -10,6 +10,8 @@ struct msi_msg {
> u32 data; /* 16 bits of msi message data */
> };
>
> +extern int pci_msi_ignore_mask;
> +
> /* Helper functions */
> struct irq_data;
> struct msi_desc;
> @@ -21,6 +23,8 @@ void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg);
> void read_msi_msg(unsigned int irq, struct msi_msg *msg);
> void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg);
> void write_msi_msg(unsigned int irq, struct msi_msg *msg);
> +u32 __msix_mask_irq(struct msi_desc *desc, u32 flag);
> +u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
>
> struct msi_desc {
> struct {
> @@ -61,8 +65,8 @@ void arch_restore_msi_irqs(struct pci_dev *dev);
>
> void default_teardown_msi_irqs(struct pci_dev *dev);
> void default_restore_msi_irqs(struct pci_dev *dev);
> -u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag);
> -u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag);
> +#define default_msi_mask_irq __msi_mask_irq
> +#define default_msix_mask_irq __msix_mask_irq
>
> struct msi_chip {
> struct module *owner;
> --
> 1.7.1
>
^ permalink raw reply
* Re: [PATCH v3 24/27] IA64/MSI: Use MSI chip framework to configure MSI/MSI-X irq
From: Yijing Wang @ 2014-10-23 1:17 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <20141022235345.GE4795@google.com>
On 2014/10/23 7:53, Bjorn Helgaas wrote:
> On Wed, Oct 15, 2014 at 11:07:12AM +0800, Yijing Wang wrote:
>> Use MSI chip framework instead of arch MSI functions to configure
>> MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework.
>
> This needs slightly more detail. You're using the MSI chip framework
> "instead of arch MSI functions". Well, there are still arch-specific
> functions, i.e., arch_ia64_setup_msi_irq() and
> arch_ia64_teardown_msi_irq().
>
> We used to have arch_setup_msi_irq() which had a weak default
> implementation, and a strong arch-specific implementation here, and you're
> replacing that model with the new "msi-ops" model. I don't know how you
> want to write that, but it's not that you're getting rid of the
> arch-specific code; you're keeping arch-specific code but structuring it
> differently.
Hm, I will rename the msi-ops functions.
>
>> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
>> ---
>> arch/ia64/include/asm/pci.h | 10 ++++++++++
>> arch/ia64/kernel/msi_ia64.c | 14 ++++++++++----
>> arch/ia64/pci/pci.c | 1 +
>> 3 files changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
>> index 52af5ed..907dcba 100644
>> --- a/arch/ia64/include/asm/pci.h
>> +++ b/arch/ia64/include/asm/pci.h
>> @@ -94,6 +94,7 @@ struct pci_controller {
>> int segment;
>> int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */
>>
>> + struct msi_chip *msi_chip;
>> void *platform_data;
>> };
>>
>> @@ -101,6 +102,15 @@ struct pci_controller {
>> #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
>> #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
>>
>> +extern struct msi_chip chip;
>
> Please make this name more descriptive. "chip" is way too generic for a
> global name.
OK, what about rename it to ia64_msi_chip, and rename the original static irq_chip ia64_msi_chip to
static irq_chip msi_chip like in x86.
>
>> +static inline struct msi_chip *pci_msi_chip(struct pci_bus *bus)
>> +{
>> + struct pci_controller *ctrl = bus->sysdata;
>> +
>> + return ctrl->msi_chip;
>> +}
>> +
>> extern struct pci_ops pci_root_ops;
>>
>> static inline int pci_proc_domain(struct pci_bus *bus)
>> diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
>> index 8c3730c..401fc98 100644
>> --- a/arch/ia64/kernel/msi_ia64.c
>> +++ b/arch/ia64/kernel/msi_ia64.c
>> @@ -112,15 +112,16 @@ static struct irq_chip ia64_msi_chip = {
>> };
>>
>>
>> -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
>> +static int arch_ia64_setup_msi_irq(struct msi_chip *chip,
>> + struct pci_dev *dev, struct msi_desc *desc)
>> {
>> if (platform_setup_msi_irq)
>> - return platform_setup_msi_irq(pdev, desc);
>> + return platform_setup_msi_irq(dev, desc);
>>
>> - return ia64_setup_msi_irq(pdev, desc);
>> + return ia64_setup_msi_irq(dev, desc);
>
> Please don't make gratuitous changes ("pdev" -> "dev") at the same time,
> especially since the rest of the file still uses "pdev".
OK.
>
>> }
>>
>> -void arch_teardown_msi_irq(unsigned int irq)
>> +static void arch_ia64_teardown_msi_irq(struct msi_chip *chip, unsigned int irq)
>> {
>> if (platform_teardown_msi_irq)
>> return platform_teardown_msi_irq(irq);
>> @@ -128,6 +129,11 @@ void arch_teardown_msi_irq(unsigned int irq)
>> return ia64_teardown_msi_irq(irq);
>> }
>>
>> +struct msi_chip chip = {
>> + .setup_irq = arch_ia64_setup_msi_irq,
>> + .teardown_irq = arch_ia64_teardown_msi_irq,
>> +};
>> +
>> #ifdef CONFIG_INTEL_IOMMU
>> #ifdef CONFIG_SMP
>> static int dmar_msi_set_affinity(struct irq_data *data,
>> diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
>> index 291a582..299b67d 100644
>> --- a/arch/ia64/pci/pci.c
>> +++ b/arch/ia64/pci/pci.c
>> @@ -437,6 +437,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
>>
>> controller->companion = device;
>> controller->node = acpi_get_node(device->handle);
>> + controller->msi_chip = &chip;
>>
>> info = kzalloc(sizeof(*info), GFP_KERNEL);
>> if (!info) {
>> --
>> 1.7.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at http://www.tux.org/lkml/
>
> .
>
--
Thanks!
Yijing
^ permalink raw reply
* Re: [PATCH v3 24/27] IA64/MSI: Use MSI chip framework to configure MSI/MSI-X irq
From: Bjorn Helgaas @ 2014-10-22 23:53 UTC (permalink / raw)
To: Yijing Wang
Cc: linux-mips, linux-ia64, linux-pci, Bharat.Bhushan, Thierry Reding,
sparclinux, linux-arch, linux-s390, Russell King, Joerg Roedel,
x86, Sebastian Ott, xen-devel, arnab.basu, Liviu Dudau,
Arnd Bergmann, Konrad Rzeszutek Wilk, Chris Metcalf,
Thomas Gleixner, linux-arm-kernel, Thomas Petazzoni, Xinwei Hu,
Tony Luck, Sergei Shtylyov, linux-kernel, Ralf Baechle, iommu,
David Vrabel, Wuyun, linuxppc-dev, David S. Miller, Lucas Stach
In-Reply-To: <1413342435-7876-25-git-send-email-wangyijing@huawei.com>
On Wed, Oct 15, 2014 at 11:07:12AM +0800, Yijing Wang wrote:
> Use MSI chip framework instead of arch MSI functions to configure
> MSI/MSI-X irq. So we can manage MSI/MSI-X irq in a unified framework.
This needs slightly more detail. You're using the MSI chip framework
"instead of arch MSI functions". Well, there are still arch-specific
functions, i.e., arch_ia64_setup_msi_irq() and
arch_ia64_teardown_msi_irq().
We used to have arch_setup_msi_irq() which had a weak default
implementation, and a strong arch-specific implementation here, and you're
replacing that model with the new "msi-ops" model. I don't know how you
want to write that, but it's not that you're getting rid of the
arch-specific code; you're keeping arch-specific code but structuring it
differently.
> Signed-off-by: Yijing Wang <wangyijing@huawei.com>
> ---
> arch/ia64/include/asm/pci.h | 10 ++++++++++
> arch/ia64/kernel/msi_ia64.c | 14 ++++++++++----
> arch/ia64/pci/pci.c | 1 +
> 3 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
> index 52af5ed..907dcba 100644
> --- a/arch/ia64/include/asm/pci.h
> +++ b/arch/ia64/include/asm/pci.h
> @@ -94,6 +94,7 @@ struct pci_controller {
> int segment;
> int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */
>
> + struct msi_chip *msi_chip;
> void *platform_data;
> };
>
> @@ -101,6 +102,15 @@ struct pci_controller {
> #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
> #define pci_domain_nr(busdev) (PCI_CONTROLLER(busdev)->segment)
>
> +extern struct msi_chip chip;
Please make this name more descriptive. "chip" is way too generic for a
global name.
> +static inline struct msi_chip *pci_msi_chip(struct pci_bus *bus)
> +{
> + struct pci_controller *ctrl = bus->sysdata;
> +
> + return ctrl->msi_chip;
> +}
> +
> extern struct pci_ops pci_root_ops;
>
> static inline int pci_proc_domain(struct pci_bus *bus)
> diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
> index 8c3730c..401fc98 100644
> --- a/arch/ia64/kernel/msi_ia64.c
> +++ b/arch/ia64/kernel/msi_ia64.c
> @@ -112,15 +112,16 @@ static struct irq_chip ia64_msi_chip = {
> };
>
>
> -int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
> +static int arch_ia64_setup_msi_irq(struct msi_chip *chip,
> + struct pci_dev *dev, struct msi_desc *desc)
> {
> if (platform_setup_msi_irq)
> - return platform_setup_msi_irq(pdev, desc);
> + return platform_setup_msi_irq(dev, desc);
>
> - return ia64_setup_msi_irq(pdev, desc);
> + return ia64_setup_msi_irq(dev, desc);
Please don't make gratuitous changes ("pdev" -> "dev") at the same time,
especially since the rest of the file still uses "pdev".
> }
>
> -void arch_teardown_msi_irq(unsigned int irq)
> +static void arch_ia64_teardown_msi_irq(struct msi_chip *chip, unsigned int irq)
> {
> if (platform_teardown_msi_irq)
> return platform_teardown_msi_irq(irq);
> @@ -128,6 +129,11 @@ void arch_teardown_msi_irq(unsigned int irq)
> return ia64_teardown_msi_irq(irq);
> }
>
> +struct msi_chip chip = {
> + .setup_irq = arch_ia64_setup_msi_irq,
> + .teardown_irq = arch_ia64_teardown_msi_irq,
> +};
> +
> #ifdef CONFIG_INTEL_IOMMU
> #ifdef CONFIG_SMP
> static int dmar_msi_set_affinity(struct irq_data *data,
> diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
> index 291a582..299b67d 100644
> --- a/arch/ia64/pci/pci.c
> +++ b/arch/ia64/pci/pci.c
> @@ -437,6 +437,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
>
> controller->companion = device;
> controller->node = acpi_get_node(device->handle);
> + controller->msi_chip = &chip;
>
> info = kzalloc(sizeof(*info), GFP_KERNEL);
> if (!info) {
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* Re: [PATCH V2 1/2] mm: Update generic gup implementation to handle hugepage directory
From: Andrew Morton @ 2014-10-22 23:02 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: Andrea Arcangeli, linux-arch, Steve Capper, linux-kernel,
linux-mm, linuxppc-dev
In-Reply-To: <1413520687-31729-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On Fri, 17 Oct 2014 10:08:06 +0530 "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
> Update generic gup implementation with powerpc specific details.
> On powerpc at pmd level we can have hugepte, normal pmd pointer
> or a pointer to the hugepage directory.
>
> ...
>
> --- a/arch/arm/include/asm/pgtable.h
> +++ b/arch/arm/include/asm/pgtable.h
> @@ -181,6 +181,8 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
> /* to find an entry in a kernel page-table-directory */
> #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
>
> +#define pgd_huge(pgd) (0)
> +
> #define pmd_none(pmd) (!pmd_val(pmd))
> #define pmd_present(pmd) (pmd_val(pmd))
>
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index cefd3e825612..ed8f42497ac4 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -464,6 +464,8 @@ static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
> extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
> extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
>
> +#define pgd_huge(pgd) (0)
> +
So only arm, arm64 and powerpc implement CONFIG_HAVE_GENERIC_RCU_GUP
and only powerpc impements pgd_huge().
Could we get a bit of documentation in place for pgd_huge() so that
people who aren't familiar with powerpc can understand what's going on?
> /*
> * Encode and decode a swap entry:
> * bits 0-1: present (must be zero)
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index 02d11ee7f19d..f97732412cb4 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -1219,6 +1219,32 @@ long get_user_pages(struct task_struct *tsk, struct mm_struct *mm,
> struct vm_area_struct **vmas);
> int get_user_pages_fast(unsigned long start, int nr_pages, int write,
> struct page **pages);
> +
> +#ifdef CONFIG_HAVE_GENERIC_RCU_GUP
> +#ifndef is_hugepd
And is_hugepd is a bit of a mystery. Let's get some description in
place for this as well? Why it exists, what its role is. Also,
specifically which arch header file is responsible for defining it.
It takes a hugepd_t argument, but hugepd_t is defined later in this
header file. This is weird because any preceding implementation of
is_hugepd() can't actually be implemented because it hasn't seen the
hugepd_t definition yet! So any is_hugepd() implementation is forced
to be a simple macro which punts to a C function which *has* seen the
hugepd_t definition. What a twisty maze.
It all seems messy, confusing and poorly documented. Can we clean this
up?
> +/*
> + * Some architectures support hugepage directory format that is
> + * required to support different hugetlbfs sizes.
> + */
> +typedef struct { unsigned long pd; } hugepd_t;
> +#define is_hugepd(hugepd) (0)
> +#define __hugepd(x) ((hugepd_t) { (x) })
What's this.
> +static inline int gup_hugepd(hugepd_t hugepd, unsigned long addr,
> + unsigned pdshift, unsigned long end,
> + int write, struct page **pages, int *nr)
> +{
> + return 0;
> +}
> +#else
> +extern int gup_hugepd(hugepd_t hugepd, unsigned long addr,
> + unsigned pdshift, unsigned long end,
> + int write, struct page **pages, int *nr);
> +#endif
> +extern int gup_huge_pte(pte_t orig, pte_t *ptep, unsigned long addr,
> + unsigned long sz, unsigned long end, int write,
> + struct page **pages, int *nr);
> +#endif
> +
>
> ...
>
^ permalink raw reply
* Re: [PATCH 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan
From: Emil Medve @ 2014-10-22 20:05 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree@vger.kernel.org, Pawel Moll,
ijc+devicetree@hellion.org.uk, Geoff.Thorpe@freescale.com,
corbet@lwn.net, linux-doc@vger.kernel.org,
linuxppc-dev@ozlabs.org, robh+dt@kernel.org, galak@codeaurora.org,
scottwood@freescale.com
In-Reply-To: <20141022143732.GB4010@leverpostej>
Hello Mark,
On 10/22/2014 09:37 AM, Mark Rutland wrote:
> On Wed, Oct 22, 2014 at 03:09:31PM +0100, Emil Medve wrote:
>> The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA).
>> QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces
>> and DPAA logic modules, maintains packet ordering within flows. Besides
>> providing flow-level queuing, is also responsible for congestion management
>> functions such as RED/WRED, congestion notifications and tail discards. This
>> binding covers the CCSR space programming model
>>
>> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
>> Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b
>> ---
>> .../devicetree/bindings/powerpc/fsl/qman.txt | 134 +++++++++++++++++++++
>> 1 file changed, 134 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman.txt
>>
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
>> new file mode 100644
>> index 0000000..b9f288f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
>> @@ -0,0 +1,134 @@
>> +QorIQ DPAA Queue Manager Device Tree Binding
>> +
>> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
>> +
>> +CONTENTS
>> +
>> + - QMan Node
>> + - QMan Private Memory Nodes
>> + - Example
>> +
>> +NOTE: The bindings described in this document are preliminary and subject to
>> + change
>
> As with the BMan portal binding, I'm rather uncomfortable with a
> preliminary binding.
Ditto
>> +
>> +QMan Node
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: Required
>> + Value type: <stringlist>
>> + Definition: Must include "fsl,qman"
>> + May include "fsl,<SoC>-qman"
>> +
>> +- reg
>> + Usage: Required
>> + Value type: <prop-encoded-array>
>> + Definition: Registers region within the CCSR address space
>> +
>> +- fsl,liodn
>> + Usage: See pamu.txt
>> + Value type: <prop-encoded-array>
>> + Definition: PAMU property used for static LIODN assignment
>> +
>> +- fsl,iommu-parent
>> + Usage: See pamu.txt
>> + Value type: <phandle>
>> + Definition: PAMU property used for dynamic LIODN assignment
>> +
>> + For additional details about the PAMU/LIODN binding(s) see pamu.txt
>
> This is not present in the example. Is this always required?
Sort of. Initial hardware (and current documentation) programming
suggestion was to configure all the PAMU instances the same way
regardless of what devices were behind them. Given the PAMU internal
caches sizes, this proved suboptimal from a performance perspective so
we're trying to discover/describe/use the PAMU topology
fsl,liodn is part of the undocumented static LIODN assignment binding
that the current PAMU driver uses. If fsl,iommu-parent is present,
fsl,liodn can be ignored and the LIODN can be assigned dynamically
and/or programmed only in the relevant PAMU instance
>> +
>> +- clocks
>> + Usage: See clock-bindings.txt and qoriq-clock.txt
>> + Value type: <prop-encoded-array>
>> + Definition: Half of the platform clock
>> +
>
> I don't understand the description here. What is the clock from the PoV
> of the QMan? Which input line on the QMan is this clock attached to?
>
> Is there only one clock input? Or jsut one that you need to manage at
> the moment?
As part of the programming model (QoS features specifically) QMan needs
to know its clock speed. Prior to the existence of the
clock-bindings.txt, a "static" clock-frequency property was/is used
convey such information. Using clock-binding.txt to describe the
clocking hierarchy in the SoC makes it easier with DFS, power
management, etc.
The platform clock/PLL binding is part of qoriq-clock.txt
> You also seem to have an interrupt in the example. How many do you
> expect, and what are their their logical functions?
That's the error interrupt and hopefully it never triggers. I didn't add
[many] words about it as it's a standard property
>> +QMan Private Memory Nodes
>> +
>> +QMan requires two contiguous range of physical memory used for the backing store
>> +for QMan Frame Queue Descriptor and Packed Frame Descriptor Record. This memory
>> +is reserved/allocated as a nodes under the /reserved-memory node
>> +
>> +The QMan FQD memory node must be named "qman-fqd"
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Must inclide "fsl,qman-fqd"
>> +
>> +The QMan PFDR memory node must be named "qman-pfdr"
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Must inclide "fsl,qman-pfdr"
>> +
>> +The following constraints are relevant to the FQD and PFDR private memory:
>> + - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
>> + 1 GiB
>> + - The alignment must be a muliptle of the memory size
>> +
>> +The size of the FQD and PFDP must be chosen by observing the hardware features
>> +configured via the RCW and that are relevant to a specific board (e.g. number of
>> +MAC(s) pinned-out, number of offline/host command FMan ports, etc.). The size
>> +configured in the DT must reflect the hardware capabilities and not the specific
>> +needs of an application
>> +
>> +If the memory reserved in the device tree proves to be larger then the needs of
>> +the application a QMan driver may provide a method to release the extra memory
>> +back to the OS
>
> Driver details should be unimportant to the binding. This sentence can
> disappear.
I'm trying to discourage reserved-memory nodes to be used to "optimize"
the memory allocation/usage. If it comes to it, I can drop this sentence
Cheers,
> Thanks,
> Mark.
>
>> +
>> +For additional details about reserved memory regions see reserved-memory.txt
>> +
>> +EXAMPLE
>> +
>> +The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + qman-fqd {
>> + compatible = "fsl,qman-fqd";
>> + alloc-ranges = <0 0 0xf 0xffffffff>;
>> + size = <0 0x400000>;
>> + alignment = <0 0x400000>;
>> + };
>> + qman-pfdr {
>> + compatible = "fsl,qman-pfdr";
>> + alloc-ranges = <0 0 0xf 0xffffffff>;
>> + size = <0 0x2000000>;
>> + alignment = <0 0x2000000>;
>> + };
>> + };
>> +
>> +The example below shows a (P4080) QMan CCSR-space node
>> +
>> + clockgen: global-utilities@e1000 {
>> + ...
>> + sysclk: sysclk {
>> + ...
>> + };
>> + ...
>> + platform-pll: platform-pll@c00 {
>> + #clock-cells = <1>;
>> + reg = <0xc00 0x4>;
>> + compatible = "fsl,qoriq-platform-pll-1.0";
>> + clocks = <&sysclk>;
>> + clock-output-names = "platform-pll", "platform-pll-div2";
>> + };
>> + ...
>> + };
>> +
>> + qman@318000 {
>> + compatible = "fsl,qman";
>> + reg = <0x318000 0x1000>;
>> + interrupts = <16 2 1 3>
>> + fsl,liodn = <0x16>;
>> + clocks = <&platform-pll 1>;
>> + };
>> --
>> 2.1.2
^ permalink raw reply
* Re: [PATCH 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
From: Emil Medve @ 2014-10-22 20:04 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree@vger.kernel.org, Pawel Moll,
ijc+devicetree@hellion.org.uk, Geoff.Thorpe@freescale.com,
corbet@lwn.net, linux-doc@vger.kernel.org,
linuxppc-dev@ozlabs.org, robh+dt@kernel.org, galak@codeaurora.org,
scottwood@freescale.com
In-Reply-To: <20141022142931.GA4010@leverpostej>
Hello Mark,
Thanks for having a look at this
On 10/22/2014 09:29 AM, Mark Rutland wrote:
> On Wed, Oct 22, 2014 at 03:09:30PM +0100, Emil Medve wrote:
>> Portals are used by software running on processor cores, accelerators and
>> network interfaces to communicate with the BMan
>
> What exactly is a portal?
>
> Is it a region of shared memory? A device?
In a nutshell a (software, i.e. processor core accessible) portal is a
memory mapped interface to the B/QMan that allows low latency, lock-less
interaction by logically separated units of software. The original
intent was to have one affine portal per core. As of now we're
sprinkling portals to use from various (core affine) contexts:
hypervisor, guests, user-space, containers, etc.
I'll make the definition more palatable in the next round
> I only received emails 2 and 3 of this series, so I'm lacking the
> context necessary to understand the bindings.
Some bubble in the pipe... As of now they all seem to have hit the
e-mail list(s), patchwork and hopefully your Inbox
>> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
>> Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95
>> ---
>> .../bindings/powerpc/fsl/bman-portals.txt | 50 ++++++++++++++++++++++
>> 1 file changed, 50 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>>
>> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>> new file mode 100644
>> index 0000000..40e607e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
>> @@ -0,0 +1,50 @@
>> +QorIQ DPAA Buffer Manager Portals Device Tree Binding
>> +
>> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
>> +
>> +CONTENTS
>> +
>> + - BMan Portal
>> + - Example
>> +
>> +NOTE: The bindings described in this document are preliminary and subject to
>> + change
>
> While we've tried that elsewhere, unstable DT bindings have been shown
> to be a major source of pain.
Agreed
> I'd feel rather uncomfortable accepting a
> binding that we already believe to be insufficient to describe the
> hardware.
>
> What do you expect to change?
Related bindings seem incomplete. As such, the PAMU binding (pamu.txt)
covers incompletely a dynamic LIODN assignment/programming model. The
current driver uses a static assignment scheme that the binding needs to
include. I also suspect that once the driver starts supporting the
dynamic LIODN assignment/programming we might find some wrinkles
>> +
>> +BMan Portal Node
>> +
>> +PROPERTIES
>> +
>> +- compatible
>> + Usage: Required
>> + Value type: <stringlist>
>> + Definition: Must include "fsl,bman-portal-<hardware revision>"
>> + May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
>> +
>> +- reg
>> + Usage: Required
>> + Value type: <prop-encoded-array>
>> + Definition: Two regions. The first is the cache-enabled region of
>> + the portal. The second is the cache-inhibited region of
>> + the portal
>> +
>> +EXAMPLE
>> +
>> +The example below shows a (P4080) BMan portals container/bus node with two portals
>
> Is there any particular reason to place these under a simple-bus?
I think they fit the ePAPR definition for simple-bus container. They can
be accessed directly and can be used independently. What are you suggesting?
>> +
>> + bman-portals@ff4000000 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "simple-bus";
>> + ranges = <0 0xf 0xf4000000 0x200000>;
>> +
>> + bman-portal@0 {
>> + compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
>> + reg = <0x0 0x4000 0x100000 0x1000>;
>
> It would be easier to read is each entry had its own set of brackets.
> Initially this looked to me like a single 64-bit address/size pair.
Something like <>, <>? It doesn't seem widely used but I agree is more
readable. I can include it in the the next spin
>> + interrupts = <105 2 0 0>;
>> + };
>
> Given the description above, surely you need to know what the portal is
> used for? Or is that queried from the portal?
We don't need/want to include such information in the DT. Portals are
"allocated" dynamically and used by the respective context
Cheers,
> Thanks,
> Mark.
>
>> + bman-portal@4000 {
>> + compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
>> + reg = <0x4000 0x4000 0x101000 0x1000>;
>> + interrupts = <107 2 0 0>;
>> + };
>> + };
>> --
>> 2.1.2
^ permalink raw reply
* Re: [PATCH] net: fs_enet: set back promiscuity mode after restart
From: David Miller @ 2014-10-22 19:33 UTC (permalink / raw)
To: christophe.leroy
Cc: netdev, linux-kernel, vbordug, linuxppc-dev, germain.montoies
In-Reply-To: <20141022070547.83AAB1A5E63@localhost.localdomain>
From: Christophe Leroy <christophe.leroy@c-s.fr>
Date: Wed, 22 Oct 2014 09:05:47 +0200 (CEST)
> After interface restart (eg: after link disconnection/reconnection), the bridge
> function doesn't work anymore. This is due to the promiscuous mode being cleared
> by the restart.
>
> The mac-fcc already includes code to set the promiscuous mode back during the restart.
> This patch adds the same handling to mac-fec and mac-scc.
>
> Tested with bridge function on MPC885 with FEC.
>
> Reported-by: Germain Montoies <germain.montoies@c-s.fr>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH] powerpc: Convert power off logic to pm_power_off
From: Guenter Roeck @ 2014-10-22 4:48 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, agraf
In-Reply-To: <1413952677-31662-1-git-send-email-mpe@ellerman.id.au>
On 10/21/2014 09:37 PM, Michael Ellerman wrote:
> The generic Linux framework to power off the machine is a function pointer
> called pm_power_off. The trick about this pointer is that device drivers can
> potentially implement it rather than board files.
>
> Today on powerpc we set pm_power_off to invoke our generic full machine power
> off logic which then calls ppc_md.power_off to invoke machine specific power
> off.
>
> However, when we want to add a power off GPIO via the "gpio-poweroff" driver,
> this card house falls apart. That driver only registers itself if pm_power_off
> is NULL to ensure it doesn't override board specific logic. However, since we
> always set pm_power_off to the generic power off logic (which will just not
> power off the machine if no ppc_md.power_off call is implemented), we can't
> implement power off via the generic GPIO power off driver.
>
> To fix this up, let's get rid of the ppc_md.power_off logic and just always use
> pm_power_off as was intended. Then individual drivers such as the GPIO power off
> driver can implement power off logic via that function pointer.
>
> With this patch set applied and a few patches on top of QEMU that implement a
> power off GPIO on the virt e500 machine, I can successfully turn off my virtual
> machine after halt.
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> [mpe: Squash into one patch and update changelog based on cover letter]
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
> ---
> arch/powerpc/include/asm/machdep.h | 1 -
> arch/powerpc/kernel/setup-common.c | 6 +--
> arch/powerpc/platforms/44x/ppc476.c | 2 +-
> arch/powerpc/platforms/52xx/efika.c | 3 +-
> arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 8 ++--
> arch/powerpc/platforms/85xx/corenet_generic.c | 2 +-
> arch/powerpc/platforms/85xx/sgy_cts1000.c | 4 +-
> arch/powerpc/platforms/cell/celleb_setup.c | 4 +-
> arch/powerpc/platforms/cell/qpace_setup.c | 2 +-
> arch/powerpc/platforms/cell/setup.c | 2 +-
> arch/powerpc/platforms/chrp/setup.c | 3 +-
> arch/powerpc/platforms/embedded6xx/gamecube.c | 3 +-
> arch/powerpc/platforms/embedded6xx/linkstation.c | 4 +-
> arch/powerpc/platforms/embedded6xx/wii.c | 3 +-
> arch/powerpc/platforms/maple/setup.c | 4 +-
> arch/powerpc/platforms/powermac/setup.c | 3 +-
> arch/powerpc/platforms/powernv/setup.c | 4 +-
> arch/powerpc/platforms/ps3/setup.c | 2 +-
> arch/powerpc/platforms/pseries/setup.c | 59 ++++++++++++------------
> arch/powerpc/sysdev/fsl_soc.c | 2 +-
> arch/powerpc/xmon/xmon.c | 3 +-
> 21 files changed, 66 insertions(+), 58 deletions(-)
>
>
> Hi guys, how does this look?
>
> If it's OK I'll put it in a topic branch for Guenter.
>
Looks good to me.
Guenter
^ permalink raw reply
* [PATCH v3 30/59] dmaengine: fsl-dma: Split device_control
From: Maxime Ripard @ 2014-10-22 15:43 UTC (permalink / raw)
To: dmaengine, Vinod Koul
Cc: lars, Russell King, linux-kernel, Zhang Wei, Laurent Pinchart,
Maxime Ripard, linuxppc-dev, Dan Williams, linux-arm-kernel,
Antoine Ténart
In-Reply-To: <1413992653-21963-1-git-send-email-maxime.ripard@free-electrons.com>
Split the device_control callback of the Freescale Elo DMA driver to make use
of the newly introduced callbacks, that will eventually be used to retrieve
slave capabilities.
While we're at it, remove the useless prep_sg callback.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/dma/fsldma.c | 91 ++++++++++++++++++----------------------------------
1 file changed, 32 insertions(+), 59 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 994bcb2c6b92..4b557643a737 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -941,37 +941,8 @@ fail:
return NULL;
}
-/**
- * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
- * @chan: DMA channel
- * @sgl: scatterlist to transfer to/from
- * @sg_len: number of entries in @scatterlist
- * @direction: DMA direction
- * @flags: DMAEngine flags
- * @context: transaction context (ignored)
- *
- * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
- * DMA_SLAVE API, this gets the device-specific information from the
- * chan->private variable.
- */
-static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
- struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
- enum dma_transfer_direction direction, unsigned long flags,
- void *context)
-{
- /*
- * This operation is not supported on the Freescale DMA controller
- *
- * However, we need to provide the function pointer to allow the
- * device_control() method to work.
- */
- return NULL;
-}
-
-static int fsl_dma_device_control(struct dma_chan *dchan,
- enum dma_ctrl_cmd cmd, unsigned long arg)
+static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
{
- struct dma_slave_config *config;
struct fsldma_chan *chan;
int size;
@@ -980,45 +951,47 @@ static int fsl_dma_device_control(struct dma_chan *dchan,
chan = to_fsl_chan(dchan);
- switch (cmd) {
- case DMA_TERMINATE_ALL:
- spin_lock_bh(&chan->desc_lock);
-
- /* Halt the DMA engine */
- dma_halt(chan);
+ spin_lock_bh(&chan->desc_lock);
- /* Remove and free all of the descriptors in the LD queue */
- fsldma_free_desc_list(chan, &chan->ld_pending);
- fsldma_free_desc_list(chan, &chan->ld_running);
- fsldma_free_desc_list(chan, &chan->ld_completed);
- chan->idle = true;
+ /* Halt the DMA engine */
+ dma_halt(chan);
- spin_unlock_bh(&chan->desc_lock);
- return 0;
+ /* Remove and free all of the descriptors in the LD queue */
+ fsldma_free_desc_list(chan, &chan->ld_pending);
+ fsldma_free_desc_list(chan, &chan->ld_running);
+ fsldma_free_desc_list(chan, &chan->ld_completed);
+ chan->idle = true;
- case DMA_SLAVE_CONFIG:
- config = (struct dma_slave_config *)arg;
+ spin_unlock_bh(&chan->desc_lock);
+ return 0;
+}
- /* make sure the channel supports setting burst size */
- if (!chan->set_request_count)
- return -ENXIO;
+static int fsl_dma_device_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct fsldma_chan *chan;
+ int size;
- /* we set the controller burst size depending on direction */
- if (config->direction == DMA_MEM_TO_DEV)
- size = config->dst_addr_width * config->dst_maxburst;
- else
- size = config->src_addr_width * config->src_maxburst;
+ if (!dchan)
+ return -EINVAL;
- chan->set_request_count(chan, size);
- return 0;
+ chan = to_fsl_chan(dchan);
- default:
+ /* make sure the channel supports setting burst size */
+ if (!chan->set_request_count)
return -ENXIO;
- }
+ /* we set the controller burst size depending on direction */
+ if (config->direction == DMA_MEM_TO_DEV)
+ size = config->dst_addr_width * config->dst_maxburst;
+ else
+ size = config->src_addr_width * config->src_maxburst;
+
+ chan->set_request_count(chan, size);
return 0;
}
+
/**
* fsl_dma_memcpy_issue_pending - Issue the DMA start command
* @chan : Freescale DMA channel
@@ -1396,8 +1369,8 @@ static int fsldma_of_probe(struct platform_device *op)
fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
fdev->common.device_tx_status = fsl_tx_status;
fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
- fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
- fdev->common.device_control = fsl_dma_device_control;
+ fdev->common.device_config = fsl_dma_device_config;
+ fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
fdev->common.dev = &op->dev;
dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
--
2.1.1
^ permalink raw reply related
* Re: [PATCH v2 08/47] kernel: Move pm_power_off to common code
From: Guenter Roeck @ 2014-10-22 15:43 UTC (permalink / raw)
To: Ralf Baechle
Cc: linux-mips, linux-m68k, linux-ia64, linux-sh, linux, sparclinux,
linux-s390, linux-am33-list, linux-c6x-dev, linux-hexagon, x86,
xen-devel, linux-xtensa, user-mode-linux-devel, linux-pm,
adi-buildroot-devel, user-mode-linux-user, linux-metag,
linux-arm-kernel, linux-parisc, linux-cris-kernel, linux-kernel,
linux-alpha, linux390, linuxppc-dev
In-Reply-To: <20141022153136.GA11045@linux-mips.org>
On Wed, Oct 22, 2014 at 05:31:36PM +0200, Ralf Baechle wrote:
> On Mon, Oct 20, 2014 at 09:12:24PM -0700, Guenter Roeck wrote:
>
> > pm_power_off is defined for all architectures. Move it to common code.
> >
> > Have all architectures call do_kernel_power_off instead of pm_power_off.
> > Some architectures point pm_power_off to machine_power_off. For those,
> > call do_kernel_power_off from machine_power_off instead.
> >
> > Acked-by: David Vrabel <david.vrabel@citrix.com>
> > Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
> > Acked-by: Hirokazu Takata <takata@linux-m32r.org>
> > Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
> > Acked-by: Max Filippov <jcmvbkbc@gmail.com>
> > Acked-by: Rafael J. Wysocki <rjw@rjwysocki.net>
> > Acked-by: Richard Weinberger <richard@nod.at>
> > Acked-by: Xuetao Guan <gxt@mprc.pku.edu.cn>
> > Signed-off-by: Guenter Roeck <linux@roeck-us.net>
>
> Acked-by: Ralf Baechle <ralf@linux-mips.org>
Thanks!
Guenter
^ permalink raw reply
* Re: [PATCH v2 08/47] kernel: Move pm_power_off to common code
From: Ralf Baechle @ 2014-10-22 15:31 UTC (permalink / raw)
To: Guenter Roeck
Cc: linux-mips, linux-m68k, linux-ia64, linux-sh, linux, sparclinux,
linux-s390, linux-am33-list, linux-c6x-dev, linux-hexagon, x86,
xen-devel, linux-xtensa, user-mode-linux-devel, linux-pm,
adi-buildroot-devel, user-mode-linux-user, linux-metag,
linux-arm-kernel, linux-parisc, linux-cris-kernel, linux-kernel,
linux-alpha, linux390, linuxppc-dev
In-Reply-To: <1413864783-3271-9-git-send-email-linux@roeck-us.net>
On Mon, Oct 20, 2014 at 09:12:24PM -0700, Guenter Roeck wrote:
> pm_power_off is defined for all architectures. Move it to common code.
>
> Have all architectures call do_kernel_power_off instead of pm_power_off.
> Some architectures point pm_power_off to machine_power_off. For those,
> call do_kernel_power_off from machine_power_off instead.
>
> Acked-by: David Vrabel <david.vrabel@citrix.com>
> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Acked-by: Hirokazu Takata <takata@linux-m32r.org>
> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
> Acked-by: Max Filippov <jcmvbkbc@gmail.com>
> Acked-by: Rafael J. Wysocki <rjw@rjwysocki.net>
> Acked-by: Richard Weinberger <richard@nod.at>
> Acked-by: Xuetao Guan <gxt@mprc.pku.edu.cn>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
^ permalink raw reply
* [PATCH 2/3] dt/bindings: qoriq-clock: Add binding for the platform PLL
From: Emil Medve @ 2014-10-22 14:42 UTC (permalink / raw)
To: scottwood, yuantian.tang, linuxppc-dev, devicetree; +Cc: Emil Medve
In-Reply-To: <1413988937-27885-1-git-send-email-Emilian.Medve@Freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I7950afa9650d15ec7ce2cca89bb2a1e38586d4a5
---
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 5666812..407fb01 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -62,6 +62,8 @@ Required properties:
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
+ * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
+ * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
@@ -94,7 +96,6 @@ Example for clock block and clock provider:
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
-
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
@@ -102,7 +103,6 @@ Example for clock block and clock provider:
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
-
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
@@ -110,7 +110,6 @@ Example for clock block and clock provider:
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
-
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
@@ -119,7 +118,6 @@ Example for clock block and clock provider:
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
-
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
@@ -128,8 +126,15 @@ Example for clock block and clock provider:
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
+ platform-pll: platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
};
- }
+};
Example for clock consumer:
@@ -139,4 +144,4 @@ Example for clock consumer:
clocks = <&mux0>;
...
};
- }
+};
--
2.1.2
^ permalink raw reply related
* [PATCH 1/3] powerpc/dts: Factorize the clock control node
From: Emil Medve @ 2014-10-22 14:42 UTC (permalink / raw)
To: scottwood, yuantian.tang, linuxppc-dev, devicetree; +Cc: Emil Medve
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
---
arch/powerpc/boot/dts/b4860emu.dts | 4 +-
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 28 +--------
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 28 +--------
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 49 +---------------
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 49 +---------------
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 55 +-----------------
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 48 +---------------
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 49 +---------------
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 78 ++++++++++++++++++++++++++
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 61 ++++++++++++++++++++
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 33 +----------
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 30 +---------
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 34 +----------
arch/powerpc/boot/dts/t4240emu.dts | 4 +-
14 files changed, 163 insertions(+), 387 deletions(-)
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
index 85646b4..2aa5cd3 100644
--- a/arch/powerpc/boot/dts/b4860emu.dts
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -193,9 +193,9 @@
fsl,liodn-bits = <12>;
};
- clockgen: global-utilities@e1000 {
+/include/ "fsl/qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
- reg = <0xe1000 0x1000>;
};
/include/ "fsl/qoriq-dma-0.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index b34c62e..aced374 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -80,33 +80,9 @@
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
mux0: mux0@0 {
#clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 256fac8..3b9bb37 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -273,33 +273,9 @@
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
mux0: mux0@0 {
#clock-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index f297514..6edacf3 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -313,53 +313,9 @@
#sleep-cells = <2>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
mux2: mux2@40 {
#clock-cells = <0>;
@@ -369,7 +325,6 @@
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
-
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index b3f89ce..cce28f9 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -340,53 +340,9 @@
#sleep-cells = <2>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
mux2: mux2@40 {
#clock-cells = <0>;
@@ -396,7 +352,6 @@
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
-
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index e410b15..9998b99 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -360,35 +360,9 @@
#sleep-cells = <2>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
pll2: pll2@840 {
#clock-cells = <1>;
@@ -397,7 +371,6 @@
clocks = <&sysclk>;
clock-output-names = "pll2", "pll2-div2";
};
-
pll3: pll3@860 {
#clock-cells = <1>;
reg = <0x860 0x4>;
@@ -405,25 +378,6 @@
clocks = <&sysclk>;
clock-output-names = "pll3", "pll3-div2";
};
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
-
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
@@ -432,7 +386,6 @@
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
-
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
@@ -441,7 +394,6 @@
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux3";
};
-
mux4: mux4@80 {
#clock-cells = <0>;
reg = <0x80 0x4>;
@@ -450,7 +402,6 @@
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux4";
};
-
mux5: mux5@a0 {
#clock-cells = <0>;
reg = <0xa0 0x4>;
@@ -459,7 +410,6 @@
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux5";
};
-
mux6: mux6@c0 {
#clock-cells = <0>;
reg = <0xc0 0x4>;
@@ -468,7 +418,6 @@
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux6";
};
-
mux7: mux7@e0 {
#clock-cells = <0>;
reg = <0xe0 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index d07c771..b70c8c3 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -345,53 +345,9 @@
#sleep-cells = <2>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 243574b..663c48b 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -305,53 +305,9 @@
#sleep-cells = <2>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen1.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
mux2: mux2@40 {
#clock-cells = <0>;
@@ -361,7 +317,6 @@
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
-
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
new file mode 100644
index 0000000..4871048
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -0,0 +1,78 @@
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+global-utilities@e1000 {
+ compatible = "fsl,qoriq-clockgen-1.0";
+ ranges = <0x0 0xe1000 0x1000>;
+ reg = <0xe1000 0x1000>;
+ clock-frequency = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ };
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2";
+ };
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2";
+ };
+ mux0: mux0@0 {
+ #clock-cells = <0>;
+ reg = <0x0 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+ clock-output-names = "cmux0";
+ };
+ mux1: mux1@20 {
+ #clock-cells = <0>;
+ reg = <0x20 0x4>;
+ compatible = "fsl,qoriq-core-mux-1.0";
+ clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
+ clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
+ clock-output-names = "cmux1";
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
new file mode 100644
index 0000000..5d18d2a
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -0,0 +1,61 @@
+/*
+ * QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
+ *
+ * Copyright 2014 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Freescale Semiconductor nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+global-utilities@e1000 {
+ compatible = "fsl,qoriq-clockgen-2.0";
+ ranges = <0x0 0xe1000 0x1000>;
+ reg = <0xe1000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysclk: sysclk {
+ #clock-cells = <0>;
+ compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
+ clock-output-names = "sysclk";
+ };
+ pll0: pll0@800 {
+ #clock-cells = <1>;
+ reg = <0x800 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll0", "pll0-div2", "pll0-div4";
+ };
+ pll1: pll1@820 {
+ #clock-cells = <1>;
+ reg = <0x820 0x4>;
+ compatible = "fsl,qoriq-core-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "pll1", "pll1-div2", "pll1-div4";
+ };
+};
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index e989b6a..e9a81ac 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -432,35 +432,9 @@
fsl,liodn-bits = <12>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0";
- clock-output-names = "sysclk", "fixed-clock";
- };
-
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
mux0: mux0@0 {
#clock-cells = <0>;
@@ -472,7 +446,6 @@
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux0";
};
-
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
@@ -483,7 +456,6 @@
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux1";
};
-
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 4>;
@@ -494,7 +466,6 @@
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux2";
};
-
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 4>;
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index dfbe499..72377c5 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -553,34 +553,9 @@
fsl,liodn-bits = <12>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0";
- clock-output-names = "sysclk", "fixed-clock";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
mux0: mux0@0 {
#clock-cells = <0>;
@@ -592,7 +567,6 @@
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux0";
};
-
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index d2ecd86..ec373b3 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -1032,34 +1032,9 @@
fsl,liodn-bits = <12>;
};
- clockgen: global-utilities@e1000 {
+/include/ "qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
pll2: pll2@840 {
#clock-cells = <1>;
@@ -1068,7 +1043,6 @@
clocks = <&sysclk>;
clock-output-names = "pll2", "pll2-div2", "pll2-div4";
};
-
pll3: pll3@860 {
#clock-cells = <1>;
reg = <0x860 0x4>;
@@ -1076,7 +1050,6 @@
clocks = <&sysclk>;
clock-output-names = "pll3", "pll3-div2", "pll3-div4";
};
-
pll4: pll4@880 {
#clock-cells = <1>;
reg = <0x880 0x4>;
@@ -1084,7 +1057,6 @@
clocks = <&sysclk>;
clock-output-names = "pll4", "pll4-div2", "pll4-div4";
};
-
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
@@ -1097,7 +1069,6 @@
"pll2", "pll2-div2", "pll2-div4";
clock-output-names = "cmux0";
};
-
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
@@ -1110,7 +1081,6 @@
"pll2", "pll2-div2", "pll2-div4";
clock-output-names = "cmux1";
};
-
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
index bc12127a..decaf35 100644
--- a/arch/powerpc/boot/dts/t4240emu.dts
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -250,9 +250,9 @@
fsl,liodn-bits = <12>;
};
- clockgen: global-utilities@e1000 {
+/include/ "fsl/qoriq-clockgen2.dtsi"
+ global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
- reg = <0xe1000 0x1000>;
};
/include/ "fsl/qoriq-dma-0.dtsi"
--
2.1.2
^ permalink raw reply related
* [PATCH 2/4] dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
From: Emil Medve @ 2014-10-22 14:09 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, Geoff.Thorpe, linuxppc-dev, devicetree,
linux-doc
Cc: Emil Medve
In-Reply-To: <1413986972-621-1-git-send-email-Emilian.Medve@Freescale.com>
Portals are used by software running on processor cores, accelerators and
network interfaces to communicate with the BMan
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95
---
.../bindings/powerpc/fsl/bman-portals.txt | 50 ++++++++++++++++++++++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
new file mode 100644
index 0000000..40e607e
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/bman-portals.txt
@@ -0,0 +1,50 @@
+QorIQ DPAA Buffer Manager Portals Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - BMan Portal
+ - Example
+
+NOTE: The bindings described in this document are preliminary and subject to
+ change
+
+BMan Portal Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,bman-portal-<hardware revision>"
+ May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Two regions. The first is the cache-enabled region of
+ the portal. The second is the cache-inhibited region of
+ the portal
+
+EXAMPLE
+
+The example below shows a (P4080) BMan portals container/bus node with two portals
+
+ bman-portals@ff4000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0xf 0xf4000000 0x200000>;
+
+ bman-portal@0 {
+ compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
+ reg = <0x0 0x4000 0x100000 0x1000>;
+ interrupts = <105 2 0 0>;
+ };
+ bman-portal@4000 {
+ compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <107 2 0 0>;
+ };
+ };
--
2.1.2
^ permalink raw reply related
* [PATCH 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan
From: Emil Medve @ 2014-10-22 14:09 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, Geoff.Thorpe, linuxppc-dev, devicetree,
linux-doc
Cc: Emil Medve
In-Reply-To: <1413986972-621-1-git-send-email-Emilian.Medve@Freescale.com>
The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA).
QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces
and DPAA logic modules, maintains packet ordering within flows. Besides
providing flow-level queuing, is also responsible for congestion management
functions such as RED/WRED, congestion notifications and tail discards. This
binding covers the CCSR space programming model
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b
---
.../devicetree/bindings/powerpc/fsl/qman.txt | 134 +++++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
new file mode 100644
index 0000000..b9f288f
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
@@ -0,0 +1,134 @@
+QorIQ DPAA Queue Manager Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - QMan Node
+ - QMan Private Memory Nodes
+ - Example
+
+NOTE: The bindings described in this document are preliminary and subject to
+ change
+
+QMan Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman"
+ May include "fsl,<SoC>-qman"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Registers region within the CCSR address space
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment
+
+ For additional details about the PAMU/LIODN binding(s) see pamu.txt
+
+- clocks
+ Usage: See clock-bindings.txt and qoriq-clock.txt
+ Value type: <prop-encoded-array>
+ Definition: Half of the platform clock
+
+QMan Private Memory Nodes
+
+QMan requires two contiguous range of physical memory used for the backing store
+for QMan Frame Queue Descriptor and Packed Frame Descriptor Record. This memory
+is reserved/allocated as a nodes under the /reserved-memory node
+
+The QMan FQD memory node must be named "qman-fqd"
+
+PROPERTIES
+
+- compatible
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must inclide "fsl,qman-fqd"
+
+The QMan PFDR memory node must be named "qman-pfdr"
+
+PROPERTIES
+
+- compatible
+ Usage: required
+ Value type: <stringlist>
+ Definition: Must inclide "fsl,qman-pfdr"
+
+The following constraints are relevant to the FQD and PFDR private memory:
+ - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
+ 1 GiB
+ - The alignment must be a muliptle of the memory size
+
+The size of the FQD and PFDP must be chosen by observing the hardware features
+configured via the RCW and that are relevant to a specific board (e.g. number of
+MAC(s) pinned-out, number of offline/host command FMan ports, etc.). The size
+configured in the DT must reflect the hardware capabilities and not the specific
+needs of an application
+
+If the memory reserved in the device tree proves to be larger then the needs of
+the application a QMan driver may provide a method to release the extra memory
+back to the OS
+
+For additional details about reserved memory regions see reserved-memory.txt
+
+EXAMPLE
+
+The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ qman-fqd {
+ compatible = "fsl,qman-fqd";
+ alloc-ranges = <0 0 0xf 0xffffffff>;
+ size = <0 0x400000>;
+ alignment = <0 0x400000>;
+ };
+ qman-pfdr {
+ compatible = "fsl,qman-pfdr";
+ alloc-ranges = <0 0 0xf 0xffffffff>;
+ size = <0 0x2000000>;
+ alignment = <0 0x2000000>;
+ };
+ };
+
+The example below shows a (P4080) QMan CCSR-space node
+
+ clockgen: global-utilities@e1000 {
+ ...
+ sysclk: sysclk {
+ ...
+ };
+ ...
+ platform-pll: platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
+ ...
+ };
+
+ qman@318000 {
+ compatible = "fsl,qman";
+ reg = <0x318000 0x1000>;
+ interrupts = <16 2 1 3>
+ fsl,liodn = <0x16>;
+ clocks = <&platform-pll 1>;
+ };
--
2.1.2
^ permalink raw reply related
* [PATCH 3/3] powerpc/dts: Add node(s) for the platform PLL
From: Emil Medve @ 2014-10-22 14:42 UTC (permalink / raw)
To: scottwood, yuantian.tang, linuxppc-dev, devicetree; +Cc: Emil Medve
In-Reply-To: <1413988937-27885-1-git-send-email-Emilian.Medve@Freescale.com>
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: If76cd705a01813abe53396c1486bc13c4289ee92
---
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 7 +++++++
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 7 +++++++
2 files changed, 14 insertions(+)
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
index 4871048..4ece1ed 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -75,4 +75,11 @@ global-utilities@e1000 {
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
+ platform_pll: platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-1.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
index 5d18d2a..48e0b6e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -58,4 +58,11 @@ global-utilities@e1000 {
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
+ platform_pll: platform-pll@c00 {
+ #clock-cells = <1>;
+ reg = <0xc00 0x4>;
+ compatible = "fsl,qoriq-platform-pll-2.0";
+ clocks = <&sysclk>;
+ clock-output-names = "platform-pll", "platform-pll-div2";
+ };
};
--
2.1.2
^ permalink raw reply related
* Re: [PATCH 3/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan
From: Mark Rutland @ 2014-10-22 14:37 UTC (permalink / raw)
To: Emil Medve
Cc: devicetree@vger.kernel.org, Pawel Moll,
ijc+devicetree@hellion.org.uk, Geoff.Thorpe@freescale.com,
corbet@lwn.net, linux-doc@vger.kernel.org,
linuxppc-dev@ozlabs.org, robh+dt@kernel.org, galak@codeaurora.org,
scottwood@freescale.com
In-Reply-To: <1413986972-621-3-git-send-email-Emilian.Medve@Freescale.com>
On Wed, Oct 22, 2014 at 03:09:31PM +0100, Emil Medve wrote:
> The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA).
> QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces
> and DPAA logic modules, maintains packet ordering within flows. Besides
> providing flow-level queuing, is also responsible for congestion management
> functions such as RED/WRED, congestion notifications and tail discards. This
> binding covers the CCSR space programming model
>
> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
> Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b
> ---
> .../devicetree/bindings/powerpc/fsl/qman.txt | 134 +++++++++++++++++++++
> 1 file changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman.txt
>
> diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
> new file mode 100644
> index 0000000..b9f288f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/powerpc/fsl/qman.txt
> @@ -0,0 +1,134 @@
> +QorIQ DPAA Queue Manager Device Tree Binding
> +
> +Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
> +
> +CONTENTS
> +
> + - QMan Node
> + - QMan Private Memory Nodes
> + - Example
> +
> +NOTE: The bindings described in this document are preliminary and subject to
> + change
As with the BMan portal binding, I'm rather uncomfortable with a
preliminary binding.
> +
> +QMan Node
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: Required
> + Value type: <stringlist>
> + Definition: Must include "fsl,qman"
> + May include "fsl,<SoC>-qman"
> +
> +- reg
> + Usage: Required
> + Value type: <prop-encoded-array>
> + Definition: Registers region within the CCSR address space
> +
> +- fsl,liodn
> + Usage: See pamu.txt
> + Value type: <prop-encoded-array>
> + Definition: PAMU property used for static LIODN assignment
> +
> +- fsl,iommu-parent
> + Usage: See pamu.txt
> + Value type: <phandle>
> + Definition: PAMU property used for dynamic LIODN assignment
> +
> + For additional details about the PAMU/LIODN binding(s) see pamu.txt
This is not present in the example. Is this always required?
> +
> +- clocks
> + Usage: See clock-bindings.txt and qoriq-clock.txt
> + Value type: <prop-encoded-array>
> + Definition: Half of the platform clock
> +
I don't understand the description here. What is the clock from the PoV
of the QMan? Which input line on the QMan is this clock attached to?
Is there only one clock input? Or jsut one that you need to manage at
the moment?
You also seem to have an interrupt in the example. How many do you
expect, and what are their their logical functions?
> +QMan Private Memory Nodes
> +
> +QMan requires two contiguous range of physical memory used for the backing store
> +for QMan Frame Queue Descriptor and Packed Frame Descriptor Record. This memory
> +is reserved/allocated as a nodes under the /reserved-memory node
> +
> +The QMan FQD memory node must be named "qman-fqd"
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: required
> + Value type: <stringlist>
> + Definition: Must inclide "fsl,qman-fqd"
> +
> +The QMan PFDR memory node must be named "qman-pfdr"
> +
> +PROPERTIES
> +
> +- compatible
> + Usage: required
> + Value type: <stringlist>
> + Definition: Must inclide "fsl,qman-pfdr"
> +
> +The following constraints are relevant to the FQD and PFDR private memory:
> + - The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
> + 1 GiB
> + - The alignment must be a muliptle of the memory size
> +
> +The size of the FQD and PFDP must be chosen by observing the hardware features
> +configured via the RCW and that are relevant to a specific board (e.g. number of
> +MAC(s) pinned-out, number of offline/host command FMan ports, etc.). The size
> +configured in the DT must reflect the hardware capabilities and not the specific
> +needs of an application
> +
> +If the memory reserved in the device tree proves to be larger then the needs of
> +the application a QMan driver may provide a method to release the extra memory
> +back to the OS
Driver details should be unimportant to the binding. This sentence can
disappear.
Thanks,
Mark.
> +
> +For additional details about reserved memory regions see reserved-memory.txt
> +
> +EXAMPLE
> +
> +The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + qman-fqd {
> + compatible = "fsl,qman-fqd";
> + alloc-ranges = <0 0 0xf 0xffffffff>;
> + size = <0 0x400000>;
> + alignment = <0 0x400000>;
> + };
> + qman-pfdr {
> + compatible = "fsl,qman-pfdr";
> + alloc-ranges = <0 0 0xf 0xffffffff>;
> + size = <0 0x2000000>;
> + alignment = <0 0x2000000>;
> + };
> + };
> +
> +The example below shows a (P4080) QMan CCSR-space node
> +
> + clockgen: global-utilities@e1000 {
> + ...
> + sysclk: sysclk {
> + ...
> + };
> + ...
> + platform-pll: platform-pll@c00 {
> + #clock-cells = <1>;
> + reg = <0xc00 0x4>;
> + compatible = "fsl,qoriq-platform-pll-1.0";
> + clocks = <&sysclk>;
> + clock-output-names = "platform-pll", "platform-pll-div2";
> + };
> + ...
> + };
> +
> + qman@318000 {
> + compatible = "fsl,qman";
> + reg = <0x318000 0x1000>;
> + interrupts = <16 2 1 3>
> + fsl,liodn = <0x16>;
> + clocks = <&platform-pll 1>;
> + };
> --
> 2.1.2
>
>
^ permalink raw reply
* [PATCH 4/4] dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s)
From: Emil Medve @ 2014-10-22 14:09 UTC (permalink / raw)
To: scottwood, galak, corbet, robh+dt, ijc+devicetree, galak,
pawel.moll, mark.rutland, Geoff.Thorpe, linuxppc-dev, devicetree,
linux-doc
Cc: Emil Medve
In-Reply-To: <1413986972-621-1-git-send-email-Emilian.Medve@Freescale.com>
Portals are used by software running on processor cores, accelerators and
network interfaces to communicate with the QMan
Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Change-Id: I29764fa8093b5ce65460abc879446795c50d7185
---
.../bindings/powerpc/fsl/qman-portals.txt | 151 +++++++++++++++++++++
1 file changed, 151 insertions(+)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt b/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
new file mode 100644
index 0000000..c4e1e98
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/qman-portals.txt
@@ -0,0 +1,151 @@
+QorIQ DPAA Queue Manager Portals Device Tree Binding
+
+Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
+
+CONTENTS
+
+ - QMan Portal
+ - QMan Pool Channel
+ - Example
+
+NOTE: The bindings described in this document are preliminary and subject to
+ change
+
+QMan Portal Node
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman-portal-<hardware revision>"
+ May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
+
+- reg
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: Two regions. The first is the cache-enabled region of
+ the portal. The second is the cache-inhibited region of
+ the portal
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment. This is
+ an optional property. It is a valid configuration for
+ this phandle to be dangling
+
+ For additional details about the PAMU/LIODN binding(s) see pamu.txt
+
+- fsl,qman-channel-id
+ Usage: Required
+ Value type: <u32>
+ Definition: The hardware index of the channel. This can also be
+ determined by dividing any of the channel's 8 work queue
+ IDs by 8
+
+In addition to these properties the qman-portals should have sub-nodes to
+represent the HW devices/portals that are connected to the software portal
+described here
+
+The currently support sub-nodes are:
+ * fman@0
+ * fman@1
+ * pme@0
+ * crypto@0
+
+These subnodes should have the following properties:
+
+- fsl,liodn
+ Usage: See pamu.txt
+ Value type: <prop-encoded-array>
+ Definition: PAMU property used for static LIODN assignment
+
+- fsl,iommu-parent
+ Usage: See pamu.txt
+ Value type: <phandle>
+ Definition: PAMU property used for dynamic LIODN assignment
+
+- dev-handle
+ Usage: Required
+ Value type: <phandle>
+ Definition: The phandle to the particular hardware device that this
+ portal is connected to.
+
+DPAA QMan Pool Channel Nodes
+
+Pool Channels are defined with the following properties.
+
+PROPERTIES
+
+- compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must include "fsl,qman-pool-channel"
+ May include "fsl,<SoC>-qman-pool-channel"
+
+- fsl,qman-channel-id
+ Usage: Required
+ Value type: <u32>
+ Definition: The hardware index of the channel. This can also be
+ determined by dividing any of the channel's 8 work queue
+ IDs by 8
+
+EXAMPLE
+
+The example below shows a (P4080) BMan portals container/bus node with two portals
+
+ qman-portals@ff4200000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0 0xf 0xf4200000 0x200000>;
+
+ qman-portal@0 {
+ cell-index = <0>;
+ compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
+ reg = <0 0x4000 0x100000 0x1000>;
+ interrupts = <104 2 0 0>;
+ fsl,liodn = <1 2>;
+ fsl,qman-channel-id = <0>;
+
+ fman@0 {
+ fsl,liodn = <0x21>;
+ dev-handle = <&fman0>;
+ };
+ fman@1 {
+ fsl,liodn = <0xa1>;
+ dev-handle = <&fman1>;
+ };
+ crypto@0 {
+ fsl,liodn = <0x41 0x66>;
+ dev-handle = <&crypto>;
+ };
+ };
+ qman-portal@4000 {
+ cell-index = <1>;
+ compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
+ reg = <0x4000 0x4000 0x101000 0x1000>;
+ interrupts = <106 2 0 0>;
+ fsl,liodn = <3 4>;
+ fsl,qman-channel-id = <1>;
+
+ fman@1 {
+ fsl,liodn = <0xa2>;
+ dev-handle = <&fman0>;
+ };
+ fman@0 {
+ fsl,liodn = <0x22>;
+ dev-handle = <&fman1>;
+ };
+ crypto@0 {
+ fsl,liodn = <0x42 0x67>;
+ dev-handle = <&crypto>;
+ };
+ };
+ };
--
2.1.2
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