* Re: powerpc/kdump: skip enabling big endian exception during crash
From: Mahesh Jagannath Salgaonkar @ 2014-12-12 4:06 UTC (permalink / raw)
To: Michael Ellerman, Hari Bathini, linuxppc-dev; +Cc: Anton Blanchard
In-Reply-To: <20141211224016.86E111400F1@ozlabs.org>
On 12/12/2014 04:10 AM, Michael Ellerman wrote:
> On Thu, 2014-11-12 at 16:44:54 UTC, Hari Bathini wrote:
>> In LE kernel, we currently have a hack for kexec that resets the exception endian
>> before starting a new kernel as the kernel that is loaded could be a big endian
>> or a little endian kernel. In kdump case, resetting exception endian fails when
>> one or more cpus is disabled. But in case of kdump, we can conveniently ignore
>> resetting endianess as crashkernel is always of same endianess as primary kernel.
>
> No, it's not guaranteed to be the same endianess.
>
> That tends to be what people do in practice, but it's not an assumption you can
> hard code.
Agree. The other solution could be to wakeup offline CPUs in crash path
as we do it in normal kexec path. PHYP expects all partitions processors
MSR[EE] = 0 while we call pseries_big_endian_exceptions(). Waking up
offline CPUs will help to achieve that. But since we are already in
crashed kernel context I am not sure how safe is to call
wake_offline_cpus().
Thanks,
-Mahesh.
^ permalink raw reply
* Re: powerpc/kdump: skip enabling big endian exception during crash
From: Michael Ellerman @ 2014-12-11 22:40 UTC (permalink / raw)
To: Hari Bathini, linuxppc-dev; +Cc: Mahesh J Salgaonkar
In-Reply-To: <20141211164454.4641.71441.stgit@localhost.localdomain>
On Thu, 2014-11-12 at 16:44:54 UTC, Hari Bathini wrote:
> In LE kernel, we currently have a hack for kexec that resets the exception endian
> before starting a new kernel as the kernel that is loaded could be a big endian
> or a little endian kernel. In kdump case, resetting exception endian fails when
> one or more cpus is disabled. But in case of kdump, we can conveniently ignore
> resetting endianess as crashkernel is always of same endianess as primary kernel.
No, it's not guaranteed to be the same endianess.
That tends to be what people do in practice, but it's not an assumption you can
hard code.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Print the M64 range information
From: Gavin Shan @ 2014-12-11 21:58 UTC (permalink / raw)
To: Wei Yang; +Cc: linuxppc-dev, Gavin Shan
In-Reply-To: <20141211072901.GA9598@richard>
On Thu, Dec 11, 2014 at 03:29:01PM +0800, Wei Yang wrote:
>On Thu, Dec 11, 2014 at 09:40:30AM +1100, Gavin Shan wrote:
>>On Wed, Dec 10, 2014 at 10:29:37PM +0800, Wei Yang wrote:
>>>The M64 range information is missed, which would be helpful in debug.
>>>
>>>This patch print the M64 range information in the same format as M32.
s/print/prints
>>>
>>>Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
>>>---
>>> arch/powerpc/platforms/powernv/pci-ioda.c | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>>diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
>>>index 21c8b4d..34f1a27 100644
>>>--- a/arch/powerpc/platforms/powernv/pci-ioda.c
>>>+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
>>>@@ -369,6 +369,9 @@ static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
>>> phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
>>> phb->ioda.m64_base = pci_addr;
>>>
>>>+ printk(KERN_INFO " MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
>>>+ res->start, res->end, pci_addr);
>>>+
>>
>>Please output segment size if you think it's helpful as well.
>
>The M64 segment size is printed in pnv_pci_init_ioda_phb() line 2620.
>
Yes, it has been printed separately. So the change looks good to me
after you replace "printk(KERN_INFO ...)" with pr_info. Could you please
send updated version and include following line if you want:
Reviewed-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Thanks,
Gavin
^ permalink raw reply
* [PATCH] powerpc/kdump: skip enabling big endian exception during crash
From: Hari Bathini @ 2014-12-11 16:44 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh J Salgaonkar
In LE kernel, we currently have a hack for kexec that resets the exception endian
before starting a new kernel as the kernel that is loaded could be a big endian
or a little endian kernel. In kdump case, resetting exception endian fails when
one or more cpus is disabled. But in case of kdump, we can conveniently ignore
resetting endianess as crashkernel is always of same endianess as primary kernel.
This patch adds a new inline function to say if this is kdump path. This function
is used at places where such a check is needed.
Signed-off-by: Hari Bathini <hbathini@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/kexec.h | 10 ++++++++++
arch/powerpc/kernel/machine_kexec_64.c | 2 +-
arch/powerpc/platforms/pseries/lpar.c | 7 ++++++-
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/kexec.h b/arch/powerpc/include/asm/kexec.h
index 19c36cb..0d96d4d 100644
--- a/arch/powerpc/include/asm/kexec.h
+++ b/arch/powerpc/include/asm/kexec.h
@@ -86,6 +86,11 @@ extern int overlaps_crashkernel(unsigned long start, unsigned long size);
extern void reserve_crashkernel(void);
extern void machine_kexec_mask_interrupts(void);
+static inline int is_kdump_path(void)
+{
+ return (crashing_cpu >= 0) ? 1 : 0;
+}
+
#else /* !CONFIG_KEXEC */
static inline void crash_kexec_secondary(struct pt_regs *regs) { }
@@ -106,6 +111,11 @@ static inline int crash_shutdown_unregister(crash_shutdown_t handler)
return 0;
}
+static inline int is_kdump_path(void)
+{
+ return 0;
+}
+
#endif /* CONFIG_KEXEC */
#endif /* ! __ASSEMBLY__ */
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
index 879b3aa..b4fe804 100644
--- a/arch/powerpc/kernel/machine_kexec_64.c
+++ b/arch/powerpc/kernel/machine_kexec_64.c
@@ -330,7 +330,7 @@ void default_machine_kexec(struct kimage *image)
* using debugger IPI.
*/
- if (crashing_cpu == -1)
+ if (!is_kdump_path())
kexec_prepare_cpus();
pr_debug("kexec: Starting switchover sequence.\n");
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index f6880d2..be41680 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -43,6 +43,7 @@
#include <asm/trace.h>
#include <asm/firmware.h>
#include <asm/plpar_wrappers.h>
+#include <asm/kexec.h>
#include <asm/fadump.h>
#include "pseries.h"
@@ -257,8 +258,12 @@ static void pSeries_lpar_hptab_clear(void)
*
* This is also called on boot when a fadump happens. In that case we
* must not change the exception endian mode.
+ *
+ * This is also called during kdump which doesn't need resetting, as the
+ * the crashkernel is of same endainess as primary kernel.
*/
- if (firmware_has_feature(FW_FEATURE_SET_MODE) && !is_fadump_active()) {
+ if (firmware_has_feature(FW_FEATURE_SET_MODE) && !is_fadump_active() &&
+ !is_kdump_path()) {
long rc;
rc = pseries_big_endian_exceptions();
^ permalink raw reply related
* Re: [PATCH] i2c-qoriq: modified compatibility for correct prescaler
From: Valentin Longchamp @ 2014-12-11 13:44 UTC (permalink / raw)
To: Scott Wood, Wolfram Sang
Cc: devicetree@vger.kernel.org, danielle.costantino, Boschung, Rainer,
Brunck, Holger, Linux I2C, Linux PowerPC Kernel
In-Reply-To: <1416966097.15957.171.camel@freescale.com>
Hi all,
Picking up this issue again.
On 11/26/2014 02:41 AM, Scott Wood wrote:
> On Tue, 2014-11-25 at 19:13 +0100, Wolfram Sang wrote:
>> On Mon, Nov 17, 2014 at 07:28:03PM -0600, Scott Wood wrote:
>>> On Fri, 2014-11-14 at 09:28 +0100, Wolfram Sang wrote:
>>>>>>
>>>>>> If we're going to change the device tree I'd rather just add a property
>>>>>> to say what the prescaler is.
>>>>>
>>>>> We would however, leave the boards' device trees that use things like
>>>>> "fsl,mpc8543-i2c" as is and introduce the prescaler for the others requiring it.
>>>>>
>>>>>
>>>>> Now the drawback is that the driver would require a change, to parse this
>>>>> prescaler new prescaler property. Would this be OK from your point of view
>>>>> Wolfram ? If yes, I will send the patches for it.
>>>>
>>>> I don't think it is OK.
>>>
>>> Why?
>>
>> Because I thought it could be deduced. Then, a seperate property would
>> not be OK.
>>
>>>> I'd think it can be deduced from the compatible property.
>>>
>>> For almost all existing device trees it cannot be.
>>
>> Pity :( If we do introduce a new property, it should probably be
>> "clock-div". Grepping through binding documentation, that seems
>> accepted. We should ask DT maintainers, too, to be safe.
>>
>>> If you want something that will work without changing device trees,
>>> you'll need to use SVR to identify the SoC.
>>
>> The driver is doing that already, see mpc_i2c_get_sec_cfg_8xxx(). Dunno
>> if it makes sense to add to it for consistency reasons?
>
> That's not SVR, but sure. Better to avoid messing with existing device
> trees.
>
What is then the agreement here ? Add a clock-div to the device trees ? Or do
something similar to mpc_i2c_get_sec_cfg_8xxx() ?
I think the clock-div property is better according to Freescale's AN 2919
section 3.1 Source clock. All the source clocks are fixed (with a clock-div of 2
in case of mpc8536/43/45/47/48/67/68/72, plus p2020) except for the mpc8533/44
where it can be 2 or 3, and that's what mpc_i2c_get_sec_cfg_8xxx() determines.
So mpc_i2c_get_sec_cfg_8xxx() should remain the exception and the other
prescaler values should be derived from an additional clock-div that must be
added in the respective device trees (at least for the qoriq devices, because
for instance mpc8543 already has the correct prescaler thanks to
mpc_i2c_data_8543 from i2c-mpc.c).
Valentin
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Remove pnv_pci_probe_mode()
From: Benjamin Herrenschmidt @ 2014-12-11 10:22 UTC (permalink / raw)
To: Gavin Shan; +Cc: linuxppc-dev
In-Reply-To: <1418277658-3541-1-git-send-email-gwshan@linux.vnet.ibm.com>
On Thu, 2014-12-11 at 17:00 +1100, Gavin Shan wrote:
> The callback (ppc_md.pci_probe_mode()) is used to determine if the
> child PCI devices of the indicated PCI bus should be probed from
> device-tree or hardware. On PowerNV platform, we always expect
> probing PCI devices from hardware, which is PowerPC PCI core's
> default behaviour. Also, the callback had some delay implemented
> based on PHB's device node property "reset-clear-timestamp", which
> wasn't exported from skiboot. So we don't need this function and
> it's safe to remove it.
Yes all that timestamp stuff was related to the old OPAL which is long
gone.
Cheers,
Ben.
> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/powernv/pci.c | 30 ------------------------------
> 1 file changed, 30 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
> index 4b20f2c..d346df2 100644
> --- a/arch/powerpc/platforms/powernv/pci.c
> +++ b/arch/powerpc/platforms/powernv/pci.c
> @@ -782,35 +782,6 @@ static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
> }
> DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
>
> -static int pnv_pci_probe_mode(struct pci_bus *bus)
> -{
> - struct pci_controller *hose = pci_bus_to_host(bus);
> - const __be64 *tstamp;
> - u64 now, target;
> -
> -
> - /* We hijack this as a way to ensure we have waited long
> - * enough since the reset was lifted on the PCI bus
> - */
> - if (bus != hose->bus)
> - return PCI_PROBE_NORMAL;
> - tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
> - if (!tstamp || !*tstamp)
> - return PCI_PROBE_NORMAL;
> -
> - now = mftb() / tb_ticks_per_usec;
> - target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
> - + PCI_RESET_DELAY_US;
> -
> - pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
> - hose->global_number, target, now);
> -
> - if (now < target)
> - msleep((target - now + 999) / 1000);
> -
> - return PCI_PROBE_NORMAL;
> -}
> -
> void __init pnv_pci_init(void)
> {
> struct device_node *np;
> @@ -857,7 +828,6 @@ void __init pnv_pci_init(void)
> ppc_md.tce_build_rm = pnv_tce_build_rm;
> ppc_md.tce_free_rm = pnv_tce_free_rm;
> ppc_md.tce_get = pnv_tce_get;
> - ppc_md.pci_probe_mode = pnv_pci_probe_mode;
> set_pci_dma_ops(&dma_iommu_ops);
>
> /* Configure MSIs */
^ permalink raw reply
* [PATCH v4 1/1] powerpc/85xx: Add support for Emerson/Artesyn MVME2500.
From: Alessio Igor Bogani @ 2014-12-11 8:56 UTC (permalink / raw)
To: Scott Wood, Kumar Gala; +Cc: Alessio Igor Bogani, linuxppc-dev
Add support for the Artesyn MVME2500 Single Board Computer.
The MVME2500 is a 6U form factor VME64 computer with:
- A single Freescale QorIQ P2010 CPU
- 1 GB of DDR3 onboard memory
- Three Gigabit Ethernets
- Five 16550 compatible UARTS
- One USB 2.0 port, one SHDC socket and one SATA connector
- One PCI/PCI eXpress Mezzanine Card (PMC/XMC) Slot
- MultiProcessor Interrupt Controller (MPIC)
- A DS1375T Real Time Clock (RTC) and 512 KB of Non-Volatile Memory
- Two 64 KB EEPROMs
- U-Boot in 16 SPI Flash
This patch is based on linux-3.18 and has been boot tested.
Signed-off-by: Alessio Igor Bogani <alessio.bogani@elettra.eu>
---
Please note that this patch assumes from v3 that a make savedefconfig has
already been done.
v3 -> v4
Rebased on v3.18
v2 -> v3
Remove an include in the device tree
Rebased on an already sent patch:
'powerpc: refresh mpc85xx_defconfig using "make savedefconfig"'
v1 -> v2
Increase an LBC window from only 0x1000 to 0x8000 bytes
Rename:
eeprom-vpd and spd to eeprom
Artesyn to artesyn
Remove:
board_soc label
partition scheme
A whitespace
#cell-index usages
The mvm2500.dtsi file (moving its definitions at the bottom
of the mvme2500.dts)
mvme2500_defconfig and use mpc85xx_defconfig instead
Useless headers in mvme2500.c
SWIOTLB usages
Replace:
printk() with pr_info()
NVRAM with MTD-RAM: Unfortunately the former doesn't cope with
16-bit addressing of the chip used in MVME2500 board but the
latter can due of the bank-witdth device tree definition.
arch/powerpc/boot/dts/mvme2500.dts | 280 +++++++++++++++++++++++++++++++++
arch/powerpc/configs/mpc85xx_defconfig | 16 +-
arch/powerpc/platforms/85xx/Kconfig | 6 +
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/mvme2500.c | 74 +++++++++
5 files changed, 374 insertions(+), 3 deletions(-)
create mode 100644 arch/powerpc/boot/dts/mvme2500.dts
create mode 100644 arch/powerpc/platforms/85xx/mvme2500.c
diff --git a/arch/powerpc/boot/dts/mvme2500.dts b/arch/powerpc/boot/dts/mvme2500.dts
new file mode 100644
index 0000000..67714cf
--- /dev/null
+++ b/arch/powerpc/boot/dts/mvme2500.dts
@@ -0,0 +1,280 @@
+/*
+ * Device tree source for the Emerson/Artesyn MVME2500
+ *
+ * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+/ {
+ model = "MVME2500";
+ compatible = "artesyn,MVME2500";
+
+ aliases {
+ serial2 = &serial2;
+ serial3 = &serial3;
+ serial4 = &serial4;
+ serial5 = &serial5;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0 0xffe00000 0x100000>;
+
+ i2c@3000 {
+ hwmon@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1337";
+ reg = <0x68>;
+ interrupts = <8 1 0 0>;
+ };
+
+ eeprom@54 {
+ compatible = "atmel,24c64";
+ reg = <0x54>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c512";
+ reg = <0x52>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c512";
+ reg = <0x53>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ };
+
+ spi0: spi@7000 {
+ fsl,espi-num-chipselects = <2>;
+
+ flash@0 {
+ compatible = "atmel,at25df641";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ };
+ flash@1 {
+ compatible = "atmel,at25df641";
+ reg = <1>;
+ spi-max-frequency = <10000000>;
+ };
+ };
+
+ usb@22000 {
+ dr_mode = "host";
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ mdio@24520 {
+ phy1: ethernet-phy@1 {
+ compatible = "brcm,bcm54616S";
+ interrupts = <6 1 0 0>;
+ reg = <0x1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ compatible = "brcm,bcm54616S";
+ interrupts = <6 1 0 0>;
+ reg = <0x2>;
+ };
+
+ phy3: ethernet-phy@3 {
+ compatible = "brcm,bcm54616S";
+ interrupts = <5 1 0 0>;
+ reg = <0x3>;
+ };
+
+ phy7: ethernet-phy@7 {
+ compatible = "brcm,bcm54616S";
+ interrupts = <7 1 0 0>;
+ reg = <0x7>;
+ };
+
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy7>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ mdio@25520 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ enet2: ethernet@26000 {
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ mdio@26520 {
+ tbi2: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+
+ ranges = <0x0 0x0 0x0 0xfff00000 0x00080000
+ 0x1 0x0 0x0 0xffc40000 0x00010000
+ 0x2 0x0 0x0 0xffc50000 0x00010000
+ 0x3 0x0 0x0 0xffc60000 0x00010000
+ 0x4 0x0 0x0 0xffc70000 0x00010000
+ 0x6 0x0 0x0 0xffc80000 0x00010000
+ 0x5 0x0 0x0 0xffdf0000 0x00008000>;
+
+ serial2: serial@1,0 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x1 0x0 0x100>;
+ clock-frequency = <1843200>;
+ interrupts = <11 2 0 0>;
+ };
+
+ serial3: serial@2,0 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x2 0x0 0x100>;
+ clock-frequency = <1843200>;
+ interrupts = <1 2 0 0>;
+ };
+
+ serial4: serial@3,0 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x3 0x0 0x100>;
+ clock-frequency = <1843200>;
+ interrupts = <2 2 0 0>;
+ };
+
+ serial5: serial@4,0 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4 0x0 0x100>;
+ clock-frequency = <1843200>;
+ interrupts = <3 2 0 0>;
+ };
+
+ mram@0,0 {
+ compatible = "everspin,mram", "mtd-ram";
+ reg = <0x0 0x0 0x80000>;
+ bank-width = <2>;
+ };
+
+ board-control@5,0 {
+ compatible = "artesyn,mvme2500-fpga";
+ reg = <0x5 0x0 0x01000>;
+ };
+
+ cpld@6,0 {
+ compatible = "artesyn,mvme2500-cpld";
+ reg = <0x6 0x0 0x10000>;
+ interrupts = <9 1 0 0>;
+ };
+ };
+
+ pci0: pcie@ffe08000 {
+ reg = <0 0xffe08000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0 0xffe09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+
+ };
+
+ pci2: pcie@ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
+
+/include/ "fsl/p2020si-post.dtsi"
+
+/ {
+ soc@ffe00000 {
+ serial@4600 {
+ status = "disabled";
+ };
+
+ i2c@3100 {
+ status = "disabled";
+ };
+
+ sdhc@2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ non-removable;
+ };
+
+ };
+
+};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cfae862..8535c34 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -42,6 +42,7 @@ CONFIG_TQM8548=y
CONFIG_TQM8555=y
CONFIG_TQM8560=y
CONFIG_SBC8548=y
+CONFIG_MVME2500=y
CONFIG_QUICC_ENGINE=y
CONFIG_QE_GPIO=y
CONFIG_HIGHMEM=y
@@ -49,6 +50,8 @@ CONFIG_BINFMT_MISC=m
CONFIG_MATH_EMULATION=y
CONFIG_FORCE_MAX_ZONEORDER=12
CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEASPM is not set
CONFIG_PCI_MSI=y
CONFIG_RAPIDIO=y
CONFIG_NET=y
@@ -85,10 +88,14 @@ CONFIG_FTL=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_M25P80=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_FSL_ELBC=y
CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
@@ -120,6 +127,7 @@ CONFIG_MARVELL_PHY=y
CONFIG_DAVICOM_PHY=y
CONFIG_CICADA_PHY=y
CONFIG_VITESSE_PHY=y
+CONFIG_BROADCOM_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_INPUT_FF_MEMLESS=m
# CONFIG_INPUT_MOUSEDEV is not set
@@ -128,8 +136,8 @@ CONFIG_INPUT_FF_MEMLESS=m
CONFIG_SERIO_LIBPS2=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_NR_UARTS=6
+CONFIG_SERIAL_8250_RUNTIME_UARTS=6
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
@@ -142,7 +150,8 @@ CONFIG_SPI=y
CONFIG_SPI_FSL_SPI=y
CONFIG_SPI_FSL_ESPI=y
CONFIG_GPIO_MPC8XXX=y
-# CONFIG_HWMON is not set
+CONFIG_HWMON=m
+CONFIG_SENSORS_LM90=m
CONFIG_FB=y
CONFIG_FB_FSL_DIU=y
# CONFIG_VGA_CONSOLE is not set
@@ -185,6 +194,7 @@ CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_OF_ESDHC=y
CONFIG_EDAC=y
CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_DS1374=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f22635a..2fb4b24 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -241,6 +241,12 @@ config SGY_CTS1000
help
Enable this to support functionality in Servergy's CTS-1000 systems.
+config MVME2500
+ bool "Artesyn MVME2500"
+ select DEFAULT_UIMAGE
+ help
+ This option enables support for the Emerson/Artesyn MVME2500 board.
+
endif # PPC32
config PPC_QEMU_E500
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 7303260..1fe7fb9 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -31,3 +31,4 @@ obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
obj-$(CONFIG_SGY_CTS1000) += sgy_cts1000.o
+obj-$(CONFIG_MVME2500) += mvme2500.o
diff --git a/arch/powerpc/platforms/85xx/mvme2500.c b/arch/powerpc/platforms/85xx/mvme2500.c
new file mode 100644
index 0000000..1233050
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mvme2500.c
@@ -0,0 +1,74 @@
+/*
+ * Board setup routines for the Emerson/Artesyn MVME2500
+ *
+ * Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
+ *
+ * Based on earlier code by:
+ *
+ * Xianghua Xiao (x.xiao@freescale.com)
+ * Tom Armistead (tom.armistead@emerson.com)
+ * Copyright 2012 Emerson
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Author Alessio Igor Bogani <alessio.bogani@elettra.eu>
+ *
+ */
+
+#include <linux/pci.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+
+void __init mvme2500_pic_init(void)
+{
+ struct mpic *mpic = mpic_alloc(NULL, 0,
+ MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init mvme2500_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("mvme2500_setup_arch()", 0);
+ fsl_pci_assign_primary();
+ pr_info("MVME2500 board from Artesyn\n");
+}
+
+machine_arch_initcall(mvme2500, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init mvme2500_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ return of_flat_dt_is_compatible(root, "artesyn,MVME2500");
+}
+
+define_machine(mvme2500) {
+ .name = "MVME2500",
+ .probe = mvme2500_probe,
+ .setup_arch = mvme2500_setup_arch,
+ .init_IRQ = mvme2500_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
2.1.3
^ permalink raw reply related
* Re: [PATCH] powerpc/powernv: Print the M64 range information
From: Wei Yang @ 2014-12-11 7:29 UTC (permalink / raw)
To: Gavin Shan; +Cc: Wei Yang, linuxppc-dev
In-Reply-To: <20141210224030.GA13035@shangw>
On Thu, Dec 11, 2014 at 09:40:30AM +1100, Gavin Shan wrote:
>On Wed, Dec 10, 2014 at 10:29:37PM +0800, Wei Yang wrote:
>>The M64 range information is missed, which would be helpful in debug.
>>
>>This patch print the M64 range information in the same format as M32.
>>
>>Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
>>---
>> arch/powerpc/platforms/powernv/pci-ioda.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>>diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
>>index 21c8b4d..34f1a27 100644
>>--- a/arch/powerpc/platforms/powernv/pci-ioda.c
>>+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
>>@@ -369,6 +369,9 @@ static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
>> phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
>> phb->ioda.m64_base = pci_addr;
>>
>>+ printk(KERN_INFO " MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
>>+ res->start, res->end, pci_addr);
>>+
>
>Please output segment size if you think it's helpful as well.
The M64 segment size is printed in pnv_pci_init_ioda_phb() line 2620.
>
>Thanks,
>Gavin
>
>> /* Use last M64 BAR to cover M64 window */
>> phb->ioda.m64_bar_idx = 15;
>> phb->init_m64 = pnv_ioda2_init_m64;
>>--
>>1.7.9.5
>>
--
Richard Yang
Help you, Help me
^ permalink raw reply
* [PATCH] powerpc/powernv: Remove pnv_pci_probe_mode()
From: Gavin Shan @ 2014-12-11 6:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Gavin Shan
The callback (ppc_md.pci_probe_mode()) is used to determine if the
child PCI devices of the indicated PCI bus should be probed from
device-tree or hardware. On PowerNV platform, we always expect
probing PCI devices from hardware, which is PowerPC PCI core's
default behaviour. Also, the callback had some delay implemented
based on PHB's device node property "reset-clear-timestamp", which
wasn't exported from skiboot. So we don't need this function and
it's safe to remove it.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/pci.c | 30 ------------------------------
1 file changed, 30 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 4b20f2c..d346df2 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -782,35 +782,6 @@ static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
-static int pnv_pci_probe_mode(struct pci_bus *bus)
-{
- struct pci_controller *hose = pci_bus_to_host(bus);
- const __be64 *tstamp;
- u64 now, target;
-
-
- /* We hijack this as a way to ensure we have waited long
- * enough since the reset was lifted on the PCI bus
- */
- if (bus != hose->bus)
- return PCI_PROBE_NORMAL;
- tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
- if (!tstamp || !*tstamp)
- return PCI_PROBE_NORMAL;
-
- now = mftb() / tb_ticks_per_usec;
- target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
- + PCI_RESET_DELAY_US;
-
- pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
- hose->global_number, target, now);
-
- if (now < target)
- msleep((target - now + 999) / 1000);
-
- return PCI_PROBE_NORMAL;
-}
-
void __init pnv_pci_init(void)
{
struct device_node *np;
@@ -857,7 +828,6 @@ void __init pnv_pci_init(void)
ppc_md.tce_build_rm = pnv_tce_build_rm;
ppc_md.tce_free_rm = pnv_tce_free_rm;
ppc_md.tce_get = pnv_tce_get;
- ppc_md.pci_probe_mode = pnv_pci_probe_mode;
set_pci_dma_ops(&dma_iommu_ops);
/* Configure MSIs */
--
1.8.3.2
^ permalink raw reply related
* [git pull] Please pull mpe/linux.git powerpc-3.19-1 tag
From: Michael Ellerman @ 2014-12-11 5:14 UTC (permalink / raw)
To: Linus Torvalds
Cc: Andrew Morton, mahesh, martijn.de.gouw, Ashish.Kumar,
Emilian.Medve, paulus, cl, jslaby, prabhakar, khandual, mikey,
agraf, James.Yang, Igal.Liberman, lu.jiang, neelegup,
aneesh.kumar, boqun.feng, steve.capper, hongtao.jia, gwshan,
Julia.Lawall, imunsie, scottwood, gkurz, kyle, pebolle, zhong,
linux-kernel, vvijayan, jk, warrier, simon.kagstrom, linuxppc-dev,
anton
[-- Attachment #1: Type: text/plain, Size: 21882 bytes --]
Hi Linus,
Please pull the first batch of powerpc updates for 3.19:
The following changes since commit 8a97577a5967c1234ccc3bc1b45e4b1a58b39ea8:
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux (2014-11-04 11:18:29 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux.git tags/powerpc-3.19-1
for you to fetch changes up to 56548fc0e86cb9156af7a7e1f15ba78f251dafaf:
powerpc/powernv: Return to cpu offline loop when finished in KVM guest (2014-12-08 13:16:31 +1100)
----------------------------------------------------------------
Some nice cleanups like removing bootmem, and removal of __get_cpu_var().
There is one patch to mm/gup.c. This is the generic GUP implementation, but is
only used by us and arm(64). We have an ack from Steve Capper, and although we
didn't get an ack from Andrew he told us to take the patch through the powerpc
tree.
There's one cxl patch. This is in drivers/misc, but Greg said he was happy for
us to manage fixes for it.
There is an infrastructure patch to support an IPMI driver for OPAL. That patch
also appears in Corey Minyard's IPMI tree, you may see a conflict there.
There is also an RTC driver for OPAL. We weren't able to get any response from
the RTC maintainer, Alessandro Zummo, so in the end we just merged the driver.
The usual batch of Freescale updates from Scott.
----------------------------------------------------------------
Alexander Graf (1):
powerpc: Convert power off logic to pm_power_off
Aneesh Kumar K.V (8):
powerpc: Disable CPU_FTR_TM if TM is disabled by firmware
powerpc/mm: Add missing pmd accessors
mm: Update generic gup implementation to handle hugepage directory
powerpc/mm: Switch to generic RCU get_user_pages_fast
powerpc/mm: Check for matching hpte without taking hpte lock
powerpc/mm/thp: Remove code duplication
powerpc/mm/thp: Use tlbiel if possible
powerpc/mm: don't do tlbie for updatepp request with NO HPTE fault
Anshuman Khandual (1):
powerpc/xmon: Enable HW instruction breakpoint on POWER8
Anton Blanchard (18):
powerpc: Use probe_kernel_address in show_instructions
powerpc/pci: Quieten unset I/O resource warning
powerpc: Remove ppc64_boot_msg
powerpc: Remove ppc_md.remove_memory
powerpc: Remove bootmem allocator
powerpc: Remove some old bootmem related comments
powerpc: Remove superfluous bootmem includes
powerpc: Move sparse_init() into initmem_init
powerpc: make __ffs return unsigned long
powerpc/ftrace: Remove mod_return_to_handler
powerpc/ftrace: simplify prepare_ftrace_return
powerpc/jump_label: Use HAVE_JUMP_LABEL
powerpc: Don't use local named register variable in current_thread_info
powerpc: Remove double braces in alignment code.
powerpc: LLVM complains about forward declaration of struct rtas_sensors
powerpc/pseries: Quieten ibm,pcie-link-speed-stats warning
powerpc/pseries: Quieten relocation on exceptions warning
powerpc: Fix bad NULL pointer check in udbg_uart_getc_poll()
Ashish Kumar (1):
powerpc/mpc85xx: Remove SPI and NAND partition from bsc9131rdb.dtsi
Boqun Feng (1):
powerpc: Fix comment typos in arch/powerpc/include/asm/bitops.h
Christoph Lameter (1):
powerpc: Replace __get_cpu_var uses
Emil Medve (7):
powerpc/dts: Factorize the clock control node
dt/bindings: qoriq-clock: Add binding for the platform PLL
powerpc/dts: Add node(s) for the platform PLL
dt/bindings: Introduce the FSL QorIQ DPAA BMan
dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)
dt/bindings: Introduce the FSL QorIQ DPAA QMan
dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s)
Gavin Shan (13):
powerpc/mm: Use PAGE_FACTOR
powerpc/powernv: Check PHB type in advance
powerpc/powernv: Fix condition to remove M64
powerpc/powernv: Rename alloc_m64_pe() to reserve_m64_pe()
powerpc/powernv: Initialize M64 PE in time
powerpc/powernv: Set PELTV for compound PEs
powerpc/powernv: Simplify pnv_ioda_configure_pe()
powerpc/powernv: Bail upon invalid master PE
powerpc/powernv: Fix potential zero devisor
powerpc/eeh: Refactor eeh_reset_pe()
powerpc/eeh: Set EEH_PE_RESET on PE reset
powerpc/eeh: Recover EEH error on ownership change for BCM5719
powerpc/eeh: Dump PHB diag-data early
Greg Kurz (1):
powerpc: Drop useless warning in eeh_init()
Hongtao Jia (2):
powerpc: Add ADT7461 to device tree for supported boards
powerpc: Add INA220 to device tree for supported boards
Ian Munsie (1):
cxl: Return error to PSL if IRQ demultiplexing fails & print clearer warning
Igal Liberman (2):
powerpc/fsl: Added rcw registers to global utility registers
powerpc/fsl: Frame Manager Device Tree binding document
James Yang (1):
powerpc/mm/hugetlb: Sanity check gigantic hugepage count
Jeremy Kerr (1):
powerpc/powernv: Add OPAL IPMI interface
Jiang Lu (1):
powerpc/oprofile: Disable pagefaults during user stack read
Jiri Slaby (1):
powerpc/ftrace: Fix obsolete comment
Julia Lawall (5):
powerpc/4xx/cpm: delete unneeded test before of_node_put
powerpc/fsl: fsl_soc: delete unneeded test before of_node_put
powerpc/mpc5xxx: delete unneeded test before of_node_put
powerpc/pseries: delete unneeded test before of_node_put
powerpc/gamecube/wii: delete unneeded test before of_node_put
Kyle McMartin (1):
powerpc: Remove unused devm_ioremap_prot()
LEROY Christophe (14):
powerpc/8xx: exception InstructionAccess does not exist on MPC8xx
powerpc/8xx: DataAccess exception not generated by MPC8xx
powerpc/8xx: No need to restore registers and save them again.
powerpc/8xx: Use M_TW instead of M_TWB
powerpc/8xx: Don't use MD_TWC for walk
powerpc/8xx: Use PAGE size related consts
powerpc/8xx: Const for TLB RPN forced value
powerpc/8xx: Implement 16k pages
powerpc/8xx: Better readibility of ERRATA CPU6 handling
powerpc/8xx: set PTE bit 22 off TLBmiss
powerpc/8xx: _PMD_PRESENT already set in level 1 entries
powerpc/8xx: Don't restore regs to save them again.
powerpc/8xx: Use DAR to save r3 for CPU6 ERRATA
powerpc/8xx: Invalidate non present TLB as early as possible
Li Zhong (1):
powerpc/pseries: Initialise nvram_pstore_info's buf_lock
Mahesh Salgaonkar (2):
powerpc/powernv: Cleanup unused MCE definitions/declarations.
powerpc/book3s: Fix partial invalidation of TLBs in MCE code.
Martijn de Gouw (1):
powerpc/fsl-rio: add support for mapping inbound windows
Michael Ellerman (11):
Merge branch 'topic/pm-power-off' into next
Merge branch 'topic/get-cpu-var' into next
powerpc: Remove CPU_FTR_HVMODE from CPU_FTRS_ALWAYS
powerpc: Remove unused CPU_FTRS_A2
powerpc: Remove unused vgacon_remap_base & fix build break
Merge branch 'topic/opal-ipmi' into next
powerpc/xmon: Fix build when 4xx=y and 44x=n
Merge remote-tracking branch 'scottwood/next' into next
powerpc: Remove more traces of bootmem
Merge remote-tracking branch 'benh/next' into next
powerpc/xmon: Cleanup the breakpoint flags
Michael Neuling (1):
cxl: Name interrupts in /proc/interrupt
Neelesh Gupta (1):
rtc/tpo: Driver to support rtc and wakeup on PowerNV platform
Paul Bolle (1):
powerpc/8xx: Remove Kconfig symbol FADS
Paul Mackerras (2):
powerpc: Fix compilation of emulate_step()
powerpc/powernv: Return to cpu offline loop when finished in KVM guest
Prabhakar Kushwaha (1):
powerpc/config: Enable memory driver
Scott Wood (1):
powerpc/fsl: Update fman dt binding with clock name and qbman link
Simon Kagstrom (1):
powerpc/boot: Parse chosen/cmdline-timeout parameter
Suresh E. Warrier (1):
powerpc: Save/restore PPR for KVM hypercalls
Vineeth Vijayan (1):
powerpc: Use generic PIE randomization
.../devicetree/bindings/clock/qoriq-clock.txt | 14 +-
.../devicetree/bindings/powerpc/fsl/fman.txt | 534 +++++++++++++++++++++
Documentation/devicetree/bindings/rtc/rtc-opal.txt | 16 +
.../devicetree/bindings/soc/fsl/bman-portals.txt | 56 +++
Documentation/devicetree/bindings/soc/fsl/bman.txt | 125 +++++
.../devicetree/bindings/soc/fsl/qman-portals.txt | 154 ++++++
Documentation/devicetree/bindings/soc/fsl/qman.txt | 165 +++++++
arch/powerpc/Kconfig | 5 +-
arch/powerpc/boot/dts/b4860emu.dts | 4 +-
arch/powerpc/boot/dts/b4qds.dtsi | 23 +
arch/powerpc/boot/dts/bsc9131rdb.dtsi | 50 --
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 28 +-
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 28 +-
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 48 +-
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 48 +-
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 48 +-
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 48 +-
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 48 +-
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 85 ++++
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 68 +++
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 30 +-
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 29 +-
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 29 +-
arch/powerpc/boot/dts/p3041ds.dts | 20 +
arch/powerpc/boot/dts/p5020ds.dts | 20 +
arch/powerpc/boot/dts/p5040ds.dts | 20 +
arch/powerpc/boot/dts/t104xrdb.dtsi | 7 +
arch/powerpc/boot/dts/t208xqds.dtsi | 11 +
arch/powerpc/boot/dts/t4240emu.dts | 4 +-
arch/powerpc/boot/main.c | 15 +-
arch/powerpc/boot/ops.h | 2 +-
arch/powerpc/boot/serial.c | 6 +-
arch/powerpc/configs/corenet32_smp_defconfig | 1 +
arch/powerpc/configs/corenet64_smp_defconfig | 1 +
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/configs/mpc85xx_smp_defconfig | 1 +
arch/powerpc/include/asm/bitops.h | 6 +-
arch/powerpc/include/asm/cputable.h | 10 +-
arch/powerpc/include/asm/eeh.h | 2 +
arch/powerpc/include/asm/elf.h | 3 +-
arch/powerpc/include/asm/fsl_guts.h | 5 +-
arch/powerpc/include/asm/hardirq.h | 7 +-
arch/powerpc/include/asm/hugetlb.h | 8 +-
arch/powerpc/include/asm/io.h | 3 -
arch/powerpc/include/asm/machdep.h | 19 +-
arch/powerpc/include/asm/mmu-8xx.h | 2 +
arch/powerpc/include/asm/mmu-hash64.h | 22 +-
arch/powerpc/include/asm/opal.h | 122 +----
arch/powerpc/include/asm/paca.h | 7 -
arch/powerpc/include/asm/page.h | 4 +-
arch/powerpc/include/asm/pgtable-ppc32.h | 20 +
arch/powerpc/include/asm/pgtable-ppc64-4k.h | 16 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h | 3 +
arch/powerpc/include/asm/pgtable-ppc64.h | 52 +-
arch/powerpc/include/asm/pgtable.h | 6 +-
arch/powerpc/include/asm/processor.h | 2 +-
arch/powerpc/include/asm/pte-8xx.h | 7 +-
arch/powerpc/include/asm/setup.h | 3 +-
arch/powerpc/include/asm/thread_info.h | 5 +-
arch/powerpc/include/asm/tlbflush.h | 10 +-
arch/powerpc/include/asm/vga.h | 4 +-
arch/powerpc/include/asm/xics.h | 8 +-
arch/powerpc/kernel/align.c | 2 +-
arch/powerpc/kernel/asm-offsets.c | 7 -
arch/powerpc/kernel/crash_dump.c | 1 -
arch/powerpc/kernel/dbell.c | 2 +-
arch/powerpc/kernel/eeh.c | 41 +-
arch/powerpc/kernel/eeh_driver.c | 10 +-
arch/powerpc/kernel/entry_32.S | 12 +-
arch/powerpc/kernel/entry_64.S | 35 +-
arch/powerpc/kernel/exceptions-64s.S | 34 +-
arch/powerpc/kernel/ftrace.c | 73 +--
arch/powerpc/kernel/head_8xx.S | 230 ++++-----
arch/powerpc/kernel/hw_breakpoint.c | 6 +-
arch/powerpc/kernel/idle_power7.S | 12 +-
arch/powerpc/kernel/iommu.c | 2 +-
arch/powerpc/kernel/irq.c | 5 +-
arch/powerpc/kernel/kgdb.c | 2 +-
arch/powerpc/kernel/kprobes.c | 6 +-
arch/powerpc/kernel/mce.c | 24 +-
arch/powerpc/kernel/mce_power.c | 4 +-
arch/powerpc/kernel/pci-common.c | 3 +-
arch/powerpc/kernel/pci_32.c | 4 +-
arch/powerpc/kernel/pci_64.c | 1 -
arch/powerpc/kernel/process.c | 36 +-
arch/powerpc/kernel/prom.c | 11 +-
arch/powerpc/kernel/rtas-proc.c | 20 +-
arch/powerpc/kernel/rtas.c | 4 +-
arch/powerpc/kernel/rtas_pci.c | 1 -
arch/powerpc/kernel/setup-common.c | 6 +-
arch/powerpc/kernel/setup_32.c | 11 +-
arch/powerpc/kernel/setup_64.c | 35 +-
arch/powerpc/kernel/smp.c | 6 +-
arch/powerpc/kernel/sysfs.c | 4 +-
arch/powerpc/kernel/time.c | 23 +-
arch/powerpc/kernel/traps.c | 8 +-
arch/powerpc/kernel/udbg_16550.c | 6 +-
arch/powerpc/kernel/vdso.c | 1 -
arch/powerpc/kvm/book3s_hv_builtin.c | 3 +-
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 54 ++-
arch/powerpc/kvm/e500.c | 14 +-
arch/powerpc/kvm/e500mc.c | 4 +-
arch/powerpc/lib/Makefile | 1 -
arch/powerpc/lib/alloc.c | 4 +-
arch/powerpc/lib/devres.c | 43 --
arch/powerpc/lib/sstep.c | 6 +-
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/fault.c | 7 -
arch/powerpc/mm/gup.c | 235 ---------
arch/powerpc/mm/hash_low_64.S | 19 +-
arch/powerpc/mm/hash_native_64.c | 41 +-
arch/powerpc/mm/hash_utils_64.c | 114 ++++-
arch/powerpc/mm/hugepage-hash64.c | 60 +--
arch/powerpc/mm/hugetlbpage-book3e.c | 6 +-
arch/powerpc/mm/hugetlbpage-hash64.c | 6 +-
arch/powerpc/mm/hugetlbpage.c | 51 +-
arch/powerpc/mm/init_32.c | 10 -
arch/powerpc/mm/init_64.c | 1 -
arch/powerpc/mm/mem.c | 77 +--
arch/powerpc/mm/mmu_context_nohash.c | 8 +-
arch/powerpc/mm/numa.c | 224 ++-------
arch/powerpc/mm/pgtable_32.c | 3 +-
arch/powerpc/mm/pgtable_64.c | 104 ++--
arch/powerpc/oprofile/backtrace.c | 6 +-
arch/powerpc/perf/core-book3s.c | 22 +-
arch/powerpc/perf/core-fsl-emb.c | 6 +-
arch/powerpc/platforms/44x/ppc476.c | 2 +-
arch/powerpc/platforms/512x/mpc512x_shared.c | 9 +-
arch/powerpc/platforms/52xx/efika.c | 3 +-
arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c | 8 +-
arch/powerpc/platforms/85xx/corenet_generic.c | 2 +-
arch/powerpc/platforms/85xx/sgy_cts1000.c | 4 +-
arch/powerpc/platforms/8xx/Kconfig | 4 -
arch/powerpc/platforms/cell/beat_htab.c | 4 +-
arch/powerpc/platforms/cell/celleb_pci.c | 6 +-
arch/powerpc/platforms/cell/celleb_scc_epci.c | 1 -
arch/powerpc/platforms/cell/celleb_scc_pciex.c | 1 -
arch/powerpc/platforms/cell/celleb_setup.c | 4 +-
arch/powerpc/platforms/cell/interrupt.c | 6 +-
arch/powerpc/platforms/cell/qpace_setup.c | 2 +-
arch/powerpc/platforms/cell/setup.c | 2 +-
arch/powerpc/platforms/cell/spu_base.c | 5 +-
arch/powerpc/platforms/cell/spufs/fault.c | 2 +-
arch/powerpc/platforms/chrp/setup.c | 3 +-
arch/powerpc/platforms/embedded6xx/gamecube.c | 3 +-
arch/powerpc/platforms/embedded6xx/linkstation.c | 4 +-
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c | 6 +-
arch/powerpc/platforms/embedded6xx/wii.c | 3 +-
arch/powerpc/platforms/maple/pci.c | 1 -
arch/powerpc/platforms/maple/setup.c | 4 +-
arch/powerpc/platforms/powermac/nvram.c | 6 +-
arch/powerpc/platforms/powermac/pci.c | 1 -
arch/powerpc/platforms/powermac/setup.c | 3 +-
arch/powerpc/platforms/powernv/eeh-ioda.c | 16 +-
arch/powerpc/platforms/powernv/opal-async.c | 3 +
arch/powerpc/platforms/powernv/opal-rtc.c | 65 +--
arch/powerpc/platforms/powernv/opal-tracepoints.c | 4 +-
arch/powerpc/platforms/powernv/opal-wrappers.S | 6 +-
arch/powerpc/platforms/powernv/opal.c | 21 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 217 ++++++---
arch/powerpc/platforms/powernv/pci-p5ioc2.c | 44 +-
arch/powerpc/platforms/powernv/pci.c | 1 -
arch/powerpc/platforms/powernv/pci.h | 2 +-
arch/powerpc/platforms/powernv/setup.c | 6 +-
arch/powerpc/platforms/powernv/smp.c | 23 +-
arch/powerpc/platforms/ps3/htab.c | 2 +-
arch/powerpc/platforms/ps3/interrupt.c | 2 +-
arch/powerpc/platforms/ps3/setup.c | 9 +-
arch/powerpc/platforms/pseries/dtl.c | 2 +-
arch/powerpc/platforms/pseries/hotplug-memory.c | 21 -
arch/powerpc/platforms/pseries/hvCall.S | 4 +-
arch/powerpc/platforms/pseries/hvCall_inst.c | 4 +-
arch/powerpc/platforms/pseries/iommu.c | 11 +-
arch/powerpc/platforms/pseries/lpar.c | 10 +-
arch/powerpc/platforms/pseries/nvram.c | 2 +
arch/powerpc/platforms/pseries/pci.c | 2 +-
arch/powerpc/platforms/pseries/ras.c | 4 +-
arch/powerpc/platforms/pseries/setup.c | 65 +--
arch/powerpc/sysdev/fsl_msi.c | 1 -
arch/powerpc/sysdev/fsl_pci.c | 3 +-
arch/powerpc/sysdev/fsl_rio.c | 104 ++++
arch/powerpc/sysdev/fsl_rio.h | 13 +
arch/powerpc/sysdev/fsl_soc.c | 5 +-
arch/powerpc/sysdev/ipic.c | 1 -
arch/powerpc/sysdev/mpc5xxx_clocks.c | 3 +-
arch/powerpc/sysdev/mpic.c | 1 -
arch/powerpc/sysdev/mpic_pasemi_msi.c | 1 -
arch/powerpc/sysdev/mpic_u3msi.c | 1 -
arch/powerpc/sysdev/ppc4xx_cpm.c | 8 +-
arch/powerpc/sysdev/ppc4xx_msi.c | 1 -
arch/powerpc/sysdev/ppc4xx_pci.c | 1 -
arch/powerpc/sysdev/qe_lib/qe.c | 1 -
arch/powerpc/sysdev/qe_lib/qe_ic.c | 1 -
arch/powerpc/sysdev/uic.c | 1 -
arch/powerpc/sysdev/xics/xics-common.c | 2 +-
arch/powerpc/xmon/xmon.c | 82 +++-
drivers/misc/cxl/cxl.h | 15 +-
drivers/misc/cxl/fault.c | 8 +-
drivers/misc/cxl/irq.c | 144 ++++--
drivers/misc/cxl/native.c | 14 +-
drivers/rtc/Kconfig | 11 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-opal.c | 261 ++++++++++
include/linux/hugetlb.h | 46 ++
mm/gup.c | 81 +++-
205 files changed, 3246 insertions(+), 2177 deletions(-)
create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/fman.txt
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-opal.txt
create mode 100644 Documentation/devicetree/bindings/soc/fsl/bman-portals.txt
create mode 100644 Documentation/devicetree/bindings/soc/fsl/bman.txt
create mode 100644 Documentation/devicetree/bindings/soc/fsl/qman-portals.txt
create mode 100644 Documentation/devicetree/bindings/soc/fsl/qman.txt
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
create mode 100644 arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
delete mode 100644 arch/powerpc/lib/devres.c
delete mode 100644 arch/powerpc/mm/gup.c
create mode 100644 drivers/rtc/rtc-opal.c
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* [PATCH 2/2] powerpc/eeh: Allow to set maximal frozen times
From: Gavin Shan @ 2014-12-11 3:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: grimm, Gavin Shan
In-Reply-To: <1418268536-15002-1-git-send-email-gwshan@linux.vnet.ibm.com>
When PE's frozen count hits maximal allowed frozen times, which is
5 currently, it will be forced to be offline permanently. Once the
PE is removed permanently, rebooting machine is required to bring
the PE back. It's not convienent when testing EEH functionality.
The patch exports the maximal allowed frozen times through debugfs
entry (/sys/kernel/debug/powerpc/eeh_max_freezes).
Requested-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/eeh.h | 7 +------
arch/powerpc/kernel/eeh.c | 24 ++++++++++++++++++++++++
arch/powerpc/kernel/eeh_driver.c | 2 +-
3 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 3e4dd34..55abfd0 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -218,6 +218,7 @@ struct eeh_ops {
};
extern int eeh_subsystem_flags;
+extern int eeh_max_freezes;
extern struct eeh_ops *eeh_ops;
extern raw_spinlock_t confirm_error_lock;
@@ -255,12 +256,6 @@ static inline void eeh_serialize_unlock(unsigned long flags)
raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
}
-/*
- * Max number of EEH freezes allowed before we consider the device
- * to be permanently disabled.
- */
-#define EEH_MAX_ALLOWED_FREEZES 5
-
typedef void *(*eeh_traverse_func)(void *data, void *flag);
void eeh_set_pe_aux_size(int size);
int eeh_phb_pe_create(struct pci_controller *phb);
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 05be77d..cada1aa 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -104,6 +104,13 @@
int eeh_subsystem_flags;
EXPORT_SYMBOL(eeh_subsystem_flags);
+/*
+ * EEH allowed maximal frozen times. If one particular PE's
+ * frozen count in last hour exceeds this limit, the PE will
+ * be forced to be offline permanently.
+ */
+int eeh_max_freezes = 5;
+
/* Platform dependent EEH operations */
struct eeh_ops *eeh_ops = NULL;
@@ -1655,8 +1662,22 @@ static int eeh_enable_dbgfs_get(void *data, u64 *val)
return 0;
}
+static int eeh_freeze_dbgfs_set(void *data, u64 val)
+{
+ eeh_max_freezes = val;
+ return 0;
+}
+
+static int eeh_freeze_dbgfs_get(void *data, u64 *val)
+{
+ *val = eeh_max_freezes;
+ return 0;
+}
+
DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
eeh_enable_dbgfs_set, "0x%llx\n");
+DEFINE_SIMPLE_ATTRIBUTE(eeh_freeze_dbgfs_ops, eeh_freeze_dbgfs_get,
+ eeh_freeze_dbgfs_set, "0x%llx\n");
#endif
static int __init eeh_init_proc(void)
@@ -1667,6 +1688,9 @@ static int __init eeh_init_proc(void)
debugfs_create_file("eeh_enable", 0600,
powerpc_debugfs_root, NULL,
&eeh_enable_dbgfs_ops);
+ debugfs_create_file("eeh_max_freezes", 0600,
+ powerpc_debugfs_root, NULL,
+ &eeh_freeze_dbgfs_ops);
#endif
}
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index ac00672..d099540 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -667,7 +667,7 @@ static void eeh_handle_normal_event(struct eeh_pe *pe)
eeh_pe_update_time_stamp(pe);
pe->freeze_count++;
- if (pe->freeze_count > EEH_MAX_ALLOWED_FREEZES)
+ if (pe->freeze_count > eeh_max_freezes)
goto excess_failures;
pr_warn("EEH: This PCI device has failed %d times in the last hour\n",
pe->freeze_count);
--
1.8.3.2
^ permalink raw reply related
* [PATCH 1/2] powerpc/eeh: Introduce flag EEH_PE_REMOVED
From: Gavin Shan @ 2014-12-11 3:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: grimm, Gavin Shan
The conditions that one specific PE's frozen count exceeds the maximal
allowed times (EEH_MAX_ALLOWED_FREEZES) and it's in isolated or recovery
state indicate the PE was removed permanently implicitly. The patch
introduces flag EEH_PE_REMOVED to indicate that explicitly so that we
don't depend on the fixed maximal allowed times, which can be varied as
we do in subsequent patch.
Flag EEH_PE_REMOVED is expected to be marked for the PE whose frozen
count exceeds the maximal allowed times, or just failed from recovery.
Requested-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/eeh.h | 1 +
arch/powerpc/kernel/eeh_driver.c | 2 +-
arch/powerpc/kernel/eeh_pe.c | 6 ++----
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 9c11d1e..3e4dd34 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -78,6 +78,7 @@ struct device_node;
#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
+#define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
struct eeh_pe {
int type; /* PE type: PHB/Bus/Device */
diff --git a/arch/powerpc/kernel/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index b17e793..ac00672 100644
--- a/arch/powerpc/kernel/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -806,7 +806,7 @@ perm_error:
eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
/* Mark the PE to be removed permanently */
- pe->freeze_count = EEH_MAX_ALLOWED_FREEZES + 1;
+ eeh_pe_state_mark(pe, EEH_PE_REMOVED);
/*
* Shut down the device drivers for good. We mark
diff --git a/arch/powerpc/kernel/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index fa950fb..1e4946c 100644
--- a/arch/powerpc/kernel/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -526,8 +526,7 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
struct pci_dev *pdev;
/* Keep the state of permanently removed PE intact */
- if ((pe->freeze_count > EEH_MAX_ALLOWED_FREEZES) &&
- (state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
+ if (pe->state & EEH_PE_REMOVED)
return NULL;
pe->state |= state;
@@ -600,8 +599,7 @@ static void *__eeh_pe_state_clear(void *data, void *flag)
struct pci_dev *pdev;
/* Keep the state of permanently removed PE intact */
- if ((pe->freeze_count > EEH_MAX_ALLOWED_FREEZES) &&
- (state & EEH_PE_ISOLATED))
+ if (pe->state & EEH_PE_REMOVED)
return NULL;
pe->state &= ~state;
--
1.8.3.2
^ permalink raw reply related
* Re: [1/2] perf/powerpc/hv-24x7: Use per-cpu page buffer
From: Michael Ellerman @ 2014-12-11 1:44 UTC (permalink / raw)
To: sukadev, Michael Ellerman
Cc: linuxppc-dev, dev, Jiri Olsa, linux-kernel,
Arnaldo Carvalho de Melo
In-Reply-To: <20141210222912.GA30869@us.ibm.com>
On Wed, 2014-10-12 at 22:29:13 UTC, sukadev@linux.vnet.ibm.com wrote:
> Michael Ellerman [mpe@ellerman.id.au] wrote:
> | On Tue, 2014-12-09 at 23:06 -0800, Sukadev Bhattiprolu wrote:
> | > From 470c16c8955672103a9529c78dffbb239e9e27b8 Mon Sep 17 00:00:00 2001
> | > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> | > Date: Tue, 9 Dec 2014 22:17:46 -0500
> | > Subject: [PATCH 1/2] perf/poweprc/hv-24x7: Use per-cpu page buffer
> | >
> | > diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
> | > index dba3408..18e1f49 100644
> | > --- a/arch/powerpc/perf/hv-24x7.c
> | > +++ b/arch/powerpc/perf/hv-24x7.c
> | > @@ -217,11 +217,14 @@ static bool is_physical_domain(int domain)
> | > domain == HV_24X7_PERF_DOMAIN_PHYSICAL_CORE;
> | > }
> | >
> | > +DEFINE_PER_CPU(char, hv_24x7_reqb[4096]);
> | > +DEFINE_PER_CPU(char, hv_24x7_resb[4096]);
> |
> | Do we need it to be 4K aligned also? I would guess so.
>
> Yes, fixed in the patch below.
OK.
> |
> | Rather than declaring these as char arrays and then casting below, can you pull
> | the struct definitions up and then declare the per cpu variables with the
> | proper type.
>
> Well, the structures, used for communication with HV, have variable length
> arrays, like:
>
> struct hv_24x7_request_buffer {
> ...
> struct hv_24x7_request requests[];
> };
>
> i.e the buffer needs to be larger than reported by sizeof(). So we
> allocate a large buffer and cast it. Not sure if there is a trick to
> get DEFINE_PER_CPU() to do that.
So the array is variable length, but no larger than 4K - at least I hope
because you're using a 4K buffer :)
The neatest way to handle that is to make it a union, with the struct and a 4K
char buffer.
But we can do that as a cleanup later.
> | > + memset(request_buffer, 0, 4096);
> | > + memset(result_buffer, 0, 4096);
> |
> | Do we have to memset them? That's not going to speed things up.
>
> I agree about the speed, specially since we have a larger buffer. But we
> are reusing the buffer for independent events and some fields need to be 0
> (hence the zalloc in the current code).
Sure, so you could explicitly initialise those fields to zero.
But that also can be another cleanup.
I'll take this as it is.
cheers
^ permalink raw reply
* [PATCH v3] powerpc/powernv: Expose OPAL firmware symbol map
From: Michael Ellerman @ 2014-12-11 1:39 UTC (permalink / raw)
To: linuxppc-dev
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Newer versions of OPAL will provide this, so let's expose it to user
space so tools like perf can use it to properly decode samples in
firmware space.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/platforms/powernv/opal.c | 38 ++++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
v3. Use bin_attribute->private & size. Add pr_fmt().
v2. Use memory_read_from_buffer()
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index d019b081df9d..8907ba039f1e 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -9,8 +9,9 @@
* 2 of the License, or (at your option) any later version.
*/
-#undef DEBUG
+#define pr_fmt(fmt) "opal: " fmt
+#include <linux/printk.h>
#include <linux/types.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
@@ -626,6 +627,39 @@ static int opal_sysfs_init(void)
return 0;
}
+static ssize_t symbol_map_read(struct file *fp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buf, loff_t off, size_t count)
+{
+ return memory_read_from_buffer(buf, count, &off, bin_attr->private,
+ bin_attr->size);
+}
+
+static BIN_ATTR_RO(symbol_map, 0);
+
+static void opal_export_symmap(void)
+{
+ const __be64 *syms;
+ unsigned int size;
+ struct device_node *fw;
+ int rc;
+
+ fw = of_find_node_by_path("/ibm,opal/firmware");
+ if (!fw)
+ return;
+ syms = of_get_property(fw, "symbol-map", &size);
+ if (!syms || size != 2 * sizeof(__be64))
+ return;
+
+ /* Setup attributes */
+ bin_attr_symbol_map.private = __va(be64_to_cpu(syms[0]));
+ bin_attr_symbol_map.size = be64_to_cpu(syms[1]);
+
+ rc = sysfs_create_bin_file(opal_kobj, &bin_attr_symbol_map);
+ if (rc)
+ pr_warn("Error %d creating OPAL symbols file\n", rc);
+}
+
static void __init opal_dump_region_init(void)
{
void *addr;
@@ -693,6 +727,8 @@ static int __init opal_init(void)
/* Create "opal" kobject under /sys/firmware */
rc = opal_sysfs_init();
if (rc == 0) {
+ /* Export symbol map to userspace */
+ opal_export_symmap();
/* Setup dump region interface */
opal_dump_region_init();
/* Setup error log interface */
--
2.1.0
^ permalink raw reply related
* [PATCH] memory/fsl-corenet-cf: Add t1040 support
From: Scott Wood @ 2014-12-11 0:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood, linux-kernel
T1040 has a different version of corenet-cf, despite being incorrectly
labelled with a fsl,corenet2-cf compatible. The t1040 version of
corenet-cf has a version register that can be read to distinguish. The
t4240/b4860 version officially does not, but testing shows that it does
and has a different value, so use that. If somehow this ends up not
being reliable and we treat a t4240/b4860 as a t1040 (the reverse
should not happen, as t1040's version register is official), currently
the worst that should happen is writing to reserved bits to enable
events that don't exist.
The changes to the t1040 version of corenet-cf that this driver cares
about are the addition of two new error events. There are also changes
to the format of cecar2, which is printed, but not interpreted, by this
driver.
Signed-off-by: Scott Wood <scottwood@freescale.com>
---
drivers/memory/fsl-corenet-cf.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/memory/fsl-corenet-cf.c b/drivers/memory/fsl-corenet-cf.c
index c9443fc..94c952e 100644
--- a/drivers/memory/fsl-corenet-cf.c
+++ b/drivers/memory/fsl-corenet-cf.c
@@ -27,18 +27,29 @@ enum ccf_version {
struct ccf_info {
enum ccf_version version;
int err_reg_offs;
+ bool has_brr;
};
static const struct ccf_info ccf1_info = {
.version = CCF1,
.err_reg_offs = 0xa00,
+ .has_brr = false,
};
static const struct ccf_info ccf2_info = {
.version = CCF2,
.err_reg_offs = 0xe40,
+ .has_brr = true,
};
+/*
+ * This register is present but not documented, with different values for
+ * IP_ID, on other chips with fsl,corenet2-cf such as t4240 and b4860.
+ */
+#define CCF_BRR 0xbf8
+#define CCF_BRR_IPID 0xffff0000
+#define CCF_BRR_IPID_T1040 0x09310000
+
static const struct of_device_id ccf_matches[] = {
{
.compatible = "fsl,corenet1-cf",
@@ -66,6 +77,8 @@ struct ccf_err_regs {
/* LAE/CV also valid for errdis and errinten */
#define ERRDET_LAE (1 << 0) /* Local Access Error */
#define ERRDET_CV (1 << 1) /* Coherency Violation */
+#define ERRDET_UTID (1 << 2) /* Unavailable Target ID (t1040) */
+#define ERRDET_MCST (1 << 3) /* Multicast Stash (t1040) */
#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */
#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT)
#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */
@@ -84,6 +97,7 @@ struct ccf_private {
struct device *dev;
void __iomem *regs;
struct ccf_err_regs __iomem *err_regs;
+ bool t1040;
};
static irqreturn_t ccf_irq(int irq, void *dev_id)
@@ -142,6 +156,12 @@ static irqreturn_t ccf_irq(int irq, void *dev_id)
if (errdet & ERRDET_CV)
dev_crit(ccf->dev, "Coherency Violation\n");
+ if (errdet & ERRDET_UTID)
+ dev_crit(ccf->dev, "Unavailable Target ID\n");
+
+ if (errdet & ERRDET_MCST)
+ dev_crit(ccf->dev, "Multicast Stash\n");
+
if (cap_valid) {
dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n",
addr, src_id);
@@ -157,6 +177,7 @@ static int ccf_probe(struct platform_device *pdev)
struct ccf_private *ccf;
struct resource *r;
const struct of_device_id *match;
+ u32 errinten;
int ret, irq;
match = of_match_device(ccf_matches, &pdev->dev);
@@ -183,6 +204,13 @@ static int ccf_probe(struct platform_device *pdev)
ccf->info = match->data;
ccf->err_regs = ccf->regs + ccf->info->err_reg_offs;
+ if (ccf->info->has_brr) {
+ u32 brr = ioread32be(ccf->regs + CCF_BRR);
+
+ if ((brr & CCF_BRR_IPID) == CCF_BRR_IPID_T1040)
+ ccf->t1040 = true;
+ }
+
dev_set_drvdata(&pdev->dev, ccf);
irq = platform_get_irq(pdev, 0);
@@ -197,15 +225,19 @@ static int ccf_probe(struct platform_device *pdev)
return ret;
}
+ errinten = ERRDET_LAE | ERRDET_CV;
+ if (ccf->t1040)
+ errinten |= ERRDET_UTID | ERRDET_MCST;
+
switch (ccf->info->version) {
case CCF1:
/* On CCF1 this register enables rather than disables. */
- iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errdis);
+ iowrite32be(errinten, &ccf->err_regs->errdis);
break;
case CCF2:
iowrite32be(0, &ccf->err_regs->errdis);
- iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errinten);
+ iowrite32be(errinten, &ccf->err_regs->errinten);
break;
}
--
2.1.0
^ permalink raw reply related
* Re: [PATCH 2/4] powerpc32: properly clear page table when 0 is not a good default PTE value
From: Scott Wood @ 2014-12-11 0:07 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <20141210180037.C46001A5D62@localhost.localdomain>
On Wed, 2014-12-10 at 19:00 +0100, Christophe Leroy wrote:
> Some HW invert some PTE bits. In some case, __pte(0) is not 0 so the PTEs shall
> be properly set prior to being used.
__pte(0) is always zero. If that changes in a future patch, that patch
is not doing the right thing. The __pte()/pte_val() accesors should not
do anything beyond boxing/unboxing the value in a struct. The right
place for special 8xx handling of the inverted bit is in pte_mkwrite()
and such.
I don't see any other architecture using __pte()/pte_val() this way.
-Scott
^ permalink raw reply
* Re: [PATCH 2 1/4] powerpc: drop the ability to tweak SMT mode at boot time
From: Scott Wood @ 2014-12-10 23:50 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Greg Kurz
In-Reply-To: <1418177689.30244.4.camel@concordia>
On Wed, 2014-12-10 at 13:14 +1100, Michael Ellerman wrote:
> On Tue, 2014-12-09 at 18:14 -0600, Scott Wood wrote:
> > What benefit is there to ignoring "scripture" here? Going from an easy
> > to use command line option to needing to mess around with the dts file
> > is not a usability improvement. If you want to make it Freescale-only,
> > fine. If you want to push me to fix the problems with the
> > implementation, fine.
>
> It's easy to use but it doesn't necessarily work.
>
> You said in your other mail to Greg "Sometimes it's useful to ensure that the
> second thread has never run when debugging a problem.".
>
> But you don't know that, for all you know your firmware has started the thread
> and it's busy looping somewhere. Perhaps you guys know that your firmware
> doesn't do that, but it's still a hack.
I know that our firmware doesn't do that, and I can verify by reading
the relevant register.
> We end up with cpus in the present map, but we have no idea where they are or
> what they are doing.
Can we check smt-enabled a little earlier and refrain from marking the
secondary threads as present if smt is disabled?
> So as far as I'm concerned it's only useful as a debugging hack, and one that
> we don't really use anymore. But if you guys think it's useful then we'll keep
> it.
>
> I'll work out with Greg what the cleanest solution is.
>
> It looks like you only need it on e6500? Which is platforms/85xx I think.
> Anywhere else?
Yes, just e6500.
-Scott
^ permalink raw reply
* Re: [PATCH] powerpc: secondary CPUs signal to master before setting active and online (fixes kernel BUG at kernel/smpboot.c:134!)
From: Michael Ellerman @ 2014-12-10 23:06 UTC (permalink / raw)
To: Linus Torvalds
Cc: Peter Zijlstra, Yuanhan Liu, Benjamin Segall, Paul Mackerras,
Ingo Molnar, Rafael J. Wysocki, Ingo Molnar, Paul Turner,
yuyang.du, Daniel J Blueman, Steven Rostedt, Anton Blanchard,
subbaram, Thomas Gleixner, Wu Fengguang, lkp,
Linux Kernel Mailing List, Slava Pestov, Tejun Heo, Andrew Morton,
Brian Norris, ppc-dev
In-Reply-To: <CA+55aFyR5PzNkojvEej1NXnpEFOPOYfnxCcPDAjg1rE79tQv7A@mail.gmail.com>
On Tue, 2014-12-09 at 12:54 -0800, Linus Torvalds wrote:
> On Mon, Dec 8, 2014 at 3:58 PM, Anton Blanchard <anton@samba.org> wrote:
> > Hi Ingo,
> >
> >> At that point I thought the previous task_cpu() was somewhat ingrained
> >> in the scheduler and came up with the patch. If not, we could go on a
> >> hunt to see what else needs fixing.
> >
> > I had another look. The scheduled does indeed make assumptions about the
> > previous task_cpu, but we have a hammer to fix it up called
> > select_fallback_rq.
> >
> > I annotated select_fallback_rq, and did hit a case where the CPU was
> > not active. ppc64 patch below.
>
> Anton, I'll assume I will get this through the usual powerpc pull requests?
Yeah I'll put it in my tree unless Anton objects.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Print the M64 range information
From: Gavin Shan @ 2014-12-10 22:40 UTC (permalink / raw)
To: Wei Yang; +Cc: linuxppc-dev, gwshan
In-Reply-To: <1418221778-12458-1-git-send-email-weiyang@linux.vnet.ibm.com>
On Wed, Dec 10, 2014 at 10:29:37PM +0800, Wei Yang wrote:
>The M64 range information is missed, which would be helpful in debug.
>
>This patch print the M64 range information in the same format as M32.
>
>Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
>---
> arch/powerpc/platforms/powernv/pci-ioda.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
>index 21c8b4d..34f1a27 100644
>--- a/arch/powerpc/platforms/powernv/pci-ioda.c
>+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
>@@ -369,6 +369,9 @@ static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
> phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe;
> phb->ioda.m64_base = pci_addr;
>
>+ printk(KERN_INFO " MEM64 0x%016llx..0x%016llx -> 0x%016llx\n",
>+ res->start, res->end, pci_addr);
>+
Please output segment size if you think it's helpful as well.
Thanks,
Gavin
> /* Use last M64 BAR to cover M64 window */
> phb->ioda.m64_bar_idx = 15;
> phb->init_m64 = pnv_ioda2_init_m64;
>--
>1.7.9.5
>
^ permalink raw reply
* Re: [PATCH 1/2] perf/powerpc/hv-24x7: Use per-cpu page buffer
From: Sukadev Bhattiprolu @ 2014-12-10 22:29 UTC (permalink / raw)
To: Michael Ellerman
Cc: linuxppc-dev, Jiri Olsa, dev, linux-kernel,
Arnaldo Carvalho de Melo
In-Reply-To: <1418202549.9279.0.camel@ellerman.id.au>
Michael Ellerman [mpe@ellerman.id.au] wrote:
| On Tue, 2014-12-09 at 23:06 -0800, Sukadev Bhattiprolu wrote:
| > From 470c16c8955672103a9529c78dffbb239e9e27b8 Mon Sep 17 00:00:00 2001
| > From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
| > Date: Tue, 9 Dec 2014 22:17:46 -0500
| > Subject: [PATCH 1/2] perf/poweprc/hv-24x7: Use per-cpu page buffer
| >
| > diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
| > index dba3408..18e1f49 100644
| > --- a/arch/powerpc/perf/hv-24x7.c
| > +++ b/arch/powerpc/perf/hv-24x7.c
| > @@ -217,11 +217,14 @@ static bool is_physical_domain(int domain)
| > domain == HV_24X7_PERF_DOMAIN_PHYSICAL_CORE;
| > }
| >
| > +DEFINE_PER_CPU(char, hv_24x7_reqb[4096]);
| > +DEFINE_PER_CPU(char, hv_24x7_resb[4096]);
|
| Do we need it to be 4K aligned also? I would guess so.
Yes, fixed in the patch below.
|
| Rather than declaring these as char arrays and then casting below, can you pull
| the struct definitions up and then declare the per cpu variables with the
| proper type.
Well, the structures, used for communication with HV, have variable length
arrays, like:
struct hv_24x7_request_buffer {
...
struct hv_24x7_request requests[];
};
i.e the buffer needs to be larger than reported by sizeof(). So we
allocate a large buffer and cast it. Not sure if there is a trick to
get DEFINE_PER_CPU() to do that. We could add code to allocate pages
per cpu during init, but that would mean more code, error handling etc.
|
|
| > static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
| > u16 lpar, u64 *res,
| > bool success_expected)
| > {
| > - unsigned long ret = -ENOMEM;
| > + unsigned long ret;
| >
| > /*
| > * request_buffer and result_buffer are not required to be 4k aligned,
| > @@ -243,13 +246,11 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
| > BUILD_BUG_ON(sizeof(*request_buffer) > 4096);
| > BUILD_BUG_ON(sizeof(*result_buffer) > 4096);
| >
| > - request_buffer = kmem_cache_zalloc(hv_page_cache, GFP_USER);
| > - if (!request_buffer)
| > - goto out;
| > + request_buffer = (void *)get_cpu_var(hv_24x7_reqb);
| > + result_buffer = (void *)get_cpu_var(hv_24x7_resb);
| >
| > - result_buffer = kmem_cache_zalloc(hv_page_cache, GFP_USER);
| > - if (!result_buffer)
| > - goto out_free_request_buffer;
| > + memset(request_buffer, 0, 4096);
| > + memset(result_buffer, 0, 4096);
|
| Do we have to memset them? That's not going to speed things up.
I agree about the speed, specially since we have a larger buffer. But we
are reusing the buffer for independent events and some fields need to be 0
(hence the zalloc in the current code).
---
>From 545ad0771ef8f22085ed8bb486f0a81b3afc5757 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Date: Tue, 9 Dec 2014 22:17:46 -0500
Subject: [PATCH 1/2] powerpc/perf/hv-24x7: Use per-cpu page buffer
The 24x7 counters are continuously running and not updated on an interrupt.
So we record the event counts when stopping the event or deleting it.
But to "read" a single counter in 24x7, we allocate a page and pass it
into the hypervisor (The HV returns the page full of counters from which
we extract the specific counter for this event).
We allocate a page using GFP_USER and when deleting the event, we end up
with the following warning because we are blocking in interrupt context.
[ 698.641709] BUG: scheduling while atomic: swapper/0/0/0x10010000
We could use GFP_ATOMIC but that could result in failures. Pre-allocate
a buffer so we don't have to allocate in interrupt context. Further as
Michael Ellerman suggested, use Per-CPU buffer so we only need to allocate
once per CPU.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
arch/powerpc/perf/hv-24x7.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
Changelog[v2]:
[Michael Ellerman] Ensure buffer is aligned to 4K.
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index dba3408..d073e06 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -217,11 +217,14 @@ static bool is_physical_domain(int domain)
domain == HV_24X7_PERF_DOMAIN_PHYSICAL_CORE;
}
+DEFINE_PER_CPU(char, hv_24x7_reqb[4096]) __aligned(4096);
+DEFINE_PER_CPU(char, hv_24x7_resb[4096]) __aligned(4096);
+
static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
u16 lpar, u64 *res,
bool success_expected)
{
- unsigned long ret = -ENOMEM;
+ unsigned long ret;
/*
* request_buffer and result_buffer are not required to be 4k aligned,
@@ -243,13 +246,11 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
BUILD_BUG_ON(sizeof(*request_buffer) > 4096);
BUILD_BUG_ON(sizeof(*result_buffer) > 4096);
- request_buffer = kmem_cache_zalloc(hv_page_cache, GFP_USER);
- if (!request_buffer)
- goto out;
+ request_buffer = (void *)get_cpu_var(hv_24x7_reqb);
+ result_buffer = (void *)get_cpu_var(hv_24x7_resb);
- result_buffer = kmem_cache_zalloc(hv_page_cache, GFP_USER);
- if (!result_buffer)
- goto out_free_request_buffer;
+ memset(request_buffer, 0, 4096);
+ memset(result_buffer, 0, 4096);
*request_buffer = (struct reqb) {
.buf = {
@@ -278,15 +279,11 @@ static unsigned long single_24x7_request(u8 domain, u32 offset, u16 ix,
domain, offset, ix, lpar, ret, ret,
result_buffer->buf.detailed_rc,
result_buffer->buf.failing_request_ix);
- goto out_free_result_buffer;
+ goto out;
}
*res = be64_to_cpu(result_buffer->result);
-out_free_result_buffer:
- kfree(result_buffer);
-out_free_request_buffer:
- kfree(request_buffer);
out:
return ret;
}
--
1.8.3.1
^ permalink raw reply related
* [PATCH 0/4] powerpc32: fix of PTE accessors and handle inverted HW bits via PTE accessors
From: Christophe Leroy @ 2014-12-10 18:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: scottwood, linuxppc-dev, linux-kernel
Some powerpc like the 8xx do invert some PTE bits in HW. In order to avoid
having to invert the bits each time we set them into hardware, this patch adds
the invertion logic into the PTE accessors in order to get them already properly
inversed in the tables.
Patchset:
1) powerpc32: misuse of accessors to pte_t objects
2) powerpc32: properly clear page table when 0 is not a good default PTE value
3) powerpc32: adds direct support to hardware inverted values in pte accessors
4) powerpc32/8xx: invert _PAGE_RW bit in PTE accessors
All changes have been successfully tested on MPC885
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Tested-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/page.h | 8 +++----
arch/powerpc/include/asm/pgtable-ppc32.h | 37 +++++++++++++++++++++-----------
arch/powerpc/include/asm/pgtable.h | 17 ++++++++-------
arch/powerpc/include/asm/pte-8xx.h | 1 +
arch/powerpc/include/asm/pte-common.h | 3 +++
arch/powerpc/kernel/head_8xx.S | 3 ---
arch/powerpc/mm/pgtable_32.c | 14 ++++++++++++
7 files changed, 56 insertions(+), 27 deletions(-)
^ permalink raw reply
* [PATCH 1/4] powerpc32: misuse of accessors to pte_t objects
From: Christophe Leroy @ 2014-12-10 18:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
scottwood
Cc: linuxppc-dev, linux-kernel
pte_val() is not meant to be used as L value.
__pte() has to be used to assign value to pte_t.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/pgtable.h | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 316f9a5..5d4fdcc 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -115,24 +115,25 @@ static inline unsigned long pte_pfn(pte_t pte) {
/* Generic modifiers for PTE bits */
static inline pte_t pte_wrprotect(pte_t pte) {
- pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
+ pte = __pte(pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE)); return pte; }
static inline pte_t pte_mkclean(pte_t pte) {
- pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
+ pte = __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
+ return pte; }
static inline pte_t pte_mkold(pte_t pte) {
- pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+ pte = __pte(pte_val(pte) & ~_PAGE_ACCESSED); return pte; }
static inline pte_t pte_mkwrite(pte_t pte) {
- pte_val(pte) |= _PAGE_RW; return pte; }
+ pte = __pte(pte_val(pte) | _PAGE_RW); return pte; }
static inline pte_t pte_mkdirty(pte_t pte) {
- pte_val(pte) |= _PAGE_DIRTY; return pte; }
+ pte = __pte(pte_val(pte) | _PAGE_DIRTY); return pte; }
static inline pte_t pte_mkyoung(pte_t pte) {
- pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+ pte = __pte(pte_val(pte) | _PAGE_ACCESSED); return pte; }
static inline pte_t pte_mkspecial(pte_t pte) {
- pte_val(pte) |= _PAGE_SPECIAL; return pte; }
+ pte = __pte(pte_val(pte) | _PAGE_SPECIAL); return pte; }
static inline pte_t pte_mkhuge(pte_t pte) {
return pte; }
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
- pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+ pte = __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
return pte;
}
--
2.1.0
^ permalink raw reply related
* [PATCH 2/4] powerpc32: properly clear page table when 0 is not a good default PTE value
From: Christophe Leroy @ 2014-12-10 18:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
scottwood
Cc: linuxppc-dev, linux-kernel
Some HW invert some PTE bits. In some case, __pte(0) is not 0 so the PTEs shall
be properly set prior to being used.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/mm/pgtable_32.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index a349089..71a2821 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -96,6 +96,14 @@ void pgd_free(struct mm_struct *mm, pgd_t *pgd)
#endif
}
+static inline void pte_alloc_clear(pte_t *pte)
+{
+ int i;
+
+ for (i = 0; i < PTRS_PER_PTE; i++)
+ pte[i] = __pte(0);
+}
+
__init_refok pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
{
pte_t *pte;
@@ -109,18 +117,24 @@ __init_refok pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long add
if (pte)
clear_page(pte);
}
+ if (pte && !pte_none(*pte))
+ pte_alloc_clear(pte);
return pte;
}
pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *ptepage;
+ pte_t *pte;
gfp_t flags = GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO;
ptepage = alloc_pages(flags, 0);
if (!ptepage)
return NULL;
+ pte = (pte_t *)pfn_to_kaddr(page_to_pfn(ptepage));
+ if (!pte_none(*pte))
+ pte_alloc_clear(pte);
if (!pgtable_page_ctor(ptepage)) {
__free_page(ptepage);
return NULL;
--
2.1.0
^ permalink raw reply related
* [PATCH 3/4] powerpc32: adds direct support to hardware inverted values in pte accessors
From: Christophe Leroy @ 2014-12-10 18:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
scottwood
Cc: linuxppc-dev, linux-kernel
Some powerpc like the 8xx do invert some PTE bits in HW. In order to avoid
having to invert the bits each time we set them into hardware, this patch adds
the invertion logic into the PTE accessors in order to get them already properly
inversed in the tables.
Inverted bits can be defined by _PTE_HW_INVERTED into the pte-XXX.h file
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/page.h | 8 +++----
arch/powerpc/include/asm/pgtable-ppc32.h | 37 +++++++++++++++++++++-----------
arch/powerpc/include/asm/pte-common.h | 3 +++
3 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
index 26fe1ae..2e7a3ff 100644
--- a/arch/powerpc/include/asm/page.h
+++ b/arch/powerpc/include/asm/page.h
@@ -285,8 +285,8 @@ extern long long virt_phys_offset;
/* PTE level */
typedef struct { pte_basic_t pte; } pte_t;
-#define pte_val(x) ((x).pte)
-#define __pte(x) ((pte_t) { (x) })
+#define pte_val(x) ((x).pte ^ _PTE_HW_INVERTED)
+#define __pte(x) ((pte_t) { ((x) ^ _PTE_HW_INVERTED) })
/* 64k pages additionally define a bigger "real PTE" type that gathers
* the "second half" part of the PTE for pseudo 64k pages
@@ -328,8 +328,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
*/
typedef pte_basic_t pte_t;
-#define pte_val(x) (x)
-#define __pte(x) (x)
+#define pte_val(x) ((x) ^ _PTE_HW_INVERTED)
+#define __pte(x) ((x) ^ _PTE_HW_INVERTED)
#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_STD_MMU_64)
typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index 543bb8e..0e4a2a7 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -162,6 +162,12 @@ extern void flush_hash_entry(struct mm_struct *mm, pte_t *ptep,
* to properly flush the virtually tagged instruction cache of
* those implementations.
*/
+#if _PTE_HW_INVERTED == 0
+#define PTE_INVERT(val,flags)
+#else
+#define PTE_INVERT(val,flags) "xori "#val","#val","#flags"\n"
+#endif
+
#ifndef CONFIG_PTE_64BIT
static inline unsigned long pte_update(pte_t *p,
unsigned long clr,
@@ -174,30 +180,34 @@ static inline unsigned long pte_update(pte_t *p,
unsigned long tmp2;
__asm__ __volatile__("\
-1: lwarx %0,0,%4\n\
- andc %1,%0,%5\n\
+1: lwarx %0,0,%4\n"
+ PTE_INVERT(%0,%8)
+" andc %1,%0,%5\n\
or %1,%1,%6\n\
/* 0x200 == Extended encoding, bit 22 */ \
/* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
- or %1,%3,%1\n\
- xori %1,%1,0x200\n"
-" stwcx. %1,0,%4\n\
+ or %1,%3,%1\n \
+ xori %1,%1,%9\n\
+ stwcx. %1,0,%4\n\
bne- 1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
- : "r" (p), "r" (clr), "r" (set), "m" (*p)
+ : "r" (p), "r" (clr), "r" (set), "m" (*p), "i"(_PTE_HW_INVERTED),
+ "i"(_PTE_HW_INVERTED|0x200)
: "cc" );
#else /* CONFIG_PPC_8xx */
__asm__ __volatile__("\
-1: lwarx %0,0,%3\n\
- andc %1,%0,%4\n\
+1: lwarx %0,0,%3\n"
+ PTE_INVERT(%0,%7)
+" andc %1,%0,%4\n\
or %1,%1,%5\n"
+ PTE_INVERT(%1,%7)
PPC405_ERR77(0,%3)
" stwcx. %1,0,%3\n\
bne- 1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" (clr), "r" (set), "m" (*p)
+ : "r" (p), "r" (clr), "r" (set), "m" (*p), "i"(_PTE_HW_INVERTED)
: "cc" );
#endif /* CONFIG_PPC_8xx */
#else /* PTE_ATOMIC_UPDATES */
@@ -222,14 +232,17 @@ static inline unsigned long long pte_update(pte_t *p,
__asm__ __volatile__("\
1: lwarx %L0,0,%4\n\
- lwzx %0,0,%3\n\
- andc %1,%L0,%5\n\
+ lwzx %0,0,%3\n"
+ PTE_INVERT(%L0,%8)
+" andc %1,%L0,%5\n\
or %1,%1,%6\n"
+ PTE_INVERT(%1,%8)
PPC405_ERR77(0,%3)
" stwcx. %1,0,%4\n\
bne- 1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p)
- : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
+ : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p),
+ "i"(_PTE_HW_INVERTED)
: "cc" );
#else /* PTE_ATOMIC_UPDATES */
unsigned long long old = pte_val(*p);
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index e040c35..3d635fb 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -59,6 +59,9 @@
#ifndef _PTE_NONE_MASK
#define _PTE_NONE_MASK _PAGE_HPTEFLAGS
#endif
+#ifndef _PTE_HW_INVERTED
+#define _PTE_HW_INVERTED 0
+#endif
/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
* kernel without large page PMD support
--
2.1.0
^ permalink raw reply related
* [PATCH 4/4] powerpc32/8xx: invert _PAGE_RW bit in PTE accessors
From: Christophe Leroy @ 2014-12-10 18:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
scottwood
Cc: linuxppc-dev, linux-kernel
The 8xx inverts _PAGE_RW. Lets to it in PTE accessors.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/pte-8xx.h | 1 +
arch/powerpc/kernel/head_8xx.S | 3 ---
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index daa4616..57bad0a 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -57,6 +57,7 @@
#define _PMD_PAGE_8M 0x000c
#define _PTE_NONE_MASK _PAGE_KNLRO
+#define _PTE_HW_INVERTED _PAGE_RW
/* Until my rework is finished, 8xx still needs atomic PTE updates */
#define PTE_ATOMIC_UPDATES 1
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 3d4b8ee..807b0db 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -441,9 +441,6 @@ DataStoreTLBMiss:
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
#endif
- /* invert RW */
- xori r10, r10, _PAGE_RW
-
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
--
2.1.0
^ permalink raw reply related
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