* Re: [PATCH v4 1/5] powerpc/mm/slice: Remove intermediate bitmap copy
From: Nicholas Piggin @ 2018-02-10 14:43 UTC (permalink / raw)
To: Christophe Leroy
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, aneesh.kumar, linux-kernel, linuxppc-dev
In-Reply-To: <01e8f783db8f4d4d41df91e0400a8634272b326f.1518226173.git.christophe.leroy@c-s.fr>
On Sat, 10 Feb 2018 13:54:25 +0100 (CET)
Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> bitmap_or() and bitmap_andnot() can work properly with dst identical
> to src1 or src2. There is no need of an intermediate result bitmap
> that is copied back to dst in a second step.
Everyone seems to be working on the slice code all of a sudden. I
had the same change in my series I just posted, but I didn't notice
this one of yours earlier, and it's better split out, so this is
fine by me.
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> v2: New in v2
> v3: patch moved up front of the serie to avoid ephemeral slice_bitmap_copy() function in following patch
> v4: No change
>
> arch/powerpc/mm/slice.c | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
> index 23ec2c5e3b78..98b53d48968f 100644
> --- a/arch/powerpc/mm/slice.c
> +++ b/arch/powerpc/mm/slice.c
> @@ -388,21 +388,17 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
>
> static inline void slice_or_mask(struct slice_mask *dst, struct slice_mask *src)
> {
> - DECLARE_BITMAP(result, SLICE_NUM_HIGH);
> -
> dst->low_slices |= src->low_slices;
> - bitmap_or(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
> - bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
> + bitmap_or(dst->high_slices, dst->high_slices, src->high_slices,
> + SLICE_NUM_HIGH);
> }
>
> static inline void slice_andnot_mask(struct slice_mask *dst, struct slice_mask *src)
> {
> - DECLARE_BITMAP(result, SLICE_NUM_HIGH);
> -
> dst->low_slices &= ~src->low_slices;
>
> - bitmap_andnot(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
> - bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
> + bitmap_andnot(dst->high_slices, dst->high_slices, src->high_slices,
> + SLICE_NUM_HIGH);
> }
>
> #ifdef CONFIG_PPC_64K_PAGES
^ permalink raw reply
* Re: [PATCH v4 1/5] powerpc/mm/slice: Remove intermediate bitmap copy
From: Christophe LEROY @ 2018-02-10 14:57 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, aneesh.kumar, linux-kernel, linuxppc-dev
In-Reply-To: <20180211004309.2eda56a3@roar.ozlabs.ibm.com>
Le 10/02/2018 à 15:43, Nicholas Piggin a écrit :
> On Sat, 10 Feb 2018 13:54:25 +0100 (CET)
> Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>
>> bitmap_or() and bitmap_andnot() can work properly with dst identical
>> to src1 or src2. There is no need of an intermediate result bitmap
>> that is copied back to dst in a second step.
>
> Everyone seems to be working on the slice code all of a sudden. I
> had the same change in my series I just posted, but I didn't notice
> this one of yours earlier, and it's better split out, so this is
> fine by me.
Thanks,
I had a quick look at your serie, it looks promising.
The main purpose of mine is to allow the use of slies on the 8xx in
order to fix a hugepage related bug.
Your serie is performance oriented and seems nice, indeed I should have
noticed that it was passing huge structures instead of pointers to
subfunctions. I will look at your serie more in details next week.
Christophe
>
> Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
>
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
>> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> ---
>> v2: New in v2
>> v3: patch moved up front of the serie to avoid ephemeral slice_bitmap_copy() function in following patch
>> v4: No change
>>
>> arch/powerpc/mm/slice.c | 12 ++++--------
>> 1 file changed, 4 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
>> index 23ec2c5e3b78..98b53d48968f 100644
>> --- a/arch/powerpc/mm/slice.c
>> +++ b/arch/powerpc/mm/slice.c
>> @@ -388,21 +388,17 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
>>
>> static inline void slice_or_mask(struct slice_mask *dst, struct slice_mask *src)
>> {
>> - DECLARE_BITMAP(result, SLICE_NUM_HIGH);
>> -
>> dst->low_slices |= src->low_slices;
>> - bitmap_or(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
>> - bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
>> + bitmap_or(dst->high_slices, dst->high_slices, src->high_slices,
>> + SLICE_NUM_HIGH);
>> }
>>
>> static inline void slice_andnot_mask(struct slice_mask *dst, struct slice_mask *src)
>> {
>> - DECLARE_BITMAP(result, SLICE_NUM_HIGH);
>> -
>> dst->low_slices &= ~src->low_slices;
>>
>> - bitmap_andnot(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
>> - bitmap_copy(dst->high_slices, result, SLICE_NUM_HIGH);
>> + bitmap_andnot(dst->high_slices, dst->high_slices, src->high_slices,
>> + SLICE_NUM_HIGH);
>> }
>>
>> #ifdef CONFIG_PPC_64K_PAGES
^ permalink raw reply
* Re: [RFC][PATCH bpf 1/2] bpf: allow 64-bit offsets for bpf function calls
From: Sandipan Das @ 2018-02-10 16:36 UTC (permalink / raw)
To: Alexei Starovoitov; +Cc: Naveen N. Rao, daniel, linuxppc-dev, mpe, netdev
In-Reply-To: <5a552a19-5600-1fd4-57f2-6337127b75e9@fb.com>
On 02/10/2018 06:08 AM, Alexei Starovoitov wrote:
> On 2/9/18 8:54 AM, Naveen N. Rao wrote:
>> Naveen N. Rao wrote:
>>> Alexei Starovoitov wrote:
>>>> On 2/8/18 4:03 AM, Sandipan Das wrote:
>>>>> The imm field of a bpf_insn is a signed 32-bit integer. For
>>>>> JIT-ed bpf-to-bpf function calls, it stores the offset from
>>>>> __bpf_call_base to the start of the callee function.
>>>>>
>>>>> For some architectures, such as powerpc64, it was found that
>>>>> this offset may be as large as 64 bits because of which this
>>>>> cannot be accomodated in the imm field without truncation.
>>>>>
>>>>> To resolve this, we additionally use the aux data within each
>>>>> bpf_prog associated with the caller functions to store the
>>>>> addresses of their respective callees.
>>>>>
>>>>> Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
>>>>> ---
>>>>> kernel/bpf/verifier.c | 39 ++++++++++++++++++++++++++++++++++++++-
>>>>> 1 file changed, 38 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c
>>>>> index 5fb69a85d967..52088b4ca02f 100644
>>>>> --- a/kernel/bpf/verifier.c
>>>>> +++ b/kernel/bpf/verifier.c
>>>>> @@ -5282,6 +5282,19 @@ static int jit_subprogs(struct
>>>>> bpf_verifier_env *env)
>>>>> * run last pass of JIT
>>>>> */
>>>>> for (i = 0; i <= env->subprog_cnt; i++) {
>>>>> + u32 flen = func[i]->len, callee_cnt = 0;
>>>>> + struct bpf_prog **callee;
>>>>> +
>>>>> + /* for now assume that the maximum number of bpf function
>>>>> + * calls that can be made by a caller must be at most the
>>>>> + * number of bpf instructions in that function
>>>>> + */
>>>>> + callee = kzalloc(sizeof(func[i]) * flen, GFP_KERNEL);
>>>>> + if (!callee) {
>>>>> + err = -ENOMEM;
>>>>> + goto out_free;
>>>>> + }
>>>>> +
>>>>> insn = func[i]->insnsi;
>>>>> for (j = 0; j < func[i]->len; j++, insn++) {
>>>>> if (insn->code != (BPF_JMP | BPF_CALL) ||
>>>>> @@ -5292,6 +5305,26 @@ static int jit_subprogs(struct
>>>>> bpf_verifier_env *env)
>>>>> insn->imm = (u64 (*)(u64, u64, u64, u64, u64))
>>>>> func[subprog]->bpf_func -
>>>>> __bpf_call_base;
>>>>> +
>>>>> + /* the offset to the callee from __bpf_call_base
>>>>> + * may be larger than what the 32 bit integer imm
>>>>> + * can accomodate which will truncate the higher
>>>>> + * order bits
>>>>> + *
>>>>> + * to avoid this, we additionally utilize the aux
>>>>> + * data of each caller function for storing the
>>>>> + * addresses of every callee associated with it
>>>>> + */
>>>>> + callee[callee_cnt++] = func[subprog];
>>>>
>>>> can you share typical /proc/kallsyms ?
>>>> Are you saying that kernel and kernel modules are allocated from
>>>> address spaces that are always more than 32-bit apart?
>>>
>>> Yes. On ppc64, kernel text is linearly mapped from 0xc000000000000000,
>>> while vmalloc'ed area starts from 0xd000000000000000 (for radix, this is
>>> different, but still beyond a 32-bit offset).
>>>
>>>> That would mean that all kernel calls into modules are far calls
>>>> and the other way around form .ko into kernel?
>>>> Performance is probably suffering because every call needs to be built
>>>> with full 64-bit offset. No ?
>>>
>>> Possibly, and I think Michael can give a better perspective, but I think
>>> this is due to our ABI. For inter-module calls, we need to setup the TOC
>>> pointer (or the address of the function being called with ABIv2),
>>> which would require us to load a full address regardless.
>>
>> Thinking more about this, as an optimization, for bpf-to-bpf calls, we
>> could detect a near call and just emit a relative branch since we don't
>> care about TOC with BPF. But, this will depend on whether the different
>> BPF functions are close enough (within 32MB) of one another.
>
> so that will be just an optimization. Understood.
> How about instead of doing callee = kzalloc(sizeof(func[i]) * flen..
> we keep insn->off pointing to subprog and move
> prog->aux->func = func;
> before the last JIT pass.
> Then you won't need to alloc this extra array.
>
Agreed. Will make the necessary changes in v2.
--
With Regards,
Sandipan
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/mm: Fix crashes with PUD level hugetlb config
From: Ram Pai @ 2018-02-10 16:50 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
In-Reply-To: <87o9kxfa7d.fsf@linux.vnet.ibm.com>
On Sat, Feb 10, 2018 at 03:17:02PM +0530, Aneesh Kumar K.V wrote:
> Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> writes:
>
> > "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
> >
> >> To support memory keys, we moved the hash pte slot information to the second
> >> half of the page table. This was ok with PTE entries at level 4 and level 3.
> >> We already allocate larger page table pages at those level to accomodate extra
> >> details. For level 4 we already have the extra space which was used to track
> >> 4k hash page table entry details and at pmd level the extra space was allocated
> >> to track the THP details.
> >>
> >> With hugetlbfs PTE, we used this extra space at the PMD level to store the
> >> slot details. But we also support hugetlbfs PTE at PUD leve and PUD level page
> >> didn't allocate extra space. This resulted in memory corruption.
> >>
> >> Fix this by allocating extra space at PUD level when HUGETLB is enabled. We
> >> may need further changes to allocate larger space at PMD level when we enable
> >> HUGETLB. That will be done in next patch.
> >>
> >> Fixes:bf9a95f9a6481bc6e(" powerpc: Free up four 64K PTE bits in 64K backed HPTE pages")
> >>
> >> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> >
> > Another fix, I still get random memory corruption with hugetlb test with
> > 16G hugepage config.
>
> Another one. I am not sure whether we really want this in this form. But
> with this tests are running fine.
>
> -aneesh
>
> commit 658fe8c310a913e69e5bc9a40d4c28a3b88d5c08
> Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> Date: Sat Feb 10 13:17:34 2018 +0530
>
> powerpc/mm/hash64: memset the pagetable pages on allocation.
>
> Now that we are using second half of the table to store slot details and we
> don't clear them in the huge_pte_get_and_clear, we need to make sure we zero
> out the range on allocation. This done some extra work because the first half
> of the table is cleared by huge_pte_get_and_clear and memset in this patch
> zero-out the full table page.
>
> We need to do this for pgd and pud because both get allocated from the same slab
> cache.
Do we need to zero pgd aswell to resolve your corruption? pud is not
sufficient? Or was it done to avoid issues in the future in case pgd
is used as the leaf; possibly for Terra_huge_pages?
RP
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/mm: Fix crashes with PUD level hugetlb config
From: Aneesh Kumar K.V @ 2018-02-10 17:14 UTC (permalink / raw)
To: Ram Pai; +Cc: benh, paulus, mpe, linuxppc-dev
In-Reply-To: <20180210165010.GC5559@ram.oc3035372033.ibm.com>
On 02/10/2018 10:20 PM, Ram Pai wrote:
> On Sat, Feb 10, 2018 at 03:17:02PM +0530, Aneesh Kumar K.V wrote:
>> Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> writes:
>>
>>> "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:
>>>
>>>> To support memory keys, we moved the hash pte slot information to the second
>>>> half of the page table. This was ok with PTE entries at level 4 and level 3.
>>>> We already allocate larger page table pages at those level to accomodate extra
>>>> details. For level 4 we already have the extra space which was used to track
>>>> 4k hash page table entry details and at pmd level the extra space was allocated
>>>> to track the THP details.
>>>>
>>>> With hugetlbfs PTE, we used this extra space at the PMD level to store the
>>>> slot details. But we also support hugetlbfs PTE at PUD leve and PUD level page
>>>> didn't allocate extra space. This resulted in memory corruption.
>>>>
>>>> Fix this by allocating extra space at PUD level when HUGETLB is enabled. We
>>>> may need further changes to allocate larger space at PMD level when we enable
>>>> HUGETLB. That will be done in next patch.
>>>>
>>>> Fixes:bf9a95f9a6481bc6e(" powerpc: Free up four 64K PTE bits in 64K backed HPTE pages")
>>>>
>>>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>>>
>>> Another fix, I still get random memory corruption with hugetlb test with
>>> 16G hugepage config.
>>
>> Another one. I am not sure whether we really want this in this form. But
>> with this tests are running fine.
>>
>> -aneesh
>>
>> commit 658fe8c310a913e69e5bc9a40d4c28a3b88d5c08
>> Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> Date: Sat Feb 10 13:17:34 2018 +0530
>>
>> powerpc/mm/hash64: memset the pagetable pages on allocation.
>>
>> Now that we are using second half of the table to store slot details and we
>> don't clear them in the huge_pte_get_and_clear, we need to make sure we zero
>> out the range on allocation. This done some extra work because the first half
>> of the table is cleared by huge_pte_get_and_clear and memset in this patch
>> zero-out the full table page.
>>
>> We need to do this for pgd and pud because both get allocated from the same slab
>> cache.
>
> Do we need to zero pgd aswell to resolve your corruption? pud is not
> sufficient? Or was it done to avoid issues in the future in case pgd
> is used as the leaf; possibly for Terra_huge_pages?
>
it is the other way round, we need to zero-out pgd. pud zerout can be
optional because first half of the page table is always cleared in the
unmap path.
-aneesh
^ permalink raw reply
* Re: [PATCH v1] PCI: Make PCI_SCAN_ALL_PCIE_DEVS work for Root as well as Downstream Ports
From: Bjorn Helgaas @ 2018-02-10 15:43 UTC (permalink / raw)
To: Christian Zigotzky
Cc: linux-pci, Michael Ellerman, linuxppc-dev, linux-kernel
In-Reply-To: <33CA1586-051C-47F4-83CD-4A406FAE85F7@xenosoft.de>
On Sat, Feb 10, 2018 at 09:05:40AM +0100, Christian Zigotzky wrote:
> Hi All,
>
> The AmigaOne X1000 doesn’t boot anymore since the PCI updates. I
> have seen, that the PCI updates are different to the updates below.
> The code below works but the latest not. Is there a problem with the
> latest PCI updates currently?
I'm not aware of a problem, and it *looks* like the patch below is in
Linus' tree (I'm looking at 9a61df9e5f74 ("Merge tag 'kbuild-v4.16-2'
of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-kbuild")).
I assume you're still booting with "pci=pcie_scan_all", since I don't
think we ever got a quirk to set PCI_SCAN_ALL_PCIE_DEVS automatically.
If AmigaOne X1000 doesn't boot with "pci=pcie_scan_all", can you diff
the working only_one_child() with the current upstream? I compared
the version in my pci/enumeration branch with what's upstream, and
they're identical. So maybe the original patch I applied was wrong?
If you have a patch that works, can you post it and maybe I can sort
out what's different?
> On 2. Dec 2017, at 20:18, Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> On Fri, Dec 01, 2017 at 06:27:10PM -0600, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> PCIe Downstream Ports normally have only a Device 0 below them. To
> optimize enumeration, we don't scan for other devices *unless* the
> PCI_SCAN_ALL_PCIE_DEVS flag is set by set by quirks or the
> "pci=pcie_scan_all" kernel parameter.
>
> Previously PCI_SCAN_ALL_PCIE_DEVS only affected scanning below Switch
> Downstream Ports, not Root Ports.
>
> But the "Nemo" system, also known as the AmigaOne X1000, has a PA Semi Root
> Port whose link leads to an AMD/ATI SB600 South Bridge. The Root Port is a
> PCIe device, of course, but the SB600 contains only conventional PCI
> devices with no visible PCIe port.
>
> Simplify and restructure only_one_child() so that we scan for all possible
> devices below Root Ports as well as Switch Downstream Ports when
> PCI_SCAN_ALL_PCIE_DEVS is set.
>
> This is enough to make Nemo work with "pci=pcie_scan_all". We would also
> like to add a quirk to set PCI_SCAN_ALL_PCIE_DEVS automatically on Nemo so
> users wouldn't have to use the "pci=pcie_scan_all" parameter, but we don't
> have that yet.
>
> Link: https://lkml.kernel.org/r/CAErSpo55Q8Q=5p6_+uu7ahnw+53ibVDNRXxrzRV9QnUr_9EUfw@mail.gmail.com
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=198057
> Reported-and-Tested-by: Christian Zigotzky <chzigotzky@xenosoft.de>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>
> Applied to pci/enumeration for v4.16.
>
> ---
> drivers/pci/probe.c | 25 +++++++++++++++----------
> 1 file changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 14e0ea1ff38b..303c0cb0550c 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2215,22 +2215,27 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
>
> static int only_one_child(struct pci_bus *bus)
> {
> - struct pci_dev *parent = bus->self;
> + struct pci_dev *bridge = bus->self;
>
> - if (!parent || !pci_is_pcie(parent))
> + /*
> + * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
> + * we scan for all possible devices, not just Device 0.
> + */
> + if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
> return 0;
> - if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
> - return 1;
>
> /*
> - * PCIe downstream ports are bridges that normally lead to only a
> - * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
> - * possible devices, not just device 0. See PCIe spec r3.0,
> - * sec 7.3.1.
> + * A PCIe Downstream Port normally leads to a Link with only Device
> + * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
> + * only for Device 0 in that situation.
> + *
> + * Checking has_secondary_link is a hack to identify Downstream
> + * Ports because sometimes Switches are configured such that the
> + * PCIe Port Type labels are backwards.
> */
> - if (parent->has_secondary_link &&
> - !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
> + if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
> return 1;
> +
> return 0;
> }
>
^ permalink raw reply
* [GIT PULL] PCI fixes for v4.16
From: Bjorn Helgaas @ 2018-02-10 18:09 UTC (permalink / raw)
To: Linus Torvalds
Cc: linux-pci, linux-kernel, Lorenzo Pieralisi, Alexey Kardashevskiy,
Michael Ellerman, Rob Herring, Benjamin Herrenschmidt,
Paul Mackerras, Alistair Popple, linuxppc-dev
PCI fixes:
- fix POWER9/powernv INTx regression from the merge window (Alexey
Kardashevskiy)
The following changes since commit ab8c609356fbe8dbcd44df11e884ce8cddf3739e:
Merge branch 'pci/spdx' into next (2018-02-01 11:40:07 -0600)
are available in the Git repository at:
ssh://git@gitolite.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git tags/pci-v4.16-fixes-1
for you to fetch changes up to c591c2e36ccc9a08f265841d2fd68e35327ab3c4:
powerpc/pci: Fix broken INTx configuration via OF (2018-02-10 11:49:56 -0600)
----------------------------------------------------------------
pci-v4.16-fixes-1
----------------------------------------------------------------
Alexey Kardashevskiy (1):
powerpc/pci: Fix broken INTx configuration via OF
arch/powerpc/kernel/pci-common.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
^ permalink raw reply
* Re: [PATCH kernel v3] powerpc/pci: Fix broken INTx configuration via OF
From: Bjorn Helgaas @ 2018-02-10 20:51 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: linuxppc-dev, Benjamin Herrenschmidt, Bjorn Helgaas,
Michael Ellerman, Rob Herring, linux-pci
In-Reply-To: <20180209180741.GB206223@bhelgaas-glaptop.roam.corp.google.com>
On Fri, Feb 09, 2018 at 12:07:41PM -0600, Bjorn Helgaas wrote:
> On Fri, Feb 09, 2018 at 05:23:58PM +1100, Alexey Kardashevskiy wrote:
> > Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
> > replaced of_irq_parse_pci() + irq_create_of_mapping() with
> > of_irq_parse_and_map_pci() but this change lost virq returned by
> > irq_create_of_mapping() so virq remained zero causing INTx
> > misconfiguration.
> >
> > This fixes pci_read_irq_line() not to loose a virq returned by
> > of_irq_parse_and_map_pci().
>
> s/not to loose a/to not lose the/
>
> > Fixes: 59f47eff03a0 "powerpc/pci: Use of_irq_parse_and_map_pci() helper"
> > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>
> I'm fine with this version.
>
> Since you started applying a previous version, Michael, I'll assume
> you will handle this unless you tell me otherwise. One way or another
> it would be good to get this in before -rc1.
I went ahead and applied this and asked Linus to pull it.
> > ---
> > Changes:
> > v3:
> > * change virq from unsigned to int as of_irq_parse_and_map_pci returns int
> > and even though it only returns non-negative values now, this may change
> > in the future
> >
> > v2:
> > * changed the condition from <=0 to !=0 as by design
> > of_irq_parse_and_map_pci() can only return 0 for an error and virq>0.
> > ---
> > arch/powerpc/kernel/pci-common.c | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
> > index ae2ede4..446c796 100644
> > --- a/arch/powerpc/kernel/pci-common.c
> > +++ b/arch/powerpc/kernel/pci-common.c
> > @@ -362,7 +362,7 @@ struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
> > */
> > static int pci_read_irq_line(struct pci_dev *pci_dev)
> > {
> > - unsigned int virq = 0;
> > + int virq;
> >
> > pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
> >
> > @@ -370,7 +370,8 @@ static int pci_read_irq_line(struct pci_dev *pci_dev)
> > memset(&oirq, 0xff, sizeof(oirq));
> > #endif
> > /* Try to get a mapping from the device-tree */
> > - if (!of_irq_parse_and_map_pci(pci_dev, 0, 0)) {
> > + virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
> > + if (virq <= 0) {
> > u8 line, pin;
> >
> > /* If that fails, lets fallback to what is in the config
> > --
> > 2.11.0
> >
^ permalink raw reply
* Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32
From: Nicholas Piggin @ 2018-02-11 13:59 UTC (permalink / raw)
To: Christophe Leroy
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, aneesh.kumar, linux-kernel, linuxppc-dev
In-Reply-To: <0ac518636ae1e601ea0732dd69b48dcd0f347285.1518226173.git.christophe.leroy@c-s.fr>
On Sat, 10 Feb 2018 13:54:27 +0100 (CET)
Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> In preparation for the following patch which will fix an issue on
> the 8xx by re-using the 'slices', this patch enhances the
> 'slices' implementation to support 32 bits CPUs.
>
> On PPC32, the address space is limited to 4Gbytes, hence only the low
> slices will be used.
>
> This patch moves "slices" functions prototypes from page64.h to slice.h
>
> The high slices use bitmaps. As bitmap functions are not prepared to
> handling bitmaps of size 0, the bitmap_xxx() calls are wrapped into
> slice_bitmap_xxx() functions which will void on PPC32
On this last point, I think it would be better to put these with the
existing slice bitmap functions in slice.c and just have a few #ifdefs
for SLICE_NUM_HIGH == 0.
Thanks,
Nick
^ permalink raw reply
* [PATCH V2 1/4] powerpc/mm: Fix crashes with PUD level hugetlb config
From: Aneesh Kumar K.V @ 2018-02-11 15:00 UTC (permalink / raw)
To: benh, paulus, mpe, Ram Pai; +Cc: linuxppc-dev, Aneesh Kumar K.V
To support memory keys, we moved the hash pte slot information to the second
half of the page table. This was ok with PTE entries at level 4 and level 3.
We already allocate larger page table pages at those level to accomodate extra
details. For level 4 we already have the extra space which was used to track
4k hash page table entry details and at pmd level the extra space was allocated
to track the THP details.
With hugetlbfs PTE, we used this extra space at the PMD level to store the
slot details. But we also support hugetlbfs PTE at PUD leve and PUD level page
didn't allocate extra space. This resulted in memory corruption.
Fix this by allocating extra space at PUD level when HUGETLB is enabled. We
may need further changes to allocate larger space at PMD level when we enable
HUGETLB. That will be done in next patch.
Fixes:bf9a95f9a6481bc6e(" powerpc: Free up four 64K PTE bits in 64K backed HPTE pages")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/32/pgtable.h | 1 +
arch/powerpc/include/asm/book3s/64/hash-64k.h | 5 +++++
arch/powerpc/include/asm/book3s/64/hash.h | 10 ++++++++++
arch/powerpc/include/asm/book3s/64/pgalloc.h | 6 +++---
arch/powerpc/include/asm/book3s/64/pgtable.h | 2 ++
arch/powerpc/include/asm/nohash/32/pgtable.h | 1 +
arch/powerpc/include/asm/nohash/64/pgtable.h | 1 +
arch/powerpc/mm/hash_utils_64.c | 1 +
arch/powerpc/mm/init-common.c | 4 ++--
arch/powerpc/mm/pgtable-radix.c | 1 +
arch/powerpc/mm/pgtable_64.c | 2 ++
11 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h
index 30a155c0a6b0..c615abdce119 100644
--- a/arch/powerpc/include/asm/book3s/32/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
@@ -16,6 +16,7 @@
#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
#define PMD_CACHE_INDEX PMD_INDEX_SIZE
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 338b7da468ce..c08b3b032ec0 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -146,7 +146,12 @@ static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long a
#else
#define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
#endif
+#ifdef CONFIG_HUGETLB_PAGE
+#define H_PUD_TABLE_SIZE ((sizeof(pud_t) << PUD_INDEX_SIZE) + \
+ (sizeof(unsigned long) << PUD_INDEX_SIZE))
+#else
#define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
+#endif
#define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 0920eff731b3..234f141fb151 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -32,6 +32,16 @@
#else
#define H_PMD_CACHE_INDEX H_PMD_INDEX_SIZE
#endif
+/*
+ * We not store the slot details in the second half of page table.
+ * Increase the pud level table so that hugetlb ptes can be stored
+ * at pud level.
+ */
+#if defined(CONFIG_HUGETLB_PAGE) && defined(CONFIG_PPC_64K_PAGES)
+#define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE + 1)
+#else
+#define H_PUD_CACHE_INDEX (H_PUD_INDEX_SIZE)
+#endif
/*
* Define the address range of the kernel non-linear virtual area
*/
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index 1fcfa425cefa..53df86d3cfce 100644
--- a/arch/powerpc/include/asm/book3s/64/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/64/pgalloc.h
@@ -93,13 +93,13 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
{
- return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE),
+ return kmem_cache_alloc(PGT_CACHE(PUD_CACHE_INDEX),
pgtable_gfp_flags(mm, GFP_KERNEL));
}
static inline void pud_free(struct mm_struct *mm, pud_t *pud)
{
- kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud);
+ kmem_cache_free(PGT_CACHE(PUD_CACHE_INDEX), pud);
}
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
@@ -115,7 +115,7 @@ static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
* ahead and flush the page walk cache
*/
flush_tlb_pgtable(tlb, address);
- pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE);
+ pgtable_free_tlb(tlb, pud, PUD_CACHE_INDEX);
}
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 51017726d495..1c8c88e90553 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -232,11 +232,13 @@ extern unsigned long __pmd_index_size;
extern unsigned long __pud_index_size;
extern unsigned long __pgd_index_size;
extern unsigned long __pmd_cache_index;
+extern unsigned long __pud_cache_index;
#define PTE_INDEX_SIZE __pte_index_size
#define PMD_INDEX_SIZE __pmd_index_size
#define PUD_INDEX_SIZE __pud_index_size
#define PGD_INDEX_SIZE __pgd_index_size
#define PMD_CACHE_INDEX __pmd_cache_index
+#define PUD_CACHE_INDEX __pud_cache_index
/*
* Because of use of pte fragments and THP, size of page table
* are not always derived out of index size above.
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index 504a3c36ce5c..03bbd1149530 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -24,6 +24,7 @@ extern int icache_44x_need_flush;
#define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
#define PMD_CACHE_INDEX PMD_INDEX_SIZE
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index abddf5830ad5..5c5f75d005ad 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -27,6 +27,7 @@
#else
#define PMD_CACHE_INDEX PMD_INDEX_SIZE
#endif
+#define PUD_CACHE_INDEX PUD_INDEX_SIZE
/*
* Define the address range of the kernel non-linear virtual area
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 7d07c7e17db6..cf290d415dcd 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -1008,6 +1008,7 @@ void __init hash__early_init_mmu(void)
__pmd_index_size = H_PMD_INDEX_SIZE;
__pud_index_size = H_PUD_INDEX_SIZE;
__pgd_index_size = H_PGD_INDEX_SIZE;
+ __pud_cache_index = H_PUD_CACHE_INDEX;
__pmd_cache_index = H_PMD_CACHE_INDEX;
__pte_table_size = H_PTE_TABLE_SIZE;
__pmd_table_size = H_PMD_TABLE_SIZE;
diff --git a/arch/powerpc/mm/init-common.c b/arch/powerpc/mm/init-common.c
index eb8c6c8c4851..2b656e67f2ea 100644
--- a/arch/powerpc/mm/init-common.c
+++ b/arch/powerpc/mm/init-common.c
@@ -100,6 +100,6 @@ void pgtable_cache_init(void)
* same size as either the pgd or pmd index except with THP enabled
* on book3s 64
*/
- if (PUD_INDEX_SIZE && !PGT_CACHE(PUD_INDEX_SIZE))
- pgtable_cache_add(PUD_INDEX_SIZE, pud_ctor);
+ if (PUD_CACHE_INDEX && !PGT_CACHE(PUD_CACHE_INDEX))
+ pgtable_cache_add(PUD_CACHE_INDEX, pud_ctor);
}
diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c
index 573a9a2ee455..27d096610369 100644
--- a/arch/powerpc/mm/pgtable-radix.c
+++ b/arch/powerpc/mm/pgtable-radix.c
@@ -535,6 +535,7 @@ void __init radix__early_init_mmu(void)
__pmd_index_size = RADIX_PMD_INDEX_SIZE;
__pud_index_size = RADIX_PUD_INDEX_SIZE;
__pgd_index_size = RADIX_PGD_INDEX_SIZE;
+ __pud_cache_index = RADIX_PUD_INDEX_SIZE;
__pmd_cache_index = RADIX_PMD_INDEX_SIZE;
__pte_table_size = RADIX_PTE_TABLE_SIZE;
__pmd_table_size = RADIX_PMD_TABLE_SIZE;
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index c9a623c2d8a2..a0f8928c0b86 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -82,6 +82,8 @@ unsigned long __pgd_index_size;
EXPORT_SYMBOL(__pgd_index_size);
unsigned long __pmd_cache_index;
EXPORT_SYMBOL(__pmd_cache_index);
+unsigned long __pud_cache_index;
+EXPORT_SYMBOL(__pud_cache_index);
unsigned long __pte_table_size;
EXPORT_SYMBOL(__pte_table_size);
unsigned long __pmd_table_size;
--
2.14.3
^ permalink raw reply related
* [PATCH V2 2/4] powerpc/mm/hash64: Allocate larger PMD table if hugetlb config is enabled.
From: Aneesh Kumar K.V @ 2018-02-11 15:00 UTC (permalink / raw)
To: benh, paulus, mpe, Ram Pai; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <20180211150009.21297-1-aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/book3s/64/hash.h | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index c08b3b032ec0..ee440fb3d240 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -140,7 +140,7 @@ static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long a
}
#define H_PTE_TABLE_SIZE PTE_FRAG_SIZE
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE)
#define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \
(sizeof(unsigned long) << PMD_INDEX_SIZE))
#else
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 234f141fb151..0851c328bea6 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -23,7 +23,8 @@
H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
#define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
-#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_PPC_64K_PAGES)
+#if (defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)) && \
+ defined(CONFIG_PPC_64K_PAGES)
/*
* only with hash 64k we need to use the second half of pmd page table
* to store pointer to deposited pgtable_t
--
2.14.3
^ permalink raw reply related
* [PATCH V2 3/4] powerpc/mm/hash64: Store the slot information at the right offset.
From: Aneesh Kumar K.V @ 2018-02-11 15:00 UTC (permalink / raw)
To: benh, paulus, mpe, Ram Pai; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <20180211150009.21297-1-aneesh.kumar@linux.vnet.ibm.com>
The hugetlb pte entries are at the PMD and PUD level. Use the right offset
for them to get the second half of the table.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/64/hash-4k.h | 3 ++-
arch/powerpc/include/asm/book3s/64/hash-64k.h | 9 +++++----
arch/powerpc/include/asm/book3s/64/pgtable.h | 2 +-
arch/powerpc/mm/hash64_4k.c | 4 ++--
arch/powerpc/mm/hash64_64k.c | 8 ++++----
arch/powerpc/mm/hugetlbpage-hash64.c | 10 +++++++---
arch/powerpc/mm/tlb_hash64.c | 9 +++++++--
7 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index 949d691094a4..67c5475311ee 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -63,7 +63,8 @@ static inline int hash__hugepd_ok(hugepd_t hpd)
* keeping the prototype consistent across the two formats.
*/
static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
- unsigned int subpg_index, unsigned long hidx)
+ unsigned int subpg_index, unsigned long hidx,
+ int offset)
{
return (hidx << H_PAGE_F_GIX_SHIFT) &
(H_PAGE_F_SECOND | H_PAGE_F_GIX);
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index ee440fb3d240..3bcf269f8f55 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -45,7 +45,7 @@
* generic accessors and iterators here
*/
#define __real_pte __real_pte
-static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
+static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep, int offset)
{
real_pte_t rpte;
unsigned long *hidxp;
@@ -59,7 +59,7 @@ static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
*/
smp_rmb();
- hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
+ hidxp = (unsigned long *)(ptep + offset);
rpte.hidx = *hidxp;
return rpte;
}
@@ -86,9 +86,10 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
* expected to modify the PTE bits accordingly and commit the PTE to memory.
*/
static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
- unsigned int subpg_index, unsigned long hidx)
+ unsigned int subpg_index,
+ unsigned long hidx, int offset)
{
- unsigned long *hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);
+ unsigned long *hidxp = (unsigned long *)(ptep + offset);
rpte.hidx &= ~HIDX_BITS(0xfUL, subpg_index);
*hidxp = rpte.hidx | HIDX_BITS(HIDX_SHIFT_BY_ONE(hidx), subpg_index);
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 1c8c88e90553..a6b9f1d74600 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -350,7 +350,7 @@ extern unsigned long pci_io_base;
*/
#ifndef __real_pte
-#define __real_pte(e,p) ((real_pte_t){(e)})
+#define __real_pte(e, p, o) ((real_pte_t){(e)})
#define __rpte_to_pte(r) ((r).pte)
#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> H_PAGE_F_GIX_SHIFT)
diff --git a/arch/powerpc/mm/hash64_4k.c b/arch/powerpc/mm/hash64_4k.c
index 5a69b51d08a3..d573d7d07f25 100644
--- a/arch/powerpc/mm/hash64_4k.c
+++ b/arch/powerpc/mm/hash64_4k.c
@@ -55,7 +55,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
* need to add in 0x1 if it's a read-only user page
*/
rflags = htab_convert_pte_flags(new_pte);
- rpte = __real_pte(__pte(old_pte), ptep);
+ rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -117,7 +117,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
return -1;
}
new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
- new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+ new_pte |= pte_set_hidx(ptep, rpte, 0, slot, PTRS_PER_PTE);
}
*ptep = __pte(new_pte & ~H_PAGE_BUSY);
return 0;
diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
index 2253bbc6a599..e601d95c3b20 100644
--- a/arch/powerpc/mm/hash64_64k.c
+++ b/arch/powerpc/mm/hash64_64k.c
@@ -86,7 +86,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
subpg_index = (ea & (PAGE_SIZE - 1)) >> shift;
vpn = hpt_vpn(ea, vsid, ssize);
- rpte = __real_pte(__pte(old_pte), ptep);
+ rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
/*
*None of the sub 4k page is hashed
*/
@@ -214,7 +214,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
return -1;
}
- new_pte |= pte_set_hidx(ptep, rpte, subpg_index, slot);
+ new_pte |= pte_set_hidx(ptep, rpte, subpg_index, slot, PTRS_PER_PTE);
new_pte |= H_PAGE_HASHPTE;
*ptep = __pte(new_pte & ~H_PAGE_BUSY);
@@ -262,7 +262,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
} while (!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
rflags = htab_convert_pte_flags(new_pte);
- rpte = __real_pte(__pte(old_pte), ptep);
+ rpte = __real_pte(__pte(old_pte), ptep, PTRS_PER_PTE);
if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -327,7 +327,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
}
new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE;
- new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+ new_pte |= pte_set_hidx(ptep, rpte, 0, slot, PTRS_PER_PTE);
}
*ptep = __pte(new_pte & ~H_PAGE_BUSY);
return 0;
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 12511f5a015f..b320f5097a06 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -27,7 +27,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
unsigned long vpn;
unsigned long old_pte, new_pte;
unsigned long rflags, pa, sz;
- long slot;
+ long slot, offset;
BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
@@ -63,7 +63,11 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
} while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte)));
rflags = htab_convert_pte_flags(new_pte);
- rpte = __real_pte(__pte(old_pte), ptep);
+ if (unlikely(mmu_psize == MMU_PAGE_16G))
+ offset = PTRS_PER_PUD;
+ else
+ offset = PTRS_PER_PMD;
+ rpte = __real_pte(__pte(old_pte), ptep, offset);
sz = ((1UL) << shift);
if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
@@ -104,7 +108,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
return -1;
}
- new_pte |= pte_set_hidx(ptep, rpte, 0, slot);
+ new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset);
}
/*
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 881ebd53ffc2..9b23f12e863c 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -51,7 +51,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
unsigned int psize;
int ssize;
real_pte_t rpte;
- int i;
+ int i, offset;
i = batch->index;
@@ -67,6 +67,10 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
psize = get_slice_psize(mm, addr);
/* Mask the address for the correct page size */
addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
+ if (unlikely(psize == MMU_PAGE_16G))
+ offset = PTRS_PER_PUD;
+ else
+ offset = PTRS_PER_PMD;
#else
BUG();
psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
@@ -78,6 +82,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
* support 64k pages, this might be different from the
* hardware page size encoded in the slice table. */
addr &= PAGE_MASK;
+ offset = PTRS_PER_PTE;
}
@@ -91,7 +96,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
}
WARN_ON(vsid == 0);
vpn = hpt_vpn(addr, vsid, ssize);
- rpte = __real_pte(__pte(pte), ptep);
+ rpte = __real_pte(__pte(pte), ptep, offset);
/*
* Check if we have an active batch on this CPU. If not, just
--
2.14.3
^ permalink raw reply related
* [PATCH V2 4/4] powerpc/mm/hash64: memset the pagetable pages on allocation.
From: Aneesh Kumar K.V @ 2018-02-11 15:00 UTC (permalink / raw)
To: benh, paulus, mpe, Ram Pai; +Cc: linuxppc-dev, Aneesh Kumar K.V
In-Reply-To: <20180211150009.21297-1-aneesh.kumar@linux.vnet.ibm.com>
Now that we are using second half of the table to store slot details and we
don't clear them in the huge_pte_get_and_clear, we need to make sure we zero
out the range on allocation.
Simplify this by calling the object initialization after kmem_cache_alloc and
update the constructor do nothing.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/book3s/32/pgalloc.h | 16 +++++++++++++
arch/powerpc/include/asm/book3s/64/pgalloc.h | 34 +++++++++++++++++++++++-----
arch/powerpc/include/asm/nohash/pgalloc.h | 16 +++++++++++++
arch/powerpc/mm/init-common.c | 15 ------------
4 files changed, 60 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/32/pgalloc.h b/arch/powerpc/include/asm/book3s/32/pgalloc.h
index 5073cc75f1c8..9f5c411bce1b 100644
--- a/arch/powerpc/include/asm/book3s/32/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/32/pgalloc.h
@@ -139,4 +139,20 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
pgtable_page_dtor(table);
pgtable_free_tlb(tlb, page_address(table), 0);
}
+
+static inline void pgd_ctor(void *addr)
+{
+ memset(addr, 0, PGD_TABLE_SIZE);
+}
+
+static inline void pud_ctor(void *addr)
+{
+ memset(addr, 0, PUD_TABLE_SIZE);
+}
+
+static inline void pmd_ctor(void *addr)
+{
+ memset(addr, 0, PMD_TABLE_SIZE);
+}
+
#endif /* _ASM_POWERPC_BOOK3S_32_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/book3s/64/pgalloc.h b/arch/powerpc/include/asm/book3s/64/pgalloc.h
index 53df86d3cfce..d6ee7563b09d 100644
--- a/arch/powerpc/include/asm/book3s/64/pgalloc.h
+++ b/arch/powerpc/include/asm/book3s/64/pgalloc.h
@@ -73,10 +73,13 @@ static inline void radix__pgd_free(struct mm_struct *mm, pgd_t *pgd)
static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
+ pgd_t *pgd;
if (radix_enabled())
return radix__pgd_alloc(mm);
- return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE),
- pgtable_gfp_flags(mm, GFP_KERNEL));
+ pgd = kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE),
+ pgtable_gfp_flags(mm, GFP_KERNEL));
+ memset(pgd, 0, PGD_TABLE_SIZE);
+ return pgd;
}
static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
@@ -93,8 +96,11 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
{
- return kmem_cache_alloc(PGT_CACHE(PUD_CACHE_INDEX),
- pgtable_gfp_flags(mm, GFP_KERNEL));
+ pud_t *pud;
+ pud = kmem_cache_alloc(PGT_CACHE(PUD_CACHE_INDEX),
+ pgtable_gfp_flags(mm, GFP_KERNEL));
+ memset(pud, 0, PUD_TABLE_SIZE);
+ return pud;
}
static inline void pud_free(struct mm_struct *mm, pud_t *pud)
@@ -120,8 +126,12 @@ static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
{
- return kmem_cache_alloc(PGT_CACHE(PMD_CACHE_INDEX),
- pgtable_gfp_flags(mm, GFP_KERNEL));
+ pmd_t *pmd;
+ pmd = kmem_cache_alloc(PGT_CACHE(PMD_CACHE_INDEX),
+ pgtable_gfp_flags(mm, GFP_KERNEL));
+ memset(pmd, 0, PMD_TABLE_SIZE);
+ return pmd;
+
}
static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
@@ -218,4 +228,16 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
#define check_pgt_cache() do { } while (0)
+static inline void pgd_ctor(void *addr)
+{
+}
+
+static inline void pud_ctor(void *addr)
+{
+}
+
+static inline void pmd_ctor(void *addr)
+{
+}
+
#endif /* _ASM_POWERPC_BOOK3S_64_PGALLOC_H */
diff --git a/arch/powerpc/include/asm/nohash/pgalloc.h b/arch/powerpc/include/asm/nohash/pgalloc.h
index 0634f2949438..df3be548ff97 100644
--- a/arch/powerpc/include/asm/nohash/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/pgalloc.h
@@ -21,4 +21,20 @@ static inline void tlb_flush_pgtable(struct mmu_gather *tlb,
#else
#include <asm/nohash/32/pgalloc.h>
#endif
+
+static inline void pgd_ctor(void *addr)
+{
+ memset(addr, 0, PGD_TABLE_SIZE);
+}
+
+static inline void pud_ctor(void *addr)
+{
+ memset(addr, 0, PUD_TABLE_SIZE);
+}
+
+static inline void pmd_ctor(void *addr)
+{
+ memset(addr, 0, PMD_TABLE_SIZE);
+}
+
#endif /* _ASM_POWERPC_NOHASH_PGALLOC_H */
diff --git a/arch/powerpc/mm/init-common.c b/arch/powerpc/mm/init-common.c
index 2b656e67f2ea..f92dd8cee3c5 100644
--- a/arch/powerpc/mm/init-common.c
+++ b/arch/powerpc/mm/init-common.c
@@ -25,21 +25,6 @@
#include <asm/pgalloc.h>
#include <asm/pgtable.h>
-static void pgd_ctor(void *addr)
-{
- memset(addr, 0, PGD_TABLE_SIZE);
-}
-
-static void pud_ctor(void *addr)
-{
- memset(addr, 0, PUD_TABLE_SIZE);
-}
-
-static void pmd_ctor(void *addr)
-{
- memset(addr, 0, PMD_TABLE_SIZE);
-}
-
struct kmem_cache *pgtable_cache[MAX_PGTABLE_INDEX_SIZE];
EXPORT_SYMBOL_GPL(pgtable_cache); /* used by kvm_hv module */
--
2.14.3
^ permalink raw reply related
* Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32
From: Aneesh Kumar K.V @ 2018-02-11 15:34 UTC (permalink / raw)
To: Nicholas Piggin, Christophe Leroy
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, linux-kernel, linuxppc-dev
In-Reply-To: <20180211235944.14c2be39@roar.ozlabs.ibm.com>
On 02/11/2018 07:29 PM, Nicholas Piggin wrote:
> On Sat, 10 Feb 2018 13:54:27 +0100 (CET)
> Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>
>> In preparation for the following patch which will fix an issue on
>> the 8xx by re-using the 'slices', this patch enhances the
>> 'slices' implementation to support 32 bits CPUs.
>>
>> On PPC32, the address space is limited to 4Gbytes, hence only the low
>> slices will be used.
>>
>> This patch moves "slices" functions prototypes from page64.h to slice.h
>>
>> The high slices use bitmaps. As bitmap functions are not prepared to
>> handling bitmaps of size 0, the bitmap_xxx() calls are wrapped into
>> slice_bitmap_xxx() functions which will void on PPC32
>
> On this last point, I think it would be better to put these with the
> existing slice bitmap functions in slice.c and just have a few #ifdefs
> for SLICE_NUM_HIGH == 0.
>
We went back and forth with that. IMHO, we should avoid as much #ifdef
as possible across platforms. It helps to understand the platform
restrictions better as we have less and less access to these platforms.
The above change indicates that nohash 32 wants to use the slice code
and they have different restrictions. With that we now know that
book3s64 and nohash 32 are the two different configs using slice code.
-aneesh
^ permalink raw reply
* KVM compile error
From: Christian Zigotzky @ 2018-02-11 16:15 UTC (permalink / raw)
To: linuxppc-dev
Just for info: KVM doesn=E2=80=99t compile currently.
Error messages:
CC arch/powerpc/kvm/powerpc.o
arch/powerpc/kvm/powerpc.c: In function 'kvm_arch_vcpu_ioctl_run':
arch/powerpc/kvm/powerpc.c:1611:1: error: label 'out' defined but not used [=
-Werror=3Dunused-label]
out:
^
cc1: all warnings being treated as errors
=E2=80=94 Christian=
^ permalink raw reply
* Re: [PATCH 1/3] cxl: Introduce various enums/defines for PSL9 trace arrays
From: Vaibhav Jain @ 2018-02-11 16:46 UTC (permalink / raw)
To: christophe lombard, linuxppc-dev, Frederic Barrat
Cc: Philippe Bergheaud, Alastair D'Silva, Andrew Donnellan,
Christophe Lombard
In-Reply-To: <ee7a08db-900b-fe9e-7e84-132a871bd38b@linux.vnet.ibm.com>
Thanks for reviewing the patch Christophe,
christophe lombard <clombard@linux.vnet.ibm.com> writes:
>> + for (traceid = 0; traceid < CXL_PSL9_TRACEID_MAX; ++traceid) {
>> + trace_state = CXL_PSL9_TRACE_STATE(trace_cfg, traceid);
>> + dev_dbg(&dev->dev, "Traceid-%d trace_state=0x%0llX\n",
>> traceid, trace_state);
>>
> any reason to use dev_dbg instead of pr_devel ?
Wanted to distinguish among multiple cxl cards in the system.
--
Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Linux Technology Center, IBM India Pvt. Ltd.
^ permalink raw reply
* Re: [PATCH 2/3] cxl: Introduce module parameter 'enable_psltrace'
From: Vaibhav Jain @ 2018-02-11 17:10 UTC (permalink / raw)
To: christophe lombard, linuxppc-dev, Frederic Barrat
Cc: Philippe Bergheaud, Alastair D'Silva, Christophe Lombard,
Andrew Donnellan
In-Reply-To: <a3880a5d-6ccb-9a90-14e5-d48376e4c8e0@linux.vnet.ibm.com>
Thanks for reviewing the patch Christophe,
christophe lombard <clombard@linux.vnet.ibm.com> writes:
>> +bool cxl_enable_psltrace = true;
>> +module_param_named(enable_psltrace, cxl_enable_psltrace, bool, 0600);
>> +MODULE_PARM_DESC(enable_psltrace, "Set PSL traces on probe. default: on");
>> +
> I am not too agree to add a new parameter. This can cause doubts.
> PSL team has confirmed that enabling traces has no impact.
> Do you see any reason to disable the traces ?
Traces on PSL follow a 'set and fetch' model. So once the trace buffer for
a specific array is full it will stop and switch to 'FIN' state and at
that point we need to fetch the trace-data and reinit the array to
re-arm it.
There might be some circumstances where this model may lead to confusion
specifically when AFU developers assume that the trace arrays are
already armed and dont re-arm it causing miss of trace data.
So this module param is a compromise to keep the old behaviour of traces
array intact where in the arming/disarming of the trace arrays is
controlled completely by userspace tooling and not by cxl.
--
Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Linux Technology Center, IBM India Pvt. Ltd.
^ permalink raw reply
* Re: [PATCH V2 1/4] powerpc/mm: Fix crashes with PUD level hugetlb config
From: Ram Pai @ 2018-02-11 22:24 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
In-Reply-To: <20180211150009.21297-1-aneesh.kumar@linux.vnet.ibm.com>
On Sun, Feb 11, 2018 at 08:30:06PM +0530, Aneesh Kumar K.V wrote:
> To support memory keys, we moved the hash pte slot information to the second
> half of the page table. This was ok with PTE entries at level 4 and level 3.
> We already allocate larger page table pages at those level to accomodate extra
> details. For level 4 we already have the extra space which was used to track
> 4k hash page table entry details and at pmd level the extra space was allocated
> to track the THP details.
>
> With hugetlbfs PTE, we used this extra space at the PMD level to store the
> slot details. But we also support hugetlbfs PTE at PUD leve and PUD level page
> didn't allocate extra space. This resulted in memory corruption.
>
> Fix this by allocating extra space at PUD level when HUGETLB is enabled. We
> may need further changes to allocate larger space at PMD level when we enable
> HUGETLB. That will be done in next patch.
>
> Fixes:bf9a95f9a6481bc6e(" powerpc: Free up four 64K PTE bits in 64K backed HPTE pages")
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/book3s/32/pgtable.h | 1 +
> arch/powerpc/include/asm/book3s/64/hash-64k.h | 5 +++++
> arch/powerpc/include/asm/book3s/64/hash.h | 10 ++++++++++
> arch/powerpc/include/asm/book3s/64/pgalloc.h | 6 +++---
> arch/powerpc/include/asm/book3s/64/pgtable.h | 2 ++
> arch/powerpc/include/asm/nohash/32/pgtable.h | 1 +
> arch/powerpc/include/asm/nohash/64/pgtable.h | 1 +
> arch/powerpc/mm/hash_utils_64.c | 1 +
> arch/powerpc/mm/init-common.c | 4 ++--
> arch/powerpc/mm/pgtable-radix.c | 1 +
> arch/powerpc/mm/pgtable_64.c | 2 ++
> 11 files changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/32/pgtable.h b/arch/powerpc/include/asm/book3s/32/pgtable.h
> index 30a155c0a6b0..c615abdce119 100644
> --- a/arch/powerpc/include/asm/book3s/32/pgtable.h
> +++ b/arch/powerpc/include/asm/book3s/32/pgtable.h
> @@ -16,6 +16,7 @@
> #define PGD_INDEX_SIZE (32 - PGDIR_SHIFT)
>
> #define PMD_CACHE_INDEX PMD_INDEX_SIZE
> +#define PUD_CACHE_INDEX PUD_INDEX_SIZE
>
> #ifndef __ASSEMBLY__
> #define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> index 338b7da468ce..c08b3b032ec0 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> @@ -146,7 +146,12 @@ static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long a
> #else
> #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
> #endif
> +#ifdef CONFIG_HUGETLB_PAGE
> +#define H_PUD_TABLE_SIZE ((sizeof(pud_t) << PUD_INDEX_SIZE) + \
> + (sizeof(unsigned long) << PUD_INDEX_SIZE))
> +#else
> #define H_PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
> +#endif
> #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
>
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
> index 0920eff731b3..234f141fb151 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash.h
> @@ -32,6 +32,16 @@
> #else
> #define H_PMD_CACHE_INDEX H_PMD_INDEX_SIZE
> #endif
> +/*
> + * We not store the slot details in the second half of page table.
s/not//
We store....
Reviewed-by: Ram Pai <linuxram@us.ibm.com>
^ permalink raw reply
* Re: [PATCH V2 2/4] powerpc/mm/hash64: Allocate larger PMD table if hugetlb config is enabled.
From: Ram Pai @ 2018-02-11 22:28 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
In-Reply-To: <20180211150009.21297-2-aneesh.kumar@linux.vnet.ibm.com>
On Sun, Feb 11, 2018 at 08:30:07PM +0530, Aneesh Kumar K.V wrote:
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
> arch/powerpc/include/asm/book3s/64/hash.h | 3 ++-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> index c08b3b032ec0..ee440fb3d240 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
> @@ -140,7 +140,7 @@ static inline int hash__remap_4k_pfn(struct vm_area_struct *vma, unsigned long a
> }
>
> #define H_PTE_TABLE_SIZE PTE_FRAG_SIZE
> -#ifdef CONFIG_TRANSPARENT_HUGEPAGE
> +#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined (CONFIG_HUGETLB_PAGE)
> #define H_PMD_TABLE_SIZE ((sizeof(pmd_t) << PMD_INDEX_SIZE) + \
> (sizeof(unsigned long) << PMD_INDEX_SIZE))
> #else
> diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
> index 234f141fb151..0851c328bea6 100644
> --- a/arch/powerpc/include/asm/book3s/64/hash.h
> +++ b/arch/powerpc/include/asm/book3s/64/hash.h
> @@ -23,7 +23,8 @@
> H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
> #define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
>
> -#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_PPC_64K_PAGES)
> +#if (defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)) && \
> + defined(CONFIG_PPC_64K_PAGES)
> /*
> * only with hash 64k we need to use the second half of pmd page table
> * to store pointer to deposited pgtable_t
A small nitpick. the definition of H_PMD_CACHE_INDEX and
H_PUD_CACHE_INDEX (introduced in the previous patch)
can be nested under #ifdef CONFIG_PPC_64K_PAGES
Reviewed-by: Ram Pai <linuxram@us.ibm.com>
^ permalink raw reply
* Re: [PATCH V2 3/4] powerpc/mm/hash64: Store the slot information at the right offset.
From: Ram Pai @ 2018-02-11 22:39 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: benh, paulus, mpe, linuxppc-dev
In-Reply-To: <20180211150009.21297-3-aneesh.kumar@linux.vnet.ibm.com>
On Sun, Feb 11, 2018 at 08:30:08PM +0530, Aneesh Kumar K.V wrote:
> The hugetlb pte entries are at the PMD and PUD level. Use the right offset
> for them to get the second half of the table.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/book3s/64/hash-4k.h | 3 ++-
> arch/powerpc/include/asm/book3s/64/hash-64k.h | 9 +++++----
> arch/powerpc/include/asm/book3s/64/pgtable.h | 2 +-
> arch/powerpc/mm/hash64_4k.c | 4 ++--
> arch/powerpc/mm/hash64_64k.c | 8 ++++----
> arch/powerpc/mm/hugetlbpage-hash64.c | 10 +++++++---
> arch/powerpc/mm/tlb_hash64.c | 9 +++++++--
> 7 files changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
> index 949d691094a4..67c5475311ee 100644
> diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
....snip...
> index 881ebd53ffc2..9b23f12e863c 100644
> --- a/arch/powerpc/mm/tlb_hash64.c
> +++ b/arch/powerpc/mm/tlb_hash64.c
> @@ -51,7 +51,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> unsigned int psize;
> int ssize;
> real_pte_t rpte;
> - int i;
> + int i, offset;
>
> i = batch->index;
>
> @@ -67,6 +67,10 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
> psize = get_slice_psize(mm, addr);
> /* Mask the address for the correct page size */
> addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1);
> + if (unlikely(psize == MMU_PAGE_16G))
> + offset = PTRS_PER_PUD;
> + else
> + offset = PTRS_PER_PMD;
I prefer to encapsulate this under some function/macro; somewhere in hugetlb.h, which returns
the offset given a mmu_size. But no big deal..
Reviewed-by: Ram Pai <linuxram@us.ibm.com>
RP
^ permalink raw reply
* Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32
From: Nicholas Piggin @ 2018-02-11 23:34 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, Scott Wood, linux-kernel, linuxppc-dev
In-Reply-To: <ba493b6c-c61a-5097-e896-5ae3f0128b3a@linux.vnet.ibm.com>
On Sun, 11 Feb 2018 21:04:42 +0530
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> wrote:
> On 02/11/2018 07:29 PM, Nicholas Piggin wrote:
> > On Sat, 10 Feb 2018 13:54:27 +0100 (CET)
> > Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> >
> >> In preparation for the following patch which will fix an issue on
> >> the 8xx by re-using the 'slices', this patch enhances the
> >> 'slices' implementation to support 32 bits CPUs.
> >>
> >> On PPC32, the address space is limited to 4Gbytes, hence only the low
> >> slices will be used.
> >>
> >> This patch moves "slices" functions prototypes from page64.h to slice.h
> >>
> >> The high slices use bitmaps. As bitmap functions are not prepared to
> >> handling bitmaps of size 0, the bitmap_xxx() calls are wrapped into
> >> slice_bitmap_xxx() functions which will void on PPC32
> >
> > On this last point, I think it would be better to put these with the
> > existing slice bitmap functions in slice.c and just have a few #ifdefs
> > for SLICE_NUM_HIGH == 0.
> >
>
> We went back and forth with that. IMHO, we should avoid as much #ifdef
> as possible across platforms. It helps to understand the platform
> restrictions better as we have less and less access to these platforms.
> The above change indicates that nohash 32 wants to use the slice code
> and they have different restrictions. With that we now know that
> book3s64 and nohash 32 are the two different configs using slice code.
I don't think it's the right place to put it. It's not platform dependent
so much as it just depends on whether or not you have 0 high slices as
a workaround for bitmap API not accepting 0 length.
Another platform that uses the slice code would just have to copy and
paste either the nop or the bitmap implementation depending if it has
high slices. So I don't think it's the right abstraction. And it
implies a bitmap operation but it very specifically only works for
struct slice_mask.high_slices bitmap, which is not clear. Better to
just work with struct slice_mask.
Some ifdefs inside .c code for small helper functions like this IMO isn't
really a big deal -- it's not worse than having it in headers. You just
want to avoid ifdef mess when looking at non-trivial logic.
static inline void slice_or_mask(struct slice_mask *dst, struct slice_mask *src)
{
dst->low_slices |= src->low_slices;
#if SLICE_NUM_HIGH > 0
bitmap_or(result, dst->high_slices, src->high_slices, SLICE_NUM_HIGH);
#endif
}
I think that's pretty fine. If you have a singular hatred for ifdef in .c,
then if() works just as well.
Thanks,
Nick
^ permalink raw reply
* [PATCH 1/1] powerpc/pseries: Enable RAS hotplug events late
From: Sam Bobroff @ 2018-02-12 0:19 UTC (permalink / raw)
To: linuxppc-dev
Currently if the kernel receives a memory hot-unplug event early
enough, it may get stuck in an infinite loop in
dissolve_free_huge_pages(). This appears as a stall just after:
pseries-hotplug-mem: Attempting to hot-remove XX LMB(s) at YYYYYYYY
It appears to be caused by "minimum_order" being uninitialized, due to
init_ras_IRQ() executing before hugetlb_init().
To correct this, extract the part of init_ras_IRQ() that enables
hotplug event processing and place it in the machine_late_initcall
phase, which is guaranteed to be after hugetlb_init() is called.
Signed-off-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
---
arch/powerpc/platforms/pseries/ras.c | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 81d8614e7379..ba284949af06 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -66,6 +66,26 @@ static int __init init_ras_IRQ(void)
of_node_put(np);
}
+ /* EPOW Events */
+ np = of_find_node_by_path("/event-sources/epow-events");
+ if (np != NULL) {
+ request_event_sources_irqs(np, ras_epow_interrupt, "RAS_EPOW");
+ of_node_put(np);
+ }
+
+ return 0;
+}
+machine_subsys_initcall(pseries, init_ras_IRQ);
+
+/*
+ * Enable the hotplug interrupt late because processing them may touch other
+ * devices or systems (e.g. hugepages) that have not been initialized at the
+ * subsys stage.
+ */
+int __init init_ras_hotplug_IRQ(void)
+{
+ struct device_node *np;
+
/* Hotplug Events */
np = of_find_node_by_path("/event-sources/hot-plug-events");
if (np != NULL) {
@@ -75,16 +95,9 @@ static int __init init_ras_IRQ(void)
of_node_put(np);
}
- /* EPOW Events */
- np = of_find_node_by_path("/event-sources/epow-events");
- if (np != NULL) {
- request_event_sources_irqs(np, ras_epow_interrupt, "RAS_EPOW");
- of_node_put(np);
- }
-
return 0;
}
-machine_subsys_initcall(pseries, init_ras_IRQ);
+machine_late_initcall(pseries, init_ras_hotplug_IRQ);
#define EPOW_SHUTDOWN_NORMAL 1
#define EPOW_SHUTDOWN_ON_UPS 2
--
2.16.1.74.g9b0b1f47b
^ permalink raw reply related
* Re: [PATCH kernel v3] powerpc/pci: Fix broken INTx configuration via OF
From: Michael Ellerman @ 2018-02-12 3:49 UTC (permalink / raw)
To: Bjorn Helgaas, Alexey Kardashevskiy
Cc: linuxppc-dev, Benjamin Herrenschmidt, Bjorn Helgaas, Rob Herring,
linux-pci
In-Reply-To: <20180210205118.GG206223@bhelgaas-glaptop.roam.corp.google.com>
Bjorn Helgaas <helgaas@kernel.org> writes:
> On Fri, Feb 09, 2018 at 12:07:41PM -0600, Bjorn Helgaas wrote:
>> On Fri, Feb 09, 2018 at 05:23:58PM +1100, Alexey Kardashevskiy wrote:
>> > Commit 59f47eff03a0 ("powerpc/pci: Use of_irq_parse_and_map_pci() helper")
>> > replaced of_irq_parse_pci() + irq_create_of_mapping() with
>> > of_irq_parse_and_map_pci() but this change lost virq returned by
>> > irq_create_of_mapping() so virq remained zero causing INTx
>> > misconfiguration.
>> >
>> > This fixes pci_read_irq_line() not to loose a virq returned by
>> > of_irq_parse_and_map_pci().
>>
>> s/not to loose a/to not lose the/
>>
>> > Fixes: 59f47eff03a0 "powerpc/pci: Use of_irq_parse_and_map_pci() helper"
>> > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>
>> I'm fine with this version.
>>
>> Since you started applying a previous version, Michael, I'll assume
>> you will handle this unless you tell me otherwise. One way or another
>> it would be good to get this in before -rc1.
>
> I went ahead and applied this and asked Linus to pull it.
Thanks.
cheers
^ permalink raw reply
* Re: [PATCH 2/4] powerpc/vas: Fix cleanup when VAS is not configured
From: Michael Ellerman @ 2018-02-12 5:23 UTC (permalink / raw)
To: Sukadev Bhattiprolu
Cc: Benjamin Herrenschmidt, mikey, hbabu, linuxppc-dev, linux-kernel
In-Reply-To: <1518234567-24869-2-git-send-email-sukadev@linux.vnet.ibm.com>
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> writes:
> When VAS is not configured in the system, make sure to remove
> the VAS debugfs directory and unregister the platform driver.
>
> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
...
> diff --git a/arch/powerpc/platforms/powernv/vas.c b/arch/powerpc/platforms/powernv/vas.c
> index aebbe95..f83e27d8 100644
> --- a/arch/powerpc/platforms/powernv/vas.c
> +++ b/arch/powerpc/platforms/powernv/vas.c
> @@ -169,8 +169,11 @@ static int __init vas_init(void)
> found++;
> }
>
> - if (!found)
> + if (!found) {
> + platform_driver_unregister(&vas_driver);
> + vas_cleanup_dbgdir();
> return -ENODEV;
> + }
The better patch would be to move the call to vas_init_dbgdir() down
here, where we know we have successfully registered the driver.
cheers
^ permalink raw reply
* Re: [PATCH v4 2/5] powerpc/mm/slice: Enhance for supporting PPC32
From: Aneesh Kumar K.V @ 2018-02-12 5:46 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, Scott Wood
Cc: linuxppc-dev, linux-kernel, Nicholas Piggin
In-Reply-To: <0ac518636ae1e601ea0732dd69b48dcd0f347285.1518226173.git.christophe.leroy@c-s.fr>
Christophe Leroy <christophe.leroy@c-s.fr> writes:
> In preparation for the following patch which will fix an issue on
> the 8xx by re-using the 'slices', this patch enhances the
> 'slices' implementation to support 32 bits CPUs.
>
> On PPC32, the address space is limited to 4Gbytes, hence only the low
> slices will be used.
>
> This patch moves "slices" functions prototypes from page64.h to slice.h
>
> The high slices use bitmaps. As bitmap functions are not prepared to
> handling bitmaps of size 0, the bitmap_xxx() calls are wrapped into
> slice_bitmap_xxx() functions which will void on PPC32
>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> v2: First patch of v1 serie split in two parts ; added slice_bitmap_xxx() macros.
> v3: Moving slice related stuff in slice.h and slice_32/64.h
> slice_bitmap_xxx() are now static inline functions and platform dependent
> SLICE_LOW_TOP declared ull on PPC32 with correct casts allows to keep it 0x100000000
> v4: Moved slice_32.h and slice_64.h to respective subarch dirs
> Moved somes #ifdefs from asm/slice.h to respective subarch slice.h
> SLICE_LOW_ details distributed in repective subarch slices allthough they are identical for the moment
>
> arch/powerpc/include/asm/book3s/64/slice.h | 79 ++++++++++++++++++++++++++++++
> arch/powerpc/include/asm/nohash/32/slice.h | 65 ++++++++++++++++++++++++
> arch/powerpc/include/asm/nohash/64/slice.h | 12 +++++
> arch/powerpc/include/asm/page.h | 1 +
> arch/powerpc/include/asm/page_64.h | 59 ----------------------
> arch/powerpc/include/asm/slice.h | 42 ++++++++++++++++
> arch/powerpc/mm/slice.c | 38 ++++++++------
> 7 files changed, 221 insertions(+), 75 deletions(-)
> create mode 100644 arch/powerpc/include/asm/book3s/64/slice.h
> create mode 100644 arch/powerpc/include/asm/nohash/32/slice.h
> create mode 100644 arch/powerpc/include/asm/nohash/64/slice.h
> create mode 100644 arch/powerpc/include/asm/slice.h
>
> diff --git a/arch/powerpc/include/asm/book3s/64/slice.h b/arch/powerpc/include/asm/book3s/64/slice.h
> new file mode 100644
> index 000000000000..f9a2c8bd7a77
> --- /dev/null
> +++ b/arch/powerpc/include/asm/book3s/64/slice.h
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_POWERPC_BOOK3S_64_SLICE_H
> +#define _ASM_POWERPC_BOOK3S_64_SLICE_H
> +
> +#ifdef CONFIG_PPC_MM_SLICES
> +
> +#define SLICE_LOW_SHIFT 28
> +#define SLICE_LOW_TOP (0x100000000ul)
> +#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
> +#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
> +
> +#define SLICE_HIGH_SHIFT 40
> +#define SLICE_NUM_HIGH (H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
> +#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
> +
> +#ifndef __ASSEMBLY__
> +
> +#include <linux/bitmap.h>
> +
> +static inline void slice_bitmap_zero(unsigned long *dst, unsigned int nbits)
> +{
> + bitmap_zero(dst, nbits);
> +}
> +
> +static inline int slice_bitmap_and(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return bitmap_and(dst, src1, src2, nbits);
> +}
> +
> +static inline void slice_bitmap_or(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + bitmap_or(dst, src1, src2, nbits);
> +}
> +
> +static inline int slice_bitmap_andnot(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return bitmap_andnot(dst, src1, src2, nbits);
> +}
> +
> +static inline int slice_bitmap_equal(const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return bitmap_equal(src1, src2, nbits);
> +}
> +
> +static inline int slice_bitmap_empty(const unsigned long *src, unsigned nbits)
> +{
> + return bitmap_empty(src, nbits);
> +}
> +
> +static inline void slice_bitmap_set(unsigned long *map, unsigned int start,
> + unsigned int nbits)
> +{
> + bitmap_set(map, start, nbits);
> +}
> +#endif /* __ASSEMBLY__ */
> +
> +#else /* CONFIG_PPC_MM_SLICES */
> +
> +#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
> +#define slice_set_user_psize(mm, psize) \
> +do { \
> + (mm)->context.user_psize = (psize); \
> + (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
> +} while (0)
> +
> +#endif /* CONFIG_PPC_MM_SLICES */
> +
> +#endif /* _ASM_POWERPC_BOOK3S_64_SLICE_H */
> diff --git a/arch/powerpc/include/asm/nohash/32/slice.h b/arch/powerpc/include/asm/nohash/32/slice.h
> new file mode 100644
> index 000000000000..bcb4924f7d22
> --- /dev/null
> +++ b/arch/powerpc/include/asm/nohash/32/slice.h
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_POWERPC_NOHASH_32_SLICE_H
> +#define _ASM_POWERPC_NOHASH_32_SLICE_H
> +
> +#ifdef CONFIG_PPC_MM_SLICES
> +
> +#define SLICE_LOW_SHIFT 28
> +#define SLICE_LOW_TOP (0x100000000ull)
> +#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
> +#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
> +
> +#define SLICE_HIGH_SHIFT 0
> +#define SLICE_NUM_HIGH 0ul
> +#define GET_HIGH_SLICE_INDEX(addr) (addr & 0)
> +
> +#ifndef __ASSEMBLY__
> +
> +static inline void slice_bitmap_zero(unsigned long *dst, unsigned int nbits)
> +{
> +}
> +
> +static inline int slice_bitmap_and(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return 0;
> +}
> +
> +static inline void slice_bitmap_or(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> +}
> +
> +static inline int slice_bitmap_andnot(unsigned long *dst,
> + const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return 0;
> +}
> +
> +static inline int slice_bitmap_equal(const unsigned long *src1,
> + const unsigned long *src2,
> + unsigned int nbits)
> +{
> + return 1;
> +}
> +
> +static inline int slice_bitmap_empty(const unsigned long *src, unsigned nbits)
> +{
> + return 1;
> +}
> +
> +static inline void slice_bitmap_set(unsigned long *map, unsigned int start,
> + unsigned int nbits)
> +{
> +}
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* CONFIG_PPC_MM_SLICES */
> +
> +#endif /* _ASM_POWERPC_NOHASH_32_SLICE_H */
> diff --git a/arch/powerpc/include/asm/nohash/64/slice.h b/arch/powerpc/include/asm/nohash/64/slice.h
> new file mode 100644
> index 000000000000..ad0d6e3cc1c5
> --- /dev/null
> +++ b/arch/powerpc/include/asm/nohash/64/slice.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_POWERPC_NOHASH_64_SLICE_H
> +#define _ASM_POWERPC_NOHASH_64_SLICE_H
> +
> +#ifdef CONFIG_PPC_64K_PAGES
> +#define get_slice_psize(mm, addr) MMU_PAGE_64K
> +#else /* CONFIG_PPC_64K_PAGES */
> +#define get_slice_psize(mm, addr) MMU_PAGE_4K
> +#endif /* !CONFIG_PPC_64K_PAGES */
> +#define slice_set_user_psize(mm, psize) do { BUG(); } while (0)
> +
> +#endif /* _ASM_POWERPC_NOHASH_64_SLICE_H */
> diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h
> index 8da5d4c1cab2..d5f1c41b7dba 100644
> --- a/arch/powerpc/include/asm/page.h
> +++ b/arch/powerpc/include/asm/page.h
> @@ -344,5 +344,6 @@ typedef struct page *pgtable_t;
>
> #include <asm-generic/memory_model.h>
> #endif /* __ASSEMBLY__ */
> +#include <asm/slice.h>
>
> #endif /* _ASM_POWERPC_PAGE_H */
> diff --git a/arch/powerpc/include/asm/page_64.h b/arch/powerpc/include/asm/page_64.h
> index 56234c6fcd61..af04acdb873f 100644
> --- a/arch/powerpc/include/asm/page_64.h
> +++ b/arch/powerpc/include/asm/page_64.h
> @@ -86,65 +86,6 @@ extern u64 ppc64_pft_size;
>
> #endif /* __ASSEMBLY__ */
>
> -#ifdef CONFIG_PPC_MM_SLICES
> -
> -#define SLICE_LOW_SHIFT 28
> -#define SLICE_HIGH_SHIFT 40
> -
> -#define SLICE_LOW_TOP (0x100000000ul)
> -#define SLICE_NUM_LOW (SLICE_LOW_TOP >> SLICE_LOW_SHIFT)
> -#define SLICE_NUM_HIGH (H_PGTABLE_RANGE >> SLICE_HIGH_SHIFT)
> -
> -#define GET_LOW_SLICE_INDEX(addr) ((addr) >> SLICE_LOW_SHIFT)
> -#define GET_HIGH_SLICE_INDEX(addr) ((addr) >> SLICE_HIGH_SHIFT)
> -
> -#ifndef __ASSEMBLY__
> -struct mm_struct;
> -
> -extern unsigned long slice_get_unmapped_area(unsigned long addr,
> - unsigned long len,
> - unsigned long flags,
> - unsigned int psize,
> - int topdown);
> -
> -extern unsigned int get_slice_psize(struct mm_struct *mm,
> - unsigned long addr);
> -
> -extern void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
> -extern void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
> - unsigned long len, unsigned int psize);
> -
> -#endif /* __ASSEMBLY__ */
> -#else
> -#define slice_init()
> -#ifdef CONFIG_PPC_BOOK3S_64
> -#define get_slice_psize(mm, addr) ((mm)->context.user_psize)
> -#define slice_set_user_psize(mm, psize) \
> -do { \
> - (mm)->context.user_psize = (psize); \
> - (mm)->context.sllp = SLB_VSID_USER | mmu_psize_defs[(psize)].sllp; \
> -} while (0)
> -#else /* !CONFIG_PPC_BOOK3S_64 */
> -#ifdef CONFIG_PPC_64K_PAGES
> -#define get_slice_psize(mm, addr) MMU_PAGE_64K
> -#else /* CONFIG_PPC_64K_PAGES */
> -#define get_slice_psize(mm, addr) MMU_PAGE_4K
> -#endif /* !CONFIG_PPC_64K_PAGES */
> -#define slice_set_user_psize(mm, psize) do { BUG(); } while(0)
> -#endif /* CONFIG_PPC_BOOK3S_64 */
> -
> -#define slice_set_range_psize(mm, start, len, psize) \
> - slice_set_user_psize((mm), (psize))
> -#endif /* CONFIG_PPC_MM_SLICES */
> -
> -#ifdef CONFIG_HUGETLB_PAGE
> -
> -#ifdef CONFIG_PPC_MM_SLICES
> -#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
> -#endif
> -
> -#endif /* !CONFIG_HUGETLB_PAGE */
> -
> #define VM_DATA_DEFAULT_FLAGS \
> (is_32bit_task() ? \
> VM_DATA_DEFAULT_FLAGS32 : VM_DATA_DEFAULT_FLAGS64)
> diff --git a/arch/powerpc/include/asm/slice.h b/arch/powerpc/include/asm/slice.h
> new file mode 100644
> index 000000000000..172711fadb1c
> --- /dev/null
> +++ b/arch/powerpc/include/asm/slice.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef _ASM_POWERPC_SLICE_H
> +#define _ASM_POWERPC_SLICE_H
> +
> +#ifdef CONFIG_PPC_BOOK3S_64
> +#include <asm/book3s/64/slice.h>
> +#elif defined(CONFIG_PPC64)
> +#include <asm/nohash/64/slice.h>
> +#elif defined(CONFIG_PPC_MMU_NOHASH)
> +#include <asm/nohash/32/slice.h>
> +#endif
> +
> +#ifdef CONFIG_PPC_MM_SLICES
> +
> +#ifdef CONFIG_HUGETLB_PAGE
> +#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
> +#endif
> +#define HAVE_ARCH_UNMAPPED_AREA
> +#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
> +
> +#ifndef __ASSEMBLY__
> +
> +struct mm_struct;
> +
> +unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
> + unsigned long flags, unsigned int psize,
> + int topdown);
> +
> +unsigned int get_slice_psize(struct mm_struct *mm, unsigned long addr);
> +
> +void slice_set_user_psize(struct mm_struct *mm, unsigned int psize);
> +void slice_set_range_psize(struct mm_struct *mm, unsigned long start,
> + unsigned long len, unsigned int psize);
> +#endif /* __ASSEMBLY__ */
> +
> +#else /* CONFIG_PPC_MM_SLICES */
> +
> +#define slice_set_range_psize(mm, start, len, psize) \
> + slice_set_user_psize((mm), (psize))
> +#endif /* CONFIG_PPC_MM_SLICES */
> +
> +#endif /* _ASM_POWERPC_SLICE_H */
> diff --git a/arch/powerpc/mm/slice.c b/arch/powerpc/mm/slice.c
> index 98b53d48968f..549704dfa777 100644
> --- a/arch/powerpc/mm/slice.c
> +++ b/arch/powerpc/mm/slice.c
> @@ -73,10 +73,11 @@ static void slice_range_to_mask(unsigned long start, unsigned long len,
> unsigned long end = start + len - 1;
>
> ret->low_slices = 0;
> - bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
>
> if (start < SLICE_LOW_TOP) {
> - unsigned long mend = min(end, (SLICE_LOW_TOP - 1));
> + unsigned long mend = min(end,
> + (unsigned long)(SLICE_LOW_TOP - 1));
>
> ret->low_slices = (1u << (GET_LOW_SLICE_INDEX(mend) + 1))
> - (1u << GET_LOW_SLICE_INDEX(start));
> @@ -87,7 +88,7 @@ static void slice_range_to_mask(unsigned long start, unsigned long len,
> unsigned long align_end = ALIGN(end, (1UL << SLICE_HIGH_SHIFT));
> unsigned long count = GET_HIGH_SLICE_INDEX(align_end) - start_index;
>
> - bitmap_set(ret->high_slices, start_index, count);
> + slice_bitmap_set(ret->high_slices, start_index, count);
> }
> }
>
> @@ -113,11 +114,13 @@ static int slice_high_has_vma(struct mm_struct *mm, unsigned long slice)
> unsigned long start = slice << SLICE_HIGH_SHIFT;
> unsigned long end = start + (1ul << SLICE_HIGH_SHIFT);
>
> +#ifdef CONFIG_PPC64
> /* Hack, so that each addresses is controlled by exactly one
> * of the high or low area bitmaps, the first high area starts
> * at 4GB, not 0 */
> if (start == 0)
> start = SLICE_LOW_TOP;
> +#endif
>
> return !slice_area_is_free(mm, start, end - start);
> }
> @@ -128,7 +131,7 @@ static void slice_mask_for_free(struct mm_struct *mm, struct slice_mask *ret,
> unsigned long i;
>
> ret->low_slices = 0;
> - bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
>
> for (i = 0; i < SLICE_NUM_LOW; i++)
> if (!slice_low_has_vma(mm, i))
> @@ -151,7 +154,7 @@ static void slice_mask_for_size(struct mm_struct *mm, int psize, struct slice_ma
> u64 lpsizes;
>
> ret->low_slices = 0;
> - bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(ret->high_slices, SLICE_NUM_HIGH);
>
> lpsizes = mm->context.low_slices_psize;
> for (i = 0; i < SLICE_NUM_LOW; i++)
> @@ -180,15 +183,16 @@ static int slice_check_fit(struct mm_struct *mm,
> */
> unsigned long slice_count = GET_HIGH_SLICE_INDEX(mm->context.slb_addr_limit);
>
> - bitmap_and(result, mask.high_slices,
> - available.high_slices, slice_count);
> + slice_bitmap_and(result, mask.high_slices, available.high_slices,
> + slice_count);
>
> return (mask.low_slices & available.low_slices) == mask.low_slices &&
> - bitmap_equal(result, mask.high_slices, slice_count);
> + slice_bitmap_equal(result, mask.high_slices, slice_count);
> }
>
> static void slice_flush_segments(void *parm)
> {
> +#ifdef CONFIG_PPC64
> struct mm_struct *mm = parm;
> unsigned long flags;
>
> @@ -200,6 +204,7 @@ static void slice_flush_segments(void *parm)
> local_irq_save(flags);
> slb_flush_and_rebolt();
> local_irq_restore(flags);
> +#endif
> }
>
> static void slice_convert(struct mm_struct *mm, struct slice_mask mask, int psize)
> @@ -389,16 +394,16 @@ static unsigned long slice_find_area(struct mm_struct *mm, unsigned long len,
> static inline void slice_or_mask(struct slice_mask *dst, struct slice_mask *src)
> {
> dst->low_slices |= src->low_slices;
> - bitmap_or(dst->high_slices, dst->high_slices, src->high_slices,
> - SLICE_NUM_HIGH);
> + slice_bitmap_or(dst->high_slices, dst->high_slices, src->high_slices,
> + SLICE_NUM_HIGH);
> }
>
> static inline void slice_andnot_mask(struct slice_mask *dst, struct slice_mask *src)
> {
> dst->low_slices &= ~src->low_slices;
>
> - bitmap_andnot(dst->high_slices, dst->high_slices, src->high_slices,
> - SLICE_NUM_HIGH);
> + slice_bitmap_andnot(dst->high_slices, dst->high_slices,
> + src->high_slices, SLICE_NUM_HIGH);
> }
>
> #ifdef CONFIG_PPC_64K_PAGES
> @@ -446,14 +451,14 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
> * init different masks
> */
> mask.low_slices = 0;
> - bitmap_zero(mask.high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(mask.high_slices, SLICE_NUM_HIGH);
>
> /* silence stupid warning */;
> potential_mask.low_slices = 0;
> - bitmap_zero(potential_mask.high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(potential_mask.high_slices, SLICE_NUM_HIGH);
>
> compat_mask.low_slices = 0;
> - bitmap_zero(compat_mask.high_slices, SLICE_NUM_HIGH);
> + slice_bitmap_zero(compat_mask.high_slices, SLICE_NUM_HIGH);
>
> /* Sanity checks */
> BUG_ON(mm->task_size == 0);
> @@ -591,7 +596,8 @@ unsigned long slice_get_unmapped_area(unsigned long addr, unsigned long len,
> convert:
> slice_andnot_mask(&mask, &good_mask);
> slice_andnot_mask(&mask, &compat_mask);
> - if (mask.low_slices || !bitmap_empty(mask.high_slices, SLICE_NUM_HIGH)) {
> + if (mask.low_slices ||
> + !slice_bitmap_empty(mask.high_slices, SLICE_NUM_HIGH)) {
> slice_convert(mm, mask, psize);
> if (psize > MMU_PAGE_BASE)
> on_each_cpu(slice_flush_segments, mm, 1);
> --
> 2.13.3
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