* Re: [RFC PATCH 4/6] mm: provide generic compat_sys_readahead() implementation
From: Al Viro @ 2018-03-19 23:23 UTC (permalink / raw)
To: Ingo Molnar
Cc: Linus Torvalds, Dominik Brodowski, Linux Kernel Mailing List,
Arnd Bergmann, linux-arch, Ralf Baechle, James Hogan, linux-mips,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, ppc-dev,
Martin Schwidefsky, Heiko Carstens, linux-s390, David S . Miller,
sparclinux, Ingo Molnar, Jiri Slaby, the arch/x86 maintainers
In-Reply-To: <20180319092920.tbh2xwkruegshzqe@gmail.com>
On Mon, Mar 19, 2018 at 10:29:20AM +0100, Ingo Molnar wrote:
>
> * Al Viro <viro@ZenIV.linux.org.uk> wrote:
>
> > On Sun, Mar 18, 2018 at 06:18:48PM +0000, Al Viro wrote:
> >
> > > I'd done some digging in that area, will find the notes and post.
> >
> > OK, found:
>
> Very nice writeup - IMHO this should go into Documentation/!
If you want to turn that into something printable - more power to you...
FWIW, I think we need to require per-architecture descriptions of ABI
for all architectures. Something along the lines of
alpha:
C ABI: 64bit, location sequence is ($16, $17, $18, $19, $20, $21, stack)
No arg padding (as for all 64bit). Stack pointer in $30, return value
in $0.
Syscall ABI: syscall number in $0, arg slots filled from $16, $17, $18, $19,
$20, $21. Return value in $0, error is reported as 1 in $19. Saved
syscall number is used as a flag for __force_successful_syscall_return()
purposes - sticking 0 there inhibits the effect of negative return value.
arm:
C ABI: 32bit, location sequence is (r0, r1, r2, r3, stack). Arg padding
for 64bit args: to even slot. Stack pointer in sp, return value in r0
Syscall ABI, EABI variant: syscall number in r7.
Syscall ABI, OABI variant: syscall number encoded into insn.
Syscall ABI (both variants): arg slots filled from r0, r1, r2, r3, r4, r5.
Return value in r0. It's not quite a biarch (support of e.g. ioctl
handling is absent, etc.; basic syscalls are handled, but that's it).
etc. Ideally the information about callee-saved registers, syscall restart
logics, etc. should also go there. I'm sick and tired of digging though
the asm glue of unfamiliar architectures ;-/
Another relevant piece of information (especially for biarch) is how
should sub-word arguments be normalized. E.g. on amd64 both int and long
are passed in 64bit words and function that expects an int does *not*
care about the upper 32 bits. If you have long f(int a) {return a;},
it will sign-extend the argument. On ppc, OTOH, it won't - the caller
is responsible for having the bits 31..63 all equal.
That used to be a source of considerable PITA - e.g. kill(2) used to
require a compat wrapper on ppc. These days SYSCALL_DEFINE and
COMPAT_SYSCALL_DEFINE glue takes care of normalizations. However
it doesn't apply for the stuff that does *not* use ...DEFINE and
for use of native syscalls on biarch we need a bit more. Consider
e.g. 32bit syscall on sparc64 wanting to use the native counterpart.
Arguments that are <= 32bit in both ABIs are fine - normalizations
will take care of them. Anything that is 64bit in both ABIs means
that we will need compat anyway - the argument needs to be recombined
from two registers into one. The headache comes from
* signed long
* unsigned long
* pointers
Those are word-sized and we need to normalize. Solution before
SYSCALL_DEFINE glue: have upper halves forcibly zeroed on entry (which
normalizes unsigned long and pointers) and then sign-extend every
signed int and signed long in per-syscall glue (that zeroing is
guaranteed to denormalize int arguments). Once SYSCALL_DEFINE started
to do normalization we disposed on the need to do separate wrappers
for int arguments; that still leaves us with signed long ones, but
* they are very rare
* most of the syscalls passing them need compat for more
serious reasons anyway.
There are only two exceptions - bdflush(2) and pciconfig_iobase(2).
The latter doesn't exist on sparc, the former ignores its signed long
argument completely. So we are left with "zero upper halves of all
argument-bearing registers upon the entry and have per-syscall glue
take care of the rest".
For s390 the situation is nastier - normalization for signed and
unsigned long is the same as usual, but pointers might have junk
in bit 31. IOW, for anything with pointer in arguments we can't
just use the native syscall. As the result, s390 doesn't bother
with zeroing upper halves in syscall dispatcher and does private
mini-wrappers for native syscalls with pointer/long/ulong arguments.
That kind of crap really needs to be documented - RTFS becomes
somewhat painful when it involves tens of assemblers *and*
missing ABI documents (try to locate one for something embedded -
great motivation for expanding vocabulary, that) ;-/
FWIW, SYSCALL_DEFINE and its ilk (COMPAT_SYSCALL_DEFINE,
s390 COMPAT_SYSCALL_WRAP, etc.) are all about stepping over the
ABI gap - we've got some values from userland caller and we
need to turn that into a valid C function call that would
satisfy C ABI constraints. Some amount of normalization might've
been done by syscall dispatcher; this stuff does the rest on
per-function basis.
> One way to implement this would be to put the argument chain types (string) and
> sizes (int) into a special debug section which isn't included in the final kernel
> image but which can be checked at link time.
Umm... Possible, but I actually believe that we can do that without
debug info.
WARNING: AVERT YOUR EYES IF YOU HAVE A WEAK STOMACH. I'm _not_ saying that
the trickery below is a good idea, no need to break out a straightjacket.
It does have some merits, but in the current form it's ugly as hell and
almost certainly not fit for inclusion. Consider that as a theoretical
exercise, please.
Again, don't read further if you are easily squicked. You've been warned.
===============================================================================
Look:
* we can generate
enum {S0 = __TYPE_IS_LL(int),
S1 = __TYPE_IS_LL(loff_t),
S2 = __TYPE_IS_LL(size_t)};
at preprocessor level (inside the compat wrapper being built). Calculations
will be done at compile time, of course, but those _are_ constants (0, 1, 0 in
our case).
* we can generate
enum {OFF0 = 0, OFF1 = STEP(OFF0 + S0, S1), OFF2 = STEP(OFF1 + S1, S2)};
at the same time, with STEP(base, big) defined as base + 1 for something like
x86, (big ? ((base) | 1) + 1 : (base) + 1) for arm and friends,
base + 1 + (big && base == 3) for s390. Again, compile-time calculations.
For x86 - (0, 1, 3), for arm - (0, 2, 4), etc.
* we can generate
C_S_moron((__force int)(S0 ? PAIR(OFF0) : ARG(OFF0)),
(__force loff_t)(S1 ? PAIR(OFF1) : ARG(OFF1)),
(__force size_t)(S2 ? PAIR(OFF2) : ARG(OFF2)));
in the body of wrapper. With PAIR(n) defined as either ((u64)ARG(n) << 32) | ARG(n+1)
or ((u64)ARG(n+1) << 32) | ARG(n) (depending upon endianness) and ARG(n)
defined as (n == 0 ? a0 : n == 1 ? a1 : n == 2 ? a2 : n == 3 ? a3 :
n == 4 ? a4 : n == 5 ? a5 : a6)
Note that each of those suckers expands to a cascade of conditional
expressions with all conditions being integer constant expressions,
no more than one of those being true. In our case that crap will fold into
C_S_moron((__force int)a0,
(__force loff_t)(((u64)a2 << 32)|a1),
(__force size_t)a3);
as soon as optimizations at the level of 0 ? x : y => y and 1 ? x : y => x
are done. And we have, in effect,
static inline long C_S_moron(int, loff_t, size_t);
long compat_SyS_moron(long a0, long a1, long a2, long a3, long a4, long a5, long a6)
{
return C_S_moron((__force int)a0,
(__force loff_t)(((u64)a2 << 32)|a1),
(__force size_t)a3);
}
static inline long C_S_moron(int fd, loff_t offset, size_t count)
{
whatever body you had for it
}
That - from
COMPAT_SYSCALL_DEFINE3(moron, int, fd, loff_t, offset, size_t, count)
{
whatever body you had for it
}
We can use similar machinery for SYSCALL_DEFINE itself, so that
SyS_moron() would be defined with (long, long, long, long, long, long)
as arguments and not (long, long long, long) as we have now.
It's not impossible to do. It won't be pretty, but that use of local
enums allows to avoid unbearably long expansions.
Benefits:
* all SyS... wrappers (i.e. the thing that really ought to
go into syscall tables) have the same type.
* we could have SYSCALL_DEFINE produce a trivial compat
wrapper, have explicit COMPAT_SYSCALL_DEFINE discard that thing
and populate the compat syscall table *entirely* with compat_SyS_...,
letting the linker sort it out. That way we don't need to keep
track of what can use native and what needs compat in each compat
table on biarch.
* s390 compat wrappers would disappear with that approach.
* we could even stop generating sys_... aliases - if
syscall table is generated by slapping SyS_... or compat_SyS_...
on the name given there, we don't need to _have_ those sys_...
things at all. All SyS_... would have the same type, so the pile
in syscalls.h would not be needed - we could generate the externs
at the same time we generate the syscall table.
And yes, it's a high-squick approach. I know and I'm not saying
it's a good idea. OTOH, to quote the motto of philosophers and
shell game operators, "there's something in it"...
> For example this attempt at creating a new system call:
>
> SYSCALL_DEFINE3(moron, int, fd, loff_t, offset, size_t, count)
>
> ... would translate into something like:
>
> .name = "moron", .pattern = "WWW", .type = "int", .size = 4,
> .name = NULL, .type = "loff_t", .size = 8,
> .name = NULL, .type = "size_t", .size = 4,
> .name = NULL, .type = NULL, .size = 0, /* end of parameter list */
>
> i.e. "WDW". The build-time constraint checker could then warn about:
>
> # error: System call "moron" uses invalid 'WWW' argument mapping for a 'WDW' sequence
> # please avoid long-long arguments or use 'SYSCALL_DEFINE3_WDW()' instead
... if you do 32bit build.
> Each architecture can provide its own syscall parameter checking logic. Both
> 'stack boundary' and parameter packing rules would be straightforward to express
> if we had such a data structure.
>
> Also note that this tool could also check for optimum packing, i.e. if the new
> system call is defined as:
>
> SYSCALL_DEFINE3_WDW(moron, int, fd, loff_t, offset, size_t, count)
> Such tooling could also do other things, such as limit the C types used for system
> call defines to a well-chosen set of ABI-safe types, such as:
>
> 3 key_t
> 3 uint32_t
> 4 aio_context_t
> 4 mqd_t
> 4 timer_t
> 10 clockid_t
> 10 gid_t
> 10 loff_t
> 10 long
Uhhuh - ABI-safe is not how I would describe that. Sodding PITA, fortunately
rare, is more like it...
> 10 old_gid_t
> 10 old_uid_t
> 10 umode_t
> 11 uid_t
> 31 pid_t
> 34 size_t
> 69 unsigned int
> 130 unsigned long
> 226 int
>
> This would also allow us some cleanups as well, such as dropping the pointless
> 'const' from arithmetic types in syscall definitions for example.
>
> etc.
>
> Basically this tool would be a secondary parser of the syscall arguments, with
> most of the parsing and type sizing difficulties solved by the C parser already.
>
> I think this problem could be much more sanely solved via annotations and a bit of
> tooling, than trying to trick CPP into doing this for us (which won't really work
> in any case).
See above. It *can* be done. Not by cpp alone, of course - you need compiler
involvement.
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/mm: Trace tlbia instruction
From: Balbir Singh @ 2018-03-19 22:43 UTC (permalink / raw)
To: Christophe Leroy
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, linux-kernel, linuxppc-dev
In-Reply-To: <cccc5b8516ce8cb57bedf2c51cf67f9a2ca95242.1521452718.git.christophe.leroy@c-s.fr>
On Mon, 19 Mar 2018 11:32:40 +0100 (CET)
Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> Add a trace point for tlbia (Translation Lookaside Buffer Invalidate
> All) instruction.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/include/asm/trace.h | 15 +++++++++++++++
> arch/powerpc/mm/mmu_decl.h | 2 ++
> 2 files changed, 17 insertions(+)
>
> diff --git a/arch/powerpc/include/asm/trace.h b/arch/powerpc/include/asm/trace.h
> index 33f3b479138b..d1d63b173dd7 100644
> --- a/arch/powerpc/include/asm/trace.h
> +++ b/arch/powerpc/include/asm/trace.h
> @@ -202,6 +202,21 @@ TRACE_EVENT(tlbie,
> __entry->r)
> );
>
> +TRACE_EVENT(tlbia,
> +
> + TP_PROTO(unsigned long lpid),
> + TP_ARGS(lpid),
> + TP_STRUCT__entry(
> + __field(unsigned long, lpid)
> + ),
> +
> + TP_fast_assign(
> + __entry->lpid = lpid;
> + ),
> +
> + TP_printk("lpid=%ld", __entry->lpid)
> +);
Do we want to call this lpid?
Balbir Singh.
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/mm: Add missing tracepoint for tlbie
From: Balbir Singh @ 2018-03-19 22:39 UTC (permalink / raw)
To: Christophe Leroy
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Scott Wood, linux-kernel, linuxppc-dev
In-Reply-To: <4ffd3d6143f991615ffe07f43952cbc62163d319.1521452718.git.christophe.leroy@c-s.fr>
On Mon, 19 Mar 2018 11:32:38 +0100 (CET)
Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> commit 0428491cba927 ("powerpc/mm: Trace tlbie(l) instructions")
> added tracepoints for tlbie calls, but _tlbil_va() was forgotten
>
> Fixes: 0428491cba927 ("powerpc/mm: Trace tlbie(l) instructions")
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/mm/mmu_decl.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
> index 57fbc554c785..b9991e0c61a2 100644
> --- a/arch/powerpc/mm/mmu_decl.h
> +++ b/arch/powerpc/mm/mmu_decl.h
> @@ -21,6 +21,7 @@
> #include <linux/mm.h>
> #include <asm/tlbflush.h>
> #include <asm/mmu.h>
> +#include <asm/trace.h>
>
> #ifdef CONFIG_PPC_MMU_NOHASH
>
> @@ -56,6 +57,7 @@ static inline void _tlbil_va(unsigned long address, unsigned int pid,
> unsigned int tsize, unsigned int ind)
> {
> asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
> + trace_tlbie(pid, 0, address, 0, 0, 0, 0);
I did not really cover a whole lot of NOHASH, any idea why its
called tlbil_va and not _tlbie_va?
The first field is really the lpid and should be 0 for non-virtualized
systems. Can I recommend that we rs field for pid and the rb field for
address? so effectively something like
trace_tlbie(0, 0, address, pid, 0, 0, 0);
Balbir
^ permalink raw reply
* Re: [PATCH 1/2] powerpc64/ftrace: Add a field in paca to disable ftrace in unsafe code paths
From: Michael Ellerman @ 2018-03-19 22:34 UTC (permalink / raw)
To: Nicholas Piggin, Naveen N. Rao
Cc: Steven Rostedt, Paul Mackerras, linuxppc-dev,
Benjamin Herrenschmidt, Anton Blanchard, sathnaga
In-Reply-To: <20180319204059.4c3a698e@roar.ozlabs.ibm.com>
Nicholas Piggin <npiggin@gmail.com> writes:
> On Mon, 19 Mar 2018 14:43:00 +0530
> "Naveen N. Rao" <naveen.n.rao@linux.vnet.ibm.com> wrote:
>
>> We have some C code that we call into from real mode where we cannot
>> take any exceptions. Though the C functions themselves are mostly safe,
>> if these functions are traced, there is a possibility that we may take
>> an exception. For instance, in certain conditions, the ftrace code uses
>> WARN(), which uses a 'trap' to do its job.
>>
>> For such scenarios, introduce a new field in paca 'ftrace_disabled',
>> which is checked on ftrace entry before continuing. This field can then
>> be set to a non-zero value to disable/pause ftrace, and reset to zero to
>> resume ftrace.
>>
>> Since KVM is the only user for this currently, we guard the
>> ftrace/mcount checks within CONFIG_KVM. This can later be removed
>> if/when there are other users.
>
> Why not test HSTATE_IN_GUEST then? Add ftrace_disabled if non-KVM users
> come along.
We want to use it for the kexec down path, we've already had bugs there.
So please keep the separate flag and pull it out of #ifdef KVM.
If we're worried about space usage in the paca we can probably
consolidate this and some other things into a flags word.
cheers
^ permalink raw reply
* Re: [PATCH 1/1] PCI set flag PCI_SCAN_ALL_PCIE_DEVS for P.A. Semi boards
From: Michael Ellerman @ 2018-03-19 22:32 UTC (permalink / raw)
To: Bjorn Helgaas, Christian Zigotzky
Cc: Bjorn Helgaas, linux-pci, Olof Johansson, linuxppc-dev
In-Reply-To: <20180319191310.GG77194@bhelgaas-glaptop.roam.corp.google.com>
Bjorn Helgaas <helgaas@kernel.org> writes:
> On Fri, Mar 16, 2018 at 01:55:36PM +0100, Christian Zigotzky wrote:
>> Bjorn Helgaas created a patch for making PCI_SCAN_ALL_PCIE_DEVS work for
>> Root Ports as well as Downstream. Previously PCI_SCAN_ALL_PCIE_DEVS (set=
by
>> quirks or the "pci=3Dpcie_scan_all"
>> kernel parameter) only affected Switch Downstream Ports, not Root Ports.=
The
>> problem is, that we have to add always the boot argument "pci=3Dpcie_sca=
n_all"
>> for using Bjorn's improvements. Without the boot argument
>> "pci=3Dpcie_scan_all", the kernel doesn't boot on P.A. Semi boards with =
SB600
>> chipset (SB600 chipset is connected via PCIe x4 to the P.A. Semi=E2=80=
=99s
>> PA6T-1682M System-on-a-Chip) because the kernel can't find any drives
>> connected to the SB600 anymore. Olof Johansson has created a patch for
>> executing "pci=3Dpcie_scan_all" automatically on P.A. Semi boards. With =
his
>> patch, we don't need to add 'pci=3Dpcie_scan_all' to the kernel boot arg=
uments
>> anymore.
>
> The patch looks fine, but I need a signed-off-by line before I can apply
> it. See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.g=
it/tree/Documentation/process/submitting-patches.rst
I'm happy to take it, I've been meaning to check if Olof sent a SOB in
his original mail but haven't got to it.
...
Yes, he did, see below.
So I'll merge that, I'll add a Tested-by for you Christian.
Christian please don't remove any of the tags when submitting other
peoples' patches in future.
cheers
>From a3b390277627b0342c8ccfc16e58679e0d8abdde Mon Sep 17 00:00:00 2001
From: Olof Johansson <olof@lixom.net>
Date: Sat, 2 Dec 2017 14:56:36 -0800
Subject: [PATCH] powerpc/pasemi: set PCI_SCAN_ALL_PCI_DEVS
Needed on Amiga X1000 with SB600.
Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
---
arch/powerpc/platforms/pasemi/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/p=
asemi/pci.c
index 5ff6108..ea54ed2 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -224,6 +224,8 @@ void __init pas_pci_init(void)
return;
}
+ pci_set_flag(PCI_SCAN_ALL_PCIE_DEVS):
+
for (np =3D NULL; (np =3D of_get_next_child(root, np)) !=3D NULL;)
if (np->name && !strcmp(np->name, "pxp") && !pas_add_bridge(np))
of_node_get(np);
^ permalink raw reply related
* Re: [01/10] selftests/powerpc: add process creation benchmark
From: Michael Ellerman @ 2018-03-19 22:23 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev; +Cc: Aneesh Kumar K . V, Nicholas Piggin
In-Reply-To: <20180306132507.10649-2-npiggin@gmail.com>
On Tue, 2018-03-06 at 13:24:58 UTC, Nicholas Piggin wrote:
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/838fd21b1bde8ed16e64289a8c7467
cheers
^ permalink raw reply
* Re: powerpc: dts: replace 'linux,stdout-path' with 'stdout-path'
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, linux-kernel, Paul Mackerras,
linuxppc-dev
In-Reply-To: <20180228224406.7049-1-robh@kernel.org>
On Wed, 2018-02-28 at 22:44:06 UTC, Rob Herring wrote:
> 'linux,stdout-path' has been deprecated for some time in favor of
> 'stdout-path'. Now dtc will warn on occurrences of 'linux,stdout-path'.
> Search and replace all the of occurrences with 'stdout-path'.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: linuxppc-dev@lists.ozlabs.org
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/d79a02b3e03b103d84536fb19ae7a7
cheers
^ permalink raw reply
* Re: powerpc/time: stop validating rtc_time in .read_time
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Alexandre Belloni
Cc: linux-rtc, Alexandre Belloni, linux-kernel, Paul Mackerras,
linuxppc-dev
In-Reply-To: <20180221214633.2012-1-alexandre.belloni@bootlin.com>
On Wed, 2018-02-21 at 21:46:33 UTC, Alexandre Belloni wrote:
> The RTC core is always calling rtc_valid_tm after the read_time callback.
> It is not necessary to call it just before returning from the callback.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/890ae7979758568734881ad0f382c4
cheers
^ permalink raw reply
* Re: [V6] cxl: Fix timebase synchronization status on P9
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Christophe Lombard, linuxppc-dev, fbarrat, vaibhav,
andrew.donnellan
In-Reply-To: <1519134536-16485-1-git-send-email-clombard@linux.vnet.ibm.com>
On Tue, 2018-02-20 at 13:48:56 UTC, Christophe Lombard wrote:
> The PSL Timebase register is updated by the PSL to maintain the
> timebase.
> On P9, the Timebase value is only provided by the CAPP as received
> the last time a timebase request was performed.
> The timebase requests are initiated through the adapter configuration or
> application registers.
> The specific sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced" is
> now dynamically updated according the content of the PSL Timebase
> register.
>
> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
> Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
> Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/c2be663d5307fb9751a562ac664fa7
cheers
^ permalink raw reply
* Re: [RESEND] powerpc/5200: dts: digsy_mtc.dts: fix rv3029 compatible
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Alexandre Belloni
Cc: linux-rtc, Alexandre Belloni, linuxppc-dev, linux-kernel
In-Reply-To: <20180216234323.27601-1-alexandre.belloni@bootlin.com>
On Fri, 2018-02-16 at 23:43:23 UTC, Alexandre Belloni wrote:
> The proper compatible for rv3029 is microcrystal,rv3029.
>
> Acked-by: Anatolij Gustschin <agust@denx.de>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/7004263bd4f4c79da9ca2a1d04d38d
cheers
^ permalink raw reply
* Re: Fix cleanup when VAS is not configured
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Sukadev Bhattiprolu; +Cc: linuxppc-dev, mikey, linux-kernel
In-Reply-To: <20180213195327.GA10678@us.ibm.com>
On Tue, 2018-02-13 at 19:53:27 UTC, Sukadev Bhattiprolu wrote:
> From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
> Date: Fri, 9 Feb 2018 11:49:06 -0600
> Subject: [PATCH 1/1] powerpc/vas: Fix cleanup when VAS is not configured
>
> When VAS is not configured, unregister the platform driver. Also simplify
> cleanup by delaying vas debugfs init until we know VAS is configured.
>
> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/45ddea8a73a25461387eb8e87f3e0e
cheers
^ permalink raw reply
* Re: [4/4] powerpc/vas: Add a couple of trace points
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Sukadev Bhattiprolu; +Cc: linuxppc-dev, mikey, linux-kernel
In-Reply-To: <1518234567-24869-4-git-send-email-sukadev@linux.vnet.ibm.com>
On Sat, 2018-02-10 at 03:49:27 UTC, Sukadev Bhattiprolu wrote:
> Add a couple of trace points in the VAS driver
>
> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/007bb7d6c77ef2243dabf9c4132afa
cheers
^ permalink raw reply
* Re: powerpc/npu-dma.c: Fix crash after __mmu_notifier_register failure
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Mark Hairgrove, linuxppc-dev; +Cc: Alistair Popple, Mark Hairgrove
In-Reply-To: <1518232806-17661-1-git-send-email-mhairgrove@nvidia.com>
On Sat, 2018-02-10 at 03:20:06 UTC, Mark Hairgrove wrote:
> pnv_npu2_init_context wasn't checking the return code from
> __mmu_notifier_register. If __mmu_notifier_register failed, the
> npu_context was still assigned to the mm and the caller wasn't given any
> indication that things went wrong. Later on pnv_npu2_destroy_context would
> be called, which in turn called mmu_notifier_unregister and dropped
> mm->mm_count without having incremented it in the first place. This led to
> various forms of corruption like mm use-after-free and mm double-free.
>
> __mmu_notifier_register can fail with EINTR if a signal is pending, so
> this case can be frequent.
>
> This patch calls opal_npu_destroy_context on the failure paths, and makes
> sure not to assign mm->context.npu_context until past the failure points.
>
> Signed-off-by: Mark Hairgrove <mhairgrove@nvidia.com>
> Acked-By: Alistair Popple <alistair@popple.id.au>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/720c84046c26444fe825f8614ddceb
cheers
^ permalink raw reply
* Re: [v6, 1/2] raid6/altivec: Add vpermxor implementation for raid6 Q syndrome
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Matt Brown, linuxppc-dev; +Cc: dja
In-Reply-To: <20170804034233.13628-1-matthew.brown.dev@gmail.com>
On Fri, 2017-08-04 at 03:42:32 UTC, Matt Brown wrote:
> This patch uses the vpermxor instruction to optimise the raid6 Q syndrome.
> This instruction was made available with POWER8, ISA version 2.07.
> It allows for both vperm and vxor instructions to be done in a single
> instruction. This has been tested for correctness on a ppc64le vm with a
> basic RAID6 setup containing 5 drives.
>
> The performance benchmarks are from the raid6test in the /lib/raid6/test
> directory. These results are from an IBM Firestone machine with ppc64le
> architecture. The benchmark results show a 35% speed increase over the best
> existing algorithm for powerpc (altivec). The raid6test has also been run
> on a big-endian ppc64 vm to ensure it also works for big-endian
> architectures.
>
> Performance benchmarks:
> raid6: altivecx4 gen() 18773 MB/s
> raid6: altivecx8 gen() 19438 MB/s
>
> raid6: vpermxor4 gen() 25112 MB/s
> raid6: vpermxor8 gen() 26279 MB/s
>
> Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com>
> Reviewed-by: Daniel Axtens <dja@axtens.net>
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/2de95953c4e6ad54c9bee5e6a5518d
cheers
^ permalink raw reply
* Re: powerpc/include/asm: Remove unused 64bit cacheflush function
From: Michael Ellerman @ 2018-03-19 22:22 UTC (permalink / raw)
To: Matt Brown, linuxppc-dev
In-Reply-To: <20170720062514.2069-1-matthew.brown.dev@gmail.com>
On Thu, 2017-07-20 at 06:25:14 UTC, Matt Brown wrote:
> The flush_dcache_phys_range function is no longer used in the kernel.
> This patch removes and cleans up the function.
>
> Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/1d82fc5c54ef7956f5c01bbcf26b52
cheers
^ permalink raw reply
* [PATCH 3/3] powerpc: Free up CPU feature bits on 64-bit machines
From: Paul Mackerras @ 2018-03-19 21:46 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1521495973-3237-1-git-send-email-paulus@ozlabs.org>
This moves all the CPU feature bits that are only used on 32-bit
machines to the top 20 bits of the CPU feature word and arranges
for them to be defined only in 32-bit builds. The features that
are common to 32-bit and 64-bit machines are moved to bits 0-11
of the CPU feature word. This means that for 64-bit platforms,
bits 44-63 can now be used for new features that only exist on
64-bit machines. (These bit numbers are counting from the right,
i.e. the LSB is bit 0.)
Because CPU_FTR_L3_DISABLE_NAP moved from the low 16 bits to the high
16 bits, we have to adjust some assembly code. Also, CPU_FTR_EMB_HV
moved from the high 16 bits to the low 16 bits.
Note that CPU_FTR_REAL_LE only applies to 64-bit chips, because only
64-bit chips (POWER6, 7, 8, 9) have a true little-endian mode that is
a CPU execution mode as opposed to being a page attribute.
With this we now have 20 free CPU feature bits on 64-bit machines.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/cputable.h | 133 ++++++++++++++++--------------
arch/powerpc/kernel/cpu_setup_6xx.S | 2 +-
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
3 files changed, 73 insertions(+), 64 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 761b99c..49fd067 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -131,40 +131,48 @@ static inline void cpu_feature_keys_init(void) { }
/* CPU kernel features */
-/* Retain the 32b definitions all use bottom half of word */
+/* Definitions for features that we have on both 32-bit and 64-bit chips */
#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
-#define CPU_FTR_L2CR ASM_CONST(0x00000002)
-#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
-#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
-#define CPU_FTR_TAU ASM_CONST(0x00000010)
-#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
-#define CPU_FTR_USE_RTC ASM_CONST(0x00000040)
-#define CPU_FTR_601 ASM_CONST(0x00000100)
-#define CPU_FTR_DBELL ASM_CONST(0x00000200)
-#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
-#define CPU_FTR_L3CR ASM_CONST(0x00000800)
-#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
-#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
-#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
-#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
-#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
-#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
-#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
-#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
-#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
-#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
-#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
-#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
-#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
-#define CPU_FTR_SPE ASM_CONST(0x02000000)
-#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
-#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
-#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
-#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
-#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
+#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
+#define CPU_FTR_DBELL ASM_CONST(0x00000004)
+#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
+#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
+#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
+#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
+#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
+#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
+#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
+
+/* Definitions for features that only exist on 32-bit chips */
+#ifdef CONFIG_PPC32
+#define CPU_FTR_601 ASM_CONST(0x00001000)
+#define CPU_FTR_L2CR ASM_CONST(0x00002000)
+#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
+#define CPU_FTR_TAU ASM_CONST(0x00008000)
+#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
+#define CPU_FTR_USE_RTC ASM_CONST(0x00020000)
+#define CPU_FTR_L3CR ASM_CONST(0x00040000)
+#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
+#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
+#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
+#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
+#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
+#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
+#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
+#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
+#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x08000000)
+#define CPU_FTR_SPE ASM_CONST(0x10000000)
+#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
+#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
+
+#else /* CONFIG_PPC32 */
+/* Define these to 0 for the sake of tests in common code */
+#define CPU_FTR_601 (0)
+#define CPU_FTR_PPC_LE (0)
+#endif
/*
- * Add the 64-bit processor unique features in the top half of the word;
+ * Definitions for the 64-bit processor unique features;
* on 32-bit, make the names available but defined to be 0.
*/
#ifdef __powerpc64__
@@ -173,37 +181,38 @@ static inline void cpu_feature_keys_init(void) { }
#define LONG_ASM_CONST(x) 0
#endif
-#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
-#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
-#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
-#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
-#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
-#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
-#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
-#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
-#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
-#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
-#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
-#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
-#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
-#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
-#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
-#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
-#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
-#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
-#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
-#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
-#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
-#define CPU_FTR_PKEY LONG_ASM_CONST(0x0020000000000000)
-#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
-#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
-#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
-#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
-#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
-#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
-#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
-#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
-#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x8000000000000000)
+#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
+#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
+#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000000004000)
+#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
+#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
+#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
+#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
+#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
+#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
+#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
+#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
+#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
+#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
+#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
+#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
+#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
+#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
+#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
+#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
+#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
+#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
+#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
+#define CPU_FTR_PKEY LONG_ASM_CONST(0x0000000400000000)
+#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
+#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
+#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
+#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
+#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
+#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
+#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
+#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x0000040000000000)
+#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
index c5e5a94..a9f3970 100644
--- a/arch/powerpc/kernel/cpu_setup_6xx.S
+++ b/arch/powerpc/kernel/cpu_setup_6xx.S
@@ -226,7 +226,7 @@ BEGIN_FTR_SECTION
beq 1f
END_FTR_SECTION_IFSET(CPU_FTR_L3CR)
lwz r6,CPU_SPEC_FEATURES(r4)
- andi. r0,r6,CPU_FTR_L3_DISABLE_NAP
+ andis. r0,r6,CPU_FTR_L3_DISABLE_NAP@h
beq 1f
li r7,CPU_FTR_CAN_NAP
andc r6,r6,r7
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 462aed9..8d142e5 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -162,7 +162,7 @@ _GLOBAL(__setup_cpu_e5500)
* the feature on the primary core, avoid doing it on the
* secondary core.
*/
- andis. r6, r3, CPU_FTR_EMB_HV@h
+ andi. r6, r3, CPU_FTR_EMB_HV
beq 2f
rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV
stw r3, CPU_SPEC_FEATURES(r4)
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] powerpc: Use feature bit for RTC presence rather than timebase presence
From: Paul Mackerras @ 2018-03-19 21:46 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1521495973-3237-1-git-send-email-paulus@ozlabs.org>
All PowerPC CPUs other than the original PPC601 have a timebase
register rather than the "real-time clock" (RTC) register that the
PPC601 (and the original POWER and POWER2 CPUs) had. Currently
we have a CPU feature bit to indicate the presence of the timebase,
but it makes more sense to use a bit to indicate the unusual
situation rather than the common situation. This therefore defines
a CPU_FTR_USE_RTC bit in place of the CPU_FTR_USE_TB bit, and
arranges for it to be set on PPC601 systems.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/cputable.h | 85 +++++++++++++++++--------------------
arch/powerpc/include/asm/time.h | 2 +-
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +-
arch/powerpc/kernel/vdso.c | 12 +++---
4 files changed, 47 insertions(+), 55 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index a2c5c95..052db18 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -138,7 +138,7 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
#define CPU_FTR_TAU ASM_CONST(0x00000010)
#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
-#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
+#define CPU_FTR_USE_RTC ASM_CONST(0x00000040)
#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
#define CPU_FTR_601 ASM_CONST(0x00000100)
#define CPU_FTR_DBELL ASM_CONST(0x00000200)
@@ -285,21 +285,19 @@ static inline void cpu_feature_keys_init(void) { }
#endif
#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
- CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
-#define CPU_FTRS_603 (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+ CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)
+#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
-#define CPU_FTRS_604 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
+#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_740 (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_PPC_LE)
#define CPU_FTRS_750 (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_PPC_LE)
#define CPU_FTRS_750CL (CPU_FTRS_750)
@@ -308,103 +306,96 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
#define CPU_FTRS_750GX (CPU_FTRS_750FX)
#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
+ CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
+ CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+ CPU_FTR_NEED_PAIRED_STWCX | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+ CPU_FTR_NEED_PAIRED_STWCX | \
CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
+ CPU_FTR_NEED_PAIRED_STWCX | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
- CPU_FTR_USE_TB | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
-#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
- CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
+#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)
#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
+ CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
+ CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_COMMON)
#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
- CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
+ CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
-#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
-#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
+#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
+#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
+#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
CPU_FTR_INDEXED_DCR)
#define CPU_FTRS_47X (CPU_FTRS_440x6)
-#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
+#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
CPU_FTR_DEBUG_LVL_EXC)
-#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
+#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
-#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
/*
* e5500/e6500 erratum A-006958 is a timebase bug that can use the
* same workaround as CPU_FTR_CELL_TB_BUG.
*/
-#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
-#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
+#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
@@ -412,21 +403,21 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
/* 64-bit CPUs */
-#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER4 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_STCX_CHECKS_ADDRESS)
-#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
CPU_FTR_HVMODE | CPU_FTR_DABRX)
-#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
-#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | \
@@ -434,7 +425,7 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
CPU_FTR_DABRX)
-#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | \
@@ -443,7 +434,7 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_CFAR | CPU_FTR_HVMODE | \
CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
-#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | \
@@ -455,7 +446,7 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
-#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | \
@@ -470,15 +461,15 @@ static inline void cpu_feature_keys_init(void) { }
(~CPU_FTR_SAO))
#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
-#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
-#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
-#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
+#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
#ifdef __powerpc64__
#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index 828ebe7..db546c0 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -47,7 +47,7 @@ struct div_result {
/* Accessor functions for the timebase (RTC on 601) registers. */
/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
#ifdef CONFIG_6xx
-#define __USE_RTC() (!cpu_has_feature(CPU_FTR_USE_TB))
+#define __USE_RTC() (cpu_has_feature(CPU_FTR_USE_RTC))
#else
#define __USE_RTC() 0
#endif
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 945e2c2..ee562ff 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -54,8 +54,7 @@ struct dt_cpu_feature {
};
#define CPU_FTRS_BASE \
- (CPU_FTR_USE_TB | \
- CPU_FTR_LWSYNC | \
+ (CPU_FTR_LWSYNC | \
CPU_FTR_FPU_UNAVAILABLE |\
CPU_FTR_NODSISRALIGN |\
CPU_FTR_NOEXECUTE |\
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 22b01a3..b44ec10 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -99,26 +99,28 @@ static struct vdso_patch_def vdso_patches[] = {
CPU_FTR_COHERENT_ICACHE, CPU_FTR_COHERENT_ICACHE,
"__kernel_sync_dicache", "__kernel_sync_dicache_p5"
},
+#ifdef CONFIG_PPC32
{
- CPU_FTR_USE_TB, 0,
+ CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_gettimeofday", NULL
},
{
- CPU_FTR_USE_TB, 0,
+ CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_clock_gettime", NULL
},
{
- CPU_FTR_USE_TB, 0,
+ CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_clock_getres", NULL
},
{
- CPU_FTR_USE_TB, 0,
+ CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_get_tbfreq", NULL
},
{
- CPU_FTR_USE_TB, 0,
+ CPU_FTR_USE_RTC, CPU_FTR_USE_RTC,
"__kernel_time", NULL
},
+#endif
};
/*
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] powerpc: Book E: Remove unused CPU_FTR_L2CSR bit
From: Paul Mackerras @ 2018-03-19 21:46 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1521495973-3237-1-git-send-email-paulus@ozlabs.org>
The CPU_FTR_L2CSR bit is never tested anywhere, so let's reclaim the bit.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/cputable.h | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 052db18..761b99c 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -139,7 +139,6 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_TAU ASM_CONST(0x00000010)
#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
#define CPU_FTR_USE_RTC ASM_CONST(0x00000040)
-#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
#define CPU_FTR_601 ASM_CONST(0x00000100)
#define CPU_FTR_DBELL ASM_CONST(0x00000200)
#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
@@ -385,18 +384,18 @@ static inline void cpu_feature_keys_init(void) { }
CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
- CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
/*
* e5500/e6500 erratum A-006958 is a timebase bug that can use the
* same workaround as CPU_FTR_CELL_TB_BUG.
*/
#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
- CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
- CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
+ CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
--
2.7.4
^ permalink raw reply related
* [PATCH 0/3] powerpc: Free up CPU feature bits
From: Paul Mackerras @ 2018-03-19 21:46 UTC (permalink / raw)
To: linuxppc-dev
This patch series is against the powerpc next branch. It takes
advantage of the fact that there are only a few CPU feature bits that
are meaningful on both 32-bit and 64-bit platforms. At the moment,
many of the 64 bits of the CPU feature mask on 64-bit platforms are
taken up with bits which are only relevant to 32-bit platforms. This
series rearranges things so that we can use those bits for new
features that are relevant only to 64-bit platforms. With this, there
are now 20 bits available for new 64-bit features.
To make things simpler, we use the bottom 12 bits of the CPU feature
word for features that are relevant to both 32-bit and 64-bit
platforms. The remaining 20 or 52 bits are then available for
features specific to 32-bit or 64-bit platforms.
Paul.
arch/powerpc/include/asm/cputable.h | 223 +++++++++++++++---------------
arch/powerpc/include/asm/time.h | 2 +-
arch/powerpc/kernel/cpu_setup_6xx.S | 2 +-
arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +-
arch/powerpc/kernel/dt_cpu_ftrs.c | 3 +-
arch/powerpc/kernel/vdso.c | 12 +-
6 files changed, 122 insertions(+), 122 deletions(-)
^ permalink raw reply
* Re: [PATCHv5 1/3] powerpc, cpu: partially unbind the mapping between cpu logical id and its seq in dt
From: kbuild test robot @ 2018-03-19 21:13 UTC (permalink / raw)
To: Pingfan Liu; +Cc: kbuild-all, linuxppc-dev, cascardo, gpiccoli, kexec
In-Reply-To: <1521088912-31742-2-git-send-email-kernelfans@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2155 bytes --]
Hi Pingfan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on v4.16-rc4]
[also build test ERROR on next-20180319]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Pingfan-Liu/enable-nr_cpus-for-powerpc/20180318-041117
config: powerpc-tqm8548_defconfig (attached as .config)
compiler: powerpc-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=powerpc
All errors (new ones prefixed by >>):
>> arch/powerpc/kernel/prom.c:79:23: error: 'boot_cpu_count' defined but not used [-Werror=unused-variable]
static int __initdata boot_cpu_count;
^~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/boot_cpu_count +79 arch/powerpc/kernel/prom.c
9b6b563c Paul Mackerras 2005-10-06 71
9b6b563c Paul Mackerras 2005-10-06 72 #ifdef CONFIG_PPC64
28897731 Olof Johansson 2006-04-12 73 int __initdata iommu_is_off;
9b6b563c Paul Mackerras 2005-10-06 74 int __initdata iommu_force_on;
cf00a8d1 Paul Mackerras 2005-10-31 75 unsigned long tce_alloc_start, tce_alloc_end;
cd3db0c4 Benjamin Herrenschmidt 2010-07-06 76 u64 ppc64_rma_size;
9b6b563c Paul Mackerras 2005-10-06 77 #endif
03bf469a Benjamin Herrenschmidt 2011-05-11 78 static phys_addr_t first_memblock_size;
7ac87abb Matt Evans 2011-05-25 @79 static int __initdata boot_cpu_count;
9b6b563c Paul Mackerras 2005-10-06 80
:::::: The code at line 79 was first introduced by commit
:::::: 7ac87abb8166b99584149fcfb2efef5773a078e9 powerpc: Fix early boot accounting of CPUs
:::::: TO: Matt Evans <matt@ozlabs.org>
:::::: CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 15193 bytes --]
^ permalink raw reply
* Re: [PATCH 1/1] PCI set flag PCI_SCAN_ALL_PCIE_DEVS for P.A. Semi boards
From: Christian Zigotzky @ 2018-03-19 20:46 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: Bjorn Helgaas, linux-pci, linuxppc-dev, Olof Johansson
In-Reply-To: <20180319191310.GG77194@bhelgaas-glaptop.roam.corp.google.com>
Hello Bjorn,
Thanks for your reply. Olof wrote this patch.
@Olof
Could you please sign off this patch?
Thanks,
Christian
On 19. Mar 2018, at 20:13, Bjorn Helgaas <helgaas@kernel.org> wrote:
The patch looks fine, but I need a signed-off-by line before I can apply
it. See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/=
tree/Documentation/process/submitting-patches.rst
---
arch/powerpc/platforms/pasemi/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pasemi/pci.c
b/arch/powerpc/platforms/pasemi/pci.c
index 5ff6108..ea54ed2 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -224,6 +224,8 @@ void __init pas_pci_init(void)
return;
}
+ pci_set_flags(PCI_SCAN_ALL_PCIE_DEVS);
+
for (np =3D NULL; (np =3D of_get_next_child(root, np)) !=3D NULL;)
if (np->name && !strcmp(np->name, "pxp") && !pas_add_bridge(np))
of_node_get(np);
--
^ permalink raw reply related
* Re: [GIT PULL 00/14] perf/core improvements and fixes
From: Ingo Molnar @ 2018-03-19 19:39 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: linux-kernel, linux-perf-users, Adrian Hunter, Alexander Shishkin,
Andi Kleen, Colin King, David Ahern, Jin Yao, Jiri Olsa,
Josh Poimboeuf, Kan Liang, kernel-janitors, Laura Abbott,
linux-kselftest, linuxppc-dev, linux-trace-users,
Masami Hiramatsu, Namhyung Kim, Peter Zijlstra, Ravi Bangoria,
Sergey Senozhatsky, Shuah Khan, Stephane Eranian, Steven Rostedt,
Sukadev Bhattiprolu, Tom Zanussi, Wang Nan, Willy Tarreau,
Yisheng Xie, Arnaldo Carvalho de Melo
In-Reply-To: <20180319190136.7441-1-acme@kernel.org>
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> Hi Ingo,
>
> Please consider pulling, this has those 31 patches that were
> blocked due to some problems (author not being the fist S-o-B, build
> broken on ppc), those issues should all be fixed and then we have 14
> patches more, described in the signed tag.
>
> Regards,
>
> - Arnaldo
>
> Test results at the end of this message, as usual.
>
> The following changes since commit 10f354a36f9a9aa1b8bffe0abc1cd43822a85bcd:
>
> perf test: Fix exit code for record+probe_libc_inet_pton.sh (2018-03-16 13:56:31 -0300)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180319
>
> for you to fetch changes up to 1cd618838b9703eabe4a75badf433382b12f6bef:
>
> perf tests bp_account: Fix build with clang-6 (2018-03-19 13:51:54 -0300)
>
> ----------------------------------------------------------------
> perf/core improvements and fixes:
>
> - Fixes for problems experienced with new gcc 8 warnings, that treated
> as errors, broke the build, related to snprintf and casting issues.
> (Arnaldo Carvalho de Melo, Jiri Olsa, Josh Poinboeuf)
>
> - Fix build of new breakpoint 'perf test' entry with clang < 6, noticed
> on fedora 25, 26 and 27 (Arnaldo Carvalho de Melo)
>
> - Workaround problem with symbol resolution in 'perf annotate', using
> the symbol name already present in the objdump output (Arnaldo Carvalho de Melo)
>
> - Document 'perf top --ignore-vmlinux' (Arnaldo Carvalho de Melo)
>
> - Fix out of bounds access on array fd when cnt is 100 in one of the
> 'perf test' entries, detected using 'cpptest' (Colin Ian King)
>
> - Add support for the forced leader feature, i.e. 'perf report --group'
> for a group of events not really grouped when scheduled (without using
> {} to enclose the list of events in the command line) in pipe mode,
> e.g.:
>
> $ perf record -e cycles,instructions -o - kill | perf report --group -i -
>
> - Use right type to access array elements in 'perf probe' (Masami Hiramatsu)
>
> - Update POWER9 vendor events (those described in JSON format) (Sukadev Bhattiprolu)
>
> - Discard head in overwrite_rb_find_range() (Yisheng Xie)
>
> - Avoid setting 'quiet' to 'true' unnecessarily (Yisheng Xie)
>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (4):
> perf annotate: Use asprintf when formatting objdump command line
> perf top: Document --ignore-vmlinux
> perf annotate: Use ops->target.name when available for unresolved call targets
> perf tests bp_account: Fix build with clang-6
>
> Colin Ian King (1):
> perf tests: Fix out of bounds access on array fd when cnt is 100
>
> Jiri Olsa (4):
> perf record: Synthesize features before events in pipe mode
> perf report: Support forced leader feature in pipe mode
> perf tools: Fix snprint warnings for gcc 8
> perf tools: Fix python extension build for gcc 8
>
> Josh Poimboeuf (1):
> objtool, perf: Fix GCC 8 -Wrestrict error
>
> Masami Hiramatsu (1):
> perf probe: Use right type to access array elements
>
> Sukadev Bhattiprolu (1):
> perf vendor events: Update POWER9 events
>
> Yisheng Xie (2):
> perf mmap: Discard head in overwrite_rb_find_range()
> perf debug: Avoid setting 'quiet' to 'true' unnecessarily
>
> tools/lib/str_error_r.c | 2 +-
> tools/perf/Documentation/perf-top.txt | 3 +
> tools/perf/builtin-record.c | 18 +-
> tools/perf/builtin-report.c | 57 +++--
> tools/perf/builtin-script.c | 22 +-
> .../perf/pmu-events/arch/powerpc/power9/cache.json | 25 ---
> .../pmu-events/arch/powerpc/power9/frontend.json | 10 -
> .../pmu-events/arch/powerpc/power9/marked.json | 5 -
> .../pmu-events/arch/powerpc/power9/memory.json | 5 -
> .../perf/pmu-events/arch/powerpc/power9/other.json | 241 ++++++++++++++-------
> .../pmu-events/arch/powerpc/power9/pipeline.json | 50 ++---
> tools/perf/pmu-events/arch/powerpc/power9/pmc.json | 5 -
> .../arch/powerpc/power9/translation.json | 10 +-
> tools/perf/tests/attr.c | 4 +-
> tools/perf/tests/bp_account.c | 10 +-
> tools/perf/tests/mem.c | 2 +-
> tools/perf/tests/pmu.c | 2 +-
> tools/perf/util/annotate.c | 20 +-
> tools/perf/util/cgroup.c | 2 +-
> tools/perf/util/debug.c | 1 -
> tools/perf/util/header.c | 11 +-
> tools/perf/util/mmap.c | 15 +-
> tools/perf/util/parse-events.c | 4 +-
> tools/perf/util/pmu.c | 2 +-
> tools/perf/util/probe-finder.c | 13 +-
> tools/perf/util/setup.py | 2 +
> 26 files changed, 298 insertions(+), 243 deletions(-)
Pulled, thanks a lot Arnaldo!
Ingo
^ permalink raw reply
* Re: [PATCH 1/1] PCI set flag PCI_SCAN_ALL_PCIE_DEVS for P.A. Semi boards
From: Bjorn Helgaas @ 2018-03-19 19:13 UTC (permalink / raw)
To: Christian Zigotzky; +Cc: Bjorn Helgaas, linux-pci, linuxppc-dev, Olof Johansson
In-Reply-To: <639e975f-1b3a-4f85-9a40-13fe2473fc28@xenosoft.de>
On Fri, Mar 16, 2018 at 01:55:36PM +0100, Christian Zigotzky wrote:
> Bjorn Helgaas created a patch for making PCI_SCAN_ALL_PCIE_DEVS work for
> Root Ports as well as Downstream. Previously PCI_SCAN_ALL_PCIE_DEVS (set by
> quirks or the "pci=pcie_scan_all"
> kernel parameter) only affected Switch Downstream Ports, not Root Ports. The
> problem is, that we have to add always the boot argument "pci=pcie_scan_all"
> for using Bjorn's improvements. Without the boot argument
> "pci=pcie_scan_all", the kernel doesn't boot on P.A. Semi boards with SB600
> chipset (SB600 chipset is connected via PCIe x4 to the P.A. Semi’s
> PA6T-1682M System-on-a-Chip) because the kernel can't find any drives
> connected to the SB600 anymore. Olof Johansson has created a patch for
> executing "pci=pcie_scan_all" automatically on P.A. Semi boards. With his
> patch, we don't need to add 'pci=pcie_scan_all' to the kernel boot arguments
> anymore.
The patch looks fine, but I need a signed-off-by line before I can apply
it. See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst
> ---
>
> arch/powerpc/platforms/pasemi/pci.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/platforms/pasemi/pci.c
> b/arch/powerpc/platforms/pasemi/pci.c
> index 5ff6108..ea54ed2 100644
> --- a/arch/powerpc/platforms/pasemi/pci.c
> +++ b/arch/powerpc/platforms/pasemi/pci.c
> @@ -224,6 +224,8 @@ void __init pas_pci_init(void)
> return;
> }
>
> + pci_set_flags(PCI_SCAN_ALL_PCIE_DEVS);
> +
> for (np = NULL; (np = of_get_next_child(root, np)) != NULL;)
> if (np->name && !strcmp(np->name, "pxp") && !pas_add_bridge(np))
> of_node_get(np);
>
> --
>
>
^ permalink raw reply
* [PATCH 05/14] perf vendor events: Update POWER9 events
From: Arnaldo Carvalho de Melo @ 2018-03-19 19:01 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Sukadev Bhattiprolu, linuxppc-dev,
Arnaldo Carvalho de Melo
In-Reply-To: <20180319190136.7441-1-acme@kernel.org>
From: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: https://lkml.kernel.org/r/20180313224647.GA22960@us.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../perf/pmu-events/arch/powerpc/power9/cache.json | 25 ---
.../pmu-events/arch/powerpc/power9/frontend.json | 10 -
.../pmu-events/arch/powerpc/power9/marked.json | 5 -
.../pmu-events/arch/powerpc/power9/memory.json | 5 -
.../perf/pmu-events/arch/powerpc/power9/other.json | 241 ++++++++++++++-------
.../pmu-events/arch/powerpc/power9/pipeline.json | 50 ++---
tools/perf/pmu-events/arch/powerpc/power9/pmc.json | 5 -
.../arch/powerpc/power9/translation.json | 10 +-
8 files changed, 178 insertions(+), 173 deletions(-)
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/cache.json b/tools/perf/pmu-events/arch/powerpc/power9/cache.json
index 7945c5196c43..851072105054 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/cache.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/cache.json
@@ -19,11 +19,6 @@
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
- {,
- "EventCode": "0x1D15C",
- "EventName": "PM_MRK_DTLB_MISS_1G",
- "BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
- },
{,
"EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
@@ -79,21 +74,6 @@
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096"
},
- {,
- "EventCode": "0x3D156",
- "EventName": "PM_MRK_DTLB_MISS_64K",
- "BriefDescription": "Marked Data TLB Miss page size 64K"
- },
- {,
- "EventCode": "0x4C15E",
- "EventName": "PM_MRK_DTLB_MISS_16M",
- "BriefDescription": "Marked Data TLB Miss page size 16M"
- },
- {,
- "EventCode": "0x2D15E",
- "EventName": "PM_MRK_DTLB_MISS_16G",
- "BriefDescription": "Marked Data TLB Miss page size 16G"
- },
{,
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
@@ -123,10 +103,5 @@
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
- },
- {,
- "EventCode": "0x1C058",
- "EventName": "PM_DTLB_MISS_16G",
- "BriefDescription": "Data TLB Miss page size 16G"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json
index bd8361b5fd6a..f9fa84b16fb5 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json
@@ -154,11 +154,6 @@
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
- {,
- "EventCode": "0x3C056",
- "EventName": "PM_DTLB_MISS_64K",
- "BriefDescription": "Data TLB Miss page size 64K"
- },
{,
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
@@ -344,11 +339,6 @@
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished"
},
- {,
- "EventCode": "0x4C056",
- "EventName": "PM_DTLB_MISS_16M",
- "BriefDescription": "Data TLB Miss page size 16M"
- },
{,
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/marked.json b/tools/perf/pmu-events/arch/powerpc/power9/marked.json
index 22f9f32060a8..b1954c38bab1 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/marked.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/marked.json
@@ -529,11 +529,6 @@
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch"
},
- {,
- "EventCode": "0x4003C",
- "EventName": "PM_DISP_HELD_SYNC_HOLD",
- "BriefDescription": "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline"
- },
{,
"EventCode": "0x3003C",
"EventName": "PM_CMPLU_STALL_NESTED_TEND",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/memory.json b/tools/perf/pmu-events/arch/powerpc/power9/memory.json
index 9960d1c0dd44..2e2ebc700c74 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/memory.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/memory.json
@@ -44,11 +44,6 @@
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed"
},
- {,
- "EventCode": "0x2D156",
- "EventName": "PM_MRK_DTLB_MISS_4K",
- "BriefDescription": "Marked Data TLB Miss page size 4k"
- },
{,
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json
index 5ce312973f1e..48cf4f920b3f 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/other.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json
@@ -69,6 +69,11 @@
"EventName": "PM_THRD_PRIO_0_1_CYC",
"BriefDescription": "Cycles thread running at priority level 0 or 1"
},
+ {,
+ "EventCode": "0x4C054",
+ "EventName": "PM_DERAT_MISS_16G_1G",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) or 1G (radix mode)"
+ },
{,
"EventCode": "0x2084",
"EventName": "PM_FLUSH_HB_RESTORE_CYC",
@@ -107,12 +112,12 @@
{,
"EventCode": "0x360B2",
"EventName": "PM_L3_GRP_GUESS_WRONG_LOW",
- "BriefDescription": "Initial scope=group (GS or NNS) but data from outside group (far or rem). Prediction too Low"
+ "BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was LNS"
},
{,
"EventCode": "0x168A6",
"EventName": "PM_TM_CAM_OVERFLOW",
- "BriefDescription": "L3 TM cam overflow during L2 co of SC"
+ "BriefDescription": "L3 TM CAM is full when a L2 castout of TM_SC line occurs. Line is pushed to memory"
},
{,
"EventCode": "0xE8B0",
@@ -149,11 +154,6 @@
"EventName": "PM_ISU3_ISS_HOLD_ALL",
"BriefDescription": "All ISU rejects"
},
- {,
- "EventCode": "0x460A6",
- "EventName": "PM_RD_FORMING_SC",
- "BriefDescription": "Read forming SC"
- },
{,
"EventCode": "0x468A0",
"EventName": "PM_L3_PF_OFF_CHIP_MEM",
@@ -187,7 +187,7 @@
{,
"EventCode": "0x368A6",
"EventName": "PM_SNP_TM_HIT_T",
- "BriefDescription": "Snp TM sthit T/Tn/Te"
+ "BriefDescription": "TM snoop that is a store hits line in L3 in T, Tn or Te state (shared modified)"
},
{,
"EventCode": "0x3001A",
@@ -204,6 +204,11 @@
"EventName": "PM_MRK_DATA_FROM_L31_ECO_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load"
},
+ {,
+ "EventCode": "0xF0B4",
+ "EventName": "PM_DC_PREF_CONS_ALLOC",
+ "BriefDescription": "Prefetch stream allocated in the conservative phase by either the hardware prefetch mechanism or software prefetch. The sum of this pair subtracted from the total number of allocs will give the total allocs in normal phase"
+ },
{,
"EventCode": "0xF894",
"EventName": "PM_LSU3_L1_CAM_CANCEL",
@@ -227,7 +232,12 @@
{,
"EventCode": "0x468A6",
"EventName": "PM_RD_CLEARING_SC",
- "BriefDescription": "Read clearing SC"
+ "BriefDescription": "Core TM load hits line in L3 in TM_SC state and causes it to be invalidated"
+ },
+ {,
+ "EventCode": "0xD0B0",
+ "EventName": "PM_HWSYNC",
+ "BriefDescription": ""
},
{,
"EventCode": "0x168B0",
@@ -264,6 +274,11 @@
"EventName": "PM_DC_PREF_HW_ALLOC",
"BriefDescription": "Prefetch stream allocated by the hardware prefetch mechanism"
},
+ {,
+ "EventCode": "0xF0BC",
+ "EventName": "PM_LS2_UNALIGNED_ST",
+ "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0xD0AC",
"EventName": "PM_SRQ_SYNC_CYC",
@@ -274,6 +289,11 @@
"EventName": "PM_MRK_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
},
+ {,
+ "EventCode": "0x58A8",
+ "EventName": "PM_DECODE_HOLD_ICT_FULL",
+ "BriefDescription": "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread"
+ },
{,
"EventCode": "0x26082",
"EventName": "PM_L2_IC_INV",
@@ -364,6 +384,16 @@
"EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load"
},
+ {,
+ "EventCode": "0xF888",
+ "EventName": "PM_LSU1_STORE_REJECT",
+ "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met"
+ },
+ {,
+ "EventCode": "0xC098",
+ "EventName": "PM_LS2_UNALIGNED_LD",
+ "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0x20058",
"EventName": "PM_DARQ1_10_12_ENTRIES",
@@ -372,7 +402,7 @@
{,
"EventCode": "0x360A6",
"EventName": "PM_SNP_TM_HIT_M",
- "BriefDescription": "Snp TM st hit M/Mu"
+ "BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified)"
},
{,
"EventCode": "0x5898",
@@ -395,9 +425,9 @@
"BriefDescription": "A data line was written to the L1 due to a hardware or software prefetch"
},
{,
- "EventCode": "0xF888",
- "EventName": "PM_LSU1_STORE_REJECT",
- "BriefDescription": "All internal store rejects cause the instruction to go back to the SRQ and go to sleep until woken up to try again after the condition has been met"
+ "EventCode": "0x2608E",
+ "EventName": "PM_TM_LD_CONF",
+ "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
},
{,
"EventCode": "0x1D144",
@@ -422,7 +452,7 @@
{,
"EventCode": "0x26884",
"EventName": "PM_DSIDE_MRU_TOUCH",
- "BriefDescription": "D-side L2 MRU touch sent to L2"
+ "BriefDescription": "D-side L2 MRU touch commands sent to the L2"
},
{,
"EventCode": "0x30134",
@@ -439,6 +469,16 @@
"EventName": "PM_EAT_FORCE_MISPRED",
"BriefDescription": "XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is issued"
},
+ {,
+ "EventCode": "0xC094",
+ "EventName": "PM_LS0_UNALIGNED_LD",
+ "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
+ {,
+ "EventCode": "0xF8BC",
+ "EventName": "PM_LS3_UNALIGNED_ST",
+ "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0x460AE",
"EventName": "PM_L3_P2_CO_RTY",
@@ -492,7 +532,7 @@
{,
"EventCode": "0xC880",
"EventName": "PM_LS1_LD_VECTOR_FIN",
- "BriefDescription": ""
+ "BriefDescription": "LS1 finished load vector op"
},
{,
"EventCode": "0x2894",
@@ -514,6 +554,11 @@
"EventName": "PM_MRK_LSU_DERAT_MISS",
"BriefDescription": "Marked derat reload (miss) for any page size"
},
+ {,
+ "EventCode": "0x160A0",
+ "EventName": "PM_L3_PF_MISS_L3",
+ "BriefDescription": "L3 PF missed in L3"
+ },
{,
"EventCode": "0x1C04A",
"EventName": "PM_DATA_FROM_RL2L3_SHR",
@@ -564,11 +609,21 @@
"EventName": "PM_L2_LOC_GUESS_WRONG",
"BriefDescription": "L2 guess local (LNS) and guess was not correct (ie data not on chip)"
},
+ {,
+ "EventCode": "0xC888",
+ "EventName": "PM_LSU_DTLB_MISS_64K",
+ "BriefDescription": "Data TLB Miss page size 64K"
+ },
{,
"EventCode": "0xE0A4",
"EventName": "PM_TMA_REQ_L2",
"BriefDescription": "addrs only req to L2 only on the first one,Indication that Load footprint is not expanding"
},
+ {,
+ "EventCode": "0xC088",
+ "EventName": "PM_LSU_DTLB_MISS_4K",
+ "BriefDescription": "Data TLB Miss page size 4K"
+ },
{,
"EventCode": "0x3C042",
"EventName": "PM_DATA_FROM_L3_DISP_CONFLICT",
@@ -602,7 +657,7 @@
{,
"EventCode": "0x26084",
"EventName": "PM_L2_RCLD_DISP_FAIL_OTHER",
- "BriefDescription": "All I-or-D side load dispatch attempts for this thread that failed due to reason other than address collision (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflicts with an L2 machines (e.g. Read-Claim/Snoop machine not available)"
},
{,
"EventCode": "0x101E4",
@@ -647,12 +702,12 @@
{,
"EventCode": "0x46080",
"EventName": "PM_L2_DISP_ALL_L2MISS",
- "BriefDescription": "All successful Ld/St dispatches for this thread that were an L2 miss (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this thread that were an L2 miss"
},
{,
- "EventCode": "0x160A0",
- "EventName": "PM_L3_PF_MISS_L3",
- "BriefDescription": "L3 PF missed in L3"
+ "EventCode": "0xF8B8",
+ "EventName": "PM_LS1_UNALIGNED_ST",
+ "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
},
{,
"EventCode": "0x408C",
@@ -667,7 +722,7 @@
{,
"EventCode": "0x160B2",
"EventName": "PM_L3_LOC_GUESS_CORRECT",
- "BriefDescription": "initial scope=node/chip (LNS) and data from local node (local) (pred successful) - always PFs only"
+ "BriefDescription": "Prefetch scope predictor selected LNS and was correct"
},
{,
"EventCode": "0x48B4",
@@ -767,7 +822,7 @@
{,
"EventCode": "0x36082",
"EventName": "PM_L2_LD_DISP",
- "BriefDescription": "All successful I-or-D side load dispatches for this thread (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread"
},
{,
"EventCode": "0xF8B0",
@@ -787,7 +842,7 @@
{,
"EventCode": "0x16884",
"EventName": "PM_L2_RCLD_DISP_FAIL_ADDR",
- "BriefDescription": "All I-od-D side load dispatch attempts for this thread that failed due to address collision with RC/CO/SN/SQ machine (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflicts with an L2 machines already working on this line (e.g. ld-hit-stq or Read-claim/Castout/Snoop machines)"
},
{,
"EventCode": "0x460A0",
@@ -829,6 +884,11 @@
"EventName": "PM_IC_PREF_REQ",
"BriefDescription": "Instruction prefetch requests"
},
+ {,
+ "EventCode": "0xC898",
+ "EventName": "PM_LS3_UNALIGNED_LD",
+ "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0x488C",
"EventName": "PM_IC_PREF_WRITE",
@@ -837,7 +897,7 @@
{,
"EventCode": "0xF89C",
"EventName": "PM_XLATE_MISS",
- "BriefDescription": "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions"
+ "BriefDescription": "The LSU requested a line from L2 for translation. It may be satisfied from any source beyond L2. Includes speculative instructions. Includes instruction, prefetch and demand"
},
{,
"EventCode": "0x14158",
@@ -849,10 +909,15 @@
"EventName": "PM_MRK_DATA_FROM_L31_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load"
},
+ {,
+ "EventCode": "0xC88C",
+ "EventName": "PM_LSU_DTLB_MISS_16G_1G",
+ "BriefDescription": "Data TLB Miss page size 16G (HPT) or 1G (Radix)"
+ },
{,
"EventCode": "0x268A6",
"EventName": "PM_TM_RST_SC",
- "BriefDescription": "TM-snp rst RM SC"
+ "BriefDescription": "TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated"
},
{,
"EventCode": "0x468A4",
@@ -917,7 +982,7 @@
{,
"EventCode": "0x46086",
"EventName": "PM_L2_SN_M_RD_DONE",
- "BriefDescription": "SNP dispatched for a read and was M (true M)"
+ "BriefDescription": "Snoop dispatched for a read and was M (true M)"
},
{,
"EventCode": "0x40154",
@@ -979,15 +1044,10 @@
"EventName": "PM_LINK_STACK_CORRECT",
"BriefDescription": "Link stack predicts right address"
},
- {,
- "EventCode": "0x4C05A",
- "EventName": "PM_DTLB_MISS_1G",
- "BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used"
- },
{,
"EventCode": "0x36886",
"EventName": "PM_L2_SN_SX_I_DONE",
- "BriefDescription": "SNP dispatched and went from Sx to Ix"
+ "BriefDescription": "Snoop dispatched and went from Sx to Ix"
},
{,
"EventCode": "0x4E04A",
@@ -999,11 +1059,6 @@
"EventName": "PM_MRK_DATA_FROM_DL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load"
},
- {,
- "EventCode": "0x2608E",
- "EventName": "PM_TM_LD_CONF",
- "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
- },
{,
"EventCode": "0x4080",
"EventName": "PM_INST_FROM_L1",
@@ -1037,7 +1092,7 @@
{,
"EventCode": "0x260A6",
"EventName": "PM_NON_TM_RST_SC",
- "BriefDescription": "Non-TM snp rst TM SC"
+ "BriefDescription": "Non-TM snoop hits line in L3 that is TM_SC state and causes it to be invalidated"
},
{,
"EventCode": "0x3608A",
@@ -1064,11 +1119,6 @@
"EventName": "PM_FLUSH_MPRED",
"BriefDescription": "Branch mispredict flushes. Includes target and address misprecition"
},
- {,
- "EventCode": "0x508C",
- "EventName": "PM_SHL_CREATED",
- "BriefDescription": "Store-Hit-Load Table Entry Created"
- },
{,
"EventCode": "0x1504C",
"EventName": "PM_IPTEG_FROM_LL4",
@@ -1107,7 +1157,7 @@
{,
"EventCode": "0x2608A",
"EventName": "PM_ISIDE_DISP_FAIL_ADDR",
- "BriefDescription": "All I-side dispatch attempts for this thread that failed due to a addr collision with another machine (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed due to an address collision conflict with an L2 machine already working on this line (e.g. ld-hit-stq or RC/CO/SN machines)"
},
{,
"EventCode": "0x50B4",
@@ -1180,9 +1230,9 @@
"BriefDescription": "Number of stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed"
},
{,
- "EventCode": "0xE0B8",
- "EventName": "PM_LS2_TM_DISALLOW",
- "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it"
+ "EventCode": "0xD8AC",
+ "EventName": "PM_LWSYNC",
+ "BriefDescription": ""
},
{,
"EventCode": "0x2094",
@@ -1209,6 +1259,11 @@
"EventName": "PM_ICT_NOSLOT_DISP_HELD_HB_FULL",
"BriefDescription": "Ict empty for this thread due to dispatch holds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
},
+ {,
+ "EventCode": "0xC894",
+ "EventName": "PM_LS1_UNALIGNED_LD",
+ "BriefDescription": "Load instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the load of that size. If the load wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0x360A2",
"EventName": "PM_L3_L2_CO_HIT",
@@ -1292,7 +1347,7 @@
{,
"EventCode": "0xC084",
"EventName": "PM_LS2_LD_VECTOR_FIN",
- "BriefDescription": ""
+ "BriefDescription": "LS2 finished load vector op"
},
{,
"EventCode": "0x1608E",
@@ -1344,6 +1399,11 @@
"EventName": "PM_SN_USAGE",
"BriefDescription": "Continuous 16 cycle (2to1) window where this signals rotates thru sampling each SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running"
},
+ {,
+ "EventCode": "0x36084",
+ "EventName": "PM_L2_RCST_DISP",
+ "BriefDescription": "All D-side store dispatch attempts for this thread"
+ },
{,
"EventCode": "0x46084",
"EventName": "PM_L2_RCST_DISP_FAIL_OTHER",
@@ -1354,11 +1414,6 @@
"EventName": "PM_DC_PREF_STRIDED_CONF",
"BriefDescription": "A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software."
},
- {,
- "EventCode": "0x36084",
- "EventName": "PM_L2_RCST_DISP",
- "BriefDescription": "All D-side store dispatch attempts for this thread"
- },
{,
"EventCode": "0x45054",
"EventName": "PM_FMA_CMPL",
@@ -1372,7 +1427,7 @@
{,
"EventCode": "0x36080",
"EventName": "PM_L2_INST",
- "BriefDescription": "All successful I-side dispatches for this thread (excludes i_l2mru_tch reqs)"
+ "BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread"
},
{,
"EventCode": "0x3504C",
@@ -1387,7 +1442,7 @@
{,
"EventCode": "0x1688A",
"EventName": "PM_ISIDE_DISP",
- "BriefDescription": "All I-side dispatch attempts for this thread (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread"
},
{,
"EventCode": "0x468AA",
@@ -1419,6 +1474,11 @@
"EventName": "PM_LSU2_TM_L1_HIT",
"BriefDescription": "Load tm hit in L1"
},
+ {,
+ "EventCode": "0xE0B8",
+ "EventName": "PM_LS2_TM_DISALLOW",
+ "BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU disallows it"
+ },
{,
"EventCode": "0x44044",
"EventName": "PM_INST_FROM_L31_ECO_MOD",
@@ -1467,7 +1527,7 @@
{,
"EventCode": "0x36086",
"EventName": "PM_L2_RC_ST_DONE",
- "BriefDescription": "RC did store to line that was Tx or Sx"
+ "BriefDescription": "Read-claim machine did store to line that was in Tx or Sx (Tagged or Shared state)"
},
{,
"EventCode": "0xE8AC",
@@ -1499,6 +1559,11 @@
"EventName": "PM_IPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request"
},
+ {,
+ "EventCode": "0x460A6",
+ "EventName": "PM_RD_FORMING_SC",
+ "BriefDescription": "Doesn't occur"
+ },
{,
"EventCode": "0x35042",
"EventName": "PM_IPTEG_FROM_L3_DISP_CONFLICT",
@@ -1527,7 +1592,7 @@
{,
"EventCode": "0x36882",
"EventName": "PM_L2_LD_HIT",
- "BriefDescription": "All successful I-or-D side load dispatches for this thread that were L2 hits (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thread that were L2 hits"
},
{,
"EventCode": "0x168AC",
@@ -1554,11 +1619,6 @@
"EventName": "PM_PROBE_NOP_DISP",
"BriefDescription": "ProbeNops dispatched"
},
- {,
- "EventCode": "0x58A8",
- "EventName": "PM_DECODE_HOLD_ICT_FULL",
- "BriefDescription": "Counts the number of cycles in which the IFU was not able to decode and transmit one or more instructions because all itags were in use. This means the ICT is full for this thread"
- },
{,
"EventCode": "0x10052",
"EventName": "PM_GRP_PUMP_MPRED_RTY",
@@ -1572,7 +1632,7 @@
{,
"EventCode": "0x2688A",
"EventName": "PM_ISIDE_DISP_FAIL_OTHER",
- "BriefDescription": "All I-side dispatch attempts for this thread that failed due to a reason other than addrs collision (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed due to reasons other than an address collision conflict with an L2 machine (e.g. no available RC/CO machines)"
},
{,
"EventCode": "0x2001A",
@@ -1652,12 +1712,12 @@
{,
"EventCode": "0x46880",
"EventName": "PM_ISIDE_MRU_TOUCH",
- "BriefDescription": "I-side L2 MRU touch sent to L2 for this thread"
+ "BriefDescription": "I-side L2 MRU touch sent to L2 for this thread I-side L2 MRU touch commands sent to the L2 for this thread"
},
{,
- "EventCode": "0x1C05C",
- "EventName": "PM_DTLB_MISS_2M",
- "BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
+ "EventCode": "0x508C",
+ "EventName": "PM_SHL_CREATED",
+ "BriefDescription": "Store-Hit-Load Table Entry Created"
},
{,
"EventCode": "0x50B8",
@@ -1672,7 +1732,7 @@
{,
"EventCode": "0x268B2",
"EventName": "PM_L3_LOC_GUESS_WRONG",
- "BriefDescription": "Initial scope=node (LNS) but data from out side local node (near or far or rem). Prediction too Low"
+ "BriefDescription": "Prefetch scope predictor selected LNS, but was wrong"
},
{,
"EventCode": "0x36088",
@@ -1684,6 +1744,11 @@
"EventName": "PM_L3_P2_PF_RTY",
"BriefDescription": "L3 PF received retry port 2, every retry counted"
},
+ {,
+ "EventCode": "0xD8B0",
+ "EventName": "PM_PTESYNC",
+ "BriefDescription": ""
+ },
{,
"EventCode": "0x26086",
"EventName": "PM_CO_TM_SC_FOOTPRINT",
@@ -1739,6 +1804,11 @@
"EventName": "PM_L2_ST_MISS",
"BriefDescription": "All successful D-Side Store dispatches that were an L2 miss for this thread"
},
+ {,
+ "EventCode": "0xF8B4",
+ "EventName": "PM_DC_PREF_XCONS_ALLOC",
+ "BriefDescription": "Prefetch stream allocated in the Ultra conservative phase by either the hardware prefetch mechanism or software prefetch"
+ },
{,
"EventCode": "0x35048",
"EventName": "PM_IPTEG_FROM_DL2L3_SHR",
@@ -1782,7 +1852,7 @@
{,
"EventCode": "0x460B2",
"EventName": "PM_L3_SYS_GUESS_WRONG",
- "BriefDescription": "Initial scope=system (VGS or RNS) but data from local or near. Prediction too high"
+ "BriefDescription": "Prefetch scope predictor selected VGS or RNS, but was wrong"
},
{,
"EventCode": "0x58B8",
@@ -1799,11 +1869,6 @@
"EventName": "PM_TM_TABORT_TRECLAIM",
"BriefDescription": "Completion time tabortnoncd, tabortcd, treclaim"
},
- {,
- "EventCode": "0x4C054",
- "EventName": "PM_DERAT_MISS_16G",
- "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G"
- },
{,
"EventCode": "0x268A0",
"EventName": "PM_L3_CO_L31",
@@ -1862,7 +1927,7 @@
{,
"EventCode": "0x368B2",
"EventName": "PM_L3_GRP_GUESS_WRONG_HIGH",
- "BriefDescription": "Initial scope=group (GS or NNS) but data from local node. Prediction too high"
+ "BriefDescription": "Prefetch scope predictor selected GS or NNS, but was wrong because scope was VGS or RNS"
},
{,
"EventCode": "0xE8BC",
@@ -1897,7 +1962,7 @@
{,
"EventCode": "0x260B2",
"EventName": "PM_L3_SYS_GUESS_CORRECT",
- "BriefDescription": "Initial scope=system (VGS or RNS) and data from outside group (far or rem)(pred successful)"
+ "BriefDescription": "Prefetch scope predictor selected VGS or RNS and was correct"
},
{,
"EventCode": "0x1D146",
@@ -1914,6 +1979,11 @@
"EventName": "PM_L2_GROUP_PUMP",
"BriefDescription": "RC requests that were on group (aka nodel) pump attempts"
},
+ {,
+ "EventCode": "0xC08C",
+ "EventName": "PM_LSU_DTLB_MISS_16M_2M",
+ "BriefDescription": "Data TLB Miss page size 16M (HPT) or 2M (Radix)"
+ },
{,
"EventCode": "0x16080",
"EventName": "PM_L2_LD",
@@ -1927,7 +1997,7 @@
{,
"EventCode": "0xC080",
"EventName": "PM_LS0_LD_VECTOR_FIN",
- "BriefDescription": ""
+ "BriefDescription": "LS0 finished load vector op"
},
{,
"EventCode": "0x368B0",
@@ -1999,6 +2069,11 @@
"EventName": "PM_BR_CORECT_PRED_TAKEN_CMPL",
"BriefDescription": "Conditional Branch Completed in which the HW correctly predicted the direction as taken. Counted at completion time"
},
+ {,
+ "EventCode": "0xF0B8",
+ "EventName": "PM_LS0_UNALIGNED_ST",
+ "BriefDescription": "Store instructions whose data crosses a double-word boundary, which causes it to require an additional slice than than what normally would be required of the Store of that size. If the Store wraps from slice 3 to slice 0, thee is an additional 3-cycle penalty"
+ },
{,
"EventCode": "0x20132",
"EventName": "PM_MRK_DFU_FIN",
@@ -2007,7 +2082,7 @@
{,
"EventCode": "0x160A6",
"EventName": "PM_TM_SC_CO",
- "BriefDescription": "L3 castout TM SC line"
+ "BriefDescription": "L3 castout of line that was StoreCopy (original value of speculatively written line) in a Transaction"
},
{,
"EventCode": "0xC8B0",
@@ -2017,7 +2092,7 @@
{,
"EventCode": "0x16084",
"EventName": "PM_L2_RCLD_DISP",
- "BriefDescription": "All I-or-D side load dispatch attempts for this thread (excludes i_l2mru_tch_reqs)"
+ "BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread"
},
{,
"EventCode": "0x3F150",
@@ -2122,12 +2197,12 @@
{,
"EventCode": "0x46082",
"EventName": "PM_L2_ST_DISP",
- "BriefDescription": "All successful D-side store dispatches for this thread (L2 miss + L2 hits)"
+ "BriefDescription": "All successful D-side store dispatches for this thread"
},
{,
"EventCode": "0x36880",
"EventName": "PM_L2_INST_MISS",
- "BriefDescription": "All successful I-side dispatches that were an L2 miss for this thread (excludes i_l2mru_tch reqs)"
+ "BriefDescription": "All successful I-side-instruction-fetch (e.g. i-demand, i-prefetch) dispatches for this thread that were an L2 miss"
},
{,
"EventCode": "0xE084",
@@ -2217,7 +2292,7 @@
{,
"EventCode": "0xC884",
"EventName": "PM_LS3_LD_VECTOR_FIN",
- "BriefDescription": ""
+ "BriefDescription": "LS3 finished load vector op"
},
{,
"EventCode": "0x360A8",
@@ -2242,7 +2317,7 @@
{,
"EventCode": "0x168B2",
"EventName": "PM_L3_GRP_GUESS_CORRECT",
- "BriefDescription": "Initial scope=group (GS or NNS) and data from same group (near) (pred successful)"
+ "BriefDescription": "Prefetch scope predictor selected GS or NNS and was correct"
},
{,
"EventCode": "0x48A4",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
index 5af1abbe82c4..b4772f54a271 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
@@ -64,11 +64,6 @@
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held"
},
- {,
- "EventCode": "0x3D154",
- "EventName": "PM_MRK_DERAT_MISS_16M",
- "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M"
- },
{,
"EventCode": "0x200F8",
"EventName": "PM_EXT_INT",
@@ -119,6 +114,11 @@
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
+ {,
+ "EventCode": "0x4C15C",
+ "EventName": "PM_MRK_DERAT_MISS_16G_1G",
+ "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radix mode)"
+ },
{,
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
@@ -154,11 +154,6 @@
"EventName": "PM_ICT_NOSLOT_IC_MISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss"
},
- {,
- "EventCode": "0x3D152",
- "EventName": "PM_MRK_DERAT_MISS_1G",
- "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation"
- },
{,
"EventCode": "0x4F14A",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
@@ -184,11 +179,6 @@
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
- {,
- "EventCode": "0x2C05A",
- "EventName": "PM_DERAT_MISS_1G",
- "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation"
- },
{,
"EventCode": "0x1F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L2",
@@ -239,11 +229,6 @@
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload"
},
- {,
- "EventCode": "0x2D152",
- "EventName": "PM_MRK_DERAT_MISS_2M",
- "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation"
- },
{,
"EventCode": "0x2C046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
@@ -289,6 +274,11 @@
"EventName": "PM_CMPLU_STALL_DFU",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle"
},
+ {,
+ "EventCode": "0x3C054",
+ "EventName": "PM_DERAT_MISS_16M_2M",
+ "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M (HPT mode) or 2M (Radix mode)"
+ },
{,
"EventCode": "0x4C04C",
"EventName": "PM_DATA_FROM_DMEM",
@@ -359,11 +349,6 @@
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)"
},
- {,
- "EventCode": "0x1C05A",
- "EventName": "PM_DERAT_MISS_2M",
- "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation"
- },
{,
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
@@ -374,6 +359,11 @@
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished"
},
+ {,
+ "EventCode": "0x3D154",
+ "EventName": "PM_MRK_DERAT_MISS_16M_2M",
+ "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M (hpt mode) or 2M (radix mode)"
+ },
{,
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
@@ -409,11 +399,6 @@
"EventName": "PM_MRK_DPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
- {,
- "EventCode": "0x4C15C",
- "EventName": "PM_MRK_DERAT_MISS_16G",
- "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G"
- },
{,
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
@@ -444,11 +429,6 @@
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Icache miss demand cycles"
},
- {,
- "EventCode": "0x3C054",
- "EventName": "PM_DERAT_MISS_16M",
- "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M"
- },
{,
"EventCode": "0x2D14E",
"EventName": "PM_MRK_DATA_FROM_L21_SHR",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pmc.json b/tools/perf/pmu-events/arch/powerpc/power9/pmc.json
index d0b89f930567..8b3b0f3be664 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/pmc.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/pmc.json
@@ -9,11 +9,6 @@
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium"
},
- {,
- "EventCode": "0x2C056",
- "EventName": "PM_DTLB_MISS_4K",
- "BriefDescription": "Data TLB Miss page size 4k"
- },
{,
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
diff --git a/tools/perf/pmu-events/arch/powerpc/power9/translation.json b/tools/perf/pmu-events/arch/powerpc/power9/translation.json
index bc8e03d7a6b0..b27642676244 100644
--- a/tools/perf/pmu-events/arch/powerpc/power9/translation.json
+++ b/tools/perf/pmu-events/arch/powerpc/power9/translation.json
@@ -29,11 +29,6 @@
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity"
},
- {,
- "EventCode": "0x44042",
- "EventName": "PM_INST_FROM_L3",
- "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
- },
{,
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
@@ -124,6 +119,11 @@
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved"
},
+ {,
+ "EventCode": "0x44042",
+ "EventName": "PM_INST_FROM_L3",
+ "BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
+ },
{,
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
--
2.14.3
^ permalink raw reply related
* [GIT PULL 00/14] perf/core improvements and fixes
From: Arnaldo Carvalho de Melo @ 2018-03-19 19:01 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Arnaldo Carvalho de Melo,
Adrian Hunter, Alexander Shishkin, Andi Kleen, Colin King,
David Ahern, Jin Yao, Jiri Olsa, Josh Poimboeuf, Kan Liang,
kernel-janitors, Laura Abbott, linux-kselftest, linuxppc-dev,
linux-trace-users, Masami Hiramatsu, Namhyung Kim, Peter Zijlstra,
Ravi Bangoria, Sergey Senozhatsky, Shuah Khan, Stephane Eranian,
Steven Rostedt, Sukadev Bhattiprolu, Tom Zanussi, Wang Nan,
Willy Tarreau, Yisheng Xie, Arnaldo Carvalho de Melo
Hi Ingo,
Please consider pulling, this has those 31 patches that were
blocked due to some problems (author not being the fist S-o-B, build
broken on ppc), those issues should all be fixed and then we have 14
patches more, described in the signed tag.
Regards,
- Arnaldo
Test results at the end of this message, as usual.
The following changes since commit 10f354a36f9a9aa1b8bffe0abc1cd43822a85bcd:
perf test: Fix exit code for record+probe_libc_inet_pton.sh (2018-03-16 13:56:31 -0300)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180319
for you to fetch changes up to 1cd618838b9703eabe4a75badf433382b12f6bef:
perf tests bp_account: Fix build with clang-6 (2018-03-19 13:51:54 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
- Fixes for problems experienced with new gcc 8 warnings, that treated
as errors, broke the build, related to snprintf and casting issues.
(Arnaldo Carvalho de Melo, Jiri Olsa, Josh Poinboeuf)
- Fix build of new breakpoint 'perf test' entry with clang < 6, noticed
on fedora 25, 26 and 27 (Arnaldo Carvalho de Melo)
- Workaround problem with symbol resolution in 'perf annotate', using
the symbol name already present in the objdump output (Arnaldo Carvalho de Melo)
- Document 'perf top --ignore-vmlinux' (Arnaldo Carvalho de Melo)
- Fix out of bounds access on array fd when cnt is 100 in one of the
'perf test' entries, detected using 'cpptest' (Colin Ian King)
- Add support for the forced leader feature, i.e. 'perf report --group'
for a group of events not really grouped when scheduled (without using
{} to enclose the list of events in the command line) in pipe mode,
e.g.:
$ perf record -e cycles,instructions -o - kill | perf report --group -i -
- Use right type to access array elements in 'perf probe' (Masami Hiramatsu)
- Update POWER9 vendor events (those described in JSON format) (Sukadev Bhattiprolu)
- Discard head in overwrite_rb_find_range() (Yisheng Xie)
- Avoid setting 'quiet' to 'true' unnecessarily (Yisheng Xie)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
----------------------------------------------------------------
Arnaldo Carvalho de Melo (4):
perf annotate: Use asprintf when formatting objdump command line
perf top: Document --ignore-vmlinux
perf annotate: Use ops->target.name when available for unresolved call targets
perf tests bp_account: Fix build with clang-6
Colin Ian King (1):
perf tests: Fix out of bounds access on array fd when cnt is 100
Jiri Olsa (4):
perf record: Synthesize features before events in pipe mode
perf report: Support forced leader feature in pipe mode
perf tools: Fix snprint warnings for gcc 8
perf tools: Fix python extension build for gcc 8
Josh Poimboeuf (1):
objtool, perf: Fix GCC 8 -Wrestrict error
Masami Hiramatsu (1):
perf probe: Use right type to access array elements
Sukadev Bhattiprolu (1):
perf vendor events: Update POWER9 events
Yisheng Xie (2):
perf mmap: Discard head in overwrite_rb_find_range()
perf debug: Avoid setting 'quiet' to 'true' unnecessarily
tools/lib/str_error_r.c | 2 +-
tools/perf/Documentation/perf-top.txt | 3 +
tools/perf/builtin-record.c | 18 +-
tools/perf/builtin-report.c | 57 +++--
tools/perf/builtin-script.c | 22 +-
.../perf/pmu-events/arch/powerpc/power9/cache.json | 25 ---
.../pmu-events/arch/powerpc/power9/frontend.json | 10 -
.../pmu-events/arch/powerpc/power9/marked.json | 5 -
.../pmu-events/arch/powerpc/power9/memory.json | 5 -
.../perf/pmu-events/arch/powerpc/power9/other.json | 241 ++++++++++++++-------
.../pmu-events/arch/powerpc/power9/pipeline.json | 50 ++---
tools/perf/pmu-events/arch/powerpc/power9/pmc.json | 5 -
.../arch/powerpc/power9/translation.json | 10 +-
tools/perf/tests/attr.c | 4 +-
tools/perf/tests/bp_account.c | 10 +-
tools/perf/tests/mem.c | 2 +-
tools/perf/tests/pmu.c | 2 +-
tools/perf/util/annotate.c | 20 +-
tools/perf/util/cgroup.c | 2 +-
tools/perf/util/debug.c | 1 -
tools/perf/util/header.c | 11 +-
tools/perf/util/mmap.c | 15 +-
tools/perf/util/parse-events.c | 4 +-
tools/perf/util/pmu.c | 2 +-
tools/perf/util/probe-finder.c | 13 +-
tools/perf/util/setup.py | 2 +
26 files changed, 298 insertions(+), 243 deletions(-)
Test results:
The first ones are container (docker) based builds of tools/perf with and
without libelf support. Where clang is available, it is also used to build
perf with/without libelf.
The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.
Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.
The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.
Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.
[root@jouet ~]# time dm
1 alpine:3.4 : Ok gcc (Alpine 5.3.0) 5.3.0
2 alpine:3.5 : Ok gcc (Alpine 6.2.1) 6.2.1 20160822
3 alpine:3.6 : Ok gcc (Alpine 6.3.0) 6.3.0
4 alpine:3.7 : Ok gcc (Alpine 6.4.0) 6.4.0
5 alpine:edge : Ok gcc (Alpine 6.4.0) 6.4.0
6 amazonlinux:1 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-11)
7 amazonlinux:2 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2)
8 android-ndk:r12b-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
9 android-ndk:r15c-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
10 centos:5 : Ok gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-55)
11 centos:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
12 centos:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16)
13 debian:7 : Ok gcc (Debian 4.7.2-5) 4.7.2
14 debian:8 : Ok gcc (Debian 4.9.2-10+deb8u1) 4.9.2
15 debian:9 : Ok gcc (Debian 6.3.0-18+deb9u1) 6.3.0 20170516
16 debian:experimental : Ok gcc (Debian 7.2.0-17) 7.2.1 20171205
17 debian:experimental-x-arm64 : Ok aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
18 debian:experimental-x-mips : Ok mips-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
19 debian:experimental-x-mips64 : Ok mips64-linux-gnuabi64-gcc (Debian 7.2.0-11) 7.2.0
20 debian:experimental-x-mipsel : Ok mipsel-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
21 fedora:20 : Ok gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7)
22 fedora:21 : Ok gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
23 fedora:22 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
24 fedora:23 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
25 fedora:24 : Ok gcc (GCC) 6.3.1 20161221 (Red Hat 6.3.1-1)
26 fedora:24-x-ARC-uClibc : Ok arc-linux-gcc (ARCompact ISA Linux uClibc toolchain 2017.09-rc2) 7.1.1 20170710
27 fedora:25 : Ok gcc (GCC) 6.4.1 20170727 (Red Hat 6.4.1-1)
28 fedora:26 : Ok gcc (GCC) 7.3.1 20180130 (Red Hat 7.3.1-2)
29 fedora:27 : Ok gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5)
30 fedora:rawhide : Ok gcc (GCC) 8.0.1 20180222 (Red Hat 8.0.1-0.16)
31 gentoo-stage3-amd64:latest : Ok gcc (Gentoo 6.4.0-r1 p1.3) 6.4.0
32 mageia:5 : Ok gcc (GCC) 4.9.2
33 mageia:6 : Ok gcc (Mageia 5.4.0-5.mga6) 5.4.0
34 opensuse:42.1 : Ok gcc (SUSE Linux) 4.8.5
35 opensuse:42.2 : Ok gcc (SUSE Linux) 4.8.5
36 opensuse:42.3 : Ok gcc (SUSE Linux) 4.8.5
37 opensuse:tumbleweed : Ok gcc (SUSE Linux) 7.3.0
38 oraclelinux:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
39 oraclelinux:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16.0.3)
40 ubuntu:12.04.5 : Ok gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
41 ubuntu:14.04.4 : Ok gcc (Ubuntu 4.8.4-2ubuntu1~14.04.3) 4.8.4
42 ubuntu:14.04.4-x-linaro-arm64 : Ok aarch64-linux-gnu-gcc (Linaro GCC 5.4-2017.05) 5.4.1 20170404
43 ubuntu:15.04 : Ok gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2
44 ubuntu:16.04 : Ok gcc (Ubuntu 5.4.0-6ubuntu1~16.04.5) 5.4.0 20160609
45 ubuntu:16.04-x-arm : Ok arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
46 ubuntu:16.04-x-arm64 : Ok aarch64-linux-gnu-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
47 ubuntu:16.04-x-powerpc : Ok powerpc-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
48 ubuntu:16.04-x-powerpc64 : Ok powerpc64-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.1) 5.4.0 20160609
49 ubuntu:16.04-x-powerpc64el : Ok powerpc64le-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
50 ubuntu:16.04-x-s390 : Ok s390x-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609
51 ubuntu:16.10 : Ok gcc (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005
52 ubuntu:17.04 : Ok gcc (Ubuntu 6.3.0-12ubuntu2) 6.3.0 20170406
53 ubuntu:17.10 : Ok gcc (Ubuntu 7.2.0-8ubuntu3) 7.2.0
54 ubuntu:18.04 : Ok gcc (Ubuntu 7.2.0-16ubuntu1) 7.2.0
# uname -a
Linux jouet 4.16.0-rc5-00086-gdf09348f78dc #1 SMP Fri Mar 16 09:46:40 -03 2018 x86_64 x86_64 x86_64 GNU/Linux
# perf test
1: vmlinux symtab matches kallsyms : Ok
2: Detect openat syscall event : Ok
3: Detect openat syscall event on all cpus : Ok
4: Read samples using the mmap interface : Ok
5: Test data source output : Ok
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
8: PERF_RECORD_* events & perf_sample fields : Ok
9: Parse perf pmu format : Ok
10: DSO data read : Ok
11: DSO data cache : Ok
12: DSO data reopen : Ok
13: Roundtrip evsel->name : Ok
14: Parse sched tracepoints fields : Ok
15: syscalls:sys_enter_openat event fields : Ok
16: Setup struct perf_event_attr : Ok
17: Match and link multiple hists : Ok
18: 'import perf' in python : Ok
19: Breakpoint overflow signal handler : Ok
20: Breakpoint overflow sampling : Ok
21: Breakpoint accounting : Skip
22: Number of exit events of a simple workload : Ok
23: Software clock events period values : Ok
24: Object code reading : Ok
25: Sample parsing : Ok
26: Use a dummy software event to keep tracking : Ok
27: Parse with no sample_id_all bit set : Ok
28: Filter hist entries : Ok
29: Lookup mmap thread : Ok
30: Share thread mg : Ok
31: Sort output of hist entries : Ok
32: Cumulate child hist entries : Ok
33: Track with sched_switch : Ok
34: Filter fds with revents mask in a fdarray : Ok
35: Add fd to a fdarray, making it autogrow : Ok
36: kmod_path__parse : Ok
37: Thread map : Ok
38: LLVM search and compile :
38.1: Basic BPF llvm compile : Ok
38.2: kbuild searching : Ok
38.3: Compile source for BPF prologue generation : Ok
38.4: Compile source for BPF relocation : Ok
39: Session topology : Ok
40: BPF filter :
40.1: Basic BPF filtering : Ok
40.2: BPF pinning : Ok
40.3: BPF prologue generation : Ok
40.4: BPF relocation checker : Ok
41: Synthesize thread map : Ok
42: Remove thread map : Ok
43: Synthesize cpu map : Ok
44: Synthesize stat config : Ok
45: Synthesize stat : Ok
46: Synthesize stat round : Ok
47: Synthesize attr update : Ok
48: Event times : Ok
49: Read backward ring buffer : Ok
50: Print cpu map : Ok
51: Probe SDT events : Ok
52: is_printable_array : Ok
53: Print bitmap : Ok
54: perf hooks : Ok
55: builtin clang support : Skip (not compiled in)
56: unit_number__scnprintf : Ok
57: mem2node : Ok
58: x86 rdpmc : Ok
59: Convert perf time to TSC : Ok
60: DWARF unwind : Ok
61: x86 instruction decoder - new instructions : Ok
62: Use vfs_getname probe to get syscall args filenames : Ok
63: Check open filename arg using perf trace + vfs_getname: Ok
64: probe libc's inet_pton & backtrace it with ping : Ok
65: Add vfs_getname probe to get syscall args filenames : Ok
#
$ make -C tools/perf build-test
make: Entering directory '/home/acme/git/perf/tools/perf'
- tarpkg: ./tests/perf-targz-src-pkg .
make_no_libbionic_O: make NO_LIBBIONIC=1
make_no_libelf_O: make NO_LIBELF=1
make_with_clangllvm_O: make LIBCLANGLLVM=1
make_install_prefix_slash_O: make install prefix=/tmp/krava/
make_no_libbpf_O: make NO_LIBBPF=1
make_no_backtrace_O: make NO_BACKTRACE=1
make_minimal_O: make NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1
make_no_slang_O: make NO_SLANG=1
make_no_libnuma_O: make NO_LIBNUMA=1
make_clean_all_O: make clean all
make_util_map_o_O: make util/map.o
make_no_demangle_O: make NO_DEMANGLE=1
make_no_auxtrace_O: make NO_AUXTRACE=1
make_pure_O: make
make_install_bin_O: make install-bin
make_install_O: make install
make_no_libdw_dwarf_unwind_O: make NO_LIBDW_DWARF_UNWIND=1
make_tags_O: make tags
make_install_prefix_O: make install prefix=/tmp/krava
make_no_ui_O: make NO_NEWT=1 NO_SLANG=1 NO_GTK2=1
make_no_libperl_O: make NO_LIBPERL=1
make_no_gtk2_O: make NO_GTK2=1
make_static_O: make LDFLAGS=-static
make_help_O: make help
make_no_newt_O: make NO_NEWT=1
make_debug_O: make DEBUG=1
make_no_libunwind_O: make NO_LIBUNWIND=1
make_with_babeltrace_O: make LIBBABELTRACE=1
make_no_libaudit_O: make NO_LIBAUDIT=1
make_perf_o_O: make perf.o
make_no_scripts_O: make NO_LIBPYTHON=1 NO_LIBPERL=1
make_util_pmu_bison_o_O: make util/pmu-bison.o
make_no_libpython_O: make NO_LIBPYTHON=1
make_doc_O: make doc
OK
make: Leaving directory '/home/acme/git/perf/tools/perf'
$
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox