* Re: How to handle PTE tables with non contiguous entries ?
From: Nicholas Piggin @ 2018-09-10 21:06 UTC (permalink / raw)
To: Christophe Leroy
Cc: akpm, linux-mm, aneesh.kumar, Michael Ellerman, linuxppc-dev,
LKML
In-Reply-To: <ddc3bb56-4da0-c093-256f-185d4a612b5c@c-s.fr>
On Mon, 10 Sep 2018 14:34:37 +0000
Christophe Leroy <christophe.leroy@c-s.fr> wrote:
> Hi,
>
> I'm having a hard time figuring out the best way to handle the following
> situation:
>
> On the powerpc8xx, handling 16k size pages requires to have page tables
> with 4 identical entries.
>
> Initially I was thinking about handling this by simply modifying
> pte_index() which changing pte_t type in order to have one entry every
> 16 bytes, then replicate the PTE value at *ptep, *ptep+1,*ptep+2 and
> *ptep+3 both in set_pte_at() and pte_update().
>
> However, this doesn't work because many many places in the mm core part
> of the kernel use loops on ptep with single ptep++ increment.
>
> Therefore did it with the following hack:
>
> /* PTE level */
> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
> +typedef struct { pte_basic_t pte, pte1, pte2, pte3; } pte_t;
> +#else
> typedef struct { pte_basic_t pte; } pte_t;
> +#endif
>
> @@ -181,7 +192,13 @@ static inline unsigned long pte_update(pte_t *p,
> : "cc" );
> #else /* PTE_ATOMIC_UPDATES */
> unsigned long old = pte_val(*p);
> - *p = __pte((old & ~clr) | set);
> + unsigned long new = (old & ~clr) | set;
> +
> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
> + p->pte = p->pte1 = p->pte2 = p->pte3 = new;
> +#else
> + *p = __pte(new);
> +#endif
> #endif /* !PTE_ATOMIC_UPDATES */
>
> #ifdef CONFIG_44x
>
>
> @@ -161,7 +161,11 @@ static inline void __set_pte_at(struct mm_struct
> *mm, unsigned long addr,
> /* Anything else just stores the PTE normally. That covers all
> 64-bit
> * cases, and 32-bit non-hash with 32-bit PTEs.
> */
> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
> + ptep->pte = ptep->pte1 = ptep->pte2 = ptep->pte3 = pte_val(pte);
> +#else
> *ptep = pte;
> +#endif
>
>
>
> But I'm not too happy with it as it means pte_t is not a single type
> anymore so passing it from one function to the other is quite heavy.
>
>
> Would someone have an idea of an elegent way to handle that ?
I can't think of anything better. Do we pass pte by value to a lot of
non inlined functions? Possible to inline the important ones?
Other option, try to get an iterator like pte = pte_next(pte) into core
code.
Thanks,
Nick
^ permalink raw reply
* Re: MPC83xx reset status register (RSR, offset 0x910)
From: Radu Rendec @ 2018-09-10 22:17 UTC (permalink / raw)
To: christophe.leroy; +Cc: linuxppc-dev, oss, mpe
In-Reply-To: <c0b2c45c-815c-d627-e975-a2d622494223@c-s.fr>
Hi,
On Mon, 2018-09-10 at 07:37 +0200, Christophe Leroy wrote:
> Le 10/09/2018 =C3=A0 01:13, Radu Rendec a =C3=A9crit :
> >
> > I'm using U-boot as well, but it's just not configured to read or clear
> > the RSR. I'm curious: if U-boot reads/clears the RSR in your case, how
> > do you make the initial value available to user space programs running
> > under Linux?
>
> I'm surprised. When looking at U-boot code, I don't see any way to
> configure that. It seems just do by default in function cpu_init_f():
>
> https://elixir.bootlin.com/u-boot/v2018.07/source/arch/powerpc/cpu/mpc83x=
x/cpu_init.c#L217
>
> /* RSR - Reset Status Register - clear all status (4.6.1.3) */
> gd->arch.reset_status =3D __raw_readl(&im->reset.rsr);
> __raw_writel(~(RSR_RES), &im->reset.rsr);
I'm working as a contractor in a large embedded project, so I don't know
all the bits and pieces. I just checked the U-boot code. Whoever was
maintaining it, "configured" it by commenting out the __raw_writel()
that clears the register :)
Probably the reason was specifically to be able to read it from Linux,
but unfortunately the guy is not here any more to ask him.
It may make more sense to read it from U-boot, but (1) the value must
still be passed to Linux somehow and (2) in my case, I would prefer not
to touch U-boot.
> Do you know any user space program in Linux that needs this value ?
I don't know of any "standard" program that needs it. In the project I'm
working on, there are multiple peripherals on the board and initialization
is slightly different when the reset line is physically asserted vs. a
soft CPU reset. Besides, we need to show the reset reason to the user.
I guess in the embedded world this is a fairly common use case, so
perhaps others can benefit from that if I fix it in a way that can be
pushed upstream.
> > Thank you very much for the patches. Is there any chance they can be
> > submitted upstream?
>
> I see no problem submitting them upstream, but are they really worth it
> ? Adding Michael in copy to get his opinion.
I guess it's worth if they are changed to make the value available to
the kernel and user space rather than just decoding/printing it, for the
reasons I mentioned above.
The MPC83xx also has a watchdog and the kernel driver (mpc8xxx_wdt.c)
could also be improved to support the WDIOC_GETBOOTSTATUS ioctl and
properly report if the system rebooted due to a watchdog.
> > I tried to look for something similar on other platforms or architectur=
es,
> > but couldn't find anything.
>
> I believe furst thing is to identify some app needing such an
> information, then we'll be able to investigate how to handle it.
Well, I guess I explained my reasons and use case. If there is any
interest in that, I will gladly implement it in a way that makes sense
to upstream. Let's see what Michael thinks.
Thanks,
Radu Rendec
^ permalink raw reply
* Re: [PATCH] powerpc: Avoid code patching freed init sections
From: Paul Mackerras @ 2018-09-10 22:38 UTC (permalink / raw)
To: Michael Neuling
Cc: Michal Suchánek, mpe, linuxppc-dev, Haren Myneni,
Nicholas Piggin
In-Reply-To: <794308ed6aa6dcccf96e10bb0e3fa8d2dab9adff.camel@neuling.org>
On Mon, Sep 10, 2018 at 08:05:38PM +1000, Michael Neuling wrote:
>
> > > + /* Make sure we aren't patching a freed init section */
> > > + if (in_init_section(patch_addr) && init_freed())
> > > + return 0;
> > > +
> >
> > Do we even need the init_freed() check?
>
> Maybe not. If userspace isn't up, then maybe it's ok to skip.
Isn't this same function used for patching asm feature sections? It's
not OK to skip patching them in init code.
> > What user input can we process in init-only code?
>
> See the stack trace in the commit message. It's a weird case for KVM guests in
> KVM PR mode.
The fault_in_pages_readable (formerly __get_user) there isn't actually
reading userspace, it's just a way of doing a load with a convenient
way to handle it if it traps.
Paul.
^ permalink raw reply
* [PATCH] powerpc/mpc85xx: fix issues in clock node
From: andy.tang @ 2018-09-11 2:12 UTC (permalink / raw)
To: oss; +Cc: robh+dt, mark.rutland, benh, devicetree, linuxppc-dev,
Yuantian Tang
From: Yuantian Tang <andy.tang@nxp.com>
The compatible string is not correct in the clock node.
The clocks property refers to the wrong node too.
This patch is to fix them.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 4908af5..763caf4 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -348,7 +348,7 @@
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 4>;
- compatible = "fsl,core-mux-clock";
+ compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>;
clock-names = "pll0_0", "pll0_1";
clock-output-names = "cmux0";
@@ -356,9 +356,9 @@
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
- compatible = "fsl,core-mux-clock";
- clocks = <&pll0 0>, <&pll0 1>;
- clock-names = "pll0_0", "pll0_1";
+ compatible = "fsl,qoriq-core-mux-2.0";
+ clocks = <&pll1 0>, <&pll1 1>;
+ clock-names = "pll1_0", "pll1_1";
clock-output-names = "cmux1";
};
};
--
1.7.1
^ permalink raw reply related
* [PATCH] powerpc/tm: Fix HFSCR bit for no suspend case
From: Michael Neuling @ 2018-09-11 3:07 UTC (permalink / raw)
To: mpe; +Cc: linuxppc-dev, Nicholas Piggin, paulus, mikey
Currently on P9N DD2.1 we end up taking infinite TM facility
unavailable exceptions on the first TM usage by userspace.
In the special case of TM no suspend (P9N DD2.1), Linux is told TM is
off via CPU dt-ftrs but told to (partially) use it via
OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM] will be off from
dt-ftrs but we need to turn it on for the no suspend case.
This patch fixes this by enabling HFSCR TM in this case.
Cc: stable@vger.kernel.org # 4.15+
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/kernel/setup_64.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 6a501b25dd..faf00222b3 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -243,13 +243,19 @@ static void cpu_ready_for_interrupts(void)
}
/*
- * Fixup HFSCR:TM based on CPU features. The bit is set by our
- * early asm init because at that point we haven't updated our
- * CPU features from firmware and device-tree. Here we have,
- * so let's do it.
+ * Set HFSCR:TM based on CPU features:
+ * In the special case of TM no suspend (P9N DD2.1), Linux is
+ * told TM is off via the dt-ftrs but told to (partially) use
+ * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
+ * will be off from dt-ftrs but we need to turn it on for the
+ * no suspend case.
*/
- if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
- mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
+ if (cpu_has_feature(CPU_FTR_HVMODE)) {
+ if (cpu_has_feature(CPU_FTR_TM_COMP))
+ mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
+ else
+ mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
+ }
/* Set IR and DR in PACA MSR */
get_paca()->kernel_msr = MSR_KERNEL;
--
2.17.1
^ permalink raw reply related
* Re: [PATCH kernel v2 1/6] KVM: PPC: Avoid marking DMA-mapped pages dirty in real mode
From: David Gibson @ 2018-09-11 3:13 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: linuxppc-dev, kvm-ppc, Aneesh Kumar K.V, Paul Mackerras,
Alex Williamson
In-Reply-To: <20180910082912.13255-2-aik@ozlabs.ru>
[-- Attachment #1: Type: text/plain, Size: 13681 bytes --]
On Mon, Sep 10, 2018 at 06:29:07PM +1000, Alexey Kardashevskiy wrote:
> At the moment the real mode handler of H_PUT_TCE calls iommu_tce_xchg_rm()
> which in turn reads the old TCE and if it was a valid entry - marks
> the physical page dirty if it was mapped for writing. Since it is
> the real mode, realmode_pfn_to_page() is used instead of pfn_to_page()
> to get the page struct. However SetPageDirty() itself reads the compound
> page head and returns a virtual address for the head page struct and
> setting dirty bit for that kills the system.
>
> This adds additional dirty bit tracking into the MM/IOMMU API for use
> in the real mode. Note that this does not change how VFIO and
> KVM (in virtual mode) set this bit. The KVM (real mode) changes include:
> - use the lowest bit of the cached host phys address to carry
> the dirty bit;
> - mark pages dirty when they are unpinned which happens when
> the preregistered memory is released which always happens in virtual
> mode;
> - add mm_iommu_ua_mark_dirty_rm() helper to set delayed dirty bit;
> - change iommu_tce_xchg_rm() to take the kvm struct for the mm to use
> in the new mm_iommu_ua_mark_dirty_rm() helper;
> - move iommu_tce_xchg_rm() to book3s_64_vio_hv.c (which is the only
> caller anyway) to reduce the real mode KVM and IOMMU knowledge
> across different subsystems.
>
> This removes realmode_pfn_to_page() as it is not used anymore.
>
> While we at it, remove some EXPORT_SYMBOL_GPL() as that code is for
> the real mode only and modules cannot call it anyway.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> Changes:
> v2:
> * only do delaying dirtying for the real mode
> * no change in VFIO IOMMU SPAPR TCE driver is needed anymore
> * inverted MM_IOMMU_TABLE_GROUP_PAGE_MASK
> ---
> arch/powerpc/include/asm/book3s/64/pgtable.h | 1 -
> arch/powerpc/include/asm/iommu.h | 2 --
> arch/powerpc/include/asm/mmu_context.h | 1 +
> arch/powerpc/kernel/iommu.c | 25 --------------
> arch/powerpc/kvm/book3s_64_vio_hv.c | 39 +++++++++++++++++-----
> arch/powerpc/mm/init_64.c | 49 ----------------------------
> arch/powerpc/mm/mmu_context_iommu.c | 34 ++++++++++++++++---
> 7 files changed, 62 insertions(+), 89 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
> index 13a688f..2fdc865 100644
> --- a/arch/powerpc/include/asm/book3s/64/pgtable.h
> +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
> @@ -1051,7 +1051,6 @@ static inline void vmemmap_remove_mapping(unsigned long start,
> return hash__vmemmap_remove_mapping(start, page_size);
> }
> #endif
> -struct page *realmode_pfn_to_page(unsigned long pfn);
>
> static inline pte_t pmd_pte(pmd_t pmd)
> {
> diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
> index ab3a4fb..3d4b88c 100644
> --- a/arch/powerpc/include/asm/iommu.h
> +++ b/arch/powerpc/include/asm/iommu.h
> @@ -220,8 +220,6 @@ extern void iommu_del_device(struct device *dev);
> extern int __init tce_iommu_bus_notifier_init(void);
> extern long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
> unsigned long *hpa, enum dma_data_direction *direction);
> -extern long iommu_tce_xchg_rm(struct iommu_table *tbl, unsigned long entry,
> - unsigned long *hpa, enum dma_data_direction *direction);
> #else
> static inline void iommu_register_group(struct iommu_table_group *table_group,
> int pci_domain_number,
> diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
> index b2f89b6..b694d6a 100644
> --- a/arch/powerpc/include/asm/mmu_context.h
> +++ b/arch/powerpc/include/asm/mmu_context.h
> @@ -38,6 +38,7 @@ extern long mm_iommu_ua_to_hpa(struct mm_iommu_table_group_mem_t *mem,
> unsigned long ua, unsigned int pageshift, unsigned long *hpa);
> extern long mm_iommu_ua_to_hpa_rm(struct mm_iommu_table_group_mem_t *mem,
> unsigned long ua, unsigned int pageshift, unsigned long *hpa);
> +extern void mm_iommu_ua_mark_dirty_rm(struct mm_struct *mm, unsigned long ua);
> extern long mm_iommu_mapped_inc(struct mm_iommu_table_group_mem_t *mem);
> extern void mm_iommu_mapped_dec(struct mm_iommu_table_group_mem_t *mem);
> #endif
> diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
> index af7a20d..19b4c62 100644
> --- a/arch/powerpc/kernel/iommu.c
> +++ b/arch/powerpc/kernel/iommu.c
> @@ -1013,31 +1013,6 @@ long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,
> }
> EXPORT_SYMBOL_GPL(iommu_tce_xchg);
>
> -#ifdef CONFIG_PPC_BOOK3S_64
> -long iommu_tce_xchg_rm(struct iommu_table *tbl, unsigned long entry,
> - unsigned long *hpa, enum dma_data_direction *direction)
> -{
> - long ret;
> -
> - ret = tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
> -
> - if (!ret && ((*direction == DMA_FROM_DEVICE) ||
> - (*direction == DMA_BIDIRECTIONAL))) {
> - struct page *pg = realmode_pfn_to_page(*hpa >> PAGE_SHIFT);
> -
> - if (likely(pg)) {
> - SetPageDirty(pg);
> - } else {
> - tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
> - ret = -EFAULT;
> - }
> - }
> -
> - return ret;
> -}
> -EXPORT_SYMBOL_GPL(iommu_tce_xchg_rm);
> -#endif
> -
> int iommu_take_ownership(struct iommu_table *tbl)
> {
> unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
> diff --git a/arch/powerpc/kvm/book3s_64_vio_hv.c b/arch/powerpc/kvm/book3s_64_vio_hv.c
> index 506a4d4..6821ead 100644
> --- a/arch/powerpc/kvm/book3s_64_vio_hv.c
> +++ b/arch/powerpc/kvm/book3s_64_vio_hv.c
> @@ -187,12 +187,35 @@ long kvmppc_gpa_to_ua(struct kvm *kvm, unsigned long gpa,
> EXPORT_SYMBOL_GPL(kvmppc_gpa_to_ua);
>
> #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> -static void kvmppc_rm_clear_tce(struct iommu_table *tbl, unsigned long entry)
> +static long iommu_tce_xchg_rm(struct mm_struct *mm, struct iommu_table *tbl,
> + unsigned long entry, unsigned long *hpa,
> + enum dma_data_direction *direction)
> +{
> + long ret;
> +
> + ret = tbl->it_ops->exchange_rm(tbl, entry, hpa, direction);
> +
> + if (!ret && ((*direction == DMA_FROM_DEVICE) ||
> + (*direction == DMA_BIDIRECTIONAL))) {
> + __be64 *pua = IOMMU_TABLE_USERSPACE_ENTRY_RM(tbl, entry);
> + /*
> + * kvmppc_rm_tce_iommu_do_map() updates the UA cache after
> + * calling this so we still get here a valid UA.
> + */
> + if (pua && *pua)
> + mm_iommu_ua_mark_dirty_rm(mm, be64_to_cpu(*pua));
> + }
> +
> + return ret;
> +}
> +
> +static void kvmppc_rm_clear_tce(struct kvm *kvm, struct iommu_table *tbl,
> + unsigned long entry)
> {
> unsigned long hpa = 0;
> enum dma_data_direction dir = DMA_NONE;
>
> - iommu_tce_xchg_rm(tbl, entry, &hpa, &dir);
> + iommu_tce_xchg_rm(kvm->mm, tbl, entry, &hpa, &dir);
> }
>
> static long kvmppc_rm_tce_iommu_mapped_dec(struct kvm *kvm,
> @@ -224,7 +247,7 @@ static long kvmppc_rm_tce_iommu_do_unmap(struct kvm *kvm,
> unsigned long hpa = 0;
> long ret;
>
> - if (iommu_tce_xchg_rm(tbl, entry, &hpa, &dir))
> + if (iommu_tce_xchg_rm(kvm->mm, tbl, entry, &hpa, &dir))
> /*
> * real mode xchg can fail if struct page crosses
> * a page boundary
> @@ -236,7 +259,7 @@ static long kvmppc_rm_tce_iommu_do_unmap(struct kvm *kvm,
>
> ret = kvmppc_rm_tce_iommu_mapped_dec(kvm, tbl, entry);
> if (ret)
> - iommu_tce_xchg_rm(tbl, entry, &hpa, &dir);
> + iommu_tce_xchg_rm(kvm->mm, tbl, entry, &hpa, &dir);
>
> return ret;
> }
> @@ -282,7 +305,7 @@ static long kvmppc_rm_tce_iommu_do_map(struct kvm *kvm, struct iommu_table *tbl,
> if (WARN_ON_ONCE_RM(mm_iommu_mapped_inc(mem)))
> return H_CLOSED;
>
> - ret = iommu_tce_xchg_rm(tbl, entry, &hpa, &dir);
> + ret = iommu_tce_xchg_rm(kvm->mm, tbl, entry, &hpa, &dir);
> if (ret) {
> mm_iommu_mapped_dec(mem);
> /*
> @@ -371,7 +394,7 @@ long kvmppc_rm_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
> return ret;
>
> WARN_ON_ONCE_RM(1);
> - kvmppc_rm_clear_tce(stit->tbl, entry);
> + kvmppc_rm_clear_tce(vcpu->kvm, stit->tbl, entry);
> }
>
> kvmppc_tce_put(stt, entry, tce);
> @@ -520,7 +543,7 @@ long kvmppc_rm_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> goto unlock_exit;
>
> WARN_ON_ONCE_RM(1);
> - kvmppc_rm_clear_tce(stit->tbl, entry);
> + kvmppc_rm_clear_tce(vcpu->kvm, stit->tbl, entry);
> }
>
> kvmppc_tce_put(stt, entry + i, tce);
> @@ -571,7 +594,7 @@ long kvmppc_rm_h_stuff_tce(struct kvm_vcpu *vcpu,
> return ret;
>
> WARN_ON_ONCE_RM(1);
> - kvmppc_rm_clear_tce(stit->tbl, entry);
> + kvmppc_rm_clear_tce(vcpu->kvm, stit->tbl, entry);
> }
> }
>
> diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
> index 51ce091..7a9886f 100644
> --- a/arch/powerpc/mm/init_64.c
> +++ b/arch/powerpc/mm/init_64.c
> @@ -308,55 +308,6 @@ void register_page_bootmem_memmap(unsigned long section_nr,
> {
> }
>
> -/*
> - * We do not have access to the sparsemem vmemmap, so we fallback to
> - * walking the list of sparsemem blocks which we already maintain for
> - * the sake of crashdump. In the long run, we might want to maintain
> - * a tree if performance of that linear walk becomes a problem.
> - *
> - * realmode_pfn_to_page functions can fail due to:
> - * 1) As real sparsemem blocks do not lay in RAM continously (they
> - * are in virtual address space which is not available in the real mode),
> - * the requested page struct can be split between blocks so get_page/put_page
> - * may fail.
> - * 2) When huge pages are used, the get_page/put_page API will fail
> - * in real mode as the linked addresses in the page struct are virtual
> - * too.
> - */
> -struct page *realmode_pfn_to_page(unsigned long pfn)
> -{
> - struct vmemmap_backing *vmem_back;
> - struct page *page;
> - unsigned long page_size = 1 << mmu_psize_defs[mmu_vmemmap_psize].shift;
> - unsigned long pg_va = (unsigned long) pfn_to_page(pfn);
> -
> - for (vmem_back = vmemmap_list; vmem_back; vmem_back = vmem_back->list) {
> - if (pg_va < vmem_back->virt_addr)
> - continue;
> -
> - /* After vmemmap_list entry free is possible, need check all */
> - if ((pg_va + sizeof(struct page)) <=
> - (vmem_back->virt_addr + page_size)) {
> - page = (struct page *) (vmem_back->phys + pg_va -
> - vmem_back->virt_addr);
> - return page;
> - }
> - }
> -
> - /* Probably that page struct is split between real pages */
> - return NULL;
> -}
> -EXPORT_SYMBOL_GPL(realmode_pfn_to_page);
> -
> -#else
> -
> -struct page *realmode_pfn_to_page(unsigned long pfn)
> -{
> - struct page *page = pfn_to_page(pfn);
> - return page;
> -}
> -EXPORT_SYMBOL_GPL(realmode_pfn_to_page);
> -
> #endif /* CONFIG_SPARSEMEM_VMEMMAP */
>
> #ifdef CONFIG_PPC_BOOK3S_64
> diff --git a/arch/powerpc/mm/mmu_context_iommu.c b/arch/powerpc/mm/mmu_context_iommu.c
> index c9ee9e2..56c2234 100644
> --- a/arch/powerpc/mm/mmu_context_iommu.c
> +++ b/arch/powerpc/mm/mmu_context_iommu.c
> @@ -18,11 +18,15 @@
> #include <linux/migrate.h>
> #include <linux/hugetlb.h>
> #include <linux/swap.h>
> +#include <linux/sizes.h>
> #include <asm/mmu_context.h>
> #include <asm/pte-walk.h>
>
> static DEFINE_MUTEX(mem_list_mutex);
>
> +#define MM_IOMMU_TABLE_GROUP_PAGE_DIRTY 0x1
> +#define MM_IOMMU_TABLE_GROUP_PAGE_MASK ~(SZ_4K - 1)
> +
> struct mm_iommu_table_group_mem_t {
> struct list_head next;
> struct rcu_head rcu;
> @@ -263,6 +267,9 @@ static void mm_iommu_unpin(struct mm_iommu_table_group_mem_t *mem)
> if (!page)
> continue;
>
> + if (mem->hpas[i] & MM_IOMMU_TABLE_GROUP_PAGE_DIRTY)
> + SetPageDirty(page);
> +
> put_page(page);
> mem->hpas[i] = 0;
> }
> @@ -360,7 +367,6 @@ struct mm_iommu_table_group_mem_t *mm_iommu_lookup_rm(struct mm_struct *mm,
>
> return ret;
> }
> -EXPORT_SYMBOL_GPL(mm_iommu_lookup_rm);
>
> struct mm_iommu_table_group_mem_t *mm_iommu_find(struct mm_struct *mm,
> unsigned long ua, unsigned long entries)
> @@ -390,7 +396,7 @@ long mm_iommu_ua_to_hpa(struct mm_iommu_table_group_mem_t *mem,
> if (pageshift > mem->pageshift)
> return -EFAULT;
>
> - *hpa = *va | (ua & ~PAGE_MASK);
> + *hpa = (*va & MM_IOMMU_TABLE_GROUP_PAGE_MASK) | (ua & ~PAGE_MASK);
>
> return 0;
> }
> @@ -413,11 +419,31 @@ long mm_iommu_ua_to_hpa_rm(struct mm_iommu_table_group_mem_t *mem,
> if (!pa)
> return -EFAULT;
>
> - *hpa = *pa | (ua & ~PAGE_MASK);
> + *hpa = (*pa & MM_IOMMU_TABLE_GROUP_PAGE_MASK) | (ua & ~PAGE_MASK);
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(mm_iommu_ua_to_hpa_rm);
> +
> +extern void mm_iommu_ua_mark_dirty_rm(struct mm_struct *mm, unsigned long ua)
> +{
> + struct mm_iommu_table_group_mem_t *mem;
> + long entry;
> + void *va;
> + unsigned long *pa;
> +
> + mem = mm_iommu_lookup_rm(mm, ua, PAGE_SIZE);
> + if (!mem)
> + return;
> +
> + entry = (ua - mem->ua) >> PAGE_SHIFT;
> + va = &mem->hpas[entry];
> +
> + pa = (void *) vmalloc_to_phys(va);
> + if (!pa)
> + return;
> +
> + *pa |= MM_IOMMU_TABLE_GROUP_PAGE_DIRTY;
> +}
>
> long mm_iommu_mapped_inc(struct mm_iommu_table_group_mem_t *mem)
> {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH kernel v2 6/6] KVM: PPC: Remove redundand permission bits removal
From: David Gibson @ 2018-09-11 3:15 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: linuxppc-dev, kvm-ppc, Aneesh Kumar K.V, Paul Mackerras,
Alex Williamson
In-Reply-To: <20180910082912.13255-7-aik@ozlabs.ru>
[-- Attachment #1: Type: text/plain, Size: 6853 bytes --]
On Mon, Sep 10, 2018 at 06:29:12PM +1000, Alexey Kardashevskiy wrote:
> The kvmppc_gpa_to_ua() helper itself takes care of the permission
> bits in the TCE and yet every single caller removes them.
>
> This changes semantics of kvmppc_gpa_to_ua() so it takes TCEs
> (which are GPAs + TCE permission bits) to make the callers simpler.
>
> This should cause no behavioural change.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> Changes:
> v2:
> * %s/kvmppc_gpa_to_ua/kvmppc_tce_to_ua/g
> ---
> arch/powerpc/include/asm/kvm_ppc.h | 2 +-
> arch/powerpc/kvm/book3s_64_vio.c | 12 ++++--------
> arch/powerpc/kvm/book3s_64_vio_hv.c | 22 +++++++++-------------
> 3 files changed, 14 insertions(+), 22 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
> index 2f5d431..38d0328 100644
> --- a/arch/powerpc/include/asm/kvm_ppc.h
> +++ b/arch/powerpc/include/asm/kvm_ppc.h
> @@ -194,7 +194,7 @@ extern struct kvmppc_spapr_tce_table *kvmppc_find_table(
> (iommu_tce_check_ioba((stt)->page_shift, (stt)->offset, \
> (stt)->size, (ioba), (npages)) ? \
> H_PARAMETER : H_SUCCESS)
> -extern long kvmppc_gpa_to_ua(struct kvm *kvm, unsigned long gpa,
> +extern long kvmppc_tce_to_ua(struct kvm *kvm, unsigned long tce,
> unsigned long *ua, unsigned long **prmap);
> extern void kvmppc_tce_put(struct kvmppc_spapr_tce_table *tt,
> unsigned long idx, unsigned long tce);
> diff --git a/arch/powerpc/kvm/book3s_64_vio.c b/arch/powerpc/kvm/book3s_64_vio.c
> index 8231b17..c0c64d1 100644
> --- a/arch/powerpc/kvm/book3s_64_vio.c
> +++ b/arch/powerpc/kvm/book3s_64_vio.c
> @@ -378,8 +378,7 @@ static long kvmppc_tce_validate(struct kvmppc_spapr_tce_table *stt,
> if (iommu_tce_check_gpa(stt->page_shift, gpa))
> return H_TOO_HARD;
>
> - if (kvmppc_gpa_to_ua(stt->kvm, tce & ~(TCE_PCI_READ | TCE_PCI_WRITE),
> - &ua, NULL))
> + if (kvmppc_tce_to_ua(stt->kvm, tce, &ua, NULL))
> return H_TOO_HARD;
>
> list_for_each_entry_rcu(stit, &stt->iommu_tables, next) {
> @@ -552,8 +551,7 @@ long kvmppc_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
>
> idx = srcu_read_lock(&vcpu->kvm->srcu);
>
> - if ((dir != DMA_NONE) && kvmppc_gpa_to_ua(vcpu->kvm,
> - tce & ~(TCE_PCI_READ | TCE_PCI_WRITE), &ua, NULL)) {
> + if ((dir != DMA_NONE) && kvmppc_tce_to_ua(vcpu->kvm, tce, &ua, NULL)) {
> ret = H_PARAMETER;
> goto unlock_exit;
> }
> @@ -614,7 +612,7 @@ long kvmppc_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> return ret;
>
> idx = srcu_read_lock(&vcpu->kvm->srcu);
> - if (kvmppc_gpa_to_ua(vcpu->kvm, tce_list, &ua, NULL)) {
> + if (kvmppc_tce_to_ua(vcpu->kvm, tce_list, &ua, NULL)) {
> ret = H_TOO_HARD;
> goto unlock_exit;
> }
> @@ -649,9 +647,7 @@ long kvmppc_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> }
> tce = be64_to_cpu(tce);
>
> - if (kvmppc_gpa_to_ua(vcpu->kvm,
> - tce & ~(TCE_PCI_READ | TCE_PCI_WRITE),
> - &ua, NULL))
> + if (kvmppc_tce_to_ua(vcpu->kvm, tce, &ua, NULL))
> return H_PARAMETER;
>
> list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
> diff --git a/arch/powerpc/kvm/book3s_64_vio_hv.c b/arch/powerpc/kvm/book3s_64_vio_hv.c
> index adf3b21..389dac1 100644
> --- a/arch/powerpc/kvm/book3s_64_vio_hv.c
> +++ b/arch/powerpc/kvm/book3s_64_vio_hv.c
> @@ -110,8 +110,7 @@ static long kvmppc_rm_tce_validate(struct kvmppc_spapr_tce_table *stt,
> if (iommu_tce_check_gpa(stt->page_shift, gpa))
> return H_PARAMETER;
>
> - if (kvmppc_gpa_to_ua(stt->kvm, tce & ~(TCE_PCI_READ | TCE_PCI_WRITE),
> - &ua, NULL))
> + if (kvmppc_tce_to_ua(stt->kvm, tce, &ua, NULL))
> return H_TOO_HARD;
>
> list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
> @@ -180,10 +179,10 @@ void kvmppc_tce_put(struct kvmppc_spapr_tce_table *stt,
> }
> EXPORT_SYMBOL_GPL(kvmppc_tce_put);
>
> -long kvmppc_gpa_to_ua(struct kvm *kvm, unsigned long gpa,
> +long kvmppc_tce_to_ua(struct kvm *kvm, unsigned long tce,
> unsigned long *ua, unsigned long **prmap)
> {
> - unsigned long gfn = gpa >> PAGE_SHIFT;
> + unsigned long gfn = tce >> PAGE_SHIFT;
> struct kvm_memory_slot *memslot;
>
> memslot = search_memslots(kvm_memslots(kvm), gfn);
> @@ -191,7 +190,7 @@ long kvmppc_gpa_to_ua(struct kvm *kvm, unsigned long gpa,
> return -EINVAL;
>
> *ua = __gfn_to_hva_memslot(memslot, gfn) |
> - (gpa & ~(PAGE_MASK | TCE_PCI_READ | TCE_PCI_WRITE));
> + (tce & ~(PAGE_MASK | TCE_PCI_READ | TCE_PCI_WRITE));
>
> #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> if (prmap)
> @@ -200,7 +199,7 @@ long kvmppc_gpa_to_ua(struct kvm *kvm, unsigned long gpa,
>
> return 0;
> }
> -EXPORT_SYMBOL_GPL(kvmppc_gpa_to_ua);
> +EXPORT_SYMBOL_GPL(kvmppc_tce_to_ua);
>
> #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
> static long iommu_tce_xchg_rm(struct mm_struct *mm, struct iommu_table *tbl,
> @@ -389,8 +388,7 @@ long kvmppc_rm_h_put_tce(struct kvm_vcpu *vcpu, unsigned long liobn,
> return ret;
>
> dir = iommu_tce_direction(tce);
> - if ((dir != DMA_NONE) && kvmppc_gpa_to_ua(vcpu->kvm,
> - tce & ~(TCE_PCI_READ | TCE_PCI_WRITE), &ua, NULL))
> + if ((dir != DMA_NONE) && kvmppc_tce_to_ua(vcpu->kvm, tce, &ua, NULL))
> return H_PARAMETER;
>
> entry = ioba >> stt->page_shift;
> @@ -492,7 +490,7 @@ long kvmppc_rm_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> */
> struct mm_iommu_table_group_mem_t *mem;
>
> - if (kvmppc_gpa_to_ua(vcpu->kvm, tce_list, &ua, NULL))
> + if (kvmppc_tce_to_ua(vcpu->kvm, tce_list, &ua, NULL))
> return H_TOO_HARD;
>
> mem = mm_iommu_lookup_rm(vcpu->kvm->mm, ua, IOMMU_PAGE_SIZE_4K);
> @@ -508,7 +506,7 @@ long kvmppc_rm_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> * We do not require memory to be preregistered in this case
> * so lock rmap and do __find_linux_pte_or_hugepte().
> */
> - if (kvmppc_gpa_to_ua(vcpu->kvm, tce_list, &ua, &rmap))
> + if (kvmppc_tce_to_ua(vcpu->kvm, tce_list, &ua, &rmap))
> return H_TOO_HARD;
>
> rmap = (void *) vmalloc_to_phys(rmap);
> @@ -542,9 +540,7 @@ long kvmppc_rm_h_put_tce_indirect(struct kvm_vcpu *vcpu,
> unsigned long tce = be64_to_cpu(((u64 *)tces)[i]);
>
> ua = 0;
> - if (kvmppc_gpa_to_ua(vcpu->kvm,
> - tce & ~(TCE_PCI_READ | TCE_PCI_WRITE),
> - &ua, NULL))
> + if (kvmppc_tce_to_ua(vcpu->kvm, tce, &ua, NULL))
> return H_PARAMETER;
>
> list_for_each_entry_lockless(stit, &stt->iommu_tables, next) {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: How to handle PTE tables with non contiguous entries ?
From: Christophe LEROY @ 2018-09-11 5:28 UTC (permalink / raw)
To: Dan Malek
Cc: akpm, linux-mm, aneesh.kumar, Nicholas Piggin, Michael Ellerman,
linuxppc-dev, LKML
In-Reply-To: <98C61C92-0D24-41C6-B9DA-8335B34D3B07@konsulko.com>
Le 10/09/2018 à 22:05, Dan Malek a écrit :
>
> Hello Cristophe.
>
>> On Sep 10, 2018, at 7:34 AM, Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>>
>> On the powerpc8xx, handling 16k size pages requires to have page tables with 4 identical entries.
>
> Do you think a 16k page is useful? Back in the day, the goal was to keep the fault handling and management overhead as simple and generic as possible, as you know this affects the system performance. I understand there would be fewer page faults and more efficient use of the MMU resources with 16k, but if this comes at an overhead cost, is it really worth it?
Yes that's definitly usefull, the current 16k implementation already
provides nice results, but it is based on the Linux structure, which
implies not being able to use the 8xx HW assistance in TLBmiss handlers.
That's the reason why I'm trying to alter the Linux structure to match
the 8xx page layout, hence the need to have 4 entries in the PTE for
each 16k page.
>
> In addition to the normal 4k mapping, I had thought about using 512k mapping, which could be easily detected at level 2 (PMD), with a single entry loaded into the MMU. We would need an aux header or something from the executable/library to assist with knowing when this could be done. I never got around to it. :)
Yes, 512k and 8M hugepages are implemented as well, but they are based
on Linux structure, hence requiring some time consuming handling like
checking the page size on every miss in order to run the appropriate
part of the handler.
With the HW layout, the 512k entries are spread every 128 bytes in the
PTE table but with those I don't have much problem because the hugepage
code uses huge_pte_offset() and never increase the pte pointer directly.
>
> The 8xx platforms tended to have smaller memory resources, so the 4k granularity was also useful in making better use of the available space.
Well, on my boards I have 128Mbytes, 16k page and hugepages have shown
their benefit.
>
>> Would someone have an idea of an elegent way to handle that ?
>
> My suggestion would be to not change the PTE table, but have the fault handler detect a 16k page and load any one of the four entries based upon miss offset. Kinda use the same 4k miss hander, but with 16k knowledge. You wouldn’t save any PTE table space, but the MMU efficiency may be worth it. As I recall, the hardware may ignore/mask any LS bits, and there is PMD level information to utilize as well.
That's exactly what I want to do, which means that everytime pte++ is
encountered in some mm/memory.c file needs to push the index to the next
16k page ie increase the pointer by 4 entries.
>
> It’s been a long time since I’ve investigated how things have evolved, glad it’s still in use, and I hope you at least have some fun with the development :)
Thanks
Christophe
^ permalink raw reply
* [PATCH kernel] powerpc/powernv/ioda2: Reduce upper limit for DMA window size (retry)
From: Alexey Kardashevskiy @ 2018-09-11 5:38 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy, Michael Ellerman
We use PHB in mode1 which uses bit 59 to select a correct DMA window.
However there is mode2 which uses bits 59:55 and allows up to 32 DMA
windows per a PE.
Even though documentation does not clearly specify that, it seems that
the actual hardware does not support bits 59:55 even in mode1, in other
words we can create a window as big as 1<<58 but DMA simply won't work.
This reduces the upper limit from 59 to 55 bits to let the userspace know
about the hardware limits.
Fixes: ce57c6610cc2 "Merge branch 'topic/ppc-kvm' into next"
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
The merge commit says d3d4ffaae439 (the original of this one) was
propagated but it was not:
[vpl1 kernel]$ git s ce57c6610cc2:arch/powerpc/platforms/powernv/pci-ioda-tce.c | grep 'page_shift >= '
if ((level_shift - 3) * levels + page_shift >= 60)
---
arch/powerpc/platforms/powernv/pci-ioda-tce.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda-tce.c b/arch/powerpc/platforms/powernv/pci-ioda-tce.c
index 6c5db1a..fe96910 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda-tce.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda-tce.c
@@ -276,7 +276,7 @@ long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
level_shift = entries_shift + 3;
level_shift = max_t(unsigned int, level_shift, PAGE_SHIFT);
- if ((level_shift - 3) * levels + page_shift >= 60)
+ if ((level_shift - 3) * levels + page_shift >= 55)
return -EINVAL;
/* Allocate TCE table */
--
2.11.0
^ permalink raw reply related
* Re: How to handle PTE tables with non contiguous entries ?
From: Christophe LEROY @ 2018-09-11 5:39 UTC (permalink / raw)
To: Nicholas Piggin
Cc: akpm, linux-mm, aneesh.kumar, Michael Ellerman, linuxppc-dev,
LKML
In-Reply-To: <20180911070645.239aef8a@roar.ozlabs.ibm.com>
Le 10/09/2018 à 23:06, Nicholas Piggin a écrit :
> On Mon, 10 Sep 2018 14:34:37 +0000
> Christophe Leroy <christophe.leroy@c-s.fr> wrote:
>
>> Hi,
>>
>> I'm having a hard time figuring out the best way to handle the following
>> situation:
>>
>> On the powerpc8xx, handling 16k size pages requires to have page tables
>> with 4 identical entries.
>>
>> Initially I was thinking about handling this by simply modifying
>> pte_index() which changing pte_t type in order to have one entry every
>> 16 bytes, then replicate the PTE value at *ptep, *ptep+1,*ptep+2 and
>> *ptep+3 both in set_pte_at() and pte_update().
>>
>> However, this doesn't work because many many places in the mm core part
>> of the kernel use loops on ptep with single ptep++ increment.
>>
>> Therefore did it with the following hack:
>>
>> /* PTE level */
>> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
>> +typedef struct { pte_basic_t pte, pte1, pte2, pte3; } pte_t;
>> +#else
>> typedef struct { pte_basic_t pte; } pte_t;
>> +#endif
>>
>> @@ -181,7 +192,13 @@ static inline unsigned long pte_update(pte_t *p,
>> : "cc" );
>> #else /* PTE_ATOMIC_UPDATES */
>> unsigned long old = pte_val(*p);
>> - *p = __pte((old & ~clr) | set);
>> + unsigned long new = (old & ~clr) | set;
>> +
>> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
>> + p->pte = p->pte1 = p->pte2 = p->pte3 = new;
>> +#else
>> + *p = __pte(new);
>> +#endif
>> #endif /* !PTE_ATOMIC_UPDATES */
>>
>> #ifdef CONFIG_44x
>>
>>
>> @@ -161,7 +161,11 @@ static inline void __set_pte_at(struct mm_struct
>> *mm, unsigned long addr,
>> /* Anything else just stores the PTE normally. That covers all
>> 64-bit
>> * cases, and 32-bit non-hash with 32-bit PTEs.
>> */
>> +#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
>> + ptep->pte = ptep->pte1 = ptep->pte2 = ptep->pte3 = pte_val(pte);
>> +#else
>> *ptep = pte;
>> +#endif
>>
>>
>>
>> But I'm not too happy with it as it means pte_t is not a single type
>> anymore so passing it from one function to the other is quite heavy.
>>
>>
>> Would someone have an idea of an elegent way to handle that ?
>
> I can't think of anything better. Do we pass pte by value to a lot of
> non inlined functions? Possible to inline the important ones?
Good question, I need to check that.
>
> Other option, try to get an iterator like pte = pte_next(pte) into core
> code.
Yes I've been thinking about that, but it looks like a huge job to
identify all places, as some drivers are also playing with it.
I'm not sure it is only to find all 'pte++' and 'ptep++', I fear there
might be places with more unexpected names.
Thanks
Christophe
>
> Thanks,
> Nick
>
^ permalink raw reply
* Re: [PATCH] KVM: PPC: Book3S HV: Don't use compound_order to determine host mapping size
From: Paul Mackerras @ 2018-09-11 10:01 UTC (permalink / raw)
To: Nicholas Piggin; +Cc: kvm-ppc, David Gibson, Aneesh Kumar K.V, linuxppc-dev
In-Reply-To: <20180904081601.32703-1-npiggin@gmail.com>
On Tue, Sep 04, 2018 at 06:16:01PM +1000, Nicholas Piggin wrote:
> THP paths can defer splitting compound pages until after the actual
> remap and TLB flushes to split a huge PMD/PUD. This causes radix
> partition scope page table mappings to get out of synch with the host
> qemu page table mappings.
>
> This results in random memory corruption in the guest when running
> with THP. The easiest way to reproduce is use KVM baloon to free up
> a lot of memory in the guest and then shrink the balloon to give the
> memory back, while some work is being done in the guest.
I'm hitting the WARN_ON you added. I think I have an old qemu that
doesn't 2M-align the guest ram and so we get to the level = 0 case
because of misalignment. The patch below on top of yours seems to
work just fine. In the case where the pte is 2M or 1G but we have
misalignment, it ORs in address bits from hva into the pte so we get
to the specific single page we want.
Care to fold this in and resend?
Paul.
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
index c290f59ae925..933c574e1cf7 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
@@ -660,11 +660,14 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
level = 1;
} else {
level = 0;
-
- /* Can not cope with unknown page shift */
- if (shift && shift != PAGE_SHIFT) {
- WARN_ON_ONCE(1);
- return -EFAULT;
+ if (shift > PAGE_SHIFT) {
+ /*
+ * If the pte maps more than one page, bring over
+ * bits from the virtual address to get the real
+ * address of the specific single page we want.
+ */
+ unsigned long rpnmask = (1ul << shift) - PAGE_SIZE;
+ pte = __pte(pte_val(pte) | (hva & rpnmask));
}
}
^ permalink raw reply related
* Patch "powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning" has been added to the 4.14-stable tree
From: gregkh @ 2018-09-11 10:14 UTC (permalink / raw)
To: alexander.levin, benh, galak, gregkh, linuxppc-dev, mpe, oss,
paulus, rdunlap
Cc: stable-commits
This is a note to let you know that I've just added the patch titled
powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-platforms-85xx-fix-t1042rdb_diu.c-build-errors-warning.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Tue Sep 11 12:07:47 CEST 2018
From: Randy Dunlap <rdunlap@infradead.org>
Date: Sun, 15 Jul 2018 10:34:46 -0700
Subject: powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning
From: Randy Dunlap <rdunlap@infradead.org>
[ Upstream commit f5daf77a55ef0e695cc90c440ed6503073ac5e07 ]
Fix build errors and warnings in t1042rdb_diu.c by adding header files
and MODULE_LICENSE().
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: warning: data definition has no type or storage class
early_initcall(t1042rdb_diu_init);
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: error: type defaults to 'int' in declaration of 'early_initcall' [-Werror=implicit-int]
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: warning: parameter names (without types) in function declaration
and
WARNING: modpost: missing MODULE_LICENSE() in arch/powerpc/platforms/85xx/t1042rdb_diu.o
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Scott Wood <oss@buserror.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -9,8 +9,10 @@
* option) any later version.
*/
+#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -150,3 +152,5 @@ static int __init t1042rdb_diu_init(void
}
early_initcall(t1042rdb_diu_init);
+
+MODULE_LICENSE("GPL");
Patches currently in stable-queue which might be from rdunlap@infradead.org are
queue-4.14/scripts-modpost-check-memory-allocation-results.patch
queue-4.14/platform-x86-intel_punit_ipc-fix-build-errors.patch
queue-4.14/powerpc-platforms-85xx-fix-t1042rdb_diu.c-build-errors-warning.patch
^ permalink raw reply
* Patch "powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning" has been added to the 4.18-stable tree
From: gregkh @ 2018-09-11 10:14 UTC (permalink / raw)
To: alexander.levin, benh, galak, gregkh, linuxppc-dev, mpe, oss,
paulus, rdunlap
Cc: stable-commits
This is a note to let you know that I've just added the patch titled
powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning
to the 4.18-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
powerpc-platforms-85xx-fix-t1042rdb_diu.c-build-errors-warning.patch
and it can be found in the queue-4.18 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@vger.kernel.org> know about it.
>From foo@baz Tue Sep 11 12:05:55 CEST 2018
From: Randy Dunlap <rdunlap@infradead.org>
Date: Sun, 15 Jul 2018 10:34:46 -0700
Subject: powerpc/platforms/85xx: fix t1042rdb_diu.c build errors & warning
From: Randy Dunlap <rdunlap@infradead.org>
[ Upstream commit f5daf77a55ef0e695cc90c440ed6503073ac5e07 ]
Fix build errors and warnings in t1042rdb_diu.c by adding header files
and MODULE_LICENSE().
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: warning: data definition has no type or storage class
early_initcall(t1042rdb_diu_init);
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: error: type defaults to 'int' in declaration of 'early_initcall' [-Werror=implicit-int]
../arch/powerpc/platforms/85xx/t1042rdb_diu.c:152:1: warning: parameter names (without types) in function declaration
and
WARNING: modpost: missing MODULE_LICENSE() in arch/powerpc/platforms/85xx/t1042rdb_diu.o
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Scott Wood <oss@buserror.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -9,8 +9,10 @@
* option) any later version.
*/
+#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -150,3 +152,5 @@ static int __init t1042rdb_diu_init(void
}
early_initcall(t1042rdb_diu_init);
+
+MODULE_LICENSE("GPL");
Patches currently in stable-queue which might be from rdunlap@infradead.org are
queue-4.18/scripts-modpost-check-memory-allocation-results.patch
queue-4.18/um-fix-parallel-building-with-o-option.patch
queue-4.18/mm-make-deferred_struct_page_init-explicitly-depend-on-sparsemem.patch
queue-4.18/platform-x86-intel_punit_ipc-fix-build-errors.patch
queue-4.18/powerpc-platforms-85xx-fix-t1042rdb_diu.c-build-errors-warning.patch
^ permalink raw reply
* Re: [PATCH] KVM: PPC: Book3S HV: Don't use compound_order to determine host mapping size
From: Nicholas Piggin @ 2018-09-11 10:46 UTC (permalink / raw)
To: Paul Mackerras; +Cc: kvm-ppc, David Gibson, Aneesh Kumar K.V, linuxppc-dev
In-Reply-To: <20180911100154.GC25158@fergus>
On Tue, 11 Sep 2018 20:01:54 +1000
Paul Mackerras <paulus@ozlabs.org> wrote:
> On Tue, Sep 04, 2018 at 06:16:01PM +1000, Nicholas Piggin wrote:
> > THP paths can defer splitting compound pages until after the actual
> > remap and TLB flushes to split a huge PMD/PUD. This causes radix
> > partition scope page table mappings to get out of synch with the host
> > qemu page table mappings.
> >
> > This results in random memory corruption in the guest when running
> > with THP. The easiest way to reproduce is use KVM baloon to free up
> > a lot of memory in the guest and then shrink the balloon to give the
> > memory back, while some work is being done in the guest.
>
> I'm hitting the WARN_ON you added. I think I have an old qemu that
> doesn't 2M-align the guest ram and so we get to the level = 0 case
> because of misalignment. The patch below on top of yours seems to
> work just fine. In the case where the pte is 2M or 1G but we have
> misalignment, it ORs in address bits from hva into the pte so we get
> to the specific single page we want.
>
> Care to fold this in and resend?
Thanks for that, I misunderstood the unaligned adjustment case.
Good thing you caught it.
Thanks,
Nick
^ permalink raw reply
* [PATCH v2] KVM: PPC: Book3S HV: Don't use compound_order to determine host mapping size
From: Nicholas Piggin @ 2018-09-11 10:48 UTC (permalink / raw)
To: kvm-ppc
Cc: Nicholas Piggin, Paul Mackerras, David Gibson, Aneesh Kumar K.V,
linuxppc-dev
THP paths can defer splitting compound pages until after the actual
remap and TLB flushes to split a huge PMD/PUD. This causes radix
partition scope page table mappings to get out of synch with the host
qemu page table mappings.
This results in random memory corruption in the guest when running
with THP. The easiest way to reproduce is use KVM baloon to free up
a lot of memory in the guest and then shrink the balloon to give the
memory back, while some work is being done in the guest.
Cc: Paul Mackerras <paulus@ozlabs.org>
Cc: David Gibson <david@gibson.dropbear.id.au>
Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com>
Cc: kvm-ppc@vger.kernel.org
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
v2: fold in unaligned case bugfix
arch/powerpc/kvm/book3s_64_mmu_radix.c | 91 +++++++++++---------------
1 file changed, 37 insertions(+), 54 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
index 0af1c0aea1fe..f85e15700355 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
@@ -525,8 +525,8 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
unsigned long ea, unsigned long dsisr)
{
struct kvm *kvm = vcpu->kvm;
- unsigned long mmu_seq, pte_size;
- unsigned long gpa, gfn, hva, pfn;
+ unsigned long mmu_seq;
+ unsigned long gpa, gfn, hva;
struct kvm_memory_slot *memslot;
struct page *page = NULL;
long ret;
@@ -623,9 +623,10 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
*/
hva = gfn_to_hva_memslot(memslot, gfn);
if (upgrade_p && __get_user_pages_fast(hva, 1, 1, &page) == 1) {
- pfn = page_to_pfn(page);
upgrade_write = true;
} else {
+ unsigned long pfn;
+
/* Call KVM generic code to do the slow-path check */
pfn = __gfn_to_pfn_memslot(memslot, gfn, false, NULL,
writing, upgrade_p);
@@ -639,63 +640,45 @@ int kvmppc_book3s_radix_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
}
}
- /* See if we can insert a 1GB or 2MB large PTE here */
- level = 0;
- if (page && PageCompound(page)) {
- pte_size = PAGE_SIZE << compound_order(compound_head(page));
- if (pte_size >= PUD_SIZE &&
- (gpa & (PUD_SIZE - PAGE_SIZE)) ==
- (hva & (PUD_SIZE - PAGE_SIZE))) {
- level = 2;
- pfn &= ~((PUD_SIZE >> PAGE_SHIFT) - 1);
- } else if (pte_size >= PMD_SIZE &&
- (gpa & (PMD_SIZE - PAGE_SIZE)) ==
- (hva & (PMD_SIZE - PAGE_SIZE))) {
- level = 1;
- pfn &= ~((PMD_SIZE >> PAGE_SHIFT) - 1);
- }
- }
-
/*
- * Compute the PTE value that we need to insert.
+ * Read the PTE from the process' radix tree and use that
+ * so we get the shift and attribute bits.
*/
- if (page) {
- pgflags = _PAGE_READ | _PAGE_EXEC | _PAGE_PRESENT | _PAGE_PTE |
- _PAGE_ACCESSED;
- if (writing || upgrade_write)
- pgflags |= _PAGE_WRITE | _PAGE_DIRTY;
- pte = pfn_pte(pfn, __pgprot(pgflags));
+ local_irq_disable();
+ ptep = __find_linux_pte(vcpu->arch.pgdir, hva, NULL, &shift);
+ pte = *ptep;
+ local_irq_enable();
+
+ /* Get pte level from shift/size */
+ if (shift == PUD_SHIFT &&
+ (gpa & (PUD_SIZE - PAGE_SIZE)) ==
+ (hva & (PUD_SIZE - PAGE_SIZE))) {
+ level = 2;
+ } else if (shift == PMD_SHIFT &&
+ (gpa & (PMD_SIZE - PAGE_SIZE)) ==
+ (hva & (PMD_SIZE - PAGE_SIZE))) {
+ level = 1;
} else {
- /*
- * Read the PTE from the process' radix tree and use that
- * so we get the attribute bits.
- */
- local_irq_disable();
- ptep = __find_linux_pte(vcpu->arch.pgdir, hva, NULL, &shift);
- pte = *ptep;
- local_irq_enable();
- if (shift == PUD_SHIFT &&
- (gpa & (PUD_SIZE - PAGE_SIZE)) ==
- (hva & (PUD_SIZE - PAGE_SIZE))) {
- level = 2;
- } else if (shift == PMD_SHIFT &&
- (gpa & (PMD_SIZE - PAGE_SIZE)) ==
- (hva & (PMD_SIZE - PAGE_SIZE))) {
- level = 1;
- } else if (shift && shift != PAGE_SHIFT) {
- /* Adjust PFN */
- unsigned long mask = (1ul << shift) - PAGE_SIZE;
- pte = __pte(pte_val(pte) | (hva & mask));
- }
- pte = __pte(pte_val(pte) | _PAGE_EXEC | _PAGE_ACCESSED);
- if (writing || upgrade_write) {
- if (pte_val(pte) & _PAGE_WRITE)
- pte = __pte(pte_val(pte) | _PAGE_DIRTY);
- } else {
- pte = __pte(pte_val(pte) & ~(_PAGE_WRITE | _PAGE_DIRTY));
+ level = 0;
+ if (shift > PAGE_SHIFT) {
+ /*
+ * If the pte maps more than one page, bring over
+ * bits from the virtual address to get the real
+ * address of the specific single page we want.
+ */
+ unsigned long rpnmask = (1ul << shift) - PAGE_SIZE;
+ pte = __pte(pte_val(pte) | (hva & rpnmask));
}
}
+ pte = __pte(pte_val(pte) | _PAGE_EXEC | _PAGE_ACCESSED);
+ if (writing || upgrade_write) {
+ if (pte_val(pte) & _PAGE_WRITE)
+ pte = __pte(pte_val(pte) | _PAGE_DIRTY);
+ } else {
+ pte = __pte(pte_val(pte) & ~(_PAGE_WRITE | _PAGE_DIRTY));
+ }
+
/* Allocate space in the tree and write the PTE */
ret = kvmppc_create_pte(kvm, pte, gpa, level, mmu_seq);
--
2.18.0
^ permalink raw reply related
* Re: [PATCH 1/2] powerpc/boot: Fix crt0.S syntax for clang
From: Segher Boessenkool @ 2018-09-11 11:32 UTC (permalink / raw)
To: Joel Stanley; +Cc: linuxppc-dev, Anton Blanchard
In-Reply-To: <20180910085714.4834-2-joel@jms.id.au>
On Mon, Sep 10, 2018 at 06:57:13PM +1000, Joel Stanley wrote:
> Clang's assembler does not like the syntax of the cmpdi:
>
> arch/powerpc/boot/crt0.S:168:22: error: unexpected modifier on variable reference
> cmpdi 12,RELACOUNT@l
> ^
> arch/powerpc/boot/crt0.S:168:11: error: unknown operand
> cmpdi 12,RELACOUNT@l
> ^
> Enclosing RELACOUNT in () makes it is happy. Tested with GCC 8 and Clang
> 8 (trunk).
Is clang going to fix this? You also might want to add a comment that
this is a workaround for that broken assembler.
Segher
^ permalink raw reply
* [PATCH v3 0/6] powerpc/powernv/pci: Discover surprise-hotplugged PCIe devices during rescan
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
This patchset allows hotplugged PCIe devices to be enumerated during a bus
rescan being issued via sysfs on PowerNV platforms, when the "Presence
Detect Changed" interrupt is not available.
As a first part of our work on adding support for hotplugging PCIe bridges
full of devices (without special requirement such as Hot-Plug Controller,
reservation of bus numbers and memory regions by firmware, etc.), this
serie is intended to solve the first two problems of the listed below:
I PowerNV doesn't discover new hotplugged PCIe devices
II EEH is falsely triggered when poking empty slots during the PCIe rescan
III The PCI subsystem is not prepared to runtime changes of BAR addresses
IV Device drivers don't track changes of their BAR addresses
V BARs of working devices don't move to make space for new ones
VI PCIe bridge hotplug is not supported
Tested on:
- POWER8 PowerNV+OPAL ppc64le (our Vesnin server) w/ and w/o pci=realloc;
- POWER8 IBM 8247-42L (pSeries);
- POWER8 IBM 8247-42L (PowerNV+OPAL) w/ and w/o pci=realloc.
Changes since v2:
- Don't reassign bus numbers on PowerNV by default (to retain the default
behavior), but only when pci=realloc is passed;
- Less code affected;
- pci_add_device_node_info is refactored with add_one_dev_pci_data;
- Minor code cleanup.
Changes since v1:
- Fixed build for ppc64le and ppc64be when CONFIG_PCI_IOV is disabled;
- Fixed build for ppc64e when CONFIG_EEH is disabled;
- Fixed code style warnings.
Sergey Miroshnichenko (6):
powerpc/pci: Access PCI config space directly w/o pci_dn
powerpc/pci: Create pci_dn on demand
powerpc/pci: Use DT to create pci_dn for root bridges only
powerpc/powernv/pci: Enable reassigning the bus numbers
PCI/powerpc/eeh: Add pcibios hooks for preparing to rescan
powerpc/pci: Reduce code duplication in pci_add_device_node_info
arch/powerpc/include/asm/eeh.h | 2 +
arch/powerpc/kernel/eeh.c | 12 ++
arch/powerpc/kernel/pci_dn.c | 119 ++++++++++++++-----
arch/powerpc/kernel/rtas_pci.c | 97 ++++++++++-----
arch/powerpc/platforms/powernv/eeh-powernv.c | 22 ++++
arch/powerpc/platforms/powernv/pci.c | 64 ++++++----
drivers/pci/probe.c | 14 +++
include/linux/pci.h | 2 +
8 files changed, 253 insertions(+), 79 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH v3 1/6] powerpc/pci: Access PCI config space directly w/o pci_dn
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
The pci_dn structures are retrieved from a DT, but hot-plugged PCIe
devices don't have them. Don't stop PCIe I/O in absence of pci_dn, so
it is now possible to discover new devices.
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/kernel/rtas_pci.c | 97 +++++++++++++++++++---------
arch/powerpc/platforms/powernv/pci.c | 64 ++++++++++++------
2 files changed, 109 insertions(+), 52 deletions(-)
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index c2b148b1634a..f675b5ecb5bc 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -55,10 +55,26 @@ static inline int config_access_valid(struct pci_dn *dn, int where)
return 0;
}
-int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
+static int rtas_read_raw_config(unsigned long buid, int busno, unsigned int devfn,
+ int where, int size, u32 *val)
{
int returnval = -1;
- unsigned long buid, addr;
+ unsigned long addr = rtas_config_addr(busno, devfn, where);
+ int ret;
+
+ if (buid) {
+ ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
+ addr, BUID_HI(buid), BUID_LO(buid), size);
+ } else {
+ ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
+ }
+ *val = returnval;
+
+ return ret;
+}
+
+int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
+{
int ret;
if (!pdn)
@@ -71,16 +87,8 @@ int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
return PCIBIOS_SET_FAILED;
#endif
- addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
- buid = pdn->phb->buid;
- if (buid) {
- ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
- addr, BUID_HI(buid), BUID_LO(buid), size);
- } else {
- ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
- }
- *val = returnval;
-
+ ret = rtas_read_raw_config(pdn->phb->buid, pdn->busno, pdn->devfn,
+ where, size, val);
if (ret)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -98,18 +106,44 @@ static int rtas_pci_read_config(struct pci_bus *bus,
pdn = pci_get_pdn_by_devfn(bus, devfn);
- /* Validity of pdn is checked in here */
- ret = rtas_read_config(pdn, where, size, val);
- if (*val == EEH_IO_ERROR_VALUE(size) &&
- eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
- return PCIBIOS_DEVICE_NOT_FOUND;
+ if (pdn) {
+ /* Validity of pdn is checked in here */
+ ret = rtas_read_config(pdn, where, size, val);
+
+ if (*val == EEH_IO_ERROR_VALUE(size) &&
+ eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
+ ret = PCIBIOS_DEVICE_NOT_FOUND;
+ } else {
+ struct pci_controller *phb = pci_bus_to_host(bus);
+
+ ret = rtas_read_raw_config(phb->buid, bus->number, devfn,
+ where, size, val);
+ }
return ret;
}
+static int rtas_write_raw_config(unsigned long buid, int busno, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ unsigned long addr = rtas_config_addr(busno, devfn, where);
+ int ret;
+
+ if (buid) {
+ ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
+ BUID_HI(buid), BUID_LO(buid), size, (ulong)val);
+ } else {
+ ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
+ }
+
+ if (ret)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
{
- unsigned long buid, addr;
int ret;
if (!pdn)
@@ -122,15 +156,8 @@ int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
return PCIBIOS_SET_FAILED;
#endif
- addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
- buid = pdn->phb->buid;
- if (buid) {
- ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
- BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
- } else {
- ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
- }
-
+ ret = rtas_write_raw_config(pdn->phb->buid, pdn->busno, pdn->devfn,
+ where, size, val);
if (ret)
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -141,12 +168,20 @@ static int rtas_pci_write_config(struct pci_bus *bus,
unsigned int devfn,
int where, int size, u32 val)
{
- struct pci_dn *pdn;
+ struct pci_dn *pdn = pci_get_pdn_by_devfn(bus, devfn);
+ int ret;
- pdn = pci_get_pdn_by_devfn(bus, devfn);
+ if (pdn) {
+ /* Validity of pdn is checked in here. */
+ ret = rtas_write_config(pdn, where, size, val);
+ } else {
+ struct pci_controller *phb = pci_bus_to_host(bus);
- /* Validity of pdn is checked in here. */
- return rtas_write_config(pdn, where, size, val);
+ ret = rtas_write_raw_config(phb->buid, bus->number, devfn,
+ where, size, val);
+ }
+
+ return ret;
}
static struct pci_ops rtas_pci_ops = {
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 13aef2323bbc..196b9d1c87b4 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -654,30 +654,29 @@ static void pnv_pci_config_check_eeh(struct pci_dn *pdn)
}
}
-int pnv_pci_cfg_read(struct pci_dn *pdn,
- int where, int size, u32 *val)
+static int pnv_pci_cfg_read_raw(u64 phb_id, int busno, unsigned int devfn,
+ int where, int size, u32 *val)
{
- struct pnv_phb *phb = pdn->phb->private_data;
- u32 bdfn = (pdn->busno << 8) | pdn->devfn;
+ u32 bdfn = (busno << 8) | devfn;
s64 rc;
switch (size) {
case 1: {
u8 v8;
- rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
+ rc = opal_pci_config_read_byte(phb_id, bdfn, where, &v8);
*val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
break;
}
case 2: {
__be16 v16;
- rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
- &v16);
+ rc = opal_pci_config_read_half_word(phb_id, bdfn, where,
+ &v16);
*val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff;
break;
}
case 4: {
__be32 v32;
- rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
+ rc = opal_pci_config_read_word(phb_id, bdfn, where, &v32);
*val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff;
break;
}
@@ -686,27 +685,28 @@ int pnv_pci_cfg_read(struct pci_dn *pdn,
}
pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
- __func__, pdn->busno, pdn->devfn, where, size, *val);
+ __func__, busno, devfn, where, size, *val);
+
return PCIBIOS_SUCCESSFUL;
}
-int pnv_pci_cfg_write(struct pci_dn *pdn,
- int where, int size, u32 val)
+static int pnv_pci_cfg_write_raw(u64 phb_id, int busno, unsigned int devfn,
+ int where, int size, u32 val)
{
- struct pnv_phb *phb = pdn->phb->private_data;
- u32 bdfn = (pdn->busno << 8) | pdn->devfn;
+ u32 bdfn = (busno << 8) | devfn;
pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
- __func__, pdn->busno, pdn->devfn, where, size, val);
+ __func__, busno, devfn, where, size, val);
+
switch (size) {
case 1:
- opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
+ opal_pci_config_write_byte(phb_id, bdfn, where, val);
break;
case 2:
- opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
+ opal_pci_config_write_half_word(phb_id, bdfn, where, val);
break;
case 4:
- opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
+ opal_pci_config_write_word(phb_id, bdfn, where, val);
break;
default:
return PCIBIOS_FUNC_NOT_SUPPORTED;
@@ -715,6 +715,24 @@ int pnv_pci_cfg_write(struct pci_dn *pdn,
return PCIBIOS_SUCCESSFUL;
}
+int pnv_pci_cfg_read(struct pci_dn *pdn,
+ int where, int size, u32 *val)
+{
+ struct pnv_phb *phb = pdn->phb->private_data;
+
+ return pnv_pci_cfg_read_raw(phb->opal_id, pdn->busno, pdn->devfn,
+ where, size, val);
+}
+
+int pnv_pci_cfg_write(struct pci_dn *pdn,
+ int where, int size, u32 val)
+{
+ struct pnv_phb *phb = pdn->phb->private_data;
+
+ return pnv_pci_cfg_write_raw(phb->opal_id, pdn->busno, pdn->devfn,
+ where, size, val);
+}
+
#if CONFIG_EEH
static bool pnv_pci_cfg_check(struct pci_dn *pdn)
{
@@ -750,13 +768,15 @@ static int pnv_pci_read_config(struct pci_bus *bus,
int where, int size, u32 *val)
{
struct pci_dn *pdn;
- struct pnv_phb *phb;
+ struct pci_controller *hose = pci_bus_to_host(bus);
+ struct pnv_phb *phb = hose->private_data;
int ret;
*val = 0xFFFFFFFF;
pdn = pci_get_pdn_by_devfn(bus, devfn);
if (!pdn)
- return PCIBIOS_DEVICE_NOT_FOUND;
+ return pnv_pci_cfg_read_raw(phb->opal_id, bus->number, devfn,
+ where, size, val);
if (!pnv_pci_cfg_check(pdn))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -779,12 +799,14 @@ static int pnv_pci_write_config(struct pci_bus *bus,
int where, int size, u32 val)
{
struct pci_dn *pdn;
- struct pnv_phb *phb;
+ struct pci_controller *hose = pci_bus_to_host(bus);
+ struct pnv_phb *phb = hose->private_data;
int ret;
pdn = pci_get_pdn_by_devfn(bus, devfn);
if (!pdn)
- return PCIBIOS_DEVICE_NOT_FOUND;
+ return pnv_pci_cfg_write_raw(phb->opal_id, bus->number, devfn,
+ where, size, val);
if (!pnv_pci_cfg_check(pdn))
return PCIBIOS_DEVICE_NOT_FOUND;
--
2.17.1
^ permalink raw reply related
* [PATCH v3 3/6] powerpc/pci: Use DT to create pci_dn for root bridges only
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
Endpoint's pci_dn can be created dynamically.
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/kernel/pci_dn.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index e2b39b562b53..8bcf10fb13ad 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -552,8 +552,10 @@ void pci_devs_phb_init_dynamic(struct pci_controller *phb)
phb->pci_data = pdn;
}
- /* Update dn->phb ptrs for new phb and children devices */
- pci_traverse_device_nodes(dn, add_pdn, phb);
+ if (!pci_has_flag(PCI_REASSIGN_ALL_BUS)) {
+ /* Update dn->phb ptrs for new phb and children devices */
+ pci_traverse_device_nodes(dn, add_pdn, phb);
+ }
}
/**
--
2.17.1
^ permalink raw reply related
* [PATCH v3 2/6] powerpc/pci: Create pci_dn on demand
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
The pci_dn structures can be created not only from DT, but also
directly from newly discovered PCIe devices, so allocate them
dynamically.
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/kernel/pci_dn.c | 63 ++++++++++++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index ab147a1909c8..e2b39b562b53 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -33,6 +33,8 @@
#include <asm/firmware.h>
#include <asm/eeh.h>
+static struct pci_dn *create_pdn(struct pci_dev *pdev, struct pci_dn *parent);
+
/*
* The function is used to find the firmware data of one
* specific PCI device, which is attached to the indicated
@@ -58,6 +60,9 @@ static struct pci_dn *pci_bus_to_pdn(struct pci_bus *bus)
pbus = pbus->parent;
}
+ if (!pbus->self && !pci_is_root_bus(pbus))
+ return NULL;
+
/*
* Except virtual bus, all PCI buses should
* have device nodes.
@@ -65,6 +70,9 @@ static struct pci_dn *pci_bus_to_pdn(struct pci_bus *bus)
dn = pci_bus_to_OF_node(pbus);
pdn = dn ? PCI_DN(dn) : NULL;
+ if (!pdn && pbus->self)
+ pdn = pbus->self->dev.archdata.pci_data;
+
return pdn;
}
@@ -134,10 +142,9 @@ struct pci_dn *pci_get_pdn(struct pci_dev *pdev)
return pdn;
}
- return NULL;
+ return create_pdn(pdev, parent);
}
-#ifdef CONFIG_PCI_IOV
static struct pci_dn *add_one_dev_pci_data(struct pci_dn *parent,
int vf_index,
int busno, int devfn)
@@ -156,7 +163,9 @@ static struct pci_dn *add_one_dev_pci_data(struct pci_dn *parent,
pdn->parent = parent;
pdn->busno = busno;
pdn->devfn = devfn;
+ #ifdef CONFIG_PCI_IOV
pdn->vf_index = vf_index;
+ #endif /* CONFIG_PCI_IOV */
pdn->pe_number = IODA_INVALID_PE;
INIT_LIST_HEAD(&pdn->child_list);
INIT_LIST_HEAD(&pdn->list);
@@ -164,7 +173,55 @@ static struct pci_dn *add_one_dev_pci_data(struct pci_dn *parent,
return pdn;
}
-#endif
+
+static struct pci_dn *create_pdn(struct pci_dev *pdev, struct pci_dn *parent)
+{
+ struct pci_dn *pdn = NULL;
+
+ if (!parent)
+ return NULL;
+
+ pdn = add_one_dev_pci_data(parent, 0, pdev->bus->busn_res.start, pdev->devfn);
+ dev_info(&pdev->dev, "Create a new pdn for devfn %2x\n", pdev->devfn / 8);
+
+ if (pdn) {
+ #ifdef CONFIG_EEH
+ struct eeh_dev *edev;
+ #endif /* CONFIG_EEH */
+ u32 class_code;
+ u16 device_id;
+ u16 vendor_id;
+
+ #ifdef CONFIG_EEH
+ edev = eeh_dev_init(pdn);
+ if (!edev) {
+ kfree(pdn);
+ dev_err(&pdev->dev, "%s: Failed to allocate edev\n", __func__);
+ return NULL;
+ }
+ #endif /* CONFIG_EEH */
+
+ pci_bus_read_config_word(pdev->bus, pdev->devfn,
+ PCI_VENDOR_ID, &vendor_id);
+ pdn->vendor_id = vendor_id;
+
+ pci_bus_read_config_word(pdev->bus, pdev->devfn,
+ PCI_DEVICE_ID, &device_id);
+ pdn->device_id = device_id;
+
+ pci_bus_read_config_dword(pdev->bus, pdev->devfn,
+ PCI_CLASS_REVISION, &class_code);
+ class_code >>= 8;
+ pdn->class_code = class_code;
+
+ pdn->pci_ext_config_space = 0;
+ pdev->dev.archdata.pci_data = pdn;
+ } else {
+ dev_err(&pdev->dev, "%s: Failed to allocate pdn\n", __func__);
+ }
+
+ return pdn;
+}
struct pci_dn *add_dev_pci_data(struct pci_dev *pdev)
{
--
2.17.1
^ permalink raw reply related
* [PATCH v3 4/6] powerpc/powernv/pci: Enable reassigning the bus numbers
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
PowerNV doesn't depend on PCIe topology info from DT anymore, and now
it is able to enumerate the fabric and assign the bus numbers.
This is enabled by the pci=realloc command line switch.
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/kernel/pci_dn.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 8bcf10fb13ad..863d00561c50 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -592,3 +592,15 @@ static void pci_dev_pdn_setup(struct pci_dev *pdev)
pdev->dev.archdata.pci_data = pdn;
}
DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pci_dev_pdn_setup);
+
+char * __init pcibios_setup(char *str)
+{
+ if (!strncmp(str, "realloc=", 8)) {
+ if (!strncmp(str + 8, "on", 2))
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ } else if (!strncmp(str, "realloc", 7)) {
+ pci_add_flags(PCI_REASSIGN_ALL_BUS);
+ }
+
+ return str;
+}
--
2.17.1
^ permalink raw reply related
* [PATCH v3 5/6] PCI/powerpc/eeh: Add pcibios hooks for preparing to rescan
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
Reading an empty slot returns all ones, which triggers a false
EEH error event on PowerNV.
New callbacks pcibios_rescan_prepare/done are introduced to
pause/resume the EEH during rescan.
In the same time it makes possible to miss a real EEH event during
rescan.
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/include/asm/eeh.h | 2 ++
arch/powerpc/kernel/eeh.c | 12 +++++++++++
arch/powerpc/platforms/powernv/eeh-powernv.c | 22 ++++++++++++++++++++
drivers/pci/probe.c | 14 +++++++++++++
include/linux/pci.h | 2 ++
5 files changed, 52 insertions(+)
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 219637ea69a1..63c8e8fa671f 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -219,6 +219,8 @@ struct eeh_ops {
int (*next_error)(struct eeh_pe **pe);
int (*restore_config)(struct pci_dn *pdn);
int (*notify_resume)(struct pci_dn *pdn);
+ int (*rescan_prepare)(struct pci_bus *bus);
+ int (*rescan_done)(struct pci_bus *bus);
};
extern int eeh_subsystem_flags;
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index 6ebba3e48b01..d55f1089ca7b 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -1831,3 +1831,15 @@ static int __init eeh_init_proc(void)
return 0;
}
__initcall(eeh_init_proc);
+
+void pcibios_rescan_prepare(struct pci_bus *bus)
+{
+ if (eeh_ops && eeh_ops->rescan_prepare)
+ eeh_ops->rescan_prepare(bus);
+}
+
+void pcibios_rescan_done(struct pci_bus *bus)
+{
+ if (eeh_ops && eeh_ops->rescan_done)
+ eeh_ops->rescan_done(bus);
+}
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 3c1beae29f2d..44c74aa89fb4 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -59,6 +59,26 @@ void pnv_pcibios_bus_add_device(struct pci_dev *pdev)
eeh_sysfs_add_device(pdev);
}
+static int pnv_eeh_rescan_prepare(struct pci_bus *bus)
+{
+ struct pci_controller *hose = pci_bus_to_host(bus);
+ struct pnv_phb *phb = hose->private_data;
+
+ phb->flags &= ~PNV_PHB_FLAG_EEH;
+ disable_irq(eeh_event_irq);
+ return 0;
+}
+
+static int pnv_eeh_rescan_done(struct pci_bus *bus)
+{
+ struct pci_controller *hose = pci_bus_to_host(bus);
+ struct pnv_phb *phb = hose->private_data;
+
+ enable_irq(eeh_event_irq);
+ phb->flags |= PNV_PHB_FLAG_EEH;
+ return 0;
+}
+
static int pnv_eeh_init(void)
{
struct pci_controller *hose;
@@ -1710,6 +1730,8 @@ static struct eeh_ops pnv_eeh_ops = {
.write_config = pnv_eeh_write_config,
.next_error = pnv_eeh_next_error,
.restore_config = pnv_eeh_restore_config,
+ .rescan_prepare = pnv_eeh_rescan_prepare,
+ .rescan_done = pnv_eeh_rescan_done,
.notify_resume = NULL
};
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ac876e32de4b..4a9045364809 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2801,6 +2801,14 @@ void __weak pcibios_remove_bus(struct pci_bus *bus)
{
}
+void __weak pcibios_rescan_prepare(struct pci_bus *bus)
+{
+}
+
+void __weak pcibios_rescan_done(struct pci_bus *bus)
+{
+}
+
struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
struct pci_ops *ops, void *sysdata, struct list_head *resources)
{
@@ -3055,9 +3063,15 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
unsigned int pci_rescan_bus(struct pci_bus *bus)
{
unsigned int max;
+ struct pci_bus *root = bus;
+
+ while (!pci_is_root_bus(root))
+ root = root->parent;
+ pcibios_rescan_prepare(root);
max = pci_scan_child_bus(bus);
pci_assign_unassigned_bus_resources(bus);
+ pcibios_rescan_done(root);
pci_bus_add_devices(bus);
return max;
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 340029b2fb38..42930731c5a7 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1929,6 +1929,8 @@ void pcibios_penalize_isa_irq(int irq, int active);
int pcibios_alloc_irq(struct pci_dev *dev);
void pcibios_free_irq(struct pci_dev *dev);
resource_size_t pcibios_default_alignment(void);
+void pcibios_rescan_prepare(struct pci_bus *bus);
+void pcibios_rescan_done(struct pci_bus *bus);
#ifdef CONFIG_HIBERNATE_CALLBACKS
extern struct dev_pm_ops pcibios_pm_ops;
--
2.17.1
^ permalink raw reply related
* [PATCH v3 6/6] powerpc/pci: Reduce code duplication in pci_add_device_node_info
From: Sergey Miroshnichenko @ 2018-09-11 11:56 UTC (permalink / raw)
To: linuxppc-dev; +Cc: linux, Sergey Miroshnichenko
In-Reply-To: <20180911115620.10507-1-s.miroshnichenko@yadro.com>
It is possible now to allocate and fill a new pdn with add_one_dev_pci_data
Signed-off-by: Sergey Miroshnichenko <s.miroshnichenko@yadro.com>
---
arch/powerpc/kernel/pci_dn.c | 38 +++++++++++++++---------------------
1 file changed, 16 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/kernel/pci_dn.c b/arch/powerpc/kernel/pci_dn.c
index 863d00561c50..9bd780895926 100644
--- a/arch/powerpc/kernel/pci_dn.c
+++ b/arch/powerpc/kernel/pci_dn.c
@@ -151,15 +151,10 @@ static struct pci_dn *add_one_dev_pci_data(struct pci_dn *parent,
{
struct pci_dn *pdn;
- /* Except PHB, we always have the parent */
- if (!parent)
- return NULL;
-
pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
if (!pdn)
return NULL;
- pdn->phb = parent->phb;
pdn->parent = parent;
pdn->busno = busno;
pdn->devfn = devfn;
@@ -169,7 +164,10 @@ static struct pci_dn *add_one_dev_pci_data(struct pci_dn *parent,
pdn->pe_number = IODA_INVALID_PE;
INIT_LIST_HEAD(&pdn->child_list);
INIT_LIST_HEAD(&pdn->list);
- list_add_tail(&pdn->list, &parent->child_list);
+ if (parent) {
+ pdn->phb = parent->phb;
+ list_add_tail(&pdn->list, &parent->child_list);
+ }
return pdn;
}
@@ -338,25 +336,29 @@ struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
const __be32 *regs;
struct device_node *parent;
struct pci_dn *pdn;
+ int busno = 0, devfn = 0;
#ifdef CONFIG_EEH
struct eeh_dev *edev;
#endif
- pdn = kzalloc(sizeof(*pdn), GFP_KERNEL);
- if (pdn == NULL)
- return NULL;
- dn->data = pdn;
- pdn->phb = hose;
- pdn->pe_number = IODA_INVALID_PE;
regs = of_get_property(dn, "reg", NULL);
if (regs) {
u32 addr = of_read_number(regs, 1);
/* First register entry is addr (00BBSS00) */
- pdn->busno = (addr >> 16) & 0xff;
- pdn->devfn = (addr >> 8) & 0xff;
+ busno = (addr >> 16) & 0xff;
+ devfn = (addr >> 8) & 0xff;
}
+ parent = of_get_parent(dn);
+ pdn = add_one_dev_pci_data(parent ? PCI_DN(parent) : NULL,
+ 0, busno, devfn);
+ if (!pdn)
+ return NULL;
+
+ dn->data = pdn;
+ pdn->phb = hose;
+
/* vendor/device IDs and class code */
regs = of_get_property(dn, "vendor-id", NULL);
pdn->vendor_id = regs ? of_read_number(regs, 1) : 0;
@@ -377,14 +379,6 @@ struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
}
#endif
- /* Attach to parent node */
- INIT_LIST_HEAD(&pdn->child_list);
- INIT_LIST_HEAD(&pdn->list);
- parent = of_get_parent(dn);
- pdn->parent = parent ? PCI_DN(parent) : NULL;
- if (pdn->parent)
- list_add_tail(&pdn->list, &pdn->parent->child_list);
-
return pdn;
}
EXPORT_SYMBOL_GPL(pci_add_device_node_info);
--
2.17.1
^ permalink raw reply related
* [PATCH v10 0/5] powerpc/pseries: Machine check handler improvements.
From: Mahesh J Salgaonkar @ 2018-09-11 14:26 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michal Suchanek, Michael Ellerman, Nicholas Piggin,
Aneesh Kumar K.V, Michal Suchanek, Ananth Narayan,
Nicholas Piggin, Aneesh Kumar K.V, Laurent Dufour
This patch series includes some improvement to Machine check handler
for pSeries. This patch series drops the sysctl knob patch that was
proposed in v7. The SLB recovery code now uses flush_and_reload_slb()
from mce_power.c.
Patch 1 defines MCE error event section.
Patch 2 implements a real mode mce handler and flushes the SLBs on SLB error.
Patch 3 display's the MCE error details on console.
Patch 4 saves and dumps the SLB contents on SLB MCE errors to improve the
debugability.
Patch 5 consolidates mce early real mode handling code.
Change in v10:
- Rebase to 4.19.0-rc2. Patch 4 now applies cleanly.
Change in V9:
- Move mce_exceptions counting to powernv's virtual mode handler.
- Recover from ERAT errors.
- Minor changes to fix few warnings/checks from checkpatch.pl
Change in V8:
- Move mce error log structure definition to ras.c
- Use flush_and_reload_slb() from mce_power.c.
- Limit the slb saving to single level of mce recursion.
- Move mce_faulty_slbs and slb_save_cache_ptr under CONFIG_PPC_BOOK3S_64
instead of CONFIG_PPC_PSERIES.
- Drop the sysctl knob patch.
Change in V7:
- Fold Michal's patch into patch 5
- Handle MSR_RI=0 and evil context case in MC handler in patch 5.
- Patch 7: Print slb cache ptr value and slb cache data.
- Move patch 8 to patch 9.
- Introduce patch 8 add sysctl knob for recovery action on recovered MCEs.
Change in V6:
- Introduce patch 8 to consolidate early real mode handling code.
- Address Nick's comment on erroneous hunk.
Change in V5:
- Use min_t instead of max_t.
- Fix an issue reported by kbuild test robot and address review comments.
Change in V4:
- Flush the SLBs in real mode mce handler to handle SLB errors for entry 0.
- Allocate buffers per cpu to hold rtas error log and old slb contents.
- Defer the logging of rtas error log to irq work queue.
Change in V3:
- Moved patch 5 to patch 2
Change in V2:
- patch 3: Display additional info (NIP and task info) in MCE error details.
- patch 5: Fix endain bug while restoring of r3 in MCE handler.
---
Mahesh Salgaonkar (5):
powerpc/pseries: Define MCE error event section.
powerpc/pseries: flush SLB contents on SLB MCE errors.
powerpc/pseries: Display machine check error details.
powerpc/pseries: Dump the SLB contents on SLB MCE errors.
powernv/pseries: consolidate code for mce early handling.
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 7 +
arch/powerpc/include/asm/machdep.h | 1
arch/powerpc/include/asm/mce.h | 3
arch/powerpc/include/asm/paca.h | 6
arch/powerpc/include/asm/rtas.h | 13 +
arch/powerpc/kernel/exceptions-64s.S | 42 +++
arch/powerpc/kernel/mce.c | 9 -
arch/powerpc/kernel/mce_power.c | 2
arch/powerpc/mm/slb.c | 70 ++++++
arch/powerpc/platforms/powernv/opal.c | 2
arch/powerpc/platforms/powernv/setup.c | 11 +
arch/powerpc/platforms/pseries/pseries.h | 1
arch/powerpc/platforms/pseries/ras.c | 303 +++++++++++++++++++++++++
arch/powerpc/platforms/pseries/setup.c | 14 +
14 files changed, 472 insertions(+), 12 deletions(-)
--
-Mahesh.
^ permalink raw reply
* [PATCH v10 1/5] powerpc/pseries: Define MCE error event section.
From: Mahesh J Salgaonkar @ 2018-09-11 14:26 UTC (permalink / raw)
To: linuxppc-dev
Cc: Michal Suchanek, Ananth Narayan, Nicholas Piggin,
Aneesh Kumar K.V, Laurent Dufour
In-Reply-To: <153667588649.24785.4453485245076541196.stgit@jupiter.in.ibm.com>
From: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
On pseries, the machine check error details are part of RTAS extended
event log passed under Machine check exception section. This patch adds
the definition of rtas MCE event section and related helper
functions.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
---
---
arch/powerpc/include/asm/rtas.h | 8 +++
arch/powerpc/platforms/pseries/ras.c | 95 ++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 71e393c46a49..adefa6493d29 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -185,6 +185,13 @@ static inline uint8_t rtas_error_disposition(const struct rtas_error_log *elog)
return (elog->byte1 & 0x18) >> 3;
}
+static inline
+void rtas_set_disposition_recovered(struct rtas_error_log *elog)
+{
+ elog->byte1 &= ~0x18;
+ elog->byte1 |= (RTAS_DISP_FULLY_RECOVERED << 3);
+}
+
static inline uint8_t rtas_error_extended(const struct rtas_error_log *elog)
{
return (elog->byte1 & 0x04) >> 2;
@@ -275,6 +282,7 @@ inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log)
#define PSERIES_ELOG_SECT_ID_CALL_HOME (('C' << 8) | 'H')
#define PSERIES_ELOG_SECT_ID_USER_DEF (('U' << 8) | 'D')
#define PSERIES_ELOG_SECT_ID_HOTPLUG (('H' << 8) | 'P')
+#define PSERIES_ELOG_SECT_ID_MCE (('M' << 8) | 'C')
/* Vendor specific Platform Event Log Format, Version 6, section header */
struct pseries_errorlog {
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index 851ce326874a..3500ad982706 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -50,6 +50,101 @@ static irqreturn_t ras_hotplug_interrupt(int irq, void *dev_id);
static irqreturn_t ras_epow_interrupt(int irq, void *dev_id);
static irqreturn_t ras_error_interrupt(int irq, void *dev_id);
+/* RTAS pseries MCE errorlog section. */
+struct pseries_mc_errorlog {
+ __be32 fru_id;
+ __be32 proc_id;
+ u8 error_type;
+ /*
+ * sub_err_type (1 byte). Bit fields depends on error_type
+ *
+ * MSB0
+ * |
+ * V
+ * 01234567
+ * XXXXXXXX
+ *
+ * For error_type == MC_ERROR_TYPE_UE
+ * XXXXXXXX
+ * X 1: Permanent or Transient UE.
+ * X 1: Effective address provided.
+ * X 1: Logical address provided.
+ * XX 2: Reserved.
+ * XXX 3: Type of UE error.
+ *
+ * For error_type != MC_ERROR_TYPE_UE
+ * XXXXXXXX
+ * X 1: Effective address provided.
+ * XXXXX 5: Reserved.
+ * XX 2: Type of SLB/ERAT/TLB error.
+ */
+ u8 sub_err_type;
+ u8 reserved_1[6];
+ __be64 effective_address;
+ __be64 logical_address;
+} __packed;
+
+/* RTAS pseries MCE error types */
+#define MC_ERROR_TYPE_UE 0x00
+#define MC_ERROR_TYPE_SLB 0x01
+#define MC_ERROR_TYPE_ERAT 0x02
+#define MC_ERROR_TYPE_TLB 0x04
+#define MC_ERROR_TYPE_D_CACHE 0x05
+#define MC_ERROR_TYPE_I_CACHE 0x07
+
+/* RTAS pseries MCE error sub types */
+#define MC_ERROR_UE_INDETERMINATE 0
+#define MC_ERROR_UE_IFETCH 1
+#define MC_ERROR_UE_PAGE_TABLE_WALK_IFETCH 2
+#define MC_ERROR_UE_LOAD_STORE 3
+#define MC_ERROR_UE_PAGE_TABLE_WALK_LOAD_STORE 4
+
+#define MC_ERROR_SLB_PARITY 0
+#define MC_ERROR_SLB_MULTIHIT 1
+#define MC_ERROR_SLB_INDETERMINATE 2
+
+#define MC_ERROR_ERAT_PARITY 1
+#define MC_ERROR_ERAT_MULTIHIT 2
+#define MC_ERROR_ERAT_INDETERMINATE 3
+
+#define MC_ERROR_TLB_PARITY 1
+#define MC_ERROR_TLB_MULTIHIT 2
+#define MC_ERROR_TLB_INDETERMINATE 3
+
+static inline u8 rtas_mc_error_sub_type(const struct pseries_mc_errorlog *mlog)
+{
+ switch (mlog->error_type) {
+ case MC_ERROR_TYPE_UE:
+ return (mlog->sub_err_type & 0x07);
+ case MC_ERROR_TYPE_SLB:
+ case MC_ERROR_TYPE_ERAT:
+ case MC_ERROR_TYPE_TLB:
+ return (mlog->sub_err_type & 0x03);
+ default:
+ return 0;
+ }
+}
+
+static
+inline u64 rtas_mc_get_effective_addr(const struct pseries_mc_errorlog *mlog)
+{
+ __be64 addr = 0;
+
+ switch (mlog->error_type) {
+ case MC_ERROR_TYPE_UE:
+ if (mlog->sub_err_type & 0x40)
+ addr = mlog->effective_address;
+ break;
+ case MC_ERROR_TYPE_SLB:
+ case MC_ERROR_TYPE_ERAT:
+ case MC_ERROR_TYPE_TLB:
+ if (mlog->sub_err_type & 0x80)
+ addr = mlog->effective_address;
+ default:
+ break;
+ }
+ return be64_to_cpu(addr);
+}
/*
* Enable the hotplug interrupt late because processing them may touch other
^ permalink raw reply related
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