* [PATCH v2 19/24] powerpc/nohash/64: do not include pte-common.h
From: Christophe Leroy @ 2018-09-12 15:58 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
nohash/64 only uses book3e PTE flags, so it doesn't need pte-common.h
This also allows to drop PAGE_SAO and H_PAGE_4K_PFN from pte_common.h
as they are only used by PPC64
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/nohash/64/pgtable.h | 16 ++++++++++++-
arch/powerpc/include/asm/nohash/pgtable.h | 27 +++++++++++++++++++++
arch/powerpc/include/asm/pte-common.h | 35 ----------------------------
3 files changed, 42 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index b7d65d4b61be..9ccea94b3d4e 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -89,7 +89,21 @@
* Include the PTE bits definitions
*/
#include <asm/nohash/pte-book3e.h>
-#include <asm/pte-common.h>
+
+#define _PAGE_HWWRITE 0
+#define _PAGE_SAO 0
+#define _PAGE_RO 0
+#define _PAGE_NA 0
+#define _PAGE_HUGE 0
+
+#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
+
+/* _PAGE_CHG_MASK masks of bits that are to be preserved across
+ * pgprot changes
+ */
+#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPECIAL)
+
+#define H_PAGE_4K_PFN 0
#ifndef __ASSEMBLY__
/* pte_clear moved to later in this file */
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h b/arch/powerpc/include/asm/nohash/pgtable.h
index a4c31b829071..897f110139c2 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -8,6 +8,33 @@
#include <asm/nohash/32/pgtable.h>
#endif
+/* Permission masks used for kernel mappings */
+#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
+#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | _PAGE_NO_CACHE)
+#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
+ _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
+#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
+#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
+
+/* Protection used for kernel text. We want the debuggers to be able to
+ * set breakpoints anywhere, so don't write protect the kernel text
+ * on platforms where such control is possible.
+ */
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
+ defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
+#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
+#else
+#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
+#endif
+
+/* Make modules code happy. We don't set RO yet */
+#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
+
+/* Advertise special mapping type for AGP */
+#define PAGE_AGP (PAGE_KERNEL_NC)
+#define HAVE_PAGE_AGP
+
#ifndef __ASSEMBLY__
/* Generic accessors to PTE bits */
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index cce60b3ba7d4..4d594039bca5 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -14,9 +14,6 @@
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU 0
#endif
-#ifndef _PAGE_SAO
-#define _PAGE_SAO 0
-#endif
/* _PAGE_RO and _PAGE_RW shall not be defined at the same time */
#ifndef _PAGE_RO
#define _PAGE_RO 0
@@ -61,35 +58,3 @@
*/
#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_DIRTY | \
_PAGE_ACCESSED | _PAGE_SPECIAL)
-
-/* Permission masks used for kernel mappings */
-#define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
-#define PAGE_KERNEL_NC __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
- _PAGE_NO_CACHE)
-#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
- _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
-#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
-#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
-
-/* Protection used for kernel text. We want the debuggers to be able to
- * set breakpoints anywhere, so don't write protect the kernel text
- * on platforms where such control is possible.
- */
-#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
- defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
-#define PAGE_KERNEL_TEXT PAGE_KERNEL_X
-#else
-#define PAGE_KERNEL_TEXT PAGE_KERNEL_ROX
-#endif
-
-/* Make modules code happy. We don't set RO yet */
-#define PAGE_KERNEL_EXEC PAGE_KERNEL_X
-
-/* Advertise special mapping type for AGP */
-#define PAGE_AGP (PAGE_KERNEL_NC)
-#define HAVE_PAGE_AGP
-
-#ifndef H_PAGE_4K_PFN
-#define H_PAGE_4K_PFN 0
-#endif
--
2.13.3
^ permalink raw reply related
* [PATCH v2 20/24] powerpc/mm: Allow platforms to redefine some helpers
From: Christophe Leroy @ 2018-09-12 15:58 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
The 40xx defines _PAGE_HWWRITE while others don't.
The 8xx defines _PAGE_RO instead of _PAGE_RW.
The 8xx defines _PAGE_PRIVILEGED instead of _PAGE_USER.
The 8xx defines _PAGE_HUGE and _PAGE_NA while others don't.
Lets those platforms redefine pte_write(), pte_wrprotect() and
pte_mkwrite() and get _PAGE_RO and _PAGE_HWWRITE off the common
helpers.
Lets the 8xx redefine pte_user(), pte_mkprivileged() and pte_mkuser()
and get rid of _PAGE_PRIVILEGED and _PAGE_USER default values.
Lets the 8xx redefine pte_mkhuge() and get rid of
_PAGE_HUGE default value.
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 16 ++++-----
arch/powerpc/include/asm/nohash/32/pte-40x.h | 16 +++++++++
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 51 ++++++++++++++++++++++++++++
arch/powerpc/include/asm/nohash/64/pgtable.h | 4 ---
arch/powerpc/include/asm/nohash/pgtable.h | 24 +++++++++----
arch/powerpc/include/asm/pte-common.h | 24 -------------
6 files changed, 91 insertions(+), 44 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index a4156da4a7a4..ce9270a0ea42 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -136,14 +136,12 @@ extern int icache_44x_need_flush;
#define pte_clear(mm, addr, ptep) \
do { pte_update(ptep, ~0, 0); } while (0)
+#ifndef pte_mkwrite
static inline pte_t pte_mkwrite(pte_t pte)
{
- pte_basic_t ptev;
-
- ptev = pte_val(pte) & ~_PAGE_RO;
- ptev |= _PAGE_RW;
- return __pte(ptev);
+ return __pte(pte_val(pte) | _PAGE_RW);
}
+#endif
static inline pte_t pte_mkdirty(pte_t pte)
{
@@ -155,14 +153,12 @@ static inline pte_t pte_mkyoung(pte_t pte)
return __pte(pte_val(pte) | _PAGE_ACCESSED);
}
+#ifndef pte_wrprotect
static inline pte_t pte_wrprotect(pte_t pte)
{
- pte_basic_t ptev;
-
- ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE);
- ptev |= _PAGE_RO;
- return __pte(ptev);
+ return __pte(pte_val(pte) & ~_PAGE_RW);
}
+#endif
static inline pte_t pte_mkexec(pte_t pte)
{
diff --git a/arch/powerpc/include/asm/nohash/32/pte-40x.h b/arch/powerpc/include/asm/nohash/32/pte-40x.h
index 2b48bc289a4d..ab043b3e9b99 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-40x.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-40x.h
@@ -87,5 +87,21 @@
#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#ifndef __ASSEMBLY__
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE));
+}
+
+#define pte_wrprotect pte_wrprotect
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
+}
+
+#define pte_mkclean pte_mkclean
+#endif
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index d06fc45bd9ac..b899c3c877ac 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -87,5 +87,56 @@
#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_RO)
#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
+#ifndef __ASSEMBLY__
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_RO);
+}
+
+#define pte_wrprotect pte_wrprotect
+
+static inline int pte_write(pte_t pte)
+{
+ return !(pte_val(pte) & _PAGE_RO);
+}
+
+#define pte_write pte_write
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~_PAGE_RO);
+}
+
+#define pte_mkwrite pte_mkwrite
+
+static inline bool pte_user(pte_t pte)
+{
+ return !(pte_val(pte) & _PAGE_PRIVILEGED);
+}
+
+#define pte_user pte_user
+
+static inline pte_t pte_mkprivileged(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
+}
+
+#define pte_mkprivileged pte_mkprivileged
+
+static inline pte_t pte_mkuser(pte_t pte)
+{
+ return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
+}
+
+#define pte_mkuser pte_mkuser
+
+static inline pte_t pte_mkhuge(pte_t pte)
+{
+ return __pte(pte_val(pte) | _PAGE_HUGE);
+}
+
+#define pte_mkhuge pte_mkhuge
+#endif
+
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index 9ccea94b3d4e..f272e4599803 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -90,11 +90,7 @@
*/
#include <asm/nohash/pte-book3e.h>
-#define _PAGE_HWWRITE 0
#define _PAGE_SAO 0
-#define _PAGE_RO 0
-#define _PAGE_NA 0
-#define _PAGE_HUGE 0
#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h b/arch/powerpc/include/asm/nohash/pgtable.h
index 897f110139c2..aa968d87337b 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -38,10 +38,12 @@
#ifndef __ASSEMBLY__
/* Generic accessors to PTE bits */
+#ifndef pte_write
static inline int pte_write(pte_t pte)
{
- return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO;
+ return pte_val(pte) & _PAGE_RW;
}
+#endif
static inline int pte_read(pte_t pte) { return 1; }
static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
@@ -78,10 +80,12 @@ static inline int pte_present(pte_t pte)
* and PTE_64BIT, PAGE_KERNEL_X contains _PAGE_BAP_SR which is also in
* _PAGE_USER. Need to explicitly match _PAGE_BAP_UR bit in that case too.
*/
+#ifndef pte_user
static inline bool pte_user(pte_t pte)
{
- return (pte_val(pte) & (_PAGE_USER | _PAGE_PRIVILEGED)) == _PAGE_USER;
+ return (pte_val(pte) & _PAGE_USER) == _PAGE_USER;
}
+#endif
/*
* We only find page table entry in the last level
@@ -121,10 +125,12 @@ static inline pte_t pte_exprotect(pte_t pte)
return __pte(pte_val(pte) & ~_PAGE_EXEC);
}
+#ifndef pte_mkclean
static inline pte_t pte_mkclean(pte_t pte)
{
- return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
+ return __pte(pte_val(pte) & ~_PAGE_DIRTY);
}
+#endif
static inline pte_t pte_mkold(pte_t pte)
{
@@ -141,20 +147,26 @@ static inline pte_t pte_mkspecial(pte_t pte)
return __pte(pte_val(pte) | _PAGE_SPECIAL);
}
+#ifndef pte_mkhuge
static inline pte_t pte_mkhuge(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_HUGE);
+ return __pte(pte_val(pte));
}
+#endif
+#ifndef pte_mkprivileged
static inline pte_t pte_mkprivileged(pte_t pte)
{
- return __pte((pte_val(pte) & ~_PAGE_USER) | _PAGE_PRIVILEGED);
+ return __pte(pte_val(pte) & ~_PAGE_USER);
}
+#endif
+#ifndef pte_mkuser
static inline pte_t pte_mkuser(pte_t pte)
{
- return __pte((pte_val(pte) & ~_PAGE_PRIVILEGED) | _PAGE_USER);
+ return __pte(pte_val(pte) | _PAGE_USER);
}
+#endif
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index 4d594039bca5..1a2102f8b1e7 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -5,36 +5,12 @@
* Some bits are only used on some cpu families... Make sure that all
* the undefined gets a sensible default
*/
-#ifndef _PAGE_HWWRITE
-#define _PAGE_HWWRITE 0
-#endif
#ifndef _PAGE_COHERENT
#define _PAGE_COHERENT 0
#endif
#ifndef _PAGE_WRITETHRU
#define _PAGE_WRITETHRU 0
#endif
-/* _PAGE_RO and _PAGE_RW shall not be defined at the same time */
-#ifndef _PAGE_RO
-#define _PAGE_RO 0
-#else
-#define _PAGE_RW 0
-#endif
-
-/* At least one of _PAGE_PRIVILEGED or _PAGE_USER must be defined */
-#ifndef _PAGE_PRIVILEGED
-#define _PAGE_PRIVILEGED 0
-#else
-#ifndef _PAGE_USER
-#define _PAGE_USER 0
-#endif
-#endif
-#ifndef _PAGE_NA
-#define _PAGE_NA 0
-#endif
-#ifndef _PAGE_HUGE
-#define _PAGE_HUGE 0
-#endif
/* Location of the PFN in the PTE. Most 32-bit platforms use the same
* as _PAGE_SHIFT here (ie, naturally aligned).
--
2.13.3
^ permalink raw reply related
* [PATCH v2 21/24] powerpc/mm: Define platform default caches related flags
From: Christophe Leroy @ 2018-09-12 15:58 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
Cache related flags like _PAGE_COHERENT and _PAGE_WRITETHRU
are defined on most platforms. The platforms not defining
them don't define any alternative. So we can give them a NUL
value directly for those platforms directly.
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/nohash/32/pte-40x.h | 3 +++
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 4 ++++
arch/powerpc/include/asm/pte-common.h | 11 -----------
3 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pte-40x.h b/arch/powerpc/include/asm/nohash/32/pte-40x.h
index ab043b3e9b99..7a8b3c94592f 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-40x.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-40x.h
@@ -53,6 +53,9 @@
/* No page size encoding in the linux PTE */
#define _PAGE_PSIZE 0
+/* cache related flags non existing on 40x */
+#define _PAGE_COHERENT 0
+
#define _PAGE_KERNEL_RO 0
#define _PAGE_KERNEL_ROX _PAGE_EXEC
#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index b899c3c877ac..2b4669b3badb 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -46,6 +46,10 @@
#define _PAGE_NA 0x0200 /* Supervisor NA, User no access */
#define _PAGE_RO 0x0600 /* Supervisor RO, User no access */
+/* cache related flags non existing on 8xx */
+#define _PAGE_COHERENT 0
+#define _PAGE_WRITETHRU 0
+
#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_RO)
#define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_RO | _PAGE_EXEC)
#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_DIRTY)
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
index 1a2102f8b1e7..ff01368a175a 100644
--- a/arch/powerpc/include/asm/pte-common.h
+++ b/arch/powerpc/include/asm/pte-common.h
@@ -1,17 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Included from asm/pgtable-*.h only ! */
-/*
- * Some bits are only used on some cpu families... Make sure that all
- * the undefined gets a sensible default
- */
-#ifndef _PAGE_COHERENT
-#define _PAGE_COHERENT 0
-#endif
-#ifndef _PAGE_WRITETHRU
-#define _PAGE_WRITETHRU 0
-#endif
-
/* Location of the PFN in the PTE. Most 32-bit platforms use the same
* as _PAGE_SHIFT here (ie, naturally aligned).
* Platform who don't just pre-define the value so we don't override it here
--
2.13.3
^ permalink raw reply related
* [PATCH v2 22/24] powerpc/mm: Get rid of pte-common.h
From: Christophe Leroy @ 2018-09-12 15:58 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
Do not include pte-common.h in nohash/32/pgtable.h
As that was the last includer, get rid of pte-common.h
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/nohash/32/pgtable.h | 23 +++++++++++++++++++++--
arch/powerpc/include/asm/pte-common.h | 25 -------------------------
2 files changed, 21 insertions(+), 27 deletions(-)
delete mode 100644 arch/powerpc/include/asm/pte-common.h
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index ce9270a0ea42..d2908a8038e8 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -128,8 +128,27 @@ extern int icache_44x_need_flush;
#include <asm/nohash/32/pte-8xx.h>
#endif
-/* And here we include common definitions */
-#include <asm/pte-common.h>
+/* Location of the PFN in the PTE. Most 32-bit platforms use the same
+ * as _PAGE_SHIFT here (ie, naturally aligned).
+ * Platform who don't just pre-define the value so we don't override it here
+ */
+#ifndef PTE_RPN_SHIFT
+#define PTE_RPN_SHIFT (PAGE_SHIFT)
+#endif
+
+/* The mask covered by the RPN must be a ULL on 32-bit platforms with
+ * 64-bit PTEs
+ */
+#if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
+#define PTE_RPN_MASK (~((1ULL << PTE_RPN_SHIFT) - 1))
+#else
+#define PTE_RPN_MASK (~((1UL << PTE_RPN_SHIFT) - 1))
+#endif
+
+/* _PAGE_CHG_MASK masks of bits that are to be preserved across
+ * pgprot changes
+ */
+#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPECIAL)
#ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/pte-common.h b/arch/powerpc/include/asm/pte-common.h
deleted file mode 100644
index ff01368a175a..000000000000
--- a/arch/powerpc/include/asm/pte-common.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Included from asm/pgtable-*.h only ! */
-
-/* Location of the PFN in the PTE. Most 32-bit platforms use the same
- * as _PAGE_SHIFT here (ie, naturally aligned).
- * Platform who don't just pre-define the value so we don't override it here
- */
-#ifndef PTE_RPN_SHIFT
-#define PTE_RPN_SHIFT (PAGE_SHIFT)
-#endif
-
-/* The mask covered by the RPN must be a ULL on 32-bit platforms with
- * 64-bit PTEs
- */
-#if defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
-#define PTE_RPN_MASK (~((1ULL<<PTE_RPN_SHIFT)-1))
-#else
-#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))
-#endif
-
-/* _PAGE_CHG_MASK masks of bits that are to be preserved across
- * pgprot changes
- */
-#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_DIRTY | \
- _PAGE_ACCESSED | _PAGE_SPECIAL)
--
2.13.3
^ permalink raw reply related
* [PATCH v2 23/24] powerpc/8xx: change name of a few page flags to avoid confusion
From: Christophe Leroy @ 2018-09-12 15:59 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
_PAGE_PRIVILEGED corresponds to the SH bit which doesn't protect
against user access but only disables ASID verification on kernel
accesses. User access is controlled with _PMD_USER flag.
Name it _PAGE_SH instead of _PAGE_PRIVILEGED
_PAGE_HUGE corresponds to the SPS bit which doesn't really tells
that's it is a huge page but only that it is not a 4k page.
Name it _PAGE_SPS instead of _PAGE_HUGE
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 28 ++++++++++++++--------------
arch/powerpc/kernel/head_8xx.S | 6 +++---
arch/powerpc/mm/8xx_mmu.c | 2 +-
arch/powerpc/mm/dump_linuxpagetables-8xx.c | 2 +-
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
index 2b4669b3badb..1c57efac089d 100644
--- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
@@ -29,10 +29,10 @@
*/
/* Definitions for 8xx embedded chips. */
-#define _PAGE_PRESENT 0x0001 /* Page is valid */
-#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
-#define _PAGE_PRIVILEGED 0x0004 /* No ASID (context) compare */
-#define _PAGE_HUGE 0x0008 /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
+#define _PAGE_PRESENT 0x0001 /* V: Page is valid */
+#define _PAGE_NO_CACHE 0x0002 /* CI: cache inhibit */
+#define _PAGE_SH 0x0004 /* SH: No ASID (context) compare */
+#define _PAGE_SPS 0x0008 /* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
#define _PAGE_DIRTY 0x0100 /* C: page changed */
/* These 4 software bits must be masked out when the L2 entry is loaded
@@ -50,15 +50,15 @@
#define _PAGE_COHERENT 0
#define _PAGE_WRITETHRU 0
-#define _PAGE_KERNEL_RO (_PAGE_PRIVILEGED | _PAGE_RO)
-#define _PAGE_KERNEL_ROX (_PAGE_PRIVILEGED | _PAGE_RO | _PAGE_EXEC)
-#define _PAGE_KERNEL_RW (_PAGE_PRIVILEGED | _PAGE_DIRTY)
-#define _PAGE_KERNEL_RWX (_PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_EXEC)
+#define _PAGE_KERNEL_RO (_PAGE_SH | _PAGE_RO)
+#define _PAGE_KERNEL_ROX (_PAGE_SH | _PAGE_RO | _PAGE_EXEC)
+#define _PAGE_KERNEL_RW (_PAGE_SH | _PAGE_DIRTY)
+#define _PAGE_KERNEL_RWX (_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
/* Mask of bits returned by pte_pgprot() */
#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_NO_CACHE | \
_PAGE_ACCESSED | _PAGE_RO | _PAGE_NA | \
- _PAGE_PRIVILEGED | _PAGE_DIRTY | _PAGE_EXEC)
+ _PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
#define _PMD_PRESENT 0x0001
#define _PMD_PRESENT_MASK _PMD_PRESENT
@@ -74,7 +74,7 @@
#define PTE_ATOMIC_UPDATES 1
#ifdef CONFIG_PPC_16K_PAGES
-#define _PAGE_PSIZE _PAGE_HUGE
+#define _PAGE_PSIZE _PAGE_SPS
#else
#define _PAGE_PSIZE 0
#endif
@@ -115,28 +115,28 @@ static inline pte_t pte_mkwrite(pte_t pte)
static inline bool pte_user(pte_t pte)
{
- return !(pte_val(pte) & _PAGE_PRIVILEGED);
+ return !(pte_val(pte) & _PAGE_SH);
}
#define pte_user pte_user
static inline pte_t pte_mkprivileged(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
+ return __pte(pte_val(pte) | _PAGE_SH);
}
#define pte_mkprivileged pte_mkprivileged
static inline pte_t pte_mkuser(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
+ return __pte(pte_val(pte) & ~_PAGE_SH);
}
#define pte_mkuser pte_mkuser
static inline pte_t pte_mkhuge(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_HUGE);
+ return __pte(pte_val(pte) | _PAGE_SPS);
}
#define pte_mkhuge pte_mkhuge
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 6582f824d620..134a573a9f2d 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -642,7 +642,7 @@ DTLBMissIMMR:
mtspr SPRN_MD_TWC, r10
mfspr r10, SPRN_IMMR /* Get current IMMR */
rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
- ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
+ ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
_PAGE_PRESENT | _PAGE_NO_CACHE
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -660,7 +660,7 @@ DTLBMissLinear:
li r11, MD_PS8MEG | MD_SVALID | M_APG2
mtspr SPRN_MD_TWC, r11
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
- ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
+ ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
_PAGE_PRESENT
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -679,7 +679,7 @@ ITLBMissLinear:
li r11, MI_PS8MEG | MI_SVALID | M_APG2
mtspr SPRN_MI_TWC, r11
rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
- ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
+ ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
_PAGE_PRESENT
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c
index 9137361d687d..36484a2ef915 100644
--- a/arch/powerpc/mm/8xx_mmu.c
+++ b/arch/powerpc/mm/8xx_mmu.c
@@ -67,7 +67,7 @@ void __init MMU_init_hw(void)
/* PIN up to the 3 first 8Mb after IMMR in DTLB table */
#ifdef CONFIG_PIN_TLB_DATA
unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
- unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY;
+ unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY;
#ifdef CONFIG_PIN_TLB_IMMR
int i = 29;
#else
diff --git a/arch/powerpc/mm/dump_linuxpagetables-8xx.c b/arch/powerpc/mm/dump_linuxpagetables-8xx.c
index 33f52a97975b..ab9e3f24db2f 100644
--- a/arch/powerpc/mm/dump_linuxpagetables-8xx.c
+++ b/arch/powerpc/mm/dump_linuxpagetables-8xx.c
@@ -11,7 +11,7 @@
static const struct flag_info flag_array[] = {
{
- .mask = _PAGE_PRIVILEGED,
+ .mask = _PAGE_SH,
.val = 0,
.set = "user",
.clear = " ",
--
2.13.3
^ permalink raw reply related
* [PATCH v2 24/24] powerpc/book3s64: Avoid multiple endian conversion in pte helpers
From: Christophe Leroy @ 2018-09-12 15:59 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Benjamin Herrenschmidt,
Dominik Brodowski, Geoff Levand, Jens Axboe, Kumar Gala, Li Yang,
Michael Ellerman, Nicholas Piggin, Paul Mackerras, Scott Wood,
aneesh.kumar
Cc: linux-arm-kernel, linux-block, linux-fbdev, linux-kernel,
linuxppc-dev, dri-devel
In-Reply-To: <cover.1536692743.git.christophe.leroy@c-s.fr>
In the same spirit as already done in pte query helpers,
this patch changes pte setting helpers to perform endian
conversions on the constants rather than on the pte value.
In the meantime, it changes pte_access_permitted() to use
pte helpers for the same reason.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/include/asm/book3s/64/pgtable.h | 71 +++++++++++++---------------
1 file changed, 32 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 6799bc02cb22..7e29bda0944e 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -506,12 +506,12 @@ static inline bool pte_soft_dirty(pte_t pte)
static inline pte_t pte_mksoft_dirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SOFT_DIRTY));
}
static inline pte_t pte_clear_soft_dirty(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SOFT_DIRTY));
}
#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
@@ -532,7 +532,7 @@ static inline pte_t pte_mk_savedwrite(pte_t pte)
*/
VM_BUG_ON((pte_raw(pte) & cpu_to_be64(_PAGE_PRESENT | _PAGE_RWX | _PAGE_PRIVILEGED)) !=
cpu_to_be64(_PAGE_PRESENT | _PAGE_PRIVILEGED));
- return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED));
}
#define pte_clear_savedwrite pte_clear_savedwrite
@@ -542,14 +542,14 @@ static inline pte_t pte_clear_savedwrite(pte_t pte)
* Used by KSM subsystem to make a protnone pte readonly.
*/
VM_BUG_ON(!pte_protnone(pte));
- return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED));
}
#else
#define pte_clear_savedwrite pte_clear_savedwrite
static inline pte_t pte_clear_savedwrite(pte_t pte)
{
VM_WARN_ON(1);
- return __pte(pte_val(pte) & ~_PAGE_WRITE);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
}
#endif /* CONFIG_NUMA_BALANCING */
@@ -573,25 +573,22 @@ static inline bool arch_pte_access_permitted(u64 pte, bool write, bool execute)
}
#endif /* CONFIG_PPC_MEM_KEYS */
+static inline bool pte_user(pte_t pte)
+{
+ return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
+}
+
#define pte_access_permitted pte_access_permitted
static inline bool pte_access_permitted(pte_t pte, bool write)
{
- unsigned long pteval = pte_val(pte);
- /* Also check for pte_user */
- unsigned long clear_pte_bits = _PAGE_PRIVILEGED;
/*
* _PAGE_READ is needed for any access and will be
* cleared for PROT_NONE
*/
- unsigned long need_pte_bits = _PAGE_PRESENT | _PAGE_READ;
-
- if (write)
- need_pte_bits |= _PAGE_WRITE;
-
- if ((pteval & need_pte_bits) != need_pte_bits)
+ if (!pte_present(pte) || !pte_user(pte) || !pte_read(pte))
return false;
- if ((pteval & clear_pte_bits) == clear_pte_bits)
+ if (write && !pte_write(pte))
return false;
return arch_pte_access_permitted(pte_val(pte), write, 0);
@@ -620,32 +617,32 @@ static inline pte_t pte_wrprotect(pte_t pte)
{
if (unlikely(pte_savedwrite(pte)))
return pte_clear_savedwrite(pte);
- return __pte(pte_val(pte) & ~_PAGE_WRITE);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_WRITE));
}
static inline pte_t pte_exprotect(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_EXEC);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_EXEC));
}
static inline pte_t pte_mkclean(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_DIRTY);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_DIRTY));
}
static inline pte_t pte_mkold(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_ACCESSED));
}
static inline pte_t pte_mkexec(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_EXEC);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_EXEC));
}
static inline pte_t pte_mkpte(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_PTE);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PTE));
}
static inline pte_t pte_mkwrite(pte_t pte)
@@ -653,22 +650,22 @@ static inline pte_t pte_mkwrite(pte_t pte)
/*
* write implies read, hence set both
*/
- return __pte(pte_val(pte) | _PAGE_RW);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_RW));
}
static inline pte_t pte_mkdirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
}
static inline pte_t pte_mkyoung(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_ACCESSED);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_ACCESSED));
}
static inline pte_t pte_mkspecial(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_SPECIAL);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL));
}
static inline pte_t pte_mkhuge(pte_t pte)
@@ -678,17 +675,17 @@ static inline pte_t pte_mkhuge(pte_t pte)
static inline pte_t pte_mkdevmap(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_SPECIAL|_PAGE_DEVMAP);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SPECIAL | _PAGE_DEVMAP));
}
static inline pte_t pte_mkprivileged(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_PRIVILEGED);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_PRIVILEGED));
}
static inline pte_t pte_mkuser(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_PRIVILEGED);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_PRIVILEGED));
}
/*
@@ -707,12 +704,8 @@ static inline int pte_devmap(pte_t pte)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
/* FIXME!! check whether this need to be a conditional */
- return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
-}
-
-static inline bool pte_user(pte_t pte)
-{
- return !(pte_raw(pte) & cpu_to_be64(_PAGE_PRIVILEGED));
+ return __pte_raw((pte_raw(pte) & cpu_to_be64(_PAGE_CHG_MASK)) |
+ cpu_to_be64(pgprot_val(newprot)));
}
/* Encode and de-code a swap entry */
@@ -753,7 +746,7 @@ static inline bool pte_user(pte_t pte)
#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
{
- return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
+ return __pte_raw(pte_raw(pte) | cpu_to_be64(_PAGE_SWP_SOFT_DIRTY));
}
static inline bool pte_swp_soft_dirty(pte_t pte)
@@ -763,7 +756,7 @@ static inline bool pte_swp_soft_dirty(pte_t pte)
static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
{
- return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
+ return __pte_raw(pte_raw(pte) & cpu_to_be64(~_PAGE_SWP_SOFT_DIRTY));
}
#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
@@ -852,10 +845,10 @@ static inline pgprot_t pgprot_writecombine(pgprot_t prot)
*/
static inline bool pte_ci(pte_t pte)
{
- unsigned long pte_v = pte_val(pte);
+ unsigned long pte_v = pte_raw(pte);
- if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||
- ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))
+ if (((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_TOLERANT)) ||
+ ((pte_v & cpu_to_be64(_PAGE_CACHE_CTL)) == cpu_to_be64(_PAGE_NON_IDEMPOTENT)))
return true;
return false;
}
--
2.13.3
^ permalink raw reply related
* Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
From: Mauro Carvalho Chehab @ 2018-09-12 16:01 UTC (permalink / raw)
To: Arnd Bergmann
Cc: viro, linux-fsdevel, Greg Kroah-Hartman, David S. Miller, devel,
linux-kernel, qat-linux, linux-crypto, linux-media, dri-devel,
linaro-mm-sig, amd-gfx, linux-input, linux-iio, linux-rdma,
linux-nvdimm, linux-nvme, linux-pci, platform-driver-x86,
linux-remoteproc, sparclinux, linux-scsi, linux-usb, linux-fbdev,
linuxppc-dev, linux-btrfs, ceph-devel, linux-wireless, netdev
In-Reply-To: <20180912151134.436719-1-arnd@arndb.de>
Em Wed, 12 Sep 2018 17:08:52 +0200
Arnd Bergmann <arnd@arndb.de> escreveu:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>=20
> One exception is the s390 architecture, where a compat pointer is only
> 31 bit wide, and converting it into a 64-bit pointer requires calling
> compat_ptr(). Most drivers here will ever run in s390, but since we now
> have a generic helper for it, it's easy enough to use it consistently.
>=20
> I double-checked all these drivers to ensure that all ioctl arguments
> are used as pointers or are ignored, but are not interpreted as integer
> values.
>=20
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/media/rc/lirc_dev.c | 4 +---
> diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c
> index f862f1b7f996..077209f414ed 100644
> --- a/drivers/media/rc/lirc_dev.c
> +++ b/drivers/media/rc/lirc_dev.c
> @@ -730,9 +730,7 @@ static const struct file_operations lirc_fops =3D {
> .owner =3D THIS_MODULE,
> .write =3D ir_lirc_transmit_ir,
> .unlocked_ioctl =3D ir_lirc_ioctl,
> -#ifdef CONFIG_COMPAT
> - .compat_ioctl =3D ir_lirc_ioctl,
> -#endif
> + .compat_ioctl =3D generic_compat_ioctl_ptrarg,
> .read =3D ir_lirc_read,
> .poll =3D ir_lirc_poll,
> .open =3D ir_lirc_open,
Adding an infrared remote controller to a s390 mainframe sounds fun :-)
I suspect that one could implement it on a s390 platform=20
using gpio-ir-recv and/or gpio-ir-tx drivers. Perhaps one possible
practical usage would be to let the mainframe to send remote
controller codes to adjust the air conditioning system ;-)
=46rom lirc driver's PoV, there's nothing that really prevents one to
do that and use lirc API, and the driver is generic enough to work
on any hardware platform.
I didn't check the implementation of generic_compat_ioctl_ptrarg(),
but assuming it is ok,
Acked-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
Thanks,
Mauro
^ permalink raw reply
* Re: [RFC PATCH v1 00/17] ban the use of _PAGE_XXX flags outside platform specific code
From: Christophe LEROY @ 2018-09-12 16:05 UTC (permalink / raw)
To: Aneesh Kumar K.V, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, npiggin, aneesh.kumar
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <8736uhsx3l.fsf@linux.ibm.com>
Le 10/09/2018 à 08:08, Aneesh Kumar K.V a écrit :
> Christophe Leroy <christophe.leroy@c-s.fr> writes:
>
>> On 09/06/2018 09:58 AM, Aneesh Kumar K.V wrote:
>>> Christophe Leroy <christophe.leroy@c-s.fr> writes:
>>>
>>>> Today flags like for instance _PAGE_RW or _PAGE_USER are used through
>>>> common parts of code.
>>>> Using those directly in common parts of code have proven to lead to
>>>> mistakes or misbehaviour, because their use is not always as trivial
>>>> as one could think.
>>>>
>>>> For instance, (flags & _PAGE_USER) == 0 isn't enough to tell
>>>> that a page is a kernel page, because some targets are using
>>>> _PAGE_PRIVILEDGED and not _PAGE_USER, so the test has to be
>>>> (flags & (_PAGE_USER | _PAGE_PRIVILEDGED)) == _PAGE_PRIVILEDGED
>>>> This has to (bad) consequences:
>>>>
>>>> - All targets must define every bit, even the unsupported ones,
>>>> leading to a lot of useless #define _PAGE_XXX 0
>>>> - If someone forgets to take into account all possible _PAGE_XXX bits
>>>> for the case, we can get unexpected behaviour on some targets.
>>>>
>>>> This becomes even more complex when we come to using _PAGE_RW.
>>>> Testing (flags & _PAGE_RW) is not enough to test whether a page
>>>> if writable or not, because:
>>>>
>>>> - Some targets have _PAGE_RO instead, which has to be unset to tell
>>>> a page is writable
>>>> - Some targets have _PAGE_R and _PAGE_W, in which case
>>>> _PAGE_RW = _PAGE_R | _PAGE_W
>>>> - Even knowing whether a page is readable is not always trivial because:
>>>> - Some targets requires to check that _PAGE_R is set to ensure page
>>>> is readable
>>>> - Some targets requires to check that _PAGE_NA is not set
>>>> - Some targets requires to check that _PAGE_RO or _PAGE_RW is set
>>>>
>>>> Etc ....
>>>>
>>>> In order to work around all those issues and minimise the risks of errors,
>>>> this serie aims at removing all use of _PAGE_XXX flags from powerpc code
>>>> and always use pte_xxx() and pte_mkxxx() accessors instead. Those accessors
>>>> are then defined in target specific parts of the kernel code.
>>>
>>> The series is really good. It also helps in code readability. Few things
>>> i am not sure there is a way to reduce the overhead
>>>
>>> - access = _PAGE_EXEC;
>>> + access = pte_val(pte_mkexec(__pte(0)));
>>>
>>> Considering we have multiple big endian to little endian coversion there
>>> for book3s 64.
>>
>> Thanks for the review.
>>
>> For the above, I propose the following:
>>
>> diff --git a/arch/powerpc/mm/hash_utils_64.c
>> b/arch/powerpc/mm/hash_utils_64.c
>> index f23a89d8e4ce..904ac9c84ea5 100644
>> --- a/arch/powerpc/mm/hash_utils_64.c
>> +++ b/arch/powerpc/mm/hash_utils_64.c
>> @@ -1482,7 +1482,7 @@ static bool should_hash_preload(struct mm_struct
>> *mm, unsigned long ea)
>> #endif
>>
>> void hash_preload(struct mm_struct *mm, unsigned long ea,
>> - unsigned long access, unsigned long trap)
>> + bool is_exec, unsigned long trap)
>> {
>> int hugepage_shift;
>> unsigned long vsid;
>> @@ -1490,6 +1490,7 @@ void hash_preload(struct mm_struct *mm, unsigned
>> long ea,
>> pte_t *ptep;
>> unsigned long flags;
>> int rc, ssize, update_flags = 0;
>> + unsigned long access = is_exec ? _PAGE_EXEC : 0;
>
>
> I guess it will be better if we do
>
> unsigned long access = _PAGE_PRESENT | _PAGE_READ
>
> if (is_exec)
> access |= _PAGE_EXEC.
>
> That will also bring it closer to __hash_page. I agree that we should
> always find _PAGE_PRESENT and _PAGE_READ set, because we just handled
> the page fault.
>
Ok, I did it in v2, can you have a look (patch 11/24) ?
Christophe
^ permalink raw reply
* Re: [RFC PATCH v1 00/17] ban the use of _PAGE_XXX flags outside platform specific code
From: Christophe LEROY @ 2018-09-12 16:07 UTC (permalink / raw)
To: Aneesh Kumar K.V, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman, npiggin, aneesh.kumar
Cc: linux-kernel, linuxppc-dev
In-Reply-To: <8736uneylc.fsf@linux.ibm.com>
Le 06/09/2018 à 11:58, Aneesh Kumar K.V a écrit :
> Christophe Leroy <christophe.leroy@c-s.fr> writes:
>
>> Today flags like for instance _PAGE_RW or _PAGE_USER are used through
>> common parts of code.
>> Using those directly in common parts of code have proven to lead to
>> mistakes or misbehaviour, because their use is not always as trivial
>> as one could think.
>>
>> For instance, (flags & _PAGE_USER) == 0 isn't enough to tell
>> that a page is a kernel page, because some targets are using
>> _PAGE_PRIVILEDGED and not _PAGE_USER, so the test has to be
>> (flags & (_PAGE_USER | _PAGE_PRIVILEDGED)) == _PAGE_PRIVILEDGED
>> This has to (bad) consequences:
>>
>> - All targets must define every bit, even the unsupported ones,
>> leading to a lot of useless #define _PAGE_XXX 0
>> - If someone forgets to take into account all possible _PAGE_XXX bits
>> for the case, we can get unexpected behaviour on some targets.
>>
>> This becomes even more complex when we come to using _PAGE_RW.
>> Testing (flags & _PAGE_RW) is not enough to test whether a page
>> if writable or not, because:
>>
>> - Some targets have _PAGE_RO instead, which has to be unset to tell
>> a page is writable
>> - Some targets have _PAGE_R and _PAGE_W, in which case
>> _PAGE_RW = _PAGE_R | _PAGE_W
>> - Even knowing whether a page is readable is not always trivial because:
>> - Some targets requires to check that _PAGE_R is set to ensure page
>> is readable
>> - Some targets requires to check that _PAGE_NA is not set
>> - Some targets requires to check that _PAGE_RO or _PAGE_RW is set
>>
>> Etc ....
>>
>> In order to work around all those issues and minimise the risks of errors,
>> this serie aims at removing all use of _PAGE_XXX flags from powerpc code
>> and always use pte_xxx() and pte_mkxxx() accessors instead. Those accessors
>> are then defined in target specific parts of the kernel code.
>
> The series is really good. It also helps in code readability. Few things
> i am not sure there is a way to reduce the overhead
>
> - access = _PAGE_EXEC;
> + access = pte_val(pte_mkexec(__pte(0)));
>
> Considering we have multiple big endian to little endian coversion there
> for book3s 64.
>
> Other thing is __ioremap_at where we do
>
> + pte_t pte = __pte(flags);
>
> /* Make sure we have the base flags */
> - if ((flags & _PAGE_PRESENT) == 0)
> + if (!pte_present(pte))
>
> - err = map_kernel_page(v+i, p+i, flags);
> + err = map_kernel_page(v + i, p + i, pte_val(pte));
>
Finally, for that I now ensure that all base flags are set by the
callers and I have removed that hack which adds PAGE_KERNEL flags when
_PAGE_PRESENT is not in the handedover flags.
>
> But otherwise for the series.
>
> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>
Thanks, I added it to all unchanged patches of the serie. You are
welcome to give a feedback on the new ones if you have time.
Christophe
^ permalink raw reply
* Re: [PATCH 0/2] sriov enablement on s390
From: Benjamin Herrenschmidt @ 2018-09-12 14:40 UTC (permalink / raw)
To: Bjorn Helgaas, Sebastian Ott
Cc: Bjorn Helgaas, linux-pci, Arnd Bergmann, Paul Mackerras,
Michael Ellerman, Russell Currey, linuxppc-dev, Oliver OHalloran
In-Reply-To: <20180912130205.GG118330@bhelgaas-glaptop.roam.corp.google.com>
On Wed, 2018-09-12 at 08:02 -0500, Bjorn Helgaas wrote:
> [+cc Arnd, powerpc folks]
[+Oliver]
> On Wed, Sep 12, 2018 at 02:34:09PM +0200, Sebastian Ott wrote:
> > Hello Bjorn,
> >
> > On s390 we currently handle SRIOV within firmware. Which means
> > that the PF is under firmware control and not visible to operating
> > systems. SRIOV enablement happens within firmware and VFs are
> > passed through to logical partitions.
> >
> > I'm working on a new mode were the PF is under operating system
> > control (including SRIOV enablement). However we still need
> > firmware support to access the VFs. The way this is supposed
> > to work is that when firmware traps the SRIOV enablement it
> > will present machine checks to the logical partition that
> > triggered the SRIOV enablement and provide the VFs via hotplug
> > events.
> >
> > The problem I'm faced with is that the VF detection code in
> > sriov_enable leads to unusable functions in s390.
>
> We're moving away from the weak function implementation style. Can
> you take a look at Arnd's work here, which uses pci_host_bridge
> callbacks instead?
>
> https://lkml.kernel.org/r/20180817102645.3839621-1-arnd@arndb.de
>
> I cc'd some powerpc folks because they also have a fair amount of
> arch-specific SR-IOV code that might one day move in this direction.
>
> > Sebastian Ott (2):
> > pci: provide pcibios_sriov_add_vfs
> > s390/pci: handle function enumeration after sriov enablement
> >
> > arch/s390/pci/pci.c | 11 +++++++++++
> > drivers/pci/iov.c | 43 +++++++++++++++++++++++++++++++------------
> > include/linux/pci.h | 2 ++
> > 3 files changed, 44 insertions(+), 12 deletions(-)
> >
> > --
> > 2.13.4
> >
^ permalink raw reply
* [PATCH] MAINTAINERS: Add PPC contacts for PCI core error handling
From: Bjorn Helgaas @ 2018-09-12 16:55 UTC (permalink / raw)
To: linux-pci, Russell Currey, linuxppc-dev
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
linux-kernel
From: Bjorn Helgaas <bhelgaas@google.com>
The original PCI error recovery functionality was for the powerpc-specific
IBM EEH feature. PCIe subsequently added some similar features, including
AER and DPC, that can be used on any architecture.
We want the generic PCI core error handling support to work with all of
these features. Driver error recovery callbacks should be independent of
which feature the platform provides.
Add the generic PCI core error recovery files to the powerpc EEH
MAINTAINERS entry so the powerpc folks will be copied on changes to the
generic PCI error handling strategy.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7e10ba65bfe4..d6699597fd89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11202,6 +11202,10 @@ PCI ENHANCED ERROR HANDLING (EEH) FOR POWERPC
M: Russell Currey <ruscur@russell.cc>
L: linuxppc-dev@lists.ozlabs.org
S: Supported
+F: Documentation/PCI/pci-error-recovery.txt
+F: drivers/pci/pcie/aer.c
+F: drivers/pci/pcie/dpc.c
+F: drivers/pci/pcie/err.c
F: Documentation/powerpc/eeh-pci-error-recovery.txt
F: arch/powerpc/kernel/eeh*.c
F: arch/powerpc/platforms/*/eeh*.c
^ permalink raw reply related
* Re: [PATCH 0/7 v7] Support for fsl-mc bus and its devices in SMMU
From: Will Deacon @ 2018-09-12 16:58 UTC (permalink / raw)
To: Nipun Gupta
Cc: joro, robin.murphy, robh+dt, robh, mark.rutland, catalin.marinas,
gregkh, laurentiu.tudor, bhelgaas, hch, m.szyprowski, shawnguo,
frowand.list, iommu, linux-kernel, devicetree, linux-arm-kernel,
linuxppc-dev, linux-pci, bharat.bhushan, stuyoder, leoyang.li
In-Reply-To: <1536587361-11047-1-git-send-email-nipun.gupta@nxp.com>
Hi Nipun,
On Mon, Sep 10, 2018 at 07:19:14PM +0530, Nipun Gupta wrote:
> This patchset defines IOMMU DT binding for fsl-mc bus and adds
> support in SMMU for fsl-mc bus.
>
> These patches
> - Define property 'iommu-map' for fsl-mc bus (patch 1)
> - Integrates the fsl-mc bus with the SMMU using this
> IOMMU binding (patch 2,3,4)
> - Adds the dma configuration support for fsl-mc bus (patch 5, 6)
> - Updates the fsl-mc device node with iommu/dma related changes (patch 7)
It looks like you have all the Acks in place for this series now, so I
assume it's going to go via Joerg directly. Is that right?
Will
> Changes in v2:
> - use iommu-map property for fsl-mc bus
> - rebase over patchset https://patchwork.kernel.org/patch/10317337/
> and make corresponding changes for dma configuration of devices on
> fsl-mc bus
>
> Changes in v3:
> - move of_map_rid in drivers/of/address.c
>
> Changes in v4:
> - move of_map_rid in drivers/of/base.c
>
> Changes in v5:
> - break patch 5 in two separate patches (now patch 5/7 and patch 6/7)
> - add changelog text in patch 3/7 and patch 5/7
> - typo fix
>
> Changes in v6:
> - Updated fsl_mc_device_group() API to be more rational
> - Added dma-coherent property in the LS2 smmu device node
> - Minor fixes in the device-tree documentation
>
> Changes in v7:
> - Rebased over linux 4.19
>
> Nipun Gupta (7):
> Documentation: fsl-mc: add iommu-map device-tree binding for fsl-mc
> bus
> iommu/of: make of_pci_map_rid() available for other devices too
> iommu/of: support iommu configuration for fsl-mc devices
> iommu/arm-smmu: Add support for the fsl-mc bus
> bus: fsl-mc: support dma configure for devices on fsl-mc bus
> bus: fsl-mc: set coherent dma mask for devices on fsl-mc bus
> arm64: dts: ls208xa: comply with the iommu map binding for fsl_mc
>
> .../devicetree/bindings/misc/fsl,qoriq-mc.txt | 39 ++++++++
> arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 7 +-
> drivers/bus/fsl-mc/fsl-mc-bus.c | 16 +++-
> drivers/iommu/arm-smmu.c | 7 ++
> drivers/iommu/iommu.c | 13 +++
> drivers/iommu/of_iommu.c | 25 ++++-
> drivers/of/base.c | 102 +++++++++++++++++++++
> drivers/of/irq.c | 5 +-
> drivers/pci/of.c | 101 --------------------
> include/linux/fsl/mc.h | 8 ++
> include/linux/iommu.h | 2 +
> include/linux/of.h | 11 +++
> include/linux/of_pci.h | 10 --
> 13 files changed, 224 insertions(+), 122 deletions(-)
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH] MAINTAINERS: Add PPC contacts for PCI core error handling
From: Bjorn Helgaas @ 2018-09-12 16:58 UTC (permalink / raw)
To: linux-pci, Russell Currey, linuxppc-dev
Cc: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
linux-kernel
In-Reply-To: <153677132617.23091.12307288405707171077.stgit@bhelgaas-glaptop.roam.corp.google.com>
On Wed, Sep 12, 2018 at 11:55:26AM -0500, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> The original PCI error recovery functionality was for the powerpc-specific
> IBM EEH feature. PCIe subsequently added some similar features, including
> AER and DPC, that can be used on any architecture.
>
> We want the generic PCI core error handling support to work with all of
> these features. Driver error recovery callbacks should be independent of
> which feature the platform provides.
>
> Add the generic PCI core error recovery files to the powerpc EEH
> MAINTAINERS entry so the powerpc folks will be copied on changes to the
> generic PCI error handling strategy.
I really want to make sure the powerpc folks are plugged into any PCI core
error handling discussions. Please let me know if there's a better way
than this patch, or if there are other people who should be added.
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> MAINTAINERS | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7e10ba65bfe4..d6699597fd89 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11202,6 +11202,10 @@ PCI ENHANCED ERROR HANDLING (EEH) FOR POWERPC
> M: Russell Currey <ruscur@russell.cc>
> L: linuxppc-dev@lists.ozlabs.org
> S: Supported
> +F: Documentation/PCI/pci-error-recovery.txt
> +F: drivers/pci/pcie/aer.c
> +F: drivers/pci/pcie/dpc.c
> +F: drivers/pci/pcie/err.c
> F: Documentation/powerpc/eeh-pci-error-recovery.txt
> F: arch/powerpc/kernel/eeh*.c
> F: arch/powerpc/platforms/*/eeh*.c
>
^ permalink raw reply
* [PATCH] powerpc/pseries: Track LMB nid instead of using device tree
From: Nathan Fontenot @ 2018-09-12 16:45 UTC (permalink / raw)
To: linuxppc-dev
When removing memory we need to remove the memory from the node
it was added to instead of looking up the node it should be in
in the device tree.
During testing we have seen scenarios where the affinity for a
LMB changes due to a partition migration or PRRN event. In these
cases the node the LMB exists in may not match the node the device
tree indicates it belongs in. This can lead to a system crash
when trying to DLAPR remove the LMB after a migration or PRRN
event. The current code looks up the node in the device tree to
remove the LMB from, the crash occurs when we try to offline this
node and it does not have any data, i.e. node_data[nid] == NULL.
36:mon> e
cpu 0x36: Vector: 300 (Data Access) at [c0000001828b7810]
pc: c00000000036d08c: try_offline_node+0x2c/0x1b0
lr: c0000000003a14ec: remove_memory+0xbc/0x110
sp: c0000001828b7a90
msr: 800000000280b033
dar: 9a28
dsisr: 40000000
current = 0xc0000006329c4c80
paca = 0xc000000007a55200 softe: 0 irq_happened: 0x01
pid = 76926, comm = kworker/u320:3
36:mon> t
[link register ] c0000000003a14ec remove_memory+0xbc/0x110
[c0000001828b7a90] c00000000006a1cc arch_remove_memory+0x9c/0xd0 (unreliable)
[c0000001828b7ad0] c0000000003a14e0 remove_memory+0xb0/0x110
[c0000001828b7b20] c0000000000c7db4 dlpar_remove_lmb+0x94/0x160
[c0000001828b7b60] c0000000000c8ef8 dlpar_memory+0x7e8/0xd10
[c0000001828b7bf0] c0000000000bf828 handle_dlpar_errorlog+0xf8/0x160
[c0000001828b7c60] c0000000000bf8cc pseries_hp_work_fn+0x3c/0xa0
[c0000001828b7c90] c000000000128cd8 process_one_work+0x298/0x5a0
[c0000001828b7d20] c000000000129068 worker_thread+0x88/0x620
[c0000001828b7dc0] c00000000013223c kthread+0x1ac/0x1c0
[c0000001828b7e30] c00000000000b45c ret_from_kernel_thread+0x5c/0x80
To resolve this we need to track the node a LMB belongs to when
it is added to the system so we can remove it from that node instead
of the node that the device tree indicates it should belong to.
Signed-off-by: Nathan Fontenot <nfont@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/drmem.h | 1 +
arch/powerpc/mm/drmem.c | 7 ++++++-
arch/powerpc/platforms/pseries/hotplug-memory.c | 18 +++++++++---------
3 files changed, 16 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/drmem.h b/arch/powerpc/include/asm/drmem.h
index ce242b9ea8c6..d099123f4f26 100644
--- a/arch/powerpc/include/asm/drmem.h
+++ b/arch/powerpc/include/asm/drmem.h
@@ -17,6 +17,7 @@ struct drmem_lmb {
u32 drc_index;
u32 aa_index;
u32 flags;
+ int nid;
};
struct drmem_lmb_info {
diff --git a/arch/powerpc/mm/drmem.c b/arch/powerpc/mm/drmem.c
index 3f1803672c9b..2baf00945b33 100644
--- a/arch/powerpc/mm/drmem.c
+++ b/arch/powerpc/mm/drmem.c
@@ -366,8 +366,11 @@ static void __init init_drmem_v1_lmbs(const __be32 *prop)
if (!drmem_info->lmbs)
return;
- for_each_drmem_lmb(lmb)
+ for_each_drmem_lmb(lmb) {
read_drconf_v1_cell(lmb, &prop);
+ lmb->nid = memory_add_physaddr_to_nid(lmb->base_addr);
+ }
+
}
static void __init init_drmem_v2_lmbs(const __be32 *prop)
@@ -412,6 +415,8 @@ static void __init init_drmem_v2_lmbs(const __be32 *prop)
lmb->aa_index = dr_cell.aa_index;
lmb->flags = dr_cell.flags;
+
+ lmb->nid = memory_add_physaddr_to_nid(lmb->base_addr);
}
}
}
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index c1578f54c626..fc3a1e2d98b8 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -221,6 +221,9 @@ static int dlpar_add_device_tree_lmb(struct drmem_lmb *lmb)
lmb->aa_index = aa_index;
+ /* Find the node id for this address */
+ lmb->nid = memory_add_physaddr_to_nid(lmb->base_addr);
+
rtas_hp_event = true;
rc = drmem_update_dt();
rtas_hp_event = false;
@@ -234,6 +237,7 @@ static int dlpar_remove_device_tree_lmb(struct drmem_lmb *lmb)
lmb->flags &= ~DRCONF_MEM_ASSIGNED;
lmb->aa_index = 0xffffffff;
+ lmb->nid = -1;
rtas_hp_event = true;
rc = drmem_update_dt();
@@ -411,7 +415,7 @@ static int dlpar_add_lmb(struct drmem_lmb *);
static int dlpar_remove_lmb(struct drmem_lmb *lmb)
{
unsigned long block_sz;
- int nid, rc;
+ int rc;
if (!lmb_is_removable(lmb))
return -EINVAL;
@@ -421,9 +425,8 @@ static int dlpar_remove_lmb(struct drmem_lmb *lmb)
return rc;
block_sz = pseries_memory_block_size();
- nid = memory_add_physaddr_to_nid(lmb->base_addr);
- remove_memory(nid, lmb->base_addr, block_sz);
+ remove_memory(lmb->nid, lmb->base_addr, block_sz);
/* Update memory regions for memory remove */
memblock_remove(lmb->base_addr, block_sz);
@@ -683,7 +686,7 @@ static int dlpar_memory_remove_by_ic(u32 lmbs_to_remove, u32 drc_index)
static int dlpar_add_lmb(struct drmem_lmb *lmb)
{
unsigned long block_sz;
- int nid, rc;
+ int rc;
if (lmb->flags & DRCONF_MEM_ASSIGNED)
return -EINVAL;
@@ -698,11 +701,8 @@ static int dlpar_add_lmb(struct drmem_lmb *lmb)
block_sz = memory_block_size_bytes();
- /* Find the node id for this address */
- nid = memory_add_physaddr_to_nid(lmb->base_addr);
-
/* Add the memory */
- rc = add_memory(nid, lmb->base_addr, block_sz);
+ rc = add_memory(lmb->nid, lmb->base_addr, block_sz);
if (rc) {
dlpar_remove_device_tree_lmb(lmb);
return rc;
@@ -710,7 +710,7 @@ static int dlpar_add_lmb(struct drmem_lmb *lmb)
rc = dlpar_online_lmb(lmb);
if (rc) {
- remove_memory(nid, lmb->base_addr, block_sz);
+ remove_memory(lmb->nid, lmb->base_addr, block_sz);
dlpar_remove_device_tree_lmb(lmb);
} else {
lmb->flags |= DRCONF_MEM_ASSIGNED;
^ permalink raw reply related
* Re: [PATCH v2 03/17] compat_ioctl: use correct compat_ptr() translation in drivers
From: Greg Kroah-Hartman @ 2018-09-12 18:13 UTC (permalink / raw)
To: Arnd Bergmann
Cc: viro, linux-fsdevel, Frederic Barrat, Andrew Donnellan,
Frank Haverkamp, Guilherme G. Piccoli, Kashyap Desai,
Sumit Saxena, Shivasharan S, James E.J. Bottomley,
Martin K. Petersen, Felipe Balbi, linuxppc-dev, linux-kernel,
megaraidlinux.pdl, linux-scsi, linux-usb
In-Reply-To: <20180912150142.157913-3-arnd@arndb.de>
On Wed, Sep 12, 2018 at 05:01:04PM +0200, Arnd Bergmann wrote:
> A handful of drivers all have a trivial wrapper around their ioctl
> handler, but don't call the compat_ptr() conversion function at the
> moment. In practice this does not matter, since none of them are used
> on the s390 architecture and for all other architectures, compat_ptr()
> does not do anything, but using the new generic_compat_ioctl_ptrarg
> helper makes it more correct in theory, and simplifies the code.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> drivers/misc/cxl/flash.c | 8 +-------
> drivers/misc/genwqe/card_dev.c | 23 +----------------------
> drivers/scsi/megaraid/megaraid_mm.c | 28 +---------------------------
> drivers/usb/gadget/function/f_fs.c | 12 +-----------
> 4 files changed, 4 insertions(+), 67 deletions(-)
Nice cleanup on this series!
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH v2 05/17] compat_ioctl: move more drivers to generic_compat_ioctl_ptrarg
From: Greg Kroah-Hartman @ 2018-09-12 18:13 UTC (permalink / raw)
To: Arnd Bergmann
Cc: viro, linux-fsdevel, David S. Miller, devel, linux-kernel,
qat-linux, linux-crypto, linux-media, dri-devel, linaro-mm-sig,
amd-gfx, linux-input, linux-iio, linux-rdma, linux-nvdimm,
linux-nvme, linux-pci, platform-driver-x86, linux-remoteproc,
sparclinux, linux-scsi, linux-usb, linux-fbdev, linuxppc-dev,
linux-btrfs, ceph-devel, linux-wireless, netdev
In-Reply-To: <20180912151134.436719-1-arnd@arndb.de>
On Wed, Sep 12, 2018 at 05:08:52PM +0200, Arnd Bergmann wrote:
> The .ioctl and .compat_ioctl file operations have the same prototype so
> they can both point to the same function, which works great almost all
> the time when all the commands are compatible.
>
> One exception is the s390 architecture, where a compat pointer is only
> 31 bit wide, and converting it into a 64-bit pointer requires calling
> compat_ptr(). Most drivers here will ever run in s390, but since we now
> have a generic helper for it, it's easy enough to use it consistently.
>
> I double-checked all these drivers to ensure that all ioctl arguments
> are used as pointers or are ignored, but are not interpreted as integer
> values.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* [RFC PATCH 00/11] New TM Model
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour
This patchset for the hardware transactional memory (TM) subsystem aims to
avoid spending a lot of time on TM suspended mode in kernel space. It basically
changes where the reclaim/recheckpoint will be executed.
Once a CPU enters in transactional state it uses a footprint area to track
down the load/stores performed in transaction so it can be verified later
to decide if a conflict happened due to some change done in that state. If
a transaction is active in userspace and there is an exception that takes
the CPU to the kernel space the CPU moves the transaction to suspended
state but does not discard the footprint area.
POWER9 has a known problem[1][2] and does not have enough room in
footprint area for several transactions to be suspended at the same time
on concurrent CPUs leading to CPU stalls.
This patchset aims to reclaim the checkpointed footprint as soon as the
kernel is invoked, in the beginning of the exception handlers, thus freeing
room to other CPUs enter in suspended mode, avoiding too many CPUs in suspended
state that can cause the CPUs to stall. The same mechanism is done on kernel
exit, doing a recheckpoint as late as possible (which will reload the
checkpointed state into CPU's room) at the exception return.
The way to achieve this goal is creating a macro (TM_KERNEL_ENTRY) which
will check if userspace was in an active transaction just after getting
into kernel and reclaiming if that's the case. Thus all exception handlers
will call this macro as soon as possible.
All exceptions should reclaim (if necessary) at this stage and only
recheckpoint if the task is tagged as TIF_RESTORE_TM (i.e. was in
transactional state before being interrupted), which will be done at
ret_from_except_lite().
Ideally all reclaims will happen at the exception entrance, however during
the recheckpoint process another exception can hit the CPU which might
cause the current thread to be rescheduled, thus there is another reclaim
point to be considered at __switch_to().
Hence, by allowing the CPU to be in suspended state for only a brief period
it's possible to cope with the TM hardware limitations like the current
problem on the new POWER9.
This patchset was tested in different scenarios using different test
suites, as the kernel selftests and htm-torture[3], in the following
configuration:
* POWER8/pseries LE and BE
* POWER8/powernv LE
* POWER9/powernv LE hosting KVM guests running TM tests
This patchset is based on initial work done by Cyril Bur:
https://patchwork.ozlabs.org/cover/875341/
Regards,
Breno
[1] Documentation/powerpc/transactional_memory.txt
[2] commit 4bb3c7a0208fc13ca70598efd109901a7cd45ae7
[3] https://github.com/leitao/htm_torture/
Breno Leitao (11):
powerpc/tm: Reclaim transaction on kernel entry
powerpc/tm: Reclaim on unavailable exception
powerpc/tm: Recheckpoint when exiting from kernel
powerpc/tm: Always set TIF_RESTORE_TM on reclaim
powerpc/tm: Function that updates the failure code
powerpc/tm: Refactor the __switch_to_tm code
powerpc/tm: Do not recheckpoint at sigreturn
powerpc/tm: Do not reclaim on ptrace
powerpc/tm: Do not restore default DSCR
powerpc/tm: Set failure summary
selftests/powerpc: Adapt the test
arch/powerpc/include/asm/exception-64s.h | 46 +++++
arch/powerpc/kernel/entry_64.S | 10 +
arch/powerpc/kernel/exceptions-64s.S | 15 +-
arch/powerpc/kernel/process.c | 185 +++++++++---------
arch/powerpc/kernel/ptrace.c | 10 +-
arch/powerpc/kernel/signal_32.c | 25 +--
arch/powerpc/kernel/signal_64.c | 17 +-
arch/powerpc/kernel/tm.S | 4 -
arch/powerpc/kernel/traps.c | 16 +-
.../testing/selftests/powerpc/tm/tm-syscall.c | 6 -
10 files changed, 178 insertions(+), 156 deletions(-)
--
2.19.0
^ permalink raw reply
* [RFC PATCH 01/11] powerpc/tm: Reclaim transaction on kernel entry
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
This patch creates a macro that will be invoked on all entrance to the
kernel, so, in kernel space the transaction will be completely reclaimed
and not suspended anymore.
This patchset checks if we are coming from PR, if not, skip. This is useful
when there is a irq_replay() being called after recheckpoint, when the IRQ
is re-enable. In this case, we do not want to re-reclaim and
re-recheckpoint, thus, if not coming from PR, skip it completely.
This macro does not care about TM SPR also, it will only be saved and
restore in the context switch code now on.
This macro will return 0 or 1 in r3 register, to specify if a reclaim was
executed or not.
This patchset is based on initial work done by Cyril:
https://patchwork.ozlabs.org/cover/875341/
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/include/asm/exception-64s.h | 46 ++++++++++++++++++++++++
arch/powerpc/kernel/entry_64.S | 10 ++++++
arch/powerpc/kernel/exceptions-64s.S | 12 +++++--
3 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index a86feddddad0..db90b6d7826e 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -36,6 +36,7 @@
*/
#include <asm/head-64.h>
#include <asm/feature-fixups.h>
+#include <asm/tm.h>
/* PACA save area offsets (exgen, exmc, etc) */
#define EX_R9 0
@@ -686,10 +687,54 @@ BEGIN_FTR_SECTION \
beql ppc64_runlatch_on_trampoline; \
END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+
+/*
+ * This macro will reclaim a transaction if called when coming from userspace
+ * (MSR.PR = 1) and if the transaction state is active or suspended.
+ *
+ * Since we don't want to reclaim when coming from kernel, for instance after
+ * a trechkpt. or a IRQ replay, the live MSR is not useful and instead of it the
+ * MSR from thread stack is used to check the MSR.PR bit.
+ * This macro has one argument which is the cause that will be used by treclaim.
+ * and returns in r3 '1' if the reclaim happens or '0' if reclaim didn't
+ * happen, which is useful to know what registers were clobbered.
+ *
+ * NOTE: If addition registers are clobbered here, make sure the callee
+ * function restores them before proceeding.
+ */
+#define TM_KERNEL_ENTRY(cause) \
+ ld r3, _MSR(r1); \
+ andi. r0, r3, MSR_PR; /* Coming from userspace? */ \
+ beq 1f; /* Skip reclaim if MSR.PR != 1 */ \
+ rldicl. r0, r3, (64-MSR_TM_LG), 63; /* Is TM enabled? */ \
+ beq 1f; /* Skip reclaim if TM is off */ \
+ rldicl. r0, r3, (64-MSR_TS_LG), 62; /* Is active */ \
+ beq 1f; /* Skip reclaim if neither */ \
+ /* \
+ * If there is a transaction active or suspended, save the \
+ * non-volatile GPRs if they are not already saved. \
+ */ \
+ bl save_nvgprs; \
+ /* \
+ * Soft disable the IRQs, otherwise it might cause a CPU hang. \
+ */ \
+ RECONCILE_IRQ_STATE(r10, r11); \
+ li r3, cause; \
+ bl tm_reclaim_current; \
+ li r3, 1; /* Reclaim happened */ \
+ b 2f; \
+1: li r3, 0; /* Reclaim didn't happen */ \
+2:
+#else
+#define TM_KERNEL_ENTRY(cause)
+#endif
+
#define EXCEPTION_COMMON(area, trap, label, hdlr, ret, additions) \
EXCEPTION_PROLOG_COMMON(trap, area); \
/* Volatile regs are potentially clobbered here */ \
additions; \
+ TM_KERNEL_ENTRY(TM_CAUSE_MISC); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
bl hdlr; \
b ret
@@ -704,6 +749,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
EXCEPTION_PROLOG_COMMON_3(trap); \
/* Volatile regs are potentially clobbered here */ \
additions; \
+ TM_KERNEL_ENTRY(TM_CAUSE_MISC); \
addi r3,r1,STACK_FRAME_OVERHEAD; \
bl hdlr
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 2206912ea4f0..c38677b7442c 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -131,6 +131,16 @@ BEGIN_FW_FTR_SECTION
END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */
+#if CONFIG_PPC_TRANSACTIONAL_MEM
+ TM_KERNEL_ENTRY(TM_CAUSE_SYSCALL)
+ cmpdi r3, 0x1
+ bne 44f
+ /* Restore from r4 to r12 */
+ REST_8GPRS(4,r1)
+44: /* treclaim was not called, just restore r3 and r0 */
+ REST_GPR(3, r1)
+ REST_GPR(0, r1)
+#endif
/*
* A syscall should always be called with interrupts enabled
* so we just unconditionally hard-enable here. When some kind
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index ea04dfb8c092..78aba71a4b2d 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -805,6 +805,7 @@ EXC_COMMON_BEGIN(alignment_common)
std r3,_DAR(r1)
std r4,_DSISR(r1)
bl save_nvgprs
+ TM_KERNEL_ENTRY(TM_CAUSE_ALIGNMENT)
RECONCILE_IRQ_STATE(r10, r11)
addi r3,r1,STACK_FRAME_OVERHEAD
bl alignment_exception
@@ -839,6 +840,8 @@ EXC_COMMON_BEGIN(program_check_common)
b 3f /* Jump into the macro !! */
1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
bl save_nvgprs
+ ld r3, _MSR(r1)
+ TM_KERNEL_ENTRY(TM_CAUSE_FAC_UNAV)
RECONCILE_IRQ_STATE(r10, r11)
addi r3,r1,STACK_FRAME_OVERHEAD
bl program_check_exception
@@ -1738,7 +1741,9 @@ do_hash_page:
/* Here we have a page fault that hash_page can't handle. */
handle_page_fault:
-11: andis. r0,r4,DSISR_DABRMATCH@h
+11: TM_KERNEL_ENTRY(TM_CAUSE_TLBI)
+ ld r4,_DSISR(r1)
+ andis. r0,r4,DSISR_DABRMATCH@h
bne- handle_dabr_fault
ld r4,_DAR(r1)
ld r5,_DSISR(r1)
@@ -1769,6 +1774,8 @@ handle_dabr_fault:
*/
13: bl save_nvgprs
mr r5,r3
+ TM_KERNEL_ENTRY(TM_CAUSE_TLBI)
+ REST_GPR(3,r1)
addi r3,r1,STACK_FRAME_OVERHEAD
ld r4,_DAR(r1)
bl low_hash_fault
@@ -1783,7 +1790,8 @@ handle_dabr_fault:
* the access, or panic if there isn't a handler.
*/
77: bl save_nvgprs
- mr r4,r3
+ TM_KERNEL_ENTRY(TM_CAUSE_TLBI)
+ ld r4,_DAR(r1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r5,SIGSEGV
bl bad_page_fault
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 02/11] powerpc/tm: Reclaim on unavailable exception
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
If there is a FP/VEC/Altivec touch inside a transaction and the facility is
disabled, then a facility unavailable exception is raised and ends up
calling {fp,vec,vsx}_unavailable_tm, which was reclaiming and recheckpointing.
This is not required anymore, since the checkpointed state was reclaimed in
the trap entrace itself, and it will be recheckpointed by restore_tm_state
later.
With this new patchset, we only reclaim at exception entrance (except at
syscall level if the transaction is suspended), and always recheckpoint on
restore_tm_state.
Adding a WARN_ON() warning if we hit the _unavailable_tm() in suspended
mode, i.e, the reclaim was not executed somehow in the trap entrance.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/exceptions-64s.S | 3 +++
arch/powerpc/kernel/traps.c | 16 ++++------------
2 files changed, 7 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 78aba71a4b2d..4108f3944bdd 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -874,6 +874,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_TM)
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
bl save_nvgprs
+ TM_KERNEL_ENTRY(TM_CAUSE_FAC_UNAV)
RECONCILE_IRQ_STATE(r10, r11)
addi r3,r1,STACK_FRAME_OVERHEAD
bl fp_unavailable_tm
@@ -1216,6 +1217,7 @@ BEGIN_FTR_SECTION
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
bl save_nvgprs
+ TM_KERNEL_ENTRY(TM_CAUSE_FAC_UNAV)
RECONCILE_IRQ_STATE(r10, r11)
addi r3,r1,STACK_FRAME_OVERHEAD
bl altivec_unavailable_tm
@@ -1252,6 +1254,7 @@ BEGIN_FTR_SECTION
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2: /* User process was in a transaction */
bl save_nvgprs
+ TM_KERNEL_ENTRY(TM_CAUSE_FAC_UNAV)
RECONCILE_IRQ_STATE(r10, r11)
addi r3,r1,STACK_FRAME_OVERHEAD
bl vsx_unavailable_tm
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index c85adb858271..b973fdb72826 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1749,19 +1749,12 @@ void fp_unavailable_tm(struct pt_regs *regs)
* transaction, and probably retry but now with FP enabled. So the
* checkpointed FP registers need to be loaded.
*/
- tm_reclaim_current(TM_CAUSE_FAC_UNAV);
+ WARN_ON(MSR_TM_SUSPENDED(mfmsr()));
/* Reclaim didn't save out any FPRs to transact_fprs. */
/* Enable FP for the task: */
current->thread.load_fp = 1;
- /* This loads and recheckpoints the FP registers from
- * thread.fpr[]. They will remain in registers after the
- * checkpoint so we don't need to reload them after.
- * If VMX is in use, the VRs now hold checkpointed values,
- * so we don't want to load the VRs from the thread_struct.
- */
- tm_recheckpoint(¤t->thread);
}
void altivec_unavailable_tm(struct pt_regs *regs)
@@ -1773,10 +1766,10 @@ void altivec_unavailable_tm(struct pt_regs *regs)
TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
"MSR=%lx\n",
regs->nip, regs->msr);
- tm_reclaim_current(TM_CAUSE_FAC_UNAV);
+ WARN_ON(MSR_TM_SUSPENDED(mfmsr()));
current->thread.load_vec = 1;
- tm_recheckpoint(¤t->thread);
current->thread.used_vr = 1;
+
}
void vsx_unavailable_tm(struct pt_regs *regs)
@@ -1795,12 +1788,11 @@ void vsx_unavailable_tm(struct pt_regs *regs)
current->thread.used_vsr = 1;
/* This reclaims FP and/or VR regs if they're already enabled */
- tm_reclaim_current(TM_CAUSE_FAC_UNAV);
+ WARN_ON(MSR_TM_SUSPENDED(mfmsr()));
current->thread.load_vec = 1;
current->thread.load_fp = 1;
- tm_recheckpoint(¤t->thread);
}
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 03/11] powerpc/tm: Recheckpoint when exiting from kernel
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
This is the only place we are going to recheckpoint now. Now the task
needs to have TIF_RESTORE_TM flag set, which will get into
restore_tm_state() and execute the recheckpoint if MSR shows that the
transaction was active.
Every time a task is required to recheckpoint, or just have the TM SPRs
restore, the TIF_RESTORE_TM flag should be set and the task MSR should
properly be in a transactional state, which will be checked by
restore_tm_state().
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/process.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 913c5725cdb2..f22f82ce174c 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -1069,6 +1069,10 @@ void restore_tm_state(struct pt_regs *regs)
if (!MSR_TM_ACTIVE(regs->msr))
return;
+ tm_enable();
+ /* The only place we recheckpoint */
+ tm_recheckpoint(¤t->thread);
+
msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 04/11] powerpc/tm: Always set TIF_RESTORE_TM on reclaim
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
If the task data was reclaimed (through TM_KERNEL_ENTRY), then it needs to
be recheckpointed later, once exiting to userspace. The recheckpoint is
done by restore_tm_state() function, which is called on our way to
userspace if the task has the TIF_RESTORE_TM flag set.
This patch makes sure the task has TIF_RESTORE_TM tag set every time there
is a reclaim, so, a recheckpoint will be executed later.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/process.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index f22f82ce174c..54fddf03b97a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -891,6 +891,9 @@ static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
tm_reclaim(thr, cause);
+ /* Tag it so restore_tm_state will pay attention to this task */
+ set_thread_flag(TIF_RESTORE_TM);
+
/*
* If we are in a transaction and FP is off then we can't have
* used FP inside that transaction. Hence the checkpointed
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 05/11] powerpc/tm: Function that updates the failure code
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
Now the transaction reclaims happens very earlier in the trap handler, and
it is impossible to know precisely, at that early time, what should be set
as the failure cause for some specific cases, as, if the task will be
rescheduled, thus, the transaction abort case should be updated from
TM_CAUSE_MISC to TM_CAUSE_RESCHED, for example.
This patch creates a function that will update TEXASR special purpose
register in the task thread and set the failure code which will be
moved to the live register afterward.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/process.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 54fddf03b97a..fe063c0142e3 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -85,6 +85,7 @@ extern unsigned long _get_SP(void);
* other paths that we should never reach with suspend disabled.
*/
bool tm_suspend_disabled __ro_after_init = false;
+static void tm_fix_failure_cause(struct task_struct *task, uint8_t cause);
static void check_if_tm_restore_required(struct task_struct *tsk)
{
@@ -988,6 +989,14 @@ void tm_recheckpoint(struct thread_struct *thread)
local_irq_restore(flags);
}
+/* Change thread->tm.texasr failure code */
+static void tm_fix_failure_cause(struct task_struct *task, uint8_t cause)
+{
+ /* Clear the cause first */
+ task->thread.tm_texasr &= ~TEXASR_FC;
+ task->thread.tm_texasr |= (unsigned long) cause << 56;
+}
+
static inline void tm_recheckpoint_new_task(struct task_struct *new)
{
if (!cpu_has_feature(CPU_FTR_TM))
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 06/11] powerpc/tm: Refactor the __switch_to_tm code
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
__switch_to_tm is the function that switches between two tasks which might
have TM enabled. This function is clearly split in two parts, the task that
is leaving the CPU, known as 'prev' and the task that is being scheduled,
known as new.
It starts checking if the previous task had TM enable, if so, it increases
the load_tm (this is the only place we increment load_tm). It also saves
the TM SPRs here.
If the previous task was scheduled out with a transaction active, the
failure cause needs to be updated, since it might contain the failure cause
that caused the exception, as TM_CAUSE_MISC. In this case, since there was
a context switch, overwrite the failure cause.
If the previous task has overflowed load_tm, disable TM, putting the
facility save/restore lazy mechanism at lazy mode.
Regarding the new task, when loading it, it basically restore the SPRs, and
TIF_RESTORE_TM (already set by tm_reclaim_current if the transaction was
active) would invoke the recheckpoint process later in restore_tm_state()
if recheckpoint is somehow required.
On top of that, both tm_reclaim_task() and tm_recheckpoint_new_task()
functions are not used anymore, removing them.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/process.c | 163 +++++++++++++++-------------------
1 file changed, 74 insertions(+), 89 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index fe063c0142e3..5cace1b744b1 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -921,48 +921,6 @@ void tm_reclaim_current(uint8_t cause)
tm_reclaim_thread(¤t->thread, cause);
}
-static inline void tm_reclaim_task(struct task_struct *tsk)
-{
- /* We have to work out if we're switching from/to a task that's in the
- * middle of a transaction.
- *
- * In switching we need to maintain a 2nd register state as
- * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
- * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
- * ckvr_state
- *
- * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
- */
- struct thread_struct *thr = &tsk->thread;
-
- if (!thr->regs)
- return;
-
- if (!MSR_TM_ACTIVE(thr->regs->msr))
- goto out_and_saveregs;
-
- WARN_ON(tm_suspend_disabled);
-
- TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
- "ccr=%lx, msr=%lx, trap=%lx)\n",
- tsk->pid, thr->regs->nip,
- thr->regs->ccr, thr->regs->msr,
- thr->regs->trap);
-
- tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
-
- TM_DEBUG("--- tm_reclaim on pid %d complete\n",
- tsk->pid);
-
-out_and_saveregs:
- /* Always save the regs here, even if a transaction's not active.
- * This context-switches a thread's TM info SPRs. We do it here to
- * be consistent with the restore path (in recheckpoint) which
- * cannot happen later in _switch().
- */
- tm_save_sprs(thr);
-}
-
extern void __tm_recheckpoint(struct thread_struct *thread);
void tm_recheckpoint(struct thread_struct *thread)
@@ -997,59 +955,87 @@ static void tm_fix_failure_cause(struct task_struct *task, uint8_t cause)
task->thread.tm_texasr |= (unsigned long) cause << 56;
}
-static inline void tm_recheckpoint_new_task(struct task_struct *new)
+static inline void __switch_to_tm(struct task_struct *prev,
+ struct task_struct *new)
{
if (!cpu_has_feature(CPU_FTR_TM))
return;
- /* Recheckpoint the registers of the thread we're about to switch to.
- *
- * If the task was using FP, we non-lazily reload both the original and
- * the speculative FP register states. This is because the kernel
- * doesn't see if/when a TM rollback occurs, so if we take an FP
- * unavailable later, we are unable to determine which set of FP regs
- * need to be restored.
- */
- if (!tm_enabled(new))
- return;
-
- if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
- tm_restore_sprs(&new->thread);
- return;
- }
- /* Recheckpoint to restore original checkpointed register state. */
- TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
- new->pid, new->thread.regs->msr);
-
- tm_recheckpoint(&new->thread);
-
- /*
- * The checkpointed state has been restored but the live state has
- * not, ensure all the math functionality is turned off to trigger
- * restore_math() to reload.
- */
- new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
+ /* The task leaving the CPU was using TM, let's handle it */
+ if (tm_enabled(prev)) {
+ /*
+ * Load_tm is incremented only when the task is scheduled out
+ */
+ prev->thread.load_tm++;
- TM_DEBUG("*** tm_recheckpoint of pid %d complete "
- "(kernel msr 0x%lx)\n",
- new->pid, mfmsr());
-}
+ /*
+ * If TM is enabled for the thread, it needs to, at least,
+ * save the SPRs
+ */
+ tm_enable();
+ tm_save_sprs(&prev->thread);
-static inline void __switch_to_tm(struct task_struct *prev,
- struct task_struct *new)
-{
- if (cpu_has_feature(CPU_FTR_TM)) {
- if (tm_enabled(prev) || tm_enabled(new))
- tm_enable();
+ /*
+ * If we got here with an active transaction, then, it was
+ * aborted by TM_KERNEL_ENTRY and the fix the failure case
+ * needs to be fixed, so, indepedently how we arrived here, the
+ * new TM abort case will be TM_CAUSE_RESCHED now.
+ */
+ if (MSR_TM_ACTIVE(prev->thread.regs->msr)) {
+ /*
+ * If there was an IRQ during trecheckpoint, it will
+ * cause an IRQ to be replayed. This replayed IRQ can
+ * invoke SCHEDULE_USER, thus, we arrive here with a TM
+ * active transaction.
+ * I.e, the task was leaving kernelspace to userspace,
+ * already trecheckpointed, but there was a IRQ during
+ * the trecheckpoint process (soft irq disabled), and
+ * on the IRQ replay, the process was de-scheduled, so,
+ * SCHEDULE_USER was called and here we are.
+ *
+ */
+ if (MSR_TM_ACTIVE(mfmsr())) {
+ /*
+ * This is the only other case other than
+ * TM_KERNEL_ENTRY that does a TM reclaim
+ */
+ tm_reclaim_current(TM_CAUSE_RESCHED);
+ }
- if (tm_enabled(prev)) {
- prev->thread.load_tm++;
- tm_reclaim_task(prev);
- if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
+ /*
+ * If rescheduled with TM active, update the
+ * failure cause
+ */
+ tm_fix_failure_cause(prev, TM_CAUSE_RESCHED);
+ } else {
+ /*
+ * TM enabled but not transactional. Just disable TM
+ * if load_tm overflows. This should be the only place
+ * that disables the TM and reenables the laziness
+ * save/restore
+ */
+ if (prev->thread.load_tm == 0)
prev->thread.regs->msr &= ~MSR_TM;
}
+ }
- tm_recheckpoint_new_task(new);
+ /*
+ * It is a *bug* if we arrived so late with a transaction active
+ * (more precisely suspended)
+ */
+ if (WARN_ON(MSR_TM_ACTIVE(mfmsr()))) {
+ /* Recovery path. 0x99 shouldn't be exported to UAPI */
+ tm_reclaim_current(0x99);
+ }
+
+ /*
+ * If the next task has TM enabled, restore the SPRs. Do not need to
+ * care about recheckpoint at this time. It will be done later if
+ * TIF_RESTORE_TM was set when the task was scheduled out
+ */
+ if (tm_enabled(new)) {
+ tm_enable();
+ tm_restore_sprs(&new->thread);
}
}
@@ -1101,7 +1087,6 @@ void restore_tm_state(struct pt_regs *regs)
}
#else
-#define tm_recheckpoint_new_task(new)
#define __switch_to_tm(prev, new)
#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
@@ -1588,9 +1573,9 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
/*
* Flush TM state out so we can copy it. __switch_to_tm() does this
* flush but it removes the checkpointed state from the current CPU and
- * transitions the CPU out of TM mode. Hence we need to call
- * tm_recheckpoint_new_task() (on the same task) to restore the
- * checkpointed state back and the TM mode.
+ * transitions the CPU out of TM mode. Hence we need to make sure
+ * TIF_RESTORE_TM is set so restore_tm_state is called to restore the
+ * checkpointed state and back to TM mode.
*
* Can't pass dst because it isn't ready. Doesn't matter, passing
* dst is only important for __switch_to()
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 07/11] powerpc/tm: Do not recheckpoint at sigreturn
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
Do not recheckpoint at signal code return. Just make sure TIF_RESTORE_TM is
set, which will restore on the exit to userspace by restore_tm_state.
All the FP and VEC lazy restore was already done by tm_reclaim_current(),
where it checked if FP/VEC was set, and filled out the ckfp and ckvr
registers area to the expected value.
The current FP/VEC restoration is not necessary, since the transaction will
be aborted and the checkpointed values will be restore.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/signal_32.c | 23 +++--------------------
arch/powerpc/kernel/signal_64.c | 15 ++-------------
2 files changed, 5 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index e6474a45cef5..4a1b17409bf3 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -850,28 +850,11 @@ static long restore_tm_user_regs(struct pt_regs *regs,
return 1;
/* Pull in the MSR TM bits from the user context */
regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr_hi & MSR_TS_MASK);
- /* Now, recheckpoint. This loads up all of the checkpointed (older)
- * registers, including FP and V[S]Rs. After recheckpointing, the
- * transactional versions should be loaded.
- */
- tm_enable();
+
/* Make sure the transaction is marked as failed */
current->thread.tm_texasr |= TEXASR_FS;
- /* This loads the checkpointed FP/VEC state, if used */
- tm_recheckpoint(¤t->thread);
-
- /* This loads the speculative FP/VEC state, if used */
- msr_check_and_set(msr & (MSR_FP | MSR_VEC));
- if (msr & MSR_FP) {
- load_fp_state(¤t->thread.fp_state);
- regs->msr |= (MSR_FP | current->thread.fpexc_mode);
- }
-#ifdef CONFIG_ALTIVEC
- if (msr & MSR_VEC) {
- load_vr_state(¤t->thread.vr_state);
- regs->msr |= MSR_VEC;
- }
-#endif
+ /* Make sure restore_tm_state will be called */
+ set_thread_flag(TIF_RESTORE_TM);
return 0;
}
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 83d51bf586c7..32402aa23a5e 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -569,21 +569,10 @@ static long restore_tm_sigcontexts(struct task_struct *tsk,
}
}
#endif
- tm_enable();
/* Make sure the transaction is marked as failed */
tsk->thread.tm_texasr |= TEXASR_FS;
- /* This loads the checkpointed FP/VEC state, if used */
- tm_recheckpoint(&tsk->thread);
-
- msr_check_and_set(msr & (MSR_FP | MSR_VEC));
- if (msr & MSR_FP) {
- load_fp_state(&tsk->thread.fp_state);
- regs->msr |= (MSR_FP | tsk->thread.fpexc_mode);
- }
- if (msr & MSR_VEC) {
- load_vr_state(&tsk->thread.vr_state);
- regs->msr |= MSR_VEC;
- }
+ /* Guarantee that restore_tm_state() will be called */
+ set_thread_flag(TIF_RESTORE_TM);
return err;
}
--
2.19.0
^ permalink raw reply related
* [RFC PATCH 08/11] powerpc/tm: Do not reclaim on ptrace
From: Breno Leitao @ 2018-09-12 19:40 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, paulus, gromero, mpe, ldufour, Breno Leitao
In-Reply-To: <1536781219-13938-1-git-send-email-leitao@debian.org>
Make sure that we are not suspended on ptrace and that the registers were
already reclaimed.
Since the data was already reclaimed, there is nothing to be done here
except to restore the SPRs.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
arch/powerpc/kernel/ptrace.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 9667666eb18e..cf6ee9154b11 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -136,12 +136,10 @@ static void flush_tmregs_to_thread(struct task_struct *tsk)
if ((!cpu_has_feature(CPU_FTR_TM)) || (tsk != current))
return;
- if (MSR_TM_SUSPENDED(mfmsr())) {
- tm_reclaim_current(TM_CAUSE_SIGNAL);
- } else {
- tm_enable();
- tm_save_sprs(&(tsk->thread));
- }
+ WARN_ON(MSR_TM_SUSPENDED(mfmsr()));
+
+ tm_enable();
+ tm_save_sprs(&(tsk->thread));
}
#else
static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
--
2.19.0
^ permalink raw reply related
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