* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Ard Biesheuvel @ 2018-10-05 14:03 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Jason A . Donenfeld, Catalin Marinas, Will Deacon, Samuel Neves,
Paul Mackerras, Herbert Xu, Richard Weinberger, Eric Biggers,
Ingo Molnar, Kees Cook, Arnd Bergmann, Andy Lutomirski,
Thomas Gleixner, linux-arm-kernel, Martin K. Petersen,
Greg Kroah-Hartman, Linux Kernel Mailing List,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Andrew Morton,
linuxppc-dev, David S. Miller
In-Reply-To: <20181005135728.GR19272@hirez.programming.kicks-ass.net>
On 5 October 2018 at 15:57, Peter Zijlstra <peterz@infradead.org> wrote:
> On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
>> Add a function pointer abstraction that can be implemented by the arch
>> in a manner that avoids the downsides of function pointers, i.e., the
>> fact that they are typically located in a writable data section, and
>> their vulnerability to Spectre like defects.
>>
>> The FFP (or fast function pointer) is callable as a function, since
>> the generic incarnation is simply that. However, due to the fact that
>> C does not distinguish between functions and function pointers at the
>> call site, the architecture can instead emit it as a patchable sequence
>> of instructions consisting of ordinary branches.
>
> This is basically a static_key, except for indirection function calls?
Yes, that is why I put you on cc :-)
> So why not call the thing static_func or static_call or something like
> that?
Yep that sounds better.
^ permalink raw reply
* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Peter Zijlstra @ 2018-10-05 14:14 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Jason A . Donenfeld, Catalin Marinas, Will Deacon, Samuel Neves,
Paul Mackerras, Herbert Xu, Richard Weinberger, Eric Biggers,
Ingo Molnar, Kees Cook, Arnd Bergmann, Andy Lutomirski,
Thomas Gleixner, linux-arm-kernel, Martin K. Petersen,
Greg Kroah-Hartman, linux-kernel, linux-crypto, Andrew Morton,
linuxppc-dev, David S. Miller
In-Reply-To: <20181005081333.15018-2-ard.biesheuvel@linaro.org>
On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
> diff --git a/include/linux/ffp.h b/include/linux/ffp.h
> new file mode 100644
> index 000000000000..8fc3b4c9b38f
> --- /dev/null
> +++ b/include/linux/ffp.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +#ifndef __LINUX_FFP_H
> +#define __LINUX_FFP_H
> +
> +#include <linux/types.h>
> +#include <linux/compiler.h>
> +
> +#ifdef CONFIG_HAVE_ARCH_FFP
> +#include <asm/ffp.h>
> +#else
> +
> +struct ffp {
> + void (**fn)(void);
> + void (*default_fn)(void);
> +};
> +
> +#define DECLARE_FFP(_fn, _def) \
> + extern typeof(_def) *_fn; \
> + extern struct ffp const __ffp_ ## _fn
> +
> +#define DEFINE_FFP(_fn, _def) \
> + typeof(_def) *_fn = &_def; \
> + struct ffp const __ffp_ ## _fn \
> + = { (void(**)(void))&_fn, (void(*)(void))&_def }; \
> + EXPORT_SYMBOL(__ffp_ ## _fn)
> +
> +static inline void ffp_set_target(const struct ffp *m, void *new_fn)
> +{
> + WRITE_ONCE(*m->fn, new_fn);
> +}
> +
> +static inline void ffp_reset_target(const struct ffp *m)
> +{
> + WRITE_ONCE(*m->fn, m->default_fn);
> +}
> +
> +#endif
> +
> +#define SET_FFP(_fn, _new) ffp_set_target(&__ffp_ ## _fn, _new)
> +#define RESET_FFP(_fn) ffp_reset_target(&__ffp_ ## _fn)
> +
> +#endif
I don't understand this interface. There is no wrapper for the call
site, so how are we going to patch all call-sites when you update the
target?
^ permalink raw reply
* Re: linux-next: Tree for Oct 4
From: Alexander Duyck @ 2018-10-05 14:27 UTC (permalink / raw)
To: Stephen Rothwell, Guenter Roeck
Cc: Linus PPC, Linux Kernel Mailing List,
open list:INTEL IOMMU (VT-d), Linux-Next, Geert Uytterhoeven,
Greg KH, Robin Murphy, Christoph Hellwig
In-Reply-To: <20181005153905.126a005e@canb.auug.org.au>
On 10/4/2018 10:39 PM, Stephen Rothwell wrote:
> Hi Guenter,
>
> On Thu, 4 Oct 2018 18:33:02 -0700 Guenter Roeck <linux@roeck-us.net> wrote:
>>
>> Most of the boot failures are hopefully fixed with
>> https://lore.kernel.org/patchwork/patch/995254/
>
> I have added that commit to linux-next today.
>
After getting over that I ended up running into an issues with a NULL
pointer dereference updating static keys/jump labels that was fixed by:
https://lore.kernel.org/patchwork/patch/993864/
Thanks.
- Alex
^ permalink raw reply
* Re: [PATCH 15/16] of: unittest: initialize args before calling of_irq_parse_one()
From: Rob Herring @ 2018-10-05 14:53 UTC (permalink / raw)
To: Frank Rowand
Cc: devicetree, Alan Tull, linux-fpga, Pantelis Antoniou,
linux-kernel@vger.kernel.org, Moritz Fischer, Paul Mackerras,
linuxppc-dev, Guenter Roeck
In-Reply-To: <1538712767-30394-16-git-send-email-frowand.list@gmail.com>
On Thu, Oct 4, 2018 at 11:14 PM <frowand.list@gmail.com> wrote:
>
> From: Frank Rowand <frank.rowand@sony.com>
>
> Callers of of_irq_parse_one() blindly use the pointer args.np
> without checking whether of_irq_parse_one() had an error and
> thus did not set the value of args.np. Initialize args to
> zero so that using the format "%pOF" to show the value of
> args.np will show "(null)" when of_irq_parse_one() has an
> error and does not set args.np instead of trying to
> dereference a random value.
>
> Reported-by: Guenter Roeck <linux@roeck-us.net>
> Signed-off-by: Frank Rowand <frank.rowand@sony.com>
> ---
> drivers/of/unittest.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Does this need to be part of this series?
Rob
^ permalink raw reply
* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Ard Biesheuvel @ 2018-10-05 14:57 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Jason A . Donenfeld, Catalin Marinas, Will Deacon, Samuel Neves,
Paul Mackerras, Herbert Xu, Richard Weinberger, Eric Biggers,
Ingo Molnar, Kees Cook, Arnd Bergmann, Andy Lutomirski,
Thomas Gleixner, linux-arm-kernel, Martin K. Petersen,
Greg Kroah-Hartman, Linux Kernel Mailing List,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Andrew Morton,
linuxppc-dev, David S. Miller
In-Reply-To: <20181005141433.GS19272@hirez.programming.kicks-ass.net>
On 5 October 2018 at 16:14, Peter Zijlstra <peterz@infradead.org> wrote:
> On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
>> diff --git a/include/linux/ffp.h b/include/linux/ffp.h
>> new file mode 100644
>> index 000000000000..8fc3b4c9b38f
>> --- /dev/null
>> +++ b/include/linux/ffp.h
>> @@ -0,0 +1,43 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +
>> +#ifndef __LINUX_FFP_H
>> +#define __LINUX_FFP_H
>> +
>> +#include <linux/types.h>
>> +#include <linux/compiler.h>
>> +
>> +#ifdef CONFIG_HAVE_ARCH_FFP
>> +#include <asm/ffp.h>
>> +#else
>> +
>> +struct ffp {
>> + void (**fn)(void);
>> + void (*default_fn)(void);
>> +};
>> +
>> +#define DECLARE_FFP(_fn, _def) \
>> + extern typeof(_def) *_fn; \
>> + extern struct ffp const __ffp_ ## _fn
>> +
>> +#define DEFINE_FFP(_fn, _def) \
>> + typeof(_def) *_fn = &_def; \
>> + struct ffp const __ffp_ ## _fn \
>> + = { (void(**)(void))&_fn, (void(*)(void))&_def }; \
>> + EXPORT_SYMBOL(__ffp_ ## _fn)
>> +
>> +static inline void ffp_set_target(const struct ffp *m, void *new_fn)
>> +{
>> + WRITE_ONCE(*m->fn, new_fn);
>> +}
>> +
>> +static inline void ffp_reset_target(const struct ffp *m)
>> +{
>> + WRITE_ONCE(*m->fn, m->default_fn);
>> +}
>> +
>> +#endif
>> +
>> +#define SET_FFP(_fn, _new) ffp_set_target(&__ffp_ ## _fn, _new)
>> +#define RESET_FFP(_fn) ffp_reset_target(&__ffp_ ## _fn)
>> +
>> +#endif
>
> I don't understand this interface. There is no wrapper for the call
> site, so how are we going to patch all call-sites when you update the
> target?
This is the generic implementation, and in this case, it is just a
function pointer which gets dereferenced and called indirectly at each
call site.
In the arch specific implementations (for ones where it matters, see
2/9), it is more like a PLT entry, which gets called from each call
site, and which can be patched to point to another function.
So we replace a single indirect call with a direct call plus a direct jump.
^ permalink raw reply
* Re: [PATCH 09/16] of: overlay: validate overlay properties #address-cells and #size-cells
From: Rob Herring @ 2018-10-05 15:07 UTC (permalink / raw)
To: Frank Rowand
Cc: devicetree, Alan Tull, linux-fpga, Pantelis Antoniou,
linux-kernel@vger.kernel.org, Moritz Fischer, Paul Mackerras,
linuxppc-dev
In-Reply-To: <1538712767-30394-10-git-send-email-frowand.list@gmail.com>
On Thu, Oct 4, 2018 at 11:14 PM <frowand.list@gmail.com> wrote:
>
> From: Frank Rowand <frank.rowand@sony.com>
>
> If overlay properties #address-cells or #size-cells are already in
> the live devicetree for any given node, then the values in the
> overlay must match the values in the live tree.
>
> If the properties are already in the live tree then there is no
> need to create a changeset entry to add them since they must
> have the same value. This reduces the memory used by the
> changeset and eliminates a possible memory leak. This is
> verified by 12 fewer warnings during the devicetree unittest,
> as the possible memory leak warnings about #address-cells and
and...?
>
> Signed-off-by: Frank Rowand <frank.rowand@sony.com>
> ---
> drivers/of/overlay.c | 38 +++++++++++++++++++++++++++++++++++---
> 1 file changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
> index 29c33a5c533f..e6fb3ffe9d93 100644
> --- a/drivers/of/overlay.c
> +++ b/drivers/of/overlay.c
> @@ -287,7 +287,12 @@ static struct property *dup_and_fixup_symbol_prop(
> * @target may be either in the live devicetree or in a new subtree that
> * is contained in the changeset.
> *
> - * Some special properties are not updated (no error returned).
> + * Some special properties are not added or updated (no error returned):
> + * "name", "phandle", "linux,phandle".
> + *
> + * Properties "#address-cells" and "#size-cells" are not updated if they
> + * are already in the live tree, but if present in the live tree, the values
> + * in the overlay must match the values in the live tree.
Perhaps this should be generalized to apply to any property? We can't
really deal with property values changing on the fly anyways.
> *
> * Update of property in symbols node is not allowed.
> *
> @@ -300,6 +305,7 @@ static int add_changeset_property(struct overlay_changeset *ovcs,
> {
> struct property *new_prop = NULL, *prop;
> int ret = 0;
> + bool check_for_non_overlay_node = false;
>
> if (!of_prop_cmp(overlay_prop->name, "name") ||
> !of_prop_cmp(overlay_prop->name, "phandle") ||
> @@ -322,13 +328,39 @@ static int add_changeset_property(struct overlay_changeset *ovcs,
> if (!new_prop)
> return -ENOMEM;
>
> - if (!prop)
> + if (!prop) {
> +
Remove the extra blank lines.
> + check_for_non_overlay_node = true;
> ret = of_changeset_add_property(&ovcs->cset, target->np,
> new_prop);
> - else
> +
> + } else if (!of_prop_cmp(prop->name, "#address-cells")) {
> +
> + if (prop->length != 4 || new_prop->length != 4 ||
> + *(u32 *)prop->value != *(u32 *)new_prop->value)
Technically these are __be32 types. This could use a helper (of_prop_val_eq).
I'm not sure we really need to validate the length here as dtc does
that (but yes, not everything is from dtc).
> + pr_err("ERROR: overlay and/or live tree #address-cells invalid in node %pOF\n",
> + target->np);
> +
> + } else if (!of_prop_cmp(prop->name, "#size-cells")) {
> +
> + if (prop->length != 4 || new_prop->length != 4 ||
> + *(u32 *)prop->value != *(u32 *)new_prop->value)
> + pr_err("ERROR: overlay and/or live tree #size-cells invalid in node %pOF\n",
> + target->np);
> +
> + } else {
> +
> + check_for_non_overlay_node = true;
> ret = of_changeset_update_property(&ovcs->cset, target->np,
> new_prop);
>
> + }
> +
> + if (check_for_non_overlay_node &&
> + !of_node_check_flag(target->np, OF_OVERLAY))
> + pr_err("WARNING: %s(), memory leak will occur if overlay removed. Property: %pOF/%s\n",
> + __func__, target->np, new_prop->name);
> +
> if (ret) {
> kfree(new_prop->name);
> kfree(new_prop->value);
> --
> Frank Rowand <frank.rowand@sony.com>
>
^ permalink raw reply
* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Andy Lutomirski @ 2018-10-05 15:08 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Jason A . Donenfeld, Catalin Marinas, Will Deacon, Samuel Neves,
Paul Mackerras, Herbert Xu, Richard Weinberger, Eric Biggers,
Ingo Molnar, Kees Cook, Arnd Bergmann, Andy Lutomirski,
Thomas Gleixner, linux-arm-kernel, Martin K. Petersen,
Ard Biesheuvel, Greg Kroah-Hartman, linux-kernel, linux-crypto,
Andrew Morton, linuxppc-dev, David S. Miller
In-Reply-To: <20181005141433.GS19272@hirez.programming.kicks-ass.net>
> On Oct 5, 2018, at 7:14 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>
>> On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
>> diff --git a/include/linux/ffp.h b/include/linux/ffp.h
>> new file mode 100644
>> index 000000000000..8fc3b4c9b38f
>> --- /dev/null
>> +++ b/include/linux/ffp.h
>> @@ -0,0 +1,43 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +
>> +#ifndef __LINUX_FFP_H
>> +#define __LINUX_FFP_H
>> +
>> +#include <linux/types.h>
>> +#include <linux/compiler.h>
>> +
>> +#ifdef CONFIG_HAVE_ARCH_FFP
>> +#include <asm/ffp.h>
>> +#else
>> +
>> +struct ffp {
>> + void (**fn)(void);
>> + void (*default_fn)(void);
>> +};
>> +
>> +#define DECLARE_FFP(_fn, _def) \
>> + extern typeof(_def) *_fn; \
>> + extern struct ffp const __ffp_ ## _fn
>> +
>> +#define DEFINE_FFP(_fn, _def) \
>> + typeof(_def) *_fn = &_def; \
>> + struct ffp const __ffp_ ## _fn \
>> + = { (void(**)(void))&_fn, (void(*)(void))&_def }; \
>> + EXPORT_SYMBOL(__ffp_ ## _fn)
>> +
>> +static inline void ffp_set_target(const struct ffp *m, void *new_fn)
>> +{
>> + WRITE_ONCE(*m->fn, new_fn);
>> +}
>> +
>> +static inline void ffp_reset_target(const struct ffp *m)
>> +{
>> + WRITE_ONCE(*m->fn, m->default_fn);
>> +}
>> +
>> +#endif
>> +
>> +#define SET_FFP(_fn, _new) ffp_set_target(&__ffp_ ## _fn, _new)
>> +#define RESET_FFP(_fn) ffp_reset_target(&__ffp_ ## _fn)
>> +
>> +#endif
>
> I don't understand this interface. There is no wrapper for the call
> site, so how are we going to patch all call-sites when you update the
> target?
I’m also confused.
Anyway, we have patchable functions on x86. They’re called PVOPs, and they’re way overcomplicated.
I’ve proposed a better way that should generate better code, be more portable, and be more maintainable. It goes like this.
To call the function, you literally just call the default implementation. It *might* be necessary to call a nonexistent wrapper to avoid annoying optimizations. At build time, the kernel is built with relocations, so the object files contain relocation entries for the call. We collect these entries into a table. If we’re using the “nonexistent wrapper” approach, we can link in a .S or linker script to alias them to the default implementation.
To patch them, we just patch them. It can’t necessarily be done concurrently because nothing forces the right alignment. But we can do it at boot time and module load time. (Maybe we can patch at runtime on architectures with appropriate instruction alignment. Or we ask gcc for an extension to align calls to a function.)
Most of the machinery already exists: this is roughly how the module loader resolves calls outside of a module.
^ permalink raw reply
* Re: [PATCH] memblock: stop using implicit alignement to SMP_CACHE_BYTES
From: Mike Rapoport @ 2018-10-05 15:05 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linux-mm
Cc: linux-mips, linux-m68k, Michal Hocko, linux-ia64, Catalin Marinas,
Richard Weinberger, Russell King, Ingo Molnar, Geert Uytterhoeven,
Matt Turner, linux-um, Thomas Gleixner, Guan Xuetao,
linux-arm-kernel, Chris Zankel, Michal Simek, Tony Luck,
linux-kernel, Paul Burton, linux-alpha, Andrew Morton,
linuxppc-dev
In-Reply-To: <8891277c7de92e93d3bfc409df95810ee6f103cd.camel@kernel.crashing.org>
On October 5, 2018 6:25:38 AM GMT+03:00, Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>On Fri, 2018-10-05 at 00:07 +0300, Mike Rapoport wrote:
>> When a memblock allocation APIs are called with align = 0, the
>alignment is
>> implicitly set to SMP_CACHE_BYTES.
>>
>> Replace all such uses of memblock APIs with the 'align' parameter
>explicitly
>> set to SMP_CACHE_BYTES and stop implicit alignment assignment in the
>> memblock internal allocation functions.
>>
>> For the case when memblock APIs are used via helper functions, e.g.
>like
>> iommu_arena_new_node() in Alpha, the helper functions were detected
>with
>> Coccinelle's help and then manually examined and updated where
>appropriate.
>>
>> The direct memblock APIs users were updated using the semantic patch
>below:
>
>What is the purpose of this ? It sounds rather counter-intuitive...
Why?
I think it actually more intuitive to explicitly set alignment to SMP_CACHE_BYTES rather than use align = 0 because deeply inside allocator it will be implicitly reset to SMP_CACHE_BYTES...
>Ben.
--
Sincerely yours,
Mike.
^ permalink raw reply
* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Ard Biesheuvel @ 2018-10-05 15:24 UTC (permalink / raw)
To: Andy Lutomirski
Cc: Jason A . Donenfeld, Peter Zijlstra, Catalin Marinas, Will Deacon,
Samuel Neves, Paul Mackerras, Herbert Xu, Richard Weinberger,
Eric Biggers, Ingo Molnar, Kees Cook, Arnd Bergmann,
Andy Lutomirski, Thomas Gleixner, linux-arm-kernel,
Martin K. Petersen, Greg Kroah-Hartman, Linux Kernel Mailing List,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Andrew Morton,
linuxppc-dev, David S. Miller
In-Reply-To: <9E0E08C8-0DFC-4E50-A4FA-73208835EF9E@amacapital.net>
On 5 October 2018 at 17:08, Andy Lutomirski <luto@amacapital.net> wrote:
>
>
>> On Oct 5, 2018, at 7:14 AM, Peter Zijlstra <peterz@infradead.org> wrote:
>>
>>> On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
>>> diff --git a/include/linux/ffp.h b/include/linux/ffp.h
>>> new file mode 100644
>>> index 000000000000..8fc3b4c9b38f
>>> --- /dev/null
>>> +++ b/include/linux/ffp.h
>>> @@ -0,0 +1,43 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>> +
>>> +#ifndef __LINUX_FFP_H
>>> +#define __LINUX_FFP_H
>>> +
>>> +#include <linux/types.h>
>>> +#include <linux/compiler.h>
>>> +
>>> +#ifdef CONFIG_HAVE_ARCH_FFP
>>> +#include <asm/ffp.h>
>>> +#else
>>> +
>>> +struct ffp {
>>> + void (**fn)(void);
>>> + void (*default_fn)(void);
>>> +};
>>> +
>>> +#define DECLARE_FFP(_fn, _def) \
>>> + extern typeof(_def) *_fn; \
>>> + extern struct ffp const __ffp_ ## _fn
>>> +
>>> +#define DEFINE_FFP(_fn, _def) \
>>> + typeof(_def) *_fn = &_def; \
>>> + struct ffp const __ffp_ ## _fn \
>>> + = { (void(**)(void))&_fn, (void(*)(void))&_def }; \
>>> + EXPORT_SYMBOL(__ffp_ ## _fn)
>>> +
>>> +static inline void ffp_set_target(const struct ffp *m, void *new_fn)
>>> +{
>>> + WRITE_ONCE(*m->fn, new_fn);
>>> +}
>>> +
>>> +static inline void ffp_reset_target(const struct ffp *m)
>>> +{
>>> + WRITE_ONCE(*m->fn, m->default_fn);
>>> +}
>>> +
>>> +#endif
>>> +
>>> +#define SET_FFP(_fn, _new) ffp_set_target(&__ffp_ ## _fn, _new)
>>> +#define RESET_FFP(_fn) ffp_reset_target(&__ffp_ ## _fn)
>>> +
>>> +#endif
>>
>> I don't understand this interface. There is no wrapper for the call
>> site, so how are we going to patch all call-sites when you update the
>> target?
>
> I’m also confused.
>
> Anyway, we have patchable functions on x86. They’re called PVOPs, and they’re way overcomplicated.
>
> I’ve proposed a better way that should generate better code, be more portable, and be more maintainable. It goes like this.
>
> To call the function, you literally just call the default implementation. It *might* be necessary to call a nonexistent wrapper to avoid annoying optimizations. At build time, the kernel is built with relocations, so the object files contain relocation entries for the call. We collect these entries into a table. If we’re using the “nonexistent wrapper” approach, we can link in a .S or linker script to alias them to the default implementation.
>
> To patch them, we just patch them. It can’t necessarily be done concurrently because nothing forces the right alignment. But we can do it at boot time and module load time. (Maybe we can patch at runtime on architectures with appropriate instruction alignment. Or we ask gcc for an extension to align calls to a function.)
>
> Most of the machinery already exists: this is roughly how the module loader resolves calls outside of a module.
Yeah nothing is ever simple on x86 :-(
So are you saying the approach i use in patch #2 (which would
translate to emitting a jmpq instruction pointing to the default
implementation, and patching it at runtime to point elsewhere) would
not fly on x86?
^ permalink raw reply
* Re: [RFC PATCH 1/9] kernel: add support for patchable function pointers
From: Andy Lutomirski @ 2018-10-05 16:58 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Jason A. Donenfeld, Peter Zijlstra, Catalin Marinas, Will Deacon,
Samuel Neves, Paul Mackerras, Herbert Xu, Richard Weinberger,
Eric Biggers, Ingo Molnar, Kees Cook, Arnd Bergmann,
Andrew Lutomirski, Thomas Gleixner, linux-arm-kernel,
Martin K. Petersen, Greg KH, LKML, Linux Crypto Mailing List,
Andrew Morton, linuxppc-dev, David S. Miller
In-Reply-To: <CAKv+Gu9z503ZJXcsG+9Ys240BZiB-+GB=kNY4VGWpjvdzN4JtA@mail.gmail.com>
On Fri, Oct 5, 2018 at 8:24 AM Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>
> On 5 October 2018 at 17:08, Andy Lutomirski <luto@amacapital.net> wrote:
> >
> >
> >> On Oct 5, 2018, at 7:14 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> >>
> >>> On Fri, Oct 05, 2018 at 10:13:25AM +0200, Ard Biesheuvel wrote:
> >>> diff --git a/include/linux/ffp.h b/include/linux/ffp.h
> >>> new file mode 100644
> >>> index 000000000000..8fc3b4c9b38f
> >>> --- /dev/null
> >>> +++ b/include/linux/ffp.h
> >>> @@ -0,0 +1,43 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>> +
> >>> +#ifndef __LINUX_FFP_H
> >>> +#define __LINUX_FFP_H
> >>> +
> >>> +#include <linux/types.h>
> >>> +#include <linux/compiler.h>
> >>> +
> >>> +#ifdef CONFIG_HAVE_ARCH_FFP
> >>> +#include <asm/ffp.h>
> >>> +#else
> >>> +
> >>> +struct ffp {
> >>> + void (**fn)(void);
> >>> + void (*default_fn)(void);
> >>> +};
> >>> +
> >>> +#define DECLARE_FFP(_fn, _def) \
> >>> + extern typeof(_def) *_fn; \
> >>> + extern struct ffp const __ffp_ ## _fn
> >>> +
> >>> +#define DEFINE_FFP(_fn, _def) \
> >>> + typeof(_def) *_fn = &_def; \
> >>> + struct ffp const __ffp_ ## _fn \
> >>> + = { (void(**)(void))&_fn, (void(*)(void))&_def }; \
> >>> + EXPORT_SYMBOL(__ffp_ ## _fn)
> >>> +
> >>> +static inline void ffp_set_target(const struct ffp *m, void *new_fn)
> >>> +{
> >>> + WRITE_ONCE(*m->fn, new_fn);
> >>> +}
> >>> +
> >>> +static inline void ffp_reset_target(const struct ffp *m)
> >>> +{
> >>> + WRITE_ONCE(*m->fn, m->default_fn);
> >>> +}
> >>> +
> >>> +#endif
> >>> +
> >>> +#define SET_FFP(_fn, _new) ffp_set_target(&__ffp_ ## _fn, _new)
> >>> +#define RESET_FFP(_fn) ffp_reset_target(&__ffp_ ## _fn)
> >>> +
> >>> +#endif
> >>
> >> I don't understand this interface. There is no wrapper for the call
> >> site, so how are we going to patch all call-sites when you update the
> >> target?
> >
> > I’m also confused.
> >
> > Anyway, we have patchable functions on x86. They’re called PVOPs, and they’re way overcomplicated.
> >
> > I’ve proposed a better way that should generate better code, be more portable, and be more maintainable. It goes like this.
> >
> > To call the function, you literally just call the default implementation. It *might* be necessary to call a nonexistent wrapper to avoid annoying optimizations. At build time, the kernel is built with relocations, so the object files contain relocation entries for the call. We collect these entries into a table. If we’re using the “nonexistent wrapper” approach, we can link in a .S or linker script to alias them to the default implementation.
> >
> > To patch them, we just patch them. It can’t necessarily be done concurrently because nothing forces the right alignment. But we can do it at boot time and module load time. (Maybe we can patch at runtime on architectures with appropriate instruction alignment. Or we ask gcc for an extension to align calls to a function.)
> >
> > Most of the machinery already exists: this is roughly how the module loader resolves calls outside of a module.
>
> Yeah nothing is ever simple on x86 :-(
>
> So are you saying the approach i use in patch #2 (which would
> translate to emitting a jmpq instruction pointing to the default
> implementation, and patching it at runtime to point elsewhere) would
> not fly on x86?
After getting some more sleep, I'm obviously wrong. The
text_poke_bp() mechanism will work. It's just really slow.
Let me try to summarize some of the issues. First, when emitting
jumps and calls from inline asm on x86, there are a few considerations
that are annoying:
1. Following the x86_64 ABI calling conventions is basically
impossible. x86_64 requires a 128-byte redzone and 16-byte stack
alignment. After much discussion a while back, we decided that it was
flat-out impossible on current gcc to get the stack pointer aligned in
a known manner in an inline asm statement. Instead, if we actually
need alignment, we need to align manually. Fortunately, the kernel is
built with an override that forces only 8-byte alignment (on *most*
GCC versions). But for crypto in particular, it sucks extra, since
the crypto code is basically the only thing in the kernel that
actually wants 16-byte alignment. I don't think this is a huge
problem in practice, but it's annoying. And the kernel is built
without a redzone.
2. On x86_64, depending on config, we either need frame pointers or
ORC. ORC is no big deal -- it Just Works (tm). Frame pointers need
extra asm hackery. It's doable, but it's still annoying.
3. Actually getting the asm constraints right to do what a C
programmer expects is distinctly nontrivial. I just fixed an
extremely longstanding bug in the vDSO code in which the asm
constraints for the syscall fallback were wrong in such a way that GCC
didn't notice that the fallback wrote to its output parameter.
Whoops.
And having all this asm hackery per architecture is ugly and annoying.
So my suggestion is to do it like a regular relocation. Call a
function the normal way (make it literally be a C function and call
it), and rig up the noinline and noclone attributes and whatever else
is needed to make sure that it's a *relocatable* call. Then the
toolchain emits ELF relocations saying exactly what part of the text
needs patching, and we can patch it at runtime. On x86, this is a bit
extra annoying because we can't fully reliably parse backwards to find
the beginning of the instruction, but objtool could doit.
And then we get something that is mostly arch-neutral! Because surely
ARM can also use a relocation-based mechanism.
I will generally object to x86 containing more than one
inline-asm-hackery-based patchable call mechanism, which your series
will add. I would *love* to see a non-inline-asm one, and then we
could move most of the x86 paravirt crap over to use it for a big win
in readability and maintainability.
--Andy
^ permalink raw reply
* [PATCH 00/36] Devicetree schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
The current DT binding documentation is not ideal as it is just free form
text with at most only a loose structure. This makes reviewing bindings a
manual process. The bindings are often duplicating information that's
already defined elsewhere and missing information one would need to
validate a DTS file. The examples in binding documents are not built and
a source of lots of typos sometimes found in review and sometimes not.
Secondly, there's no verification that DTS files match what the
documentation says. While dtc does do some checking (and has gained more
recently), it can't do per binding checks as it would have to understand
thousands of compatible strings to match on.
There's been a number of proposals over the years to address validation.
They've all suffered from inventing their own validation language and the
effort it would take to fully define and flush out a validation language.
Enter json-schema. The language has a defined specification, maps well to
DT data, and there are numerous existing tools which can be leveraged.
The actual DT schema doc files are stored as YAML using only a JSON
compatible subset. YAML is considered more human readable allowing
comments for example.
This series adds the build support, some documentation, and converts
some bindings (mostly ARM board/soc bindings). The tools, core schema,
and meta-schema are in a separate repository[1]. This might eventually
be integrated with dtc or added to the kernel, but for now I plan to
keep it separate.
Future plans/ideas:
- Validate examples against the schema. Currently, they are just built
with dtc.
- Support single targets in addition to validating all enabled dtb
targets.
- Better control of which schemas to use for validation such as core
only or specific lists of schemas. This will make for more easily
testing new schema and filtering warnings.
- Printing out nodes without any specific schema (i.e. missing schema).
This series is dependent on the dt/next branch and is available here[2].
The branch also has a doc2yaml script which can help convert binding
files. It's not perfect, but works pretty well considering the input is
free form text.
Rob
[1] https://github.com/robherring/yaml-bindings
[2] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git yaml-bindings
Rob Herring (36):
dt-bindings: arm: alpine: Move CPU control related binding to
cpu-enable-method/al,alpine-smp
dt-bindings: arm: amlogic: Move 'amlogic,meson-gx-ao-secure' binding
to its own file
dt-bindings: arm: atmel: Move various sys registers out of SoC binding
doc
dt-bindings: arm: fsl: Move DCFG and SCFG bindings to their own docs
dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc
dt-bindings: arm: zte: Move sysctrl bindings to their own doc
kbuild: Add support for DT binding schema checks
dt-bindings: Add a writing DT schemas how-to and annotated example
dt-bindings: Convert trivial-devices.txt to json-schema
dt-bindings: altera: Convert clkmgr binding to json-schema
dt-bindings: timer: Convert ARM timer bindings to json-schema
dt-bindings: arm: Convert cpu binding to json-schema
dt-bindings: arm: Convert PMU binding to json-schema
dt-bindings: arm: Convert primecell binding to json-schema
dt-bindings: arm: Convert Actions Semi bindings to jsonschema
dt-bindings: arm: Convert Alpine board/soc bindings to json-schema
dt-bindings: arm: Convert Altera board/soc bindings to json-schema
dt-bindings: arm: Convert Amlogic board/soc bindings to json-schema
dt-bindings: arm: Convert Atmel board/soc bindings to json-schema
dt-bindings: arm: Convert Calxeda board/soc bindings to json-schema
dt-bindings: arm: Convert TI davinci board/soc bindings to json-schema
dt-bindings: arm: Convert FSL board/soc bindings to json-schema
dt-bindings: arm: Convert MediaTek board/soc bindings to json-schema
dt-bindings: arm: Convert TI nspire board/soc bindings to json-schema
dt-bindings: arm: Convert Oxford Semi board/soc bindings to
json-schema
dt-bindings: arm: Convert QCom board/soc bindings to json-schema
dt-bindings: arm: Convert Realtek board/soc bindings to json-schema
dt-bindings: arm: Convert Rockchip board/soc bindings to json-schema
dt-bindings: arm: Convert Renesas board/soc bindings to json-schema
dt-bindings: arm: Convert CSR SiRF board/soc bindings to json-schema
dt-bindings: arm: Convert SPEAr board/soc bindings to json-schema
dt-bindings: arm: Convert ST STi board/soc bindings to json-schema
dt-bindings: arm: Convert Tegra board/soc bindings to json-schema
dt-bindings: arm: Convert VIA board/soc bindings to json-schema
dt-bindings: arm: Convert Xilinx board/soc bindings to json-schema
dt-bindings: arm: Convert ZTE board/soc bindings to json-schema
.gitignore | 1 +
Documentation/Makefile | 2 +-
Documentation/devicetree/bindings/.gitignore | 2 +
Documentation/devicetree/bindings/Makefile | 30 ++
.../devicetree/bindings/arm/actions.txt | 56 --
.../devicetree/bindings/arm/actions.yaml | 34 ++
.../devicetree/bindings/arm/al,alpine.txt | 88 ---
.../devicetree/bindings/arm/al,alpine.yaml | 21 +
.../devicetree/bindings/arm/altera.txt | 14 -
.../devicetree/bindings/arm/altera.yaml | 20 +
.../arm/altera/socfpga-clk-manager.txt | 11 -
.../arm/altera/socfpga-clk-manager.yaml | 30 ++
.../devicetree/bindings/arm/amlogic.txt | 131 -----
.../devicetree/bindings/arm/amlogic.yaml | 104 ++++
.../amlogic/amlogic,meson-gx-ao-secure.txt | 28 +
.../devicetree/bindings/arm/armadeus.txt | 6 -
.../devicetree/bindings/arm/atmel-at91.yaml | 132 +++++
.../arm/{atmel-at91.txt => atmel-sysregs.txt} | 73 +--
Documentation/devicetree/bindings/arm/bhf.txt | 6 -
.../devicetree/bindings/arm/calxeda.txt | 15 -
.../devicetree/bindings/arm/calxeda.yaml | 22 +
.../bindings/arm/compulab-boards.txt | 25 -
.../arm/cpu-enable-method/al,alpine-smp | 34 +-
.../devicetree/bindings/arm/cpus.txt | 490 -----------------
.../devicetree/bindings/arm/cpus.yaml | 503 ++++++++++++++++++
.../devicetree/bindings/arm/davinci.txt | 25 -
.../arm/freescale/fsl,layerscape-dcfg.txt | 19 +
.../arm/freescale/fsl,layerscape-scfg.txt | 19 +
Documentation/devicetree/bindings/arm/fsl.txt | 224 --------
.../devicetree/bindings/arm/fsl.yaml | 166 ++++++
.../devicetree/bindings/arm/i2se.txt | 22 -
.../devicetree/bindings/arm/mediatek.txt | 79 ---
.../devicetree/bindings/arm/mediatek.yaml | 85 +++
.../devicetree/bindings/arm/nspire.txt | 14 -
.../devicetree/bindings/arm/olimex.txt | 10 -
.../devicetree/bindings/arm/oxnas.txt | 14 -
.../devicetree/bindings/arm/oxnas.yaml | 25 +
Documentation/devicetree/bindings/arm/pmu.txt | 70 ---
.../devicetree/bindings/arm/pmu.yaml | 96 ++++
.../devicetree/bindings/arm/primecell.txt | 46 --
.../devicetree/bindings/arm/primecell.yaml | 35 ++
.../devicetree/bindings/arm/qcom.txt | 57 --
.../devicetree/bindings/arm/qcom.yaml | 125 +++++
.../devicetree/bindings/arm/realtek.txt | 22 -
.../devicetree/bindings/arm/realtek.yaml | 25 +
.../devicetree/bindings/arm/renesas,prr.txt | 18 +
.../devicetree/bindings/arm/rockchip.txt | 220 --------
.../devicetree/bindings/arm/rockchip.yaml | 242 +++++++++
.../devicetree/bindings/arm/shmobile.txt | 161 ------
.../devicetree/bindings/arm/shmobile.yaml | 205 +++++++
.../devicetree/bindings/arm/sirf.txt | 11 -
.../devicetree/bindings/arm/sirf.yaml | 27 +
.../devicetree/bindings/arm/spear.txt | 26 -
.../devicetree/bindings/arm/spear.yaml | 25 +
Documentation/devicetree/bindings/arm/sti.txt | 23 -
.../devicetree/bindings/arm/sti.yaml | 23 +
.../devicetree/bindings/arm/technologic.txt | 23 -
.../devicetree/bindings/arm/tegra.txt | 60 ---
.../devicetree/bindings/arm/tegra.yaml | 88 +++
.../devicetree/bindings/arm/ti/nspire.yaml | 24 +
.../bindings/arm/ti/ti,davinci.yaml | 26 +
.../devicetree/bindings/arm/vt8500.txt | 22 -
.../devicetree/bindings/arm/vt8500.yaml | 23 +
.../devicetree/bindings/arm/xilinx.txt | 83 ---
.../devicetree/bindings/arm/xilinx.yaml | 81 +++
.../bindings/arm/{zte.txt => zte-sysctrl.txt} | 15 +-
.../devicetree/bindings/arm/zte.yaml | 26 +
.../devicetree/bindings/example-schema.yaml | 155 ++++++
.../bindings/timer/arm,arch_timer.txt | 112 ----
.../bindings/timer/arm,arch_timer.yaml | 103 ++++
.../bindings/timer/arm,arch_timer_mmio.yaml | 120 +++++
.../bindings/timer/arm,global_timer.txt | 27 -
.../bindings/timer/arm,global_timer.yaml | 46 ++
.../devicetree/bindings/trivial-devices.txt | 201 -------
.../devicetree/bindings/trivial-devices.yaml | 414 ++++++++++++++
Documentation/devicetree/writing-schema.md | 111 ++++
Makefile | 8 +-
scripts/Makefile.lib | 24 +-
78 files changed, 3344 insertions(+), 2485 deletions(-)
create mode 100644 Documentation/devicetree/bindings/.gitignore
create mode 100644 Documentation/devicetree/bindings/Makefile
delete mode 100644 Documentation/devicetree/bindings/arm/actions.txt
create mode 100644 Documentation/devicetree/bindings/arm/actions.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/al,alpine.txt
create mode 100644 Documentation/devicetree/bindings/arm/al,alpine.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/altera.txt
create mode 100644 Documentation/devicetree/bindings/arm/altera.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/amlogic.txt
create mode 100644 Documentation/devicetree/bindings/arm/amlogic.yaml
create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
delete mode 100644 Documentation/devicetree/bindings/arm/armadeus.txt
create mode 100644 Documentation/devicetree/bindings/arm/atmel-at91.yaml
rename Documentation/devicetree/bindings/arm/{atmel-at91.txt => atmel-sysregs.txt} (67%)
delete mode 100644 Documentation/devicetree/bindings/arm/bhf.txt
delete mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
create mode 100644 Documentation/devicetree/bindings/arm/calxeda.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/compulab-boards.txt
delete mode 100644 Documentation/devicetree/bindings/arm/cpus.txt
create mode 100644 Documentation/devicetree/bindings/arm/cpus.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/davinci.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
delete mode 100644 Documentation/devicetree/bindings/arm/fsl.txt
create mode 100644 Documentation/devicetree/bindings/arm/fsl.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/i2se.txt
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/nspire.txt
delete mode 100644 Documentation/devicetree/bindings/arm/olimex.txt
delete mode 100644 Documentation/devicetree/bindings/arm/oxnas.txt
create mode 100644 Documentation/devicetree/bindings/arm/oxnas.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt
create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/primecell.txt
create mode 100644 Documentation/devicetree/bindings/arm/primecell.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/qcom.txt
create mode 100644 Documentation/devicetree/bindings/arm/qcom.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/realtek.txt
create mode 100644 Documentation/devicetree/bindings/arm/realtek.yaml
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt
delete mode 100644 Documentation/devicetree/bindings/arm/rockchip.txt
create mode 100644 Documentation/devicetree/bindings/arm/rockchip.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/shmobile.txt
create mode 100644 Documentation/devicetree/bindings/arm/shmobile.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/sirf.txt
create mode 100644 Documentation/devicetree/bindings/arm/sirf.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/spear.txt
create mode 100644 Documentation/devicetree/bindings/arm/spear.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/sti.txt
create mode 100644 Documentation/devicetree/bindings/arm/sti.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/technologic.txt
delete mode 100644 Documentation/devicetree/bindings/arm/tegra.txt
create mode 100644 Documentation/devicetree/bindings/arm/tegra.yaml
create mode 100644 Documentation/devicetree/bindings/arm/ti/nspire.yaml
create mode 100644 Documentation/devicetree/bindings/arm/ti/ti,davinci.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/vt8500.txt
create mode 100644 Documentation/devicetree/bindings/arm/vt8500.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/xilinx.txt
create mode 100644 Documentation/devicetree/bindings/arm/xilinx.yaml
rename Documentation/devicetree/bindings/arm/{zte.txt => zte-sysctrl.txt} (62%)
create mode 100644 Documentation/devicetree/bindings/arm/zte.yaml
create mode 100644 Documentation/devicetree/bindings/example-schema.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.yaml
delete mode 100644 Documentation/devicetree/bindings/trivial-devices.txt
create mode 100644 Documentation/devicetree/bindings/trivial-devices.yaml
create mode 100644 Documentation/devicetree/writing-schema.md
--
2.17.1
^ permalink raw reply
* [PATCH 01/36] dt-bindings: arm: alpine: Move CPU control related binding to cpu-enable-method/al, alpine-smp
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Frank Rowand, Antoine Tenart,
Jonathan Cameron, Tsahee Zidenberg
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
It is best practice to have 1 binding per file, so board level bindings
should be separate for various misc SoC bindings. Move the Alpine CPU
control to al,alpine-smp and we can also remove a cross reference.
Cc: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/al,alpine.txt | 72 -------------------
.../arm/cpu-enable-method/al,alpine-smp | 34 ++++++++-
2 files changed, 31 insertions(+), 75 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/al,alpine.txt b/Documentation/devicetree/bindings/arm/al,alpine.txt
index f404a4f9b165..d00debe2e86f 100644
--- a/Documentation/devicetree/bindings/arm/al,alpine.txt
+++ b/Documentation/devicetree/bindings/arm/al,alpine.txt
@@ -14,75 +14,3 @@ compatible: must contain "al,alpine"
...
}
-
-* CPU node:
-
-The Alpine platform includes cortex-a15 cores.
-enable-method: must be "al,alpine-smp" to allow smp [1]
-
-Example:
-
-cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- enable-method = "al,alpine-smp";
-
- cpu@0 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <0>;
- };
-
- cpu@1 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <1>;
- };
-
- cpu@2 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <2>;
- };
-
- cpu@3 {
- compatible = "arm,cortex-a15";
- device_type = "cpu";
- reg = <3>;
- };
-};
-
-
-* Alpine CPU resume registers
-
-The CPU resume register are used to define required resume address after
-reset.
-
-Properties:
-- compatible : Should contain "al,alpine-cpu-resume".
-- reg : Offset and length of the register set for the device
-
-Example:
-
-cpu_resume {
- compatible = "al,alpine-cpu-resume";
- reg = <0xfbff5ed0 0x30>;
-};
-
-* Alpine System-Fabric Service Registers
-
-The System-Fabric Service Registers allow various operation on CPU and
-system fabric, like powering CPUs off.
-
-Properties:
-- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
-- reg : Offset and length of the register set for the device
-
-Example:
-
-nb_service {
- compatible = "al,alpine-sysfabric-service", "syscon";
- reg = <0xfb070000 0x10000>;
-};
-
-[1] arm/cpu-enable-method/al,alpine-smp
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp
index c2e0cc5e4cfd..35e5afb6d9ad 100644
--- a/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp
+++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/al,alpine-smp
@@ -14,7 +14,28 @@ Related properties: (none)
Note:
This enable method requires valid nodes compatible with
-"al,alpine-cpu-resume" and "al,alpine-nb-service"[1].
+"al,alpine-cpu-resume" and "al,alpine-nb-service".
+
+
+* Alpine CPU resume registers
+
+The CPU resume register are used to define required resume address after
+reset.
+
+Properties:
+- compatible : Should contain "al,alpine-cpu-resume".
+- reg : Offset and length of the register set for the device
+
+
+* Alpine System-Fabric Service Registers
+
+The System-Fabric Service Registers allow various operation on CPU and
+system fabric, like powering CPUs off.
+
+Properties:
+- compatible : Should contain "al,alpine-sysfabric-service" and "syscon".
+- reg : Offset and length of the register set for the device
+
Example:
@@ -48,5 +69,12 @@ cpus {
};
};
---
-[1] arm/al,alpine.txt
+cpu_resume {
+ compatible = "al,alpine-cpu-resume";
+ reg = <0xfbff5ed0 0x30>;
+};
+
+nb_service {
+ compatible = "al,alpine-sysfabric-service", "syscon";
+ reg = <0xfb070000 0x10000>;
+};
--
2.17.1
^ permalink raw reply related
* [PATCH 02/36] dt-bindings: arm: amlogic: Move 'amlogic, meson-gx-ao-secure' binding to its own file
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Kevin Hilman, Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
Carlo Caione, Mark Brown, Geert Uytterhoeven, Olof Johansson,
linux-amlogic, Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
It is best practice to have 1 binding per file, so board level bindings
should be separate for various misc SoC bindings.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Carlo Caione <carlo@caione.org>
Cc: Kevin Hilman <khilman@baylibre.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-amlogic@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/amlogic.txt | 29 -------------------
.../amlogic/amlogic,meson-gx-ao-secure.txt | 28 ++++++++++++++++++
2 files changed, 28 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index b5c2b5c35766..2f2d01a00c54 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -100,32 +100,3 @@ Board compatible values (alphabetically, grouped by SoC):
- "tronsmart,vega-s96" (Meson gxm s912)
- "amlogic,s400" (Meson axg a113d)
-
-Amlogic Meson Firmware registers Interface
-------------------------------------------
-
-The Meson SoCs have a register bank with status and data shared with the
-secure firmware.
-
-Required properties:
- - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
-
-Properties should indentify components of this register interface :
-
-Meson GX SoC Information
-------------------------
-A firmware register encodes the SoC type, package and revision information on
-the Meson GX SoCs.
-If present, the following property should be added :
-
-Optional properties:
- - amlogic,has-chip-id: If present, the interface gives the current SoC version.
-
-Example
--------
-
-ao-secure@140 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x140 0x0 0x140>;
- amlogic,has-chip-id;
-};
diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
new file mode 100644
index 000000000000..c67d9f48fb91
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
@@ -0,0 +1,28 @@
+Amlogic Meson Firmware registers Interface
+------------------------------------------
+
+The Meson SoCs have a register bank with status and data shared with the
+secure firmware.
+
+Required properties:
+ - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
+
+Properties should indentify components of this register interface :
+
+Meson GX SoC Information
+------------------------
+A firmware register encodes the SoC type, package and revision information on
+the Meson GX SoCs.
+If present, the following property should be added :
+
+Optional properties:
+ - amlogic,has-chip-id: If present, the interface gives the current SoC version.
+
+Example
+-------
+
+ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x0 0x140 0x0 0x140>;
+ amlogic,has-chip-id;
+};
--
2.17.1
^ permalink raw reply related
* [PATCH 03/36] dt-bindings: arm: atmel: Move various sys registers out of SoC binding doc
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Alexandre Belloni, Kumar Gala,
Grant Likely, Arnd Bergmann, Linus Walleij, Pantelis Antoniou,
Nicolas Ferre, Bjorn Andersson, Mark Brown, Geert Uytterhoeven,
Olof Johansson, Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
In preparation to convert board-level bindings to json-schema, move
various misc SoC bindings out to their own file.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/atmel-at91.txt | 170 -----------------
.../devicetree/bindings/arm/atmel-sysregs.txt | 171 ++++++++++++++++++
2 files changed, 171 insertions(+), 170 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/atmel-sysregs.txt
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 31220b54d85d..4bf1b4da7659 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -70,173 +70,3 @@ compatible: must be one of:
- "atmel,samv71q19"
- "atmel,samv71q20"
- "atmel,samv71q21"
-
-Chipid required properties:
-- compatible: Should be "atmel,sama5d2-chipid"
-- reg : Should contain registers location and length
-
-PIT Timer required properties:
-- compatible: Should be "atmel,at91sam9260-pit"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the PIT which is the IRQ line
- shared across all System Controller members.
-
-System Timer (ST) required properties:
-- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
-- reg: Should contain registers location and length
-- interrupts: Should contain interrupt for the ST which is the IRQ line
- shared across all System Controller members.
-- clocks: phandle to input clock.
-Its subnodes can be:
-- watchdog: compatible should be "atmel,at91rm9200-wdt"
-
-RSTC Reset Controller required properties:
-- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
-- reg: Should contain registers location and length
-- clocks: phandle to input clock.
-
-Example:
-
- rstc@fffffd00 {
- compatible = "atmel,at91sam9260-rstc";
- reg = <0xfffffd00 0x10>;
- clocks = <&clk32k>;
- };
-
-RAMC SDRAM/DDR Controller required properties:
-- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
- "atmel,at91sam9260-sdramc",
- "atmel,at91sam9g45-ddramc",
- "atmel,sama5d3-ddramc",
-- reg: Should contain registers location and length
-
-Examples:
-
- ramc0: ramc@ffffe800 {
- compatible = "atmel,at91sam9g45-ddramc";
- reg = <0xffffe800 0x200>;
- };
-
-SHDWC Shutdown Controller
-
-required properties:
-- compatible: Should be "atmel,<chip>-shdwc".
- <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
-- reg: Should contain registers location and length
-- clocks: phandle to input clock.
-
-optional properties:
-- atmel,wakeup-mode: String, operation mode of the wakeup mode.
- Supported values are: "none", "high", "low", "any".
-- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
-
-optional at91sam9260 properties:
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9rl properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
-
-optional at91sam9x5 properties:
-- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
-
-Example:
-
- shdwc@fffffd10 {
- compatible = "atmel,at91sam9260-shdwc";
- reg = <0xfffffd10 0x10>;
- clocks = <&clk32k>;
- };
-
-SHDWC SAMA5D2-Compatible Shutdown Controller
-
-1) shdwc node
-
-required properties:
-- compatible: should be "atmel,sama5d2-shdwc".
-- reg: should contain registers location and length
-- clocks: phandle to input clock.
-- #address-cells: should be one. The cell is the wake-up input index.
-- #size-cells: should be zero.
-
-optional properties:
-
-- debounce-delay-us: minimum wake-up inputs debouncer period in
- microseconds. It's usually a board-related property.
-- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
-
-The node contains child nodes for each wake-up input that the platform uses.
-
-2) input nodes
-
-Wake-up input nodes are usually described in the "board" part of the Device
-Tree. Note also that input 0 is linked to the wake-up pin and is frequently
-used.
-
-Required properties:
-- reg: should contain the wake-up input index [0 - 15].
-
-Optional properties:
-- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
- by the child, forces the wake-up of the core power supply on a high level.
- The default is to be active low.
-
-Example:
-
-On the SoC side:
- shdwc@f8048010 {
- compatible = "atmel,sama5d2-shdwc";
- reg = <0xf8048010 0x10>;
- clocks = <&clk32k>;
- #address-cells = <1>;
- #size-cells = <0>;
- atmel,wakeup-rtc-timer;
- };
-
-On the board side:
- shdwc@f8048010 {
- debounce-delay-us = <976>;
-
- input@0 {
- reg = <0>;
- };
-
- input@1 {
- reg = <1>;
- atmel,wakeup-active-high;
- };
- };
-
-Special Function Registers (SFR)
-
-Special Function Registers (SFR) manage specific aspects of the integrated
-memory, bridge implementations, processor and other functionality not controlled
-elsewhere.
-
-required properties:
-- compatible: Should be "atmel,<chip>-sfr", "syscon" or
- "atmel,<chip>-sfrbu", "syscon"
- <chip> can be "sama5d3", "sama5d4" or "sama5d2".
-- reg: Should contain registers location and length
-
- sfr@f0038000 {
- compatible = "atmel,sama5d3-sfr", "syscon";
- reg = <0xf0038000 0x60>;
- };
-
-Security Module (SECUMOD)
-
-The Security Module macrocell provides all necessary secure functions to avoid
-voltage, temperature, frequency and mechanical attacks on the chip. It also
-embeds secure memories that can be scrambled
-
-required properties:
-- compatible: Should be "atmel,<chip>-secumod", "syscon".
- <chip> can be "sama5d2".
-- reg: Should contain registers location and length
-
- secumod@fc040000 {
- compatible = "atmel,sama5d2-secumod", "syscon";
- reg = <0xfc040000 0x100>;
- };
diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
new file mode 100644
index 000000000000..4b96608ad692
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt
@@ -0,0 +1,171 @@
+Atmel system registers
+
+Chipid required properties:
+- compatible: Should be "atmel,sama5d2-chipid"
+- reg : Should contain registers location and length
+
+PIT Timer required properties:
+- compatible: Should be "atmel,at91sam9260-pit"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the PIT which is the IRQ line
+ shared across all System Controller members.
+
+System Timer (ST) required properties:
+- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd"
+- reg: Should contain registers location and length
+- interrupts: Should contain interrupt for the ST which is the IRQ line
+ shared across all System Controller members.
+- clocks: phandle to input clock.
+Its subnodes can be:
+- watchdog: compatible should be "atmel,at91rm9200-wdt"
+
+RSTC Reset Controller required properties:
+- compatible: Should be "atmel,<chip>-rstc".
+ <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
+- reg: Should contain registers location and length
+- clocks: phandle to input clock.
+
+Example:
+
+ rstc@fffffd00 {
+ compatible = "atmel,at91sam9260-rstc";
+ reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
+ };
+
+RAMC SDRAM/DDR Controller required properties:
+- compatible: Should be "atmel,at91rm9200-sdramc", "syscon"
+ "atmel,at91sam9260-sdramc",
+ "atmel,at91sam9g45-ddramc",
+ "atmel,sama5d3-ddramc",
+- reg: Should contain registers location and length
+
+Examples:
+
+ ramc0: ramc@ffffe800 {
+ compatible = "atmel,at91sam9g45-ddramc";
+ reg = <0xffffe800 0x200>;
+ };
+
+SHDWC Shutdown Controller
+
+required properties:
+- compatible: Should be "atmel,<chip>-shdwc".
+ <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
+- reg: Should contain registers location and length
+- clocks: phandle to input clock.
+
+optional properties:
+- atmel,wakeup-mode: String, operation mode of the wakeup mode.
+ Supported values are: "none", "high", "low", "any".
+- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
+
+optional at91sam9260 properties:
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9rl properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
+
+optional at91sam9x5 properties:
+- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
+
+Example:
+
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
+ };
+
+SHDWC SAMA5D2-Compatible Shutdown Controller
+
+1) shdwc node
+
+required properties:
+- compatible: should be "atmel,sama5d2-shdwc".
+- reg: should contain registers location and length
+- clocks: phandle to input clock.
+- #address-cells: should be one. The cell is the wake-up input index.
+- #size-cells: should be zero.
+
+optional properties:
+
+- debounce-delay-us: minimum wake-up inputs debouncer period in
+ microseconds. It's usually a board-related property.
+- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
+
+The node contains child nodes for each wake-up input that the platform uses.
+
+2) input nodes
+
+Wake-up input nodes are usually described in the "board" part of the Device
+Tree. Note also that input 0 is linked to the wake-up pin and is frequently
+used.
+
+Required properties:
+- reg: should contain the wake-up input index [0 - 15].
+
+Optional properties:
+- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
+ by the child, forces the wake-up of the core power supply on a high level.
+ The default is to be active low.
+
+Example:
+
+On the SoC side:
+ shdwc@f8048010 {
+ compatible = "atmel,sama5d2-shdwc";
+ reg = <0xf8048010 0x10>;
+ clocks = <&clk32k>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ atmel,wakeup-rtc-timer;
+ };
+
+On the board side:
+ shdwc@f8048010 {
+ debounce-delay-us = <976>;
+
+ input@0 {
+ reg = <0>;
+ };
+
+ input@1 {
+ reg = <1>;
+ atmel,wakeup-active-high;
+ };
+ };
+
+Special Function Registers (SFR)
+
+Special Function Registers (SFR) manage specific aspects of the integrated
+memory, bridge implementations, processor and other functionality not controlled
+elsewhere.
+
+required properties:
+- compatible: Should be "atmel,<chip>-sfr", "syscon" or
+ "atmel,<chip>-sfrbu", "syscon"
+ <chip> can be "sama5d3", "sama5d4" or "sama5d2".
+- reg: Should contain registers location and length
+
+ sfr@f0038000 {
+ compatible = "atmel,sama5d3-sfr", "syscon";
+ reg = <0xf0038000 0x60>;
+ };
+
+Security Module (SECUMOD)
+
+The Security Module macrocell provides all necessary secure functions to avoid
+voltage, temperature, frequency and mechanical attacks on the chip. It also
+embeds secure memories that can be scrambled
+
+required properties:
+- compatible: Should be "atmel,<chip>-secumod", "syscon".
+ <chip> can be "sama5d2".
+- reg: Should contain registers location and length
+
+ secumod@fc040000 {
+ compatible = "atmel,sama5d2-secumod", "syscon";
+ reg = <0xfc040000 0x100>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH 04/36] dt-bindings: arm: fsl: Move DCFG and SCFG bindings to their own docs
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Shawn Guo, Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
Mark Brown, Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
In preparation to convert board-level bindings to json-schema, move
various misc SoC bindings out to their own file.
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../arm/freescale/fsl,layerscape-dcfg.txt | 19 +++++++++
.../arm/freescale/fsl,layerscape-scfg.txt | 19 +++++++++
Documentation/devicetree/bindings/arm/fsl.txt | 39 -------------------
3 files changed, 38 insertions(+), 39 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
new file mode 100644
index 000000000000..b5cb374dc47d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
@@ -0,0 +1,19 @@
+Freescale DCFG
+
+DCFG is the device configuration unit, that provides general purpose
+configuration and status for the device. Such as setting the secondary
+core start address and release the secondary core from holdoff and startup.
+
+Required properties:
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-dcfg",
+ The following <chip>s are known to be supported:
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+
+ - reg : should contain base address and length of DCFG memory-mapped registers
+
+Example:
+ dcfg: dcfg@1ee0000 {
+ compatible = "fsl,ls1021a-dcfg";
+ reg = <0x0 0x1ee0000 0x0 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
new file mode 100644
index 000000000000..0ab67b0b216d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
@@ -0,0 +1,19 @@
+Freescale SCFG
+
+SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+
+Required properties:
+ - compatible: Should contain a chip-specific compatible string,
+ Chip-specific strings are of the form "fsl,<chip>-scfg",
+ The following <chip>s are known to be supported:
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+
+ - reg: should contain base address and length of SCFG memory-mapped registers
+
+Example:
+ scfg: scfg@1570000 {
+ compatible = "fsl,ls1021a-scfg";
+ reg = <0x0 0x1570000 0x0 0x10000>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 8a1baa2b9723..1e775aaa5c5b 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -101,45 +101,6 @@ Freescale LS1021A Platform Device Tree Bindings
Required root node compatible properties:
- compatible = "fsl,ls1021a";
-Freescale SoC-specific Device Tree Bindings
--------------------------------------------
-
-Freescale SCFG
- SCFG is the supplemental configuration unit, that provides SoC specific
-configuration and status registers for the chip. Such as getting PEX port
-status.
- Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-scfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
-
- - reg: should contain base address and length of SCFG memory-mapped registers
-
-Example:
- scfg: scfg@1570000 {
- compatible = "fsl,ls1021a-scfg";
- reg = <0x0 0x1570000 0x0 0x10000>;
- };
-
-Freescale DCFG
- DCFG is the device configuration unit, that provides general purpose
-configuration and status for the device. Such as setting the secondary
-core start address and release the secondary core from holdoff and startup.
- Required properties:
- - compatible: Should contain a chip-specific compatible string,
- Chip-specific strings are of the form "fsl,<chip>-dcfg",
- The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
-
- - reg : should contain base address and length of DCFG memory-mapped registers
-
-Example:
- dcfg: dcfg@1ee0000 {
- compatible = "fsl,ls1021a-dcfg";
- reg = <0x0 0x1ee0000 0x0 0x10000>;
- };
-
Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
----------------------------------------------------------------
--
2.17.1
^ permalink raw reply related
* [PATCH 05/36] dt-bindings: arm: renesas: Move 'renesas, prr' binding to its own doc
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Simon Horman, Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
linux-renesas-soc, Mark Brown, Geert Uytterhoeven, Olof Johansson,
Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
In preparation to convert board-level bindings to json-schema, move
various misc SoC bindings out to their own file.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Simon Horman <horms@verge.net.au>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/renesas,prr.txt | 18 ++++++++++++++++++
.../devicetree/bindings/arm/shmobile.txt | 18 ------------------
2 files changed, 18 insertions(+), 18 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/renesas,prr.txt
diff --git a/Documentation/devicetree/bindings/arm/renesas,prr.txt b/Documentation/devicetree/bindings/arm/renesas,prr.txt
new file mode 100644
index 000000000000..5000bf492f70
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/renesas,prr.txt
@@ -0,0 +1,18 @@
+Renesas Product Register
+
+Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
+product and revision information. If present, a device node for this register
+should be added.
+
+Required properties:
+ - compatible: Must be "renesas,prr".
+ - reg: Base address and length of the register block.
+
+
+Examples
+--------
+
+ prr: chipid@ff000044 {
+ compatible = "renesas,prr";
+ reg = <0 0xff000044 0 4>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 89b4a389fbc7..619b765e5bee 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -141,21 +141,3 @@ Boards:
compatible = "renesas,v3msk", "renesas,r8a77970"
- Wheat (RTP0RC7792ASKB0000JE)
compatible = "renesas,wheat", "renesas,r8a7792"
-
-
-Most Renesas ARM SoCs have a Product Register that allows to retrieve SoC
-product and revision information. If present, a device node for this register
-should be added.
-
-Required properties:
- - compatible: Must be "renesas,prr".
- - reg: Base address and length of the register block.
-
-
-Examples
---------
-
- prr: chipid@ff000044 {
- compatible = "renesas,prr";
- reg = <0 0xff000044 0 4>;
- };
--
2.17.1
^ permalink raw reply related
* [PATCH 06/36] dt-bindings: arm: zte: Move sysctrl bindings to their own doc
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Shawn Guo, Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
Mark Brown, Geert Uytterhoeven, Olof Johansson, Jun Nie,
Baoyou Xie, Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
In preparation to convert board-level bindings to json-schema, move
various misc SoC bindings out to their own file.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Baoyou Xie <baoyou.xie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/zte-sysctrl.txt | 30 +++++++++++++++++++
Documentation/devicetree/bindings/arm/zte.txt | 27 +----------------
2 files changed, 31 insertions(+), 26 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/zte-sysctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/zte-sysctrl.txt b/Documentation/devicetree/bindings/arm/zte-sysctrl.txt
new file mode 100644
index 000000000000..7e66b7f7ba96
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/zte-sysctrl.txt
@@ -0,0 +1,30 @@
+ZTE sysctrl Registers
+
+Registers for 'zte,zx296702' SoC:
+
+System management required properties:
+ - compatible = "zte,sysctrl"
+
+Low power management required properties:
+ - compatible = "zte,zx296702-pcu"
+
+Bus matrix required properties:
+ - compatible = "zte,zx-bus-matrix"
+
+
+Registers for 'zte,zx296718' SoC:
+
+System management required properties:
+ - compatible = "zte,zx296718-aon-sysctrl"
+ - compatible = "zte,zx296718-sysctrl"
+
+Example:
+aon_sysctrl: aon-sysctrl@116000 {
+ compatible = "zte,zx296718-aon-sysctrl", "syscon";
+ reg = <0x116000 0x1000>;
+};
+
+sysctrl: sysctrl@1463000 {
+ compatible = "zte,zx296718-sysctrl", "syscon";
+ reg = <0x1463000 0x1000>;
+};
diff --git a/Documentation/devicetree/bindings/arm/zte.txt b/Documentation/devicetree/bindings/arm/zte.txt
index 83369785d29c..340612794a37 100644
--- a/Documentation/devicetree/bindings/arm/zte.txt
+++ b/Documentation/devicetree/bindings/arm/zte.txt
@@ -1,20 +1,10 @@
ZTE platforms device tree bindings
----------------------------------------
+---------------------------------------
- ZX296702 board:
Required root node properties:
- compatible = "zte,zx296702-ad1", "zte,zx296702"
-System management required properties:
- - compatible = "zte,sysctrl"
-
-Low power management required properties:
- - compatible = "zte,zx296702-pcu"
-
-Bus matrix required properties:
- - compatible = "zte,zx-bus-matrix"
-
-
---------------------------------------
- ZX296718 SoC:
Required root node properties:
@@ -22,18 +12,3 @@ Bus matrix required properties:
ZX296718 EVB board:
- "zte,zx296718-evb"
-
-System management required properties:
- - compatible = "zte,zx296718-aon-sysctrl"
- - compatible = "zte,zx296718-sysctrl"
-
-Example:
-aon_sysctrl: aon-sysctrl@116000 {
- compatible = "zte,zx296718-aon-sysctrl", "syscon";
- reg = <0x116000 0x1000>;
-};
-
-sysctrl: sysctrl@1463000 {
- compatible = "zte,zx296718-sysctrl", "syscon";
- reg = <0x1463000 0x1000>;
-};
--
2.17.1
^ permalink raw reply related
* [PATCH 07/36] kbuild: Add support for DT binding schema checks
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Jonathan Corbet, linux-kbuild, Linus Walleij, linux-doc,
Pantelis Antoniou, Bjorn Andersson, Masahiro Yamada, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Michal Marek, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
This adds the build infrastructure for checking DT binding schema
documents and validating dts files using the binding schema.
Check DT binding schema documents:
make dt_binding_check
Build dts files and check using DT binding schema:
make dtbs_check
Currently, the validation targets are separate from a normal build to
avoid a hard dependency on the external DT schema project and because
there are lots of warnings generated.
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Michal Marek <michal.lkml@markovi.net>
Cc: linux-doc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kbuild@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.gitignore | 1 +
Documentation/Makefile | 2 +-
Documentation/devicetree/bindings/.gitignore | 2 ++
Documentation/devicetree/bindings/Makefile | 30 ++++++++++++++++++++
Makefile | 8 +++++-
scripts/Makefile.lib | 24 ++++++++++++++--
6 files changed, 63 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/.gitignore
create mode 100644 Documentation/devicetree/bindings/Makefile
diff --git a/.gitignore b/.gitignore
index 97ba6b79834c..a20ac26aa2f5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,6 +15,7 @@
*.bin
*.bz2
*.c.[012]*.*
+*.dt.yaml
*.dtb
*.dtb.S
*.dwo
diff --git a/Documentation/Makefile b/Documentation/Makefile
index 2ca77ad0f238..9786957c6a35 100644
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@@ -2,7 +2,7 @@
# Makefile for Sphinx documentation
#
-subdir-y :=
+subdir-y := devicetree/bindings/
# You can set these variables from the command line.
SPHINXBUILD = sphinx-build
diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore
new file mode 100644
index 000000000000..7e47316f1d7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/.gitignore
@@ -0,0 +1,2 @@
+*.example.dts
+*.yaml.tmp
diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile
new file mode 100644
index 000000000000..b57f0dec3fab
--- /dev/null
+++ b/Documentation/devicetree/bindings/Makefile
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0
+DT_DOC_CHECKER ?= dt-doc-validate
+DT_EXTRACT_EX ?= dt-extract-example
+
+quiet_cmd_chk_binding = CHKDT $<
+ cmd_chk_binding = (set -e; \
+ $(DT_DOC_CHECKER) $< ; \
+ mkdir -p $(dir $@) ; \
+ $(DT_EXTRACT_EX) $< > $@ )
+
+$(obj)/%.example.dts: $(src)/%.yaml FORCE
+ $(call if_changed,chk_binding)
+
+DT_MK_SCHEMA ?= dt-mk-schema
+DT_TMP_SCHEMA := .schema.yaml.tmp
+extra-y += $(DT_TMP_SCHEMA)
+
+quiet_cmd_mk_schema = SCHEMA $@
+ cmd_mk_schema = mkdir -p $(obj); \
+ $(DT_MK_SCHEMA) -o $@ $(srctree)/$(src)
+
+DT_DOCS = $(shell cd $(srctree)/$(src) && find * -name '*.yaml')
+DTS_EXAMPLES = $(patsubst %.yaml,%.example.dts, $(DT_DOCS))
+extra-y += $(DTS_EXAMPLES)
+
+DTBS = $(patsubst %.yaml,%.example.dtb, $(DT_DOCS))
+extra-y += $(DTBS)
+
+$(obj)/$(DT_TMP_SCHEMA): $(addprefix $(obj)/, $(DTBS)) FORCE
+ $(call if_changed,mk_schema)
diff --git a/Makefile b/Makefile
index 021e274c4b03..648f7238e883 100644
--- a/Makefile
+++ b/Makefile
@@ -1227,10 +1227,13 @@ ifneq ($(dtstree),)
%.dtb: prepare3 scripts_dtc
$(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@
-PHONY += dtbs dtbs_install
+PHONY += dtbs dtbs_install dt_binding_check
dtbs: prepare3 scripts_dtc
$(Q)$(MAKE) $(build)=$(dtstree)
+dtbs_check: prepare3 dt_binding_check
+ $(Q)$(MAKE) $(build)=$(dtstree) CHECK_DTBS=1
+
dtbs_install:
$(Q)$(MAKE) $(dtbinst)=$(dtstree)
@@ -1244,6 +1247,9 @@ PHONY += scripts_dtc
scripts_dtc: scripts_basic
$(Q)$(MAKE) $(build)=scripts/dtc
+dt_binding_check: scripts_dtc
+ $(Q)$(MAKE) $(build)=Documentation/devicetree/bindings
+
# ---------------------------------------------------------------------------
# Modules
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 8fe4468f9bda..d1c5630ba24c 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -61,6 +61,11 @@ real-obj-m := $(foreach m, $(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))
extra-y += $(dtb-y)
extra-$(CONFIG_OF_ALL_DTBS) += $(dtb-)
+ifneq ($(CHECK_DTBS),)
+extra-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y))
+extra-$(CONFIG_OF_ALL_DTBS) += $(patsubst %.dtb,%.dt.yaml, $(dtb-))
+endif
+
# Add subdir path
extra-y := $(addprefix $(obj)/,$(extra-y))
@@ -284,13 +289,28 @@ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE
quiet_cmd_dtc = DTC $@
cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
$(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
- $(DTC) -O dtb -o $@ -b 0 \
+ $(DTC) -O $(2) -o $@ -b 0 \
$(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \
-d $(depfile).dtc.tmp $(dtc-tmp) ; \
cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile)
$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE
- $(call if_changed_dep,dtc)
+ $(call if_changed_dep,dtc,dtb)
+
+DT_CHECKER ?= dt-validate
+DT_BINDING_DIR := Documentation/devicetree/bindings
+DT_TMP_SCHEMA := $(objtree)/$(DT_BINDING_DIR)/.schema.yaml.tmp
+
+quiet_cmd_dtb_check = CHECK $@
+ cmd_dtb_check = $(DT_CHECKER) -p $(DT_TMP_SCHEMA) $@ ;
+
+define rule_dtc_dt_yaml
+ $(call cmd_and_fixdep,dtc,yaml) \
+ $(call echo-cmd,dtb_check) $(cmd_dtb_check)
+endef
+
+$(obj)/%.dt.yaml: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE
+ $(call if_changed_rule,dtc_dt_yaml)
dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp)
--
2.17.1
^ permalink raw reply related
* [PATCH 08/36] dt-bindings: Add a writing DT schemas how-to and annotated example
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Add a how-to doc on writing DT schema documentation. This gives a
description of each section and details on how to validate the DT schema
file. The DT schema are written using json-schema vocabulary in a YAML
encoded document. Using jsonschema gives us access to existing tooling.
A YAML encoding gives us something easy to edit. The example is
annotated to help explain what each section does.
This example is just the tip of the iceberg, but is it the part most
developers writing bindings will interact with. Backing all this up
are meta-schema (to validate the binding schemas), some DT core schema,
YAML encoded DT output with dtc, and a small number of python scripts to
run validation.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/example-schema.yaml | 155 ++++++++++++++++++
Documentation/devicetree/writing-schema.md | 111 +++++++++++++
2 files changed, 266 insertions(+)
create mode 100644 Documentation/devicetree/bindings/example-schema.yaml
create mode 100644 Documentation/devicetree/writing-schema.md
diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml
new file mode 100644
index 000000000000..4cbdbf59695f
--- /dev/null
+++ b/Documentation/devicetree/bindings/example-schema.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+# All the top-level keys are standard json-schema keywords except for
+# 'maintainers' and 'select'
+
+# $id is a unique idenifier based on the filename
+$id: "http://devicetree.org/schemas/example-schema.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: An example schema annotated with jsonschema details
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |
+ A more detailed multi-line description of the binding.
+
+ Details about the hardware device and any links to datasheets can go here.
+
+ Literal blocks are marked with the '|' at the beginning. The end is marked by
+ indentation less than the first line of the literal block.
+
+select: false
+ # 'select' is a schema applied to a DT node to determine if this binding
+ # schema should be applied to the node. It is optional and by default the
+ # possible compatible strings are extracted and used to match.
+
+properties:
+ # A dictionary of DT properties for this binding schema
+ compatible:
+ # More complicated schema can use oneOf (XOR), anyOf (OR), or allOf (AND)
+ # to handle different conditions.
+ # In this case, it's needed to handle a variable number of values as there
+ # isn't another way to express a constraint of the last string value.
+ # The boolean schema must be a list of schemas.
+ oneOf:
+ - items:
+ # items is a list of possible values for the property. The number of
+ # values is determined by the number of elements in the list.
+ # Order in lists is significant, order in dicts is not
+ # Must be one of the 1st enums followed by the 2nd enum
+ #
+ # Each element in items should be 'enum' or 'const'
+ - enum:
+ - vendor,soc4-ip
+ - vendor,soc3-ip
+ - vendor,soc2-ip
+ - enum:
+ - vendor,soc1-ip
+ # additionalItems being false is implied
+ # minItems/maxItems equal to 2 is implied
+ - items:
+ # 'const' is just a special case of an enum with a single possible value
+ - const: vendor,soc1-ip
+
+ reg:
+ # The description of each element defines the order and implicitly defines
+ # the number of reg entries
+ items:
+ - description: core registers
+ - description: aux registers
+ # minItems/maxItems equal to 2 is implied
+
+ reg-names:
+ # The core schema enforces this is a string array
+ items:
+ - const: core
+ - const: aux
+
+ clocks:
+ maxItems: 1
+ # Only a single entry, so just need to set the max number of items.
+ description: hello
+
+ clock-names:
+ items:
+ - const: bus
+
+ interrupts:
+ # Either 1 or 2 interrupts can be present
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: tx or combined interrupt
+ - description: rx interrupt
+
+ description:
+ A variable number of interrupts warrants a description of what conditions
+ affect the number of interrupts. Otherwise, descriptions on standard
+ properties are not necessary.
+
+ interrupt-names:
+ # minItems must be specified here because the default would be 2
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: "tx irq"
+ - const: "rx irq"
+
+ # Property names starting with '#' must be quoted
+ '#interrupt-cells':
+ # A simple case where the value must always be '2'.
+ # The core schema handles that this must be a single integer.
+ const: 2
+
+ interrupt-controller: true
+ # The core checks this is a boolean, so just have to list it here to be
+ # valid for this binding.
+
+ clock-frequency:
+ # The type is set in the core schema. Per device schema only need to set
+ # constraints on the possible values.
+ minimum: 100
+ maximum: 400000
+ # The value that should be used if the property is not present
+ default: 200
+
+ foo-gpios:
+ maxItems: 1
+ description: A connection of the 'foo' gpio line.
+
+ vendor,int-property:
+ description: Vendor specific properties must have a description
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum: [2, 4, 6, 8, 10]
+
+ vendor,bool-property:
+ description: Vendor specific properties must have a description
+ type: boolean
+
+ vendor,string-array-property:
+ description: Vendor specific properties may refer to core schema
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/stringarray'
+ - maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+
+examples:
+ - |
+ node@1000 {
+ compatible = "vendor,soc4-ip", "vendor,soc1-ip";
+ reg = <0x1000 0x80>,
+ <0x3000 0x80>;
+ reg-names = "core", "aux";
+ interrupts = <10>;
+ interrupt-controller;
+ };
diff --git a/Documentation/devicetree/writing-schema.md b/Documentation/devicetree/writing-schema.md
new file mode 100644
index 000000000000..b1d9798ca3e4
--- /dev/null
+++ b/Documentation/devicetree/writing-schema.md
@@ -0,0 +1,111 @@
+# Writing DeviceTree Bindings in json-schema
+
+Devicetree bindings are written using json-schema vocabulary. Schema files are
+written in a JSON compatible subset of YAML. YAML is used instead of JSON as it
+considered more human readable and has some advantages such as allowing
+comments (Prefixed with '#').
+
+## Schema Contents
+
+Each schema doc is a structured json-schema which is defined by a set of
+top-level properties:
+
+- __$id__ - A json-schema unique identifier string. The string must be a valid
+URI typically containing the binding's filename and path. DT schema it must
+begin with "http://devicetree.org/schema/". The URL is used for non file local
+"$ref" lookups. A URL is used even for local files, and there may not actually
+be files present at those locations.
+
+- __$schema__ - Indicates the meta-schema the schema file adheres to.
+
+- __title__ - A one line description on the contents of the binding schema.
+
+- __maintainers__ - A DT specific property. Contains a list of email address(es)
+for maintainers of this binding.
+
+- __description__ - Optional. A multi-line text block containing any detailed
+information about this binding. It should contain things such as what the block
+or device does, standards the device conforms to, and links to datasheets for
+more information.
+
+- __select__ - Optional. A json-schema to match nodes for applying the schema.
+By default, nodes are matched against their possible compatible string values
+or node name and select is not necessary.
+
+- __properties__ - A set of sub-schema defining all the DT properties for the
+binding. The exact schema depends on the type of property. A property can also
+define a child DT node with child properties defined under it.
+
+- __patternProperties__ - Optional. Similar to 'properties', but names are regex.
+
+- __required__ - A list of DT properties from the 'properties' section that
+must always be present.
+
+- __examples__ - Optional. A list of one or more DTS hunks implementing the
+binding.
+
+Unless noted otherwise, all properties are required.
+
+## Property Schema
+
+The 'properties' section of the schema contains all the DT properties for a
+binding. Each property contains a set of constraints using json-schema
+vocabulary for that property. The properties schemas are what is used for
+validation of DT files.
+
+For common properties, only additional constraints not covered by the common
+binding schema need to be defined such as how many values are valid or what
+possible values are valid.
+
+Vendor specific properties will typically need more detailed schema. With the
+exception of boolean properties, they should have a reference to a type in
+schemas/types.yaml. A "description" property is always required.
+
+The Devicetree schemas don't exactly match the YAML encoded DT data produced by
+dtc. They are simplified to make them more compact and avoid a bunch of
+boilerplate. The tools process the schema files to produce the final schema for
+validation. There are currently 2 transformations the tools perform.
+
+The default for arrays in json-schema is they are variable sized and allow more
+entries than explicitly defined. This can be restricted by defining 'minItems',
+'maxItems', and 'additionalItems'. However, for DeviceTree Schemas, a fixed
+size is desired in most cases, so these properties are added based on the
+number of entries in an 'items' list.
+
+The YAML Devicetree format also makes all string values an array and scalar
+values a matrix (in order to define groupings) even when only a single value
+is present. Single entries in schemas are fixed up to match this encoding.
+
+## Testing
+
+### Dependencies
+
+The DT schema project must be installed in order to validate the DT schema
+binding documents and validate DTS files using the DT schema. The DT schema
+project can be installed with pip:
+
+`pip3 install git+https://github.com/robherring/yaml-bindings.git@master --process-dependency-links`
+
+dtc must also be built with YAML output support enabled. This requires that
+libyaml and its headers be installed on the host system.
+
+### Running checks
+
+The DT schema binding documents must be validated using the meta-schema (the
+schema for the schema) to ensure they are both valid json-schema and valid
+binding schema. All of the DT binding documents can be validated using the
+`dt_binding_check` target:
+
+`make dt_binding_check`
+
+In order to perform validation of DT source files, use the `dtbs_check` target:
+
+`make dtbs_check`
+
+This will first run the `dt_binding_check` which generates the processed schema.
+
+## json-schema Resources
+
+[JSON-Schema Specifications](http://json-schema.org/)
+
+[Using JSON Schema Book](http://usingjsonschema.com/)
--
2.17.1
^ permalink raw reply related
* [PATCH 09/36] dt-bindings: Convert trivial-devices.txt to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert trivial-devices.txt to DT schema format using json-schema.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/trivial-devices.txt | 201 ---------
.../devicetree/bindings/trivial-devices.yaml | 414 ++++++++++++++++++
2 files changed, 414 insertions(+), 201 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/trivial-devices.txt
create mode 100644 Documentation/devicetree/bindings/trivial-devices.yaml
diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt
deleted file mode 100644
index 763a2808a95c..000000000000
--- a/Documentation/devicetree/bindings/trivial-devices.txt
+++ /dev/null
@@ -1,201 +0,0 @@
-This is a list of trivial i2c devices that have simple device tree
-bindings, consisting only of a compatible field, an address and
-possibly an interrupt line.
-
-If a device needs more specific bindings, such as properties to
-describe some aspect of it, there needs to be a specific binding
-document for it just like any other devices.
-
-
-Compatible Vendor / Chip
-========== =============
-abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
-ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
-ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
-adi,adt7461 +/-1C TDM Extended Temp Range I.C
-adt7461 +/-1C TDM Extended Temp Range I.C
-adi,adt7473 +/-1C TDM Extended Temp Range I.C
-adi,adt7475 +/-1C TDM Extended Temp Range I.C
-adi,adt7476 +/-1C TDM Extended Temp Range I.C
-adi,adt7490 +/-1C TDM Extended Temp Range I.C
-adi,adxl345 Three-Axis Digital Accelerometer
-adi,adxl346 Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too)
-ams,iaq-core AMS iAQ-Core VOC Sensor
-amstaos,tsl2571 AMS/TAOS ALS and proximity sensor
-amstaos,tsl2671 AMS/TAOS ALS and proximity sensor
-amstaos,tmd2671 AMS/TAOS ALS and proximity sensor
-amstaos,tsl2771 AMS/TAOS ALS and proximity sensor
-amstaos,tmd2771 AMS/TAOS ALS and proximity sensor
-amstaos,tsl2572 AMS/TAOS ALS and proximity sensor
-amstaos,tsl2672 AMS/TAOS ALS and proximity sensor
-amstaos,tmd2672 AMS/TAOS ALS and proximity sensor
-amstaos,tsl2772 AMS/TAOS ALS and proximity sensor
-amstaos,tmd2772 AMS/TAOS ALS and proximity sensor
-at,24c08 i2c serial eeprom (24cxx)
-atmel,at97sc3204t i2c trusted platform module (TPM)
-capella,cm32181 CM32181: Ambient Light Sensor
-capella,cm3232 CM3232: Ambient Light Sensor
-cirrus,cs42l51 Cirrus Logic CS42L51 audio codec
-dallas,ds1374 I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
-dallas,ds1631 High-Precision Digital Thermometer
-dallas,ds1672 Dallas DS1672 Real-time Clock
-dallas,ds1682 Total-Elapsed-Time Recorder with Alarm
-dallas,ds1775 Tiny Digital Thermometer and Thermostat
-dallas,ds3232 Extremely Accurate I²C RTC with Integrated Crystal and SRAM
-dallas,ds4510 CPU Supervisor with Nonvolatile Memory and Programmable I/O
-dallas,ds75 Digital Thermometer and Thermostat
-devantech,srf02 Devantech SRF02 ultrasonic ranger in I2C mode
-devantech,srf08 Devantech SRF08 ultrasonic ranger
-devantech,srf10 Devantech SRF10 ultrasonic ranger
-dlg,da9053 DA9053: flexible system level PMIC with multicore support
-dlg,da9063 DA9063: system PMIC for quad-core application processors
-domintech,dmard09 DMARD09: 3-axis Accelerometer
-domintech,dmard10 DMARD10: 3-axis Accelerometer
-epson,rx8010 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
-epson,rx8581 I2C-BUS INTERFACE REAL TIME CLOCK MODULE
-emmicro,em3027 EM Microelectronic EM3027 Real-time Clock
-fsl,mag3110 MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
-fsl,mma7660 MMA7660FC: 3-Axis Orientation/Motion Detection Sensor
-fsl,mma8450 MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
-fsl,mpl3115 MPL3115: Absolute Digital Pressure Sensor
-fsl,mpr121 MPR121: Proximity Capacitive Touch Sensor Controller
-fsl,sgtl5000 SGTL5000: Ultra Low-Power Audio Codec
-gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
-infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
-infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz)
-infineon,tlv493d-a1b6 Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
-isil,isl1208 Intersil ISL1208 Low Power RTC with Battery Backed SRAM
-isil,isl1218 Intersil ISL1218 Low Power RTC with Battery Backed SRAM
-isil,isl12022 Intersil ISL12022 Real-time Clock
-isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor
-isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor
-maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator
-maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
-maxim,max6621 PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
-maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
-mcube,mc3230 mCube 3-axis 8-bit digital accelerometer
-memsic,mxc6225 MEMSIC 2-axis 8-bit digital accelerometer
-microchip,mcp4017-502 Microchip 7-bit Single I2C Digital POT (5k)
-microchip,mcp4017-103 Microchip 7-bit Single I2C Digital POT (10k)
-microchip,mcp4017-503 Microchip 7-bit Single I2C Digital POT (50k)
-microchip,mcp4017-104 Microchip 7-bit Single I2C Digital POT (100k)
-microchip,mcp4018-502 Microchip 7-bit Single I2C Digital POT (5k)
-microchip,mcp4018-103 Microchip 7-bit Single I2C Digital POT (10k)
-microchip,mcp4018-503 Microchip 7-bit Single I2C Digital POT (50k)
-microchip,mcp4018-104 Microchip 7-bit Single I2C Digital POT (100k)
-microchip,mcp4019-502 Microchip 7-bit Single I2C Digital POT (5k)
-microchip,mcp4019-103 Microchip 7-bit Single I2C Digital POT (10k)
-microchip,mcp4019-503 Microchip 7-bit Single I2C Digital POT (50k)
-microchip,mcp4019-104 Microchip 7-bit Single I2C Digital POT (100k)
-microchip,mcp4531-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
-microchip,mcp4531-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
-microchip,mcp4531-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
-microchip,mcp4531-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
-microchip,mcp4532-502 Microchip 7-bit Single I2C Digital Potentiometer (5k)
-microchip,mcp4532-103 Microchip 7-bit Single I2C Digital Potentiometer (10k)
-microchip,mcp4532-503 Microchip 7-bit Single I2C Digital Potentiometer (50k)
-microchip,mcp4532-104 Microchip 7-bit Single I2C Digital Potentiometer (100k)
-microchip,mcp4541-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4541-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4541-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4541-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4542-502 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4542-103 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4542-503 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4542-104 Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4551-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
-microchip,mcp4551-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
-microchip,mcp4551-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
-microchip,mcp4551-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
-microchip,mcp4552-502 Microchip 8-bit Single I2C Digital Potentiometer (5k)
-microchip,mcp4552-103 Microchip 8-bit Single I2C Digital Potentiometer (10k)
-microchip,mcp4552-503 Microchip 8-bit Single I2C Digital Potentiometer (50k)
-microchip,mcp4552-104 Microchip 8-bit Single I2C Digital Potentiometer (100k)
-microchip,mcp4561-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4561-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4561-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4561-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4562-502 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4562-103 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4562-503 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4562-104 Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4631-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
-microchip,mcp4631-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
-microchip,mcp4631-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
-microchip,mcp4631-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
-microchip,mcp4632-502 Microchip 7-bit Dual I2C Digital Potentiometer (5k)
-microchip,mcp4632-103 Microchip 7-bit Dual I2C Digital Potentiometer (10k)
-microchip,mcp4632-503 Microchip 7-bit Dual I2C Digital Potentiometer (50k)
-microchip,mcp4632-104 Microchip 7-bit Dual I2C Digital Potentiometer (100k)
-microchip,mcp4641-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4641-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4641-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4641-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4642-502 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4642-103 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4642-503 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4642-104 Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4651-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
-microchip,mcp4651-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
-microchip,mcp4651-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
-microchip,mcp4651-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
-microchip,mcp4652-502 Microchip 8-bit Dual I2C Digital Potentiometer (5k)
-microchip,mcp4652-103 Microchip 8-bit Dual I2C Digital Potentiometer (10k)
-microchip,mcp4652-503 Microchip 8-bit Dual I2C Digital Potentiometer (50k)
-microchip,mcp4652-104 Microchip 8-bit Dual I2C Digital Potentiometer (100k)
-microchip,mcp4661-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4661-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4661-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4661-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
-microchip,mcp4662-502 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
-microchip,mcp4662-103 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
-microchip,mcp4662-503 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
-microchip,mcp4662-104 Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
-microchip,tc654 PWM Fan Speed Controller With Fan Fault Detection
-microchip,tc655 PWM Fan Speed Controller With Fan Fault Detection
-microcrystal,rv3029 Real Time Clock Module with I2C-Bus
-miramems,da226 MiraMEMS DA226 2-axis 14-bit digital accelerometer
-miramems,da280 MiraMEMS DA280 3-axis 14-bit digital accelerometer
-miramems,da311 MiraMEMS DA311 3-axis 12-bit digital accelerometer
-national,lm63 Temperature sensor with integrated fan control
-national,lm75 I2C TEMP SENSOR
-national,lm80 Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
-national,lm85 Temperature sensor with integrated fan control
-national,lm92 ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
-nuvoton,npct501 i2c trusted platform module (TPM)
-nuvoton,npct601 i2c trusted platform module (TPM2)
-nuvoton,w83773g Nuvoton Temperature Sensor
-nxp,pca9556 Octal SMBus and I2C registered interface
-nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
-nxp,pcf2127 Real-time clock
-nxp,pcf2129 Real-time clock
-nxp,pcf8523 Real-time Clock
-nxp,pcf8563 Real-time clock/calendar
-nxp,pcf85063 Tiny Real-Time Clock
-oki,ml86v7667 OKI ML86V7667 video decoder
-ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
-pericom,pt7c4338 Real-time Clock Module
-plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
-pulsedlight,lidar-lite-v2 Pulsedlight LIDAR range-finding sensor
-ricoh,r2025sd I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-ricoh,r2221tl I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-ricoh,rs5c372a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-ricoh,rs5c372b I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-ricoh,rv5c386 I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-ricoh,rv5c387a I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
-samsung,24ad0xd1 S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
-sgx,vz89x SGX Sensortech VZ89X Sensors
-sii,s35390a 2-wire CMOS real-time clock
-silabs,si7020 Relative Humidity and Temperature Sensors
-skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
-st,24c256 i2c serial eeprom (24cxx)
-taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
-ti,ads7828 8-Channels, 12-bit ADC
-ti,ads7830 8-Channels, 8-bit ADC
-ti,amc6821 Temperature Monitoring and Fan Control
-ti,tsc2003 I2C Touch-Screen Controller
-ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
-ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
-ti,tmp275 Digital Temperature Sensor
-winbond,w83793 Winbond/Nuvoton H/W Monitor
-winbond,wpct301 i2c trusted platform module (TPM)
diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml
new file mode 100644
index 000000000000..a17278a44699
--- /dev/null
+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
@@ -0,0 +1,414 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/trivial-devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trivial I2C and SPI devices that have simple device tree bindings
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |
+ This is a list of trivial I2C and SPI devices that have simple device tree
+ bindings, consisting only of a compatible field, an address and possibly an
+ interrupt line.
+
+ If a device needs more specific bindings, such as properties to
+ describe some aspect of it, there needs to be a specific binding
+ document for it just like any other devices.
+
+properties:
+ reg:
+ maxItems: 1
+ interrupts:
+ maxItems: 1
+ compatible:
+ items:
+ - enum:
+ # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
+ - abracon,abb5zes3
+ # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
+ - ad,ad7414
+ # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
+ - ad,adm9240
+ # +/-1C TDM Extended Temp Range I.C
+ - adi,adt7461
+ # +/-1C TDM Extended Temp Range I.C
+ - adt7461
+ # +/-1C TDM Extended Temp Range I.C
+ - adi,adt7473
+ # +/-1C TDM Extended Temp Range I.C
+ - adi,adt7475
+ # +/-1C TDM Extended Temp Range I.C
+ - adi,adt7476
+ # +/-1C TDM Extended Temp Range I.C
+ - adi,adt7490
+ # Three-Axis Digital Accelerometer
+ - adi,adxl345
+ # Three-Axis Digital Accelerometer (backward-compatibility value "adi,adxl345" must be listed too)
+ - adi,adxl346
+ # AMS iAQ-Core VOC Sensor
+ - ams,iaq-core
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2571
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2671
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tmd2671
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2771
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tmd2771
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2572
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2672
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tmd2672
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tsl2772
+ # AMS/TAOS ALS and proximity sensor
+ - amstaos,tmd2772
+ # i2c serial eeprom (24cxx)
+ - at,24c08
+ # i2c trusted platform module (TPM)
+ - atmel,at97sc3204t
+ # CM32181: Ambient Light Sensor
+ - capella,cm32181
+ # CM3232: Ambient Light Sensor
+ - capella,cm3232
+ # Cirrus Logic CS42L51 audio codec
+ - cirrus,cs42l51
+ # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
+ - dallas,ds1374
+ # High-Precision Digital Thermometer
+ - dallas,ds1631
+ # Dallas DS1672 Real-time Clock
+ - dallas,ds1672
+ # Total-Elapsed-Time Recorder with Alarm
+ - dallas,ds1682
+ # Tiny Digital Thermometer and Thermostat
+ - dallas,ds1775
+ # Extremely Accurate I²C RTC with Integrated Crystal and SRAM
+ - dallas,ds3232
+ # CPU Supervisor with Nonvolatile Memory and Programmable I/O
+ - dallas,ds4510
+ # Digital Thermometer and Thermostat
+ - dallas,ds75
+ # Devantech SRF02 ultrasonic ranger in I2C mode
+ - devantech,srf02
+ # Devantech SRF08 ultrasonic ranger
+ - devantech,srf08
+ # Devantech SRF10 ultrasonic ranger
+ - devantech,srf10
+ # DA9053: flexible system level PMIC with multicore support
+ - dlg,da9053
+ # DA9063: system PMIC for quad-core application processors
+ - dlg,da9063
+ # DMARD09: 3-axis Accelerometer
+ - domintech,dmard09
+ # DMARD10: 3-axis Accelerometer
+ - domintech,dmard10
+ # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
+ - epson,rx8010
+ # I2C-BUS INTERFACE REAL TIME CLOCK MODULE
+ - epson,rx8581
+ # EM Microelectronic EM3027 Real-time Clock
+ - emmicro,em3027
+ # MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
+ - fsl,mag3110
+ # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor
+ - fsl,mma7660
+ # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
+ - fsl,mma8450
+ # MPL3115: Absolute Digital Pressure Sensor
+ - fsl,mpl3115
+ # MPR121: Proximity Capacitive Touch Sensor Controller
+ - fsl,mpr121
+ # SGTL5000: Ultra Low-Power Audio Codec
+ - fsl,sgtl5000
+ # G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
+ - gmt,g751
+ # Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz)
+ - infineon,slb9635tt
+ # Infineon SLB9645 I2C TPM (new protocol, max 400khz)
+ - infineon,slb9645tt
+ # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
+ - infineon,tlv493d-a1b6
+ # Intersil ISL1208 Low Power RTC with Battery Backed SRAM
+ - isil,isl1208
+ # Intersil ISL1218 Low Power RTC with Battery Backed SRAM
+ - isil,isl1218
+ # Intersil ISL12022 Real-time Clock
+ - isil,isl12022
+ # Intersil ISL29028 Ambient Light and Proximity Sensor
+ - isil,isl29028
+ # Intersil ISL29030 Ambient Light and Proximity Sensor
+ - isil,isl29030
+ # 5 Bit Programmable, Pulse-Width Modulator
+ - maxim,ds1050
+ # Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
+ - maxim,max1237
+ # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion
+ - maxim,max6621
+ # 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
+ - maxim,max6625
+ # mCube 3-axis 8-bit digital accelerometer
+ - mcube,mc3230
+ # MEMSIC 2-axis 8-bit digital accelerometer
+ - memsic,mxc6225
+ # Microchip 7-bit Single I2C Digital POT (5k)
+ - microchip,mcp4017-502
+ # Microchip 7-bit Single I2C Digital POT (10k)
+ - microchip,mcp4017-103
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4017-503
+ # Microchip 7-bit Single I2C Digital POT (100k)
+ - microchip,mcp4017-104
+ # Microchip 7-bit Single I2C Digital POT (5k)
+ - microchip,mcp4018-502
+ # Microchip 7-bit Single I2C Digital POT (10k)
+ - microchip,mcp4018-103
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4018-503
+ # Microchip 7-bit Single I2C Digital POT (100k)
+ - microchip,mcp4018-104
+ # Microchip 7-bit Single I2C Digital POT (5k)
+ - microchip,mcp4019-502
+ # Microchip 7-bit Single I2C Digital POT (10k)
+ - microchip,mcp4019-103
+ # Microchip 7-bit Single I2C Digital POT (50k)
+ - microchip,mcp4019-503
+ # Microchip 7-bit Single I2C Digital POT (100k)
+ - microchip,mcp4019-104
+ # Microchip 7-bit Single I2C Digital Potentiometer (5k)
+ - microchip,mcp4531-502
+ # Microchip 7-bit Single I2C Digital Potentiometer (10k)
+ - microchip,mcp4531-103
+ # Microchip 7-bit Single I2C Digital Potentiometer (50k)
+ - microchip,mcp4531-503
+ # Microchip 7-bit Single I2C Digital Potentiometer (100k)
+ - microchip,mcp4531-104
+ # Microchip 7-bit Single I2C Digital Potentiometer (5k)
+ - microchip,mcp4532-502
+ # Microchip 7-bit Single I2C Digital Potentiometer (10k)
+ - microchip,mcp4532-103
+ # Microchip 7-bit Single I2C Digital Potentiometer (50k)
+ - microchip,mcp4532-503
+ # Microchip 7-bit Single I2C Digital Potentiometer (100k)
+ - microchip,mcp4532-104
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4541-502
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4541-103
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4541-503
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4541-104
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4542-502
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4542-103
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4542-503
+ # Microchip 7-bit Single I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4542-104
+ # Microchip 8-bit Single I2C Digital Potentiometer (5k)
+ - microchip,mcp4551-502
+ # Microchip 8-bit Single I2C Digital Potentiometer (10k)
+ - microchip,mcp4551-103
+ # Microchip 8-bit Single I2C Digital Potentiometer (50k)
+ - microchip,mcp4551-503
+ # Microchip 8-bit Single I2C Digital Potentiometer (100k)
+ - microchip,mcp4551-104
+ # Microchip 8-bit Single I2C Digital Potentiometer (5k)
+ - microchip,mcp4552-502
+ # Microchip 8-bit Single I2C Digital Potentiometer (10k)
+ - microchip,mcp4552-103
+ # Microchip 8-bit Single I2C Digital Potentiometer (50k)
+ - microchip,mcp4552-503
+ # Microchip 8-bit Single I2C Digital Potentiometer (100k)
+ - microchip,mcp4552-104
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4561-502
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4561-103
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4561-503
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4561-104
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4562-502
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4562-103
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4562-503
+ # Microchip 8-bit Single I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4562-104
+ # Microchip 7-bit Dual I2C Digital Potentiometer (5k)
+ - microchip,mcp4631-502
+ # Microchip 7-bit Dual I2C Digital Potentiometer (10k)
+ - microchip,mcp4631-103
+ # Microchip 7-bit Dual I2C Digital Potentiometer (50k)
+ - microchip,mcp4631-503
+ # Microchip 7-bit Dual I2C Digital Potentiometer (100k)
+ - microchip,mcp4631-104
+ # Microchip 7-bit Dual I2C Digital Potentiometer (5k)
+ - microchip,mcp4632-502
+ # Microchip 7-bit Dual I2C Digital Potentiometer (10k)
+ - microchip,mcp4632-103
+ # Microchip 7-bit Dual I2C Digital Potentiometer (50k)
+ - microchip,mcp4632-503
+ # Microchip 7-bit Dual I2C Digital Potentiometer (100k)
+ - microchip,mcp4632-104
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4641-502
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4641-103
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4641-503
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4641-104
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4642-502
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4642-103
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4642-503
+ # Microchip 7-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4642-104
+ # Microchip 8-bit Dual I2C Digital Potentiometer (5k)
+ - microchip,mcp4651-502
+ # Microchip 8-bit Dual I2C Digital Potentiometer (10k)
+ - microchip,mcp4651-103
+ # Microchip 8-bit Dual I2C Digital Potentiometer (50k)
+ - microchip,mcp4651-503
+ # Microchip 8-bit Dual I2C Digital Potentiometer (100k)
+ - microchip,mcp4651-104
+ # Microchip 8-bit Dual I2C Digital Potentiometer (5k)
+ - microchip,mcp4652-502
+ # Microchip 8-bit Dual I2C Digital Potentiometer (10k)
+ - microchip,mcp4652-103
+ # Microchip 8-bit Dual I2C Digital Potentiometer (50k)
+ - microchip,mcp4652-503
+ # Microchip 8-bit Dual I2C Digital Potentiometer (100k)
+ - microchip,mcp4652-104
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4661-502
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4661-103
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4661-503
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4661-104
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (5k)
+ - microchip,mcp4662-502
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (10k)
+ - microchip,mcp4662-103
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (50k)
+ - microchip,mcp4662-503
+ # Microchip 8-bit Dual I2C Digital Potentiometer with NV Memory (100k)
+ - microchip,mcp4662-104
+ # PWM Fan Speed Controller With Fan Fault Detection
+ - microchip,tc654
+ # PWM Fan Speed Controller With Fan Fault Detection
+ - microchip,tc655
+ # Real Time Clock Module with I2C-Bus
+ - microcrystal,rv3029
+ # MiraMEMS DA226 2-axis 14-bit digital accelerometer
+ - miramems,da226
+ # MiraMEMS DA280 3-axis 14-bit digital accelerometer
+ - miramems,da280
+ # MiraMEMS DA311 3-axis 12-bit digital accelerometer
+ - miramems,da311
+ # Temperature sensor with integrated fan control
+ - national,lm63
+ # I2C TEMP SENSOR
+ - national,lm75
+ # Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
+ - national,lm80
+ # Temperature sensor with integrated fan control
+ - national,lm85
+ # ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
+ - national,lm92
+ # i2c trusted platform module (TPM)
+ - nuvoton,npct501
+ # i2c trusted platform module (TPM2)
+ - nuvoton,npct601
+ # Nuvoton Temperature Sensor
+ - nuvoton,w83773g
+ # Octal SMBus and I2C registered interface
+ - nxp,pca9556
+ # 8-bit I2C-bus and SMBus I/O port with reset
+ - nxp,pca9557
+ # Real-time clock
+ - nxp,pcf2127
+ # Real-time clock
+ - nxp,pcf2129
+ # Real-time Clock
+ - nxp,pcf8523
+ # Real-time clock/calendar
+ - nxp,pcf8563
+ # Tiny Real-Time Clock
+ - nxp,pcf85063
+ # OKI ML86V7667 video decoder
+ - oki,ml86v7667
+ # OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
+ - ovti,ov5642
+ # Real-time Clock Module
+ - pericom,pt7c4338
+ # 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
+ - plx,pex8648
+ # Pulsedlight LIDAR range-finding sensor
+ - pulsedlight,lidar-lite-v2
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,r2025sd
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,r2221tl
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,rs5c372a
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,rs5c372b
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,rv5c386
+ # I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+ - ricoh,rv5c387a
+ # S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
+ - samsung,24ad0xd1
+ # SGX Sensortech VZ89X Sensors
+ - sgx,vz89x
+ # 2-wire CMOS real-time clock
+ - sii,s35390a
+ # Relative Humidity and Temperature Sensors
+ - silabs,si7020
+ # Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
+ - skyworks,sky81452
+ # i2c serial eeprom (24cxx)
+ - st,24c256
+ # Ambient Light Sensor with SMBUS/Two Wire Serial Interface
+ - taos,tsl2550
+ # 8-Channels, 12-bit ADC
+ - ti,ads7828
+ # 8-Channels, 8-bit ADC
+ - ti,ads7830
+ # Temperature Monitoring and Fan Control
+ - ti,amc6821
+ # I2C Touch-Screen Controller
+ - ti,tsc2003
+ # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
+ - ti,tmp102
+ # Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
+ - ti,tmp103
+ # Digital Temperature Sensor
+ - ti,tmp275
+ # Winbond/Nuvoton H/W Monitor
+ - winbond,w83793
+ # i2c trusted platform module (TPM)
+ - winbond,wpct301
+
+required:
+ - compatible
+ - reg
+
+...
--
2.17.1
^ permalink raw reply related
* [PATCH 10/36] dt-bindings: altera: Convert clkmgr binding to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Dinh Nguyen,
Mark Brown, Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert Altera clkmgr to DT schema format using json-schema.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../arm/altera/socfpga-clk-manager.txt | 11 -------
.../arm/altera/socfpga-clk-manager.yaml | 30 +++++++++++++++++++
2 files changed, 30 insertions(+), 11 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
deleted file mode 100644
index 2c28f1d12f45..000000000000
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Altera SOCFPGA Clock Manager
-
-Required properties:
-- compatible : "altr,clk-mgr"
-- reg : Should contain base address and length for Clock Manager
-
-Example:
- clkmgr@ffd04000 {
- compatible = "altr,clk-mgr";
- reg = <0xffd04000 0x1000>;
- };
diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
new file mode 100644
index 000000000000..37c2cf08fae0
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-clk-manager.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/altera/socfpga-clk-manager.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SOCFPGA Clock Manager
+
+maintainers:
+ - Dinh Nguyen <dinguyen@altera.com>
+description: test
+
+properties:
+ compatible:
+ items:
+ - const: altr,clk-mgr
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+examples:
+ - |
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
+ };
+
+...
--
2.17.1
^ permalink raw reply related
* [PATCH 11/36] dt-bindings: timer: Convert ARM timer bindings to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Daniel Lezcano, Pantelis Antoniou, Bjorn Andersson,
Mark Brown, Geert Uytterhoeven, Olof Johansson, Thomas Gleixner,
Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert ARM timers to DT schema format using json-schema.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../bindings/timer/arm,arch_timer.txt | 112 ----------------
.../bindings/timer/arm,arch_timer.yaml | 103 +++++++++++++++
.../bindings/timer/arm,arch_timer_mmio.yaml | 120 ++++++++++++++++++
.../bindings/timer/arm,global_timer.txt | 27 ----
.../bindings/timer/arm,global_timer.yaml | 46 +++++++
5 files changed, 269 insertions(+), 139 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt
deleted file mode 100644
index 68301b77e854..000000000000
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-* ARM architected timer
-
-ARM cores may have a per-core architected timer, which provides per-cpu timers,
-or a memory mapped architected timer, which provides up to 8 frames with a
-physical and optional virtual timer per frame.
-
-The per-core architected timer is attached to a GIC to deliver its
-per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
-to deliver its interrupts via SPIs.
-
-** CP15 Timer node properties:
-
-- compatible : Should at least contain one of
- "arm,armv7-timer"
- "arm,armv8-timer"
-
-- interrupts : Interrupt list for secure, non-secure, virtual and
- hypervisor timers, in that order.
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
- only where necessary to work around broken firmware which does not configure
- CNTFRQ on all CPUs to a uniform correct value. Use of this property is
- strongly discouraged; fix your firmware unless absolutely impossible.
-
-- always-on : a boolean property. If present, the timer is powered through an
- always-on power domain, therefore it never loses context.
-
-- fsl,erratum-a008585 : A boolean property. Indicates the presence of
- QorIQ erratum A-008585, which says that reading the counter is
- unreliable unless the same value is returned by back-to-back reads.
- This also affects writes to the tval register, due to the implicit
- counter read.
-
-- hisilicon,erratum-161010101 : A boolean property. Indicates the
- presence of Hisilicon erratum 161010101, which says that reading the
- counters is unreliable in some cases, and reads may return a value 32
- beyond the correct value. This also affects writes to the tval
- registers, due to the implicit counter read.
-
-** Optional properties:
-
-- arm,cpu-registers-not-fw-configured : Firmware does not initialize
- any of the generic timer CPU registers, which contain their
- architecturally-defined reset values. Only supported for 32-bit
- systems which follow the ARMv7 architected reset values.
-
-- arm,no-tick-in-suspend : The main counter does not tick when the system is in
- low-power system suspend on some SoCs. This behavior does not match the
- Architecture Reference Manual's specification that the system counter "must
- be implemented in an always-on power domain."
-
-
-Example:
-
- timer {
- compatible = "arm,cortex-a15-timer",
- "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- clock-frequency = <100000000>;
- };
-
-** Memory mapped timer node properties:
-
-- compatible : Should at least contain "arm,armv7-timer-mem".
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
- only when firmware has not configured the MMIO CNTFRQ registers.
-
-- reg : The control frame base address.
-
-Note that #address-cells, #size-cells, and ranges shall be present to ensure
-the CPU can address a frame's registers.
-
-A timer node has up to 8 frame sub-nodes, each with the following properties:
-
-- frame-number: 0 to 7.
-
-- interrupts : Interrupt list for physical and virtual timers in that order.
- The virtual timer interrupt is optional.
-
-- reg : The first and second view base addresses in that order. The second view
- base address is optional.
-
-- status : "disabled" indicates the frame is not available for use. Optional.
-
-Example:
-
- timer@f0000000 {
- compatible = "arm,armv7-timer-mem";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0xf0000000 0x1000>;
- clock-frequency = <50000000>;
-
- frame@f0001000 {
- frame-number = <0>
- interrupts = <0 13 0x8>,
- <0 14 0x8>;
- reg = <0xf0001000 0x1000>,
- <0xf0002000 0x1000>;
- };
-
- frame@f0003000 {
- frame-number = <1>
- interrupts = <0 15 0x8>;
- reg = <0xf0003000 0x1000>;
- };
- };
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
new file mode 100644
index 000000000000..733ae2254c65
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm,arch_timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM architected timer
+
+maintainers:
+ - Marc Zyngier <marc.zyngier@arm.com>
+ - Mark Rutland <mark.rutland@arm.com>
+description: |+
+ ARM cores may have a per-core architected timer, which provides per-cpu timers,
+ or a memory mapped architected timer, which provides up to 8 frames with a
+ physical and optional virtual timer per frame.
+
+ The per-core architected timer is attached to a GIC to deliver its
+ per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+ to deliver its interrupts via SPIs.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - arm,cortex-a15-timer
+ - enum:
+ - arm,armv7-timer
+ - items:
+ - enum:
+ - arm,armv7-timer
+ - items:
+ - enum:
+ - arm,armv8-timer
+
+ interrupts:
+ items:
+ - description: secure timer irq
+ - description: non-secure timer irq
+ - description: virtual timer irq
+ - description: hypervisor timer irq
+
+ clock-frequency:
+ description: The frequency of the main counter, in Hz. Should be present
+ only where necessary to work around broken firmware which does not configure
+ CNTFRQ on all CPUs to a uniform correct value. Use of this property is
+ strongly discouraged; fix your firmware unless absolutely impossible.
+
+ always-on:
+ type: boolean
+ description: If present, the timer is powered through an always-on power
+ domain, therefore it never loses context.
+
+ fsl,erratum-a008585:
+ type: boolean
+ description: Indicates the presence of QorIQ erratum A-008585, which says
+ that reading the counter is unreliable unless the same value is returned
+ by back-to-back reads. This also affects writes to the tval register, due
+ to the implicit counter read.
+
+ hisilicon,erratum-161010101:
+ type: boolean
+ description: Indicates the presence of Hisilicon erratum 161010101, which
+ says that reading the counters is unreliable in some cases, and reads may
+ return a value 32 beyond the correct value. This also affects writes to
+ the tval registers, due to the implicit counter read.
+
+ arm,cpu-registers-not-fw-configured:
+ type: boolean
+ description: Firmware does not initialize any of the generic timer CPU
+ registers, which contain their architecturally-defined reset values. Only
+ supported for 32-bit systems which follow the ARMv7 architected reset
+ values.
+
+ arm,no-tick-in-suspend:
+ type: boolean
+ description: The main counter does not tick when the system is in
+ low-power system suspend on some SoCs. This behavior does not match the
+ Architecture Reference Manual's specification that the system counter "must
+ be implemented in an always-on power domain."
+
+required:
+ - compatible
+
+oneOf:
+ - required:
+ - interrupts
+ - required:
+ - interrupts-extended
+
+examples:
+ - |
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ clock-frequency = <100000000>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
new file mode 100644
index 000000000000..34c8ecfea2a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm,arch_timer_mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM memory mapped architected timer
+
+maintainers:
+ - Marc Zyngier <marc.zyngier@arm.com>
+ - Mark Rutland <mark.rutland@arm.com>
+
+description: |+
+ ARM cores may have a memory mapped architected timer, which provides up to 8
+ frames with a physical and optional virtual timer per frame.
+
+ The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,armv7-timer-mem
+
+ reg:
+ maxItems: 1
+ description: The control frame base address
+
+ '#address-cells':
+ enum: [1, 2]
+
+ '#size-cells':
+ const: 1
+
+ clock-frequency:
+ description: The frequency of the main counter, in Hz. Should be present
+ only where necessary to work around broken firmware which does not configure
+ CNTFRQ on all CPUs to a uniform correct value. Use of this property is
+ strongly discouraged; fix your firmware unless absolutely impossible.
+
+ always-on:
+ type: boolean
+ description: If present, the timer is powered through an always-on power
+ domain, therefore it never loses context.
+
+ arm,cpu-registers-not-fw-configured:
+ type: boolean
+ description: Firmware does not initialize any of the generic timer CPU
+ registers, which contain their architecturally-defined reset values. Only
+ supported for 32-bit systems which follow the ARMv7 architected reset
+ values.
+
+ arm,no-tick-in-suspend:
+ type: boolean
+ description: The main counter does not tick when the system is in
+ low-power system suspend on some SoCs. This behavior does not match the
+ Architecture Reference Manual's specification that the system counter "must
+ be implemented in an always-on power domain."
+
+patternProperties:
+ '^frame@[0-9a-z]*$':
+ description: A timer node has up to 8 frame sub-nodes, each with the following properties.
+ properties:
+ frame-number:
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ maximum: 7
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: physical timer irq
+ - description: virtual timer irq
+
+ reg :
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: 1st view base address
+ - description: 2nd optional view base address
+
+ required:
+ - frame-number
+ - interrupts
+ - reg
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ timer@f0000000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0xf0000000 0x1000>;
+ clock-frequency = <50000000>;
+
+ frame@f0001000 {
+ frame-number = <0>;
+ interrupts = <0 13 0x8>,
+ <0 14 0x8>;
+ reg = <0xf0001000 0x1000>,
+ <0xf0002000 0x1000>;
+ };
+
+ frame@f0003000 {
+ frame-number = <1>;
+ interrupts = <0 15 0x8>;
+ reg = <0xf0003000 0x1000>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt
deleted file mode 100644
index bdae3a818793..000000000000
--- a/Documentation/devicetree/bindings/timer/arm,global_timer.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-
-* ARM Global Timer
- Cortex-A9 are often associated with a per-core Global timer.
-
-** Timer node required properties:
-
-- compatible : should contain
- * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
- * "arm,cortex-a9-global-timer" for Cortex-A9 global
- timers or any compatible implementation. Note: driver
- supports versions r2p0 and above.
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the GT timer
- register window.
-
-- clocks : Should be phandle to a clock.
-
-Example:
-
- timer@2c000600 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x2c000600 0x20>;
- interrupts = <1 13 0xf01>;
- clocks = <&arm_periph_clk>;
- };
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
new file mode 100644
index 000000000000..09090f677387
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm,global_timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Global Timer
+
+maintainers:
+ - Stuart Menefy <stuart.menefy@st.com>
+
+description:
+ Cortex-A9 are often associated with a per-core Global timer.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,cortex-a5-global-timer
+ - arm,cortex-a9-global-timer
+
+ description: driver supports versions r2p0 and above.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ timer@2c000600 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x2c000600 0x20>;
+ interrupts = <1 13 0xf01>;
+ clocks = <&arm_periph_clk>;
+ };
+...
--
2.17.1
^ permalink raw reply related
* [PATCH 12/36] dt-bindings: arm: Convert cpu binding to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
Matthias Brugger, Mark Brown, Geert Uytterhoeven, Olof Johansson,
linux-mediatek, Frank Rowand, Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert ARM CPU binding to DT schema format using json-schema.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/cpus.txt | 490 -----------------
.../devicetree/bindings/arm/cpus.yaml | 503 ++++++++++++++++++
2 files changed, 503 insertions(+), 490 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/cpus.txt
create mode 100644 Documentation/devicetree/bindings/arm/cpus.yaml
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
deleted file mode 100644
index b0198a1cf403..000000000000
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ /dev/null
@@ -1,490 +0,0 @@
-=================
-ARM CPUs bindings
-=================
-
-The device tree allows to describe the layout of CPUs in a system through
-the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
-defining properties for every cpu.
-
-Bindings for CPU nodes follow the Devicetree Specification, available from:
-
-https://www.devicetree.org/specifications/
-
-with updates for 32-bit and 64-bit ARM systems provided in this document.
-
-================================
-Convention used in this document
-================================
-
-This document follows the conventions described in the Devicetree
-Specification, with the addition:
-
-- square brackets define bitfields, eg reg[7:0] value of the bitfield in
- the reg property contained in bits 7 down to 0
-
-=====================================
-cpus and cpu node bindings definition
-=====================================
-
-The ARM architecture, in accordance with the Devicetree Specification,
-requires the cpus and cpu nodes to be present and contain the properties
-described below.
-
-- cpus node
-
- Description: Container of cpu nodes
-
- The node name must be "cpus".
-
- A cpus node must define the following properties:
-
- - #address-cells
- Usage: required
- Value type: <u32>
-
- Definition depends on ARM architecture version and
- configuration:
-
- # On uniprocessor ARM architectures previous to v7
- value must be 1, to enable a simple enumeration
- scheme for processors that do not have a HW CPU
- identification register.
- # On 32-bit ARM 11 MPcore, ARM v7 or later systems
- value must be 1, that corresponds to CPUID/MPIDR
- registers sizes.
- # On ARM v8 64-bit systems value should be set to 2,
- that corresponds to the MPIDR_EL1 register size.
- If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
- in the system, #address-cells can be set to 1, since
- MPIDR_EL1[63:32] bits are not used for CPUs
- identification.
- - #size-cells
- Usage: required
- Value type: <u32>
- Definition: must be set to 0
-
-- cpu node
-
- Description: Describes a CPU in an ARM based system
-
- PROPERTIES
-
- - device_type
- Usage: required
- Value type: <string>
- Definition: must be "cpu"
- - reg
- Usage and definition depend on ARM architecture version and
- configuration:
-
- # On uniprocessor ARM architectures previous to v7
- this property is required and must be set to 0.
-
- # On ARM 11 MPcore based systems this property is
- required and matches the CPUID[11:0] register bits.
-
- Bits [11:0] in the reg cell must be set to
- bits [11:0] in CPU ID register.
-
- All other bits in the reg cell must be set to 0.
-
- # On 32-bit ARM v7 or later systems this property is
- required and matches the CPU MPIDR[23:0] register
- bits.
-
- Bits [23:0] in the reg cell must be set to
- bits [23:0] in MPIDR.
-
- All other bits in the reg cell must be set to 0.
-
- # On ARM v8 64-bit systems this property is required
- and matches the MPIDR_EL1 register affinity bits.
-
- * If cpus node's #address-cells property is set to 2
-
- The first reg cell bits [7:0] must be set to
- bits [39:32] of MPIDR_EL1.
-
- The second reg cell bits [23:0] must be set to
- bits [23:0] of MPIDR_EL1.
-
- * If cpus node's #address-cells property is set to 1
-
- The reg cell bits [23:0] must be set to bits [23:0]
- of MPIDR_EL1.
-
- All other bits in the reg cells must be set to 0.
-
- - compatible:
- Usage: required
- Value type: <string>
- Definition: should be one of:
- "arm,arm710t"
- "arm,arm720t"
- "arm,arm740t"
- "arm,arm7ej-s"
- "arm,arm7tdmi"
- "arm,arm7tdmi-s"
- "arm,arm9es"
- "arm,arm9ej-s"
- "arm,arm920t"
- "arm,arm922t"
- "arm,arm925"
- "arm,arm926e-s"
- "arm,arm926ej-s"
- "arm,arm940t"
- "arm,arm946e-s"
- "arm,arm966e-s"
- "arm,arm968e-s"
- "arm,arm9tdmi"
- "arm,arm1020e"
- "arm,arm1020t"
- "arm,arm1022e"
- "arm,arm1026ej-s"
- "arm,arm1136j-s"
- "arm,arm1136jf-s"
- "arm,arm1156t2-s"
- "arm,arm1156t2f-s"
- "arm,arm1176jzf"
- "arm,arm1176jz-s"
- "arm,arm1176jzf-s"
- "arm,arm11mpcore"
- "arm,cortex-a5"
- "arm,cortex-a7"
- "arm,cortex-a8"
- "arm,cortex-a9"
- "arm,cortex-a12"
- "arm,cortex-a15"
- "arm,cortex-a17"
- "arm,cortex-a53"
- "arm,cortex-a57"
- "arm,cortex-a72"
- "arm,cortex-a73"
- "arm,cortex-m0"
- "arm,cortex-m0+"
- "arm,cortex-m1"
- "arm,cortex-m3"
- "arm,cortex-m4"
- "arm,cortex-r4"
- "arm,cortex-r5"
- "arm,cortex-r7"
- "brcm,brahma-b15"
- "brcm,brahma-b53"
- "brcm,vulcan"
- "cavium,thunder"
- "cavium,thunder2"
- "faraday,fa526"
- "intel,sa110"
- "intel,sa1100"
- "marvell,feroceon"
- "marvell,mohawk"
- "marvell,pj4a"
- "marvell,pj4b"
- "marvell,sheeva-v5"
- "nvidia,tegra132-denver"
- "nvidia,tegra186-denver"
- "nvidia,tegra194-carmel"
- "qcom,krait"
- "qcom,kryo"
- "qcom,kryo385"
- "qcom,scorpion"
- - enable-method
- Value type: <stringlist>
- Usage and definition depend on ARM architecture version.
- # On ARM v8 64-bit this property is required and must
- be one of:
- "psci"
- "spin-table"
- # On ARM 32-bit systems this property is optional and
- can be one of:
- "actions,s500-smp"
- "allwinner,sun6i-a31"
- "allwinner,sun8i-a23"
- "allwinner,sun9i-a80-smp"
- "amlogic,meson8-smp"
- "amlogic,meson8b-smp"
- "arm,realview-smp"
- "brcm,bcm11351-cpu-method"
- "brcm,bcm23550"
- "brcm,bcm2836-smp"
- "brcm,bcm-nsp-smp"
- "brcm,brahma-b15"
- "marvell,armada-375-smp"
- "marvell,armada-380-smp"
- "marvell,armada-390-smp"
- "marvell,armada-xp-smp"
- "marvell,98dx3236-smp"
- "mediatek,mt6589-smp"
- "mediatek,mt81xx-tz-smp"
- "qcom,gcc-msm8660"
- "qcom,kpss-acc-v1"
- "qcom,kpss-acc-v2"
- "renesas,apmu"
- "renesas,r9a06g032-smp"
- "rockchip,rk3036-smp"
- "rockchip,rk3066-smp"
- "ste,dbx500-smp"
-
- - cpu-release-addr
- Usage: required for systems that have an "enable-method"
- property value of "spin-table".
- Value type: <prop-encoded-array>
- Definition:
- # On ARM v8 64-bit systems must be a two cell
- property identifying a 64-bit zero-initialised
- memory location.
-
- - qcom,saw
- Usage: required for systems that have an "enable-method"
- property value of "qcom,kpss-acc-v1" or
- "qcom,kpss-acc-v2"
- Value type: <phandle>
- Definition: Specifies the SAW[1] node associated with this CPU.
-
- - qcom,acc
- Usage: required for systems that have an "enable-method"
- property value of "qcom,kpss-acc-v1" or
- "qcom,kpss-acc-v2"
- Value type: <phandle>
- Definition: Specifies the ACC[2] node associated with this CPU.
-
- - cpu-idle-states
- Usage: Optional
- Value type: <prop-encoded-array>
- Definition:
- # List of phandles to idle state nodes supported
- by this cpu [3].
-
- - capacity-dmips-mhz
- Usage: Optional
- Value type: <u32>
- Definition:
- # u32 value representing CPU capacity [4] in
- DMIPS/MHz, relative to highest capacity-dmips-mhz
- in the system.
-
- - rockchip,pmu
- Usage: optional for systems that have an "enable-method"
- property value of "rockchip,rk3066-smp"
- While optional, it is the preferred way to get access to
- the cpu-core power-domains.
- Value type: <phandle>
- Definition: Specifies the syscon node controlling the cpu core
- power domains.
-
- - dynamic-power-coefficient
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: A u32 value that represents the running time dynamic
- power coefficient in units of uW/MHz/V^2. The
- coefficient can either be calculated from power
- measurements or derived by analysis.
-
- The dynamic power consumption of the CPU is
- proportional to the square of the Voltage (V) and
- the clock frequency (f). The coefficient is used to
- calculate the dynamic power as below -
-
- Pdyn = dynamic-power-coefficient * V^2 * f
-
- where voltage is in V, frequency is in MHz.
-
-Example 1 (dual-cluster big.LITTLE system 32-bit):
-
- cpus {
- #size-cells = <0>;
- #address-cells = <1>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x1>;
- };
-
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x100>;
- };
-
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a7";
- reg = <0x101>;
- };
- };
-
-Example 2 (Cortex-A8 uniprocessor 32-bit system):
-
- cpus {
- #size-cells = <0>;
- #address-cells = <1>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a8";
- reg = <0x0>;
- };
- };
-
-Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
-
- cpus {
- #size-cells = <0>;
- #address-cells = <1>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,arm926ej-s";
- reg = <0x0>;
- };
- };
-
-Example 4 (ARM Cortex-A57 64-bit system):
-
-cpus {
- #size-cells = <0>;
- #address-cells = <2>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x0>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x1>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@10000 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x10000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@10001 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x10001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@10100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x10100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@10101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x0 0x10101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100000000 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x0>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100000001 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x1>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100000100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100000101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100010000 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x10000>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100010001 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x10001>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100010100 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x10100>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-
- cpu@100010101 {
- device_type = "cpu";
- compatible = "arm,cortex-a57";
- reg = <0x1 0x10101>;
- enable-method = "spin-table";
- cpu-release-addr = <0 0x20000000>;
- };
-};
-
---
-[1] arm/msm/qcom,saw2.txt
-[2] arm/msm/qcom,kpss-acc.txt
-[3] ARM Linux kernel documentation - idle states bindings
- Documentation/devicetree/bindings/arm/idle-states.txt
-[4] ARM Linux kernel documentation - cpu capacity bindings
- Documentation/devicetree/bindings/arm/cpu-capacity.txt
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
new file mode 100644
index 000000000000..bb75914324a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -0,0 +1,503 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM CPUs bindings
+
+maintainers:
+ - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+
+description: |+
+ The device tree allows to describe the layout of CPUs in a system through
+ the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+ defining properties for every cpu.
+
+ Bindings for CPU nodes follow the Devicetree Specification, available from:
+
+ https://www.devicetree.org/specifications/
+
+ with updates for 32-bit and 64-bit ARM systems provided in this document.
+
+ ================================
+ Convention used in this document
+ ================================
+
+ This document follows the conventions described in the Devicetree
+ Specification, with the addition:
+
+ - square brackets define bitfields, eg reg[7:0] value of the bitfield in
+ the reg property contained in bits 7 down to 0
+
+ =====================================
+ cpus and cpu node bindings definition
+ =====================================
+
+ The ARM architecture, in accordance with the Devicetree Specification,
+ requires the cpus and cpu nodes to be present and contain the properties
+ described below.
+
+properties:
+ $nodename:
+ const: cpus
+ description: Container of cpu nodes
+
+ '#address-cells':
+ enum: [1, 2]
+ description: |
+ Definition depends on ARM architecture version and configuration:
+
+ On uniprocessor ARM architectures previous to v7
+ value must be 1, to enable a simple enumeration
+ scheme for processors that do not have a HW CPU
+ identification register.
+ On 32-bit ARM 11 MPcore, ARM v7 or later systems
+ value must be 1, that corresponds to CPUID/MPIDR
+ registers sizes.
+ On ARM v8 64-bit systems value should be set to 2,
+ that corresponds to the MPIDR_EL1 register size.
+ If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
+ in the system, #address-cells can be set to 1, since
+ MPIDR_EL1[63:32] bits are not used for CPUs
+ identification.
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^cpu@[0-9a-f]+$':
+ properties:
+ device_type:
+ const: cpu
+
+ reg:
+ maxItems: 1
+ description: |
+ Usage and definition depend on ARM architecture version and
+ configuration:
+
+ On uniprocessor ARM architectures previous to v7
+ this property is required and must be set to 0.
+
+ On ARM 11 MPcore based systems this property is
+ required and matches the CPUID[11:0] register bits.
+
+ Bits [11:0] in the reg cell must be set to
+ bits [11:0] in CPU ID register.
+
+ All other bits in the reg cell must be set to 0.
+
+ On 32-bit ARM v7 or later systems this property is
+ required and matches the CPU MPIDR[23:0] register
+ bits.
+
+ Bits [23:0] in the reg cell must be set to
+ bits [23:0] in MPIDR.
+
+ All other bits in the reg cell must be set to 0.
+
+ On ARM v8 64-bit systems this property is required
+ and matches the MPIDR_EL1 register affinity bits.
+
+ * If cpus node's #address-cells property is set to 2
+
+ The first reg cell bits [7:0] must be set to
+ bits [39:32] of MPIDR_EL1.
+
+ The second reg cell bits [23:0] must be set to
+ bits [23:0] of MPIDR_EL1.
+
+ * If cpus node's #address-cells property is set to 1
+
+ The reg cell bits [23:0] must be set to bits [23:0]
+ of MPIDR_EL1.
+
+ All other bits in the reg cells must be set to 0.
+
+ compatible:
+ items:
+ - enum:
+ - arm,arm710t
+ - arm,arm720t
+ - arm,arm740t
+ - arm,arm7ej-s
+ - arm,arm7tdmi
+ - arm,arm7tdmi-s
+ - arm,arm9es
+ - arm,arm9ej-s
+ - arm,arm920t
+ - arm,arm922t
+ - arm,arm925
+ - arm,arm926e-s
+ - arm,arm926ej-s
+ - arm,arm940t
+ - arm,arm946e-s
+ - arm,arm966e-s
+ - arm,arm968e-s
+ - arm,arm9tdmi
+ - arm,arm1020e
+ - arm,arm1020t
+ - arm,arm1022e
+ - arm,arm1026ej-s
+ - arm,arm1136j-s
+ - arm,arm1136jf-s
+ - arm,arm1156t2-s
+ - arm,arm1156t2f-s
+ - arm,arm1176jzf
+ - arm,arm1176jz-s
+ - arm,arm1176jzf-s
+ - arm,arm11mpcore
+ - arm,cortex-a5
+ - arm,cortex-a7
+ - arm,cortex-a8
+ - arm,cortex-a9
+ - arm,cortex-a12
+ - arm,cortex-a15
+ - arm,cortex-a17
+ - arm,cortex-a53
+ - arm,cortex-a57
+ - arm,cortex-a72
+ - arm,cortex-a73
+ - arm,cortex-m0
+ - arm,cortex-m0+
+ - arm,cortex-m1
+ - arm,cortex-m3
+ - arm,cortex-m4
+ - arm,cortex-r4
+ - arm,cortex-r5
+ - arm,cortex-r7
+ - brcm,brahma-b15
+ - brcm,brahma-b53
+ - brcm,vulcan
+ - cavium,thunder
+ - cavium,thunder2
+ - faraday,fa526
+ - intel,sa110
+ - intel,sa1100
+ - marvell,feroceon
+ - marvell,mohawk
+ - marvell,pj4a
+ - marvell,pj4b
+ - marvell,sheeva-v5
+ - nvidia,tegra132-denver
+ - nvidia,tegra186-denver
+ - nvidia,tegra194-carmel
+ - qcom,krait
+ - qcom,kryo
+ - qcom,kryo385
+ - qcom,scorpion
+
+ enable-method:
+ allOf:
+ - $ref: '/schemas/types.yaml#/definitions/string'
+ - oneOf:
+ # On ARM v8 64-bit this property is required
+ - enum:
+ - psci
+ - spin-table
+ # On ARM 32-bit systems this property is optional
+ - enum:
+ - actions,s500-smp
+ - allwinner,sun6i-a31
+ - allwinner,sun8i-a23
+ - allwinner,sun9i-a80-smp
+ - allwinner,sun8i-a83t-smp
+ - amlogic,meson8-smp
+ - amlogic,meson8b-smp
+ - arm,realview-smp
+ - brcm,bcm11351-cpu-method
+ - brcm,bcm23550
+ - brcm,bcm2836-smp
+ - brcm,bcm63138
+ - brcm,bcm-nsp-smp
+ - brcm,brahma-b15
+ - marvell,armada-375-smp
+ - marvell,armada-380-smp
+ - marvell,armada-390-smp
+ - marvell,armada-xp-smp
+ - marvell,98dx3236-smp
+ - mediatek,mt6589-smp
+ - mediatek,mt81xx-tz-smp
+ - qcom,gcc-msm8660
+ - qcom,kpss-acc-v1
+ - qcom,kpss-acc-v2
+ - renesas,apmu
+ - renesas,r9a06g032-smp
+ - rockchip,rk3036-smp
+ - rockchip,rk3066-smp
+ - ste,dbx500-smp
+
+ cpu-release-addr:
+ $ref: '/schemas/types.yaml#/definitions/uint64'
+
+ description:
+ Required for systems that have an "enable-method"
+ property value of "spin-table".
+ On ARM v8 64-bit systems must be a two cell
+ property identifying a 64-bit zero-initialised
+ memory location.
+
+ qcom,saw:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Usage: required for systems that have an "enable-method"
+ property value of "qcom,kpss-acc-v1" or
+ "qcom,kpss-acc-v2"
+ Definition: Specifies the SAW[1] node associated with this CPU.
+
+ qcom,acc:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: |
+ Usage: required for systems that have an "enable-method"
+ property value of "qcom,kpss-acc-v1" or
+ "qcom,kpss-acc-v2"
+ Definition: Specifies the ACC[2] node associated with this CPU.
+
+ cpu-idle-states:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ description: |
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ description: List of phandles to idle state nodes supported
+ by this cpu [3].
+
+ capacity-dmips-mhz:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ u32 value representing CPU capacity [4] in
+ DMIPS/MHz, relative to highest capacity-dmips-mhz
+ in the system.
+
+ rockchip,pmu:
+ description: |
+ Optional for systems that have an "enable-method"
+ property value of "rockchip,rk3066-smp"
+ While optional, it is the preferred way to get access to
+ the cpu-core power-domains.
+ Value type: <phandle>
+ Definition: Specifies the syscon node controlling the cpu core
+ power domains.
+
+ dynamic-power-coefficient:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ A u32 value that represents the running time dynamic
+ power coefficient in units of uW/MHz/V^2. The
+ coefficient can either be calculated from power
+ measurements or derived by analysis.
+
+ The dynamic power consumption of the CPU is
+ proportional to the square of the Voltage (V) and
+ the clock frequency (f). The coefficient is used to
+ calculate the dynamic power as below -
+
+ Pdyn = dynamic-power-coefficient * V^2 * f
+
+ where voltage is in V, frequency is in MHz.
+
+ required:
+ - device_type
+ - reg
+ - compatible
+
+ dependencies:
+ cpu-release-addr: [enable-method]
+ rockchip,pmu: [enable-method]
+
+required:
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ };
+ };
+
+ - |
+ // Example 2 (Cortex-A8 uniprocessor 32-bit system):
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a8";
+ reg = <0x0>;
+ };
+ };
+
+ - |
+ // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,arm926ej-s";
+ reg = <0x0>;
+ };
+ };
+
+ - |
+ // Example 4 (ARM Cortex-A57 64-bit system):
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+
+ cpu@100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x1 0x10101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0 0x20000000>;
+ };
+ };
+...
--
2.17.1
^ permalink raw reply related
* [PATCH 13/36] dt-bindings: arm: Convert PMU binding to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Will Deacon, Linus Walleij, Pantelis Antoniou, Bjorn Andersson,
Mark Brown, Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert ARM PMU binding to DT schema format using json-schema.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/pmu.txt | 70 --------------
.../devicetree/bindings/arm/pmu.yaml | 96 +++++++++++++++++++
2 files changed, 96 insertions(+), 70 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/pmu.txt
create mode 100644 Documentation/devicetree/bindings/arm/pmu.yaml
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
deleted file mode 100644
index 13611a8199bb..000000000000
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-* ARM Performance Monitor Units
-
-ARM cores often have a PMU for counting cpu and cache events like cache misses
-and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
-representation in the device tree should be done as under:-
-
-Required properties:
-
-- compatible : should be one of
- "apm,potenza-pmu"
- "arm,armv8-pmuv3"
- "arm,cortex-a73-pmu"
- "arm,cortex-a72-pmu"
- "arm,cortex-a57-pmu"
- "arm,cortex-a53-pmu"
- "arm,cortex-a35-pmu"
- "arm,cortex-a17-pmu"
- "arm,cortex-a15-pmu"
- "arm,cortex-a12-pmu"
- "arm,cortex-a9-pmu"
- "arm,cortex-a8-pmu"
- "arm,cortex-a7-pmu"
- "arm,cortex-a5-pmu"
- "arm,arm11mpcore-pmu"
- "arm,arm1176-pmu"
- "arm,arm1136-pmu"
- "brcm,vulcan-pmu"
- "cavium,thunder-pmu"
- "qcom,scorpion-pmu"
- "qcom,scorpion-mp-pmu"
- "qcom,krait-pmu"
-- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
- interrupt (PPI) then 1 interrupt should be specified.
-
-Optional properties:
-
-- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
- nodes corresponding directly to the affinity of
- the SPIs listed in the interrupts property.
-
- When using a PPI, specifies a list of phandles to CPU
- nodes corresponding to the set of CPUs which have
- a PMU of this type signalling the PPI listed in the
- interrupts property, unless this is already specified
- by the PPI interrupt specifier itself (in which case
- the interrupt-affinity property shouldn't be present).
-
- This property should be present when there is more than
- a single SPI.
-
-
-- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
- events.
-
-- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
- (SDER) is accessible. This will cause the driver to do
- any setup required that is only possible in ARMv7 secure
- state. If not present the ARMv7 SDER will not be touched,
- which means the PMU may fail to operate unless external
- code (bootloader or security monitor) has performed the
- appropriate initialisation. Note that this property is
- not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
- in Non-secure state.
-
-Example:
-
-pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupts = <100 101>;
-};
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml
new file mode 100644
index 000000000000..0dbb9e0566af
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/pmu.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Performance Monitor Units
+
+maintainers:
+ - Mark Rutland <mark.rutland@arm.com>
+ - Will Deacon <will.deacon@arm.com>
+description: |+
+ ARM cores often have a PMU for counting cpu and cache events like cache misses
+ and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
+ representation in the device tree should be done as under:-
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apm,potenza-pmu
+ - arm,armv8-pmuv3
+ - arm,cortex-a73-pmu
+ - arm,cortex-a72-pmu
+ - arm,cortex-a57-pmu
+ - arm,cortex-a53-pmu
+ - arm,cortex-a35-pmu
+ - arm,cortex-a17-pmu
+ - arm,cortex-a15-pmu
+ - arm,cortex-a12-pmu
+ - arm,cortex-a9-pmu
+ - arm,cortex-a8-pmu
+ - arm,cortex-a7-pmu
+ - arm,cortex-a5-pmu
+ - arm,arm11mpcore-pmu
+ - arm,arm1176-pmu
+ - arm,arm1136-pmu
+ - brcm,vulcan-pmu
+ - cavium,thunder-pmu
+ - qcom,scorpion-pmu
+ - qcom,scorpion-mp-pmu
+ - qcom,krait-pmu
+ interrupts:
+ oneOf:
+ - maxItems: 1
+ - minItems: 2
+ maxItems: 8
+ description: 1 interrupt per core.
+
+ interrupts-extended:
+ $ref: '#/properties/interrupts'
+
+ interrupt-affinity:
+ description:
+ When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
+ the SPIs listed in the interrupts property.
+
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property, unless this is already specified
+ by the PPI interrupt specifier itself (in which case
+ the interrupt-affinity property shouldn't be present).
+
+ This property should be present when there is more than
+ a single SPI.
+
+ qcom,no-pc-write:
+ type: boolean
+ description:
+ Indicates that this PMU doesn't support the 0xc and 0xd events.
+
+ secure-reg-access:
+ type: boolean
+ description:
+ Indicates that the ARMv7 Secure Debug Enable Register
+ (SDER) is accessible. This will cause the driver to do
+ any setup required that is only possible in ARMv7 secure
+ state. If not present the ARMv7 SDER will not be touched,
+ which means the PMU may fail to operate unless external
+ code (bootloader or security monitor) has performed the
+ appropriate initialisation. Note that this property is
+ not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
+ in Non-secure state.
+
+required:
+ - compatible
+
+oneOf:
+ - required:
+ - interrupts
+ - required:
+ - interrupts-extended
+
+...
--
2.17.1
^ permalink raw reply related
* [PATCH 14/36] dt-bindings: arm: Convert primecell binding to json-schema
From: Rob Herring @ 2018-10-05 16:58 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linuxppc-dev
Cc: Mark Rutland, Tom Rini, Kumar Gala, Grant Likely, Arnd Bergmann,
Linus Walleij, Pantelis Antoniou, Bjorn Andersson, Mark Brown,
Geert Uytterhoeven, Olof Johansson, Frank Rowand,
Jonathan Cameron
In-Reply-To: <20181005165848.3474-1-robh@kernel.org>
Convert ARM Primecell binding to DT schema format using json-schema.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/primecell.txt | 46 -------------------
.../devicetree/bindings/arm/primecell.yaml | 35 ++++++++++++++
2 files changed, 35 insertions(+), 46 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/primecell.txt
create mode 100644 Documentation/devicetree/bindings/arm/primecell.yaml
diff --git a/Documentation/devicetree/bindings/arm/primecell.txt b/Documentation/devicetree/bindings/arm/primecell.txt
deleted file mode 100644
index 0df6acacfaea..000000000000
--- a/Documentation/devicetree/bindings/arm/primecell.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* ARM Primecell Peripherals
-
-ARM, Ltd. Primecell peripherals have a standard id register that can be used to
-identify the peripheral type, vendor, and revision. This value can be used for
-driver matching.
-
-Required properties:
-
-- compatible : should be a specific name for the peripheral and
- "arm,primecell". The specific name will match the ARM
- engineering name for the logic block in the form: "arm,pl???"
-
-Optional properties:
-
-- arm,primecell-periphid : Value to override the h/w value with
-- clocks : From common clock binding. First clock is phandle to clock for apb
- pclk. Additional clocks are optional and specific to those peripherals.
-- clock-names : From common clock binding. Shall be "apb_pclk" for first clock.
-- dmas : From common DMA binding. If present, refers to one or more dma channels.
-- dma-names : From common DMA binding, needs to match the 'dmas' property.
- Devices with exactly one receive and transmit channel shall name
- these "rx" and "tx", respectively.
-- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
-- pinctrl-names : Names corresponding to the numbered pinctrl states
-- interrupts : one or more interrupt specifiers
-- interrupt-names : names corresponding to the interrupts properties
-
-Example:
-
-serial@fff36000 {
- compatible = "arm,pl011", "arm,primecell";
- arm,primecell-periphid = <0x00341011>;
-
- clocks = <&pclk>;
- clock-names = "apb_pclk";
-
- dmas = <&dma-controller 4>, <&dma-controller 5>;
- dma-names = "rx", "tx";
-
- pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
- pinctrl-1 = <&uart0_sleep_mode>;
- pinctrl-names = "default","sleep";
-
- interrupts = <0 11 0x4>;
-};
-
diff --git a/Documentation/devicetree/bindings/arm/primecell.yaml b/Documentation/devicetree/bindings/arm/primecell.yaml
new file mode 100644
index 000000000000..d8097521dc7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/primecell.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: None
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bindings/arm/primecell.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Primecell Peripherals
+
+maintainers:
+ - Grant Likely <grant.likely@secretlab.ca>
+description: |+
+ ARM, Ltd. Primecell peripherals have a standard id register that can be used to
+ identify the peripheral type, vendor, and revision. This value can be used for
+ driver matching.
+
+properties:
+ compatible:
+ contains:
+ const: arm,primecell
+ description:
+ Should be a specific name for the peripheral followed by "arm,primecell".
+ The specific name will match the ARM engineering name for the logic block
+ in the form "arm,pl???"
+
+ arm,primecell-periphid:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Value to override the h/w ID value
+ clocks:
+ minItems: 1
+ maxItems: 32
+ clock-names:
+ contains:
+ const: apb_pclk
+ additionalItems: true
+...
--
2.17.1
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