* [PATCH v5 25/33] KVM: PPC: Book3S HV: Invalidate TLB when nested vcpu moves physical cpu
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
This is only done at level 0, since only level 0 knows which physical
CPU a vcpu is running on. This does for nested guests what L0 already
did for its own guests, which is to flush the TLB on a pCPU when it
goes to run a vCPU there, and there is another vCPU in the same VM
which previously ran on this pCPU and has now started to run on another
pCPU. This is to handle the situation where the other vCPU touched
a mapping, moved to another pCPU and did a tlbiel (local-only tlbie)
on that new pCPU and thus left behind a stale TLB entry on this pCPU.
This introduces a limit on the the vcpu_token values used in the
H_ENTER_NESTED hcall -- they must now be less than NR_CPUS.
[paulus@ozlabs.org - made prev_cpu array be short[] to reduce
memory consumption.]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/kvm_book3s_64.h | 3 +
arch/powerpc/kvm/book3s_hv.c | 101 +++++++++++++++++++------------
arch/powerpc/kvm/book3s_hv_nested.c | 5 ++
3 files changed, 71 insertions(+), 38 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index 719b31723..83d4def 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -52,6 +52,9 @@ struct kvm_nested_guest {
long refcnt; /* number of pointers to this struct */
struct mutex tlb_lock; /* serialize page faults and tlbies */
struct kvm_nested_guest *next;
+ cpumask_t need_tlb_flush;
+ cpumask_t cpu_in_guest;
+ short prev_cpu[NR_CPUS];
};
/*
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 49f07de..24a6683 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -2397,10 +2397,18 @@ static void kvmppc_release_hwthread(int cpu)
static void radix_flush_cpu(struct kvm *kvm, int cpu, struct kvm_vcpu *vcpu)
{
+ struct kvm_nested_guest *nested = vcpu->arch.nested;
+ cpumask_t *cpu_in_guest;
int i;
cpu = cpu_first_thread_sibling(cpu);
- cpumask_set_cpu(cpu, &kvm->arch.need_tlb_flush);
+ if (nested) {
+ cpumask_set_cpu(cpu, &nested->need_tlb_flush);
+ cpu_in_guest = &nested->cpu_in_guest;
+ } else {
+ cpumask_set_cpu(cpu, &kvm->arch.need_tlb_flush);
+ cpu_in_guest = &kvm->arch.cpu_in_guest;
+ }
/*
* Make sure setting of bit in need_tlb_flush precedes
* testing of cpu_in_guest bits. The matching barrier on
@@ -2408,13 +2416,23 @@ static void radix_flush_cpu(struct kvm *kvm, int cpu, struct kvm_vcpu *vcpu)
*/
smp_mb();
for (i = 0; i < threads_per_core; ++i)
- if (cpumask_test_cpu(cpu + i, &kvm->arch.cpu_in_guest))
+ if (cpumask_test_cpu(cpu + i, cpu_in_guest))
smp_call_function_single(cpu + i, do_nothing, NULL, 1);
}
static void kvmppc_prepare_radix_vcpu(struct kvm_vcpu *vcpu, int pcpu)
{
+ struct kvm_nested_guest *nested = vcpu->arch.nested;
struct kvm *kvm = vcpu->kvm;
+ int prev_cpu;
+
+ if (!cpu_has_feature(CPU_FTR_HVMODE))
+ return;
+
+ if (nested)
+ prev_cpu = nested->prev_cpu[vcpu->arch.nested_vcpu_id];
+ else
+ prev_cpu = vcpu->arch.prev_cpu;
/*
* With radix, the guest can do TLB invalidations itself,
@@ -2428,12 +2446,46 @@ static void kvmppc_prepare_radix_vcpu(struct kvm_vcpu *vcpu, int pcpu)
* ran to flush the TLB. The TLB is shared between threads,
* so we use a single bit in .need_tlb_flush for all 4 threads.
*/
- if (vcpu->arch.prev_cpu != pcpu) {
- if (vcpu->arch.prev_cpu >= 0 &&
- cpu_first_thread_sibling(vcpu->arch.prev_cpu) !=
+ if (prev_cpu != pcpu) {
+ if (prev_cpu >= 0 &&
+ cpu_first_thread_sibling(prev_cpu) !=
cpu_first_thread_sibling(pcpu))
- radix_flush_cpu(kvm, vcpu->arch.prev_cpu, vcpu);
- vcpu->arch.prev_cpu = pcpu;
+ radix_flush_cpu(kvm, prev_cpu, vcpu);
+ if (nested)
+ nested->prev_cpu[vcpu->arch.nested_vcpu_id] = pcpu;
+ else
+ vcpu->arch.prev_cpu = pcpu;
+ }
+}
+
+static void kvmppc_radix_check_need_tlb_flush(struct kvm *kvm, int pcpu,
+ struct kvm_nested_guest *nested)
+{
+ cpumask_t *need_tlb_flush;
+ int lpid;
+
+ if (!cpu_has_feature(CPU_FTR_HVMODE))
+ return;
+
+ if (cpu_has_feature(CPU_FTR_ARCH_300))
+ pcpu &= ~0x3UL;
+
+ if (nested) {
+ lpid = nested->shadow_lpid;
+ need_tlb_flush = &nested->need_tlb_flush;
+ } else {
+ lpid = kvm->arch.lpid;
+ need_tlb_flush = &kvm->arch.need_tlb_flush;
+ }
+
+ mtspr(SPRN_LPID, lpid);
+ isync();
+ smp_mb();
+
+ if (cpumask_test_cpu(pcpu, need_tlb_flush)) {
+ radix__local_flush_tlb_lpid_guest(lpid);
+ /* Clear the bit after the TLB flush */
+ cpumask_clear_cpu(pcpu, need_tlb_flush);
}
}
@@ -3127,8 +3179,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
spin_unlock(&core_info.vc[sub]->lock);
if (kvm_is_radix(vc->kvm)) {
- int tmp = pcpu;
-
/*
* Do we need to flush the process scoped TLB for the LPAR?
*
@@ -3139,17 +3189,7 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)
*
* Hash must be flushed in realmode in order to use tlbiel.
*/
- mtspr(SPRN_LPID, vc->kvm->arch.lpid);
- isync();
-
- if (cpu_has_feature(CPU_FTR_ARCH_300))
- tmp &= ~0x3UL;
-
- if (cpumask_test_cpu(tmp, &vc->kvm->arch.need_tlb_flush)) {
- radix__local_flush_tlb_lpid_guest(vc->kvm->arch.lpid);
- /* Clear the bit after the TLB flush */
- cpumask_clear_cpu(tmp, &vc->kvm->arch.need_tlb_flush);
- }
+ kvmppc_radix_check_need_tlb_flush(vc->kvm, pcpu, NULL);
}
/*
@@ -3868,12 +3908,11 @@ int kvmhv_run_single_vcpu(struct kvm_run *kvm_run,
struct kvm_vcpu *vcpu, u64 time_limit,
unsigned long lpcr)
{
- int trap, r, pcpu, pcpu0;
+ int trap, r, pcpu;
int srcu_idx;
struct kvmppc_vcore *vc;
struct kvm *kvm = vcpu->kvm;
struct kvm_nested_guest *nested = vcpu->arch.nested;
- unsigned long lpid;
trace_kvmppc_run_vcpu_enter(vcpu);
@@ -3946,22 +3985,8 @@ int kvmhv_run_single_vcpu(struct kvm_run *kvm_run,
vc->vcore_state = VCORE_RUNNING;
trace_kvmppc_run_core(vc, 0);
- lpid = vc->kvm->arch.lpid;
- if (nested)
- lpid = nested->shadow_lpid;
- mtspr(SPRN_LPID, lpid);
- isync();
-
- /* See comment above in kvmppc_run_core() about this */
- pcpu0 = pcpu;
- if (cpu_has_feature(CPU_FTR_ARCH_300))
- pcpu0 &= ~0x3UL;
-
- if (cpumask_test_cpu(pcpu0, &kvm->arch.need_tlb_flush)) {
- radix__local_flush_tlb_lpid_guest(lpid);
- /* Clear the bit after the TLB flush */
- cpumask_clear_cpu(pcpu0, &kvm->arch.need_tlb_flush);
- }
+ if (cpu_has_feature(CPU_FTR_HVMODE))
+ kvmppc_radix_check_need_tlb_flush(kvm, pcpu, nested);
trace_hardirqs_on();
guest_enter_irqoff();
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index 486d900..a876dc3 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -168,6 +168,9 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
if (err)
return H_PARAMETER;
+ if (l2_hv.vcpu_token >= NR_CPUS)
+ return H_PARAMETER;
+
/* translate lpid */
l2 = kvmhv_get_nested(vcpu->kvm, l2_hv.lpid, true);
if (!l2)
@@ -412,6 +415,8 @@ struct kvm_nested_guest *kvmhv_alloc_nested(struct kvm *kvm, unsigned int lpid)
goto out_free2;
gp->shadow_lpid = shadow_lpid;
+ memset(gp->prev_cpu, -1, sizeof(gp->prev_cpu));
+
return gp;
out_free2:
--
2.7.4
^ permalink raw reply related
* [PATCH v5 26/33] KVM: PPC: Book3S HV: Don't access HFSCR, LPIDR or LPCR when running nested
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
When running as a nested hypervisor, this avoids reading hypervisor
privileged registers (specifically HFSCR, LPIDR and LPCR) at startup;
instead reasonable default values are used. This also avoids writing
LPIDR in the single-vcpu entry/exit path.
Also, this removes the check for CPU_FTR_HVMODE in kvmppc_mmu_hv_init()
since its only caller already checks this.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/kvm/book3s_64_mmu_hv.c | 7 +++----
arch/powerpc/kvm/book3s_hv.c | 33 +++++++++++++++++++++------------
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 68e14af..c615617 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -268,14 +268,13 @@ int kvmppc_mmu_hv_init(void)
{
unsigned long host_lpid, rsvd_lpid;
- if (!cpu_has_feature(CPU_FTR_HVMODE))
- return -EINVAL;
-
if (!mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE))
return -EINVAL;
/* POWER7 has 10-bit LPIDs (12-bit in POWER8) */
- host_lpid = mfspr(SPRN_LPID);
+ host_lpid = 0;
+ if (cpu_has_feature(CPU_FTR_HVMODE))
+ host_lpid = mfspr(SPRN_LPID);
rsvd_lpid = LPID_RSVD;
kvmppc_init_lpid(rsvd_lpid + 1);
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 24a6683..b8f14ea 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -2174,15 +2174,18 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_hv(struct kvm *kvm,
* Set the default HFSCR for the guest from the host value.
* This value is only used on POWER9.
* On POWER9, we want to virtualize the doorbell facility, so we
- * turn off the HFSCR bit, which causes those instructions to trap.
+ * don't set the HFSCR_MSGP bit, and that causes those instructions
+ * to trap and then we emulate them.
*/
- vcpu->arch.hfscr = mfspr(SPRN_HFSCR);
- if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
+ vcpu->arch.hfscr = HFSCR_TAR | HFSCR_EBB | HFSCR_PM | HFSCR_BHRB |
+ HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP;
+ if (cpu_has_feature(CPU_FTR_HVMODE)) {
+ vcpu->arch.hfscr &= mfspr(SPRN_HFSCR);
+ if (cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
+ vcpu->arch.hfscr |= HFSCR_TM;
+ }
+ if (cpu_has_feature(CPU_FTR_TM_COMP))
vcpu->arch.hfscr |= HFSCR_TM;
- else if (!cpu_has_feature(CPU_FTR_TM_COMP))
- vcpu->arch.hfscr &= ~HFSCR_TM;
- if (cpu_has_feature(CPU_FTR_ARCH_300))
- vcpu->arch.hfscr &= ~HFSCR_MSGP;
kvmppc_mmu_book3s_hv_init(vcpu);
@@ -4002,8 +4005,10 @@ int kvmhv_run_single_vcpu(struct kvm_run *kvm_run,
srcu_read_unlock(&kvm->srcu, srcu_idx);
- mtspr(SPRN_LPID, kvm->arch.host_lpid);
- isync();
+ if (cpu_has_feature(CPU_FTR_HVMODE)) {
+ mtspr(SPRN_LPID, kvm->arch.host_lpid);
+ isync();
+ }
trace_hardirqs_off();
set_irq_happened(trap);
@@ -4630,9 +4635,13 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
kvm->arch.host_sdr1 = mfspr(SPRN_SDR1);
/* Init LPCR for virtual RMA mode */
- kvm->arch.host_lpid = mfspr(SPRN_LPID);
- kvm->arch.host_lpcr = lpcr = mfspr(SPRN_LPCR);
- lpcr &= LPCR_PECE | LPCR_LPES;
+ if (cpu_has_feature(CPU_FTR_HVMODE)) {
+ kvm->arch.host_lpid = mfspr(SPRN_LPID);
+ kvm->arch.host_lpcr = lpcr = mfspr(SPRN_LPCR);
+ lpcr &= LPCR_PECE | LPCR_LPES;
+ } else {
+ lpcr = 0;
+ }
lpcr |= (4UL << LPCR_DPFD_SH) | LPCR_HDICE |
LPCR_VPM0 | LPCR_VPM1;
kvm->arch.vrma_slb_v = SLB_VSID_B_1T |
--
2.7.4
^ permalink raw reply related
* [PATCH v5 27/33] KVM: PPC: Book3S HV: Add one-reg interface to virtual PTCR register
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
This adds a one-reg register identifier which can be used to read and
set the virtual PTCR for the guest. This register identifies the
address and size of the virtual partition table for the guest, which
contains information about the nested guests under this guest.
Migrating this value is the only extra requirement for migrating a
guest which has nested guests (assuming of course that the destination
host supports nested virtualization in the kvm-hv module).
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
Documentation/virtual/kvm/api.txt | 1 +
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 6 ++++++
3 files changed, 8 insertions(+)
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 647f941..2f5f9b7 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1922,6 +1922,7 @@ registers, find a list below:
PPC | KVM_REG_PPC_TIDR | 64
PPC | KVM_REG_PPC_PSSCR | 64
PPC | KVM_REG_PPC_DEC_EXPIRY | 64
+ PPC | KVM_REG_PPC_PTCR | 64
PPC | KVM_REG_PPC_TM_GPR0 | 64
...
PPC | KVM_REG_PPC_TM_GPR31 | 64
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index 1b32b56..8c876c1 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -634,6 +634,7 @@ struct kvm_ppc_cpu_char {
#define KVM_REG_PPC_DEC_EXPIRY (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbe)
#define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
+#define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0)
/* Transactional Memory checkpointed state:
* This is all GPRs, all VSX regs and a subset of SPRs
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index b8f14ea..127bb5f 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1710,6 +1710,9 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
case KVM_REG_PPC_ONLINE:
*val = get_reg_val(id, vcpu->arch.online);
break;
+ case KVM_REG_PPC_PTCR:
+ *val = get_reg_val(id, vcpu->kvm->arch.l1_ptcr);
+ break;
default:
r = -EINVAL;
break;
@@ -1941,6 +1944,9 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
atomic_dec(&vcpu->arch.vcore->online_count);
vcpu->arch.online = i;
break;
+ case KVM_REG_PPC_PTCR:
+ vcpu->kvm->arch.l1_ptcr = set_reg_val(id, *val);
+ break;
default:
r = -EINVAL;
break;
--
2.7.4
^ permalink raw reply related
* [PATCH v5 28/33] KVM: PPC: Book3S HV: Sanitise hv_regs on nested guest entry
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
restore_hv_regs() is used to copy the hv_regs L1 wants to set to run the
nested (L2) guest into the vcpu structure. We need to sanitise these
values to ensure we don't let the L1 guest hypervisor do things we don't
want it to.
We don't let data address watchpoints or completed instruction address
breakpoints be set to match in hypervisor state.
We also don't let L1 enable features in the hypervisor facility status
and control register (HFSCR) for L2 which we have disabled for L1. That
is L2 will get the subset of features which the L0 hypervisor has
enabled for L1 and the features L1 wants to enable for L2. This could
mean we give L1 a hypervisor facility unavailable interrupt for a
facility it thinks it has enabled, however it shouldn't have enabled a
facility it itself doesn't have for the L2 guest.
We sanitise the registers when copying in the L2 hv_regs. We don't need
to sanitise when copying back the L1 hv_regs since these shouldn't be
able to contain invalid values as they're just what was copied out.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/reg.h | 1 +
arch/powerpc/kvm/book3s_hv_nested.c | 17 +++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 6fda746..c9069897 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -415,6 +415,7 @@
#define HFSCR_DSCR __MASK(FSCR_DSCR_LG)
#define HFSCR_VECVSX __MASK(FSCR_VECVSX_LG)
#define HFSCR_FP __MASK(FSCR_FP_LG)
+#define HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
#define SPRN_TAR 0x32f /* Target Address Register */
#define SPRN_LPCR 0x13E /* LPAR Control Register */
#define LPCR_VPM0 ASM_CONST(0x8000000000000000)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index a876dc3..e2305962 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -86,6 +86,22 @@ static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
}
}
+static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
+{
+ /*
+ * Don't let L1 enable features for L2 which we've disabled for L1,
+ * but preserve the interrupt cause field.
+ */
+ hr->hfscr &= (HFSCR_INTR_CAUSE | vcpu->arch.hfscr);
+
+ /* Don't let data address watchpoint match in hypervisor state */
+ hr->dawrx0 &= ~DAWRX_HYP;
+
+ /* Don't let completed instruction address breakpt match in HV state */
+ if ((hr->ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
+ hr->ciabr &= ~CIABR_PRIV;
+}
+
static void restore_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
{
struct kvmppc_vcore *vc = vcpu->arch.vcore;
@@ -198,6 +214,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
mask = LPCR_DPFD | LPCR_ILE | LPCR_TC | LPCR_AIL | LPCR_LD |
LPCR_LPES | LPCR_MER;
lpcr = (vc->lpcr & ~mask) | (l2_hv.lpcr & mask);
+ sanitise_hv_regs(vcpu, &l2_hv);
restore_hv_regs(vcpu, &l2_hv);
vcpu->arch.ret = RESUME_GUEST;
--
2.7.4
^ permalink raw reply related
* [PATCH v5 29/33] KVM: PPC: Book3S HV: Handle differing endianness for H_ENTER_NESTED
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The hcall H_ENTER_NESTED takes two parameters: the address in L1 guest
memory of a hv_regs struct and the address of a pt_regs struct. The
hcall requests the L0 hypervisor to use the register values in these
structs to run a L2 guest and to return the exit state of the L2 guest
in these structs. These are in the endianness of the L1 guest, rather
than being always big-endian as is usually the case for PAPR
hypercalls.
This is convenient because it means that the L1 guest can pass the
address of the regs field in its kvm_vcpu_arch struct. This also
improves performance slightly by avoiding the need for two copies of
the pt_regs struct.
When reading/writing these structures, this patch handles the case
where the endianness of the L1 guest differs from that of the L0
hypervisor, by byteswapping the structures after reading and before
writing them back.
Since all the fields of the pt_regs are of the same type, i.e.,
unsigned long, we treat it as an array of unsigned longs. The fields
of struct hv_guest_state are not all the same, so its fields are
byteswapped individually.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/kvm/book3s_hv_nested.c | 51 ++++++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index e2305962..3f21f78 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -51,6 +51,48 @@ void kvmhv_save_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)
hr->ppr = vcpu->arch.ppr;
}
+static void byteswap_pt_regs(struct pt_regs *regs)
+{
+ unsigned long *addr = (unsigned long *) regs;
+
+ for (; addr < ((unsigned long *) (regs + 1)); addr++)
+ *addr = swab64(*addr);
+}
+
+static void byteswap_hv_regs(struct hv_guest_state *hr)
+{
+ hr->version = swab64(hr->version);
+ hr->lpid = swab32(hr->lpid);
+ hr->vcpu_token = swab32(hr->vcpu_token);
+ hr->lpcr = swab64(hr->lpcr);
+ hr->pcr = swab64(hr->pcr);
+ hr->amor = swab64(hr->amor);
+ hr->dpdes = swab64(hr->dpdes);
+ hr->hfscr = swab64(hr->hfscr);
+ hr->tb_offset = swab64(hr->tb_offset);
+ hr->dawr0 = swab64(hr->dawr0);
+ hr->dawrx0 = swab64(hr->dawrx0);
+ hr->ciabr = swab64(hr->ciabr);
+ hr->hdec_expiry = swab64(hr->hdec_expiry);
+ hr->purr = swab64(hr->purr);
+ hr->spurr = swab64(hr->spurr);
+ hr->ic = swab64(hr->ic);
+ hr->vtb = swab64(hr->vtb);
+ hr->hdar = swab64(hr->hdar);
+ hr->hdsisr = swab64(hr->hdsisr);
+ hr->heir = swab64(hr->heir);
+ hr->asdr = swab64(hr->asdr);
+ hr->srr0 = swab64(hr->srr0);
+ hr->srr1 = swab64(hr->srr1);
+ hr->sprg[0] = swab64(hr->sprg[0]);
+ hr->sprg[1] = swab64(hr->sprg[1]);
+ hr->sprg[2] = swab64(hr->sprg[2]);
+ hr->sprg[3] = swab64(hr->sprg[3]);
+ hr->pidr = swab64(hr->pidr);
+ hr->cfar = swab64(hr->cfar);
+ hr->ppr = swab64(hr->ppr);
+}
+
static void save_hv_return_state(struct kvm_vcpu *vcpu, int trap,
struct hv_guest_state *hr)
{
@@ -175,6 +217,8 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
sizeof(struct hv_guest_state));
if (err)
return H_PARAMETER;
+ if (kvmppc_need_byteswap(vcpu))
+ byteswap_hv_regs(&l2_hv);
if (l2_hv.version != HV_GUEST_STATE_VERSION)
return H_P2;
@@ -183,7 +227,8 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
sizeof(struct pt_regs));
if (err)
return H_PARAMETER;
-
+ if (kvmppc_need_byteswap(vcpu))
+ byteswap_pt_regs(&l2_regs);
if (l2_hv.vcpu_token >= NR_CPUS)
return H_PARAMETER;
@@ -255,6 +300,10 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)
kvmhv_put_nested(l2);
/* copy l2_hv_state and regs back to guest */
+ if (kvmppc_need_byteswap(vcpu)) {
+ byteswap_hv_regs(&l2_hv);
+ byteswap_pt_regs(&l2_regs);
+ }
err = kvm_vcpu_write_guest(vcpu, hv_ptr, &l2_hv,
sizeof(struct hv_guest_state));
if (err)
--
2.7.4
^ permalink raw reply related
* [PATCH v5 31/33] KVM: PPC: Book3S HV: Add nested shadow page tables to debugfs
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
This adds a list of valid shadow PTEs for each nested guest to
the 'radix' file for the guest in debugfs. This can be useful for
debugging.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/include/asm/kvm_book3s_64.h | 1 +
arch/powerpc/kvm/book3s_64_mmu_radix.c | 39 +++++++++++++++++++++++++++++---
arch/powerpc/kvm/book3s_hv_nested.c | 15 ++++++++++++
3 files changed, 52 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index 83d4def..6d29814 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -120,6 +120,7 @@ struct rmap_nested {
struct kvm_nested_guest *kvmhv_get_nested(struct kvm *kvm, int l1_lpid,
bool create);
void kvmhv_put_nested(struct kvm_nested_guest *gp);
+int kvmhv_nested_next_lpid(struct kvm *kvm, int lpid);
/* Encoding of first parameter for H_TLB_INVALIDATE */
#define H_TLBIE_P1_ENC(ric, prs, r) (___PPC_RIC(ric) | ___PPC_PRS(prs) | \
diff --git a/arch/powerpc/kvm/book3s_64_mmu_radix.c b/arch/powerpc/kvm/book3s_64_mmu_radix.c
index ae0e3ed..43b21e8 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_radix.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_radix.c
@@ -1002,6 +1002,7 @@ struct debugfs_radix_state {
struct kvm *kvm;
struct mutex mutex;
unsigned long gpa;
+ int lpid;
int chars_left;
int buf_index;
char buf[128];
@@ -1043,6 +1044,7 @@ static ssize_t debugfs_radix_read(struct file *file, char __user *buf,
struct kvm *kvm;
unsigned long gpa;
pgd_t *pgt;
+ struct kvm_nested_guest *nested;
pgd_t pgd, *pgdp;
pud_t pud, *pudp;
pmd_t pmd, *pmdp;
@@ -1077,10 +1079,39 @@ static ssize_t debugfs_radix_read(struct file *file, char __user *buf,
}
gpa = p->gpa;
- pgt = kvm->arch.pgtable;
- while (len != 0 && gpa < RADIX_PGTABLE_RANGE) {
+ nested = NULL;
+ pgt = NULL;
+ while (len != 0 && p->lpid >= 0) {
+ if (gpa >= RADIX_PGTABLE_RANGE) {
+ gpa = 0;
+ pgt = NULL;
+ if (nested) {
+ kvmhv_put_nested(nested);
+ nested = NULL;
+ }
+ p->lpid = kvmhv_nested_next_lpid(kvm, p->lpid);
+ p->hdr = 0;
+ if (p->lpid < 0)
+ break;
+ }
+ if (!pgt) {
+ if (p->lpid == 0) {
+ pgt = kvm->arch.pgtable;
+ } else {
+ nested = kvmhv_get_nested(kvm, p->lpid, false);
+ if (!nested) {
+ gpa = RADIX_PGTABLE_RANGE;
+ continue;
+ }
+ pgt = nested->shadow_pgtable;
+ }
+ }
+ n = 0;
if (!p->hdr) {
- n = scnprintf(p->buf, sizeof(p->buf),
+ if (p->lpid > 0)
+ n = scnprintf(p->buf, sizeof(p->buf),
+ "\nNested LPID %d: ", p->lpid);
+ n += scnprintf(p->buf + n, sizeof(p->buf) - n,
"pgdir: %lx\n", (unsigned long)pgt);
p->hdr = 1;
goto copy;
@@ -1146,6 +1177,8 @@ static ssize_t debugfs_radix_read(struct file *file, char __user *buf,
}
}
p->gpa = gpa;
+ if (nested)
+ kvmhv_put_nested(nested);
out:
mutex_unlock(&p->mutex);
diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c
index 3f21f78..401d2ec 100644
--- a/arch/powerpc/kvm/book3s_hv_nested.c
+++ b/arch/powerpc/kvm/book3s_hv_nested.c
@@ -1274,3 +1274,18 @@ long int kvmhv_nested_page_fault(struct kvm_vcpu *vcpu)
mutex_unlock(&gp->tlb_lock);
return ret;
}
+
+int kvmhv_nested_next_lpid(struct kvm *kvm, int lpid)
+{
+ int ret = -1;
+
+ spin_lock(&kvm->mmu_lock);
+ while (++lpid <= kvm->arch.max_nested_lpid) {
+ if (kvm->arch.nested_guests[lpid]) {
+ ret = lpid;
+ break;
+ }
+ }
+ spin_unlock(&kvm->mmu_lock);
+ return ret;
+}
--
2.7.4
^ permalink raw reply related
* [PATCH v5 30/33] KVM: PPC: Book3S HV: Allow HV module to load without hypervisor mode
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
With this, the KVM-HV module can be loaded in a guest running under
KVM-HV, and if the hypervisor supports nested virtualization, this
guest can now act as a nested hypervisor and run nested guests.
This also adds some checks to inform userspace that HPT guests are not
supported by nested hypervisors (by returning false for the
KVM_CAP_PPC_MMU_HASH_V3 capability), and to prevent userspace from
configuring a guest to use HPT mode.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
arch/powerpc/kvm/book3s_hv.c | 16 ++++++++++++----
arch/powerpc/kvm/powerpc.c | 3 ++-
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 127bb5f..152bf75 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -4807,11 +4807,15 @@ static int kvmppc_core_emulate_mfspr_hv(struct kvm_vcpu *vcpu, int sprn,
static int kvmppc_core_check_processor_compat_hv(void)
{
- if (!cpu_has_feature(CPU_FTR_HVMODE) ||
- !cpu_has_feature(CPU_FTR_ARCH_206))
- return -EIO;
+ if (cpu_has_feature(CPU_FTR_HVMODE) &&
+ cpu_has_feature(CPU_FTR_ARCH_206))
+ return 0;
- return 0;
+ /* POWER9 in radix mode is capable of being a nested hypervisor. */
+ if (cpu_has_feature(CPU_FTR_ARCH_300) && radix_enabled())
+ return 0;
+
+ return -EIO;
}
#ifdef CONFIG_KVM_XICS
@@ -5129,6 +5133,10 @@ static int kvmhv_configure_mmu(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
if (radix && !radix_enabled())
return -EINVAL;
+ /* If we're a nested hypervisor, we currently only support radix */
+ if (kvmhv_on_pseries() && !radix)
+ return -EINVAL;
+
mutex_lock(&kvm->lock);
if (radix != kvm_is_radix(kvm)) {
if (kvm->arch.mmu_ready) {
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index eba5756..1f4b128 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -594,7 +594,8 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
r = !!(hv_enabled && radix_enabled());
break;
case KVM_CAP_PPC_MMU_HASH_V3:
- r = !!(hv_enabled && cpu_has_feature(CPU_FTR_ARCH_300));
+ r = !!(hv_enabled && cpu_has_feature(CPU_FTR_ARCH_300) &&
+ cpu_has_feature(CPU_FTR_HVMODE));
break;
#endif
case KVM_CAP_SYNC_MMU:
--
2.7.4
^ permalink raw reply related
* [PATCH v5 32/33] KVM: PPC: Book3S HV: Add a VM capability to enable nested virtualization
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
With this, userspace can enable a KVM-HV guest to run nested guests
under it.
The administrator can control whether any nested guests can be run;
setting the "nested" module parameter to false prevents any guests
becoming nested hypervisors (that is, any attempt to enable the nested
capability on a guest will fail). Guests which are already nested
hypervisors will continue to be so.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
Documentation/virtual/kvm/api.txt | 14 ++++++++++++++
arch/powerpc/include/asm/kvm_ppc.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 39 +++++++++++++++++++++++++++++---------
arch/powerpc/kvm/powerpc.c | 12 ++++++++++++
include/uapi/linux/kvm.h | 1 +
5 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index 2f5f9b7..fde48b6 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -4532,6 +4532,20 @@ With this capability, a guest may read the MSR_PLATFORM_INFO MSR. Otherwise,
a #GP would be raised when the guest tries to access. Currently, this
capability does not enable write permissions of this MSR for the guest.
+7.16 KVM_CAP_PPC_NESTED_HV
+
+Architectures: ppc
+Parameters: none
+Returns: 0 on success, -EINVAL when the implementation doesn't support
+ nested-HV virtualization.
+
+HV-KVM on POWER9 and later systems allows for "nested-HV"
+virtualization, which provides a way for a guest VM to run guests that
+can run using the CPU's supervisor mode (privileged non-hypervisor
+state). Enabling this capability on a VM depends on the CPU having
+the necessary functionality and on the facility being enabled with a
+kvm-hv module parameter.
+
8. Other capabilities.
----------------------
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index 245e564..b3796bd 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -327,6 +327,7 @@ struct kvmppc_ops {
int (*set_smt_mode)(struct kvm *kvm, unsigned long mode,
unsigned long flags);
void (*giveup_ext)(struct kvm_vcpu *vcpu, ulong msr);
+ int (*enable_nested)(struct kvm *kvm);
};
extern struct kvmppc_ops *kvmppc_hv_ops;
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 152bf75..fa61647 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -118,6 +118,16 @@ module_param_cb(h_ipi_redirect, &module_param_ops, &h_ipi_redirect, 0644);
MODULE_PARM_DESC(h_ipi_redirect, "Redirect H_IPI wakeup to a free host core");
#endif
+/* If set, guests are allowed to create and control nested guests */
+static bool nested = true;
+module_param(nested, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(nested, "Enable nested virtualization (only on POWER9)");
+
+static inline bool nesting_enabled(struct kvm *kvm)
+{
+ return kvm->arch.nested_enable && kvm_is_radix(kvm);
+}
+
/* If set, the threads on each CPU core have to be in the same MMU mode */
static bool no_mixing_hpt_and_radix;
@@ -959,12 +969,12 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
case H_SET_PARTITION_TABLE:
ret = H_FUNCTION;
- if (vcpu->kvm->arch.nested_enable)
+ if (nesting_enabled(vcpu->kvm))
ret = kvmhv_set_partition_table(vcpu);
break;
case H_ENTER_NESTED:
ret = H_FUNCTION;
- if (!vcpu->kvm->arch.nested_enable)
+ if (!nesting_enabled(vcpu->kvm))
break;
ret = kvmhv_enter_nested_guest(vcpu);
if (ret == H_INTERRUPT) {
@@ -974,9 +984,8 @@ int kvmppc_pseries_do_hcall(struct kvm_vcpu *vcpu)
break;
case H_TLB_INVALIDATE:
ret = H_FUNCTION;
- if (!vcpu->kvm->arch.nested_enable)
- break;
- ret = kvmhv_do_nested_tlbie(vcpu);
+ if (nesting_enabled(vcpu->kvm))
+ ret = kvmhv_do_nested_tlbie(vcpu);
break;
default:
@@ -4496,10 +4505,8 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
/* Must be called with kvm->lock held and mmu_ready = 0 and no vcpus running */
int kvmppc_switch_mmu_to_hpt(struct kvm *kvm)
{
- if (kvm->arch.nested_enable) {
- kvm->arch.nested_enable = false;
+ if (nesting_enabled(kvm))
kvmhv_release_all_nested(kvm);
- }
kvmppc_free_radix(kvm);
kvmppc_update_lpcr(kvm, LPCR_VPM1,
LPCR_VPM1 | LPCR_UPRT | LPCR_GTSE | LPCR_HR);
@@ -4776,7 +4783,7 @@ static void kvmppc_core_destroy_vm_hv(struct kvm *kvm)
/* Perform global invalidation and return lpid to the pool */
if (cpu_has_feature(CPU_FTR_ARCH_300)) {
- if (kvm->arch.nested_enable)
+ if (nesting_enabled(kvm))
kvmhv_release_all_nested(kvm);
kvm->arch.process_table = 0;
kvmhv_set_ptbl_entry(kvm->arch.lpid, 0, 0);
@@ -5169,6 +5176,19 @@ static int kvmhv_configure_mmu(struct kvm *kvm, struct kvm_ppc_mmuv3_cfg *cfg)
return err;
}
+static int kvmhv_enable_nested(struct kvm *kvm)
+{
+ if (!nested)
+ return -EPERM;
+ if (!cpu_has_feature(CPU_FTR_ARCH_300))
+ return -ENODEV;
+
+ /* kvm == NULL means the caller is testing if the capability exists */
+ if (kvm)
+ kvm->arch.nested_enable = true;
+ return 0;
+}
+
static struct kvmppc_ops kvm_ops_hv = {
.get_sregs = kvm_arch_vcpu_ioctl_get_sregs_hv,
.set_sregs = kvm_arch_vcpu_ioctl_set_sregs_hv,
@@ -5208,6 +5228,7 @@ static struct kvmppc_ops kvm_ops_hv = {
.configure_mmu = kvmhv_configure_mmu,
.get_rmmu_info = kvmhv_get_rmmu_info,
.set_smt_mode = kvmhv_set_smt_mode,
+ .enable_nested = kvmhv_enable_nested,
};
static int kvm_init_subcore_bitmap(void)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 1f4b128..2869a29 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -597,6 +597,10 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
r = !!(hv_enabled && cpu_has_feature(CPU_FTR_ARCH_300) &&
cpu_has_feature(CPU_FTR_HVMODE));
break;
+ case KVM_CAP_PPC_NESTED_HV:
+ r = !!(hv_enabled && kvmppc_hv_ops->enable_nested &&
+ !kvmppc_hv_ops->enable_nested(NULL));
+ break;
#endif
case KVM_CAP_SYNC_MMU:
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
@@ -2115,6 +2119,14 @@ static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
r = kvm->arch.kvm_ops->set_smt_mode(kvm, mode, flags);
break;
}
+
+ case KVM_CAP_PPC_NESTED_HV:
+ r = -EINVAL;
+ if (!is_kvmppc_hv_enabled(kvm) ||
+ !kvm->arch.kvm_ops->enable_nested)
+ break;
+ r = kvm->arch.kvm_ops->enable_nested(kvm);
+ break;
#endif
default:
r = -EINVAL;
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index 251be35..d9cec6b 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -953,6 +953,7 @@ struct kvm_ppc_resize_hpt {
#define KVM_CAP_NESTED_STATE 157
#define KVM_CAP_ARM_INJECT_SERROR_ESR 158
#define KVM_CAP_MSR_PLATFORM_INFO 159
+#define KVM_CAP_PPC_NESTED_HV 160
#ifdef KVM_CAP_IRQ_ROUTING
--
2.7.4
^ permalink raw reply related
* [PATCH v5 33/33] KVM: PPC: Book3S HV: Add NO_HASH flag to GET_SMMU_INFO ioctl result
From: Paul Mackerras @ 2018-10-08 5:31 UTC (permalink / raw)
To: kvm, kvm-ppc; +Cc: linuxppc-dev, David Gibson
In-Reply-To: <1538976679-1363-1-git-send-email-paulus@ozlabs.org>
This adds a KVM_PPC_NO_HASH flag to the flags field of the
kvm_ppc_smmu_info struct, and arranges for it to be set when
running as a nested hypervisor, as an unambiguous indication
to userspace that HPT guests are not supported. Reporting the
KVM_CAP_PPC_MMU_HASH_V3 capability as false could be taken as
indicating only that the new HPT features in ISA V3.0 are not
supported, leaving it ambiguous whether pre-V3.0 HPT features
are supported.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
---
Documentation/virtual/kvm/api.txt | 4 ++++
arch/powerpc/kvm/book3s_hv.c | 4 ++++
include/uapi/linux/kvm.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index fde48b6..df98b63 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -2270,6 +2270,10 @@ The supported flags are:
The emulated MMU supports 1T segments in addition to the
standard 256M ones.
+ - KVM_PPC_NO_HASH
+ This flag indicates that HPT guests are not supported by KVM,
+ thus all guests must use radix MMU mode.
+
The "slb_size" field indicates how many SLB entries are supported
The "sps" array contains 8 entries indicating the supported base
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index fa61647..f565403 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -4245,6 +4245,10 @@ static int kvm_vm_ioctl_get_smmu_info_hv(struct kvm *kvm,
kvmppc_add_seg_page_size(&sps, 16, SLB_VSID_L | SLB_VSID_LP_01);
kvmppc_add_seg_page_size(&sps, 24, SLB_VSID_L);
+ /* If running as a nested hypervisor, we don't support HPT guests */
+ if (kvmhv_on_pseries())
+ info->flags |= KVM_PPC_NO_HASH;
+
return 0;
}
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index d9cec6b..7f2ff3a 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -719,6 +719,7 @@ struct kvm_ppc_one_seg_page_size {
#define KVM_PPC_PAGE_SIZES_REAL 0x00000001
#define KVM_PPC_1T_SEGMENTS 0x00000002
+#define KVM_PPC_NO_HASH 0x00000004
struct kvm_ppc_smmu_info {
__u64 flags;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support
From: Shawn Guo @ 2018-10-08 5:45 UTC (permalink / raw)
To: Vabhav Sharma
Cc: mark.rutland, kstewart, Yogesh Gaur, linux-kernel-owner,
catalin.marinas, mturquette, will.deacon, yamada.masahiro,
Sriram Dash, linux-clk, pankaj.bansal, udit.kumar, linux,
Priyanka Jain, viresh.kumar, devicetree, arnd, linux-pm, oss,
robh+dt, V.Sethi, Nipun Gupta, linux-arm-kernel, Ramneek Mehresh,
sboyd, gregkh, Zhang Ying-22455, rjw, linux-kernel, leoyang.li,
sudeep.holla, linuxppc-dev
In-Reply-To: <1538615031-7507-6-git-send-email-vabhav.sharma@nxp.com>
On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:
> LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
>
> LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
> in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
> controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
> UARTs etc.
>
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 702 +++++++++++++++++++++++++
> 1 file changed, 702 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> new file mode 100644
> index 0000000..c758268
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -0,0 +1,702 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree Include file for Layerscape-LX2160A family SoC.
> +//
> +// Copyright 2018 NXP
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x80000000 0x00010000;
> +
> +/ {
> + compatible = "fsl,lx2160a";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + // 8 clusters having 2 Cortex-A72 cores each
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster0_l2>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x1>;
> + clocks = <&clockgen 1 0>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster0_l2>;
> + };
> +
> + cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x100>;
> + clocks = <&clockgen 1 1>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster1_l2>;
> + };
> +
> + cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x101>;
> + clocks = <&clockgen 1 1>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster1_l2>;
> + };
> +
> + cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x200>;
> + clocks = <&clockgen 1 2>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster2_l2>;
> + };
> +
> + cpu@201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x201>;
> + clocks = <&clockgen 1 2>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster2_l2>;
> + };
> +
> + cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x300>;
> + clocks = <&clockgen 1 3>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster3_l2>;
> + };
> +
> + cpu@301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x301>;
> + clocks = <&clockgen 1 3>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster3_l2>;
> + };
> +
> + cpu@400 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x400>;
> + clocks = <&clockgen 1 4>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster4_l2>;
> + };
> +
> + cpu@401 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x401>;
> + clocks = <&clockgen 1 4>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster4_l2>;
> + };
> +
> + cpu@500 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x500>;
> + clocks = <&clockgen 1 5>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster5_l2>;
> + };
> +
> + cpu@501 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x501>;
> + clocks = <&clockgen 1 5>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster5_l2>;
> + };
> +
> + cpu@600 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x600>;
> + clocks = <&clockgen 1 6>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster6_l2>;
> + };
> +
> + cpu@601 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x601>;
> + clocks = <&clockgen 1 6>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster6_l2>;
> + };
> +
> + cpu@700 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x700>;
> + clocks = <&clockgen 1 7>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster7_l2>;
> + };
> +
> + cpu@701 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + enable-method = "psci";
> + reg = <0x701>;
> + clocks = <&clockgen 1 7>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + i-cache-size = <0xC000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <192>;
> + next-level-cache = <&cluster7_l2>;
> + };
> +
> + cluster0_l2: l2-cache0 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster1_l2: l2-cache1 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster2_l2: l2-cache2 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster3_l2: l2-cache3 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster4_l2: l2-cache4 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster5_l2: l2-cache5 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster6_l2: l2-cache6 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> +
> + cluster7_l2: l2-cache7 {
> + compatible = "cache";
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <1024>;
> + cache-level = <2>;
> + };
> + };
> +
> + gic: interrupt-controller@6000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
> + <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
> + // SGI_base)
> + <0x0 0x0c0c0000 0 0x2000>, // GICC
> + <0x0 0x0c0d0000 0 0x1000>, // GICH
> + <0x0 0x0c0e0000 0 0x20000>; // GICV
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + its: gic-its@6020000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + reg = <0x0 0x6020000 0 0x20000>;
> + };
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a72-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + memory@80000000 {
> + // DRAM space - 1, size : 2 GB DRAM
> + device_type = "memory";
> + reg = <0x00000000 0x80000000 0 0x80000000>;
> + };
> +
> + ddr1: memory-controller@1080000 {
> + compatible = "fsl,qoriq-memory-controller";
> + reg = <0x0 0x1080000 0x0 0x1000>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> + };
> +
> + ddr2: memory-controller@1090000 {
> + compatible = "fsl,qoriq-memory-controller";
> + reg = <0x0 0x1090000 0x0 0x1000>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> + little-endian;
> + };
> +
> + sysclk: sysclk {
Name the node a bit generic like clock-xxx.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking@1300000 {
clock-controller for node name.
> + compatible = "fsl,lx2160a-clockgen";
> + reg = <0 0x1300000 0 0xa0000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + };
> +
> + crypto: crypto@8000000 {
> + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> + fsl,sec-era = <10>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x00 0x8000000 0x100000>;
> + reg = <0x00 0x8000000 0x0 0x100000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + dma-coherent;
> + status = "disabled";
> +
> + sec_jr0: jr@10000 {
> + compatible = "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x10000 0x10000>;
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr1: jr@20000 {
> + compatible = "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x20000 0x10000>;
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr2: jr@30000 {
> + compatible = "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x30000 0x10000>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + sec_jr3: jr@40000 {
> + compatible = "fsl,sec-v5.0-job-ring",
> + "fsl,sec-v4.0-job-ring";
> + reg = <0x40000 0x10000>;
> + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + dcfg: dcfg@1e00000 {
As per suggestion from devicetree specification, we can "syscon" as
a more generic node name?
> + compatible = "fsl,lx2160a-dcfg", "syscon";
> + reg = <0x0 0x1e00000 0x0 0x10000>;
> + little-endian;
> + };
> +
> + gpio0: gpio@2300000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + little-endian;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio@2310000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2310000 0x0 0x10000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + little-endian;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio@2320000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2320000 0x0 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + little-endian;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio@2330000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2330000 0x0 0x10000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + little-endian;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + i2c0: i2c@2000000 {
Sort the nodes under bus in order of unit-address.
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2000000 0x0 0x10000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + fsl-scl-gpio = <&gpio2 15 0>;
I cannot find this property in fsl,vf610-i2c bindings.
> + status = "disabled";
> + };
> +
> + i2c1: i2c@2010000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2010000 0x0 0x10000>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@2020000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2020000 0x0 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@2030000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2030000 0x0 0x10000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@2040000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2040000 0x0 0x10000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + fsl-scl-gpio = <&gpio2 16 0>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@2050000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2050000 0x0 0x10000>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + i2c6: i2c@2060000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2060000 0x0 0x10000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + i2c7: i2c@2070000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2070000 0x0 0x10000>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "i2c";
> + clocks = <&clockgen 4 7>;
> + status = "disabled";
> + };
> +
> + uart0: serial@21c0000 {
> + device_type = "serial";
Quote from devicetree specification:
The device_type property was used in IEEE 1275 to describe the device’s
FCode programming model. Because DTSpec does not have FCode, new use of
the property is deprecated, and it should be included only on cpu and
memory nodes for compatibility with IEEE 1275–derived devicetrees.
> + compatible = "arm,sbsa-uart","arm,pl011";
> + reg = <0x0 0x21c0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + current-speed = <115200>;
> + status = "disabled";
> + };
> +
> + uart1: serial@21d0000 {
> + device_type = "serial";
> + compatible = "arm,sbsa-uart","arm,pl011";
> + reg = <0x0 0x21d0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + current-speed = <115200>;
> + status = "disabled";
> + };
> +
> + uart2: serial@21e0000 {
> + device_type = "serial";
> + compatible = "arm,sbsa-uart","arm,pl011";
> + reg = <0x0 0x21e0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> + current-speed = <115200>;
> + status = "disabled";
> + };
> +
> + uart3: serial@21f0000 {
> + device_type = "serial";
> + compatible = "arm,sbsa-uart","arm,pl011";
> + reg = <0x0 0x21f0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + current-speed = <115200>;
> + status = "disabled";
> + };
> +
> + smmu: iommu@5000000 {
> + compatible = "arm,mmu-500";
> + reg = <0 0x5000000 0 0x800000>;
> + #iommu-cells = <1>;
> + #global-interrupts = <14>;
> + interrupts = <0 13 4>, // global secure fault
Can we use defines for interrupt cells just like other device nodes?
> + <0 14 4>, // combined secure interrupt
> + <0 15 4>, // global non-secure fault
> + <0 16 4>, // combined non-secure interrupt
> + // performance counter interrupts 0-9
> + <0 211 4>, <0 212 4>,
> + <0 213 4>, <0 214 4>,
> + <0 215 4>, <0 216 4>,
> + <0 217 4>, <0 218 4>,
> + <0 219 4>, <0 220 4>,
> + // per context interrupt, 64 interrupts
> + <0 146 4>, <0 147 4>,
> + <0 148 4>, <0 149 4>,
> + <0 150 4>, <0 151 4>,
> + <0 152 4>, <0 153 4>,
> + <0 154 4>, <0 155 4>,
> + <0 156 4>, <0 157 4>,
> + <0 158 4>, <0 159 4>,
> + <0 160 4>, <0 161 4>,
> + <0 162 4>, <0 163 4>,
> + <0 164 4>, <0 165 4>,
> + <0 166 4>, <0 167 4>,
> + <0 168 4>, <0 169 4>,
> + <0 170 4>, <0 171 4>,
> + <0 172 4>, <0 173 4>,
> + <0 174 4>, <0 175 4>,
> + <0 176 4>, <0 177 4>,
> + <0 178 4>, <0 179 4>,
> + <0 180 4>, <0 181 4>,
> + <0 182 4>, <0 183 4>,
> + <0 184 4>, <0 185 4>,
> + <0 186 4>, <0 187 4>,
> + <0 188 4>, <0 189 4>,
> + <0 190 4>, <0 191 4>,
> + <0 192 4>, <0 193 4>,
> + <0 194 4>, <0 195 4>,
> + <0 196 4>, <0 197 4>,
> + <0 198 4>, <0 199 4>,
> + <0 200 4>, <0 201 4>,
> + <0 202 4>, <0 203 4>,
> + <0 204 4>, <0 205 4>,
> + <0 206 4>, <0 207 4>,
> + <0 208 4>, <0 209 4>;
> + dma-coherent;
> + };
> +
> + usb0: usb3@3100000 {
usb for node name.
Shawn
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> + usb1: usb3@3110000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3110000 0x0 0x10000>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> + watchdog@23a0000 {
> + compatible = "arm,sbsa-gwdt";
> + reg = <0x0 0x23a0000 0 0x1000>,
> + <0x0 0x2390000 0 0x1000>;
> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + timeout-sec = <30>;
> + };
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support
From: Shawn Guo @ 2018-10-08 5:52 UTC (permalink / raw)
To: Vabhav Sharma
Cc: mark.rutland, kstewart, linux-kernel-owner, catalin.marinas,
mturquette, will.deacon, yamada.masahiro, Sriram Dash, linux-clk,
pankaj.bansal, udit.kumar, linux, Priyanka Jain, viresh.kumar,
devicetree, arnd, linux-pm, oss, robh+dt, V.Sethi,
linux-arm-kernel, sboyd, gregkh, rjw, linux-kernel, leoyang.li,
sudeep.holla, linuxppc-dev
In-Reply-To: <1538615031-7507-7-git-send-email-vabhav.sharma@nxp.com>
On Thu, Oct 04, 2018 at 06:33:51AM +0530, Vabhav Sharma wrote:
> LX2160A reference design board (RDB) is a high-performance
> computing, evaluation, and development platform with LX2160A
> SoC.
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 100 ++++++++++++++++++++++
> 2 files changed, 101 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 86e18ad..445b72b 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> new file mode 100644
> index 0000000..1483071
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -0,0 +1,100 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree file for LX2160ARDB
> +//
> +// Copyright 2018 NXP
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +/ {
> + model = "NXP Layerscape LX2160ARDB";
> + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + sb_3v3: regulator-fixed {
The node name should probably be named like regulator-sb3v3 or
something, so that the pattern can be followed when we have another
fixed regulator to be added.
> + compatible = "regulator-fixed";
> + regulator-name = "fixed-3.3V";
The name should be something we can find on board schematics.
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&i2c0 {
Please keep these labeled nodes sorted alphabetically.
> + status = "okay";
Have a newline between properties and child node.
> + i2c-mux@77 {
> + compatible = "nxp,pca9547";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x2>;
> +
> + power-monitor@40 {
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> + };
> +
> + i2c@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x3>;
> +
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <&sb_3v3>;
> + };
> +
> + temperature-sensor@4d {
> + compatible = "nxp,sa56004";
> + reg = <0x4d>;
> + vcc-supply = <&sb_3v3>;
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + status = "okay";
> +
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + // IRQ10_B
> + interrupts = <0 150 0x4>;
> + };
Bad indentation.
Shawn
> +
> +};
> +
> +&usb0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&crypto {
> + status = "okay";
> +};
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 04/36] dt-bindings: arm: fsl: Move DCFG and SCFG bindings to their own docs
From: Shawn Guo @ 2018-10-08 6:25 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Kumar Gala, Grant Likely, Arnd Bergmann,
Tom Rini, Frank Rowand, Linus Walleij, Pantelis Antoniou,
linux-kernel, Bjorn Andersson, Mark Brown, Geert Uytterhoeven,
Jonathan Cameron, Olof Johansson, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20181005165848.3474-5-robh@kernel.org>
On Fri, Oct 05, 2018 at 11:58:16AM -0500, Rob Herring wrote:
> In preparation to convert board-level bindings to json-schema, move
> various misc SoC bindings out to their own file.
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply
* Re: [PATCH 06/36] dt-bindings: arm: zte: Move sysctrl bindings to their own doc
From: Shawn Guo @ 2018-10-08 6:30 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Kumar Gala, Grant Likely, Arnd Bergmann,
Tom Rini, Frank Rowand, Linus Walleij, Pantelis Antoniou,
linux-kernel, Bjorn Andersson, Mark Brown, Geert Uytterhoeven,
Jonathan Cameron, Olof Johansson, Jun Nie, Baoyou Xie,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <20181005165848.3474-7-robh@kernel.org>
On Fri, Oct 05, 2018 at 11:58:18AM -0500, Rob Herring wrote:
> In preparation to convert board-level bindings to json-schema, move
> various misc SoC bindings out to their own file.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Jun Nie <jun.nie@linaro.org>
> Cc: Baoyou Xie <baoyou.xie@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/arm/zte-sysctrl.txt | 30 +++++++++++++++++++
zte,sysctrl.txt to be consistent with other files like
fsl,layerscape-dcfg.txt? I'm fine with either way, but just want to
see more consistent naming convention? Other than that,
Acked-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply
* Re: [PATCH 22/36] dt-bindings: arm: Convert FSL board/soc bindings to json-schema
From: Shawn Guo @ 2018-10-08 7:01 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Kumar Gala, Grant Likely, Arnd Bergmann,
Tom Rini, Frank Rowand, Linus Walleij, Pantelis Antoniou,
linux-kernel, Bjorn Andersson, Mark Brown, Geert Uytterhoeven,
Jonathan Cameron, Olof Johansson, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20181005165848.3474-23-robh@kernel.org>
On Fri, Oct 05, 2018 at 11:58:34AM -0500, Rob Herring wrote:
> Convert Freescale SoC bindings to DT schema format using json-schema.
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/arm/armadeus.txt | 6 -
> Documentation/devicetree/bindings/arm/bhf.txt | 6 -
> .../bindings/arm/compulab-boards.txt | 25 ---
> Documentation/devicetree/bindings/arm/fsl.txt | 185 ------------------
> .../devicetree/bindings/arm/fsl.yaml | 166 ++++++++++++++++
> .../devicetree/bindings/arm/i2se.txt | 22 ---
> .../devicetree/bindings/arm/olimex.txt | 10 -
> .../devicetree/bindings/arm/technologic.txt | 23 ---
> 8 files changed, 166 insertions(+), 277 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/armadeus.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/bhf.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/compulab-boards.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/fsl.txt
> create mode 100644 Documentation/devicetree/bindings/arm/fsl.yaml
> delete mode 100644 Documentation/devicetree/bindings/arm/i2se.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/olimex.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/technologic.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/armadeus.txt b/Documentation/devicetree/bindings/arm/armadeus.txt
> deleted file mode 100644
> index 9821283ff516..000000000000
> --- a/Documentation/devicetree/bindings/arm/armadeus.txt
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -Armadeus i.MX Platforms Device Tree Bindings
> ------------------------------------------------
> -
> -APF51: i.MX51 based module.
> -Required root node properties:
> - - compatible = "armadeus,imx51-apf51", "fsl,imx51";
> diff --git a/Documentation/devicetree/bindings/arm/bhf.txt b/Documentation/devicetree/bindings/arm/bhf.txt
> deleted file mode 100644
> index 886b503caf9c..000000000000
> --- a/Documentation/devicetree/bindings/arm/bhf.txt
> +++ /dev/null
> @@ -1,6 +0,0 @@
> -Beckhoff Automation Platforms Device Tree Bindings
> ---------------------------------------------------
> -
> -CX9020 Embedded PC
> -Required root node properties:
> - - compatible = "bhf,cx9020", "fsl,imx53";
> diff --git a/Documentation/devicetree/bindings/arm/compulab-boards.txt b/Documentation/devicetree/bindings/arm/compulab-boards.txt
> deleted file mode 100644
> index 42a10285af9c..000000000000
> --- a/Documentation/devicetree/bindings/arm/compulab-boards.txt
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -CompuLab SB-SOM is a multi-module baseboard capable of carrying:
> - - CM-T43
> - - CM-T54
> - - CM-QS600
> - - CL-SOM-AM57x
> - - CL-SOM-iMX7
> -modules with minor modifications to the SB-SOM assembly.
> -
> -Required root node properties:
> - - compatible = should be "compulab,sb-som"
> -
> -Compulab CL-SOM-iMX7 is a miniature System-on-Module (SoM) based on
> -Freescale i.MX7 ARM Cortex-A7 System-on-Chip.
> -
> -Required root node properties:
> - - compatible = "compulab,cl-som-imx7", "fsl,imx7d";
> -
> -Compulab SBC-iMX7 is a single board computer based on the
> -Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
> -the CL-SOM-iMX7 System-on-Module providing most of the functions,
> -and SB-SOM-iMX7 carrier board providing additional peripheral
> -functions and connectors.
> -
> -Required root node properties:
> - - compatible = "compulab,sbc-imx7", "compulab,cl-som-imx7", "fsl,imx7d";
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
> deleted file mode 100644
> index 1e775aaa5c5b..000000000000
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ /dev/null
> @@ -1,185 +0,0 @@
> -Freescale i.MX Platforms Device Tree Bindings
> ------------------------------------------------
> -
> -i.MX23 Evaluation Kit
> -Required root node properties:
> - - compatible = "fsl,imx23-evk", "fsl,imx23";
> -
> -i.MX25 Product Development Kit
> -Required root node properties:
> - - compatible = "fsl,imx25-pdk", "fsl,imx25";
> -
> -i.MX27 Product Development Kit
> -Required root node properties:
> - - compatible = "fsl,imx27-pdk", "fsl,imx27";
> -
> -i.MX28 Evaluation Kit
> -Required root node properties:
> - - compatible = "fsl,imx28-evk", "fsl,imx28";
> -
> -i.MX51 Babbage Board
> -Required root node properties:
> - - compatible = "fsl,imx51-babbage", "fsl,imx51";
> -
> -i.MX53 Automotive Reference Design Board
> -Required root node properties:
> - - compatible = "fsl,imx53-ard", "fsl,imx53";
> -
> -i.MX53 Evaluation Kit
> -Required root node properties:
> - - compatible = "fsl,imx53-evk", "fsl,imx53";
> -
> -i.MX53 Quick Start Board
> -Required root node properties:
> - - compatible = "fsl,imx53-qsb", "fsl,imx53";
> -
> -i.MX53 Smart Mobile Reference Design Board
> -Required root node properties:
> - - compatible = "fsl,imx53-smd", "fsl,imx53";
> -
> -i.MX6 Quad Armadillo2 Board
> -Required root node properties:
> - - compatible = "fsl,imx6q-arm2", "fsl,imx6q";
> -
> -i.MX6 Quad SABRE Lite Board
> -Required root node properties:
> - - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
> -
> -i.MX6 Quad SABRE Smart Device Board
> -Required root node properties:
> - - compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
> -
> -i.MX6 Quad SABRE Automotive Board
> -Required root node properties:
> - - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
> -
> -i.MX6SLL EVK board
> -Required root node properties:
> - - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
> -
> -Generic i.MX boards
> --------------------
> -
> -No iomux setup is done for these boards, so this must have been configured
> -by the bootloader for boards to work with the generic bindings.
> -
> -i.MX27 generic board
> -Required root node properties:
> - - compatible = "fsl,imx27";
> -
> -i.MX51 generic board
> -Required root node properties:
> - - compatible = "fsl,imx51";
> -
> -i.MX53 generic board
> -Required root node properties:
> - - compatible = "fsl,imx53";
> -
> -i.MX6q generic board
> -Required root node properties:
> - - compatible = "fsl,imx6q";
> -
> -Freescale Vybrid Platform Device Tree Bindings
> -----------------------------------------------
> -
> -For the Vybrid SoC familiy all variants with DDR controller are supported,
> -which is the VF5xx and VF6xx series. Out of historical reasons, in most
> -places the kernel uses vf610 to refer to the whole familiy.
> -The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
> -core support.
> -
> -Required root node compatible property (one of them):
> - - compatible = "fsl,vf500";
> - - compatible = "fsl,vf510";
> - - compatible = "fsl,vf600";
> - - compatible = "fsl,vf610";
> - - compatible = "fsl,vf610m4";
> -
> -Freescale LS1021A Platform Device Tree Bindings
> -------------------------------------------------
> -
> -Required root node compatible properties:
> - - compatible = "fsl,ls1021a";
> -
> -Freescale ARMv8 based Layerscape SoC family Device Tree Bindings
> -----------------------------------------------------------------
> -
> -LS1012A SoC
> -Required root node properties:
> - - compatible = "fsl,ls1012a";
> -
> -LS1012A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
> -
> -LS1012A ARMv8 based FRDM Board
> -Required root node properties:
> - - compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
> -
> -LS1012A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
> -
> -LS1043A SoC
> -Required root node properties:
> - - compatible = "fsl,ls1043a";
> -
> -LS1043A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
> -
> -LS1043A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
> -
> -LS1046A SoC
> -Required root node properties:
> - - compatible = "fsl,ls1046a";
> -
> -LS1046A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
> -
> -LS1046A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
> -
> -LS1088A SoC
> -Required root node properties:
> - - compatible = "fsl,ls1088a";
> -
> -LS1088A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
> -
> -LS1088A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
> -
> -LS2080A SoC
> -Required root node properties:
> - - compatible = "fsl,ls2080a";
> -
> -LS2080A ARMv8 based Simulator model
> -Required root node properties:
> - - compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
> -
> -LS2080A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
> -
> -LS2080A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
> -
> -LS2088A SoC
> -Required root node properties:
> - - compatible = "fsl,ls2088a";
> -
> -LS2088A ARMv8 based QDS Board
> -Required root node properties:
> - - compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
> -
> -LS2088A ARMv8 based RDB Board
> -Required root node properties:
> - - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> new file mode 100644
> index 000000000000..5241fa92e3d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -0,0 +1,166 @@
> +# SPDX-License-Identifier: None
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/arm/fsl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX Platforms Device Tree Bindings
> +
> +maintainers:
> + - Shawn Guo <shawn.guo@freescale.com>
The email address has been unavailable for long time. Please use
Shawn Guo <shawnguo@kernel.org>.
> + - Shaohui Xie <Shaohui.Xie@nxp.com>
Li Yang <leoyang.li@nxp.com> is the co-maintainer for Layerscape.
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: i.MX23 based Boards
> + items:
> + - enum:
> + - fsl,imx23-evk
> + - olimex,imx23-olinuxino
> + - const: fsl,imx23
> +
> + - description: i.MX25 Product Development Kit
> + items:
> + - enum:
> + - fsl,imx25-pdk
> + - const: fsl,imx25
> +
> + - description: i.MX27 Product Development Kit
> + items:
> + - enum:
> + - fsl,imx27-pdk
> + - const: fsl,imx27
> +
> + - description: i.MX28 based Boards
> + items:
> + - enum:
> + - fsl,imx28-evk
> + - i2se,duckbill
> + - i2se,duckbill-2
> + - technologic,imx28-ts4600
> + - const: fsl,imx28
> + - items:
The schema is new to me. This line looks unusual to me, so you may want
to double check.
> + - enum:
> + - i2se,duckbill-2-485
> + - i2se,duckbill-2-enocean
> + - i2se,duckbill-2-spi
> + - const: i2se,duckbill-2
> + - const: fsl,imx28
> +
> + - description: i.MX51 Babbage Board
i.MX51 based Boards
> + items:
> + - enum:
> + - armadeus,imx51-apf51
> + - fsl,imx51-babbage
> + - technologic,imx51-ts4800
> + - const: fsl,imx51
> +
> + - description: i.MX53 Boards
i.MX53 based Boards
Shawn
> + items:
> + - enum:
> + - bhf,cx9020
> + - fsl,imx53-ard
> + - fsl,imx53-evk
> + - fsl,imx53-qsb
> + - fsl,imx53-smd
> + - const: fsl,imx53
> +
> + - description: i.MX6Q based Boards
> + items:
> + - enum:
> + - fsl,imx6q-arm2
> + - fsl,imx6q-sabrelite
> + - fsl,imx6q-sabresd
> + - fsl,imx6q-sabreauto
> + - technologic,imx6q-ts4900
> + - technologic,imx6q-ts7970
> + - const: fsl,imx6q
> +
> + - description: i.MX6DL based Boards
> + items:
> + - enum:
> + - technologic,imx6dl-ts4900
> + - technologic,imx6dl-ts7970
> + - const: fsl,imx6dl
> +
> + - description: i.MX6SLL based Boards
> + items:
> + - enum:
> + - fsl,imx6sll-evk
> + - const: fsl,imx6sll
> +
> + - description:
> + Compulab SBC-iMX7 is a single board computer based on the
> + Freescale i.MX7 system-on-chip. SBC-iMX7 is implemented with
> + the CL-SOM-iMX7 System-on-Module providing most of the functions,
> + and SB-SOM-iMX7 carrier board providing additional peripheral
> + functions and connectors.
> + items:
> + - const: compulab,sbc-imx7
> + - const: compulab,cl-som-imx7
> + - const: fsl,imx7d
> +
> + - description:
> + Freescale Vybrid Platform Device Tree Bindings
> +
> + For the Vybrid SoC familiy all variants with DDR controller are supported,
> + which is the VF5xx and VF6xx series. Out of historical reasons, in most
> + places the kernel uses vf610 to refer to the whole familiy.
> + The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
> + core support.
> + items:
> + - enum:
> + - fsl,vf500
> + - fsl,vf510
> + - fsl,vf600
> + - fsl,vf610
> + - fsl,vf610m4
> +
> + - description: LS1021A based Boards
> + items:
> + - enum:
> + - fsl,ls1012a-rdb
> + - fsl,ls1012a-frdm
> + - fsl,ls1012a-qds
> + - const: fsl,ls1021a
> +
> + - description: LS1043A based Boards
> + items:
> + - enum:
> + - fsl,ls1043a-rdb
> + - fsl,ls1043a-qds
> + - const: fsl,ls1043a
> +
> + - description: LS1046A based Boards
> + items:
> + - enum:
> + - fsl,ls1046a-qds
> + - fsl,ls1046a-rdb
> + - const: fsl,ls1046a
> +
> + - description: LS1088A based Boards
> + items:
> + - enum:
> + - fsl,ls1088a-qds
> + - fsl,ls1088a-rdb
> + - const: fsl,ls1088a
> +
> + - description: LS2080A based Boards
> + items:
> + - enum:
> + - fsl,ls2080a-simu
> + - fsl,ls2080a-qds
> + - fsl,ls2080a-rdb
> + - const: fsl,ls2080a
> +
> + - description: LS2088A based Boards
> + items:
> + - enum:
> + - fsl,ls2088a-qds
> + - fsl,ls2088a-rdb
> + - const: fsl,ls2088a
> +
> +...
> diff --git a/Documentation/devicetree/bindings/arm/i2se.txt b/Documentation/devicetree/bindings/arm/i2se.txt
> deleted file mode 100644
> index dbd54a3aa07d..000000000000
> --- a/Documentation/devicetree/bindings/arm/i2se.txt
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -I2SE Device Tree Bindings
> --------------------------
> -
> -Duckbill Board
> -Required root node properties:
> - - compatible = "i2se,duckbill", "fsl,imx28";
> -
> -Duckbill 2 Board
> -Required root node properties:
> - - compatible = "i2se,duckbill-2", "fsl,imx28";
> -
> -Duckbill 2 485 Board
> -Required root node properties:
> - - compatible = "i2se,duckbill-2-485", "i2se,duckbill-2", "fsl,imx28";
> -
> -Duckbill 2 EnOcean Board
> -Required root node properties:
> - - compatible = "i2se,duckbill-2-enocean", "i2se,duckbill-2", "fsl,imx28";
> -
> -Duckbill 2 SPI Board
> -Required root node properties:
> - - compatible = "i2se,duckbill-2-spi", "i2se,duckbill-2", "fsl,imx28";
> diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt
> deleted file mode 100644
> index d726aeca56be..000000000000
> --- a/Documentation/devicetree/bindings/arm/olimex.txt
> +++ /dev/null
> @@ -1,10 +0,0 @@
> -Olimex Device Tree Bindings
> ----------------------------
> -
> -SAM9-L9260 Board
> -Required root node properties:
> - - compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
> -
> -i.MX23 Olinuxino Low Cost Board
> -Required root node properties:
> - - compatible = "olimex,imx23-olinuxino", "fsl,imx23";
> diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt
> deleted file mode 100644
> index f1cedc00dcab..000000000000
> --- a/Documentation/devicetree/bindings/arm/technologic.txt
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -Technologic Systems Platforms Device Tree Bindings
> ---------------------------------------------------
> -
> -TS-4600 is a System-on-Module based on the Freescale i.MX28 System-on-Chip.
> -It can be mounted on a carrier board providing additional peripheral connectors.
> -Required root node properties:
> - - compatible = "technologic,imx28-ts4600", "fsl,imx28"
> -
> -TS-4800 board
> -Required root node properties:
> - - compatible = "technologic,imx51-ts4800", "fsl,imx51";
> -
> -TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
> -It can be mounted on a carrier board providing additional peripheral connectors.
> -Required root node properties:
> - - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
> - - compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
> -
> -TS-7970 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
> -It can be mounted on a carrier board providing additional peripheral connectors.
> -Required root node properties:
> - - compatible = "technologic,imx6dl-ts7970", "fsl,imx6dl"
> - - compatible = "technologic,imx6q-ts7970", "fsl,imx6q"
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH] powerpc: Fix HMIs on big-endian with CONFIG_RELOCATABLE=y
From: Nicholas Piggin @ 2018-10-08 7:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <e4bfa53ea8c777105359e1770df906909dde2c57.camel@kernel.crashing.org>
On Mon, 08 Oct 2018 15:08:31 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> HMIs will crash the kernel due to
>
> BRANCH_LINK_TO_FAR(hmi_exception_realmode)
>
> Calling into the OPD instead of the actual code.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>
> This hack fixes it for me, but it's not great. Nick, any better idea ?
Is it a hack because the ifdef gunk, or because there's something
deeper wrong with using the .sym?
I guess all those handlers that load label address by hand could have
the bug silently creep in. Can we have them use the DOTSYM() macro?
Thanks,
Nick
>
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index ea04dfb..752709cc8 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -1119,7 +1119,11 @@ TRAMP_REAL_BEGIN(hmi_exception_early)
> EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
> EXCEPTION_PROLOG_COMMON_3(0xe60)
> addi r3,r1,STACK_FRAME_OVERHEAD
> +#ifdef PPC64_ELF_ABI_v1
> + BRANCH_LINK_TO_FAR(.hmi_exception_realmode) /* Function call ABI */
> +#else
> BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */
> +#endif
> cmpdi cr0,r3,0
>
> /* Windup the stack. */
>
>
^ permalink raw reply
* Re: [PATCH 05/36] dt-bindings: arm: renesas: Move 'renesas,prr' binding to its own doc
From: Geert Uytterhoeven @ 2018-10-08 7:05 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Kumar Gala, Grant Likely, Arnd Bergmann, Tom Rini, Simon Horman,
Frank Rowand, Linus Walleij, Pantelis Antoniou,
Linux Kernel Mailing List, Björn Andersson, Linux-Renesas,
Mark Brown, Jonathan Cameron, Olof Johansson, linuxppc-dev,
Linux ARM
In-Reply-To: <20181005165848.3474-6-robh@kernel.org>
Hi Rob,
On Fri, Oct 5, 2018 at 6:58 PM Rob Herring <robh@kernel.org> wrote:
> In preparation to convert board-level bindings to json-schema, move
> various misc SoC bindings out to their own file.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-renesas-soc@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
Looks good to me, but needs a rebase, as the PRR section has been extended
in -next.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 36/36] dt-bindings: arm: Convert ZTE board/soc bindings to json-schema
From: Shawn Guo @ 2018-10-08 7:16 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, Kumar Gala, Grant Likely, Arnd Bergmann,
Tom Rini, Frank Rowand, Linus Walleij, Pantelis Antoniou,
linux-kernel, Bjorn Andersson, Mark Brown, Geert Uytterhoeven,
Jonathan Cameron, Olof Johansson, Jun Nie, Baoyou Xie,
linuxppc-dev, linux-arm-kernel
In-Reply-To: <20181005165848.3474-37-robh@kernel.org>
On Fri, Oct 05, 2018 at 11:58:48AM -0500, Rob Herring wrote:
> Convert ZTE SoC bindings to DT schema format using json-schema.
>
> Cc: Jun Nie <jun.nie@linaro.org>
> Cc: Baoyou Xie <baoyou.xie@linaro.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
^ permalink raw reply
* Re: [RFC PATCH kernel] vfio/spapr_tce: Get rid of possible infinite loop
From: Serhii Popovych @ 2018-10-08 7:29 UTC (permalink / raw)
To: Alexey Kardashevskiy, linuxppc-dev; +Cc: Alex Williamson, kvm-ppc, David Gibson
In-Reply-To: <20181002032231.7494-1-aik@ozlabs.ru>
[-- Attachment #1.1: Type: text/plain, Size: 2107 bytes --]
Alexey Kardashevskiy wrote:
> As a part of cleanup, the SPAPR TCE IOMMU subdriver releases preregistered
> memory. If there is a bug in memory release, the loop in
> tce_iommu_release() becomes infinite; this actually happened to me.
>
> This makes the loop finite and prints a warning on every failure to make
> the code more bug prone.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> drivers/vfio/vfio_iommu_spapr_tce.c | 10 +++-------
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c
> index b1a8ab3..ece0651 100644
> --- a/drivers/vfio/vfio_iommu_spapr_tce.c
> +++ b/drivers/vfio/vfio_iommu_spapr_tce.c
> @@ -371,6 +371,7 @@ static void tce_iommu_release(void *iommu_data)
> {
> struct tce_container *container = iommu_data;
> struct tce_iommu_group *tcegrp;
> + struct tce_iommu_prereg *tcemem, *tmtmp;
> long i;
>
> while (tce_groups_attached(container)) {
> @@ -393,13 +394,8 @@ static void tce_iommu_release(void *iommu_data)
> tce_iommu_free_table(container, tbl);
> }
>
> - while (!list_empty(&container->prereg_list)) {
> - struct tce_iommu_prereg *tcemem;
> -
> - tcemem = list_first_entry(&container->prereg_list,
> - struct tce_iommu_prereg, next);
> - WARN_ON_ONCE(tce_iommu_prereg_free(container, tcemem));
> - }
> + list_for_each_entry_safe(tcemem, tmtmp, &container->prereg_list, next)
> + WARN_ON(tce_iommu_prereg_free(container, tcemem));
I'm not sure that tce_iommu_prereg_free() call under WARN_ON() is good
idea because WARN_ON() is a preprocessor macro:
if CONFIG_WARN=n is added by the analogy with CONFIG_BUG=n defining
WARN_ON() as empty we will loose call to tce_iommu_prereg_free()
leaking resources.
There is no problem at the moment: WARN_ON() defined for PPC in
arch/powerpc/include/asm/bug.h unconditionally.
So your first version with intermediate variable looks better to me.
>
> tce_iommu_disable(container);
> if (container->mm)
>
--
Thanks,
Serhii
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: [PATCH 29/36] dt-bindings: arm: Convert Renesas board/soc bindings to json-schema
From: Geert Uytterhoeven @ 2018-10-08 7:47 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Kumar Gala, Grant Likely, Arnd Bergmann, Tom Rini, Simon Horman,
Frank Rowand, Linus Walleij, Pantelis Antoniou,
Linux Kernel Mailing List, Björn Andersson, Linux-Renesas,
Mark Brown, Jonathan Cameron, Olof Johansson, linuxppc-dev,
Linux ARM
In-Reply-To: <20181005165848.3474-30-robh@kernel.org>
Hi Rob,
On Fri, Oct 5, 2018 at 6:59 PM Rob Herring <robh@kernel.org> wrote:
> Convert Renesas SoC bindings to DT schema format using json-schema.
>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Magnus Damm <magnus.damm@gmail.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-renesas-soc@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Rob Herring <robh@kernel.org>
Thanks for your patch!
Note that this will need a rebase, as more SoCs/boards have been added
in -next.
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/shmobile.yaml
> @@ -0,0 +1,205 @@
> +# SPDX-License-Identifier: None
The old file didn't have an SPDX header, so it was GPL-2.0, implicitly?
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bindings/arm/shmobile.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas SH-Mobile, R-Mobile, and R-Car Platform Device Tree Bindings
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
Simon Horman <horms@verge.net.au> (supporter:ARM/SHMOBILE ARM ARCHITECTURE)
Magnus Damm <magnus.damm@gmail.com> (supporter:ARM/SHMOBILE ARM ARCHITECTURE)
You had it right in the CC list, though...
> + - description: RZ/G1M (R8A77430)
> + items:
> + - enum:
> + # iWave Systems RZ/G1M Qseven Development Platform (iW-RainboW-G20D-Qseven)
> + - iwave,g20d
> + - const: iwave,g20m
> + - const: renesas,r8a7743
> +
> + - items:
> + - enum:
> + # iWave Systems RZ/G1M Qseven System On Module (iW-RainboW-G20M-Qseven)
> + - iwave,g20m
> + - const: renesas,r8a7743
> +
> + - description: RZ/G1N (R8A77440)
> + items:
> + - enum:
> + - renesas,sk-rzg1m # SK-RZG1M (YR8A77430S000BE)
This board belongs under the RZ/G1M section above
(see also the 7743 in the part number).
> + - const: renesas,r8a7744
> + - description: Kingfisher (SBEV-RCAR-KF-M03)
> + items:
> + - const: shimafuji,kingfisher
> + - enum:
> + - renesas,h3ulcb
> + - renesas,m3ulcb
> + - enum:
> + - renesas,r8a7795
> + - renesas,r8a7796
This looks a bit funny: all other entries have the "const" last, and
use it for the
SoC number. May be correct, though.
To clarify, this is an extension board that can fit both the [HM]3ULCB
boards (actually also the new M3NULCB, I think).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] powerpc: Don't print kernel instructions in show_user_instructions()
From: Michael Ellerman @ 2018-10-08 8:12 UTC (permalink / raw)
To: Christophe LEROY, linuxppc-dev; +Cc: jannh, muriloo
In-Reply-To: <73301bba-c675-a930-83d6-5b258c07c26e@c-s.fr>
Christophe LEROY <christophe.leroy@c-s.fr> writes:
> Le 05/10/2018 à 15:21, Michael Ellerman a écrit :
>> Recently we implemented show_user_instructions() which dumps the code
...
>> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
>> index 913c5725cdb2..bb6ac471a784 100644
>> --- a/arch/powerpc/kernel/process.c
>> +++ b/arch/powerpc/kernel/process.c
>> @@ -1306,6 +1306,16 @@ void show_user_instructions(struct pt_regs *regs)
>>
>> pc = regs->nip - (instructions_to_print * 3 / 4 * sizeof(int));
>>
>> + /*
>> + * Make sure the NIP points at userspace, not kernel text/data or
>> + * elsewhere.
>> + */
>> + if (!__access_ok(pc, instructions_to_print * sizeof(int), USER_DS)) {
>> + pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
>> + current->comm, current->pid);
>> + return;
>> + }
>> +
>
> This will conflict with my serie
> https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=64611
> which changes instructions_to_print to a constant. Will you merge it or
> do you expect me to rebase my serie ?
I can fix it up.
But I see you've already rebased it and resent, you're too quick for me :)
cheers
^ permalink raw reply
* Re: [PATCH v5 05/33] KVM: PPC: Book3S HV: Extract PMU save/restore operations as C-callable functions
From: Madhavan Srinivasan @ 2018-10-08 8:16 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1538976679-1363-6-git-send-email-paulus@ozlabs.org>
On Monday 08 October 2018 11:00 AM, Paul Mackerras wrote:
> This pulls out the assembler code that is responsible for saving and
> restoring the PMU state for the host and guest into separate functions
> so they can be used from an alternate entry path. The calling
> convention is made compatible with C.
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
> ---
> arch/powerpc/include/asm/asm-prototypes.h | 5 +
> arch/powerpc/kvm/book3s_hv_interrupts.S | 95 ++++----
> arch/powerpc/kvm/book3s_hv_rmhandlers.S | 363 ++++++++++++++++--------------
> 3 files changed, 253 insertions(+), 210 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h
> index 1f4691c..024e8fc 100644
> --- a/arch/powerpc/include/asm/asm-prototypes.h
> +++ b/arch/powerpc/include/asm/asm-prototypes.h
> @@ -150,4 +150,9 @@ extern s32 patch__memset_nocache, patch__memcpy_nocache;
>
> extern long flush_count_cache;
>
> +void kvmhv_save_host_pmu(void);
> +void kvmhv_load_host_pmu(void);
> +void kvmhv_save_guest_pmu(struct kvm_vcpu *vcpu, bool pmu_in_use);
> +void kvmhv_load_guest_pmu(struct kvm_vcpu *vcpu);
> +
> #endif /* _ASM_POWERPC_ASM_PROTOTYPES_H */
> diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S
> index 666b91c..a6d1001 100644
> --- a/arch/powerpc/kvm/book3s_hv_interrupts.S
> +++ b/arch/powerpc/kvm/book3s_hv_interrupts.S
> @@ -64,52 +64,7 @@ BEGIN_FTR_SECTION
> END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
>
> /* Save host PMU registers */
> -BEGIN_FTR_SECTION
> - /* Work around P8 PMAE bug */
> - li r3, -1
> - clrrdi r3, r3, 10
> - mfspr r8, SPRN_MMCR2
> - mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
> - isync
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - li r3, 1
> - sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> - mfspr r7, SPRN_MMCR0 /* save MMCR0 */
> - mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
> - mfspr r6, SPRN_MMCRA
> - /* Clear MMCRA in order to disable SDAR updates */
> - li r5, 0
> - mtspr SPRN_MMCRA, r5
> - isync
> - lbz r5, PACA_PMCINUSE(r13) /* is the host using the PMU? */
> - cmpwi r5, 0
> - beq 31f /* skip if not */
> - mfspr r5, SPRN_MMCR1
> - mfspr r9, SPRN_SIAR
> - mfspr r10, SPRN_SDAR
> - std r7, HSTATE_MMCR0(r13)
> - std r5, HSTATE_MMCR1(r13)
> - std r6, HSTATE_MMCRA(r13)
> - std r9, HSTATE_SIAR(r13)
> - std r10, HSTATE_SDAR(r13)
> -BEGIN_FTR_SECTION
> - mfspr r9, SPRN_SIER
> - std r8, HSTATE_MMCR2(r13)
> - std r9, HSTATE_SIER(r13)
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - mfspr r3, SPRN_PMC1
> - mfspr r5, SPRN_PMC2
> - mfspr r6, SPRN_PMC3
> - mfspr r7, SPRN_PMC4
> - mfspr r8, SPRN_PMC5
> - mfspr r9, SPRN_PMC6
> - stw r3, HSTATE_PMC1(r13)
> - stw r5, HSTATE_PMC2(r13)
> - stw r6, HSTATE_PMC3(r13)
> - stw r7, HSTATE_PMC4(r13)
> - stw r8, HSTATE_PMC5(r13)
> - stw r9, HSTATE_PMC6(r13)
> -31:
> + bl kvmhv_save_host_pmu
>
> /*
> * Put whatever is in the decrementer into the
> @@ -161,3 +116,51 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
> ld r0, PPC_LR_STKOFF(r1)
> mtlr r0
> blr
> +
> +_GLOBAL(kvmhv_save_host_pmu)
> +BEGIN_FTR_SECTION
> + /* Work around P8 PMAE bug */
> + li r3, -1
> + clrrdi r3, r3, 10
> + mfspr r8, SPRN_MMCR2
> + mtspr SPRN_MMCR2, r3 /* freeze all counters using MMCR2 */
> + isync
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + li r3, 1
> + sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> + mfspr r7, SPRN_MMCR0 /* save MMCR0 */
> + mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
> + mfspr r6, SPRN_MMCRA
> + /* Clear MMCRA in order to disable SDAR updates */
> + li r5, 0
> + mtspr SPRN_MMCRA, r5
> + isync
> + lbz r5, PACA_PMCINUSE(r13) /* is the host using the PMU? */
> + cmpwi r5, 0
> + beq 31f /* skip if not */
> + mfspr r5, SPRN_MMCR1
> + mfspr r9, SPRN_SIAR
> + mfspr r10, SPRN_SDAR
> + std r7, HSTATE_MMCR0(r13)
> + std r5, HSTATE_MMCR1(r13)
> + std r6, HSTATE_MMCRA(r13)
> + std r9, HSTATE_SIAR(r13)
> + std r10, HSTATE_SDAR(r13)
> +BEGIN_FTR_SECTION
> + mfspr r9, SPRN_SIER
> + std r8, HSTATE_MMCR2(r13)
> + std r9, HSTATE_SIER(r13)
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + mfspr r3, SPRN_PMC1
> + mfspr r5, SPRN_PMC2
> + mfspr r6, SPRN_PMC3
> + mfspr r7, SPRN_PMC4
> + mfspr r8, SPRN_PMC5
> + mfspr r9, SPRN_PMC6
> + stw r3, HSTATE_PMC1(r13)
> + stw r5, HSTATE_PMC2(r13)
> + stw r6, HSTATE_PMC3(r13)
> + stw r7, HSTATE_PMC4(r13)
> + stw r8, HSTATE_PMC5(r13)
> + stw r9, HSTATE_PMC6(r13)
> +31: blr
> diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> index 6752da1..5b2ae34 100644
> --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
> @@ -28,6 +28,7 @@
> #include <asm/exception-64s.h>
> #include <asm/kvm_book3s_asm.h>
> #include <asm/book3s/64/mmu-hash.h>
> +#include <asm/export.h>
> #include <asm/tm.h>
> #include <asm/opal.h>
> #include <asm/xive-regs.h>
> @@ -113,45 +114,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
> mtspr SPRN_SPRG_VDSO_WRITE,r3
>
> /* Reload the host's PMU registers */
> - lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
> - cmpwi r4, 0
> - beq 23f /* skip if not */
> -BEGIN_FTR_SECTION
> - ld r3, HSTATE_MMCR0(r13)
> - andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
> - cmpwi r4, MMCR0_PMAO
> - beql kvmppc_fix_pmao
> -END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
> - lwz r3, HSTATE_PMC1(r13)
> - lwz r4, HSTATE_PMC2(r13)
> - lwz r5, HSTATE_PMC3(r13)
> - lwz r6, HSTATE_PMC4(r13)
> - lwz r8, HSTATE_PMC5(r13)
> - lwz r9, HSTATE_PMC6(r13)
> - mtspr SPRN_PMC1, r3
> - mtspr SPRN_PMC2, r4
> - mtspr SPRN_PMC3, r5
> - mtspr SPRN_PMC4, r6
> - mtspr SPRN_PMC5, r8
> - mtspr SPRN_PMC6, r9
> - ld r3, HSTATE_MMCR0(r13)
> - ld r4, HSTATE_MMCR1(r13)
> - ld r5, HSTATE_MMCRA(r13)
> - ld r6, HSTATE_SIAR(r13)
> - ld r7, HSTATE_SDAR(r13)
> - mtspr SPRN_MMCR1, r4
> - mtspr SPRN_MMCRA, r5
> - mtspr SPRN_SIAR, r6
> - mtspr SPRN_SDAR, r7
> -BEGIN_FTR_SECTION
> - ld r8, HSTATE_MMCR2(r13)
> - ld r9, HSTATE_SIER(r13)
> - mtspr SPRN_MMCR2, r8
> - mtspr SPRN_SIER, r9
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - mtspr SPRN_MMCR0, r3
> - isync
> -23:
> + bl kvmhv_load_host_pmu
>
> /*
> * Reload DEC. HDEC interrupts were disabled when
> @@ -805,57 +768,12 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
> 91:
> #endif
>
> - /* Load guest PMU registers */
> - /* R4 is live here (vcpu pointer) */
> - li r3, 1
> - sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> - mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
> - isync
> -BEGIN_FTR_SECTION
> - ld r3, VCPU_MMCR(r4)
> - andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
> - cmpwi r5, MMCR0_PMAO
> - beql kvmppc_fix_pmao
> -END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
> - lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
> - lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
> - lwz r6, VCPU_PMC + 8(r4)
> - lwz r7, VCPU_PMC + 12(r4)
> - lwz r8, VCPU_PMC + 16(r4)
> - lwz r9, VCPU_PMC + 20(r4)
> - mtspr SPRN_PMC1, r3
> - mtspr SPRN_PMC2, r5
> - mtspr SPRN_PMC3, r6
> - mtspr SPRN_PMC4, r7
> - mtspr SPRN_PMC5, r8
> - mtspr SPRN_PMC6, r9
> - ld r3, VCPU_MMCR(r4)
> - ld r5, VCPU_MMCR + 8(r4)
> - ld r6, VCPU_MMCR + 16(r4)
> - ld r7, VCPU_SIAR(r4)
> - ld r8, VCPU_SDAR(r4)
> - mtspr SPRN_MMCR1, r5
> - mtspr SPRN_MMCRA, r6
> - mtspr SPRN_SIAR, r7
> - mtspr SPRN_SDAR, r8
> -BEGIN_FTR_SECTION
> - ld r5, VCPU_MMCR + 24(r4)
> - ld r6, VCPU_SIER(r4)
> - mtspr SPRN_MMCR2, r5
> - mtspr SPRN_SIER, r6
> -BEGIN_FTR_SECTION_NESTED(96)
> - lwz r7, VCPU_PMC + 24(r4)
> - lwz r8, VCPU_PMC + 28(r4)
> - ld r9, VCPU_MMCR + 32(r4)
> - mtspr SPRN_SPMC1, r7
> - mtspr SPRN_SPMC2, r8
> - mtspr SPRN_MMCRS, r9
> -END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - mtspr SPRN_MMCR0, r3
> - isync
> + /* Load guest PMU registers; r4 = vcpu pointer here */
> + mr r3, r4
> + bl kvmhv_load_guest_pmu
>
> /* Load up FP, VMX and VSX registers */
> + ld r4, HSTATE_KVM_VCPU(r13)
> bl kvmppc_load_fp
>
> ld r14, VCPU_GPR(R14)(r4)
> @@ -1766,83 +1684,12 @@ END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
> 25:
> /* Save PMU registers if requested */
> /* r8 and cr0.eq are live here */
> -BEGIN_FTR_SECTION
> - /*
> - * POWER8 seems to have a hardware bug where setting
> - * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
> - * when some counters are already negative doesn't seem
> - * to cause a performance monitor alert (and hence interrupt).
> - * The effect of this is that when saving the PMU state,
> - * if there is no PMU alert pending when we read MMCR0
> - * before freezing the counters, but one becomes pending
> - * before we read the counters, we lose it.
> - * To work around this, we need a way to freeze the counters
> - * before reading MMCR0. Normally, freezing the counters
> - * is done by writing MMCR0 (to set MMCR0[FC]) which
> - * unavoidably writes MMCR0[PMA0] as well. On POWER8,
> - * we can also freeze the counters using MMCR2, by writing
> - * 1s to all the counter freeze condition bits (there are
> - * 9 bits each for 6 counters).
> - */
> - li r3, -1 /* set all freeze bits */
> - clrrdi r3, r3, 10
> - mfspr r10, SPRN_MMCR2
> - mtspr SPRN_MMCR2, r3
> - isync
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - li r3, 1
> - sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> - mfspr r4, SPRN_MMCR0 /* save MMCR0 */
> - mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
> - mfspr r6, SPRN_MMCRA
> - /* Clear MMCRA in order to disable SDAR updates */
> - li r7, 0
> - mtspr SPRN_MMCRA, r7
> - isync
> + mr r3, r9
> + li r4, 1
> beq 21f /* if no VPA, save PMU stuff anyway */
> - lbz r7, LPPACA_PMCINUSE(r8)
> - cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
> - bne 21f
> - std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
> - b 22f
> -21: mfspr r5, SPRN_MMCR1
> - mfspr r7, SPRN_SIAR
> - mfspr r8, SPRN_SDAR
> - std r4, VCPU_MMCR(r9)
> - std r5, VCPU_MMCR + 8(r9)
> - std r6, VCPU_MMCR + 16(r9)
> -BEGIN_FTR_SECTION
> - std r10, VCPU_MMCR + 24(r9)
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> - std r7, VCPU_SIAR(r9)
> - std r8, VCPU_SDAR(r9)
> - mfspr r3, SPRN_PMC1
> - mfspr r4, SPRN_PMC2
> - mfspr r5, SPRN_PMC3
> - mfspr r6, SPRN_PMC4
> - mfspr r7, SPRN_PMC5
> - mfspr r8, SPRN_PMC6
> - stw r3, VCPU_PMC(r9)
> - stw r4, VCPU_PMC + 4(r9)
> - stw r5, VCPU_PMC + 8(r9)
> - stw r6, VCPU_PMC + 12(r9)
> - stw r7, VCPU_PMC + 16(r9)
> - stw r8, VCPU_PMC + 20(r9)
> -BEGIN_FTR_SECTION
> - mfspr r5, SPRN_SIER
> - std r5, VCPU_SIER(r9)
> -BEGIN_FTR_SECTION_NESTED(96)
> - mfspr r6, SPRN_SPMC1
> - mfspr r7, SPRN_SPMC2
> - mfspr r8, SPRN_MMCRS
> - stw r6, VCPU_PMC + 24(r9)
> - stw r7, VCPU_PMC + 28(r9)
> - std r8, VCPU_MMCR + 32(r9)
> - lis r4, 0x8000
> - mtspr SPRN_MMCRS, r4
> -END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
> -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> -22:
> + lbz r4, LPPACA_PMCINUSE(r8)
> +21: bl kvmhv_save_guest_pmu
> + ld r9, HSTATE_KVM_VCPU(r13)
>
> /* Restore host values of some registers */
> BEGIN_FTR_SECTION
> @@ -3388,6 +3235,194 @@ kvmppc_msr_interrupt:
> blr
>
> /*
> + * Load up guest PMU state. R3 points to the vcpu struct.
> + */
> +_GLOBAL(kvmhv_load_guest_pmu)
> +EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
> + mr r4, r3
> + mflr r0
> + li r3, 1
> + sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> + mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
> + isync
> +BEGIN_FTR_SECTION
> + ld r3, VCPU_MMCR(r4)
> + andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
> + cmpwi r5, MMCR0_PMAO
> + beql kvmppc_fix_pmao
> +END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
> + lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
> + lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
> + lwz r6, VCPU_PMC + 8(r4)
> + lwz r7, VCPU_PMC + 12(r4)
> + lwz r8, VCPU_PMC + 16(r4)
> + lwz r9, VCPU_PMC + 20(r4)
> + mtspr SPRN_PMC1, r3
> + mtspr SPRN_PMC2, r5
> + mtspr SPRN_PMC3, r6
> + mtspr SPRN_PMC4, r7
> + mtspr SPRN_PMC5, r8
> + mtspr SPRN_PMC6, r9
> + ld r3, VCPU_MMCR(r4)
> + ld r5, VCPU_MMCR + 8(r4)
> + ld r6, VCPU_MMCR + 16(r4)
> + ld r7, VCPU_SIAR(r4)
> + ld r8, VCPU_SDAR(r4)
> + mtspr SPRN_MMCR1, r5
> + mtspr SPRN_MMCRA, r6
> + mtspr SPRN_SIAR, r7
> + mtspr SPRN_SDAR, r8
> +BEGIN_FTR_SECTION
> + ld r5, VCPU_MMCR + 24(r4)
> + ld r6, VCPU_SIER(r4)
> + mtspr SPRN_MMCR2, r5
> + mtspr SPRN_SIER, r6
> +BEGIN_FTR_SECTION_NESTED(96)
> + lwz r7, VCPU_PMC + 24(r4)
> + lwz r8, VCPU_PMC + 28(r4)
> + ld r9, VCPU_MMCR + 32(r4)
> + mtspr SPRN_SPMC1, r7
> + mtspr SPRN_SPMC2, r8
> + mtspr SPRN_MMCRS, r9
> +END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + mtspr SPRN_MMCR0, r3
> + isync
> + mtlr r0
> + blr
> +
> +/*
> + * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
> + */
> +_GLOBAL(kvmhv_load_host_pmu)
> +EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
> + mflr r0
> + lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
> + cmpwi r4, 0
> + beq 23f /* skip if not */
> +BEGIN_FTR_SECTION
> + ld r3, HSTATE_MMCR0(r13)
> + andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
> + cmpwi r4, MMCR0_PMAO
> + beql kvmppc_fix_pmao
> +END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
> + lwz r3, HSTATE_PMC1(r13)
> + lwz r4, HSTATE_PMC2(r13)
> + lwz r5, HSTATE_PMC3(r13)
> + lwz r6, HSTATE_PMC4(r13)
> + lwz r8, HSTATE_PMC5(r13)
> + lwz r9, HSTATE_PMC6(r13)
> + mtspr SPRN_PMC1, r3
> + mtspr SPRN_PMC2, r4
> + mtspr SPRN_PMC3, r5
> + mtspr SPRN_PMC4, r6
> + mtspr SPRN_PMC5, r8
> + mtspr SPRN_PMC6, r9
> + ld r3, HSTATE_MMCR0(r13)
> + ld r4, HSTATE_MMCR1(r13)
> + ld r5, HSTATE_MMCRA(r13)
> + ld r6, HSTATE_SIAR(r13)
> + ld r7, HSTATE_SDAR(r13)
> + mtspr SPRN_MMCR1, r4
> + mtspr SPRN_MMCRA, r5
> + mtspr SPRN_SIAR, r6
> + mtspr SPRN_SDAR, r7
> +BEGIN_FTR_SECTION
> + ld r8, HSTATE_MMCR2(r13)
> + ld r9, HSTATE_SIER(r13)
> + mtspr SPRN_MMCR2, r8
> + mtspr SPRN_SIER, r9
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + mtspr SPRN_MMCR0, r3
> + isync
> + mtlr r0
> +23: blr
> +
> +/*
> + * Save guest PMU state into the vcpu struct.
> + * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
> + */
> +_GLOBAL(kvmhv_save_guest_pmu)
> +EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
> + mr r9, r3
> + mr r8, r4
> +BEGIN_FTR_SECTION
> + /*
> + * POWER8 seems to have a hardware bug where setting
> + * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
> + * when some counters are already negative doesn't seem
> + * to cause a performance monitor alert (and hence interrupt).
> + * The effect of this is that when saving the PMU state,
> + * if there is no PMU alert pending when we read MMCR0
> + * before freezing the counters, but one becomes pending
> + * before we read the counters, we lose it.
> + * To work around this, we need a way to freeze the counters
> + * before reading MMCR0. Normally, freezing the counters
> + * is done by writing MMCR0 (to set MMCR0[FC]) which
> + * unavoidably writes MMCR0[PMA0] as well. On POWER8,
> + * we can also freeze the counters using MMCR2, by writing
> + * 1s to all the counter freeze condition bits (there are
> + * 9 bits each for 6 counters).
> + */
> + li r3, -1 /* set all freeze bits */
> + clrrdi r3, r3, 10
> + mfspr r10, SPRN_MMCR2
> + mtspr SPRN_MMCR2, r3
> + isync
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + li r3, 1
> + sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
> + mfspr r4, SPRN_MMCR0 /* save MMCR0 */
> + mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
> + mfspr r6, SPRN_MMCRA
> + /* Clear MMCRA in order to disable SDAR updates */
> + li r7, 0
> + mtspr SPRN_MMCRA, r7
> + isync
> + cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
> + bne 21f
> + std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
> + b 22f
> +21: mfspr r5, SPRN_MMCR1
> + mfspr r7, SPRN_SIAR
> + mfspr r8, SPRN_SDAR
> + std r4, VCPU_MMCR(r9)
> + std r5, VCPU_MMCR + 8(r9)
> + std r6, VCPU_MMCR + 16(r9)
> +BEGIN_FTR_SECTION
> + std r10, VCPU_MMCR + 24(r9)
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> + std r7, VCPU_SIAR(r9)
> + std r8, VCPU_SDAR(r9)
> + mfspr r3, SPRN_PMC1
> + mfspr r4, SPRN_PMC2
> + mfspr r5, SPRN_PMC3
> + mfspr r6, SPRN_PMC4
> + mfspr r7, SPRN_PMC5
> + mfspr r8, SPRN_PMC6
> + stw r3, VCPU_PMC(r9)
> + stw r4, VCPU_PMC + 4(r9)
> + stw r5, VCPU_PMC + 8(r9)
> + stw r6, VCPU_PMC + 12(r9)
> + stw r7, VCPU_PMC + 16(r9)
> + stw r8, VCPU_PMC + 20(r9)
> +BEGIN_FTR_SECTION
> + mfspr r5, SPRN_SIER
> + std r5, VCPU_SIER(r9)
> +BEGIN_FTR_SECTION_NESTED(96)
> + mfspr r6, SPRN_SPMC1
> + mfspr r7, SPRN_SPMC2
> + mfspr r8, SPRN_MMCRS
> + stw r6, VCPU_PMC + 24(r9)
> + stw r7, VCPU_PMC + 28(r9)
> + std r8, VCPU_MMCR + 32(r9)
> + lis r4, 0x8000
> + mtspr SPRN_MMCRS, r4
> +END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
> +22: blr
> +
> +/*
> * This works around a hardware bug on POWER8E processors, where
> * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
> * performance monitor interrupt. Instead, when we need to have
^ permalink raw reply
* Re: [PATCH] powerpc: Don't print kernel instructions in show_user_instructions()
From: Michael Ellerman @ 2018-10-08 8:23 UTC (permalink / raw)
To: Jann Horn; +Cc: linuxppc-dev, muriloo
In-Reply-To: <CAG48ez3OZ5iquQeeqsy_SaLQF04hf6kphTSuP=OfsWC35G+TbA@mail.gmail.com>
Jann Horn <jannh@google.com> writes:
> On Fri, Oct 5, 2018 at 3:21 PM Michael Ellerman <mpe@ellerman.id.au> wrote:
>> Recently we implemented show_user_instructions() which dumps the code
>> around the NIP when a user space process dies with an unhandled
>> signal. This was modelled on the x86 code, and we even went so far as
>> to implement the exact same bug, namely that if the user process
>> crashed with its NIP pointing into the kernel we will dump kernel text
>> to dmesg. eg:
>>
>> bad-bctr[2996]: segfault (11) at c000000000010000 nip c000000000010000 lr 12d0b0894 code 1
>> bad-bctr[2996]: code: fbe10068 7cbe2b78 7c7f1b78 fb610048 38a10028 38810020 fb810050 7f8802a6
>> bad-bctr[2996]: code: 3860001c f8010080 48242371 60000000 <7c7b1b79> 4082002c e8010080 eb610048
>>
>> This was discovered on x86 by Jann Horn and fixed in commit
>> 342db04ae712 ("x86/dumpstack: Don't dump kernel memory based on usermode RIP").
>>
>> Fix it by checking the adjusted NIP value (pc) and number of
>> instructions against USER_DS, and bail if we fail the check, eg:
>
> This fix looks good to me.
Thanks.
> In the long term, I think it is somewhat awkward to use
> probe_kernel_address(), which uses set_fs(KERNEL_DS), when you
> actually just want to access userspace memory. It might make sense to
> provide a better helper for explicitly accessing memory with USER_DS.
Yes I agree, it's a bit messy. A probe_user_read() that sets USER_DS and
does the access_ok() check would be less error prone I think.
cheers
^ permalink raw reply
* Re: [PATCH -next] powerpc/powernv: Fix debugfs_simple_attr.cocci warnings
From: Michael Ellerman @ 2018-10-08 8:27 UTC (permalink / raw)
To: YueHaibing, Benjamin Herrenschmidt, Paul Mackerras,
David Hildenbrand, Michael Neuling, Balbir Singh, Rashmica Gupta,
Andrew Morton, Pavel Tatashin, Stephen Rothwell
Cc: linuxppc-dev, kernel-janitors, YueHaibing, linux-kernel
In-Reply-To: <1538736631-99728-1-git-send-email-yuehaibing@huawei.com>
YueHaibing <yuehaibing@huawei.com> writes:
> Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE
> for debugfs files.
>
> Semantic patch information:
> Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file()
> imposes some significant overhead as compared to
> DEFINE_DEBUGFS_ATTRIBUTE + debugfs_create_file_unsafe().
Sorry this isn't detailed enough for me to actually understand the
pros/cons of this patch.
Perhaps I'm expected to know it, but I don't.
I had a look at what each macro produces and it wasn't obvious to me
what the benefit is.
cheers
> Generated by: scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci
>
> Signed-off-by: YueHaibing <yuehaibing@huawei.com>
> ---
> arch/powerpc/platforms/powernv/memtrace.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powernv/memtrace.c b/arch/powerpc/platforms/powernv/memtrace.c
> index 84d038e..0cb6548 100644
> --- a/arch/powerpc/platforms/powernv/memtrace.c
> +++ b/arch/powerpc/platforms/powernv/memtrace.c
> @@ -311,8 +311,8 @@ static int memtrace_enable_get(void *data, u64 *val)
> return 0;
> }
>
> -DEFINE_SIMPLE_ATTRIBUTE(memtrace_init_fops, memtrace_enable_get,
> - memtrace_enable_set, "0x%016llx\n");
> +DEFINE_DEBUGFS_ATTRIBUTE(memtrace_init_fops, memtrace_enable_get,
> + memtrace_enable_set, "0x%016llx\n");
>
> static int memtrace_init(void)
> {
> @@ -321,8 +321,8 @@ static int memtrace_init(void)
> if (!memtrace_debugfs_dir)
> return -1;
>
> - debugfs_create_file("enable", 0600, memtrace_debugfs_dir,
> - NULL, &memtrace_init_fops);
> + debugfs_create_file_unsafe("enable", 0600, memtrace_debugfs_dir, NULL,
> + &memtrace_init_fops);
>
> return 0;
> }
^ permalink raw reply
* [PATCH v6 1/9] book3s/64: avoid circular header inclusion in mmu-hash.h
From: Christophe Leroy @ 2018-10-08 9:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1538954166.git.christophe.leroy@c-s.fr>
When activating CONFIG_THREAD_INFO_IN_TASK, linux/sched.h
includes asm/current.h. This generates a circular dependency.
To avoid that, asm/processor.h shall not be included in mmu-hash.h
In order to do that, this patch moves into a new header called
asm/task_size_user64.h the information from asm/processor.h required
by mmu-hash.h
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 +-
arch/powerpc/include/asm/processor.h | 34 +---------------------
arch/powerpc/include/asm/task_size_user64.h | 42 +++++++++++++++++++++++++++
arch/powerpc/kvm/book3s_hv_hmi.c | 1 +
4 files changed, 45 insertions(+), 34 deletions(-)
create mode 100644 arch/powerpc/include/asm/task_size_user64.h
diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
index e0e4ce8f77d6..02955d867067 100644
--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h
@@ -23,7 +23,7 @@
*/
#include <asm/book3s/64/pgtable.h>
#include <asm/bug.h>
-#include <asm/processor.h>
+#include <asm/task_size_user64.h>
#include <asm/cpu_has_feature.h>
/*
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 52fadded5c1e..13589274fe9b 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -101,40 +101,8 @@ void release_thread(struct task_struct *);
#endif
#ifdef CONFIG_PPC64
-/*
- * 64-bit user address space can have multiple limits
- * For now supported values are:
- */
-#define TASK_SIZE_64TB (0x0000400000000000UL)
-#define TASK_SIZE_128TB (0x0000800000000000UL)
-#define TASK_SIZE_512TB (0x0002000000000000UL)
-#define TASK_SIZE_1PB (0x0004000000000000UL)
-#define TASK_SIZE_2PB (0x0008000000000000UL)
-/*
- * With 52 bits in the address we can support
- * upto 4PB of range.
- */
-#define TASK_SIZE_4PB (0x0010000000000000UL)
-/*
- * For now 512TB is only supported with book3s and 64K linux page size.
- */
-#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
-/*
- * Max value currently used:
- */
-#define TASK_SIZE_USER64 TASK_SIZE_4PB
-#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_128TB
-#define TASK_CONTEXT_SIZE TASK_SIZE_512TB
-#else
-#define TASK_SIZE_USER64 TASK_SIZE_64TB
-#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_64TB
-/*
- * We don't need to allocate extended context ids for 4K page size, because
- * we limit the max effective address on this config to 64TB.
- */
-#define TASK_CONTEXT_SIZE TASK_SIZE_64TB
-#endif
+#include <asm/task_size_user64.h>
/*
* 32-bit user address space is 4GB - 1 page
diff --git a/arch/powerpc/include/asm/task_size_user64.h b/arch/powerpc/include/asm/task_size_user64.h
new file mode 100644
index 000000000000..a4043075864b
--- /dev/null
+++ b/arch/powerpc/include/asm/task_size_user64.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_POWERPC_TASK_SIZE_USER64_H
+#define _ASM_POWERPC_TASK_SIZE_USER64_H
+
+#ifdef CONFIG_PPC64
+/*
+ * 64-bit user address space can have multiple limits
+ * For now supported values are:
+ */
+#define TASK_SIZE_64TB (0x0000400000000000UL)
+#define TASK_SIZE_128TB (0x0000800000000000UL)
+#define TASK_SIZE_512TB (0x0002000000000000UL)
+#define TASK_SIZE_1PB (0x0004000000000000UL)
+#define TASK_SIZE_2PB (0x0008000000000000UL)
+/*
+ * With 52 bits in the address we can support
+ * upto 4PB of range.
+ */
+#define TASK_SIZE_4PB (0x0010000000000000UL)
+
+/*
+ * For now 512TB is only supported with book3s and 64K linux page size.
+ */
+#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
+/*
+ * Max value currently used:
+ */
+#define TASK_SIZE_USER64 TASK_SIZE_4PB
+#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_128TB
+#define TASK_CONTEXT_SIZE TASK_SIZE_512TB
+#else
+#define TASK_SIZE_USER64 TASK_SIZE_64TB
+#define DEFAULT_MAP_WINDOW_USER64 TASK_SIZE_64TB
+/*
+ * We don't need to allocate extended context ids for 4K page size, because
+ * we limit the max effective address on this config to 64TB.
+ */
+#define TASK_CONTEXT_SIZE TASK_SIZE_64TB
+#endif
+
+#endif /* CONFIG_PPC64 */
+#endif /* _ASM_POWERPC_TASK_SIZE_USER64_H */
diff --git a/arch/powerpc/kvm/book3s_hv_hmi.c b/arch/powerpc/kvm/book3s_hv_hmi.c
index e3f738eb1cac..64b5011475c7 100644
--- a/arch/powerpc/kvm/book3s_hv_hmi.c
+++ b/arch/powerpc/kvm/book3s_hv_hmi.c
@@ -24,6 +24,7 @@
#include <linux/compiler.h>
#include <asm/paca.h>
#include <asm/hmi.h>
+#include <asm/processor.h>
void wait_for_subcore_guest_exit(void)
{
--
2.13.3
^ permalink raw reply related
* [PATCH v6 0/9] powerpc: Switch to CONFIG_THREAD_INFO_IN_TASK
From: Christophe Leroy @ 2018-10-08 9:16 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
The purpose of this serie is to activate CONFIG_THREAD_INFO_IN_TASK which
moves the thread_info into task_struct.
Moving thread_info into task_struct has the following advantages:
- It protects thread_info from corruption in the case of stack
overflows.
- Its address is harder to determine if stack addresses are
leaked, making a number of attacks more difficult.
Changes since v5:
- Fixed livepatch_sp setup by using end_of_stack() instead of hardcoding
- Fixed PPC_BPF_LOAD_CPU() macro
Changes since v4:
- Fixed a build failure on 32bits SMP when include/generated/asm-offsets.h is not
already existing, was due to spaces instead of a tab in the Makefile
Changes since RFC v3: (based on Nick's review)
- Renamed task_size.h to task_size_user64.h to better relate to what it contains.
- Handling of the isolation of thread_info cpu field inside CONFIG_SMP #ifdefs moved to a separate patch.
- Removed CURRENT_THREAD_INFO macro completely.
- Added a guard in asm/smp.h to avoid build failure before _TASK_CPU is defined.
- Added a patch at the end to rename 'tp' pointers to 'sp' pointers
- Renamed 'tp' into 'sp' pointers in preparation patch when relevant
- Fixed a few commit logs
- Fixed checkpatch report.
Changes since RFC v2:
- Removed the modification of names in asm-offsets
- Created a rule in arch/powerpc/Makefile to append the offset of current->cpu in CFLAGS
- Modified asm/smp.h to use the offset set in CFLAGS
- Squashed the renaming of THREAD_INFO to TASK_STACK in the preparation patch
- Moved the modification of current_pt_regs in the patch activating CONFIG_THREAD_INFO_IN_TASK
Changes since RFC v1:
- Removed the first patch which was modifying header inclusion order in timer
- Modified some names in asm-offsets to avoid conflicts when including asm-offsets in C files
- Modified asm/smp.h to avoid having to include linux/sched.h (using asm-offsets instead)
- Moved some changes from the activation patch to the preparation patch.
Christophe Leroy (9):
book3s/64: avoid circular header inclusion in mmu-hash.h
powerpc: Only use task_struct 'cpu' field on SMP
powerpc: Prepare for moving thread_info into task_struct
powerpc: Activate CONFIG_THREAD_INFO_IN_TASK
powerpc: regain entire stack space
powerpc: 'current_set' is now a table of task_struct pointers
powerpc/32: Remove CURRENT_THREAD_INFO and rename TI_CPU
powerpc/64: Remove CURRENT_THREAD_INFO
powerpc: clean stack pointers naming
arch/powerpc/Kconfig | 1 +
arch/powerpc/Makefile | 8 ++-
arch/powerpc/include/asm/asm-prototypes.h | 4 +-
arch/powerpc/include/asm/book3s/64/mmu-hash.h | 2 +-
arch/powerpc/include/asm/exception-64s.h | 4 +-
arch/powerpc/include/asm/irq.h | 14 ++---
arch/powerpc/include/asm/livepatch.h | 7 ++-
arch/powerpc/include/asm/processor.h | 39 +------------
arch/powerpc/include/asm/ptrace.h | 2 +-
arch/powerpc/include/asm/reg.h | 2 +-
arch/powerpc/include/asm/smp.h | 17 +++++-
arch/powerpc/include/asm/task_size_user64.h | 42 ++++++++++++++
arch/powerpc/include/asm/thread_info.h | 19 -------
arch/powerpc/kernel/asm-offsets.c | 10 ++--
arch/powerpc/kernel/entry_32.S | 66 ++++++++--------------
arch/powerpc/kernel/entry_64.S | 12 ++--
arch/powerpc/kernel/epapr_hcalls.S | 5 +-
arch/powerpc/kernel/exceptions-64e.S | 13 +----
arch/powerpc/kernel/exceptions-64s.S | 2 +-
arch/powerpc/kernel/head_32.S | 14 ++---
arch/powerpc/kernel/head_40x.S | 4 +-
arch/powerpc/kernel/head_44x.S | 8 +--
arch/powerpc/kernel/head_64.S | 1 +
arch/powerpc/kernel/head_8xx.S | 2 +-
arch/powerpc/kernel/head_booke.h | 12 +---
arch/powerpc/kernel/head_fsl_booke.S | 16 +++---
arch/powerpc/kernel/idle_6xx.S | 8 +--
arch/powerpc/kernel/idle_book3e.S | 2 +-
arch/powerpc/kernel/idle_e500.S | 8 +--
arch/powerpc/kernel/idle_power4.S | 2 +-
arch/powerpc/kernel/irq.c | 77 +++++---------------------
arch/powerpc/kernel/kgdb.c | 28 ----------
arch/powerpc/kernel/machine_kexec_64.c | 6 +-
arch/powerpc/kernel/misc_32.S | 17 +++---
arch/powerpc/kernel/process.c | 17 +++---
arch/powerpc/kernel/setup-common.c | 2 +-
arch/powerpc/kernel/setup_32.c | 15 ++---
arch/powerpc/kernel/setup_64.c | 41 ++++----------
arch/powerpc/kernel/smp.c | 16 +++---
arch/powerpc/kernel/trace/ftrace_64_mprofile.S | 6 +-
arch/powerpc/kvm/book3s_hv_hmi.c | 1 +
arch/powerpc/mm/hash_low_32.S | 14 ++---
arch/powerpc/net/bpf_jit32.h | 5 +-
arch/powerpc/sysdev/6xx-suspend.S | 5 +-
arch/powerpc/xmon/xmon.c | 2 +-
45 files changed, 230 insertions(+), 368 deletions(-)
create mode 100644 arch/powerpc/include/asm/task_size_user64.h
--
2.13.3
^ permalink raw reply
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