* Re: [PATCH v2 12/18] of: overlay: check prevents multiple fragments add or delete same node
From: Frank Rowand @ 2018-10-15 0:29 UTC (permalink / raw)
To: Joe Perches, Rob Herring, Pantelis Antoniou, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Alan Tull, Moritz Fischer
Cc: devicetree, linux-fpga, linuxppc-dev, linux-kernel
In-Reply-To: <651a8488-caec-b153-43c7-1fb81f641f1a@gmail.com>
On 10/13/18 11:21, Frank Rowand wrote:
> On 10/13/18 05:51, Joe Perches wrote:
>> On Fri, 2018-10-12 at 21:53 -0700, frowand.list@gmail.com wrote:
>>> From: Frank Rowand <frank.rowand@sony.com>
>>>
>>> Multiple overlay fragments adding or deleting the same node is not
>>> supported. Replace code comment of such, with check to detect the
>>> attempt and fail the overlay apply.
>>>
>>> Devicetree unittest where multiple fragments added the same node was
>>> added in the previous patch in the series. After applying this patch
>>> the unittest messages will no longer include:
>>>
>>> Duplicate name in motor-1, renamed to "controller#1"
>>> OF: overlay: of_overlay_apply() err=0
>>> ### dt-test ### of_overlay_fdt_apply() expected -22, ret=0, overlay_bad_add_dup_node
>>> ### dt-test ### FAIL of_unittest_overlay_high_level():2419 Adding overlay 'overlay_bad_add_dup_node' failed
>>>
>>> ...
>>>
>>> ### dt-test ### end of unittest - 210 passed, 1 failed
>>>
>>> but will instead include:
>>>
>>> OF: overlay: ERROR: multiple overlay fragments add and/or delete node /testcase-data-2/substation@100/motor-1/controller
>>>
>>> ...
>>>
>>> ### dt-test ### end of unittest - 211 passed, 0 failed
>> []
>>> diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
>> []
>>> @@ -523,6 +515,54 @@ static int build_changeset_symbols_node(struct overlay_changeset *ovcs,
>>> }
>>>
>>> /**
>>> + * check_changeset_dup_add_node() - changeset validation: duplicate add node
>>> + * @ovcs: Overlay changeset
>>> + *
>>> + * Check changeset @ovcs->cset for multiple add node entries for the same
>>> + * node.
>>> + *
>>> + * Returns 0 on success, -ENOMEM if memory allocation failure, or -EINVAL if
>>> + * invalid overlay in @ovcs->fragments[].
>>> + */
>>> +static int check_changeset_dup_add_node(struct overlay_changeset *ovcs)
>>> +{
>>> + struct of_changeset_entry *ce_1, *ce_2;
>>> + char *fn_1, *fn_2;
>>> + int name_match;
>>> +
>>> + list_for_each_entry(ce_1, &ovcs->cset.entries, node) {
>>> +
>>> + if (ce_1->action == OF_RECONFIG_ATTACH_NODE ||
>>> + ce_1->action == OF_RECONFIG_DETACH_NODE) {
>>> +
>>> + ce_2 = ce_1;
>>> + list_for_each_entry_continue(ce_2, &ovcs->cset.entries, node) {
>>> + if (ce_2->action == OF_RECONFIG_ATTACH_NODE ||
>>> + ce_2->action == OF_RECONFIG_DETACH_NODE) {
>>> + /* inexpensive name compare */
>>> + if (!of_node_cmp(ce_1->np->full_name,
>>> + ce_2->np->full_name)) {
>>
>> A bit of odd indentation here.
>> This line is normally aligned to the second ( on the line above.
>
> Yes, thanks.
This line gets joined into a single line in version 3, so I will leave
the bad formatting in patch 12 to make my life easier when moving
to version 3.
>>
>>> + /* expensive full path name compare */
>>> + fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
>>> + fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
>>> + name_match = !strcmp(fn_1, fn_2);
>>> + kfree(fn_1);
>>> + kfree(fn_2);
>>> + if (name_match) {
>>> + pr_err("ERROR: multiple overlay fragments add and/or delete node %pOF\n",
>>> + ce_1->np);
>>> + return -EINVAL;
>>> + }
>>> + }
>>> + }
>>> + }
>>> + }
>>> + }
>>> +
>>> + return 0;
>>> +}
>>
>> Style trivia:
>>
>> Using inverted tests and continue would reduce indentation.
>
> Yes, thanks.
In version 3, fixed in patch 13/18 instead of 12/18, where this pattern
has been split into two functions.
-Frank
>
> -Frank
>
>
>>
>> list_for_each_entry(ce_1, &ovcs->cset.entries, node) {
>> if (ce_1->action != OF_RECONFIG_ATTACH_NODE &&
>> ce_1->action != OF_RECONFIG_DETACH_NODE)
>> continue;
>>
>> ce_2 = ce_1;
>> list_for_each_entry_continue(ce_2, &ovcs->cset.entries, node) {
>> if (ce_2->action != OF_RECONFIG_ATTACH_NODE &&
>> ce_2->action != OF_RECONFIG_DETACH_NODE)
>> continue;
>>
>> /* inexpensive name compare */
>> if (of_node_cmp(ce_1->np->full_name, ce_2->np->full_name))
>> continue;
>>
>> /* expensive full path name compare */
>> fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
>> fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
>> name_match = !strcmp(fn_1, fn_2);
>> kfree(fn_1);
>> kfree(fn_2);
>> if (name_match) {
>> pr_err("ERROR: multiple overlay fragments add and/or delete node %pOF\n",
>> ce_1->np);
>> return -EINVAL;
>> }
>> }
>> }
>>
>>
>>
>
>
^ permalink raw reply
* Re: [PATCH 2/2] powerpc/pseries: Add driver for PAPR SCM regions
From: Michael Ellerman @ 2018-10-15 0:55 UTC (permalink / raw)
To: Dan Williams
Cc: Nathan Fontenot, Oliver O'Halloran, linuxppc-dev,
linux-nvdimm
In-Reply-To: <CAPcyv4h0b9jmrizygCEOU8GGMj-5yxz+vgEyVmVq+KNAozs+rA@mail.gmail.com>
Dan Williams <dan.j.williams@intel.com> writes:
> On Sat, Oct 13, 2018 at 5:08 AM Michael Ellerman <mpe@ellerman.id.au> wrote:
>>
>> Dan Williams <dan.j.williams@intel.com> writes:
>> > On Tue, Oct 9, 2018 at 11:21 PM Oliver O'Halloran <oohall@gmail.com> wrote:
>> >>
>> >> Adds a driver that implements support for enabling and accessing PAPR
>> >> SCM regions. Unfortunately due to how the PAPR interface works we can't
>> >> use the existing of_pmem driver (yet) because:
>> >>
>> ...
>> >> +
>> >> +static int papr_scm_nvdimm_init(struct papr_scm_priv *p)
>> >> +{
>> >> + struct device *dev = &p->pdev->dev;
>> >> + struct nd_mapping_desc mapping;
>> >> + struct nd_region_desc ndr_desc;
>> >> + unsigned long dimm_flags;
>> >> +
>> >> + p->bus_desc.ndctl = papr_scm_ndctl;
>> >> + p->bus_desc.module = THIS_MODULE;
>> >> + p->bus_desc.of_node = p->pdev->dev.of_node;
>> >> + p->bus_desc.attr_groups = bus_attr_groups;
>> >> + p->bus_desc.provider_name = kstrdup(p->pdev->name, GFP_KERNEL);
>> >> +
>> >> + if (!p->bus_desc.provider_name)
>> >> + return -ENOMEM;
>> >> +
>> >> + p->bus = nvdimm_bus_register(NULL, &p->bus_desc);
>> >> + if (!p->bus) {
>> >> + dev_err(dev, "Error creating nvdimm bus %pOF\n", p->dn);
>> >> + return -ENXIO;
>> >> + }
>> >> +
>> >> + dimm_flags = 0;
>> >> + set_bit(NDD_ALIASING, &dimm_flags);
>> >> +
>> >> + p->nvdimm = nvdimm_create(p->bus, p, papr_scm_dimm_groups,
>> >> + dimm_flags, PAPR_SCM_DIMM_CMD_MASK, 0, NULL);
>> >
>> > Looks good, although I'm just about to push out commits that change
>> > this function signature to take a 'security_ops' pointer. If you need
>> > a stable branch to base this on, let me know.
>> ...
>> >
>> > Other than that looks ok to me:
>> >
>> > Acked-by: Dan Williams <dan.j.williams@intel.com>
>> >
>> > ...just the matter of what to do about function signature change.
>>
>> Yeah that's a bit of a bother.
>>
>> The ideal for me would be that you put the commit that changes the
>> signature by itself in a branch based on 4.19-rc3 (or earlier), and then
>> we could both just merge that.
>>
>> But not sure if that will work with whatever else you're trying to sync
>> up with.
>
> How about this, I'll move the new signature to an 'advanced':
>
> __nvdimm_create()
>
> ...and make the existing:
>
> nvdimm_create()
>
> ...a simple wrapper around the new functionality. That way no matter
> what merge order we should be ok.
Yep that's much easier, thanks.
cheers
^ permalink raw reply
* Re: [PATCH v3 13/18] of: overlay: check prevents multiple fragments touching same property
From: Joe Perches @ 2018-10-15 1:06 UTC (permalink / raw)
To: frowand.list, Rob Herring, Pantelis Antoniou, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Alan Tull, Moritz Fischer
Cc: devicetree, linux-fpga, linuxppc-dev, linux-kernel
In-Reply-To: <1539563070-12969-14-git-send-email-frowand.list@gmail.com>
On Sun, 2018-10-14 at 17:24 -0700, frowand.list@gmail.com wrote:
> From: Frank Rowand <frank.rowand@sony.com>
>
> Add test case of two fragments updating the same property. After
> adding the test case, the system hangs at end of boot, after
> after slub stack dumps from kfree() in crypto modprobe code.
[]
> -static int check_changeset_dup_add_node(struct overlay_changeset *ovcs)
> +static int changeset_dup_entry_check(struct overlay_changeset *ovcs)
> {
> - struct of_changeset_entry *ce_1, *ce_2;
> - char *fn_1, *fn_2;
> - int name_match;
> + struct of_changeset_entry *ce_1;
> + int dup_entry = 0;
>
> list_for_each_entry(ce_1, &ovcs->cset.entries, node) {
> -
> - if (ce_1->action == OF_RECONFIG_ATTACH_NODE ||
> - ce_1->action == OF_RECONFIG_DETACH_NODE) {
> -
> - ce_2 = ce_1;
> - list_for_each_entry_continue(ce_2, &ovcs->cset.entries, node) {
> - if (ce_2->action == OF_RECONFIG_ATTACH_NODE ||
> - ce_2->action == OF_RECONFIG_DETACH_NODE) {
> - /* inexpensive name compare */
> - if (!of_node_cmp(ce_1->np->full_name,
> - ce_2->np->full_name)) {
> - /* expensive full path name compare */
> - fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
> - fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
> - name_match = !strcmp(fn_1, fn_2);
> - kfree(fn_1);
> - kfree(fn_2);
> - if (name_match) {
> - pr_err("ERROR: multiple overlay fragments add and/or delete node %pOF\n",
> - ce_1->np);
> - return -EINVAL;
> - }
> - }
> - }
> - }
> - }
> + dup_entry |= find_dup_cset_node_entry(ovcs, ce_1);
> + dup_entry |= find_dup_cset_prop(ovcs, ce_1);
I think this is worse performance than before.
This now walks all entries when before it would
return -EINVAL directly when it found a match.
^ permalink raw reply
* Re: [PATCH 16/33] powerpc/powernv: remove dead npu-dma code
From: Alexey Kardashevskiy @ 2018-10-15 1:34 UTC (permalink / raw)
To: Christoph Hellwig, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman
Cc: linux-arch, linux-mm, iommu, linuxppc-dev, linux-kernel
In-Reply-To: <20181009132500.17643-17-hch@lst.de>
On 10/10/2018 00:24, Christoph Hellwig wrote:
> This code has been unused since it was merged and is in the way of
> cleaning up the DMA code, thus remove it.
>
> This effectively reverts commit 5d2aa710 ("powerpc/powernv: Add support
> for Nvlink NPUs").
This code is heavily used by the NVIDIA GPU driver.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/powerpc/include/asm/pci.h | 3 -
> arch/powerpc/include/asm/powernv.h | 23 -
> arch/powerpc/platforms/powernv/Makefile | 2 +-
> arch/powerpc/platforms/powernv/npu-dma.c | 999 ----------------------
> arch/powerpc/platforms/powernv/pci-ioda.c | 243 ------
> arch/powerpc/platforms/powernv/pci.h | 11 -
> 6 files changed, 1 insertion(+), 1280 deletions(-)
> delete mode 100644 arch/powerpc/platforms/powernv/npu-dma.c
>
> diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
> index 2af9ded80540..a01d2e3d6ff9 100644
> --- a/arch/powerpc/include/asm/pci.h
> +++ b/arch/powerpc/include/asm/pci.h
> @@ -127,7 +127,4 @@ extern void pcibios_scan_phb(struct pci_controller *hose);
>
> #endif /* __KERNEL__ */
>
> -extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev);
> -extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
> -
> #endif /* __ASM_POWERPC_PCI_H */
> diff --git a/arch/powerpc/include/asm/powernv.h b/arch/powerpc/include/asm/powernv.h
> index 2f3ff7a27881..4848a6b3c6b2 100644
> --- a/arch/powerpc/include/asm/powernv.h
> +++ b/arch/powerpc/include/asm/powernv.h
> @@ -11,33 +11,10 @@
> #define _ASM_POWERNV_H
>
> #ifdef CONFIG_PPC_POWERNV
> -#define NPU2_WRITE 1
> extern void powernv_set_nmmu_ptcr(unsigned long ptcr);
> -extern struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
> - unsigned long flags,
> - void (*cb)(struct npu_context *, void *),
> - void *priv);
> -extern void pnv_npu2_destroy_context(struct npu_context *context,
> - struct pci_dev *gpdev);
> -extern int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
> - unsigned long *flags, unsigned long *status,
> - int count);
> -
> void pnv_tm_init(void);
> #else
> static inline void powernv_set_nmmu_ptcr(unsigned long ptcr) { }
> -static inline struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
> - unsigned long flags,
> - struct npu_context *(*cb)(struct npu_context *, void *),
> - void *priv) { return ERR_PTR(-ENODEV); }
> -static inline void pnv_npu2_destroy_context(struct npu_context *context,
> - struct pci_dev *gpdev) { }
> -
> -static inline int pnv_npu2_handle_fault(struct npu_context *context,
> - uintptr_t *ea, unsigned long *flags,
> - unsigned long *status, int count) {
> - return -ENODEV;
> -}
>
> static inline void pnv_tm_init(void) { }
> static inline void pnv_power9_force_smt4(void) { }
> diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
> index b540ce8eec55..2b13e9dd137c 100644
> --- a/arch/powerpc/platforms/powernv/Makefile
> +++ b/arch/powerpc/platforms/powernv/Makefile
> @@ -6,7 +6,7 @@ obj-y += opal-msglog.o opal-hmi.o opal-power.o opal-irqchip.o
> obj-y += opal-kmsg.o opal-powercap.o opal-psr.o opal-sensor-groups.o
>
> obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o
> -obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o pci-ioda-tce.o
> +obj-$(CONFIG_PCI) += pci.o pci-ioda.o pci-ioda-tce.o
> obj-$(CONFIG_CXL_BASE) += pci-cxl.o
> obj-$(CONFIG_EEH) += eeh-powernv.o
> obj-$(CONFIG_PPC_SCOM) += opal-xscom.o
> diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c
> deleted file mode 100644
> index 8006c54a91e3..000000000000
> --- a/arch/powerpc/platforms/powernv/npu-dma.c
> +++ /dev/null
> @@ -1,999 +0,0 @@
> -/*
> - * This file implements the DMA operations for NVLink devices. The NPU
> - * devices all point to the same iommu table as the parent PCI device.
> - *
> - * Copyright Alistair Popple, IBM Corporation 2015.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of version 2 of the GNU General Public
> - * License as published by the Free Software Foundation.
> - */
> -
> -#include <linux/slab.h>
> -#include <linux/mmu_notifier.h>
> -#include <linux/mmu_context.h>
> -#include <linux/of.h>
> -#include <linux/export.h>
> -#include <linux/pci.h>
> -#include <linux/memblock.h>
> -#include <linux/iommu.h>
> -#include <linux/debugfs.h>
> -
> -#include <asm/debugfs.h>
> -#include <asm/tlb.h>
> -#include <asm/powernv.h>
> -#include <asm/reg.h>
> -#include <asm/opal.h>
> -#include <asm/io.h>
> -#include <asm/iommu.h>
> -#include <asm/pnv-pci.h>
> -#include <asm/msi_bitmap.h>
> -#include <asm/opal.h>
> -
> -#include "powernv.h"
> -#include "pci.h"
> -
> -#define npu_to_phb(x) container_of(x, struct pnv_phb, npu)
> -
> -/*
> - * spinlock to protect initialisation of an npu_context for a particular
> - * mm_struct.
> - */
> -static DEFINE_SPINLOCK(npu_context_lock);
> -
> -/*
> - * When an address shootdown range exceeds this threshold we invalidate the
> - * entire TLB on the GPU for the given PID rather than each specific address in
> - * the range.
> - */
> -static uint64_t atsd_threshold = 2 * 1024 * 1024;
> -static struct dentry *atsd_threshold_dentry;
> -
> -/*
> - * Other types of TCE cache invalidation are not functional in the
> - * hardware.
> - */
> -static struct pci_dev *get_pci_dev(struct device_node *dn)
> -{
> - struct pci_dn *pdn = PCI_DN(dn);
> -
> - return pci_get_domain_bus_and_slot(pci_domain_nr(pdn->phb->bus),
> - pdn->busno, pdn->devfn);
> -}
> -
> -/* Given a NPU device get the associated PCI device. */
> -struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev)
> -{
> - struct device_node *dn;
> - struct pci_dev *gpdev;
> -
> - if (WARN_ON(!npdev))
> - return NULL;
> -
> - if (WARN_ON(!npdev->dev.of_node))
> - return NULL;
> -
> - /* Get assoicated PCI device */
> - dn = of_parse_phandle(npdev->dev.of_node, "ibm,gpu", 0);
> - if (!dn)
> - return NULL;
> -
> - gpdev = get_pci_dev(dn);
> - of_node_put(dn);
> -
> - return gpdev;
> -}
> -EXPORT_SYMBOL(pnv_pci_get_gpu_dev);
> -
> -/* Given the real PCI device get a linked NPU device. */
> -struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index)
> -{
> - struct device_node *dn;
> - struct pci_dev *npdev;
> -
> - if (WARN_ON(!gpdev))
> - return NULL;
> -
> - /* Not all PCI devices have device-tree nodes */
> - if (!gpdev->dev.of_node)
> - return NULL;
> -
> - /* Get assoicated PCI device */
> - dn = of_parse_phandle(gpdev->dev.of_node, "ibm,npu", index);
> - if (!dn)
> - return NULL;
> -
> - npdev = get_pci_dev(dn);
> - of_node_put(dn);
> -
> - return npdev;
> -}
> -EXPORT_SYMBOL(pnv_pci_get_npu_dev);
> -
> -#define NPU_DMA_OP_UNSUPPORTED() \
> - dev_err_once(dev, "%s operation unsupported for NVLink devices\n", \
> - __func__)
> -
> -static void *dma_npu_alloc(struct device *dev, size_t size,
> - dma_addr_t *dma_handle, gfp_t flag,
> - unsigned long attrs)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> - return NULL;
> -}
> -
> -static void dma_npu_free(struct device *dev, size_t size,
> - void *vaddr, dma_addr_t dma_handle,
> - unsigned long attrs)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> -}
> -
> -static dma_addr_t dma_npu_map_page(struct device *dev, struct page *page,
> - unsigned long offset, size_t size,
> - enum dma_data_direction direction,
> - unsigned long attrs)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> - return 0;
> -}
> -
> -static int dma_npu_map_sg(struct device *dev, struct scatterlist *sglist,
> - int nelems, enum dma_data_direction direction,
> - unsigned long attrs)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> - return 0;
> -}
> -
> -static int dma_npu_dma_supported(struct device *dev, u64 mask)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> - return 0;
> -}
> -
> -static u64 dma_npu_get_required_mask(struct device *dev)
> -{
> - NPU_DMA_OP_UNSUPPORTED();
> - return 0;
> -}
> -
> -static const struct dma_map_ops dma_npu_ops = {
> - .map_page = dma_npu_map_page,
> - .map_sg = dma_npu_map_sg,
> - .alloc = dma_npu_alloc,
> - .free = dma_npu_free,
> - .dma_supported = dma_npu_dma_supported,
> - .get_required_mask = dma_npu_get_required_mask,
> -};
> -
> -/*
> - * Returns the PE assoicated with the PCI device of the given
> - * NPU. Returns the linked pci device if pci_dev != NULL.
> - */
> -static struct pnv_ioda_pe *get_gpu_pci_dev_and_pe(struct pnv_ioda_pe *npe,
> - struct pci_dev **gpdev)
> -{
> - struct pnv_phb *phb;
> - struct pci_controller *hose;
> - struct pci_dev *pdev;
> - struct pnv_ioda_pe *pe;
> - struct pci_dn *pdn;
> -
> - pdev = pnv_pci_get_gpu_dev(npe->pdev);
> - if (!pdev)
> - return NULL;
> -
> - pdn = pci_get_pdn(pdev);
> - if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
> - return NULL;
> -
> - hose = pci_bus_to_host(pdev->bus);
> - phb = hose->private_data;
> - pe = &phb->ioda.pe_array[pdn->pe_number];
> -
> - if (gpdev)
> - *gpdev = pdev;
> -
> - return pe;
> -}
> -
> -long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> - struct iommu_table *tbl)
> -{
> - struct pnv_phb *phb = npe->phb;
> - int64_t rc;
> - const unsigned long size = tbl->it_indirect_levels ?
> - tbl->it_level_size : tbl->it_size;
> - const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
> - const __u64 win_size = tbl->it_size << tbl->it_page_shift;
> -
> - pe_info(npe, "Setting up window %llx..%llx pg=%lx\n",
> - start_addr, start_addr + win_size - 1,
> - IOMMU_PAGE_SIZE(tbl));
> -
> - rc = opal_pci_map_pe_dma_window(phb->opal_id,
> - npe->pe_number,
> - npe->pe_number,
> - tbl->it_indirect_levels + 1,
> - __pa(tbl->it_base),
> - size << 3,
> - IOMMU_PAGE_SIZE(tbl));
> - if (rc) {
> - pe_err(npe, "Failed to configure TCE table, err %lld\n", rc);
> - return rc;
> - }
> - pnv_pci_ioda2_tce_invalidate_entire(phb, false);
> -
> - /* Add the table to the list so its TCE cache will get invalidated */
> - pnv_pci_link_table_and_group(phb->hose->node, num,
> - tbl, &npe->table_group);
> -
> - return 0;
> -}
> -
> -long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num)
> -{
> - struct pnv_phb *phb = npe->phb;
> - int64_t rc;
> -
> - pe_info(npe, "Removing DMA window\n");
> -
> - rc = opal_pci_map_pe_dma_window(phb->opal_id, npe->pe_number,
> - npe->pe_number,
> - 0/* levels */, 0/* table address */,
> - 0/* table size */, 0/* page size */);
> - if (rc) {
> - pe_err(npe, "Unmapping failed, ret = %lld\n", rc);
> - return rc;
> - }
> - pnv_pci_ioda2_tce_invalidate_entire(phb, false);
> -
> - pnv_pci_unlink_table_and_group(npe->table_group.tables[num],
> - &npe->table_group);
> -
> - return 0;
> -}
> -
> -/*
> - * Enables 32 bit DMA on NPU.
> - */
> -static void pnv_npu_dma_set_32(struct pnv_ioda_pe *npe)
> -{
> - struct pci_dev *gpdev;
> - struct pnv_ioda_pe *gpe;
> - int64_t rc;
> -
> - /*
> - * Find the assoicated PCI devices and get the dma window
> - * information from there.
> - */
> - if (!npe->pdev || !(npe->flags & PNV_IODA_PE_DEV))
> - return;
> -
> - gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
> - if (!gpe)
> - return;
> -
> - rc = pnv_npu_set_window(npe, 0, gpe->table_group.tables[0]);
> -
> - /*
> - * We don't initialise npu_pe->tce32_table as we always use
> - * dma_npu_ops which are nops.
> - */
> - set_dma_ops(&npe->pdev->dev, &dma_npu_ops);
> -}
> -
> -/*
> - * Enables bypass mode on the NPU. The NPU only supports one
> - * window per link, so bypass needs to be explicitly enabled or
> - * disabled. Unlike for a PHB3 bypass and non-bypass modes can't be
> - * active at the same time.
> - */
> -static int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe)
> -{
> - struct pnv_phb *phb = npe->phb;
> - int64_t rc = 0;
> - phys_addr_t top = memblock_end_of_DRAM();
> -
> - if (phb->type != PNV_PHB_NPU_NVLINK || !npe->pdev)
> - return -EINVAL;
> -
> - rc = pnv_npu_unset_window(npe, 0);
> - if (rc != OPAL_SUCCESS)
> - return rc;
> -
> - /* Enable the bypass window */
> -
> - top = roundup_pow_of_two(top);
> - dev_info(&npe->pdev->dev, "Enabling bypass for PE %x\n",
> - npe->pe_number);
> - rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
> - npe->pe_number, npe->pe_number,
> - 0 /* bypass base */, top);
> -
> - if (rc == OPAL_SUCCESS)
> - pnv_pci_ioda2_tce_invalidate_entire(phb, false);
> -
> - return rc;
> -}
> -
> -void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass)
> -{
> - int i;
> - struct pnv_phb *phb;
> - struct pci_dn *pdn;
> - struct pnv_ioda_pe *npe;
> - struct pci_dev *npdev;
> -
> - for (i = 0; ; ++i) {
> - npdev = pnv_pci_get_npu_dev(gpdev, i);
> -
> - if (!npdev)
> - break;
> -
> - pdn = pci_get_pdn(npdev);
> - if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
> - return;
> -
> - phb = pci_bus_to_host(npdev->bus)->private_data;
> -
> - /* We only do bypass if it's enabled on the linked device */
> - npe = &phb->ioda.pe_array[pdn->pe_number];
> -
> - if (bypass) {
> - dev_info(&npdev->dev,
> - "Using 64-bit DMA iommu bypass\n");
> - pnv_npu_dma_set_bypass(npe);
> - } else {
> - dev_info(&npdev->dev, "Using 32-bit DMA via iommu\n");
> - pnv_npu_dma_set_32(npe);
> - }
> - }
> -}
> -
> -/* Switch ownership from platform code to external user (e.g. VFIO) */
> -void pnv_npu_take_ownership(struct pnv_ioda_pe *npe)
> -{
> - struct pnv_phb *phb = npe->phb;
> - int64_t rc;
> -
> - /*
> - * Note: NPU has just a single TVE in the hardware which means that
> - * while used by the kernel, it can have either 32bit window or
> - * DMA bypass but never both. So we deconfigure 32bit window only
> - * if it was enabled at the moment of ownership change.
> - */
> - if (npe->table_group.tables[0]) {
> - pnv_npu_unset_window(npe, 0);
> - return;
> - }
> -
> - /* Disable bypass */
> - rc = opal_pci_map_pe_dma_window_real(phb->opal_id,
> - npe->pe_number, npe->pe_number,
> - 0 /* bypass base */, 0);
> - if (rc) {
> - pe_err(npe, "Failed to disable bypass, err %lld\n", rc);
> - return;
> - }
> - pnv_pci_ioda2_tce_invalidate_entire(npe->phb, false);
> -}
> -
> -struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe)
> -{
> - struct pnv_phb *phb = npe->phb;
> - struct pci_bus *pbus = phb->hose->bus;
> - struct pci_dev *npdev, *gpdev = NULL, *gptmp;
> - struct pnv_ioda_pe *gpe = get_gpu_pci_dev_and_pe(npe, &gpdev);
> -
> - if (!gpe || !gpdev)
> - return NULL;
> -
> - list_for_each_entry(npdev, &pbus->devices, bus_list) {
> - gptmp = pnv_pci_get_gpu_dev(npdev);
> -
> - if (gptmp != gpdev)
> - continue;
> -
> - pe_info(gpe, "Attached NPU %s\n", dev_name(&npdev->dev));
> - iommu_group_add_device(gpe->table_group.group, &npdev->dev);
> - }
> -
> - return gpe;
> -}
> -
> -/* Maximum number of nvlinks per npu */
> -#define NV_MAX_LINKS 6
> -
> -/* Maximum index of npu2 hosts in the system. Always < NV_MAX_NPUS */
> -static int max_npu2_index;
> -
> -struct npu_context {
> - struct mm_struct *mm;
> - struct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];
> - struct mmu_notifier mn;
> - struct kref kref;
> - bool nmmu_flush;
> -
> - /* Callback to stop translation requests on a given GPU */
> - void (*release_cb)(struct npu_context *context, void *priv);
> -
> - /*
> - * Private pointer passed to the above callback for usage by
> - * device drivers.
> - */
> - void *priv;
> -};
> -
> -struct mmio_atsd_reg {
> - struct npu *npu;
> - int reg;
> -};
> -
> -/*
> - * Find a free MMIO ATSD register and mark it in use. Return -ENOSPC
> - * if none are available.
> - */
> -static int get_mmio_atsd_reg(struct npu *npu)
> -{
> - int i;
> -
> - for (i = 0; i < npu->mmio_atsd_count; i++) {
> - if (!test_bit(i, &npu->mmio_atsd_usage))
> - if (!test_and_set_bit_lock(i, &npu->mmio_atsd_usage))
> - return i;
> - }
> -
> - return -ENOSPC;
> -}
> -
> -static void put_mmio_atsd_reg(struct npu *npu, int reg)
> -{
> - clear_bit_unlock(reg, &npu->mmio_atsd_usage);
> -}
> -
> -/* MMIO ATSD register offsets */
> -#define XTS_ATSD_AVA 1
> -#define XTS_ATSD_STAT 2
> -
> -static void mmio_launch_invalidate(struct mmio_atsd_reg *mmio_atsd_reg,
> - unsigned long launch, unsigned long va)
> -{
> - struct npu *npu = mmio_atsd_reg->npu;
> - int reg = mmio_atsd_reg->reg;
> -
> - __raw_writeq_be(va, npu->mmio_atsd_regs[reg] + XTS_ATSD_AVA);
> - eieio();
> - __raw_writeq_be(launch, npu->mmio_atsd_regs[reg]);
> -}
> -
> -static void mmio_invalidate_pid(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
> - unsigned long pid, bool flush)
> -{
> - int i;
> - unsigned long launch;
> -
> - for (i = 0; i <= max_npu2_index; i++) {
> - if (mmio_atsd_reg[i].reg < 0)
> - continue;
> -
> - /* IS set to invalidate matching PID */
> - launch = PPC_BIT(12);
> -
> - /* PRS set to process-scoped */
> - launch |= PPC_BIT(13);
> -
> - /* AP */
> - launch |= (u64)
> - mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
> -
> - /* PID */
> - launch |= pid << PPC_BITLSHIFT(38);
> -
> - /* No flush */
> - launch |= !flush << PPC_BITLSHIFT(39);
> -
> - /* Invalidating the entire process doesn't use a va */
> - mmio_launch_invalidate(&mmio_atsd_reg[i], launch, 0);
> - }
> -}
> -
> -static void mmio_invalidate_va(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS],
> - unsigned long va, unsigned long pid, bool flush)
> -{
> - int i;
> - unsigned long launch;
> -
> - for (i = 0; i <= max_npu2_index; i++) {
> - if (mmio_atsd_reg[i].reg < 0)
> - continue;
> -
> - /* IS set to invalidate target VA */
> - launch = 0;
> -
> - /* PRS set to process scoped */
> - launch |= PPC_BIT(13);
> -
> - /* AP */
> - launch |= (u64)
> - mmu_get_ap(mmu_virtual_psize) << PPC_BITLSHIFT(17);
> -
> - /* PID */
> - launch |= pid << PPC_BITLSHIFT(38);
> -
> - /* No flush */
> - launch |= !flush << PPC_BITLSHIFT(39);
> -
> - mmio_launch_invalidate(&mmio_atsd_reg[i], launch, va);
> - }
> -}
> -
> -#define mn_to_npu_context(x) container_of(x, struct npu_context, mn)
> -
> -static void mmio_invalidate_wait(
> - struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
> -{
> - struct npu *npu;
> - int i, reg;
> -
> - /* Wait for all invalidations to complete */
> - for (i = 0; i <= max_npu2_index; i++) {
> - if (mmio_atsd_reg[i].reg < 0)
> - continue;
> -
> - /* Wait for completion */
> - npu = mmio_atsd_reg[i].npu;
> - reg = mmio_atsd_reg[i].reg;
> - while (__raw_readq(npu->mmio_atsd_regs[reg] + XTS_ATSD_STAT))
> - cpu_relax();
> - }
> -}
> -
> -/*
> - * Acquires all the address translation shootdown (ATSD) registers required to
> - * launch an ATSD on all links this npu_context is active on.
> - */
> -static void acquire_atsd_reg(struct npu_context *npu_context,
> - struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
> -{
> - int i, j;
> - struct npu *npu;
> - struct pci_dev *npdev;
> - struct pnv_phb *nphb;
> -
> - for (i = 0; i <= max_npu2_index; i++) {
> - mmio_atsd_reg[i].reg = -1;
> - for (j = 0; j < NV_MAX_LINKS; j++) {
> - /*
> - * There are no ordering requirements with respect to
> - * the setup of struct npu_context, but to ensure
> - * consistent behaviour we need to ensure npdev[][] is
> - * only read once.
> - */
> - npdev = READ_ONCE(npu_context->npdev[i][j]);
> - if (!npdev)
> - continue;
> -
> - nphb = pci_bus_to_host(npdev->bus)->private_data;
> - npu = &nphb->npu;
> - mmio_atsd_reg[i].npu = npu;
> - mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
> - while (mmio_atsd_reg[i].reg < 0) {
> - mmio_atsd_reg[i].reg = get_mmio_atsd_reg(npu);
> - cpu_relax();
> - }
> - break;
> - }
> - }
> -}
> -
> -/*
> - * Release previously acquired ATSD registers. To avoid deadlocks the registers
> - * must be released in the same order they were acquired above in
> - * acquire_atsd_reg.
> - */
> -static void release_atsd_reg(struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS])
> -{
> - int i;
> -
> - for (i = 0; i <= max_npu2_index; i++) {
> - /*
> - * We can't rely on npu_context->npdev[][] being the same here
> - * as when acquire_atsd_reg() was called, hence we use the
> - * values stored in mmio_atsd_reg during the acquire phase
> - * rather than re-reading npdev[][].
> - */
> - if (mmio_atsd_reg[i].reg < 0)
> - continue;
> -
> - put_mmio_atsd_reg(mmio_atsd_reg[i].npu, mmio_atsd_reg[i].reg);
> - }
> -}
> -
> -/*
> - * Invalidate either a single address or an entire PID depending on
> - * the value of va.
> - */
> -static void mmio_invalidate(struct npu_context *npu_context, int va,
> - unsigned long address, bool flush)
> -{
> - struct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];
> - unsigned long pid = npu_context->mm->context.id;
> -
> - if (npu_context->nmmu_flush)
> - /*
> - * Unfortunately the nest mmu does not support flushing specific
> - * addresses so we have to flush the whole mm once before
> - * shooting down the GPU translation.
> - */
> - flush_all_mm(npu_context->mm);
> -
> - /*
> - * Loop over all the NPUs this process is active on and launch
> - * an invalidate.
> - */
> - acquire_atsd_reg(npu_context, mmio_atsd_reg);
> - if (va)
> - mmio_invalidate_va(mmio_atsd_reg, address, pid, flush);
> - else
> - mmio_invalidate_pid(mmio_atsd_reg, pid, flush);
> -
> - mmio_invalidate_wait(mmio_atsd_reg);
> - if (flush) {
> - /*
> - * The GPU requires two flush ATSDs to ensure all entries have
> - * been flushed. We use PID 0 as it will never be used for a
> - * process on the GPU.
> - */
> - mmio_invalidate_pid(mmio_atsd_reg, 0, true);
> - mmio_invalidate_wait(mmio_atsd_reg);
> - mmio_invalidate_pid(mmio_atsd_reg, 0, true);
> - mmio_invalidate_wait(mmio_atsd_reg);
> - }
> - release_atsd_reg(mmio_atsd_reg);
> -}
> -
> -static void pnv_npu2_mn_release(struct mmu_notifier *mn,
> - struct mm_struct *mm)
> -{
> - struct npu_context *npu_context = mn_to_npu_context(mn);
> -
> - /* Call into device driver to stop requests to the NMMU */
> - if (npu_context->release_cb)
> - npu_context->release_cb(npu_context, npu_context->priv);
> -
> - /*
> - * There should be no more translation requests for this PID, but we
> - * need to ensure any entries for it are removed from the TLB.
> - */
> - mmio_invalidate(npu_context, 0, 0, true);
> -}
> -
> -static void pnv_npu2_mn_change_pte(struct mmu_notifier *mn,
> - struct mm_struct *mm,
> - unsigned long address,
> - pte_t pte)
> -{
> - struct npu_context *npu_context = mn_to_npu_context(mn);
> -
> - mmio_invalidate(npu_context, 1, address, true);
> -}
> -
> -static void pnv_npu2_mn_invalidate_range(struct mmu_notifier *mn,
> - struct mm_struct *mm,
> - unsigned long start, unsigned long end)
> -{
> - struct npu_context *npu_context = mn_to_npu_context(mn);
> - unsigned long address;
> -
> - if (end - start > atsd_threshold) {
> - /*
> - * Just invalidate the entire PID if the address range is too
> - * large.
> - */
> - mmio_invalidate(npu_context, 0, 0, true);
> - } else {
> - for (address = start; address < end; address += PAGE_SIZE)
> - mmio_invalidate(npu_context, 1, address, false);
> -
> - /* Do the flush only on the final addess == end */
> - mmio_invalidate(npu_context, 1, address, true);
> - }
> -}
> -
> -static const struct mmu_notifier_ops nv_nmmu_notifier_ops = {
> - .release = pnv_npu2_mn_release,
> - .change_pte = pnv_npu2_mn_change_pte,
> - .invalidate_range = pnv_npu2_mn_invalidate_range,
> -};
> -
> -/*
> - * Call into OPAL to setup the nmmu context for the current task in
> - * the NPU. This must be called to setup the context tables before the
> - * GPU issues ATRs. pdev should be a pointed to PCIe GPU device.
> - *
> - * A release callback should be registered to allow a device driver to
> - * be notified that it should not launch any new translation requests
> - * as the final TLB invalidate is about to occur.
> - *
> - * Returns an error if there no contexts are currently available or a
> - * npu_context which should be passed to pnv_npu2_handle_fault().
> - *
> - * mmap_sem must be held in write mode and must not be called from interrupt
> - * context.
> - */
> -struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,
> - unsigned long flags,
> - void (*cb)(struct npu_context *, void *),
> - void *priv)
> -{
> - int rc;
> - u32 nvlink_index;
> - struct device_node *nvlink_dn;
> - struct mm_struct *mm = current->mm;
> - struct pnv_phb *nphb;
> - struct npu *npu;
> - struct npu_context *npu_context;
> -
> - /*
> - * At present we don't support GPUs connected to multiple NPUs and I'm
> - * not sure the hardware does either.
> - */
> - struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
> -
> - if (!firmware_has_feature(FW_FEATURE_OPAL))
> - return ERR_PTR(-ENODEV);
> -
> - if (!npdev)
> - /* No nvlink associated with this GPU device */
> - return ERR_PTR(-ENODEV);
> -
> - nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
> - if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
> - &nvlink_index)))
> - return ERR_PTR(-ENODEV);
> -
> - if (!mm || mm->context.id == 0) {
> - /*
> - * Kernel thread contexts are not supported and context id 0 is
> - * reserved on the GPU.
> - */
> - return ERR_PTR(-EINVAL);
> - }
> -
> - nphb = pci_bus_to_host(npdev->bus)->private_data;
> - npu = &nphb->npu;
> -
> - /*
> - * Setup the NPU context table for a particular GPU. These need to be
> - * per-GPU as we need the tables to filter ATSDs when there are no
> - * active contexts on a particular GPU. It is safe for these to be
> - * called concurrently with destroy as the OPAL call takes appropriate
> - * locks and refcounts on init/destroy.
> - */
> - rc = opal_npu_init_context(nphb->opal_id, mm->context.id, flags,
> - PCI_DEVID(gpdev->bus->number, gpdev->devfn));
> - if (rc < 0)
> - return ERR_PTR(-ENOSPC);
> -
> - /*
> - * We store the npu pci device so we can more easily get at the
> - * associated npus.
> - */
> - spin_lock(&npu_context_lock);
> - npu_context = mm->context.npu_context;
> - if (npu_context) {
> - if (npu_context->release_cb != cb ||
> - npu_context->priv != priv) {
> - spin_unlock(&npu_context_lock);
> - opal_npu_destroy_context(nphb->opal_id, mm->context.id,
> - PCI_DEVID(gpdev->bus->number,
> - gpdev->devfn));
> - return ERR_PTR(-EINVAL);
> - }
> -
> - WARN_ON(!kref_get_unless_zero(&npu_context->kref));
> - }
> - spin_unlock(&npu_context_lock);
> -
> - if (!npu_context) {
> - /*
> - * We can set up these fields without holding the
> - * npu_context_lock as the npu_context hasn't been returned to
> - * the caller meaning it can't be destroyed. Parallel allocation
> - * is protected against by mmap_sem.
> - */
> - rc = -ENOMEM;
> - npu_context = kzalloc(sizeof(struct npu_context), GFP_KERNEL);
> - if (npu_context) {
> - kref_init(&npu_context->kref);
> - npu_context->mm = mm;
> - npu_context->mn.ops = &nv_nmmu_notifier_ops;
> - rc = __mmu_notifier_register(&npu_context->mn, mm);
> - }
> -
> - if (rc) {
> - kfree(npu_context);
> - opal_npu_destroy_context(nphb->opal_id, mm->context.id,
> - PCI_DEVID(gpdev->bus->number,
> - gpdev->devfn));
> - return ERR_PTR(rc);
> - }
> -
> - mm->context.npu_context = npu_context;
> - }
> -
> - npu_context->release_cb = cb;
> - npu_context->priv = priv;
> -
> - /*
> - * npdev is a pci_dev pointer setup by the PCI code. We assign it to
> - * npdev[][] to indicate to the mmu notifiers that an invalidation
> - * should also be sent over this nvlink. The notifiers don't use any
> - * other fields in npu_context, so we just need to ensure that when they
> - * deference npu_context->npdev[][] it is either a valid pointer or
> - * NULL.
> - */
> - WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], npdev);
> -
> - if (!nphb->npu.nmmu_flush) {
> - /*
> - * If we're not explicitly flushing ourselves we need to mark
> - * the thread for global flushes
> - */
> - npu_context->nmmu_flush = false;
> - mm_context_add_copro(mm);
> - } else
> - npu_context->nmmu_flush = true;
> -
> - return npu_context;
> -}
> -EXPORT_SYMBOL(pnv_npu2_init_context);
> -
> -static void pnv_npu2_release_context(struct kref *kref)
> -{
> - struct npu_context *npu_context =
> - container_of(kref, struct npu_context, kref);
> -
> - if (!npu_context->nmmu_flush)
> - mm_context_remove_copro(npu_context->mm);
> -
> - npu_context->mm->context.npu_context = NULL;
> -}
> -
> -/*
> - * Destroy a context on the given GPU. May free the npu_context if it is no
> - * longer active on any GPUs. Must not be called from interrupt context.
> - */
> -void pnv_npu2_destroy_context(struct npu_context *npu_context,
> - struct pci_dev *gpdev)
> -{
> - int removed;
> - struct pnv_phb *nphb;
> - struct npu *npu;
> - struct pci_dev *npdev = pnv_pci_get_npu_dev(gpdev, 0);
> - struct device_node *nvlink_dn;
> - u32 nvlink_index;
> -
> - if (WARN_ON(!npdev))
> - return;
> -
> - if (!firmware_has_feature(FW_FEATURE_OPAL))
> - return;
> -
> - nphb = pci_bus_to_host(npdev->bus)->private_data;
> - npu = &nphb->npu;
> - nvlink_dn = of_parse_phandle(npdev->dev.of_node, "ibm,nvlink", 0);
> - if (WARN_ON(of_property_read_u32(nvlink_dn, "ibm,npu-link-index",
> - &nvlink_index)))
> - return;
> - WRITE_ONCE(npu_context->npdev[npu->index][nvlink_index], NULL);
> - opal_npu_destroy_context(nphb->opal_id, npu_context->mm->context.id,
> - PCI_DEVID(gpdev->bus->number, gpdev->devfn));
> - spin_lock(&npu_context_lock);
> - removed = kref_put(&npu_context->kref, pnv_npu2_release_context);
> - spin_unlock(&npu_context_lock);
> -
> - /*
> - * We need to do this outside of pnv_npu2_release_context so that it is
> - * outside the spinlock as mmu_notifier_destroy uses SRCU.
> - */
> - if (removed) {
> - mmu_notifier_unregister(&npu_context->mn,
> - npu_context->mm);
> -
> - kfree(npu_context);
> - }
> -
> -}
> -EXPORT_SYMBOL(pnv_npu2_destroy_context);
> -
> -/*
> - * Assumes mmap_sem is held for the contexts associated mm.
> - */
> -int pnv_npu2_handle_fault(struct npu_context *context, uintptr_t *ea,
> - unsigned long *flags, unsigned long *status, int count)
> -{
> - u64 rc = 0, result = 0;
> - int i, is_write;
> - struct page *page[1];
> -
> - /* mmap_sem should be held so the struct_mm must be present */
> - struct mm_struct *mm = context->mm;
> -
> - if (!firmware_has_feature(FW_FEATURE_OPAL))
> - return -ENODEV;
> -
> - WARN_ON(!rwsem_is_locked(&mm->mmap_sem));
> -
> - for (i = 0; i < count; i++) {
> - is_write = flags[i] & NPU2_WRITE;
> - rc = get_user_pages_remote(NULL, mm, ea[i], 1,
> - is_write ? FOLL_WRITE : 0,
> - page, NULL, NULL);
> -
> - /*
> - * To support virtualised environments we will have to do an
> - * access to the page to ensure it gets faulted into the
> - * hypervisor. For the moment virtualisation is not supported in
> - * other areas so leave the access out.
> - */
> - if (rc != 1) {
> - status[i] = rc;
> - result = -EFAULT;
> - continue;
> - }
> -
> - status[i] = 0;
> - put_page(page[0]);
> - }
> -
> - return result;
> -}
> -EXPORT_SYMBOL(pnv_npu2_handle_fault);
> -
> -int pnv_npu2_init(struct pnv_phb *phb)
> -{
> - unsigned int i;
> - u64 mmio_atsd;
> - struct device_node *dn;
> - struct pci_dev *gpdev;
> - static int npu_index;
> - uint64_t rc = 0;
> -
> - if (!atsd_threshold_dentry) {
> - atsd_threshold_dentry = debugfs_create_x64("atsd_threshold",
> - 0600, powerpc_debugfs_root, &atsd_threshold);
> - }
> -
> - phb->npu.nmmu_flush =
> - of_property_read_bool(phb->hose->dn, "ibm,nmmu-flush");
> - for_each_child_of_node(phb->hose->dn, dn) {
> - gpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));
> - if (gpdev) {
> - rc = opal_npu_map_lpar(phb->opal_id,
> - PCI_DEVID(gpdev->bus->number, gpdev->devfn),
> - 0, 0);
> - if (rc)
> - dev_err(&gpdev->dev,
> - "Error %lld mapping device to LPAR\n",
> - rc);
> - }
> - }
> -
> - for (i = 0; !of_property_read_u64_index(phb->hose->dn, "ibm,mmio-atsd",
> - i, &mmio_atsd); i++)
> - phb->npu.mmio_atsd_regs[i] = ioremap(mmio_atsd, 32);
> -
> - pr_info("NPU%lld: Found %d MMIO ATSD registers", phb->opal_id, i);
> - phb->npu.mmio_atsd_count = i;
> - phb->npu.mmio_atsd_usage = 0;
> - npu_index++;
> - if (WARN_ON(npu_index >= NV_MAX_NPUS))
> - return -ENOSPC;
> - max_npu2_index = npu_index;
> - phb->npu.index = npu_index;
> -
> - return 0;
> -}
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index 913175ba1c10..b6db65917bb4 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -1203,75 +1203,6 @@ static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
> return pe;
> }
>
> -static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
> -{
> - int pe_num, found_pe = false, rc;
> - long rid;
> - struct pnv_ioda_pe *pe;
> - struct pci_dev *gpu_pdev;
> - struct pci_dn *npu_pdn;
> - struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
> - struct pnv_phb *phb = hose->private_data;
> -
> - /*
> - * Due to a hardware errata PE#0 on the NPU is reserved for
> - * error handling. This means we only have three PEs remaining
> - * which need to be assigned to four links, implying some
> - * links must share PEs.
> - *
> - * To achieve this we assign PEs such that NPUs linking the
> - * same GPU get assigned the same PE.
> - */
> - gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
> - for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
> - pe = &phb->ioda.pe_array[pe_num];
> - if (!pe->pdev)
> - continue;
> -
> - if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
> - /*
> - * This device has the same peer GPU so should
> - * be assigned the same PE as the existing
> - * peer NPU.
> - */
> - dev_info(&npu_pdev->dev,
> - "Associating to existing PE %x\n", pe_num);
> - pci_dev_get(npu_pdev);
> - npu_pdn = pci_get_pdn(npu_pdev);
> - rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
> - npu_pdn->pe_number = pe_num;
> - phb->ioda.pe_rmap[rid] = pe->pe_number;
> -
> - /* Map the PE to this link */
> - rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
> - OpalPciBusAll,
> - OPAL_COMPARE_RID_DEVICE_NUMBER,
> - OPAL_COMPARE_RID_FUNCTION_NUMBER,
> - OPAL_MAP_PE);
> - WARN_ON(rc != OPAL_SUCCESS);
> - found_pe = true;
> - break;
> - }
> - }
> -
> - if (!found_pe)
> - /*
> - * Could not find an existing PE so allocate a new
> - * one.
> - */
> - return pnv_ioda_setup_dev_PE(npu_pdev);
> - else
> - return pe;
> -}
> -
> -static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
> -{
> - struct pci_dev *pdev;
> -
> - list_for_each_entry(pdev, &bus->devices, bus_list)
> - pnv_ioda_setup_npu_PE(pdev);
> -}
> -
> static void pnv_pci_ioda_setup_PEs(void)
> {
> struct pci_controller *hose, *tmp;
> @@ -1281,13 +1212,6 @@ static void pnv_pci_ioda_setup_PEs(void)
>
> list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
> phb = hose->private_data;
> - if (phb->type == PNV_PHB_NPU_NVLINK) {
> - /* PE#0 is needed for error reporting */
> - pnv_ioda_reserve_pe(phb, 0);
> - pnv_ioda_setup_npu_PEs(hose->bus);
> - if (phb->model == PNV_PHB_MODEL_NPU2)
> - pnv_npu2_init(phb);
> - }
> if (phb->type == PNV_PHB_NPU_OCAPI) {
> bus = hose->bus;
> list_for_each_entry(pdev, &bus->devices, bus_list)
> @@ -1871,9 +1795,6 @@ static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
> }
> *pdev->dev.dma_mask = dma_mask;
>
> - /* Update peer npu devices */
> - pnv_npu_try_dma_set_bypass(pdev, bypass);
> -
> return 0;
> }
>
> @@ -2119,14 +2040,6 @@ static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
> }
> }
>
> -void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
> -{
> - if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
> - pnv_pci_phb3_tce_invalidate_entire(phb, rm);
> - else
> - opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
> -}
> -
> static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
> long npages, unsigned long uaddr,
> enum dma_data_direction direction,
> @@ -2615,137 +2528,6 @@ static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
> .take_ownership = pnv_ioda2_take_ownership,
> .release_ownership = pnv_ioda2_release_ownership,
> };
> -
> -static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
> -{
> - struct pci_controller *hose;
> - struct pnv_phb *phb;
> - struct pnv_ioda_pe **ptmppe = opaque;
> - struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
> - struct pci_dn *pdn = pci_get_pdn(pdev);
> -
> - if (!pdn || pdn->pe_number == IODA_INVALID_PE)
> - return 0;
> -
> - hose = pci_bus_to_host(pdev->bus);
> - phb = hose->private_data;
> - if (phb->type != PNV_PHB_NPU_NVLINK)
> - return 0;
> -
> - *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
> -
> - return 1;
> -}
> -
> -/*
> - * This returns PE of associated NPU.
> - * This assumes that NPU is in the same IOMMU group with GPU and there is
> - * no other PEs.
> - */
> -static struct pnv_ioda_pe *gpe_table_group_to_npe(
> - struct iommu_table_group *table_group)
> -{
> - struct pnv_ioda_pe *npe = NULL;
> - int ret = iommu_group_for_each_dev(table_group->group, &npe,
> - gpe_table_group_to_npe_cb);
> -
> - BUG_ON(!ret || !npe);
> -
> - return npe;
> -}
> -
> -static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
> - int num, struct iommu_table *tbl)
> -{
> - struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
> - int num2 = (num == 0) ? 1 : 0;
> - long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
> -
> - if (ret)
> - return ret;
> -
> - if (table_group->tables[num2])
> - pnv_npu_unset_window(npe, num2);
> -
> - ret = pnv_npu_set_window(npe, num, tbl);
> - if (ret) {
> - pnv_pci_ioda2_unset_window(table_group, num);
> - if (table_group->tables[num2])
> - pnv_npu_set_window(npe, num2,
> - table_group->tables[num2]);
> - }
> -
> - return ret;
> -}
> -
> -static long pnv_pci_ioda2_npu_unset_window(
> - struct iommu_table_group *table_group,
> - int num)
> -{
> - struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
> - int num2 = (num == 0) ? 1 : 0;
> - long ret = pnv_pci_ioda2_unset_window(table_group, num);
> -
> - if (ret)
> - return ret;
> -
> - if (!npe->table_group.tables[num])
> - return 0;
> -
> - ret = pnv_npu_unset_window(npe, num);
> - if (ret)
> - return ret;
> -
> - if (table_group->tables[num2])
> - ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
> -
> - return ret;
> -}
> -
> -static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
> -{
> - /*
> - * Detach NPU first as pnv_ioda2_take_ownership() will destroy
> - * the iommu_table if 32bit DMA is enabled.
> - */
> - pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
> - pnv_ioda2_take_ownership(table_group);
> -}
> -
> -static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
> - .get_table_size = pnv_pci_ioda2_get_table_size,
> - .create_table = pnv_pci_ioda2_create_table_userspace,
> - .set_window = pnv_pci_ioda2_npu_set_window,
> - .unset_window = pnv_pci_ioda2_npu_unset_window,
> - .take_ownership = pnv_ioda2_npu_take_ownership,
> - .release_ownership = pnv_ioda2_release_ownership,
> -};
> -
> -static void pnv_pci_ioda_setup_iommu_api(void)
> -{
> - struct pci_controller *hose, *tmp;
> - struct pnv_phb *phb;
> - struct pnv_ioda_pe *pe, *gpe;
> -
> - /*
> - * Now we have all PHBs discovered, time to add NPU devices to
> - * the corresponding IOMMU groups.
> - */
> - list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
> - phb = hose->private_data;
> -
> - if (phb->type != PNV_PHB_NPU_NVLINK)
> - continue;
> -
> - list_for_each_entry(pe, &phb->ioda.pe_list, list) {
> - gpe = pnv_pci_npu_setup_iommu(pe);
> - if (gpe)
> - gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
> - }
> - }
> -}
> -#else /* !CONFIG_IOMMU_API */
> -static void pnv_pci_ioda_setup_iommu_api(void) { };
> #endif
>
> static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
> @@ -3242,7 +3024,6 @@ static void pnv_pci_enable_bridges(void)
> static void pnv_pci_ioda_fixup(void)
> {
> pnv_pci_ioda_setup_PEs();
> - pnv_pci_ioda_setup_iommu_api();
> pnv_pci_ioda_create_dbgfs();
>
> pnv_pci_enable_bridges();
> @@ -3689,27 +3470,6 @@ static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
> .shutdown = pnv_pci_ioda_shutdown,
> };
>
> -static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
> -{
> - dev_err_once(&npdev->dev,
> - "%s operation unsupported for NVLink devices\n",
> - __func__);
> - return -EPERM;
> -}
> -
> -static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
> - .dma_dev_setup = pnv_pci_dma_dev_setup,
> -#ifdef CONFIG_PCI_MSI
> - .setup_msi_irqs = pnv_setup_msi_irqs,
> - .teardown_msi_irqs = pnv_teardown_msi_irqs,
> -#endif
> - .enable_device_hook = pnv_pci_enable_device_hook,
> - .window_alignment = pnv_pci_window_alignment,
> - .reset_secondary_bus = pnv_pci_reset_secondary_bus,
> - .dma_set_mask = pnv_npu_dma_set_mask,
> - .shutdown = pnv_pci_ioda_shutdown,
> -};
> -
> static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
> .enable_device_hook = pnv_pci_enable_device_hook,
> .window_alignment = pnv_pci_window_alignment,
> @@ -3931,9 +3691,6 @@ static void __init pnv_pci_init_ioda_phb(struct device_node *np,
> ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
>
> switch (phb->type) {
> - case PNV_PHB_NPU_NVLINK:
> - hose->controller_ops = pnv_npu_ioda_controller_ops;
> - break;
> case PNV_PHB_NPU_OCAPI:
> hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
> break;
> diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
> index 8b37b28e3831..54f2935b7ac5 100644
> --- a/arch/powerpc/platforms/powernv/pci.h
> +++ b/arch/powerpc/platforms/powernv/pci.h
> @@ -231,17 +231,6 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
> #define pe_info(pe, fmt, ...) \
> pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
>
> -/* Nvlink functions */
> -extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
> -extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
> -extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
> -extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
> - struct iommu_table *tbl);
> -extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
> -extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
> -extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
> -extern int pnv_npu2_init(struct pnv_phb *phb);
> -
> /* pci-ioda-tce.c */
> #define POWERNV_IOMMU_DEFAULT_LEVELS 1
> #define POWERNV_IOMMU_MAX_LEVELS 5
>
--
Alexey
^ permalink raw reply
* Re: [PATCH v3 13/18] of: overlay: check prevents multiple fragments touching same property
From: Frank Rowand @ 2018-10-15 1:52 UTC (permalink / raw)
To: Joe Perches, Rob Herring, Pantelis Antoniou, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Alan Tull, Moritz Fischer
Cc: devicetree, linux-fpga, linuxppc-dev, linux-kernel
In-Reply-To: <b6ee53f7e02cc3ea52713ae82402e97d7050cb3e.camel@perches.com>
On 10/14/18 18:06, Joe Perches wrote:
> On Sun, 2018-10-14 at 17:24 -0700, frowand.list@gmail.com wrote:
>> From: Frank Rowand <frank.rowand@sony.com>
>>
>> Add test case of two fragments updating the same property. After
>> adding the test case, the system hangs at end of boot, after
>> after slub stack dumps from kfree() in crypto modprobe code.
> []
>> -static int check_changeset_dup_add_node(struct overlay_changeset *ovcs)
>> +static int changeset_dup_entry_check(struct overlay_changeset *ovcs)
>> {
>> - struct of_changeset_entry *ce_1, *ce_2;
>> - char *fn_1, *fn_2;
>> - int name_match;
>> + struct of_changeset_entry *ce_1;
>> + int dup_entry = 0;
>>
>> list_for_each_entry(ce_1, &ovcs->cset.entries, node) {
>> -
>> - if (ce_1->action == OF_RECONFIG_ATTACH_NODE ||
>> - ce_1->action == OF_RECONFIG_DETACH_NODE) {
>> -
>> - ce_2 = ce_1;
>> - list_for_each_entry_continue(ce_2, &ovcs->cset.entries, node) {
>> - if (ce_2->action == OF_RECONFIG_ATTACH_NODE ||
>> - ce_2->action == OF_RECONFIG_DETACH_NODE) {
>> - /* inexpensive name compare */
>> - if (!of_node_cmp(ce_1->np->full_name,
>> - ce_2->np->full_name)) {
>> - /* expensive full path name compare */
>> - fn_1 = kasprintf(GFP_KERNEL, "%pOF", ce_1->np);
>> - fn_2 = kasprintf(GFP_KERNEL, "%pOF", ce_2->np);
>> - name_match = !strcmp(fn_1, fn_2);
>> - kfree(fn_1);
>> - kfree(fn_2);
>> - if (name_match) {
>> - pr_err("ERROR: multiple overlay fragments add and/or delete node %pOF\n",
>> - ce_1->np);
>> - return -EINVAL;
>> - }
>> - }
>> - }
>> - }
>> - }
>> + dup_entry |= find_dup_cset_node_entry(ovcs, ce_1);
>> + dup_entry |= find_dup_cset_prop(ovcs, ce_1);
>
> I think this is worse performance than before.
>
> This now walks all entries when before it would
> return -EINVAL directly when it found a match.
Yes, it is worse performance, but that is OK.
This is a check that is done when a devicetree overlay is applied.
If an error occurs then that means that the overlay was incorrectly
specified. The file drivers/of/unittest-data/overlay_bad_add_dup_prop.dts
in this patch provides an example of how a bad overlay can be created.
Once an error was detected, the check could return immediately, or it
could continue to give a complete list of detected errors. I chose to
give the complete list of detected errors.
-Frank
^ permalink raw reply
* Re: [PATCH v3 13/18] of: overlay: check prevents multiple fragments touching same property
From: Joe Perches @ 2018-10-15 1:55 UTC (permalink / raw)
To: Frank Rowand, Rob Herring, Pantelis Antoniou, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Alan Tull, Moritz Fischer
Cc: devicetree, linux-fpga, linuxppc-dev, linux-kernel
In-Reply-To: <850f0866-1189-5a49-01c5-79caf270abbd@gmail.com>
On Sun, 2018-10-14 at 18:52 -0700, Frank Rowand wrote:
> On 10/14/18 18:06, Joe Perches wrote:
> > On Sun, 2018-10-14 at 17:24 -0700, frowand.list@gmail.com wrote:
> > > From: Frank Rowand <frank.rowand@sony.com>
> > >
> > > Add test case of two fragments updating the same property. After
> > > adding the test case, the system hangs at end of boot, after
> > > after slub stack dumps from kfree() in crypto modprobe code.
[]
> > I think this is worse performance than before.
> >
> > This now walks all entries when before it would
> > return -EINVAL directly when it found a match.
>
> Yes, it is worse performance, but that is OK.
>
> This is a check that is done when a devicetree overlay is applied.
> If an error occurs then that means that the overlay was incorrectly
> specified. The file drivers/of/unittest-data/overlay_bad_add_dup_prop.dts
> in this patch provides an example of how a bad overlay can be created.
>
> Once an error was detected, the check could return immediately, or it
> could continue to give a complete list of detected errors. I chose to
> give the complete list of detected errors.
Swell. Please describe that in the commit message.
^ permalink raw reply
* [PATCH] powerpc/xmon: Show the stack protector canary in xmon
From: Michael Ellerman @ 2018-10-15 2:23 UTC (permalink / raw)
To: linuxppc-dev
This is helpful for debugging stack protector crashes.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
arch/powerpc/xmon/xmon.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index c70d17c9a6ba..d139741f26fe 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2418,6 +2418,9 @@ static void dump_one_paca(int cpu)
DUMP(p, __current, "%-*px");
DUMP(p, kstack, "%#-*llx");
printf(" %-*s = 0x%016llx\n", 25, "kstack_base", p->kstack & ~(THREAD_SIZE - 1));
+#ifdef CONFIG_STACKPROTECTOR
+ DUMP(p, canary, "%#-*lx");
+#endif
DUMP(p, saved_r1, "%#-*llx");
DUMP(p, trap_save, "%#-*x");
DUMP(p, irq_soft_mask, "%#-*x");
--
2.17.1
^ permalink raw reply related
* RE: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support
From: Vabhav Sharma @ 2018-10-15 2:44 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland@arm.com, kstewart@linuxfoundation.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
mturquette@baylibre.com, will.deacon@arm.com,
yamada.masahiro@socionext.com, Sriram Dash,
linux-clk@vger.kernel.org, Pankaj Bansal, Udit Kumar,
linux@armlinux.org.uk, Priyanka Jain, viresh.kumar@linaro.org,
devicetree@vger.kernel.org, arnd@arndb.de,
linux-pm@vger.kernel.org, oss@buserror.net, robh+dt@kernel.org,
Varun Sethi, linux-arm-kernel@lists.infradead.org,
sboyd@kernel.org, gregkh@linuxfoundation.org, rjw@rjwysocki.net,
linux-kernel@vger.kernel.org, Leo Li, sudeep.holla@arm.com,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20181008055159.GH3587@dragon>
> -----Original Message-----
> From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> owner@vger.kernel.org> On Behalf Of Shawn Guo
> Sent: Monday, October 8, 2018 11:22 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: sudeep.holla@arm.com; oss@buserror.net; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> viresh.kumar@linaro.org; linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com; Leo Li
> <leoyang.li@nxp.com>; linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>;
> Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal <pankaj.bansal@nxp.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Sriram Dash <sriram.dash@nxp.com>
> Subject: Re: [PATCH v4 6/6] arm64: dts: add LX2160ARDB board support
>
> On Thu, Oct 04, 2018 at 06:33:51AM +0530, Vabhav Sharma wrote:
> > LX2160A reference design board (RDB) is a high-performance computing,
> > evaluation, and development platform with LX2160A SoC.
> >
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 100
> > ++++++++++++++++++++++
> > 2 files changed, 101 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 86e18ad..445b72b 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-
> rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > new file mode 100644
> > index 0000000..1483071
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -0,0 +1,100 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree file
> > +for LX2160ARDB // // Copyright 2018 NXP
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-lx2160a.dtsi"
> > +
> > +/ {
> > + model = "NXP Layerscape LX2160ARDB";
> > + compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + sb_3v3: regulator-fixed {
>
> The node name should probably be named like regulator-sb3v3 or something, so
> that the pattern can be followed when we have another fixed regulator to be
> added.
Ok, Agree this is fixed 3.3 standby voltage for i2c subchannels
Updating to regulator-sb3v3
>
> > + compatible = "regulator-fixed";
> > + regulator-name = "fixed-3.3V";
>
> The name should be something we can find on board schematics.
Sure, I will update SMPS name which provide fixed 3.3 stand-by voltage
>
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + };
> > +
> > +};
> > +
> > +&uart0 {
> > + status = "okay";
> > +};
> > +
> > +&uart1 {
> > + status = "okay";
> > +};
> > +
> > +&i2c0 {
>
> Please keep these labeled nodes sorted alphabetically.
Ok
>
> > + status = "okay";
>
> Have a newline between properties and child node.
Sure.
>
> > + i2c-mux@77 {
> > + compatible = "nxp,pca9547";
> > + reg = <0x77>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + i2c@2 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x2>;
> > +
> > + power-monitor@40 {
> > + compatible = "ti,ina220";
> > + reg = <0x40>;
> > + shunt-resistor = <1000>;
> > + };
> > + };
> > +
> > + i2c@3 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x3>;
> > +
> > + temperature-sensor@4c {
> > + compatible = "nxp,sa56004";
> > + reg = <0x4c>;
> > + vcc-supply = <&sb_3v3>;
> > + };
> > +
> > + temperature-sensor@4d {
> > + compatible = "nxp,sa56004";
> > + reg = <0x4d>;
> > + vcc-supply = <&sb_3v3>;
> > + };
> > + };
> > + };
> > +};
> > +
> > +&i2c4 {
> > + status = "okay";
> > +
> > + rtc@51 {
> > + compatible = "nxp,pcf2129";
> > + reg = <0x51>;
> > + // IRQ10_B
> > + interrupts = <0 150 0x4>;
> > + };
>
> Bad indentation.
My mistake, Updated
>
> Shawn
>
> > +
> > +};
> > +
> > +&usb0 {
> > + status = "okay";
> > +};
> > +
> > +&usb1 {
> > + status = "okay";
> > +};
> > +
> > +&crypto {
> > + status = "okay";
> > +};
> > --
> > 2.7.4
> >
^ permalink raw reply
* [PATCH 01/12] powerpc/prom_init: Make of_workarounds static
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
It's not used anywhere else
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 9b38a2e5dd35..a1ba56e8c917 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -87,7 +87,7 @@
#define OF_WORKAROUNDS 0
#else
#define OF_WORKAROUNDS of_workarounds
-int of_workarounds;
+static int of_workarounds __promdata;
#endif
#define OF_WA_CLAIM 1 /* do phys/virt claim separately, then map */
--
2.17.1
^ permalink raw reply related
* [PATCH 02/12] powerpc/prom_init: Make "fake_elf" const
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
It is never modified
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index a1ba56e8c917..e44f55be64ba 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -922,7 +922,7 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
/* Old method - ELF header with PT_NOTE sections only works on BE */
#ifdef __BIG_ENDIAN__
-static struct fake_elf {
+static const struct fake_elf {
Elf32_Ehdr elfhdr;
Elf32_Phdr phdr[2];
struct chrpnote {
--
2.17.1
^ permalink raw reply related
* [PATCH 11/12] powerpc: Check prom_init for disallowed sections
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
prom_init.c must not modify the kernel image outside
of the .bss.prominit section. Thus make sure that
prom_init.o doesn't have anything in any of these:
.data
.bss
.init.data
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init_check.sh | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/kernel/prom_init_check.sh b/arch/powerpc/kernel/prom_init_check.sh
index acb6b9226352..667df97d2595 100644
--- a/arch/powerpc/kernel/prom_init_check.sh
+++ b/arch/powerpc/kernel/prom_init_check.sh
@@ -28,6 +28,18 @@ OBJ="$2"
ERROR=0
+function check_section()
+{
+ file=$1
+ section=$2
+ size=$(objdump -h -j $section $file 2>/dev/null | awk "\$2 == \"$section\" {print \$3}")
+ size=${size:-0}
+ if [ $size -ne 0 ]; then
+ ERROR=1
+ echo "Error: Section $section not empty in prom_init.c" >&2
+ fi
+}
+
for UNDEF in $($NM -u $OBJ | awk '{print $2}')
do
# On 64-bit nm gives us the function descriptors, which have
@@ -66,4 +78,8 @@ do
fi
done
+check_section $OBJ .data
+check_section $OBJ .bss
+check_section $OBJ .init.data
+
exit $ERROR
--
2.17.1
^ permalink raw reply related
* [PATCH 12/12] powerpc/prom_init: Generate "phandle" instead of "linux, phandle"
From: Benjamin Herrenschmidt @ 2018-10-15 2:50 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
When creating the boot-time FDT from an actual Open Firmware live
tree, let's generate "phandle" properties for the phandles instead
of the old deprecated "linux,phandle".
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 57762f19f136..64409d2ecaee 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2407,14 +2407,12 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
has_phandle = 1;
}
- /* Add a "linux,phandle" property if no "phandle" property already
- * existed.
- */
+ /* Add a "phandle" property if none already exist */
if (!has_phandle) {
- soff = dt_find_string("linux,phandle");
+ soff = dt_find_string("phandle");
if (soff == 0)
prom_printf("WARNING: Can't find string index for"
- " <linux-phandle> node %s\n", path);
+ " <phandle> node %s\n", path);
else {
dt_push_token(OF_DT_PROP, mem_start, mem_end);
dt_push_token(4, mem_start, mem_end);
@@ -2474,9 +2472,9 @@ static void __init flatten_device_tree(void)
dt_string_start = mem_start;
mem_start += 4; /* hole */
- /* Add "linux,phandle" in there, we'll need it */
+ /* Add "phandle" in there, we'll need it */
namep = make_room(&mem_start, &mem_end, 16, 1);
- strcpy(namep, "linux,phandle");
+ strcpy(namep, "phandle");
mem_start = (unsigned long)namep + strlen(namep) + 1;
/* Build string array */
--
2.17.1
^ permalink raw reply related
* [PATCH 07/12] powerpc/prom_init: Move ibm_arch_vec to __prombss
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
Make the existing initialized definition constant and copy
it to a __prombss copy
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 70f2bde06ab3..03b171bb1c29 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -788,7 +788,7 @@ struct ibm_arch_vec {
struct option_vector6 vec6;
} __packed;
-struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
+static const struct ibm_arch_vec ibm_architecture_vec_template = {
.pvrs = {
{
.mask = cpu_to_be32(0xfffe0000), /* POWER5/POWER5+ */
@@ -926,6 +926,8 @@ struct ibm_arch_vec __cacheline_aligned ibm_architecture_vec = {
},
};
+static struct ibm_arch_vec __prombss ibm_architecture_vec ____cacheline_aligned;
+
/* Old method - ELF header with PT_NOTE sections only works on BE */
#ifdef __BIG_ENDIAN__
static const struct fake_elf {
@@ -1135,6 +1137,10 @@ static void __init prom_check_platform_support(void)
};
int prop_len = prom_getproplen(prom.chosen,
"ibm,arch-vec-5-platform-support");
+
+ /* First copy the architecture vec template */
+ ibm_architecture_vec = ibm_architecture_vec_template;
+
if (prop_len > 1) {
int i;
u8 vec[prop_len];
--
2.17.1
^ permalink raw reply related
* [PATCH 05/12] powerpc/prom_init: Remove support for OPAL v2
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
We removed support for running under any OPAL version
earlier than v3 in 2015 (they never saw the light of day
anyway), but we kept some leftovers of this support in
prom_init.c, so let's take it out.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 125 +++-----------------------------
1 file changed, 10 insertions(+), 115 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 9942bfca12e4..9852cdb8bb9e 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -43,7 +43,6 @@
#include <asm/btext.h>
#include <asm/sections.h>
#include <asm/machdep.h>
-#include <asm/opal.h>
#include <asm/asm-prototypes.h>
#include <linux/linux_logo.h>
@@ -191,7 +190,6 @@ struct platform_support {
#define PLATFORM_LPAR 0x0001
#define PLATFORM_POWERMAC 0x0400
#define PLATFORM_GENERIC 0x0500
-#define PLATFORM_OPAL 0x0600
static int __prombss of_platform;
@@ -684,7 +682,7 @@ static void __init early_cmdline_parse(void)
prom_debug("Radix disabled from cmdline\n");
}
-#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
+#ifdef CONFIG_PPC_PSERIES
/*
* The architecture vector has an array of PVR mask/value pairs,
* followed by # option vectors - 1, followed by the option vectors.
@@ -1228,7 +1226,7 @@ static void __init prom_send_capabilities(void)
}
#endif /* __BIG_ENDIAN__ */
}
-#endif /* #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) */
+#endif /* CONFIG_PPC_PSERIES */
/*
* Memory allocation strategy... our layout is normally:
@@ -1565,88 +1563,6 @@ static void __init prom_close_stdin(void)
}
}
-#ifdef CONFIG_PPC_POWERNV
-
-#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
-static u64 __prombss prom_opal_base;
-static u64 __prombss prom_opal_entry;
-#endif
-
-/*
- * Allocate room for and instantiate OPAL
- */
-static void __init prom_instantiate_opal(void)
-{
- phandle opal_node;
- ihandle opal_inst;
- u64 base, entry;
- u64 size = 0, align = 0x10000;
- __be64 val64;
- u32 rets[2];
-
- prom_debug("prom_instantiate_opal: start...\n");
-
- opal_node = call_prom("finddevice", 1, 1, ADDR("/ibm,opal"));
- prom_debug("opal_node: %x\n", opal_node);
- if (!PHANDLE_VALID(opal_node))
- return;
-
- val64 = 0;
- prom_getprop(opal_node, "opal-runtime-size", &val64, sizeof(val64));
- size = be64_to_cpu(val64);
- if (size == 0)
- return;
- val64 = 0;
- prom_getprop(opal_node, "opal-runtime-alignment", &val64,sizeof(val64));
- align = be64_to_cpu(val64);
-
- base = alloc_down(size, align, 0);
- if (base == 0) {
- prom_printf("OPAL allocation failed !\n");
- return;
- }
-
- opal_inst = call_prom("open", 1, 1, ADDR("/ibm,opal"));
- if (!IHANDLE_VALID(opal_inst)) {
- prom_printf("opening opal package failed (%x)\n", opal_inst);
- return;
- }
-
- prom_printf("instantiating opal at 0x%llx...", base);
-
- if (call_prom_ret("call-method", 4, 3, rets,
- ADDR("load-opal-runtime"),
- opal_inst,
- base >> 32, base & 0xffffffff) != 0
- || (rets[0] == 0 && rets[1] == 0)) {
- prom_printf(" failed\n");
- return;
- }
- entry = (((u64)rets[0]) << 32) | rets[1];
-
- prom_printf(" done\n");
-
- reserve_mem(base, size);
-
- prom_debug("opal base = 0x%llx\n", base);
- prom_debug("opal align = 0x%llx\n", align);
- prom_debug("opal entry = 0x%llx\n", entry);
- prom_debug("opal size = 0x%llx\n", size);
-
- prom_setprop(opal_node, "/ibm,opal", "opal-base-address",
- &base, sizeof(base));
- prom_setprop(opal_node, "/ibm,opal", "opal-entry-address",
- &entry, sizeof(entry));
-
-#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
- prom_opal_base = base;
- prom_opal_entry = entry;
-#endif
- prom_debug("prom_instantiate_opal: end...\n");
-}
-
-#endif /* CONFIG_PPC_POWERNV */
-
/*
* Allocate room for and instantiate RTAS
*/
@@ -2153,10 +2069,6 @@ static int __init prom_find_machine_type(void)
}
}
#ifdef CONFIG_PPC64
- /* Try to detect OPAL */
- if (PHANDLE_VALID(call_prom("finddevice", 1, 1, ADDR("/ibm,opal"))))
- return PLATFORM_OPAL;
-
/* Try to figure out if it's an IBM pSeries or any other
* PAPR compliant platform. We assume it is if :
* - /device_type is "chrp" (please, do NOT use that for future
@@ -2485,7 +2397,7 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
}
/* Add a "linux,phandle" property if no "phandle" property already
- * existed (can happen with OPAL)
+ * existed.
*/
if (!has_phandle) {
soff = dt_find_string("linux,phandle");
@@ -3175,7 +3087,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
*/
early_cmdline_parse();
-#if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
+#ifdef CONFIG_PPC_PSERIES
/*
* On pSeries, inform the firmware about our capabilities
*/
@@ -3219,15 +3131,9 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
* On non-powermacs, try to instantiate RTAS. PowerMacs don't
* have a usable RTAS implementation.
*/
- if (of_platform != PLATFORM_POWERMAC &&
- of_platform != PLATFORM_OPAL)
+ if (of_platform != PLATFORM_POWERMAC)
prom_instantiate_rtas();
-#ifdef CONFIG_PPC_POWERNV
- if (of_platform == PLATFORM_OPAL)
- prom_instantiate_opal();
-#endif /* CONFIG_PPC_POWERNV */
-
#ifdef CONFIG_PPC64
/* instantiate sml */
prom_instantiate_sml();
@@ -3240,8 +3146,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
*
* (This must be done after instanciating RTAS)
*/
- if (of_platform != PLATFORM_POWERMAC &&
- of_platform != PLATFORM_OPAL)
+ if (of_platform != PLATFORM_POWERMAC)
prom_hold_cpus();
/*
@@ -3285,11 +3190,9 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
/*
* in case stdin is USB and still active on IBM machines...
* Unfortunately quiesce crashes on some powermacs if we have
- * closed stdin already (in particular the powerbook 101). It
- * appears that the OPAL version of OFW doesn't like it either.
+ * closed stdin already (in particular the powerbook 101).
*/
- if (of_platform != PLATFORM_POWERMAC &&
- of_platform != PLATFORM_OPAL)
+ if (of_platform != PLATFORM_POWERMAC)
prom_close_stdin();
/*
@@ -3307,10 +3210,8 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
hdr = dt_header_start;
/* Don't print anything after quiesce under OPAL, it crashes OFW */
- if (of_platform != PLATFORM_OPAL) {
- prom_printf("Booting Linux via __start() @ 0x%lx ...\n", kbase);
- prom_debug("->dt_header_start=0x%lx\n", hdr);
- }
+ prom_printf("Booting Linux via __start() @ 0x%lx ...\n", kbase);
+ prom_debug("->dt_header_start=0x%lx\n", hdr);
#ifdef CONFIG_PPC32
reloc_got2(-offset);
@@ -3318,13 +3219,7 @@ unsigned long __init prom_init(unsigned long r3, unsigned long r4,
unreloc_toc();
#endif
-#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
- /* OPAL early debug gets the OPAL base & entry in r8 and r9 */
- __start(hdr, kbase, 0, 0, 0,
- prom_opal_base, prom_opal_entry);
-#else
__start(hdr, kbase, 0, 0, 0, 0, 0);
-#endif
return 0;
}
--
2.17.1
^ permalink raw reply related
* [PATCH 08/12] powerpc/prom_init: Move const structures to __initconst
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
As they are no longer used past the end of prom_init
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 03b171bb1c29..cbd54fe30367 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -788,7 +788,7 @@ struct ibm_arch_vec {
struct option_vector6 vec6;
} __packed;
-static const struct ibm_arch_vec ibm_architecture_vec_template = {
+static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
.pvrs = {
{
.mask = cpu_to_be32(0xfffe0000), /* POWER5/POWER5+ */
@@ -963,7 +963,7 @@ static const struct fake_elf {
u32 ignore_me;
} rpadesc;
} rpanote;
-} fake_elf = {
+} fake_elf __initconst = {
.elfhdr = {
.e_ident = { 0x7f, 'E', 'L', 'F',
ELFCLASS32, ELFDATA2MSB, EV_CURRENT },
@@ -2128,7 +2128,7 @@ static void __init prom_check_displays(void)
ihandle ih;
int i;
- static const unsigned char default_colors[] = {
+ static const unsigned char default_colors[] __initconst = {
0x00, 0x00, 0x00,
0x00, 0x00, 0xaa,
0x00, 0xaa, 0x00,
--
2.17.1
^ permalink raw reply related
* [PATCH 06/12] powerpc/prom_init: Move prom_radix_disable to __prombss
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
Initialize it dynamically instead of statically
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 9852cdb8bb9e..70f2bde06ab3 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -172,7 +172,9 @@ static unsigned long __prombss prom_tce_alloc_start;
static unsigned long __prombss prom_tce_alloc_end;
#endif
-static bool prom_radix_disable __initdata = !IS_ENABLED(CONFIG_PPC_RADIX_MMU_DEFAULT);
+#ifdef CONFIG_PPC_PSERIES
+static bool prom_radix_disable __prombss;
+#endif
struct platform_support {
bool hash_mmu;
@@ -665,6 +667,8 @@ static void __init early_cmdline_parse(void)
#endif
}
+#ifdef CONFIG_PPC_PSERIES
+ prom_radix_disable = !IS_ENABLED(CONFIG_PPC_RADIX_MMU_DEFAULT);
opt = strstr(prom_cmd_line, "disable_radix");
if (opt) {
opt += 13;
@@ -680,6 +684,7 @@ static void __init early_cmdline_parse(void)
}
if (prom_radix_disable)
prom_debug("Radix disabled from cmdline\n");
+#endif /* CONFIG_PPC_PSERIES */
}
#ifdef CONFIG_PPC_PSERIES
--
2.17.1
^ permalink raw reply related
* [PATCH 03/12] powerpc/prom_init: Make "default_colors" const
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
It's never modified either
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index e44f55be64ba..2e1ebf26e8e4 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -2202,7 +2202,7 @@ static void __init prom_check_displays(void)
ihandle ih;
int i;
- static unsigned char default_colors[] = {
+ static const unsigned char default_colors[] = {
0x00, 0x00, 0x00,
0x00, 0x00, 0xaa,
0x00, 0xaa, 0x00,
--
2.17.1
^ permalink raw reply related
* [PATCH 04/12] powerpc/prom_init: Replace __initdata with __prombss when applicable
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
This replaces all occurrences of __initdata for uninitialized
data with a new __prombss
Currently __promdata is defined to be __initdata but we'll
eventually change that.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 55 +++++++++++++++++----------------
1 file changed, 29 insertions(+), 26 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 2e1ebf26e8e4..9942bfca12e4 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -48,6 +48,9 @@
#include <linux/linux_logo.h>
+/* All of prom_init bss lives here */
+#define __prombss __initdata
+
/*
* Eventually bump that one up
*/
@@ -87,7 +90,7 @@
#define OF_WORKAROUNDS 0
#else
#define OF_WORKAROUNDS of_workarounds
-static int of_workarounds __promdata;
+static int of_workarounds __prombss;
#endif
#define OF_WA_CLAIM 1 /* do phys/virt claim separately, then map */
@@ -148,26 +151,26 @@ extern void copy_and_flush(unsigned long dest, unsigned long src,
unsigned long size, unsigned long offset);
/* prom structure */
-static struct prom_t __initdata prom;
+static struct prom_t __prombss prom;
-static unsigned long prom_entry __initdata;
+static unsigned long __prombss prom_entry;
#define PROM_SCRATCH_SIZE 256
-static char __initdata of_stdout_device[256];
-static char __initdata prom_scratch[PROM_SCRATCH_SIZE];
+static char __prombss of_stdout_device[256];
+static char __prombss prom_scratch[PROM_SCRATCH_SIZE];
-static unsigned long __initdata dt_header_start;
-static unsigned long __initdata dt_struct_start, dt_struct_end;
-static unsigned long __initdata dt_string_start, dt_string_end;
+static unsigned long __prombss dt_header_start;
+static unsigned long __prombss dt_struct_start, dt_struct_end;
+static unsigned long __prombss dt_string_start, dt_string_end;
-static unsigned long __initdata prom_initrd_start, prom_initrd_end;
+static unsigned long __prombss prom_initrd_start, prom_initrd_end;
#ifdef CONFIG_PPC64
-static int __initdata prom_iommu_force_on;
-static int __initdata prom_iommu_off;
-static unsigned long __initdata prom_tce_alloc_start;
-static unsigned long __initdata prom_tce_alloc_end;
+static int __prombss prom_iommu_force_on;
+static int __prombss prom_iommu_off;
+static unsigned long __prombss prom_tce_alloc_start;
+static unsigned long __prombss prom_tce_alloc_end;
#endif
static bool prom_radix_disable __initdata = !IS_ENABLED(CONFIG_PPC_RADIX_MMU_DEFAULT);
@@ -190,22 +193,22 @@ struct platform_support {
#define PLATFORM_GENERIC 0x0500
#define PLATFORM_OPAL 0x0600
-static int __initdata of_platform;
+static int __prombss of_platform;
-static char __initdata prom_cmd_line[COMMAND_LINE_SIZE];
+static char __prombss prom_cmd_line[COMMAND_LINE_SIZE];
-static unsigned long __initdata prom_memory_limit;
+static unsigned long __prombss prom_memory_limit;
-static unsigned long __initdata alloc_top;
-static unsigned long __initdata alloc_top_high;
-static unsigned long __initdata alloc_bottom;
-static unsigned long __initdata rmo_top;
-static unsigned long __initdata ram_top;
+static unsigned long __prombss alloc_top;
+static unsigned long __prombss alloc_top_high;
+static unsigned long __prombss alloc_bottom;
+static unsigned long __prombss rmo_top;
+static unsigned long __prombss ram_top;
-static struct mem_map_entry __initdata mem_reserve_map[MEM_RESERVE_MAP_SIZE];
-static int __initdata mem_reserve_cnt;
+static struct mem_map_entry __prombss mem_reserve_map[MEM_RESERVE_MAP_SIZE];
+static int __prombss mem_reserve_cnt;
-static cell_t __initdata regbuf[1024];
+static cell_t __prombss regbuf[1024];
static bool rtas_has_query_cpu_stopped;
@@ -1565,8 +1568,8 @@ static void __init prom_close_stdin(void)
#ifdef CONFIG_PPC_POWERNV
#ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
-static u64 __initdata prom_opal_base;
-static u64 __initdata prom_opal_entry;
+static u64 __prombss prom_opal_base;
+static u64 __prombss prom_opal_entry;
#endif
/*
--
2.17.1
^ permalink raw reply related
* [PATCH 10/12] powerpc/prom_init: Move __prombss to it's own section and store it in .bss
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
This makes __prombss its own section, and for now store
it in .bss.
This will give us the ability later to store it elsewhere
and/or free it after boot (it's about 8KB).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 2 +-
arch/powerpc/kernel/vmlinux.lds.S | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 306562d4d818..57762f19f136 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -48,7 +48,7 @@
#include <linux/linux_logo.h>
/* All of prom_init bss lives here */
-#define __prombss __initdata
+#define __prombss __section(.bss.prominit)
/*
* Eventually bump that one up
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index 07ae018e550e..ac0ceb31b336 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -4,6 +4,9 @@
#else
#define PROVIDE32(x) PROVIDE(x)
#endif
+
+#define BSS_FIRST_SECTIONS *(.bss.prominit)
+
#include <asm/page.h>
#include <asm-generic/vmlinux.lds.h>
#include <asm/cache.h>
--
2.17.1
^ permalink raw reply related
* RE: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support
From: Vabhav Sharma @ 2018-10-15 2:58 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland@arm.com, kstewart@linuxfoundation.org,
Yogesh Narayan Gaur, linux-kernel-owner@vger.kernel.org,
catalin.marinas@arm.com, mturquette@baylibre.com,
will.deacon@arm.com, yamada.masahiro@socionext.com, Sriram Dash,
linux-clk@vger.kernel.org, Pankaj Bansal, Udit Kumar,
linux@armlinux.org.uk, Priyanka Jain, viresh.kumar@linaro.org,
devicetree@vger.kernel.org, arnd@arndb.de,
linux-pm@vger.kernel.org, oss@buserror.net, robh+dt@kernel.org,
Varun Sethi, Nipun Gupta, linux-arm-kernel@lists.infradead.org,
Ramneek Mehresh, sboyd@kernel.org, gregkh@linuxfoundation.org,
Ying Zhang, rjw@rjwysocki.net, linux-kernel@vger.kernel.org,
Leo Li, sudeep.holla@arm.com, linuxppc-dev@lists.ozlabs.org
In-Reply-To: <20181008054510.GG3587@dragon>
> -----Original Message-----
> From: Shawn Guo <shawnguo@kernel.org>
> Sent: Monday, October 8, 2018 11:15 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: sudeep.holla@arm.com; oss@buserror.net; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> viresh.kumar@linaro.org; linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com; Leo Li
> <leoyang.li@nxp.com>; linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>;
> Udit Kumar <udit.kumar@nxp.com>; Pankaj Bansal <pankaj.bansal@nxp.com>;
> Ramneek Mehresh <ramneek.mehresh@nxp.com>; Ying Zhang
> <ying.zhang22455@nxp.com>; Nipun Gupta <nipun.gupta@nxp.com>; Priyanka
> Jain <priyanka.jain@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; Sriram Dash <sriram.dash@nxp.com>
> Subject: Re: [PATCH v4 5/6] arm64: dts: add QorIQ LX2160A SoC support
>
> On Thu, Oct 04, 2018 at 06:33:50AM +0530, Vabhav Sharma wrote:
> > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> >
> > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor
> > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8
> > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011
> > SBSA UARTs etc.
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 702
> > +++++++++++++++++++++++++
> > 1 file changed, 702 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > new file mode 100644
> > index 0000000..c758268
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -0,0 +1,702 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree
> > +Include file for Layerscape-LX2160A family SoC.
> > +//
> > +// Copyright 2018 NXP
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/memreserve/ 0x80000000 0x00010000;
> > +
> > +/ {
> > + compatible = "fsl,lx2160a";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + // 8 clusters having 2 Cortex-A72 cores each
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x0>;
> > + clocks = <&clockgen 1 0>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x1>;
> > + clocks = <&clockgen 1 0>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x100>;
> > + clocks = <&clockgen 1 1>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cpu@101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x101>;
> > + clocks = <&clockgen 1 1>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x200>;
> > + clocks = <&clockgen 1 2>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster2_l2>;
> > + };
> > +
> > + cpu@201 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x201>;
> > + clocks = <&clockgen 1 2>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster2_l2>;
> > + };
> > +
> > + cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x300>;
> > + clocks = <&clockgen 1 3>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster3_l2>;
> > + };
> > +
> > + cpu@301 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x301>;
> > + clocks = <&clockgen 1 3>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster3_l2>;
> > + };
> > +
> > + cpu@400 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x400>;
> > + clocks = <&clockgen 1 4>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster4_l2>;
> > + };
> > +
> > + cpu@401 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x401>;
> > + clocks = <&clockgen 1 4>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster4_l2>;
> > + };
> > +
> > + cpu@500 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x500>;
> > + clocks = <&clockgen 1 5>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster5_l2>;
> > + };
> > +
> > + cpu@501 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x501>;
> > + clocks = <&clockgen 1 5>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster5_l2>;
> > + };
> > +
> > + cpu@600 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x600>;
> > + clocks = <&clockgen 1 6>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster6_l2>;
> > + };
> > +
> > + cpu@601 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x601>;
> > + clocks = <&clockgen 1 6>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster6_l2>;
> > + };
> > +
> > + cpu@700 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x700>;
> > + clocks = <&clockgen 1 7>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster7_l2>;
> > + };
> > +
> > + cpu@701 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x701>;
> > + clocks = <&clockgen 1 7>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster7_l2>;
> > + };
> > +
> > + cluster0_l2: l2-cache0 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster1_l2: l2-cache1 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster2_l2: l2-cache2 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster3_l2: l2-cache3 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster4_l2: l2-cache4 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster5_l2: l2-cache5 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster6_l2: l2-cache6 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster7_l2: l2-cache7 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > + };
> > +
> > + gic: interrupt-controller@6000000 {
> > + compatible = "arm,gic-v3";
> > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
> > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
> > + // SGI_base)
> > + <0x0 0x0c0c0000 0 0x2000>, // GICC
> > + <0x0 0x0c0d0000 0 0x1000>, // GICH
> > + <0x0 0x0c0e0000 0 0x20000>; // GICV
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + interrupt-controller;
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + its: gic-its@6020000 {
> > + compatible = "arm,gic-v3-its";
> > + msi-controller;
> > + reg = <0x0 0x6020000 0 0x20000>;
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a72-pmu";
> > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + memory@80000000 {
> > + // DRAM space - 1, size : 2 GB DRAM
> > + device_type = "memory";
> > + reg = <0x00000000 0x80000000 0 0x80000000>;
> > + };
> > +
> > + ddr1: memory-controller@1080000 {
> > + compatible = "fsl,qoriq-memory-controller";
> > + reg = <0x0 0x1080000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + little-endian;
> > + };
> > +
> > + ddr2: memory-controller@1090000 {
> > + compatible = "fsl,qoriq-memory-controller";
> > + reg = <0x0 0x1090000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > + little-endian;
> > + };
> > +
> > + sysclk: sysclk {
>
> Name the node a bit generic like clock-xxx.
There is only one clock-unit, Bootloader(U-boot) require sysclk node during device tree fix-up as different platform support varied platform frequency as per reset configuration word used.
Referred other ARM based platform with one clock using name as x: x
>
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + clockgen: clocking@1300000 {
>
> clock-controller for node name.
Ok, I see generic name recommendation section 2.2.2 DT Specification
>
> > + compatible = "fsl,lx2160a-clockgen";
> > + reg = <0 0x1300000 0 0xa0000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + };
> > +
> > + crypto: crypto@8000000 {
> > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> > + fsl,sec-era = <10>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x00 0x8000000 0x100000>;
> > + reg = <0x00 0x8000000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > + status = "disabled";
> > +
> > + sec_jr0: jr@10000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x10000 0x10000>;
> > + interrupts = <GIC_SPI 140
> IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr1: jr@20000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x20000 0x10000>;
> > + interrupts = <GIC_SPI 141
> IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr2: jr@30000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x30000 0x10000>;
> > + interrupts = <GIC_SPI 142
> IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr3: jr@40000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x40000 0x10000>;
> > + interrupts = <GIC_SPI 143
> IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > + };
> > +
> > + dcfg: dcfg@1e00000 {
>
> As per suggestion from devicetree specification, we can "syscon" as a more
> generic node name?
Sure as per DT spec recommendation, Updating to dcfg: syscon@1e00000
>
> > + compatible = "fsl,lx2160a-dcfg", "syscon";
> > + reg = <0x0 0x1e00000 0x0 0x10000>;
> > + little-endian;
> > + };
> > +
> > + gpio0: gpio@2300000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2300000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio1: gpio@2310000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2310000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio2: gpio@2320000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2320000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio3: gpio@2330000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2330000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + i2c0: i2c@2000000 {
>
> Sort the nodes under bus in order of unit-address.
Ok, I will update
Is it recommendation or rule? I don't see in DT specification
>
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2000000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + fsl-scl-gpio = <&gpio2 15 0>;
>
> I cannot find this property in fsl,vf610-i2c bindings.
Yes this is not present, I will update the property as scl-gpio
>
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@2010000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2010000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c@2020000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2020000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c@2030000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2030000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c4: i2c@2040000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2040000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + fsl-scl-gpio = <&gpio2 16 0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c5: i2c@2050000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2050000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c6: i2c@2060000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2060000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c7: i2c@2070000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2070000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + uart0: serial@21c0000 {
> > + device_type = "serial";
>
> Quote from devicetree specification:
>
> The device_type property was used in IEEE 1275 to describe the device’s FCode
> programming model. Because DTSpec does not have FCode, new use of the
> property is deprecated, and it should be included only on cpu and memory nodes
> for compatibility with IEEE 1275–derived devicetrees.
Ok, Thanks. I see section 2.3.11 DT specification as you mentioned.
Not required except for memory/cpu node, I will update
>
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21c0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@21d0000 {
> > + device_type = "serial";
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21d0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@21e0000 {
> > + device_type = "serial";
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21e0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@21f0000 {
> > + device_type = "serial";
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21f0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + smmu: iommu@5000000 {
> > + compatible = "arm,mmu-500";
> > + reg = <0 0x5000000 0 0x800000>;
> > + #iommu-cells = <1>;
> > + #global-interrupts = <14>;
> > + interrupts = <0 13 4>, // global secure fault
>
> Can we use defines for interrupt cells just like other device nodes?
Sure
>
> > + <0 14 4>, // combined secure interrupt
> > + <0 15 4>, // global non-secure fault
> > + <0 16 4>, // combined non-secure interrupt
> > + // performance counter interrupts 0-9
> > + <0 211 4>, <0 212 4>,
> > + <0 213 4>, <0 214 4>,
> > + <0 215 4>, <0 216 4>,
> > + <0 217 4>, <0 218 4>,
> > + <0 219 4>, <0 220 4>,
> > + // per context interrupt, 64 interrupts
> > + <0 146 4>, <0 147 4>,
> > + <0 148 4>, <0 149 4>,
> > + <0 150 4>, <0 151 4>,
> > + <0 152 4>, <0 153 4>,
> > + <0 154 4>, <0 155 4>,
> > + <0 156 4>, <0 157 4>,
> > + <0 158 4>, <0 159 4>,
> > + <0 160 4>, <0 161 4>,
> > + <0 162 4>, <0 163 4>,
> > + <0 164 4>, <0 165 4>,
> > + <0 166 4>, <0 167 4>,
> > + <0 168 4>, <0 169 4>,
> > + <0 170 4>, <0 171 4>,
> > + <0 172 4>, <0 173 4>,
> > + <0 174 4>, <0 175 4>,
> > + <0 176 4>, <0 177 4>,
> > + <0 178 4>, <0 179 4>,
> > + <0 180 4>, <0 181 4>,
> > + <0 182 4>, <0 183 4>,
> > + <0 184 4>, <0 185 4>,
> > + <0 186 4>, <0 187 4>,
> > + <0 188 4>, <0 189 4>,
> > + <0 190 4>, <0 191 4>,
> > + <0 192 4>, <0 193 4>,
> > + <0 194 4>, <0 195 4>,
> > + <0 196 4>, <0 197 4>,
> > + <0 198 4>, <0 199 4>,
> > + <0 200 4>, <0 201 4>,
> > + <0 202 4>, <0 203 4>,
> > + <0 204 4>, <0 205 4>,
> > + <0 206 4>, <0 207 4>,
> > + <0 208 4>, <0 209 4>;
> > + dma-coherent;
> > + };
> > +
> > + usb0: usb3@3100000 {
>
> usb for node name.
Ok, I see recommendation for generic name in DT spec
>
> Shawn
>
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0x3100000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "host";
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,dis_rxdet_inp3_quirk;
> > + status = "disabled";
> > + };
> > +
> > + usb1: usb3@3110000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0x3110000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "host";
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,dis_rxdet_inp3_quirk;
> > + status = "disabled";
> > + };
> > +
> > + watchdog@23a0000 {
> > + compatible = "arm,sbsa-gwdt";
> > + reg = <0x0 0x23a0000 0 0x1000>,
> > + <0x0 0x2390000 0 0x1000>;
> > + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > + timeout-sec = <30>;
> > + };
> > + };
> > +};
> > --
> > 2.7.4
> >
^ permalink raw reply
* Re: [PATCH v3 13/18] of: overlay: check prevents multiple fragments touching same property
From: Frank Rowand @ 2018-10-15 3:21 UTC (permalink / raw)
To: Joe Perches, Rob Herring, Pantelis Antoniou, Michael Ellerman,
Benjamin Herrenschmidt, Paul Mackerras, Alan Tull, Moritz Fischer
Cc: devicetree, linux-fpga, linuxppc-dev, linux-kernel
In-Reply-To: <16f48648393366d91e43cd66b3d0a346b1ed29ab.camel@perches.com>
On 10/14/18 18:55, Joe Perches wrote:
> On Sun, 2018-10-14 at 18:52 -0700, Frank Rowand wrote:
>> On 10/14/18 18:06, Joe Perches wrote:
>>> On Sun, 2018-10-14 at 17:24 -0700, frowand.list@gmail.com wrote:
>>>> From: Frank Rowand <frank.rowand@sony.com>
>>>>
>>>> Add test case of two fragments updating the same property. After
>>>> adding the test case, the system hangs at end of boot, after
>>>> after slub stack dumps from kfree() in crypto modprobe code.
> []
>>> I think this is worse performance than before.
>>>
>>> This now walks all entries when before it would
>>> return -EINVAL directly when it found a match.
>>
>> Yes, it is worse performance, but that is OK.
>>
>> This is a check that is done when a devicetree overlay is applied.
>> If an error occurs then that means that the overlay was incorrectly
>> specified. The file drivers/of/unittest-data/overlay_bad_add_dup_prop.dts
>> in this patch provides an example of how a bad overlay can be created.
>>
>> Once an error was detected, the check could return immediately, or it
>> could continue to give a complete list of detected errors. I chose to
>> give the complete list of detected errors.
>
> Swell. Please describe that in the commit message.
If a version 4 of the series is created I will update the commit
message. As a stand alone item I do not think it is worth a
new version.
-Frank
^ permalink raw reply
* Re: [RFC,01/11] powerpc/prom_init: Make of_workarounds static
From: Michael Ellerman @ 2018-10-15 4:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
In-Reply-To: <20180531043349.24783-2-benh@kernel.crashing.org>
On Thu, 2018-05-31 at 04:33:39 UTC, Benjamin Herrenschmidt wrote:
> It's not used anywhere else
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/3bad719b495467a7e7023c5b26f0f5
cheers
^ permalink raw reply
* Re: [RFC,02/11] powerpc/prom_init: Make "fake_elf" const
From: Michael Ellerman @ 2018-10-15 4:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
In-Reply-To: <20180531043349.24783-3-benh@kernel.crashing.org>
On Thu, 2018-05-31 at 04:33:40 UTC, Benjamin Herrenschmidt wrote:
> It is never modified
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/30c69ca0486fd73f2e5d40096ee68b
cheers
^ permalink raw reply
* Re: [RFC,03/11] powerpc/prom_init: Make "default_colors" const
From: Michael Ellerman @ 2018-10-15 4:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt, linuxppc-dev
In-Reply-To: <20180531043349.24783-4-benh@kernel.crashing.org>
On Thu, 2018-05-31 at 04:33:41 UTC, Benjamin Herrenschmidt wrote:
> It's never modified either
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/7f995d3ba6f2bfbe274f5a012f5b54
cheers
^ permalink raw reply
* Re: [1/2] powerpc/64s/hash: do not use PPC_INVALIDATE_ERAT on CPUs before POWER9
From: Michael Ellerman @ 2018-10-15 4:00 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev; +Cc: Nicholas Piggin
In-Reply-To: <20180827030302.17541-2-npiggin@gmail.com>
On Mon, 2018-08-27 at 03:03:01 UTC, Nicholas Piggin wrote:
> PPC_INVALIDATE_ERAT is slbia IH=7 which is a new variant introduced
> with POWER9, and the result is undefined on earlier CPUs.
>
> Commits 7b9f71f974 ("powerpc/64s: POWER9 machine check handler") and
> d4748276ae ("powerpc/64s: Improve local TLB flush for boot and MCE on
> POWER9") caused POWER7/8 code to use this instruction. Remove it. An
> ERAT flush can be made by invalidatig the SLB, but before POWER9 that
> requires a flush and rebolt.
>
> Fixes: 7b9f71f974 ("powerpc/64s: POWER9 machine check handler")
> Fixes: d4748276ae ("powerpc/64s: Improve local TLB flush for boot and
> MCE on POWER9")
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/bc276ecba132caccb1fda5863a652c
cheers
^ permalink raw reply
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