* Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/
From: Christoph Hellwig @ 2018-10-15 9:06 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev, Christoph Hellwig
In-Reply-To: <CAK7LNAQ3SNStaA6-tOWhm0QHWpNczO07x9T2F7gMcusduMS7GA@mail.gmail.com>
> Thanks for great work again.
>
> However, I suspect some breakages
> (not testing yet, just quick review by my eyes.)
>
> I left some comments in individual patches.
Thanks. I've updated the git tree based on your comments.
^ permalink raw reply
* Re: [PATCH 4/8] pci: consolidate PCI config entry in drivers/pci
From: Christoph Hellwig @ 2018-10-15 8:57 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev, Christoph Hellwig
In-Reply-To: <CAK7LNAQy_NTu5=8R6C3Xc2VLrJo7tKOz-u1=3JfGtBa3Z+ZD9g@mail.gmail.com>
On Mon, Oct 15, 2018 at 03:37:05PM +0900, Masahiro Yamada wrote:
> I think HAVE_ is a preferred prefix in this case according to this doc:
> https://github.com/masahir0y/linux/blob/v4.19-rc4/Documentation/kbuild/kconfig-language.txt#L448
Ok, I'll switch everything to HAVE_*
> If you do this for entire powerpc,
> the other 'select HAS_PCI' addtions to
> arch/powerpc/platforms/*/Kconfig look redundant.
I'll drop them.
> > -config PCI
> > - bool "PCI support"
> > - select PCI_MSI
>
>
> I think this 'select PCI_MSI' for riscv was lost.
Indeed, fixed.
> > menu "Bus options (PCI etc.)"
> >
> > -config PCI
> > - bool "PCI support"
> > - default y
>
>
> The default is y for x86 (and xtensa as well).
>
> With this patch, the default will be flipped.
>
> I think most of people want to use PCI for x86,
> and this change will make people upset.
>
> Will you update arch/{x86,xtensa}/configs/*_defconfig?
Yes. Alternatively we could add a new ARCH_PCI_DEFAULT symbol,
that architectures could select if they want PCI by default. Does
anyone thing this is a good idea?
^ permalink raw reply
* Re: [PATCH 2/8] powerpc: simplify CONFIG_PCI_QSPAN Kconfig magic
From: Christoph Hellwig @ 2018-10-15 8:47 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev, Christoph Hellwig
In-Reply-To: <CAK7LNAQxZcBNadLJhfrmxJGj-XJFVaya3Z1eexZp20vRPwrN7A@mail.gmail.com>
On Mon, Oct 15, 2018 at 03:35:41PM +0900, Masahiro Yamada wrote:
> 'git grep' did not get any other hit.
>
> masahiro@pug:~/ref/linux$ git grep PCI_QSPAN
> arch/powerpc/Kconfig: default PCI_QSPAN if PPC_8xx
> arch/powerpc/Kconfig:config PCI_QSPAN
>
> With your patch, PCI_QSPAN will become
> a dead config option.
>
> How about removing it entirely?
Yes, it should just go away. Thanks!
^ permalink raw reply
* Re: linux-next: qemu boot failures with today's linux-next
From: Stephen Rothwell @ 2018-10-15 8:20 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, PowerPC
Cc: Linux-Next Mailing List, Linux Kernel Mailing List
In-Reply-To: <20181015191859.2f600de5@canb.auug.org.au>
[-- Attachment #1: Type: text/plain, Size: 343 bytes --]
Hi all,
On Mon, 15 Oct 2018 19:18:59 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>
> Today's linux-next tree does not boot in qemu (with kvm or without).
> Here is the (non-kvm) boot log (the kvm one is basically the same):
I should have said that the kernel build is pseries_le_defconfig.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply
* linux-next: qemu boot failures with today's linux-next
From: Stephen Rothwell @ 2018-10-15 8:18 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, PowerPC
Cc: Linux-Next Mailing List, Linux Kernel Mailing List
[-- Attachment #1: Type: text/plain, Size: 2578 bytes --]
Hi all,
Today's linux-next tree does not boot in qemu (with kvm or without).
Here is the (non-kvm) boot log (the kvm one is basically the same):
------------------------------------------------------
SLOF^[[0m^[[?25l **********************************************************************
^[[1mQEMU Starting
^[[0m Build Date = Sep 24 2017 12:23:07
FW Version = buildd@ release 20170724
Press "s" to enter Open Firmware.
^[[0m^[[?25hC0000\rC0100\rC0120\rC0140\rC0200\rC0240\rC0260\rC02E0\rC0300\rC0320\rC0340\rC0360\rC0370\rC0380\rC0371\rC0372\rC0373\rC0374\rC03F0\rC0400\rC0480\rC04C0\rC04D0\rC0500\rPopulating /vdevice methods
Populating /vdevice/vty@71000000
Populating /vdevice/nvram@71000001
Populating /vdevice/l-lan@71000002
Populating /vdevice/v-scsi@71000003
SCSI: Looking for devices
8200000000000000 CD-ROM : "QEMU QEMU CD-ROM 2.5+"
C05A0\rPopulating /pci@800000020000000
C0600\rC06C0\rC0700\rC0800\rC0880\rNo NVRAM common partition, re-initializing...
C0890\rC08A0\rC08A8\rC08B0\rScanning USB
C08C0\rC08D0\rUsing default console: /vdevice/vty@71000000
C08E0\rC08E8\rDetected RAM kernel at 400000 (122a850 bytes)
C08FF\r
Welcome to Open Firmware
Copyright (c) 2004, 2017 IBM Corporation All rights reserved.
This program and the accompanying materials are made available
under the terms of the BSD License available at
http://www.opensource.org/licenses/bsd-license.php
Booting from memory...
OF stdout device is: /vdevice/vty@71000000
Preparing to boot Linux version 4.19.0-rc7 (sfr@ash) (gcc version 8.2.0 (Debian 8.2.0-4)) #2 SMP Mon Oct 15 18:53:28 AEDT 2018
Detected machine type: 0000000000000101
command line:
Max number of cores passed to firmware: 2048 (NR_CPUS = 2048)
Calling ibm,client-architecture-support... done
memory layout at init:
memory_limit : 0000000000000000 (16 MB aligned)
alloc_bottom : 0000000001640000
alloc_top : 0000000030000000
alloc_top_hi : 0000000080000000
rmo_top : 0000000030000000
ram_top : 0000000080000000
instantiating rtas at 0x000000002fff0000... done
prom_hold_cpus: skipped
copying OF device tree...
Building dt strings...
Building dt structure...
Device tree strings 0x0000000001850000 -> 0x0000000001850a02
Device tree struct 0x0000000001860000 -> 0x0000000001870000
Quiescing Open Firmware ...
Booting Linux via __start() @ 0x0000000000400000 ...
------------------------------------------------------
I have no idea what may have caused this.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/2] mm: speed up mremap by 500x on large regions
From: Christian Borntraeger @ 2018-10-15 7:10 UTC (permalink / raw)
To: Joel Fernandes (Google), linux-kernel
Cc: linux-mips, Rich Felker, linux-ia64, linux-sh, Peter Zijlstra,
Catalin Marinas, Dave Hansen, Will Deacon, mhocko, linux-mm,
lokeshgidra, sparclinux, linux-riscv, elfring, Jonas Bonn,
linux-s390, dancol, Yoshinori Sato, linux-xtensa, linux-hexagon,
Helge Deller, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
hughd, James E.J. Bottomley, kasan-dev, kvmarm, Ingo Molnar,
Geert Uytterhoeven, Andrey Ryabinin, linux-snps-arc, kernel-team,
Sam Creasey, Fenghua Yu, Jeff Dike, linux-um, Stefan Kristiansson,
Julia Lawall, linux-m68k, openrisc, Borislav Petkov,
Andy Lutomirski, nios2-dev, kirill, Stafford Horne, Guan Xuetao,
linux-arm-kernel, Chris Zankel, Tony Luck, Richard Weinberger,
linux-parisc, pantin, Max Filippov, minchan, Thomas Gleixner,
linux-alpha, Martin Schwidefsky, Ley Foon Tan, akpm, linuxppc-dev,
David S. Miller
In-Reply-To: <20181012013756.11285-2-joel@joelfernandes.org>
On 10/12/2018 03:37 AM, Joel Fernandes (Google) wrote:
> Android needs to mremap large regions of memory during memory management
> related operations. The mremap system call can be really slow if THP is
> not enabled. The bottleneck is move_page_tables, which is copying each
> pte at a time, and can be really slow across a large map. Turning on THP
> may not be a viable option, and is not for us. This patch speeds up the
> performance for non-THP system by copying at the PMD level when possible.
>
> The speed up is three orders of magnitude. On a 1GB mremap, the mremap
> completion times drops from 160-250 millesconds to 380-400 microseconds.
>
> Before:
> Total mremap time for 1GB data: 242321014 nanoseconds.
> Total mremap time for 1GB data: 196842467 nanoseconds.
> Total mremap time for 1GB data: 167051162 nanoseconds.
>
> After:
> Total mremap time for 1GB data: 385781 nanoseconds.
> Total mremap time for 1GB data: 388959 nanoseconds.
> Total mremap time for 1GB data: 402813 nanoseconds.
>
> Incase THP is enabled, the optimization is skipped. I also flush the
> tlb every time we do this optimization since I couldn't find a way to
> determine if the low-level PTEs are dirty. It is seen that the cost of
> doing so is not much compared the improvement, on both x86-64 and arm64.
>
> Cc: minchan@kernel.org
> Cc: pantin@google.com
> Cc: hughd@google.com
> Cc: lokeshgidra@google.com
> Cc: dancol@google.com
> Cc: mhocko@kernel.org
> Cc: kirill@shutemov.name
> Cc: akpm@linux-foundation.org
> Signed-off-by: Joel Fernandes (Google) <joel@joelfernandes.org>
> ---
> mm/mremap.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/mm/mremap.c b/mm/mremap.c
> index 9e68a02a52b1..d82c485822ef 100644
> --- a/mm/mremap.c
> +++ b/mm/mremap.c
> @@ -191,6 +191,54 @@ static void move_ptes(struct vm_area_struct *vma, pmd_t *old_pmd,
> drop_rmap_locks(vma);
> }
>
> +static bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
> + unsigned long new_addr, unsigned long old_end,
> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
> +{
> + spinlock_t *old_ptl, *new_ptl;
> + struct mm_struct *mm = vma->vm_mm;
> +
> + if ((old_addr & ~PMD_MASK) || (new_addr & ~PMD_MASK)
> + || old_end - old_addr < PMD_SIZE)
> + return false;
> +
> + /*
> + * The destination pmd shouldn't be established, free_pgtables()
> + * should have release it.
> + */
> + if (WARN_ON(!pmd_none(*new_pmd)))
> + return false;
> +
> + /*
> + * We don't have to worry about the ordering of src and dst
> + * ptlocks because exclusive mmap_sem prevents deadlock.
> + */
> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
> + if (old_ptl) {
> + pmd_t pmd;
> +
> + new_ptl = pmd_lockptr(mm, new_pmd);
> + if (new_ptl != old_ptl)
> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
> +
> + /* Clear the pmd */
> + pmd = *old_pmd;
> + pmd_clear(old_pmd);
Adding Martin Schwidefsky.
Is this mapping maybe still in use on other CPUs? If yes, I think for
s390 we need to flush here as well (in other word we might need to introduce
pmd_clear_flush). On s390 you have to use instructions like CRDTE,IPTE or IDTE
to modify page table entries that are still in use. Otherwise you can get a
delayed access exception which is - in contrast to page faults - not recoverable.
> +
> + VM_BUG_ON(!pmd_none(*new_pmd));
> +
> + /* Set the new pmd */
> + set_pmd_at(mm, new_addr, new_pmd, pmd);
> + if (new_ptl != old_ptl)
> + spin_unlock(new_ptl);
> + spin_unlock(old_ptl);
> +
> + *need_flush = true;
> + return true;
> + }
> + return false;
> +}
> +
> unsigned long move_page_tables(struct vm_area_struct *vma,
> unsigned long old_addr, struct vm_area_struct *new_vma,
> unsigned long new_addr, unsigned long len,
> @@ -239,7 +287,21 @@ unsigned long move_page_tables(struct vm_area_struct *vma,
> split_huge_pmd(vma, old_pmd, old_addr);
> if (pmd_trans_unstable(old_pmd))
> continue;
> + } else if (extent == PMD_SIZE) {
> + bool moved;
> +
> + /* See comment in move_ptes() */
> + if (need_rmap_locks)
> + take_rmap_locks(vma);
> + moved = move_normal_pmd(vma, old_addr, new_addr,
> + old_end, old_pmd, new_pmd,
> + &need_flush);
> + if (need_rmap_locks)
> + drop_rmap_locks(vma);
> + if (moved)
> + continue;
> }
> +
> if (pte_alloc(new_vma->vm_mm, new_pmd))
> break;
> next = (new_addr + PMD_SIZE) & PMD_MASK;
>
^ permalink raw reply
* Re: [PATCH] powerpc/traps: restore recoverability of machine_check interrupts
From: Christophe LEROY @ 2018-10-15 7:40 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, npiggin
Cc: linuxppc-dev, linux-kernel, stable@vger.kernel.org
In-Reply-To: <f79824d5da910441ede885fa32a25083c4cc9359.1539422122.git.christophe.leroy@c-s.fr>
Cc: stable@vger.kernel.org <stable@vger.kernel.org>
Le 13/10/2018 à 11:16, Christophe Leroy a écrit :
> commit b96672dd840f ("powerpc: Machine check interrupt is a non-
> maskable interrupt") added a call to nmi_enter() at the beginning of
> machine check restart exception handler. Due to that, in_interrupt()
> always returns true regardless of the state before entering the
> exception, and die() panics even when the system was not already in
> interrupt.
>
> This patch calls nmi_exit() before calling die() in order to restore
> the interrupt state we had before calling nmi_enter()
>
> Fixes: b96672dd840f ("powerpc: Machine check interrupt is a non-maskable interrupt")
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/kernel/traps.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> index fd58749b4d6b..4f880c2a6e4c 100644
> --- a/arch/powerpc/kernel/traps.c
> +++ b/arch/powerpc/kernel/traps.c
> @@ -765,12 +765,17 @@ void machine_check_exception(struct pt_regs *regs)
> if (check_io_access(regs))
> goto bail;
>
> - die("Machine check", regs, SIGBUS);
> -
> /* Must die if the interrupt is not recoverable */
> if (!(regs->msr & MSR_RI))
> nmi_panic(regs, "Unrecoverable Machine check");
>
> + if (!nested)
> + nmi_exit();
> +
> + die("Machine check", regs, SIGBUS);
> +
> + return;
> +
> bail:
> if (!nested)
> nmi_exit();
>
^ permalink raw reply
* [PATCH] powerpc/traps: remove redundant in_interrupt panic in die()
From: Christophe Leroy @ 2018-10-15 7:38 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
do_exit() already includes a test to panic() is in_interrupt()
This patch removes powerpc one which is redundant.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/traps.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 39fde4b40b6e..47904cd1ff46 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -247,8 +247,6 @@ static void oops_end(unsigned long flags, struct pt_regs *regs,
mdelay(MSEC_PER_SEC);
}
- if (in_interrupt())
- panic("Fatal exception in interrupt");
if (panic_on_oops)
panic("Fatal exception");
do_exit(signr);
--
2.13.3
^ permalink raw reply related
* Re: [PATCH kernel RFC 0/3] powerpc/pseries/iommu: GPU coherent memory pass through
From: Alexey Kardashevskiy @ 2018-10-15 7:29 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kvm-ppc, David Gibson
In-Reply-To: <cc415da6-74e9-536c-9065-5b2f0a10f5a1@ozlabs.ru>
Ping?
On 17/09/2018 17:05, Alexey Kardashevskiy wrote:
> Ping?
>
> The problem is still there...
>
>
> On 24/08/2018 13:04, Alexey Kardashevskiy wrote:
>>
>>
>> On 09/08/2018 14:41, Alexey Kardashevskiy wrote:
>>>
>>>
>>> On 25/07/2018 19:50, Alexey Kardashevskiy wrote:
>>>> I am trying to pass through a 3D controller:
>>>> [0302]: NVIDIA Corporation GV100GL [Tesla V100 SXM2] [10de:1db1] (rev a1)
>>>>
>>>> which has a quite unique feature as coherent memory directly accessible
>>>> from a POWER9 CPU via an NVLink2 transport.
>>>>
>>>> So in addition to passing a PCI device + accompanying NPU devices,
>>>> we will also be passing the host physical address range as it is done
>>>> on the bare metal system.
>>>>
>>>> The memory on the host is presented as:
>>>>
>>>> ===
>>>> [aik@yc02goos ~]$ lsprop /proc/device-tree/memory@42000000000
>>>> ibm,chip-id 000000fe (254)
>>>> device_type "memory"
>>>> compatible "ibm,coherent-device-memory"
>>>> reg 00000420 00000000 00000020 00000000
>>>> linux,usable-memory
>>>> 00000420 00000000 00000000 00000000
>>>> phandle 00000726 (1830)
>>>> name "memory"
>>>> ibm,associativity
>>>> 00000004 000000fe 000000fe 000000fe 000000fe
>>>> ===
>>>>
>>>> and the host does not touch it as the second 64bit value of
>>>> "linux,usable-memory" - the size - is null. Later on the NVIDIA driver
>>>> trains the NVLink2 and probes this memory and this is how it becomes
>>>> onlined.
>>>>
>>>> In the virtual environment I am planning on doing the same thing,
>>>> however there is a difference in 64bit DMA handling. The powernv
>>>> platform uses a PHB3 bypass mode and that just works but
>>>> the pseries platform uses DDW RTAS API to achieve the same
>>>> result and the problem with this is that we need a huge DMA
>>>> window to start from zero (because this GPU supports less than
>>>> 50bits for DMA address space) and cover not just present memory
>>>> but also this new coherent memory.
>>>>
>>>>
>>>> This is based on sha1
>>>> d72e90f3 Linus Torvalds "Linux 4.18-rc6".
>>>>
>>>> Please comment. Thanks.
>>>
>>>
>>> Ping?
>>
>>
>> Ping?
>>
>>>
>>>
>>>>
>>>>
>>>>
>>>> Alexey Kardashevskiy (3):
>>>> powerpc/pseries/iommu: Allow dynamic window to start from zero
>>>> powerpc/pseries/iommu: Force default DMA window removal
>>>> powerpc/pseries/iommu: Use memory@ nodes in max RAM address
>>>> calculation
>>>>
>>>> arch/powerpc/platforms/pseries/iommu.c | 77 ++++++++++++++++++++++++++++++----
>>>> 1 file changed, 70 insertions(+), 7 deletions(-)
>>>>
>>>
>>
>
--
Alexey
^ permalink raw reply
* [PATCH] powerpc/traps: fix machine check handlers to use pr_cont()
From: Christophe Leroy @ 2018-10-15 7:20 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
When printing the machine check cause, the cause appears on the
following line due to bad use of printk without \n:
[ 33.663993] Machine check in kernel mode.
[ 33.664011] Caused by (from SRR1=9032):
[ 33.664036] Data access error at address c90c8000
This patch fixes it by using pr_cont() for the second part:
[ 133.258131] Machine check in kernel mode.
[ 133.258146] Caused by (from SRR1=9032): Data access error at address c90c8000
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/traps.c | 78 +++++++++++++++---------------
arch/powerpc/platforms/8xx/machine_check.c | 4 +-
2 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 4f880c2a6e4c..39fde4b40b6e 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -535,10 +535,10 @@ int machine_check_e500mc(struct pt_regs *regs)
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
- printk("Machine Check Signal\n");
+ pr_cont("Machine Check Signal\n");
if (reason & MCSR_ICPERR) {
- printk("Instruction Cache Parity Error\n");
+ pr_cont("Instruction Cache Parity Error\n");
/*
* This is recoverable by invalidating the i-cache.
@@ -556,7 +556,7 @@ int machine_check_e500mc(struct pt_regs *regs)
}
if (reason & MCSR_DCPERR_MC) {
- printk("Data Cache Parity Error\n");
+ pr_cont("Data Cache Parity Error\n");
/*
* In write shadow mode we auto-recover from the error, but it
@@ -575,38 +575,38 @@ int machine_check_e500mc(struct pt_regs *regs)
}
if (reason & MCSR_L2MMU_MHIT) {
- printk("Hit on multiple TLB entries\n");
+ pr_cont("Hit on multiple TLB entries\n");
recoverable = 0;
}
if (reason & MCSR_NMI)
- printk("Non-maskable interrupt\n");
+ pr_cont("Non-maskable interrupt\n");
if (reason & MCSR_IF) {
- printk("Instruction Fetch Error Report\n");
+ pr_cont("Instruction Fetch Error Report\n");
recoverable = 0;
}
if (reason & MCSR_LD) {
- printk("Load Error Report\n");
+ pr_cont("Load Error Report\n");
recoverable = 0;
}
if (reason & MCSR_ST) {
- printk("Store Error Report\n");
+ pr_cont("Store Error Report\n");
recoverable = 0;
}
if (reason & MCSR_LDG) {
- printk("Guarded Load Error Report\n");
+ pr_cont("Guarded Load Error Report\n");
recoverable = 0;
}
if (reason & MCSR_TLBSYNC)
- printk("Simultaneous tlbsync operations\n");
+ pr_cont("Simultaneous tlbsync operations\n");
if (reason & MCSR_BSL2_ERR) {
- printk("Level 2 Cache Error\n");
+ pr_cont("Level 2 Cache Error\n");
recoverable = 0;
}
@@ -616,7 +616,7 @@ int machine_check_e500mc(struct pt_regs *regs)
addr = mfspr(SPRN_MCAR);
addr |= (u64)mfspr(SPRN_MCARU) << 32;
- printk("Machine Check %s Address: %#llx\n",
+ pr_cont("Machine Check %s Address: %#llx\n",
reason & MCSR_MEA ? "Effective" : "Physical", addr);
}
@@ -640,29 +640,29 @@ int machine_check_e500(struct pt_regs *regs)
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
- printk("Machine Check Signal\n");
+ pr_cont("Machine Check Signal\n");
if (reason & MCSR_ICPERR)
- printk("Instruction Cache Parity Error\n");
+ pr_cont("Instruction Cache Parity Error\n");
if (reason & MCSR_DCP_PERR)
- printk("Data Cache Push Parity Error\n");
+ pr_cont("Data Cache Push Parity Error\n");
if (reason & MCSR_DCPERR)
- printk("Data Cache Parity Error\n");
+ pr_cont("Data Cache Parity Error\n");
if (reason & MCSR_BUS_IAERR)
- printk("Bus - Instruction Address Error\n");
+ pr_cont("Bus - Instruction Address Error\n");
if (reason & MCSR_BUS_RAERR)
- printk("Bus - Read Address Error\n");
+ pr_cont("Bus - Read Address Error\n");
if (reason & MCSR_BUS_WAERR)
- printk("Bus - Write Address Error\n");
+ pr_cont("Bus - Write Address Error\n");
if (reason & MCSR_BUS_IBERR)
- printk("Bus - Instruction Data Error\n");
+ pr_cont("Bus - Instruction Data Error\n");
if (reason & MCSR_BUS_RBERR)
- printk("Bus - Read Data Bus Error\n");
+ pr_cont("Bus - Read Data Bus Error\n");
if (reason & MCSR_BUS_WBERR)
- printk("Bus - Write Data Bus Error\n");
+ pr_cont("Bus - Write Data Bus Error\n");
if (reason & MCSR_BUS_IPERR)
- printk("Bus - Instruction Parity Error\n");
+ pr_cont("Bus - Instruction Parity Error\n");
if (reason & MCSR_BUS_RPERR)
- printk("Bus - Read Parity Error\n");
+ pr_cont("Bus - Read Parity Error\n");
return 0;
}
@@ -680,19 +680,19 @@ int machine_check_e200(struct pt_regs *regs)
printk("Caused by (from MCSR=%lx): ", reason);
if (reason & MCSR_MCP)
- printk("Machine Check Signal\n");
+ pr_cont("Machine Check Signal\n");
if (reason & MCSR_CP_PERR)
- printk("Cache Push Parity Error\n");
+ pr_cont("Cache Push Parity Error\n");
if (reason & MCSR_CPERR)
- printk("Cache Parity Error\n");
+ pr_cont("Cache Parity Error\n");
if (reason & MCSR_EXCP_ERR)
- printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
+ pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
if (reason & MCSR_BUS_IRERR)
- printk("Bus - Read Bus Error on instruction fetch\n");
+ pr_cont("Bus - Read Bus Error on instruction fetch\n");
if (reason & MCSR_BUS_DRERR)
- printk("Bus - Read Bus Error on data load\n");
+ pr_cont("Bus - Read Bus Error on data load\n");
if (reason & MCSR_BUS_WRERR)
- printk("Bus - Write Bus Error on buffered store or cache line push\n");
+ pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
return 0;
}
@@ -705,30 +705,30 @@ int machine_check_generic(struct pt_regs *regs)
printk("Caused by (from SRR1=%lx): ", reason);
switch (reason & 0x601F0000) {
case 0x80000:
- printk("Machine check signal\n");
+ pr_cont("Machine check signal\n");
break;
case 0: /* for 601 */
case 0x40000:
case 0x140000: /* 7450 MSS error and TEA */
- printk("Transfer error ack signal\n");
+ pr_cont("Transfer error ack signal\n");
break;
case 0x20000:
- printk("Data parity error signal\n");
+ pr_cont("Data parity error signal\n");
break;
case 0x10000:
- printk("Address parity error signal\n");
+ pr_cont("Address parity error signal\n");
break;
case 0x20000000:
- printk("L1 Data Cache error\n");
+ pr_cont("L1 Data Cache error\n");
break;
case 0x40000000:
- printk("L1 Instruction Cache error\n");
+ pr_cont("L1 Instruction Cache error\n");
break;
case 0x00100000:
- printk("L2 data cache parity error\n");
+ pr_cont("L2 data cache parity error\n");
break;
default:
- printk("Unknown values in msr\n");
+ pr_cont("Unknown values in msr\n");
}
return 0;
}
diff --git a/arch/powerpc/platforms/8xx/machine_check.c b/arch/powerpc/platforms/8xx/machine_check.c
index 402016705a39..9944fc303df0 100644
--- a/arch/powerpc/platforms/8xx/machine_check.c
+++ b/arch/powerpc/platforms/8xx/machine_check.c
@@ -18,9 +18,9 @@ int machine_check_8xx(struct pt_regs *regs)
pr_err("Machine check in kernel mode.\n");
pr_err("Caused by (from SRR1=%lx): ", reason);
if (reason & 0x40000000)
- pr_err("Fetch error at address %lx\n", regs->nip);
+ pr_cont("Fetch error at address %lx\n", regs->nip);
else
- pr_err("Data access error at address %lx\n", regs->dar);
+ pr_cont("Data access error at address %lx\n", regs->dar);
#ifdef CONFIG_PCI
/* the qspan pci read routines can cause machine checks -- Cort
--
2.13.3
^ permalink raw reply related
* Re: [PATCH kernel v2] powerpc/ioda/npu: Call skiboot's hot reset hook when disabling NPU2
From: Alexey Kardashevskiy @ 2018-10-15 7:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alistair Popple, Reza Arbab, David Gibson
In-Reply-To: <20181002032021.7126-1-aik@ozlabs.ru>
Ping?
On 02/10/2018 13:20, Alexey Kardashevskiy wrote:
> The skiboot firmware has a hot reset handler which fences the NVIDIA V100
> GPU RAM on Witherspoons and makes accesses no-op instead of throwing HMIs:
> https://github.com/open-power/skiboot/commit/fca2b2b839a67
>
> Now we are going to pass V100 via VFIO which most certainly involves
> KVM guests which are often terminated without getting a chance to offline
> GPU RAM so we end up with a running machine with misconfigured memory.
> Accessing this memory produces hardware management interrupts (HMI)
> which bring the host down.
>
> To suppress HMIs, this wires up this hot reset hook to vfio_pci_disable()
> via pci_disable_device() which switches NPU2 to a safe mode and prevents
> HMIs.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
> ---
> Changes:
> v2:
> * updated the commit log
> ---
> arch/powerpc/platforms/powernv/pci-ioda.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
> index cde7102..e37b9cc 100644
> --- a/arch/powerpc/platforms/powernv/pci-ioda.c
> +++ b/arch/powerpc/platforms/powernv/pci-ioda.c
> @@ -3688,6 +3688,15 @@ static void pnv_pci_release_device(struct pci_dev *pdev)
> pnv_ioda_release_pe(pe);
> }
>
> +static void pnv_npu_disable_device(struct pci_dev *pdev)
> +{
> + struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
> + struct eeh_pe *eehpe = edev ? edev->pe : NULL;
> +
> + if (eehpe && eeh_ops && eeh_ops->reset)
> + eeh_ops->reset(eehpe, EEH_RESET_HOT);
> +}
> +
> static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
> {
> struct pnv_phb *phb = hose->private_data;
> @@ -3732,6 +3741,7 @@ static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
> .reset_secondary_bus = pnv_pci_reset_secondary_bus,
> .dma_set_mask = pnv_npu_dma_set_mask,
> .shutdown = pnv_pci_ioda_shutdown,
> + .disable_device = pnv_npu_disable_device,
> };
>
> static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
>
--
Alexey
^ permalink raw reply
* Re: move bus (PCI, PCMCIA, EISA, rapdio) config to drivers/
From: Masahiro Yamada @ 2018-10-15 6:38 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev
In-Reply-To: <20181013151016.31674-1-hch@lst.de>
On Sun, Oct 14, 2018 at 12:10 AM Christoph Hellwig <hch@lst.de> wrote:
>
> Hi all,
>
> currently every architecture that wants to provide on of the common
> periphal busses needs to add some boilerplate code and include the
> right Kconfig files. This series instead just selects the presence
> (when needed) and then handles everything in the bus-specific
> Kconfig file under drivers/.
>
Thanks for great work again.
However, I suspect some breakages
(not testing yet, just quick review by my eyes.)
I left some comments in individual patches.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Re: [PATCH 7/8] eisa: consolidate EISA Kconfig entry in drivers/eisa
From: Masahiro Yamada @ 2018-10-15 6:37 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev
In-Reply-To: <20181013151016.31674-8-hch@lst.de>
On Sun, Oct 14, 2018 at 12:11 AM Christoph Hellwig <hch@lst.de> wrote:
>
> Let architectures opt into EISA support by selecting HAS_EISA and
> handle everything else in drivers/eisa.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
How about HAVE_EISA ?
You forgot to add
source "drivers/eisa/Kconfig" to drivers/Kconfig
You forgot to delete the one
from arch/alpha/Kconfig
> arch/alpha/Kconfig | 8 +++-----
> arch/arm/Kconfig | 16 +---------------
> arch/mips/Kconfig | 31 +++++--------------------------
> arch/powerpc/Kconfig | 3 ---
> arch/x86/Kconfig | 19 +------------------
> drivers/eisa/Kconfig | 21 ++++++++++++++++++++-
> drivers/parisc/Kconfig | 11 +----------
> 7 files changed, 31 insertions(+), 78 deletions(-)
>
> diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
> index 73a7558c71bd..6a9be9cb74e6 100644
> --- a/arch/alpha/Kconfig
> +++ b/arch/alpha/Kconfig
> @@ -6,6 +6,9 @@ config ALPHA
> select ARCH_MIGHT_HAVE_PC_SERIO
> select ARCH_NO_PREEMPT
> select ARCH_USE_CMPXCHG_LOCKREF
> + select HAS_EISA if ALPHA_GENERIC || ALPHA_JENSEN || ALPHA_ALCOR || \
> + ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || \
> + ALPHA_NORITAKE || ALPHA_RAWHIDE
> select HAS_PCI if !ALPHA_JENSEN
> select PCI if !ALPHA_JENSEN
> select HAVE_AOUT
> @@ -518,11 +521,6 @@ config ALPHA_SRM
>
> If unsure, say N.
>
> -config EISA
> - bool
> - depends on ALPHA_GENERIC || ALPHA_JENSEN || ALPHA_ALCOR || ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_RAWHIDE
> - default y
> -
Better to add CONFIG_EISA=y to arch/alpha/defconfig
to not flip the default?
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Re: [PATCH 4/8] pci: consolidate PCI config entry in drivers/pci
From: Masahiro Yamada @ 2018-10-15 6:37 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev
In-Reply-To: <20181013151016.31674-5-hch@lst.de>
On Sun, Oct 14, 2018 at 12:11 AM Christoph Hellwig <hch@lst.de> wrote:
>
> There is no good reason to duplicate the PCI menu in every architecture.
> Instead provide a selectable HAS_PCI symbol that indicates availability
> of PCI support and the handle the rest in drivers/pci.
I think HAVE_ is a preferred prefix in this case according to this doc:
https://github.com/masahir0y/linux/blob/v4.19-rc4/Documentation/kbuild/kconfig-language.txt#L448
It is true we have some options with HAS_ prefix,
but the majority is HAVE_.
masahiro@pug:~/ref/linux$ find . -name 'Kconfig*' | xargs grep 'config
HAS_' | wc
9 18 355
masahiro@pug:~/ref/linux$ find . -name 'Kconfig*' | xargs grep 'config
HAVE_' | wc
177 354 8182
> Note that for powerpc we now select HAS_PCI globally instead of the
> convoluted mess of conditional or or non-conditional support per board,
> similar to what we do e.g. on x86. For alpha PCI is selected for the
> non-jensen configs as it was the default before, and a lot of code does
> not compile without PCI enabled. On other architectures with limited
> PCI support that wasn't as complicated I've left the selection as-is.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 6fa6f92edb7f..0713375e1127 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -168,10 +168,16 @@ config PPC
> select GENERIC_CPU_VULNERABILITIES if PPC_BARRIER_NOSPEC
> select GENERIC_IRQ_SHOW
> select GENERIC_IRQ_SHOW_LEVEL
> + select GENERIC_PCI_IOMAP if PCI
> select GENERIC_SMP_IDLE_THREAD
> select GENERIC_STRNCPY_FROM_USER
> select GENERIC_STRNLEN_USER
> select GENERIC_TIME_VSYSCALL
> + # Platforms that what PCI turned unconditionally just do select PCI
> + # in their config node, otherwise allow the user to enable it.
> + # This means we can enable PCI even on platforms that don't support
> + # it, which is harmless except for wasted memory.
> + select HAS_PCI
If you do this for entire powerpc,
the other 'select HAS_PCI' addtions to
arch/powerpc/platforms/*/Kconfig look redundant.
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index a344980287a5..6eb31a0698ac 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -38,6 +38,7 @@ config RISCV
> select RISCV_ISA_A if SMP
> select SPARSE_IRQ
> select SYSCTL_EXCEPTION_TRACE
> + select HAS_PCI
> select HAVE_ARCH_TRACEHOOK
> select MODULES_USE_ELF_RELA if MODULES
> select THREAD_INFO_IN_TASK
> @@ -216,28 +217,12 @@ source "kernel/Kconfig.hz"
>
> endmenu
>
> -menu "Bus support"
> -
> -config PCI
> - bool "PCI support"
> - select PCI_MSI
I think this 'select PCI_MSI' for riscv was lost.
> - help
> - This feature enables support for PCI bus system. If you say Y
> - here, the kernel will include drivers and infrastructure code
> - to support PCI bus devices.
> -
> - If you don't know what to do here, say Y.
> -
> config PCI_DOMAINS
> def_bool PCI
>
> config PCI_DOMAINS_GENERIC
> def_bool PCI
>
> -source "drivers/pci/Kconfig"
> -
> -endmenu
> -
> menu "Power management options"
>
> source kernel/power/Kconfig
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index 1a0be022f91d..7cbc656f47e7 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -113,6 +113,7 @@ config X86
> select GENERIC_STRNLEN_USER
> select GENERIC_TIME_VSYSCALL
> select HARDLOCKUP_CHECK_TIMESTAMP if X86_64
> + select HAS_PCI
> select HAVE_ACPI_APEI if ACPI
> select HAVE_ACPI_APEI_NMI if ACPI
> select HAVE_ALIGNED_STRUCT_PAGE if SLUB
> @@ -2567,15 +2568,6 @@ endmenu
>
> menu "Bus options (PCI etc.)"
>
> -config PCI
> - bool "PCI support"
> - default y
The default is y for x86 (and xtensa as well).
With this patch, the default will be flipped.
I think most of people want to use PCI for x86,
and this change will make people upset.
Will you update arch/{x86,xtensa}/configs/*_defconfig?
> - ---help---
> - Find out whether you have a PCI motherboard. PCI is the name of a
> - bus system, i.e. the way the CPU talks to the other stuff inside
> - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
> - VESA. If you have PCI, say Y, otherwise N.
> -
> choice
> prompt "PCI access mode"
> depends on X86_32 && PCI
> @@ -2658,8 +2650,6 @@ config PCI_CNB20LE_QUIRK
>
> You should say N unless you know you need this.
>
> -source "drivers/pci/Kconfig"
> -
> config ISA_BUS
> bool "ISA bus support on modern systems" if EXPERT
> help
> diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
> index b9ad83a0ee5d..22abeb236863 100644
> --- a/arch/xtensa/Kconfig
> +++ b/arch/xtensa/Kconfig
> @@ -20,6 +20,7 @@ config XTENSA
> select GENERIC_PCI_IOMAP
> select GENERIC_SCHED_CLOCK
> select GENERIC_STRNCPY_FROM_USER if KASAN
> + select HAS_PCI
> select HAVE_ARCH_KASAN if MMU
> select HAVE_DEBUG_KMEMLEAK
> select HAVE_DMA_CONTIGUOUS
> @@ -384,21 +385,6 @@ config XTENSA_CALIBRATE_CCOUNT
> config SERIAL_CONSOLE
> def_bool n
>
> -menu "Bus options"
> -
> -config PCI
> - bool "PCI support"
> - default y
> - help
> - Find out whether you have a PCI motherboard. PCI is the name of a
> - bus system, i.e. the way the CPU talks to the other stuff inside
> - your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
> - VESA. If you have PCI, say Y, otherwise N.
> -
> -source "drivers/pci/Kconfig"
> -
> -endmenu
> -
> menu "Platform options"
>
> choice
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index ab4d43923c4d..059573823387 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -1,7 +1,11 @@
> # SPDX-License-Identifier: GPL-2.0
> menu "Device Drivers"
>
> +# Keep I/O buses first
> +
> source "drivers/amba/Kconfig"
> +source "drivers/pci/Kconfig"
> +
>
> source "drivers/base/Kconfig"
>
> diff --git a/drivers/parisc/Kconfig b/drivers/parisc/Kconfig
> index 5a48b5606110..5bbfea1a019c 100644
> --- a/drivers/parisc/Kconfig
> +++ b/drivers/parisc/Kconfig
> @@ -63,17 +63,6 @@ config ISA
> If you want to plug an ISA card into your EISA bus, say Y here.
> Most people should say N.
>
> -config PCI
> - bool "PCI support"
> - help
> - All recent HP machines have PCI slots, and you should say Y here
> - if you have a recent machine. If you are convinced you do not have
> - PCI slots in your machine (eg a 712), then you may say "N" here.
> - Beware that some GSC cards have a Dino onboard and PCI inside them,
> - so it may be safest to say "Y" anyway.
> -
> -source "drivers/pci/Kconfig"
> -
> config GSC_DINO
> bool "GSCtoPCI/Dino PCI support"
> depends on PCI && GSC
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index 56ff8f6d31fc..229a518b68cd 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -3,6 +3,18 @@
> # PCI configuration
> #
>
> +config HAS_PCI
> + bool
> +
> +menuconfig PCI
> + bool "PCI support"
> + depends on HAS_PCI
> +
> + help
> + This option enables support for the PCI local bus, including
> + support for PCI-X and the fundations for PCI Express support.
> + Say 'Y' here unless you know what you are doing.
> +
> source "drivers/pci/pcie/Kconfig"
>
> config PCI_MSI
> --
> 2.19.1
>
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH] powerpc/book3s64: fix dump_linuxpagetables "present" flag
From: Christophe Leroy @ 2018-10-15 6:37 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
Since commit bd0dbb73e013 ("powerpc/mm/books3s: Add new pte bit to
mark pte temporarily invalid."), _PAGE_PRESENT doesn't mean exactly
that a page is present. A page is also considered preset when
_PAGE_INVALID is set.
This patch changes the meaning of "present" and adds a status "valid"
associated to the _PAGE_PRESENT flag.
Fixes: bd0dbb73e013 ("powerpc/mm/books3s: Add new pte bit to mark pte temporarily invalid.")
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/mm/dump_linuxpagetables-book3s64.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c b/arch/powerpc/mm/dump_linuxpagetables-book3s64.c
index a637e612b205..ed6fcf78256e 100644
--- a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c
+++ b/arch/powerpc/mm/dump_linuxpagetables-book3s64.c
@@ -38,8 +38,13 @@ static const struct flag_info flag_array[] = {
}, {
.mask = _PAGE_PRESENT,
.val = _PAGE_PRESENT,
- .set = "present",
- .clear = " ",
+ .set = "valid",
+ .clear = " ",
+ }, {
+ .mask = _PAGE_PRESENT | _PAGE_INVALID,
+ .val = 0,
+ .set = " ",
+ .clear = "present",
}, {
.mask = H_PAGE_HASHPTE,
.val = H_PAGE_HASHPTE,
--
2.13.3
^ permalink raw reply related
* Re: [PATCH 2/8] powerpc: simplify CONFIG_PCI_QSPAN Kconfig magic
From: Masahiro Yamada @ 2018-10-15 6:35 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, linux-scsi, Linux Kbuild mailing list, linux-pci,
Linux Kernel Mailing List, Dominik Brodowski, alex.bou9,
linuxppc-dev
In-Reply-To: <20181013151016.31674-3-hch@lst.de>
On Sun, Oct 14, 2018 at 12:11 AM Christoph Hellwig <hch@lst.de> wrote:
>
> The way how CONFIG_PCI_QSPAN selects the CONFIG_PCI default is highly
> unusual and gets in the way of moving CONFIG_PCI into
> drivers/pci/Kconfig. Simplify it by just having it depend on
> CONFIG_PCI.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/powerpc/Kconfig | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index a80669209155..6fa6f92edb7f 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -955,7 +955,6 @@ config PCI
> bool "PCI support" if PPC_PCI_CHOICE
> default y if !40x && !CPM2 && !PPC_8xx && !PPC_83xx \
> && !PPC_85xx && !PPC_86xx && !GAMECUBE_COMMON
> - default PCI_QSPAN if PPC_8xx
> select GENERIC_PCI_IOMAP
> help
> Find out whether your system includes a PCI bus. PCI is the name of
> @@ -971,7 +970,7 @@ config PCI_SYSCALL
>
> config PCI_QSPAN
> bool "QSpan PCI"
> - depends on PPC_8xx
> + depends on PPC_8xx && PCI
> select PPC_I8259
> help
> Say Y here if you have a system based on a Motorola 8xx-series
> --
> 2.19.1
>
'git grep' did not get any other hit.
masahiro@pug:~/ref/linux$ git grep PCI_QSPAN
arch/powerpc/Kconfig: default PCI_QSPAN if PPC_8xx
arch/powerpc/Kconfig:config PCI_QSPAN
With your patch, PCI_QSPAN will become
a dead config option.
How about removing it entirely?
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* Re: [PATCH 16/33] powerpc/powernv: remove dead npu-dma code
From: Christoph Hellwig @ 2018-10-15 5:50 UTC (permalink / raw)
To: Alexey Kardashevskiy
Cc: linux-arch, linux-kernel, linux-mm, iommu, Paul Mackerras,
linuxppc-dev, Christoph Hellwig
In-Reply-To: <7709932d-efb8-2c9b-5128-99cc491c302b@ozlabs.ru>
On Mon, Oct 15, 2018 at 12:34:02PM +1100, Alexey Kardashevskiy wrote:
>
> On 10/10/2018 00:24, Christoph Hellwig wrote:
> > This code has been unused since it was merged and is in the way of
> > cleaning up the DMA code, thus remove it.
> >
> > This effectively reverts commit 5d2aa710 ("powerpc/powernv: Add support
> > for Nvlink NPUs").
>
>
> This code is heavily used by the NVIDIA GPU driver.
Not by the that actually exists in the kernel tree, so it simply doesn't
matter.
^ permalink raw reply
* [PATCH v5 6/6] arm64: dts: add LX2160ARDB board support
From: Vabhav Sharma @ 2018-10-14 17:08 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, Horia Geanta, udit.kumar, Priyanka Jain,
pankaj.bansal, Zhang Ying-22455, linux, adrian.hunter, V.Sethi,
Vabhav Sharma, Sriram Dash, Ran Wang, Yinbo Zhu
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 119 ++++++++++++++++++++++
2 files changed, 120 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18ad..445b72b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..6481e5f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160ARDB
+//
+// Copyright 2018 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160ARDB";
+ compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "MC34717-3.3VSB";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ power-monitor@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ vcc-supply = <&sb_3v3>;
+ };
+
+ temperature-sensor@4d {
+ compatible = "nxp,sa56004";
+ reg = <0x4d>;
+ vcc-supply = <&sb_3v3>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ // IRQ10_B
+ interrupts = <0 150 0x4>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v5 5/6] arm64: dts: add QorIQ LX2160A SoC support
From: Vabhav Sharma @ 2018-10-14 17:08 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, Yogesh Gaur, Horia Geanta, udit.kumar, Priyanka Jain,
pankaj.bansal, Zhang Ying-22455, linux, adrian.hunter,
Ramneek Mehresh, V.Sethi, Vabhav Sharma, Nipun Gupta, Sriram Dash,
Ran Wang, Yinbo Zhu
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 765 +++++++++++++++++++++++++
1 file changed, 765 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
index 0000000..56f846c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -0,0 +1,765 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,lx2160a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // 8 clusters having 2 Cortex-A72 cores each
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x100>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x101>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x200>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x201>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x300>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x301>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x400>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x401>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x500>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x501>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x600>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x601>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x700>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x701>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster2_l2: l2-cache2 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster3_l2: l2-cache3 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster4_l2: l2-cache4 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster5_l2: l2-cache5 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster6_l2: l2-cache6 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster7_l2: l2-cache7 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
+ <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
+ // SGI_base)
+ <0x0 0x0c0c0000 0 0x2000>, // GICC
+ <0x0 0x0c0d0000 0 0x1000>, // GICH
+ <0x0 0x0c0e0000 0 0x20000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x6020000 0 0x20000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ memory@80000000 {
+ // DRAM space - 1, size : 2 GB DRAM
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ };
+
+ ddr1: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ ddr2: memory-controller@1090000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1090000 0x0 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ clockgen: clock-controller@1300000 {
+ compatible = "fsl,lx2160a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dcfg: syscon@1e00000 {
+ compatible = "fsl,lx2160a-dcfg", "syscon";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ little-endian;
+ };
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ broken-cd;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ uart0: serial@21c0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart1: serial@21d0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart2: serial@21e0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart3: serial@21f0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-sec = <30>;
+ };
+
+ usb0: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ usb1: usb@3110000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ smmu: iommu@5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <14>;
+ // global secure fault
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ // combined secure
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ // global non-secure fault
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ // combined non-secure
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ // performance counter interrupts 0-9
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ // per context interrupt, 64 interrupts
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v5 4/6] clk: qoriq: Add clockgen support for lx2160a
From: Vabhav Sharma @ 2018-10-14 17:08 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, Yogesh Gaur, Tang Yuantian, udit.kumar,
pankaj.bansal, linux, adrian.hunter, V.Sethi, Vabhav Sharma
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/clk/clk-qoriq.c | 12 ++++++++++++
drivers/cpufreq/qoriq-cpufreq.c | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index e152bfb..99675de 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
},
{
+ .compat = "fsl,lx2160a-clockgen",
+ .cmux_groups = {
+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+ },
+ .cmux_to_group = {
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
+ },
+ .pll_mask = 0x37,
+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+ },
+ {
.compat = "fsl,p2041-clockgen",
.guts_compat = "fsl,qoriq-device-config-1.0",
.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
/* Legacy nodes */
CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = {
{ .compatible = "fsl,ls1046a-clockgen", },
{ .compatible = "fsl,ls1088a-clockgen", },
{ .compatible = "fsl,ls2080a-clockgen", },
+ { .compatible = "fsl,lx2160a-clockgen", },
{ .compatible = "fsl,p4080-clockgen", },
{ .compatible = "fsl,qoriq-clockgen-1.0", },
{ .compatible = "fsl,qoriq-clockgen-2.0", },
--
2.7.4
^ permalink raw reply related
* [PATCH v5 3/6] clk: qoriq: increase array size of cmux_to_group
From: Vabhav Sharma @ 2018-10-14 17:08 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, Yogesh Gaur, udit.kumar, pankaj.bansal, linux,
adrian.hunter, V.Sethi, Vabhav Sharma
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Increase size of cmux_to_group array, to accomdate entry of
-1 termination.
Added -1, terminated, entry for 4080_cmux_grpX.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
drivers/clk/clk-qoriq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..e152bfb 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
const struct clockgen_muxinfo *cmux_groups[2];
const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
void (*init_periph)(struct clockgen *cg);
- int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
+ int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
u32 pll_mask; /* 1 << n bit set if PLL n is valid */
u32 flags; /* CG_xxx */
};
@@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
&p4080_cmux_grp1, &p4080_cmux_grp2
},
.cmux_to_group = {
- 0, 0, 0, 0, 1, 1, 1, 1
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
},
.pll_mask = 0x1f,
},
--
2.7.4
^ permalink raw reply related
* [PATCH v5 2/6] soc/fsl/guts: Add definition for LX2160A
From: Vabhav Sharma @ 2018-10-14 17:07 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, udit.kumar, pankaj.bansal, linux, adrian.hunter,
V.Sethi, Vabhav Sharma, Yinbo Zhu
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160 and SoC die
attribute definition for LX2160A
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
drivers/soc/fsl/guts.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..bcab1ee 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -100,6 +100,11 @@ static const struct fsl_soc_die_attr fsl_soc_die[] = {
.svr = 0x87000000,
.mask = 0xfff70000,
},
+ /* Die: LX2160A, SoC: LX2160A/LX2120A/LX2080A */
+ { .die = "LX2160A",
+ .svr = 0x87360000,
+ .mask = 0xff3f0000,
+ },
{ },
};
@@ -222,6 +227,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1088a-dcfg", },
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
+ { .compatible = "fsl,lx2160a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
--
2.7.4
^ permalink raw reply related
* [PATCH v5 1/6] dt-bindings: arm64: add compatible for LX2160A
From: Vabhav Sharma @ 2018-10-14 17:07 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, udit.kumar, pankaj.bansal, linux, adrian.hunter,
V.Sethi, Vabhav Sharma
In-Reply-To: <1539536883-1928-1-git-send-email-vabhav.sharma@nxp.com>
Add compatible for LX2160A SoC,QDS and RDB board
Add lx2160a compatible for clockgen and dcfg
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/fsl.txt | 14 +++++++++++++-
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 8a1baa2..71adce2 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -130,7 +130,7 @@ core start address and release the secondary core from holdoff and startup.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a.
- reg : should contain base address and length of DCFG memory-mapped registers
@@ -222,3 +222,15 @@ Required root node properties:
LS2088A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
+
+LX2160A SoC
+Required root node properties:
+ - compatible = "fsl,lx2160a";
+
+LX2160A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
+
+LX2160A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 97f46ad..3fb9995 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -37,6 +37,7 @@ Required properties:
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
+ * "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
--
2.7.4
^ permalink raw reply related
* [PATCH v5 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC
From: Vabhav Sharma @ 2018-10-14 17:07 UTC (permalink / raw)
To: sudeep.holla, oss, linux-kernel, devicetree, robh+dt,
mark.rutland, linuxppc-dev, linux-arm-kernel, mturquette, sboyd,
rjw, viresh.kumar, linux-clk, linux-pm, linux-kernel-owner,
catalin.marinas, will.deacon, gregkh, arnd, kstewart,
yamada.masahiro, leoyang.li, shawnguo
Cc: ulf.hansson, udit.kumar, pankaj.bansal, linux, adrian.hunter,
V.Sethi, Vabhav Sharma
Changes for v5:
- Updated temperature sensor regulator name in board device tree
- Sorted nodes alphabatically and unit-address in SoC/board device tree
- Identation, new line update in SoC/board device tree
- Updated nodes name as per DT spec generic name recommendation in SoC DT
- Updated macro define for interrupt/gpio property
- Updated i2c node property name scl-gpio
- Removed device_type property except cpu/memory node
- Added esdhc controller nodes in SoC/RDB board device tree
- Added aliases for uart/crypto nodes
- Add SoC die attribute definition for LX2160A
Changes for v4:
- Updated bindings for lx2160a clockgen and dcfg
- Modified commit message for lx2160a clockgen changes
- Updated interrupt property with macro definition
- Added required enable-method property to each core node with psci value
- Removed unused node syscon in device tree
- Removed blank lines in device tree fsl-lx2160a.dtsi
- Updated uart node compatible sbsa-uart first
- Added and defined vcc-supply property to temperature sensor node in
device tree fsl-lx2160a-rdb.dts
Changes for v3:
-Split clockgen support patch into below two patches:
- a)Updated array size of cmux_to_group[] with NUM_CMUX+1 to include -1
terminator and p4080 cmux_to_group[] array with -1 terminator
- b)Add clockgen support for lx2160a
Changes for v2:
- Modified cmux_to_group array to include -1 terminator
- Revert NUM_CMUX to original value 8 from 16
- Remove “As LX2160A is 16 core, so modified value for NUM_CMUX”
in patch "[PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
lx2160a" description
- Populated cache properties for L1 and L2 cache in lx2160a device-tree.
- Removed reboot node from lx2160a device-tree as PSCI is implemented.
- Removed incorrect comment for timer node interrupt property in
lx2160a device-tree.
- Modified pmu node compatible property from "arm,armv8-pmuv3" to
"arm,cortex-a72-pmu" in lx2160a device-tree
- Non-standard aliases removed in lx2160a rdb board device-tree
- Updated i2c child nodes to generic name in lx2160a rdb device-tree.
Changes for v1:
- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
(Reference design board)
Vabhav Sharma (4):
dt-bindings: arm64: add compatible for LX2160A
soc/fsl/guts: Add definition for LX2160A
arm64: dts: add QorIQ LX2160A SoC support
arm64: dts: add LX2160ARDB board support
Yogesh Gaur (2):
clk: qoriq: increase array size of cmux_to_group
clk: qoriq: Add clockgen support for lx2160a
Documentation/devicetree/bindings/arm/fsl.txt | 14 +-
.../devicetree/bindings/clock/qoriq-clock.txt | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 119 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 765 +++++++++++++++++++++
drivers/clk/clk-qoriq.c | 16 +-
drivers/cpufreq/qoriq-cpufreq.c | 1 +
drivers/soc/fsl/guts.c | 6 +
8 files changed, 920 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
--
2.7.4
^ permalink raw reply
* [PATCH 09/12] powerpc/prom_init: Move a few remaining statics to appropriate sections
From: Benjamin Herrenschmidt @ 2018-10-15 2:49 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20181015025000.4522-1-benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/kernel/prom_init.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index cbd54fe30367..306562d4d818 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -173,7 +173,7 @@ static unsigned long __prombss prom_tce_alloc_end;
#endif
#ifdef CONFIG_PPC_PSERIES
-static bool prom_radix_disable __prombss;
+static bool __prombss prom_radix_disable;
#endif
struct platform_support {
@@ -210,7 +210,7 @@ static int __prombss mem_reserve_cnt;
static cell_t __prombss regbuf[1024];
-static bool rtas_has_query_cpu_stopped;
+static bool __prombss rtas_has_query_cpu_stopped;
/*
@@ -525,8 +525,8 @@ static void add_string(char **str, const char *q)
static char *tohex(unsigned int x)
{
- static char digits[] = "0123456789abcdef";
- static char result[9];
+ static const char digits[] __initconst = "0123456789abcdef";
+ static char result[9] __prombss;
int i;
result[8] = 0;
@@ -2324,7 +2324,7 @@ static void __init scan_dt_build_struct(phandle node, unsigned long *mem_start,
char *namep, *prev_name, *sstart, *p, *ep, *lp, *path;
unsigned long soff;
unsigned char *valp;
- static char pname[MAX_PROPERTY_NAME];
+ static char pname[MAX_PROPERTY_NAME] __prombss;
int l, room, has_phandle = 0;
dt_push_token(OF_DT_BEGIN_NODE, mem_start, mem_end);
--
2.17.1
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