* Re: [PATCH] net/wan/fsl_ucc_hdlc: add BQL support
From: David Miller @ 2018-10-23 17:56 UTC (permalink / raw)
To: mathias.thore; +Cc: netdev, linuxppc-dev, david.gounaris, qiang.zhao
In-Reply-To: <20181023114832.31350-1-mathias.thore@infinera.com>
From: Mathias Thore <mathias.thore@infinera.com>
Date: Tue, 23 Oct 2018 13:48:32 +0200
> Add byte queue limits support in the fsl_ucc_hdlc driver.
>
> Signed-off-by: Mathias Thore <mathias.thore@infinera.com>
> ---
>
> Note that this patch is created relative to another patch that was
> applied recently: net/wan/fsl_ucc_hdlc: error counters
net-next is closed, please resubmit this when net-next opens back up.
Thank you.
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Joakim Tjernlund @ 2018-10-23 18:02 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org, netdev@vger.kernel.org,
f.fainelli@gmail.com
Cc: andrew@lunn.ch
In-Reply-To: <518e0cf1-ef7e-b251-a153-34e01a80267d@gmail.com>
On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
> > SPI (and others) has a way to define bus number in a aliases:
> > aliases {
> > ethernet4 = &enet4;
> > ethernet0 = &enet0;
> > ethernet1 = &enet1;
> > ethernet2 = &enet2;
> > ethernet3 = &enet3;
> > spi0 = &spi0
> > };
> > The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
> > I am looking for the same for ethernet devices:
> > ethernet4 = &enet4; /* should become eth4 */
> > ethernet0 = &enet0; /* should become eth0 */
> > but I cannot find something like that for eth devices.
> >
> > Could such functionality be added?
>
> It could, do we want and need to, no. You have the Ethernet alias in
> /sys/class/net/*/device/uevent already that would allow you to perform
> that (re)naming in user-space:
>
> # cat /sys/class/net/eth0/device/uevent
> DRIVER=bcmgenet
> OF_NAME=ethernet
> OF_FULLNAME=/rdb/ethernet@f0480000
> OF_TYPE=network
> OF_COMPATIBLE_0=brcm,genet-v5
> OF_COMPATIBLE_N=1
> OF_ALIAS_0=eth0 <==================
> MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
Yes, one can if one uses udev and can find something to identify the hw I/F with, my
cat /sys/class/net/eth0/device/uevent looks like:
DRIVER=fsl_dpa
MODALIAS=platform:dpaa-ethernet
not sure mdev supports this, does it?
Our simple installer FS(initramfs) doesn't have either udev or mdev.
I also noted that using status = "disabled" didn't work either to create a fix name scheme.
Even worse, all the eth I/F after gets renumbered. It seems to me there
is value in having stability in eth I/F naming at boot.
Then userspace(udev) can rename if need be.
Sure would like to known more about why this feature is not wanted ?
I found
https://patchwork.kernel.org/patch/4122441/
You quote policy as reason but surely it must be better to
have something stable, connected to the hardware name, than semirandom naming?
Jocke
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Florian Fainelli @ 2018-10-23 18:20 UTC (permalink / raw)
To: Joakim Tjernlund, linuxppc-dev@lists.ozlabs.org,
netdev@vger.kernel.org
Cc: andrew@lunn.ch
In-Reply-To: <694b6f4f6b66eb35176e3eb48bbec474c9647007.camel@infinera.com>
On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
> On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
>> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>>
>>
>> On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
>>> SPI (and others) has a way to define bus number in a aliases:
>>> aliases {
>>> ethernet4 = &enet4;
>>> ethernet0 = &enet0;
>>> ethernet1 = &enet1;
>>> ethernet2 = &enet2;
>>> ethernet3 = &enet3;
>>> spi0 = &spi0
>>> };
>>> The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
>>> I am looking for the same for ethernet devices:
>>> ethernet4 = &enet4; /* should become eth4 */
>>> ethernet0 = &enet0; /* should become eth0 */
>>> but I cannot find something like that for eth devices.
>>>
>>> Could such functionality be added?
>>
>> It could, do we want and need to, no. You have the Ethernet alias in
>> /sys/class/net/*/device/uevent already that would allow you to perform
>> that (re)naming in user-space:
>>
>> # cat /sys/class/net/eth0/device/uevent
>> DRIVER=bcmgenet
>> OF_NAME=ethernet
>> OF_FULLNAME=/rdb/ethernet@f0480000
>> OF_TYPE=network
>> OF_COMPATIBLE_0=brcm,genet-v5
>> OF_COMPATIBLE_N=1
>> OF_ALIAS_0=eth0 <==================
>> MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
>
> Yes, one can if one uses udev and can find something to identify the hw I/F with, my
> cat /sys/class/net/eth0/device/uevent looks like:
> DRIVER=fsl_dpa
> MODALIAS=platform:dpaa-ethernet
Does not dpaa have a notion of Ethernet ports and those should have
proper information? Maybe that is part of your problem here, it should
have the OF_ALIAS information somehow available.
>
> not sure mdev supports this, does it?
> Our simple installer FS(initramfs) doesn't have either udev or mdev.
I don't know, but you could have a simple shell script that looks at
specific network device properties to decide on the naming and call
ifrename.
>
> I also noted that using status = "disabled" didn't work either to create a fix name scheme.
> Even worse, all the eth I/F after gets renumbered. It seems to me there
> is value in having stability in eth I/F naming at boot.
> Then userspace(udev) can rename if need be.
>
> Sure would like to known more about why this feature is not wanted ?
>
> I found
> https://patchwork.kernel.org/patch/4122441/
> You quote policy as reason but surely it must be better to
> have something stable, connected to the hardware name, than semirandom naming?
If the Device Tree nodes are ordered by ascending base register address,
my understanding is that you get the same order as far as
platform_device creation goes, this may not be true in the future if Rob
decides to randomize that, but AFAICT this is still true. This may not
work well with status = disabled properties being inserted here and
there, but we have used that here and it has worked for as far as I can
remember doing it.
Second, you might want to name network devices ethX, but what if I want
to name them ethernetX or fooX or barX? Should we be accepting a
mechanism in the kernel that would allow someone to name the interfaces
the way they want straight from a name being provided in Device Tree?
Aliases are fine for providing relative stability within the Device Tree
itself and boot programs that might need to modify the Device Tree (e.g:
inserting MAC addresses) such that you don't have to encode logic to
search for nodes by compatible strings etc. but outside of that use
case, it seems to me that you can resolve every naming decision in
user-space.
--
Florian
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Joakim Tjernlund @ 2018-10-23 20:02 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org, netdev@vger.kernel.org,
f.fainelli@gmail.com
Cc: andrew@lunn.ch
In-Reply-To: <8225ba9e-ce8f-b0e0-8f3d-73783693eea4@gmail.com>
On Tue, 2018-10-23 at 11:20 -0700, Florian Fainelli wrote:
>
> On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
> > On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
> > >
> > >
> > > On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
> > > > SPI (and others) has a way to define bus number in a aliases:
> > > > aliases {
> > > > ethernet4 = &enet4;
> > > > ethernet0 = &enet0;
> > > > ethernet1 = &enet1;
> > > > ethernet2 = &enet2;
> > > > ethernet3 = &enet3;
> > > > spi0 = &spi0
> > > > };
> > > > The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
> > > > I am looking for the same for ethernet devices:
> > > > ethernet4 = &enet4; /* should become eth4 */
> > > > ethernet0 = &enet0; /* should become eth0 */
> > > > but I cannot find something like that for eth devices.
> > > >
> > > > Could such functionality be added?
> > >
> > > It could, do we want and need to, no. You have the Ethernet alias in
> > > /sys/class/net/*/device/uevent already that would allow you to perform
> > > that (re)naming in user-space:
> > >
> > > # cat /sys/class/net/eth0/device/uevent
> > > DRIVER=bcmgenet
> > > OF_NAME=ethernet
> > > OF_FULLNAME=/rdb/ethernet@f0480000
> > > OF_TYPE=network
> > > OF_COMPATIBLE_0=brcm,genet-v5
> > > OF_COMPATIBLE_N=1
> > > OF_ALIAS_0=eth0 <==================
> > > MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
> >
> > Yes, one can if one uses udev and can find something to identify the hw I/F with, my
> > cat /sys/class/net/eth0/device/uevent looks like:
> > DRIVER=fsl_dpa
> > MODALIAS=platform:dpaa-ethernet
>
> Does not dpaa have a notion of Ethernet ports and those should have
> proper information? Maybe that is part of your problem here, it should
> have the OF_ALIAS information somehow available.
I cannot say ATM, but this lack of standard does not make it easier to rename I/F's in udev.
>
> > not sure mdev supports this, does it?
> > Our simple installer FS(initramfs) doesn't have either udev or mdev.
>
> I don't know, but you could have a simple shell script that looks at
> specific network device properties to decide on the naming and call
> ifrename.
This reinventing of the wheel is what I am trying to avoid.
>
> > I also noted that using status = "disabled" didn't work either to create a fix name scheme.
> > Even worse, all the eth I/F after gets renumbered. It seems to me there
> > is value in having stability in eth I/F naming at boot.
> > Then userspace(udev) can rename if need be.
> >
> > Sure would like to known more about why this feature is not wanted ?
> >
> > I found
> > https://patchwork.kernel.org/patch/4122441/
> > You quote policy as reason but surely it must be better to
> > have something stable, connected to the hardware name, than semirandom naming?
>
> If the Device Tree nodes are ordered by ascending base register address,
> my understanding is that you get the same order as far as
> platform_device creation goes, this may not be true in the future if Rob
> decides to randomize that, but AFAICT this is still true. This may not
> work well with status = disabled properties being inserted here and
> there, but we have used that here and it has worked for as far as I can
> remember doing it.
I recall it is the order in which the eth alias appear that controls the naming,
not 100% sure though.
>
> Second, you might want to name network devices ethX, but what if I want
> to name them ethernetX or fooX or barX? Should we be accepting a
> mechanism in the kernel that would allow someone to name the interfaces
> the way they want straight from a name being provided in Device Tree?
I just want to have stable boot names, aka ethX, which can defined in
the platforms DT. Then userspace can go from there to whatever it needs,
udev could possibly use these stable boot names to identify the I/F's to rename.
ATM, it is pretty hard to even use udev when /sys/class/net/eth0/device/uevent
can look different even for OF created interfaces.
>
> Aliases are fine for providing relative stability within the Device Tree
> itself and boot programs that might need to modify the Device Tree (e.g:
> inserting MAC addresses) such that you don't have to encode logic to
> search for nodes by compatible strings etc. but outside of that use
> case, it seems to me that you can resolve every naming decision in
> user-space.
Well, you can resolve MAC address assignment in user space too but most
will agree that is not convenient. I suggest it is also handy to have
some control of I/F enumeration(ethX that is) from platform code like DT.
Jocke
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Florian Fainelli @ 2018-10-23 20:07 UTC (permalink / raw)
To: Joakim Tjernlund, linuxppc-dev@lists.ozlabs.org,
netdev@vger.kernel.org
Cc: andrew@lunn.ch
In-Reply-To: <af78570fc7874ca656ee2d81c3841f789fc7d0eb.camel@infinera.com>
On 10/23/18 1:02 PM, Joakim Tjernlund wrote:
> On Tue, 2018-10-23 at 11:20 -0700, Florian Fainelli wrote:
>>
>> On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
>>> On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
>>>>
>>>>
>>>> On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
>>>>> SPI (and others) has a way to define bus number in a aliases:
>>>>> aliases {
>>>>> ethernet4 = &enet4;
>>>>> ethernet0 = &enet0;
>>>>> ethernet1 = &enet1;
>>>>> ethernet2 = &enet2;
>>>>> ethernet3 = &enet3;
>>>>> spi0 = &spi0
>>>>> };
>>>>> The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
>>>>> I am looking for the same for ethernet devices:
>>>>> ethernet4 = &enet4; /* should become eth4 */
>>>>> ethernet0 = &enet0; /* should become eth0 */
>>>>> but I cannot find something like that for eth devices.
>>>>>
>>>>> Could such functionality be added?
>>>>
>>>> It could, do we want and need to, no. You have the Ethernet alias in
>>>> /sys/class/net/*/device/uevent already that would allow you to perform
>>>> that (re)naming in user-space:
>>>>
>>>> # cat /sys/class/net/eth0/device/uevent
>>>> DRIVER=bcmgenet
>>>> OF_NAME=ethernet
>>>> OF_FULLNAME=/rdb/ethernet@f0480000
>>>> OF_TYPE=network
>>>> OF_COMPATIBLE_0=brcm,genet-v5
>>>> OF_COMPATIBLE_N=1
>>>> OF_ALIAS_0=eth0 <==================
>>>> MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
>>>
>>> Yes, one can if one uses udev and can find something to identify the hw I/F with, my
>>> cat /sys/class/net/eth0/device/uevent looks like:
>>> DRIVER=fsl_dpa
>>> MODALIAS=platform:dpaa-ethernet
>>
>> Does not dpaa have a notion of Ethernet ports and those should have
>> proper information? Maybe that is part of your problem here, it should
>> have the OF_ALIAS information somehow available.
>
> I cannot say ATM, but this lack of standard does not make it easier to rename I/F's in udev.
>
>>
>>> not sure mdev supports this, does it?
>>> Our simple installer FS(initramfs) doesn't have either udev or mdev.
>>
>> I don't know, but you could have a simple shell script that looks at
>> specific network device properties to decide on the naming and call
>> ifrename.
>
> This reinventing of the wheel is what I am trying to avoid.
Embedded is all about being a special snowflake and re-inventing the
wheel, but having some desktop-like distribution user-space would
certainly allow you to re-invent other parts of the wheel.
>
>>
>>> I also noted that using status = "disabled" didn't work either to create a fix name scheme.
>>> Even worse, all the eth I/F after gets renumbered. It seems to me there
>>> is value in having stability in eth I/F naming at boot.
>>> Then userspace(udev) can rename if need be.
>>>
>>> Sure would like to known more about why this feature is not wanted ?
>>>
>>> I found
>>> https://patchwork.kernel.org/patch/4122441/
>>> You quote policy as reason but surely it must be better to
>>> have something stable, connected to the hardware name, than semirandom naming?
>>
>> If the Device Tree nodes are ordered by ascending base register address,
>> my understanding is that you get the same order as far as
>> platform_device creation goes, this may not be true in the future if Rob
>> decides to randomize that, but AFAICT this is still true. This may not
>> work well with status = disabled properties being inserted here and
>> there, but we have used that here and it has worked for as far as I can
>> remember doing it.
>
> I recall it is the order in which the eth alias appear that controls the naming,
> not 100% sure though.
Aliases are not looked up at all by the platform bus code other that
with of_get_alias() and friends, it is the order in which the nodes are
declared in the Device Tree, preferably ordered by base address that
dictates the order in which platform devices are created.
>
>>
>> Second, you might want to name network devices ethX, but what if I want
>> to name them ethernetX or fooX or barX? Should we be accepting a
>> mechanism in the kernel that would allow someone to name the interfaces
>> the way they want straight from a name being provided in Device Tree?
>
> I just want to have stable boot names, aka ethX, which can defined in
> the platforms DT. Then userspace can go from there to whatever it needs,
> udev could possibly use these stable boot names to identify the I/F's to rename.
>
> ATM, it is pretty hard to even use udev when /sys/class/net/eth0/device/uevent
> can look different even for OF created interfaces.
network devices have a gazillion of other sysfs attributes that all make
them unique enough to create stable names.
>
>>
>> Aliases are fine for providing relative stability within the Device Tree
>> itself and boot programs that might need to modify the Device Tree (e.g:
>> inserting MAC addresses) such that you don't have to encode logic to
>> search for nodes by compatible strings etc. but outside of that use
>> case, it seems to me that you can resolve every naming decision in
>> user-space.
>
> Well, you can resolve MAC address assignment in user space too but most
> will agree that is not convenient. I suggest it is also handy to have
> some control of I/F enumeration(ethX that is) from platform code like DT.
If that is what you desire because you do not want to use user-space to
do that job, that is probably fine, it's open source after all, an not
every patch is a candidate for being included upstream. A patch doing
what you describe would likely be rejected again.
--
Florian
^ permalink raw reply
* [PATCH 1/2] selftests/powerpc: Allocate base registers
From: Breno Leitao @ 2018-10-23 20:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Breno Leitao
Some ptrace selftests are passing input operands using a constraint that
can allocate any register for the operand, and using these registers on
load/store operations.
If the register allocated by the compiler happens to be zero (r0), it might
cause an invalid memory address access, since load and store operations
consider the content of 0x0 address if the base register is r0, instead
of the content of the r0 register. For example:
r1 := 0xdeadbeef
r0 := 0xdeadbeef
ld r2, 0(r1) /* will load into r2 the content of r1 address */
ld r2, 0(r0) /* will load into r2 the context of 0x0 */
In order to avoid this possible problem, the inline assembly constraint
should be aware that these registers will be used as a base register, thus,
r0 should not be alocated.
Other than that, this patch removes inline assembly operands that are not used
by the tests.
Signed-off-by: Breno Leitao <leitao@debian.org>
---
tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c | 2 +-
tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c | 4 ++--
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c | 2 +-
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c | 3 +--
tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c | 2 +-
tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c | 2 +-
tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c | 3 +--
7 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
index 0b4ebcc2f485..ca29fafeed5d 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
@@ -31,7 +31,7 @@ void gpr(void)
ASM_LOAD_GPR_IMMED(gpr_1)
ASM_LOAD_FPR_SINGLE_PRECISION(flt_1)
:
- : [gpr_1]"i"(GPR_1), [flt_1] "r" (&a)
+ : [gpr_1]"i"(GPR_1), [flt_1] "b" (&a)
: "memory", "r6", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16", "r17",
"r18", "r19", "r20", "r21", "r22", "r23", "r24",
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
index 59206b96e98a..a08a91594dbe 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
@@ -59,8 +59,8 @@ void tm_gpr(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
: [gpr_1]"i"(GPR_1), [gpr_2]"i"(GPR_2),
- [sprn_texasr] "i" (SPRN_TEXASR), [flt_1] "r" (&a),
- [flt_2] "r" (&b), [cptr1] "r" (&cptr[1])
+ [sprn_texasr] "i" (SPRN_TEXASR), [flt_1] "b" (&a),
+ [flt_2] "b" (&b), [cptr1] "b" (&cptr[1])
: "memory", "r7", "r8", "r9", "r10",
"r11", "r12", "r13", "r14", "r15", "r16",
"r17", "r18", "r19", "r20", "r21", "r22",
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
index b3c061dc9512..f47174746231 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
@@ -72,7 +72,7 @@ void tm_spd_tar(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
- : [val] "r" (cptr[1]), [sprn_dscr]"i"(SPRN_DSCR),
+ : [sprn_dscr]"i"(SPRN_DSCR),
[sprn_tar]"i"(SPRN_TAR), [sprn_ppr]"i"(SPRN_PPR),
[sprn_texasr]"i"(SPRN_TEXASR), [tar_1]"i"(TAR_1),
[dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2),
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
index 277dade1b382..18a685bf6a09 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
@@ -77,8 +77,7 @@ void tm_spd_vsx(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
- : [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
- [sprn_texasr] "i" (SPRN_TEXASR)
+ : [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11"
);
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
index 51427a2465f6..ba04999254e3 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
@@ -74,7 +74,7 @@ void tm_spr(void)
"3: ;"
: [tfhar] "=r" (tfhar), [res] "=r" (result),
- [texasr] "=r" (texasr), [cptr1] "=r" (cptr1)
+ [texasr] "=r" (texasr), [cptr1] "=b" (cptr1)
: [sprn_texasr] "i" (SPRN_TEXASR)
: "memory", "r0", "r8", "r31"
);
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
index 48b462f75023..f70023b25e6e 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
@@ -65,7 +65,7 @@ void tm_tar(void)
: [sprn_dscr]"i"(SPRN_DSCR), [sprn_tar]"i"(SPRN_TAR),
[sprn_ppr]"i"(SPRN_PPR), [sprn_texasr]"i"(SPRN_TEXASR),
[tar_1]"i"(TAR_1), [dscr_1]"i"(DSCR_1), [tar_2]"i"(TAR_2),
- [dscr_2]"i"(DSCR_2), [cptr1] "r" (&cptr[1])
+ [dscr_2]"i"(DSCR_2), [cptr1] "b" (&cptr[1])
: "memory", "r0", "r1", "r3", "r4", "r5", "r6"
);
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
index 17c23cabac3e..dfba80058977 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
@@ -65,8 +65,7 @@ void tm_vsx(void)
"3: ;"
: [res] "=r" (result), [texasr] "=r" (texasr)
- : [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt),
- [sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "r" (&cptr[1])
+ : [sprn_texasr] "i" (SPRN_TEXASR), [cptr1] "b" (&cptr[1])
: "memory", "r0", "r1", "r3", "r4",
"r7", "r8", "r9", "r10", "r11"
);
--
2.19.0
^ permalink raw reply related
* [PATCH 2/2] selftests/powerpc: Skip test instead of failing
From: Breno Leitao @ 2018-10-23 20:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Breno Leitao, Thiago Jung Bauermann
In-Reply-To: <1540326197-15537-1-git-send-email-leitao@debian.org>
Current core-pkey selftest fails if the test runs without privileges to
write into the core pattern file (/proc/sys/kernel/core_pattern). This
causes the test to fail and give the impression that the subsystem being
tested is broken, when, in fact, the test is being executed without the
proper privileges. This is the current error:
test: core_pkey
tags: git_version:v4.19-3-g9e3363be9bce-dirty
Error writing to core_pattern file: Permission denied
failure: core_pkey
This patch simply skips this test if it runs without the proper privileges,
avoiding this undesired failure.
CC: Thiago Jung Bauermann <bauerman@linux.ibm.com>
Signed-off-by: Breno Leitao <leitao@debian.org>
---
tools/testing/selftests/powerpc/ptrace/core-pkey.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/tools/testing/selftests/powerpc/ptrace/core-pkey.c b/tools/testing/selftests/powerpc/ptrace/core-pkey.c
index e23e2e199eb4..e07949120fc8 100644
--- a/tools/testing/selftests/powerpc/ptrace/core-pkey.c
+++ b/tools/testing/selftests/powerpc/ptrace/core-pkey.c
@@ -352,17 +352,11 @@ static int write_core_pattern(const char *core_pattern)
FILE *f;
f = fopen(core_pattern_file, "w");
- if (!f) {
- perror("Error writing to core_pattern file");
- return TEST_FAIL;
- }
+ SKIP_IF(!f);
ret = fwrite(core_pattern, 1, len, f);
fclose(f);
- if (ret != len) {
- perror("Error writing to core_pattern file");
- return TEST_FAIL;
- }
+ SKIP_IF(ret != len);
return TEST_PASS;
}
--
2.19.0
^ permalink raw reply related
* Re: [PATCH 2/2] selftests/powerpc: Skip test instead of failing
From: Tyrel Datwyler @ 2018-10-23 20:41 UTC (permalink / raw)
To: Breno Leitao, linuxppc-dev; +Cc: Thiago Jung Bauermann
In-Reply-To: <1540326197-15537-2-git-send-email-leitao@debian.org>
On 10/23/2018 01:23 PM, Breno Leitao wrote:
> Current core-pkey selftest fails if the test runs without privileges to
> write into the core pattern file (/proc/sys/kernel/core_pattern). This
> causes the test to fail and give the impression that the subsystem being
> tested is broken, when, in fact, the test is being executed without the
> proper privileges. This is the current error:
>
> test: core_pkey
> tags: git_version:v4.19-3-g9e3363be9bce-dirty
> Error writing to core_pattern file: Permission denied
> failure: core_pkey
>
> This patch simply skips this test if it runs without the proper privileges,
> avoiding this undesired failure.
>
> CC: Thiago Jung Bauermann <bauerman@linux.ibm.com>
> Signed-off-by: Breno Leitao <leitao@debian.org>
> ---
> tools/testing/selftests/powerpc/ptrace/core-pkey.c | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/tools/testing/selftests/powerpc/ptrace/core-pkey.c b/tools/testing/selftests/powerpc/ptrace/core-pkey.c
> index e23e2e199eb4..e07949120fc8 100644
> --- a/tools/testing/selftests/powerpc/ptrace/core-pkey.c
> +++ b/tools/testing/selftests/powerpc/ptrace/core-pkey.c
> @@ -352,17 +352,11 @@ static int write_core_pattern(const char *core_pattern)
> FILE *f;
>
> f = fopen(core_pattern_file, "w");
> - if (!f) {
> - perror("Error writing to core_pattern file");
> - return TEST_FAIL;
> - }
> + SKIP_IF(!f);
>
> ret = fwrite(core_pattern, 1, len, f);
> fclose(f);
> - if (ret != len) {
> - perror("Error writing to core_pattern file");
> - return TEST_FAIL;
> - }
> + SKIP_IF(ret != len);
If we don't have proper privileges we should fail on the open, right? So wouldn't we still want to fail on the write if something goes wrong?
-Tyrel
>
> return TEST_PASS;
> }
>
^ permalink raw reply
* Re: [PATCH 1/2] selftests/powerpc: Allocate base registers
From: Segher Boessenkool @ 2018-10-23 21:39 UTC (permalink / raw)
To: Breno Leitao; +Cc: linuxppc-dev
In-Reply-To: <1540326197-15537-1-git-send-email-leitao@debian.org>
On Tue, Oct 23, 2018 at 05:23:16PM -0300, Breno Leitao wrote:
> Some ptrace selftests are passing input operands using a constraint that
> can allocate any register for the operand, and using these registers on
> load/store operations.
>
> If the register allocated by the compiler happens to be zero (r0), it might
> cause an invalid memory address access, since load and store operations
> consider the content of 0x0 address if the base register is r0, instead
> of the content of the r0 register. For example:
>
> r1 := 0xdeadbeef
> r0 := 0xdeadbeef
>
> ld r2, 0(r1) /* will load into r2 the content of r1 address */
> ld r2, 0(r0) /* will load into r2 the context of 0x0 */
That isn't valid syntax: you have to write
ld r2, 0(0)
(s/context/content/ btw)
> In order to avoid this possible problem, the inline assembly constraint
> should be aware that these registers will be used as a base register, thus,
> r0 should not be alocated.
(allocated)
The patch looks fine :-)
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Segher
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Joakim Tjernlund @ 2018-10-23 22:15 UTC (permalink / raw)
To: linuxppc-dev@lists.ozlabs.org, netdev@vger.kernel.org,
f.fainelli@gmail.com
Cc: andrew@lunn.ch
In-Reply-To: <adaad568-bbaf-fd5d-a2c3-ae7bf1be3d31@gmail.com>
On Tue, 2018-10-23 at 13:07 -0700, Florian Fainelli wrote:
>
> On 10/23/18 1:02 PM, Joakim Tjernlund wrote:
> > On Tue, 2018-10-23 at 11:20 -0700, Florian Fainelli wrote:
> > > On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
> > > > >
> > > > > On 10/23/18 9:49 AM, Joakim Tjernlund wrote:
> > > > > > SPI (and others) has a way to define bus number in a aliases:
> > > > > > aliases {
> > > > > > ethernet4 = &enet4;
> > > > > > ethernet0 = &enet0;
> > > > > > ethernet1 = &enet1;
> > > > > > ethernet2 = &enet2;
> > > > > > ethernet3 = &enet3;
> > > > > > spi0 = &spi0
> > > > > > };
> > > > > > The 0 in the spi0 alias will translate to bus num 0 so one can control the /dev nodes, like /dev/spidev0
> > > > > > I am looking for the same for ethernet devices:
> > > > > > ethernet4 = &enet4; /* should become eth4 */
> > > > > > ethernet0 = &enet0; /* should become eth0 */
> > > > > > but I cannot find something like that for eth devices.
> > > > > >
> > > > > > Could such functionality be added?
> > > > >
> > > > > It could, do we want and need to, no. You have the Ethernet alias in
> > > > > /sys/class/net/*/device/uevent already that would allow you to perform
> > > > > that (re)naming in user-space:
> > > > >
> > > > > # cat /sys/class/net/eth0/device/uevent
> > > > > DRIVER=bcmgenet
> > > > > OF_NAME=ethernet
> > > > > OF_FULLNAME=/rdb/ethernet@f0480000
> > > > > OF_TYPE=network
> > > > > OF_COMPATIBLE_0=brcm,genet-v5
> > > > > OF_COMPATIBLE_N=1
> > > > > OF_ALIAS_0=eth0 <==================
> > > > > MODALIAS=of:NethernetTnetworkCbrcm,genet-v5
> > > >
> > > > Yes, one can if one uses udev and can find something to identify the hw I/F with, my
> > > > cat /sys/class/net/eth0/device/uevent looks like:
> > > > DRIVER=fsl_dpa
> > > > MODALIAS=platform:dpaa-ethernet
> > >
> > > Does not dpaa have a notion of Ethernet ports and those should have
> > > proper information? Maybe that is part of your problem here, it should
> > > have the OF_ALIAS information somehow available.
> >
> > I cannot say ATM, but this lack of standard does not make it easier to rename I/F's in udev.
> >
> > > > not sure mdev supports this, does it?
> > > > Our simple installer FS(initramfs) doesn't have either udev or mdev.
> > >
> > > I don't know, but you could have a simple shell script that looks at
> > > specific network device properties to decide on the naming and call
> > > ifrename.
> >
> > This reinventing of the wheel is what I am trying to avoid.
>
> Embedded is all about being a special snowflake and re-inventing the
> wheel, but having some desktop-like distribution user-space would
> certainly allow you to re-invent other parts of the wheel.
>
> > > > I also noted that using status = "disabled" didn't work either to create a fix name scheme.
> > > > Even worse, all the eth I/F after gets renumbered. It seems to me there
> > > > is value in having stability in eth I/F naming at boot.
> > > > Then userspace(udev) can rename if need be.
> > > >
> > > > Sure would like to known more about why this feature is not wanted ?
> > > >
> > > > I found
> > > > https://patchwork.kernel.org/patch/4122441/
> > > > You quote policy as reason but surely it must be better to
> > > > have something stable, connected to the hardware name, than semirandom naming?
> > >
> > > If the Device Tree nodes are ordered by ascending base register address,
> > > my understanding is that you get the same order as far as
> > > platform_device creation goes, this may not be true in the future if Rob
> > > decides to randomize that, but AFAICT this is still true. This may not
> > > work well with status = disabled properties being inserted here and
> > > there, but we have used that here and it has worked for as far as I can
> > > remember doing it.
> >
> > I recall it is the order in which the eth alias appear that controls the naming,
> > not 100% sure though.
>
> Aliases are not looked up at all by the platform bus code other that
> with of_get_alias() and friends, it is the order in which the nodes are
> declared in the Device Tree, preferably ordered by base address that
> dictates the order in which platform devices are created.
I see, thanks.
>
> > > Second, you might want to name network devices ethX, but what if I want
> > > to name them ethernetX or fooX or barX? Should we be accepting a
> > > mechanism in the kernel that would allow someone to name the interfaces
> > > the way they want straight from a name being provided in Device Tree?
> >
> > I just want to have stable boot names, aka ethX, which can defined in
> > the platforms DT. Then userspace can go from there to whatever it needs,
> > udev could possibly use these stable boot names to identify the I/F's to rename.
> >
> > ATM, it is pretty hard to even use udev when /sys/class/net/eth0/device/uevent
> > can look different even for OF created interfaces.
>
> network devices have a gazillion of other sysfs attributes that all make
> them unique enough to create stable names.
That is kind of my point, there doesn't seem to be any stable source of info
that can be relied on. Each platform/driver is it own, DT/OF created I/F's should
look the same in /sys/class/net/eth0/device/uevent but that is not so.
I am sure I can find something though.
>
> > > Aliases are fine for providing relative stability within the Device Tree
> > > itself and boot programs that might need to modify the Device Tree (e.g:
> > > inserting MAC addresses) such that you don't have to encode logic to
> > > search for nodes by compatible strings etc. but outside of that use
> > > case, it seems to me that you can resolve every naming decision in
> > > user-space.
> >
> > Well, you can resolve MAC address assignment in user space too but most
> > will agree that is not convenient. I suggest it is also handy to have
> > some control of I/F enumeration(ethX that is) from platform code like DT.
>
> If that is what you desire because you do not want to use user-space to
> do that job, that is probably fine, it's open source after all, an not
> every patch is a candidate for being included upstream. A patch doing
> what you describe would likely be rejected again.
> --
Of course, but I didn't start this thread just to hack my own patch. I wanted
buy in from the community and that is not happening so I will rest now.
Thanks you for taking the time to discuss this,
Jocke
^ permalink raw reply
* [PATCH] powerpc/perf: Add mem access events to sysfs
From: Madhavan Srinivasan @ 2018-10-24 0:24 UTC (permalink / raw)
To: mpe; +Cc: Madhavan Srinivasan, linuxppc-dev
Add mem-loads/mem-stores events to sysfs.
The event is formed based on raw event encoding.
Primary PMU event used here is PM_MRK_INST_CMPL
along with MMCRA[SM] modes and Thresholding bits
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/perf/power9-events-list.h | 8 ++++++++
arch/powerpc/perf/power9-pmu.c | 4 ++++
2 files changed, 12 insertions(+)
diff --git a/arch/powerpc/perf/power9-events-list.h b/arch/powerpc/perf/power9-events-list.h
index 7de344b7d9cc..c2241e54f9ba 100644
--- a/arch/powerpc/perf/power9-events-list.h
+++ b/arch/powerpc/perf/power9-events-list.h
@@ -97,3 +97,11 @@ EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156)
EVENT(PM_DTLB_MISS_16M, 0x4c056)
EVENT(PM_DTLB_MISS_1G, 0x4c05a)
EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e)
+
+/*
+ * Memory Access Events
+ * Primary PMU event used here is PM_MRK_INST_CMPL, along with
+ * Random Instruction Sampling (RIS) ([MMCRA[SM])
+ */
+EVENT(MEM_LOADS, 0x67340401e0)
+EVENT(MEM_STORES, 0x351c0401e0)
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index cd3b28f585e4..46e0a312776e 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -168,6 +168,8 @@ GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
+GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
+GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
@@ -195,6 +197,8 @@ static struct attribute *power9_events_attr[] = {
GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
GENERIC_EVENT_PTR(PM_LD_REF_L1),
GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
+ GENERIC_EVENT_PTR(MEM_LOADS),
+ GENERIC_EVENT_PTR(MEM_STORES),
CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
CACHE_EVENT_PTR(PM_LD_REF_L1),
CACHE_EVENT_PTR(PM_L1_PREF),
--
2.7.4
^ permalink raw reply related
* [PATCH 3/3 v2] clk: qoriq: update clock driver
From: andy.tang @ 2018-10-24 2:11 UTC (permalink / raw)
To: sboyd, mturquette, oss
Cc: mark.rutland, devicetree, Yuantian Tang, linux-kernel, robh+dt,
paulus, linuxppc-dev, linux-clk
In-Reply-To: <20181024021122.3942-2-andy.tang@nxp.com>
From: Yuantian Tang <andy.tang@nxp.com>
Legacy bindings are deleted. So the legacy support in driver
can be deleted safely.
Add more chip-specific compatible as well to support more Socs.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
- remove all legacy code
drivers/clk/clk-qoriq.c | 159 +++-------------------------------------------
1 files changed, 11 insertions(+), 148 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..405a9ab 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -914,43 +914,6 @@ static void __init create_muxes(struct clockgen *cg)
}
}
-static void __init clockgen_init(struct device_node *np);
-
-/*
- * Legacy nodes may get probed before the parent clockgen node.
- * It is assumed that device trees with legacy nodes will not
- * contain a "clocks" property -- otherwise the input clocks may
- * not be initialized at this point.
- */
-static void __init legacy_init_clockgen(struct device_node *np)
-{
- if (!clockgen.node)
- clockgen_init(of_get_parent(np));
-}
-
-/* Legacy node */
-static void __init core_mux_init(struct device_node *np)
-{
- struct clk *clk;
- struct resource res;
- int idx, rc;
-
- legacy_init_clockgen(np);
-
- if (of_address_to_resource(np, 0, &res))
- return;
-
- idx = (res.start & 0xf0) >> 5;
- clk = clockgen.cmux[idx];
-
- rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
- if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
- return;
- }
-}
-
static struct clk __init
*sysclk_from_fixed(struct device_node *node, const char *name)
{
@@ -1036,30 +999,9 @@ static void __init core_mux_init(struct device_node *np)
if (!IS_ERR(clk))
return clk;
- /*
- * This indicates a mix of legacy nodes with the new coreclk
- * mechanism, which should never happen. If this error occurs,
- * don't use the wrong input clock just because coreclk isn't
- * ready yet.
- */
- if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
- return clk;
-
return NULL;
}
-/* Legacy node */
-static void __init sysclk_init(struct device_node *node)
-{
- struct clk *clk;
-
- legacy_init_clockgen(node);
-
- clk = clockgen.sysclk;
- if (clk)
- of_clk_add_provider(node, of_clk_src_simple_get, clk);
-}
-
#define PLL_KILL BIT(31)
static void __init create_one_pll(struct clockgen *cg, int idx)
@@ -1162,82 +1104,6 @@ static void __init create_plls(struct clockgen *cg)
create_one_pll(cg, i);
}
-static void __init legacy_pll_init(struct device_node *np, int idx)
-{
- struct clockgen_pll *pll;
- struct clk_onecell_data *onecell_data;
- struct clk **subclks;
- int count, rc;
-
- legacy_init_clockgen(np);
-
- pll = &clockgen.pll[idx];
- count = of_property_count_strings(np, "clock-output-names");
-
- BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
- subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
- if (!subclks)
- return;
-
- onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
- if (!onecell_data)
- goto err_clks;
-
- if (count <= 3) {
- subclks[0] = pll->div[0].clk;
- subclks[1] = pll->div[1].clk;
- subclks[2] = pll->div[3].clk;
- } else {
- subclks[0] = pll->div[0].clk;
- subclks[1] = pll->div[1].clk;
- subclks[2] = pll->div[2].clk;
- subclks[3] = pll->div[3].clk;
- }
-
- onecell_data->clks = subclks;
- onecell_data->clk_num = count;
-
- rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
- if (rc) {
- pr_err("%s: Couldn't register clk provider for node %s: %d\n",
- __func__, np->name, rc);
- goto err_cell;
- }
-
- return;
-err_cell:
- kfree(onecell_data);
-err_clks:
- kfree(subclks);
-}
-
-/* Legacy node */
-static void __init pltfrm_pll_init(struct device_node *np)
-{
- legacy_pll_init(np, PLATFORM_PLL);
-}
-
-/* Legacy node */
-static void __init core_pll_init(struct device_node *np)
-{
- struct resource res;
- int idx;
-
- if (of_address_to_resource(np, 0, &res))
- return;
-
- if ((res.start & 0xfff) == 0xc00) {
- /*
- * ls1021a devtree labels the platform PLL
- * with the core PLL compatible
- */
- pltfrm_pll_init(np);
- } else {
- idx = (res.start & 0xf0) >> 5;
- legacy_pll_init(np, CGA_PLL1 + idx);
- }
-}
-
static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
{
struct clockgen *cg = data;
@@ -1347,10 +1213,6 @@ static void __init clockgen_init(struct device_node *np)
int i, ret;
bool is_old_ls1021a = false;
- /* May have already been called by a legacy probe */
- if (clockgen.node)
- return;
-
clockgen.node = np;
clockgen.regs = of_iomap(np, 0);
if (!clockgen.regs &&
@@ -1418,19 +1280,20 @@ static void __init clockgen_init(struct device_node *np)
CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,fsl,b4420-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,fsl,b4860-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
-
-/* Legacy nodes */
-CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
-CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
-CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
-CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
-CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
-CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
-CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
-CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);
+CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
--
1.7.1
^ permalink raw reply related
* [PATCH 2/3 v2] clk: qoriq: remove legacy bindings and add more compatibles
From: andy.tang @ 2018-10-24 2:11 UTC (permalink / raw)
To: sboyd, mturquette, oss
Cc: mark.rutland, devicetree, Yuantian Tang, linux-kernel, robh+dt,
paulus, linuxppc-dev, linux-clk
In-Reply-To: <20181024021122.3942-1-andy.tang@nxp.com>
From: Yuantian Tang <andy.tang@nxp.com>
The new bindings will be used, so delete the old bindings.
Add more SOC compatibles as needed as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
- involve more chips
.../devicetree/bindings/clock/qoriq-clock.txt | 112 +------------------
1 files changed, 6 insertions(+), 106 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 97f46ad..8484d90 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -28,6 +28,12 @@ Required properties:
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
+ * "fsl,t1023-clockgen"
+ * "fsl,t1024-clockgen"
+ * "fsl,t1040-clockgen"
+ * "fsl,t1042-clockgen"
+ * "fsl,t2080-clockgen"
+ * "fsl,t2081-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
@@ -96,109 +102,3 @@ second cell is the clock index for the specified type.
...
};
}
-4. Legacy Child Nodes
-
-NOTE: These nodes are deprecated. Kernels should continue to support
-device trees with these nodes, but new device trees should not use them.
-
-Most of the bindings are from the common clock binding[1].
- [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : Should include one of the following:
- * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
- * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
- * "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
- * "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
- * "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
- It takes parent's clock-frequency as its clock.
- * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
- * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
-- #clock-cells: From common clock binding. The number of cells in a
- clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
- clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
- For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
- clock-specifier cell may take the following values:
- * 0 - equal to the PLL frequency
- * 1 - equal to the PLL frequency divided by 2
- * 2 - equal to the PLL frequency divided by 4
-
-Recommended properties:
-- clocks: Should be the phandle of input parent clock
-- clock-names: From common clock binding, indicates the clock name
-- clock-output-names: From common clock binding, indicates the names of
- output clocks
-- reg: Should be the offset and length of clock block base address.
- The length should be 4.
-
-Legacy Example:
-/ {
- clockgen: global-utilities@e1000 {
- compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
- clock-frequency = <133333333>;
- reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0";
- clock-output-names = "sysclk";
- };
-
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
-
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
-
- platform-pll: platform-pll@c00 {
- #clock-cells = <1>;
- reg = <0xc00 0x4>;
- compatible = "fsl,qoriq-platform-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "platform-pll", "platform-pll-div2";
- };
- };
-};
-
-Example for legacy clock consumer:
-
-/ {
- cpu0: PowerPC,e5500@0 {
- ...
- clocks = <&mux0>;
- ...
- };
-};
--
1.7.1
^ permalink raw reply related
* [PATCH 1/3 v2] powerpc/fsl: Use new clockgen binding
From: andy.tang @ 2018-10-24 2:11 UTC (permalink / raw)
To: sboyd, mturquette, oss
Cc: mark.rutland, devicetree, Tang Yuantian, linux-kernel, robh+dt,
paulus, linuxppc-dev, linux-clk
From: Scott Wood <oss@buserror.net>
The driver retains compatibility with old device trees, but we don't
want the old nodes lying around to be copied, or used as a reference
(some of the mux options are incorrect), or even just being clutter.
We will also need the #clock-cells in the clockgen node in order to
add fman nodes.
Signed-off-by: Scott Wood <oss@buserror.net>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
---
v2:
- involve more soc
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 15 -----
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 18 ------
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 18 ------
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 70 ------------------------
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi | 16 +++---
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi | 18 ------
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi | 55 +++----------------
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi | 38 +++----------
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi | 16 ------
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi | 4 +-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 44 ---------------
arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 22 --------
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi | 8 ++--
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi | 61 ---------------------
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi | 24 ++++----
22 files changed, 66 insertions(+), 409 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 88d8423..bb7b9b9 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -70,14 +70,14 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index f3f968c..388ba1b 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -75,28 +75,28 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
index 1b33f51..4f044b4 100644
--- a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -398,21 +398,6 @@
};
/include/ "qoriq-clockgen2.dtsi"
- clockgen: global-utilities@e1000 {
- compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
- reg = <0xe1000 0x1000>;
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll0-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux0";
- };
- };
rcpm: global-utilities@e2000 {
compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 51e975d..872e448 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -327,24 +327,6 @@
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux2";
- };
-
- mux3: mux3@60 {
- #clock-cells = <0>;
- reg = <0x60 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux3";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 941274c..6318962 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -89,7 +89,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
@@ -99,7 +99,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
@@ -109,7 +109,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
@@ -119,7 +119,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
- clocks = <&mux3>;
+ clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 187676f..81bc75a 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -354,24 +354,6 @@
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux2";
- };
-
- mux3: mux3@60 {
- #clock-cells = <0>;
- reg = <0x60 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux3";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 50b73e8..db92f11 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -90,7 +90,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
@@ -100,7 +100,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
@@ -110,7 +110,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
@@ -120,7 +120,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
- clocks = <&mux3>;
+ clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index a025208..4da49b6 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -374,76 +374,6 @@
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
-
- pll2: pll2@840 {
- #clock-cells = <1>;
- reg = <0x840 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll2", "pll2-div2";
- };
-
- pll3: pll3@860 {
- #clock-cells = <1>;
- reg = <0x860 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll3", "pll3-div2";
- };
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux2";
- };
-
- mux3: mux3@60 {
- #clock-cells = <0>;
- reg = <0x60 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux3";
- };
-
- mux4: mux4@80 {
- #clock-cells = <0>;
- reg = <0x80 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
- clock-output-names = "cmux4";
- };
-
- mux5: mux5@a0 {
- #clock-cells = <0>;
- reg = <0xa0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
- clock-output-names = "cmux5";
- };
-
- mux6: mux6@c0 {
- #clock-cells = <0>;
- reg = <0xc0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
- clock-output-names = "cmux6";
- };
-
- mux7: mux7@e0 {
- #clock-cells = <0>;
- reg = <0xe0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
- clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
- clock-output-names = "cmux7";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index d56a546..0a7c65a 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -94,7 +94,7 @@
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
@@ -104,7 +104,7 @@
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
@@ -114,7 +114,7 @@
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
@@ -124,7 +124,7 @@
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
- clocks = <&mux3>;
+ clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
@@ -134,7 +134,7 @@
cpu4: PowerPC,e500mc@4 {
device_type = "cpu";
reg = <4>;
- clocks = <&mux4>;
+ clocks = <&clockgen 1 4>;
next-level-cache = <&L2_4>;
fsl,portid-mapping = <0x08000000>;
L2_4: l2-cache {
@@ -144,7 +144,7 @@
cpu5: PowerPC,e500mc@5 {
device_type = "cpu";
reg = <5>;
- clocks = <&mux5>;
+ clocks = <&clockgen 1 5>;
next-level-cache = <&L2_5>;
fsl,portid-mapping = <0x04000000>;
L2_5: l2-cache {
@@ -154,7 +154,7 @@
cpu6: PowerPC,e500mc@6 {
device_type = "cpu";
reg = <6>;
- clocks = <&mux6>;
+ clocks = <&clockgen 1 6>;
next-level-cache = <&L2_6>;
fsl,portid-mapping = <0x02000000>;
L2_6: l2-cache {
@@ -164,7 +164,7 @@
cpu7: PowerPC,e500mc@7 {
device_type = "cpu";
reg = <7>;
- clocks = <&mux7>;
+ clocks = <&clockgen 1 7>;
next-level-cache = <&L2_7>;
fsl,portid-mapping = <0x01000000>;
L2_7: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index bfba0b4..2d74ea8 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -96,7 +96,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
@@ -106,7 +106,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index e2bd931..16b454b 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -319,24 +319,6 @@
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux2";
- };
-
- mux3: mux3@60 {
- #clock-cells = <0>;
- reg = <0x60 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux3";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index dbd5775..ed89dbb 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -102,7 +102,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache {
@@ -112,7 +112,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache {
@@ -122,7 +122,7 @@
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache {
@@ -132,7 +132,7 @@
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
- clocks = <&mux3>;
+ clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
index 88cd70d..5c89cfa 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
@@ -32,55 +32,16 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+};
+
clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-1.0";
- ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
- clock-frequency = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
#clock-cells = <2>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
- clock-output-names = "sysclk";
- };
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2";
- };
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2";
- };
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux0";
- };
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-1.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
- clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
- clock-output-names = "cmux1";
- };
- platform_pll: platform-pll@c00 {
- #clock-cells = <1>;
- reg = <0xc00 0x4>;
- compatible = "fsl,qoriq-platform-pll-1.0";
- clocks = <&sysclk>;
- clock-output-names = "platform-pll", "platform-pll-div2";
- };
+ clocks = <&sysclk>;
};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
index 6dfd7c5..bf649ce 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
@@ -32,38 +32,16 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "sysclk";
+};
+
clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-2.0";
- ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
#clock-cells = <2>;
-
- sysclk: sysclk {
- #clock-cells = <0>;
- compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
- clock-output-names = "sysclk";
- };
- pll0: pll0@800 {
- #clock-cells = <1>;
- reg = <0x800 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll0", "pll0-div2", "pll0-div4";
- };
- pll1: pll1@820 {
- #clock-cells = <1>;
- reg = <0x820 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll1", "pll1-div2", "pll1-div4";
- };
- platform_pll: platform-pll@c00 {
- #clock-cells = <1>;
- reg = <0xc00 0x4>;
- compatible = "fsl,qoriq-platform-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "platform-pll", "platform-pll-div2";
- };
+ clocks = <&sysclk>;
};
diff --git a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
index 4908af5..d552044 100644
--- a/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
@@ -345,22 +345,6 @@
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0";
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 4>;
- compatible = "fsl,core-mux-clock";
- clocks = <&pll0 0>, <&pll0 1>;
- clock-names = "pll0_0", "pll0_1";
- clock-output-names = "cmux0";
- };
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 4>;
- compatible = "fsl,core-mux-clock";
- clocks = <&pll0 0>, <&pll0 1>;
- clock-names = "pll0_0", "pll0_1";
- clock-output-names = "cmux1";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
index 9d08a36..d87ea13 100644
--- a/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
@@ -74,7 +74,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
@@ -84,7 +84,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 145c7f4..315d055 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -425,50 +425,6 @@
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll1-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll1-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux1";
- };
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll1-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux2";
- };
-
- mux3: mux3@60 {
- #clock-cells = <0>;
- reg = <0x60 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0_0", "pll0_1", "pll0_2",
- "pll1_0", "pll1_1", "pll1_2";
- clock-output-names = "cmux3";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
index 6db0ee8..dd59e4b 100644
--- a/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
@@ -74,7 +74,7 @@
cpu0: PowerPC,e5500@0 {
device_type = "cpu";
reg = <0>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
@@ -84,7 +84,7 @@
cpu1: PowerPC,e5500@1 {
device_type = "cpu";
reg = <1>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
@@ -94,7 +94,7 @@
cpu2: PowerPC,e5500@2 {
device_type = "cpu";
reg = <2>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
@@ -104,7 +104,7 @@
cpu3: PowerPC,e5500@3 {
device_type = "cpu";
reg = <3>;
- clocks = <&mux3>;
+ clocks = <&clockgen 1 3>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index a97296c..ecbb447 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -535,28 +535,6 @@
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll0-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>;
- clock-names = "pll0", "pll0-div2", "pll0-div4",
- "pll1", "pll1-div2", "pll1-div4";
- clock-output-names = "cmux1";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
index c2e5720..3f745de 100644
--- a/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
@@ -81,28 +81,28 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 68c4ead..fcac734 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -950,67 +950,6 @@
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
-
- pll2: pll2@840 {
- #clock-cells = <1>;
- reg = <0x840 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll2", "pll2-div2", "pll2-div4";
- };
-
- pll3: pll3@860 {
- #clock-cells = <1>;
- reg = <0x860 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll3", "pll3-div2", "pll3-div4";
- };
-
- pll4: pll4@880 {
- #clock-cells = <1>;
- reg = <0x880 0x4>;
- compatible = "fsl,qoriq-core-pll-2.0";
- clocks = <&sysclk>;
- clock-output-names = "pll4", "pll4-div2", "pll4-div4";
- };
-
- mux0: mux0@0 {
- #clock-cells = <0>;
- reg = <0x0 0x4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>,
- <&pll2 0>, <&pll2 1>, <&pll2 2>;
- clock-names = "pll0", "pll0-div2", "pll0-div4",
- "pll1", "pll1-div2", "pll1-div4",
- "pll2", "pll2-div2", "pll2-div4";
- clock-output-names = "cmux0";
- };
-
- mux1: mux1@20 {
- #clock-cells = <0>;
- reg = <0x20 0x4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
- <&pll1 0>, <&pll1 1>, <&pll1 2>,
- <&pll2 0>, <&pll2 1>, <&pll2 2>;
- clock-names = "pll0", "pll0-div2", "pll0-div4",
- "pll1", "pll1-div2", "pll1-div4",
- "pll2", "pll2-div2", "pll2-div4";
- clock-output-names = "cmux1";
- };
-
- mux2: mux2@40 {
- #clock-cells = <0>;
- reg = <0x40 0x4>;
- compatible = "fsl,qoriq-core-mux-2.0";
- clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
- <&pll4 0>, <&pll4 1>, <&pll4 2>;
- clock-names = "pll3", "pll3-div2", "pll3-div4",
- "pll4", "pll4-div2", "pll4-div4";
- clock-output-names = "cmux2";
- };
};
rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index 038cf8f..632314c 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -90,84 +90,84 @@
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
- clocks = <&mux0>;
+ clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu4: PowerPC,e6500@8 {
device_type = "cpu";
reg = <8 9>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu5: PowerPC,e6500@10 {
device_type = "cpu";
reg = <10 11>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu6: PowerPC,e6500@12 {
device_type = "cpu";
reg = <12 13>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu7: PowerPC,e6500@14 {
device_type = "cpu";
reg = <14 15>;
- clocks = <&mux1>;
+ clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>;
};
cpu8: PowerPC,e6500@16 {
device_type = "cpu";
reg = <16 17>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu9: PowerPC,e6500@18 {
device_type = "cpu";
reg = <18 19>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu10: PowerPC,e6500@20 {
device_type = "cpu";
reg = <20 21>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
cpu11: PowerPC,e6500@22 {
device_type = "cpu";
reg = <22 23>;
- clocks = <&mux2>;
+ clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>;
};
--
1.7.1
^ permalink raw reply related
* Re: [bug report] powerpc/perf: Add nest IMC PMU support
From: Anju T Sudhakar @ 2018-10-24 7:06 UTC (permalink / raw)
To: Dan Carpenter; +Cc: linuxppc-dev
In-Reply-To: <20181018093346.gw72isttyope3nxe@kili.mountain>
Hi,
On 10/18/18 3:03 PM, Dan Carpenter wrote:
> Hello Anju T Sudhakar,
>
> The patch 885dcd709ba9: "powerpc/perf: Add nest IMC PMU support" from
> Jul 19, 2017, leads to the following static checker warning:
>
> arch/powerpc/perf/imc-pmu.c:506 nest_imc_event_init()
> warn: 'pcni' can't be NULL.
Unfortunately this warning didn't appear when I checked with smatch.
Could you please provide the steps to reproduce this?
This is the commit id with which I build smatch: commit
79fe36620a7a3a45d1a51d62238da250fb8db920
But anyway I am looking into the code part. Thanks for mentioning this.
I will update soon.
Thanks,
Anju
^ permalink raw reply
* [PATCH v3 2/7] include: add setbits_leXX/clrbits_leXX/clrsetbits_leXX in linux/setbits.h
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch adds setbits_le32/clrbits_le32/clrsetbits_le32 and
setbits_le64/clrbits_le64/clrsetbits_le64 in linux/setbits.h header.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
include/linux/setbits.h | 84 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 include/linux/setbits.h
diff --git a/include/linux/setbits.h b/include/linux/setbits.h
new file mode 100644
index 000000000000..c82faf8d7fe4
--- /dev/null
+++ b/include/linux/setbits.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __LINUX_SETBITS_H
+#define __LINUX_SETBITS_H
+
+#include <linux/io.h>
+
+#define __setbits(rfn, wfn, addr, set) wfn((rfn(addr) | (set)), addr)
+#define __clrbits(rfn, wfn, addr, mask) wfn((rfn(addr) & ~(mask)), addr)
+#define __clrsetbits(rfn, wfn, addr, mask, set) wfn(((rfn(addr) & ~(mask)) | (set)), addr)
+#define __setclrbits(rfn, wfn, addr, mask, set) wfn(((rfn(addr) | (set)) & ~(mask)), addr)
+
+#ifndef setbits_le32
+#define setbits_le32(addr, set) __setbits(readl, writel, addr, set)
+#endif
+#ifndef setbits_le32_relaxed
+#define setbits_le32_relaxed(addr, set) __setbits(readl_relaxed, writel_relaxed, \
+ addr, set)
+#endif
+
+#ifndef clrbits_le32
+#define clrbits_le32(addr, mask) __clrbits(readl, writel, addr, mask)
+#endif
+#ifndef clrbits_le32_relaxed
+#define clrbits_le32_relaxed(addr, mask) __clrbits(readl_relaxed, writel_relaxed, \
+ addr, mask)
+#endif
+
+#ifndef clrsetbits_le32
+#define clrsetbits_le32(addr, mask, set) __clrsetbits(readl, writel, addr, mask, set)
+#endif
+#ifndef clrsetbits_le32_relaxed
+#define clrsetbits_le32_relaxed(addr, mask, set) __clrsetbits(readl_relaxed, \
+ writel_relaxed, \
+ addr, mask, set)
+#endif
+
+#ifndef setclrbits_le32
+#define setclrbits_le32(addr, mask, set) __setclrbits(readl, writel, addr, mask, set)
+#endif
+#ifndef setclrbits_le32_relaxed
+#define setclrbits_le32_relaxed(addr, mask, set) __setclrbits(readl_relaxed, \
+ writel_relaxed, \
+ addr, mask, set)
+#endif
+
+/* We cannot use CONFIG_64BIT as some x86 drivers use non-atomicwriteq() */
+#if defined(writeq) && defined(readq)
+#ifndef setbits_le64
+#define setbits_le64(addr, set) __setbits(readq, writeq, addr, set)
+#endif
+#ifndef setbits_le64_relaxed
+#define setbits_le64_relaxed(addr, set) __setbits(readq_relaxed, writeq_relaxed, \
+ addr, set)
+#endif
+
+#ifndef clrbits_le64
+#define clrbits_le64(addr, mask) __clrbits(readq, writeq, addr, mask)
+#endif
+#ifndef clrbits_le64_relaxed
+#define clrbits_le64_relaxed(addr, mask) __clrbits(readq_relaxed, writeq_relaxed, \
+ addr, mask)
+#endif
+
+#ifndef clrsetbits_le64
+#define clrsetbits_le64(addr, mask, set) __clrsetbits(readq, writeq, addr, mask, set)
+#endif
+#ifndef clrsetbits_le64_relaxed
+#define clrsetbits_le64_relaxed(addr, mask, set) __clrsetbits(readq_relaxed, \
+ writeq_relaxed, \
+ addr, mask, set)
+#endif
+
+#ifndef setclrbits_le64
+#define setclrbits_le64(addr, mask, set) __setclrbits(readq, writeq, addr, mask, set)
+#endif
+#ifndef setclrbits_le64_relaxed
+#define setclrbits_le64_relaxed(addr, mask, set) __setclrbits(readq_relaxed, \
+ writeq_relaxed, \
+ addr, mask, set)
+#endif
+
+#endif /* writeq/readq */
+
+#endif /* __LINUX_SETBITS_H */
--
2.18.1
^ permalink raw reply related
* [PATCH v3 0/7] include: add setbits32/clrbits32/clrsetbits32/setbits64/clrbits64/clrsetbits64
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
Hello
This patchset adds a new set of functions which are open-coded in lot of
place.
Basicly the pattern is always the same, "read, modify a bit, write"
some driver and the powerpc arch already have thoses pattern them as functions. (like ahci_sunxi.c or dwmac-meson8b)
The first patch rename some powerpc functions for being consistent with
the new name convention.
The second patch adds the header with all setbits functions.
The third patch is a try to implement a coccinelle semantic patch to
find all place where xxxbits function could be used.
It should not be merged since it is un-finalized.
For the moment, the "add setbits.h header" is not working and need a future
coccinelle version.
The four last patch are example of some drivers conversion.
Thoses patchs give an example of the reduction of code won by using xxxbits32.
I would like to thanks Julia Lawall for her help on the coccinelle
patch.
Note that I dont know which maintainer will take the linux/setbits.h include patch.
Regards
Changes since v2:
- Fixed patch title
- Fixed style problems
- shorted macro arguments name
Changes since v1:
- renamed LE functions to _leXX
- updated coccinnelle patch with JLawall's comments
Corentin Labbe (7):
powerpc: rename setbits32/clrbits32 to setbits_be32/clrbits_be32
include: add setbits_leXX/clrbits_leXX/clrsetbits_leXX in
linux/setbits.h
coccinelle: add xxxsetbits_leXX converting spatch
ata: ahci_sunxi: use xxxsetbitsi_le32 functions
net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits_le32
drm: meson: use xxxsetbits_le32
net: stmmac: dwmac-meson8b: use xxxsetbits_le32
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 +-
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 12 +-
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +-
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 +-
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 6 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 6 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 6 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 6 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +-
.../platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-
arch/powerpc/platforms/embedded6xx/wii.c | 12 +-
arch/powerpc/sysdev/cpm1.c | 26 +-
arch/powerpc/sysdev/cpm2.c | 16 +-
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 16 +-
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 12 +-
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74 +--
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 9 +-
arch/powerpc/sysdev/mpic_timer.c | 12 +-
drivers/ata/ahci_sunxi.c | 62 +--
drivers/gpu/drm/meson/meson_crtc.c | 14 +-
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +-
drivers/gpu/drm/meson/meson_plane.c | 13 +-
drivers/gpu/drm/meson/meson_registers.h | 3 -
drivers/gpu/drm/meson/meson_venc.c | 13 +-
drivers/gpu/drm/meson/meson_venc_cvbs.c | 4 +-
drivers/gpu/drm/meson/meson_viu.c | 65 +--
drivers/gpu/drm/meson/meson_vpp.c | 22 +-
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 56 +-
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +--
include/linux/setbits.h | 84 +++
scripts/add_new_include_in_source.py | 61 +++
scripts/coccinelle/misc/setbits32.cocci | 487 ++++++++++++++++++
.../coccinelle/misc/setbits32_relaxed.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits64.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits_dev.cocci | 235 +++++++++
58 files changed, 2172 insertions(+), 395 deletions(-)
create mode 100644 include/linux/setbits.h
create mode 100755 scripts/add_new_include_in_source.py
create mode 100644 scripts/coccinelle/misc/setbits32.cocci
create mode 100644 scripts/coccinelle/misc/setbits32_relaxed.cocci
create mode 100644 scripts/coccinelle/misc/setbits64.cocci
create mode 100644 scripts/coccinelle/misc/setbits_dev.cocci
--
2.18.1
^ permalink raw reply
* [PATCH v3 1/7] powerpc: rename setbits32/clrbits32 to setbits_be32/clrbits_be32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
Since setbits32/clrbits32 work on be32, it's better to remove ambiguity on
the used data type.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
arch/powerpc/include/asm/fsl_lbc.h | 2 +-
arch/powerpc/include/asm/io.h | 4 +-
arch/powerpc/platforms/44x/canyonlands.c | 4 +-
arch/powerpc/platforms/4xx/gpio.c | 28 +++----
arch/powerpc/platforms/512x/pdm360ng.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 6 +-
arch/powerpc/platforms/52xx/mpc52xx_gpt.c | 12 +--
arch/powerpc/platforms/82xx/ep8248e.c | 2 +-
arch/powerpc/platforms/82xx/km82xx.c | 6 +-
arch/powerpc/platforms/82xx/mpc8272_ads.c | 10 +--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c | 4 +-
arch/powerpc/platforms/82xx/pq2fads.c | 10 +--
arch/powerpc/platforms/83xx/km83xx.c | 6 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c | 4 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 2 +-
arch/powerpc/platforms/85xx/p1022_ds.c | 6 +-
arch/powerpc/platforms/85xx/p1022_rdk.c | 6 +-
arch/powerpc/platforms/85xx/t1042rdb_diu.c | 6 +-
arch/powerpc/platforms/85xx/twr_p102x.c | 2 +-
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 6 +-
arch/powerpc/platforms/8xx/adder875.c | 2 +-
arch/powerpc/platforms/8xx/m8xx_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc86xads_setup.c | 4 +-
arch/powerpc/platforms/8xx/mpc885ads_setup.c | 28 +++----
.../platforms/embedded6xx/flipper-pic.c | 6 +-
arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 8 +-
arch/powerpc/platforms/embedded6xx/wii.c | 12 +--
arch/powerpc/sysdev/cpm1.c | 26 +++----
arch/powerpc/sysdev/cpm2.c | 16 ++--
arch/powerpc/sysdev/cpm_common.c | 4 +-
arch/powerpc/sysdev/fsl_85xx_l2ctlr.c | 16 ++--
arch/powerpc/sysdev/fsl_lbc.c | 2 +-
arch/powerpc/sysdev/fsl_pci.c | 12 +--
arch/powerpc/sysdev/fsl_pmc.c | 2 +-
arch/powerpc/sysdev/fsl_rcpm.c | 74 +++++++++----------
arch/powerpc/sysdev/fsl_rio.c | 4 +-
arch/powerpc/sysdev/fsl_rmu.c | 9 ++-
arch/powerpc/sysdev/mpic_timer.c | 12 +--
41 files changed, 190 insertions(+), 189 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index c7240a024b96..4d6a56b48a28 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -276,7 +276,7 @@ static inline void fsl_upm_start_pattern(struct fsl_upm *upm, u8 pat_offset)
*/
static inline void fsl_upm_end_pattern(struct fsl_upm *upm)
{
- clrbits32(upm->mxmr, MxMR_OP_RP);
+ clrbits_be32(upm->mxmr, MxMR_OP_RP);
while (in_be32(upm->mxmr) & MxMR_OP_RP)
cpu_relax();
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 0a034519957d..bc2fc014fd4f 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -882,8 +882,8 @@ static inline void * bus_to_virt(unsigned long address)
#endif /* CONFIG_PPC32 */
/* access ports */
-#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
-#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+#define setbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits_be32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
diff --git a/arch/powerpc/platforms/44x/canyonlands.c b/arch/powerpc/platforms/44x/canyonlands.c
index 157f4ce46386..6aeb4ca64d09 100644
--- a/arch/powerpc/platforms/44x/canyonlands.c
+++ b/arch/powerpc/platforms/44x/canyonlands.c
@@ -113,8 +113,8 @@ static int __init ppc460ex_canyonlands_fixup(void)
* USB2HStop and gpio19 will be USB2DStop. For more details refer to
* table 34-7 of PPC460EX user manual.
*/
- setbits32((vaddr + GPIO0_OSRH), 0x42000000);
- setbits32((vaddr + GPIO0_TSRH), 0x42000000);
+ setbits_be32((vaddr + GPIO0_OSRH), 0x42000000);
+ setbits_be32((vaddr + GPIO0_TSRH), 0x42000000);
err_gpio:
iounmap(vaddr);
err_bcsr:
diff --git a/arch/powerpc/platforms/4xx/gpio.c b/arch/powerpc/platforms/4xx/gpio.c
index 2238e369cde4..8436da0617fd 100644
--- a/arch/powerpc/platforms/4xx/gpio.c
+++ b/arch/powerpc/platforms/4xx/gpio.c
@@ -82,9 +82,9 @@ __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
if (val)
- setbits32(®s->or, GPIO_MASK(gpio));
+ setbits_be32(®s->or, GPIO_MASK(gpio));
else
- clrbits32(®s->or, GPIO_MASK(gpio));
+ clrbits_be32(®s->or, GPIO_MASK(gpio));
}
static void
@@ -112,18 +112,18 @@ static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&chip->lock, flags);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits_be32(®s->odr, GPIO_MASK(gpio));
/* Float the pin */
- clrbits32(®s->tcr, GPIO_MASK(gpio));
+ clrbits_be32(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
@@ -145,18 +145,18 @@ ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
__ppc4xx_gpio_set(gc, gpio, val);
/* Disable open-drain function */
- clrbits32(®s->odr, GPIO_MASK(gpio));
+ clrbits_be32(®s->odr, GPIO_MASK(gpio));
/* Drive the pin */
- setbits32(®s->tcr, GPIO_MASK(gpio));
+ setbits_be32(®s->tcr, GPIO_MASK(gpio));
/* Bits 0-15 use TSRL, bits 16-31 use TSRH */
if (gpio < 16) {
- clrbits32(®s->osrl, GPIO_MASK2(gpio));
- clrbits32(®s->tsrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrl, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrl, GPIO_MASK2(gpio));
} else {
- clrbits32(®s->osrh, GPIO_MASK2(gpio));
- clrbits32(®s->tsrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->osrh, GPIO_MASK2(gpio));
+ clrbits_be32(®s->tsrh, GPIO_MASK2(gpio));
}
spin_unlock_irqrestore(&chip->lock, flags);
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
index dc81f05e0bce..06b95795267a 100644
--- a/arch/powerpc/platforms/512x/pdm360ng.c
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -38,7 +38,7 @@ static int pdm360ng_get_pendown_state(void)
reg = in_be32(pdm360ng_gpio_base + 0xc);
if (reg & 0x40)
- setbits32(pdm360ng_gpio_base + 0xc, 0x40);
+ setbits_be32(pdm360ng_gpio_base + 0xc, 0x40);
reg = in_be32(pdm360ng_gpio_base + 0x8);
@@ -69,8 +69,8 @@ static int __init pdm360ng_penirq_init(void)
return -ENODEV;
}
out_be32(pdm360ng_gpio_base + 0xc, 0xffffffff);
- setbits32(pdm360ng_gpio_base + 0x18, 0x2000);
- setbits32(pdm360ng_gpio_base + 0x10, 0x40);
+ setbits_be32(pdm360ng_gpio_base + 0x18, 0x2000);
+ setbits_be32(pdm360ng_gpio_base + 0x10, 0x40);
return 0;
}
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index 565e3a83dc9e..edfe619d67bf 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -314,13 +314,13 @@ int mpc5200_psc_ac97_gpio_reset(int psc_number)
/* enable gpio pins for output */
setbits8(&wkup_gpio->wkup_gpioe, reset);
- setbits32(&simple_gpio->simple_gpioe, sync | out);
+ setbits_be32(&simple_gpio->simple_gpioe, sync | out);
setbits8(&wkup_gpio->wkup_ddr, reset);
- setbits32(&simple_gpio->simple_ddr, sync | out);
+ setbits_be32(&simple_gpio->simple_ddr, sync | out);
/* Assert cold reset */
- clrbits32(&simple_gpio->simple_dvo, sync | out);
+ clrbits_be32(&simple_gpio->simple_dvo, sync | out);
clrbits8(&wkup_gpio->wkup_dvo, reset);
/* wait for 1 us */
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 17cf249b18ee..833cc33ebf91 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -142,7 +142,7 @@ static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ setbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -152,7 +152,7 @@ static void mpc52xx_gpt_irq_mask(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
}
@@ -308,7 +308,7 @@ static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
raw_spin_lock_irqsave(&gpt->lock, flags);
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
@@ -482,7 +482,7 @@ int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
return -EBUSY;
}
- clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
+ clrbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
raw_spin_unlock_irqrestore(&gpt->lock, flags);
return 0;
}
@@ -639,8 +639,8 @@ static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
unsigned long flags;
raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
- clrbits32(&gpt_wdt->regs->mode,
- MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
+ clrbits_be32(&gpt_wdt->regs->mode,
+ MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
#endif
diff --git a/arch/powerpc/platforms/82xx/ep8248e.c b/arch/powerpc/platforms/82xx/ep8248e.c
index 8fec050f2d5b..18626cd3db16 100644
--- a/arch/powerpc/platforms/82xx/ep8248e.c
+++ b/arch/powerpc/platforms/82xx/ep8248e.c
@@ -262,7 +262,7 @@ static void __init ep8248e_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
ep8248e_bcsr_node =
of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index 28860e40b5db..27d16d1a89f5 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -157,9 +157,9 @@ static void __init init_ioports(void)
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
/* Force USB FULL SPEED bit to '1' */
- setbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
+ setbits_be32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 10));
/* clear USB_SLAVE */
- clrbits32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
+ clrbits_be32(&cpm2_immr->im_ioport.iop_pdata, 1 << (31 - 11));
}
static void __init km82xx_setup_arch(void)
@@ -172,7 +172,7 @@ static void __init km82xx_setup_arch(void)
/* When this is set, snooping CPM DMA from RAM causes
* machine checks. See erratum SIU18.
*/
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
init_ioports();
diff --git a/arch/powerpc/platforms/82xx/mpc8272_ads.c b/arch/powerpc/platforms/82xx/mpc8272_ads.c
index d23c10a96bde..75338e9e8acc 100644
--- a/arch/powerpc/platforms/82xx/mpc8272_ads.c
+++ b/arch/powerpc/platforms/82xx/mpc8272_ads.c
@@ -164,13 +164,13 @@ static void __init mpc8272_ads_setup_arch(void)
#define BCSR3_FETHIEN2 0x10000000
#define BCSR3_FETH2_RST 0x08000000
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits_be32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits_be32(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits_be32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits_be32(&bcsr[3], BCSR3_FETH2_RST);
- clrbits32(&bcsr[3], BCSR3_USB_nEN);
+ clrbits_be32(&bcsr[3], BCSR3_USB_nEN);
iounmap(bcsr);
diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c
index c4f7029fc9ae..92f2b4a5dcc8 100644
--- a/arch/powerpc/platforms/82xx/pq2.c
+++ b/arch/powerpc/platforms/82xx/pq2.c
@@ -25,7 +25,7 @@
void __noreturn pq2_restart(char *cmd)
{
local_irq_disable();
- setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
+ setbits_be32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE);
/* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 8b065bdf7412..060400ec3ebb 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -47,7 +47,7 @@ static void pq2ads_pci_mask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- setbits32(&priv->regs->mask, 1 << irq);
+ setbits_be32(&priv->regs->mask, 1 << irq);
mb();
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
@@ -63,7 +63,7 @@ static void pq2ads_pci_unmask_irq(struct irq_data *d)
unsigned long flags;
raw_spin_lock_irqsave(&pci_pic_lock, flags);
- clrbits32(&priv->regs->mask, 1 << irq);
+ clrbits_be32(&priv->regs->mask, 1 << irq);
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
}
}
diff --git a/arch/powerpc/platforms/82xx/pq2fads.c b/arch/powerpc/platforms/82xx/pq2fads.c
index 6c654dc74a4b..84b637e019ed 100644
--- a/arch/powerpc/platforms/82xx/pq2fads.c
+++ b/arch/powerpc/platforms/82xx/pq2fads.c
@@ -140,18 +140,18 @@ static void __init pq2fads_setup_arch(void)
/* Enable the serial and ethernet ports */
- clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
- setbits32(&bcsr[1], BCSR1_FETH_RST);
+ clrbits_be32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
+ setbits_be32(&bcsr[1], BCSR1_FETH_RST);
- clrbits32(&bcsr[3], BCSR3_FETHIEN2);
- setbits32(&bcsr[3], BCSR3_FETH2_RST);
+ clrbits_be32(&bcsr[3], BCSR3_FETHIEN2);
+ setbits_be32(&bcsr[3], BCSR3_FETH2_RST);
iounmap(bcsr);
init_ioports();
/* Enable external IRQs */
- clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
+ clrbits_be32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
pq2_init_pci();
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index d8642a4afc74..d036b179dc65 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -101,19 +101,19 @@ static void quirk_mpc8360e_qe_enet10(void)
* UCC1: write 0b11 to bits 18:19
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x00003000);
+ setbits_be32((base + 0xa8), 0x00003000);
/*
* UCC2 option 1: write 0b11 to bits 4:5
* at address IMMRBAR+0x14A8
*/
- setbits32((base + 0xa8), 0x0c000000);
+ setbits_be32((base + 0xa8), 0x0c000000);
/*
* UCC2 option 2: write 0b11 to bits 16:17
* at address IMMRBAR+0x14AC
*/
- setbits32((base + 0xac), 0x0000c000);
+ setbits_be32((base + 0xac), 0x0000c000);
}
iounmap(base);
of_node_put(np_par);
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index fd44dd03e1f3..83a5e27e2f63 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -118,7 +118,7 @@ static void __init mpc836x_mds_setup_arch(void)
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
- setbits32(immap, 0x0c003000);
+ setbits_be32(immap, 0x0c003000);
/*
* IMMR + 0x14AC[20:27] = 10101010
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d7e440e6dba3..52b4fb179c9e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -262,7 +262,7 @@ static void __init mpc85xx_mds_qe_init(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
index f05325f0cc03..926d0f9dc29d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_pm_ops.c
@@ -60,9 +60,9 @@ static void mpc85xx_freeze_time_base(bool freeze)
mask = CCSR_GUTS_DEVDISR_TB0 | CCSR_GUTS_DEVDISR_TB1;
if (freeze)
- setbits32(&guts->devdisr, mask);
+ setbits_be32(&guts->devdisr, mask);
else
- clrbits32(&guts->devdisr, mask);
+ clrbits_be32(&guts->devdisr, mask);
in_be32(&guts->devdisr);
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 10069503e39f..fdea28dd90dd 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -115,7 +115,7 @@ static void __init mpc85xx_rdb_setup_arch(void)
* and QE12 for QE MII management singals in PMUXCR
* register.
*/
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 9fb57f78cdbe..a2fbe4a592f0 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -405,11 +405,11 @@ void p1022ds_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/p1022_rdk.c b/arch/powerpc/platforms/85xx/p1022_rdk.c
index 276e00ab3dde..7eaec20faa95 100644
--- a/arch/powerpc/platforms/85xx/p1022_rdk.c
+++ b/arch/powerpc/platforms/85xx/p1022_rdk.c
@@ -75,11 +75,11 @@ void p1022rdk_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/85xx/t1042rdb_diu.c b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
index dac36ba82fea..dffe44451fb9 100644
--- a/arch/powerpc/platforms/85xx/t1042rdb_diu.c
+++ b/arch/powerpc/platforms/85xx/t1042rdb_diu.c
@@ -114,11 +114,11 @@ static void t1042rdb_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 255);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(scfg + CCSR_SCFG_PIXCLKCR,
- PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
+ clrbits_be32(scfg + CCSR_SCFG_PIXCLKCR,
+ PIXCLKCR_PXCKEN | PIXCLKCR_PXCKDLY | PIXCLKCR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
+ setbits_be32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16));
iounmap(scfg);
}
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 360f6253e9ff..5c385ebf6cac 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -95,7 +95,7 @@ static void __init twr_p1025_setup_arch(void)
* and QE12 for QE MII management signals in PMUXCR
* register.
* Set QE mux bits in PMUXCR */
- setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
+ setbits_be32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
MPC85xx_PMUXCR_QE(3) |
MPC85xx_PMUXCR_QE(9) |
MPC85xx_PMUXCR_QE(12));
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index a5d73fabe4d1..ddd5a525dd3f 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -261,11 +261,11 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
pxclk = clamp_t(u32, pxclk, 2, 31);
/* Disable the pixel clock, and set it to non-inverted and no delay */
- clrbits32(&guts->clkdvdr,
- CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
+ clrbits_be32(&guts->clkdvdr,
+ CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
/* Enable the clock and set the pxclk */
- setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
+ setbits_be32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
iounmap(guts);
}
diff --git a/arch/powerpc/platforms/8xx/adder875.c b/arch/powerpc/platforms/8xx/adder875.c
index bcef9f66191e..7bfae1617cfa 100644
--- a/arch/powerpc/platforms/8xx/adder875.c
+++ b/arch/powerpc/platforms/8xx/adder875.c
@@ -77,7 +77,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init adder875_setup(void)
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index f1c805c8adbc..ebdc3754b99f 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -103,7 +103,7 @@ void __init mpc8xx_calibrate_decr(void)
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
- setbits32(&clk_r2->car_sccr, 0x02000000);
+ setbits_be32(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
@@ -204,7 +204,7 @@ void __noreturn mpc8xx_restart(char *cmd)
local_irq_disable();
- setbits32(&clk_r->car_plprcr, 0x00000080);
+ setbits_be32(&clk_r->car_plprcr, 0x00000080);
/* Clear the ME bit in MSR to cause checkstop on machine check
*/
mtmsr(mfmsr() & ~0x1000);
diff --git a/arch/powerpc/platforms/8xx/mpc86xads_setup.c b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
index 8d02f5ff4481..88c611ecee0a 100644
--- a/arch/powerpc/platforms/8xx/mpc86xads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc86xads_setup.c
@@ -87,7 +87,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc86xads_setup_arch(void)
@@ -112,7 +112,7 @@ static void __init mpc86xads_setup_arch(void)
return;
}
- clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
+ clrbits_be32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
iounmap(bcsr_io);
}
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
index a0c83c1905c6..17e10250830b 100644
--- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -123,7 +123,7 @@ static void __init init_ioports(void)
cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
/* Set FEC1 and FEC2 to MII mode */
- clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
}
static void __init mpc885ads_setup_arch(void)
@@ -148,33 +148,33 @@ static void __init mpc885ads_setup_arch(void)
return;
}
- clrbits32(&bcsr[1], BCSR1_RS232EN_1);
+ clrbits_be32(&bcsr[1], BCSR1_RS232EN_1);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- setbits32(&bcsr[1], BCSR1_RS232EN_2);
+ setbits_be32(&bcsr[1], BCSR1_RS232EN_2);
#else
- clrbits32(&bcsr[1], BCSR1_RS232EN_2);
+ clrbits_be32(&bcsr[1], BCSR1_RS232EN_2);
#endif
- clrbits32(bcsr5, BCSR5_MII1_EN);
- setbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits_be32(bcsr5, BCSR5_MII1_EN);
+ setbits_be32(bcsr5, BCSR5_MII1_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII1_RST);
+ clrbits_be32(bcsr5, BCSR5_MII1_RST);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
- clrbits32(bcsr5, BCSR5_MII2_EN);
- setbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits_be32(bcsr5, BCSR5_MII2_EN);
+ setbits_be32(bcsr5, BCSR5_MII2_RST);
udelay(1000);
- clrbits32(bcsr5, BCSR5_MII2_RST);
+ clrbits_be32(bcsr5, BCSR5_MII2_RST);
#else
- setbits32(bcsr5, BCSR5_MII2_EN);
+ setbits_be32(bcsr5, BCSR5_MII2_EN);
#endif
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
- clrbits32(&bcsr[4], BCSR4_ETH10_RST);
+ clrbits_be32(&bcsr[4], BCSR4_ETH10_RST);
udelay(1000);
- setbits32(&bcsr[4], BCSR4_ETH10_RST);
+ setbits_be32(&bcsr[4], BCSR4_ETH10_RST);
- setbits32(&bcsr[1], BCSR1_ETHEN);
+ setbits_be32(&bcsr[1], BCSR1_ETHEN);
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
#else
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
index db0be007fd06..658f972d277a 100644
--- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -53,7 +53,7 @@ static void flipper_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + FLIPPER_IMR, mask);
+ clrbits_be32(io_base + FLIPPER_IMR, mask);
/* this is at least needed for RSW */
out_be32(io_base + FLIPPER_ICR, mask);
}
@@ -72,7 +72,7 @@ static void flipper_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + FLIPPER_IMR, 1 << irq);
+ clrbits_be32(io_base + FLIPPER_IMR, 1 << irq);
}
static void flipper_pic_unmask(struct irq_data *d)
@@ -80,7 +80,7 @@ static void flipper_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + FLIPPER_IMR, 1 << irq);
+ setbits_be32(io_base + FLIPPER_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 8112b39879d6..a5431ad4a529 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -50,7 +50,7 @@ static void hlwd_pic_mask_and_ack(struct irq_data *d)
void __iomem *io_base = irq_data_get_irq_chip_data(d);
u32 mask = 1 << irq;
- clrbits32(io_base + HW_BROADWAY_IMR, mask);
+ clrbits_be32(io_base + HW_BROADWAY_IMR, mask);
out_be32(io_base + HW_BROADWAY_ICR, mask);
}
@@ -67,7 +67,7 @@ static void hlwd_pic_mask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ clrbits_be32(io_base + HW_BROADWAY_IMR, 1 << irq);
}
static void hlwd_pic_unmask(struct irq_data *d)
@@ -75,10 +75,10 @@ static void hlwd_pic_unmask(struct irq_data *d)
int irq = irqd_to_hwirq(d);
void __iomem *io_base = irq_data_get_irq_chip_data(d);
- setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
+ setbits_be32(io_base + HW_BROADWAY_IMR, 1 << irq);
/* Make sure the ARM (aka. Starlet) doesn't handle this interrupt. */
- clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
+ clrbits_be32(io_base + HW_STARLET_IMR, 1 << irq);
}
diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c
index ecf703ee3a76..a7a62871e68f 100644
--- a/arch/powerpc/platforms/embedded6xx/wii.c
+++ b/arch/powerpc/platforms/embedded6xx/wii.c
@@ -134,8 +134,8 @@ static void __init wii_setup_arch(void)
hw_gpio = wii_ioremap_hw_regs("hw_gpio", HW_GPIO_COMPATIBLE);
if (hw_gpio) {
/* turn off the front blue led and IR light */
- clrbits32(hw_gpio + HW_GPIO_OUT(0),
- HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
+ clrbits_be32(hw_gpio + HW_GPIO_OUT(0),
+ HW_GPIO_SLOT_LED | HW_GPIO_SENSOR_BAR);
}
}
@@ -145,7 +145,7 @@ static void __noreturn wii_restart(char *cmd)
if (hw_ctrl) {
/* clear the system reset pin to cause a reset */
- clrbits32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
+ clrbits_be32(hw_ctrl + HW_CTRL_RESETS, HW_CTRL_RESETS_SYS);
}
wii_spin();
}
@@ -159,13 +159,13 @@ static void wii_power_off(void)
* set the owner of the shutdown pin to ARM, because it is
* accessed through the registers for the ARM, below
*/
- clrbits32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
+ clrbits_be32(hw_gpio + HW_GPIO_OWNER, HW_GPIO_SHUTDOWN);
/* make sure that the poweroff GPIO is configured as output */
- setbits32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
+ setbits_be32(hw_gpio + HW_GPIO_DIR(1), HW_GPIO_SHUTDOWN);
/* drive the poweroff GPIO high */
- setbits32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
+ setbits_be32(hw_gpio + HW_GPIO_OUT(1), HW_GPIO_SHUTDOWN);
}
wii_spin();
}
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 4f8dcf124828..7fcbf8c059eb 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -60,14 +60,14 @@ static void cpm_mask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ clrbits_be32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_unmask_irq(struct irq_data *d)
{
unsigned int cpm_vec = (unsigned int)irqd_to_hwirq(d);
- setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
+ setbits_be32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
}
static void cpm_end_irq(struct irq_data *d)
@@ -188,7 +188,7 @@ unsigned int cpm_pic_init(void)
if (setup_irq(eirq, &cpm_error_irqaction))
printk(KERN_ERR "Could not allocate CPM error IRQ!");
- setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
+ setbits_be32(&cpic_reg->cpic_cicr, CICR_IEN);
end:
of_node_put(np);
@@ -317,14 +317,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
&mpc8xx_immr->im_cpm.cp_pedir;
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop->dir, pin);
+ setbits_be32(&iop->dir, pin);
else
- clrbits32(&iop->dir, pin);
+ clrbits_be32(&iop->dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop->par, pin);
+ setbits_be32(&iop->par, pin);
else
- clrbits32(&iop->par, pin);
+ clrbits_be32(&iop->par, pin);
if (port == CPM_PORTB) {
if (flags & CPM_PIN_OPENDRAIN)
@@ -335,14 +335,14 @@ static void cpm1_set_pin32(int port, int pin, int flags)
if (port == CPM_PORTE) {
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop->sor, pin);
+ setbits_be32(&iop->sor, pin);
else
- clrbits32(&iop->sor, pin);
+ clrbits_be32(&iop->sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ setbits_be32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
else
- clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
+ clrbits_be32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
}
}
@@ -732,7 +732,7 @@ static int cpm1_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits_be32(&iop->dir, pin_mask);
__cpm1_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
@@ -750,7 +750,7 @@ static int cpm1_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm1_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits_be32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm1_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 07718b9a2c99..e8c7a0117eed 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -335,22 +335,22 @@ void cpm2_set_pin(int port, int pin, int flags)
pin = 1 << (31 - pin);
if (flags & CPM_PIN_OUTPUT)
- setbits32(&iop[port].dir, pin);
+ setbits_be32(&iop[port].dir, pin);
else
- clrbits32(&iop[port].dir, pin);
+ clrbits_be32(&iop[port].dir, pin);
if (!(flags & CPM_PIN_GPIO))
- setbits32(&iop[port].par, pin);
+ setbits_be32(&iop[port].par, pin);
else
- clrbits32(&iop[port].par, pin);
+ clrbits_be32(&iop[port].par, pin);
if (flags & CPM_PIN_SECONDARY)
- setbits32(&iop[port].sor, pin);
+ setbits_be32(&iop[port].sor, pin);
else
- clrbits32(&iop[port].sor, pin);
+ clrbits_be32(&iop[port].sor, pin);
if (flags & CPM_PIN_OPENDRAIN)
- setbits32(&iop[port].odr, pin);
+ setbits_be32(&iop[port].odr, pin);
else
- clrbits32(&iop[port].odr, pin);
+ clrbits_be32(&iop[port].odr, pin);
}
diff --git a/arch/powerpc/sysdev/cpm_common.c b/arch/powerpc/sysdev/cpm_common.c
index b74508175b67..8f4fba3067c9 100644
--- a/arch/powerpc/sysdev/cpm_common.c
+++ b/arch/powerpc/sysdev/cpm_common.c
@@ -165,7 +165,7 @@ static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- setbits32(&iop->dir, pin_mask);
+ setbits_be32(&iop->dir, pin_mask);
__cpm2_gpio32_set(mm_gc, pin_mask, val);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
@@ -183,7 +183,7 @@ static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
spin_lock_irqsave(&cpm2_gc->lock, flags);
- clrbits32(&iop->dir, pin_mask);
+ clrbits_be32(&iop->dir, pin_mask);
spin_unlock_irqrestore(&cpm2_gc->lock, flags);
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index c27058e5df26..cf80b8dc3366 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -124,24 +124,24 @@ static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
switch (ways) {
case LOCK_WAYS_EIGHTH:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
break;
case LOCK_WAYS_TWO_EIGHTH:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
break;
case LOCK_WAYS_HALF:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
break;
case LOCK_WAYS_FULL:
default:
- setbits32(&l2ctlr->ctl,
- L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
+ setbits_be32(&l2ctlr->ctl,
+ L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
break;
}
eieio();
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 5340a483cf55..0264f8c67a96 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -192,7 +192,7 @@ static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
/* clear event registers */
- setbits32(&lbc->ltesr, LTESR_CLEAR);
+ setbits_be32(&lbc->ltesr, LTESR_CLEAR);
out_be32(&lbc->lteatr, 0);
out_be32(&lbc->ltear, 0);
out_be32(&lbc->lteccr, LTECCR_CLEAR);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 918be816b097..9290d8a7335b 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1196,12 +1196,12 @@ static int fsl_pci_pme_probe(struct pci_controller *hose)
pci = hose->private_data;
/* Enable PTOD, ENL23D & EXL23D */
- clrbits32(&pci->pex_pme_mes_disr,
- PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+ clrbits_be32(&pci->pex_pme_mes_disr,
+ PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
out_be32(&pci->pex_pme_mes_ier, 0);
- setbits32(&pci->pex_pme_mes_ier,
- PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
+ setbits_be32(&pci->pex_pme_mes_ier,
+ PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
/* PME Enable */
pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
@@ -1218,7 +1218,7 @@ static void send_pme_turnoff_message(struct pci_controller *hose)
int i;
/* Send PME_Turn_Off Message Request */
- setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
+ setbits_be32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
/* Wait trun off done */
for (i = 0; i < 150; i++) {
@@ -1254,7 +1254,7 @@ static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
int i;
/* Send Exit L2 State Message */
- setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
+ setbits_be32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
/* Wait exit done */
for (i = 0; i < 150; i++) {
diff --git a/arch/powerpc/sysdev/fsl_pmc.c b/arch/powerpc/sysdev/fsl_pmc.c
index 232225e7f863..ff29fa6af01c 100644
--- a/arch/powerpc/sysdev/fsl_pmc.c
+++ b/arch/powerpc/sysdev/fsl_pmc.c
@@ -37,7 +37,7 @@ static int pmc_suspend_enter(suspend_state_t state)
{
int ret;
- setbits32(&pmc_regs->pmcsr, PMCSR_SLP);
+ setbits_be32(&pmc_regs->pmcsr, PMCSR_SLP);
/* At this point, the CPU is asleep. */
/* Upon resume, wait for SLP bit to be clear. */
diff --git a/arch/powerpc/sysdev/fsl_rcpm.c b/arch/powerpc/sysdev/fsl_rcpm.c
index 9259a94f70e1..fce703c400e6 100644
--- a/arch/powerpc/sysdev/fsl_rcpm.c
+++ b/arch/powerpc/sysdev/fsl_rcpm.c
@@ -33,10 +33,10 @@ static void rcpm_v1_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v1_regs->cpmimr, mask);
- setbits32(&rcpm_v1_regs->cpmcimr, mask);
- setbits32(&rcpm_v1_regs->cpmmcmr, mask);
- setbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmcimr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmmcmr, mask);
+ setbits_be32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_mask(int cpu)
@@ -44,10 +44,10 @@ static void rcpm_v2_irq_mask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- setbits32(&rcpm_v2_regs->tpmimr0, mask);
- setbits32(&rcpm_v2_regs->tpmcimr0, mask);
- setbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- setbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmcimr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmmcmr0, mask);
+ setbits_be32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_irq_unmask(int cpu)
@@ -55,10 +55,10 @@ static void rcpm_v1_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v1_regs->cpmimr, mask);
- clrbits32(&rcpm_v1_regs->cpmcimr, mask);
- clrbits32(&rcpm_v1_regs->cpmmcmr, mask);
- clrbits32(&rcpm_v1_regs->cpmnmimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmcimr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmmcmr, mask);
+ clrbits_be32(&rcpm_v1_regs->cpmnmimr, mask);
}
static void rcpm_v2_irq_unmask(int cpu)
@@ -66,26 +66,26 @@ static void rcpm_v2_irq_unmask(int cpu)
int hw_cpu = get_hard_smp_processor_id(cpu);
unsigned int mask = 1 << hw_cpu;
- clrbits32(&rcpm_v2_regs->tpmimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmcimr0, mask);
- clrbits32(&rcpm_v2_regs->tpmmcmr0, mask);
- clrbits32(&rcpm_v2_regs->tpmnmimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmcimr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmmcmr0, mask);
+ clrbits_be32(&rcpm_v2_regs->tpmnmimr0, mask);
}
static void rcpm_v1_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ setbits_be32(&rcpm_v1_regs->ippdexpcr, mask);
else
- clrbits32(&rcpm_v1_regs->ippdexpcr, mask);
+ clrbits_be32(&rcpm_v1_regs->ippdexpcr, mask);
}
static void rcpm_v2_set_ip_power(bool enable, u32 mask)
{
if (enable)
- setbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ setbits_be32(&rcpm_v2_regs->ippdexpcr[0], mask);
else
- clrbits32(&rcpm_v2_regs->ippdexpcr[0], mask);
+ clrbits_be32(&rcpm_v2_regs->ippdexpcr[0], mask);
}
static void rcpm_v1_cpu_enter_state(int cpu, int state)
@@ -95,10 +95,10 @@ static void rcpm_v1_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v1_regs->cdozcr, mask);
+ setbits_be32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v1_regs->cnapcr, mask);
+ setbits_be32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -114,16 +114,16 @@ static void rcpm_v2_cpu_enter_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
/* one bit corresponds to one thread for PH10 of 6500 */
- setbits32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
+ setbits_be32(&rcpm_v2_regs->tph10setr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph15setr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph20setr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30setr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph30setr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -172,10 +172,10 @@ static void rcpm_v1_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- clrbits32(&rcpm_v1_regs->cdozcr, mask);
+ clrbits_be32(&rcpm_v1_regs->cdozcr, mask);
break;
case E500_PM_PH15:
- clrbits32(&rcpm_v1_regs->cnapcr, mask);
+ clrbits_be32(&rcpm_v1_regs->cnapcr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -196,16 +196,16 @@ static void rcpm_v2_cpu_exit_state(int cpu, int state)
switch (state) {
case E500_PM_PH10:
- setbits32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
+ setbits_be32(&rcpm_v2_regs->tph10clrr0, 1 << hw_cpu);
break;
case E500_PM_PH15:
- setbits32(&rcpm_v2_regs->pcph15clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph15clrr, mask);
break;
case E500_PM_PH20:
- setbits32(&rcpm_v2_regs->pcph20clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph20clrr, mask);
break;
case E500_PM_PH30:
- setbits32(&rcpm_v2_regs->pcph30clrr, mask);
+ setbits_be32(&rcpm_v2_regs->pcph30clrr, mask);
break;
default:
pr_warn("Unknown cpu PM state (%d)\n", state);
@@ -226,7 +226,7 @@ static int rcpm_v1_plat_enter_state(int state)
switch (state) {
case PLAT_PM_SLEEP:
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_SLP);
/* Upon resume, wait for RCPM_POWMGTCSR_SLP bit to be clear. */
result = spin_event_timeout(
@@ -253,9 +253,9 @@ static int rcpm_v2_plat_enter_state(int state)
switch (state) {
case PLAT_PM_LPM20:
/* clear previous LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_P_LPM20_ST);
/* enter LPM20 status */
- setbits32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
+ setbits_be32(pmcsr_reg, RCPM_POWMGTCSR_LPM20_RQ);
/* At this point, the device is in LPM20 status. */
@@ -291,9 +291,9 @@ static void rcpm_common_freeze_time_base(u32 *tben_reg, int freeze)
if (freeze) {
mask = in_be32(tben_reg);
- clrbits32(tben_reg, mask);
+ clrbits_be32(tben_reg, mask);
} else {
- setbits32(tben_reg, mask);
+ setbits_be32(tben_reg, mask);
}
/* read back to push the previous write */
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 5011ffea4e4b..891e11d12222 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -668,10 +668,10 @@ int fsl_rio_setup(struct platform_device *dev)
out_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0);
/* Set 1x lane */
- setbits32(priv->regs_win
+ setbits_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0x02000000);
/* Enable ports */
- setbits32(priv->regs_win
+ setbits_be32(priv->regs_win
+ RIO_CCSR + i*0x20, 0x00600000);
msleep(100);
if (in_be32((priv->regs_win
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 88b35a3dcdc5..b4f49049d75d 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -355,7 +355,7 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
dmsg->sid, dmsg->tid,
dmsg->info);
}
- setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
+ setbits_be32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
}
@@ -909,10 +909,11 @@ fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
out_be32(&rmu->msg_regs->imr, 0x001b0060);
/* Set number of queue entries */
- setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
+ setbits_be32(&rmu->msg_regs->imr,
+ (get_bitmask_order(entries) - 2) << 12);
/* Now enable the unit */
- setbits32(&rmu->msg_regs->imr, 0x1);
+ setbits_be32(&rmu->msg_regs->imr, 0x1);
out:
return rc;
@@ -1015,7 +1016,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
out1:
- setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
+ setbits_be32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
out2:
return buf;
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
index 87e7c42777a8..5cc8216a85e5 100644
--- a/arch/powerpc/sysdev/mpic_timer.c
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -154,7 +154,7 @@ static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
tcr = casc_priv->tcr_value |
(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
- setbits32(priv->group_tcr, tcr);
+ setbits_be32(priv->group_tcr, tcr);
tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
@@ -253,7 +253,7 @@ void mpic_start_timer(struct mpic_timer *handle)
struct timer_group_priv *priv = container_of(handle,
struct timer_group_priv, timer[handle->num]);
- clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ clrbits_be32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
}
EXPORT_SYMBOL(mpic_start_timer);
@@ -269,7 +269,7 @@ void mpic_stop_timer(struct mpic_timer *handle)
struct timer_group_priv, timer[handle->num]);
struct cascade_priv *casc_priv;
- setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+ setbits_be32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
casc_priv = priv->timer[handle->num].cascade_handle;
if (casc_priv) {
@@ -340,7 +340,7 @@ void mpic_free_timer(struct mpic_timer *handle)
u32 tcr;
tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
MPIC_TIMER_TCR_ROVR_OFFSET);
- clrbits32(priv->group_tcr, tcr);
+ clrbits_be32(priv->group_tcr, tcr);
priv->idle |= casc_priv->cascade_map;
priv->timer[handle->num].cascade_handle = NULL;
} else {
@@ -508,7 +508,7 @@ static void timer_group_init(struct device_node *np)
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits_be32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
list_add_tail(&priv->node, &timer_group_list);
@@ -531,7 +531,7 @@ static void mpic_timer_resume(void)
list_for_each_entry(priv, &timer_group_list, node) {
/* Init FSL timer hardware */
if (priv->flags & FSL_GLOBAL_TIMER)
- setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+ setbits_be32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
}
}
--
2.18.1
^ permalink raw reply related
* [PATCH v3 4/7] ata: ahci_sunxi: use xxxsetbitsi_le32 functions
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch converts ahci_sunxi to use xxxsetbits_le32 functions
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/ata/ahci_sunxi.c | 62 +++++++++++-----------------------------
1 file changed, 17 insertions(+), 45 deletions(-)
diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c
index 911710643305..69c2e01c3d52 100644
--- a/drivers/ata/ahci_sunxi.c
+++ b/drivers/ata/ahci_sunxi.c
@@ -25,6 +25,7 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include <linux/setbits.h>
#include "ahci.h"
#define DRV_NAME "ahci-sunxi"
@@ -58,34 +59,6 @@ MODULE_PARM_DESC(enable_pmp,
#define AHCI_P0PHYCR 0x0178
#define AHCI_P0PHYSR 0x017c
-static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- writel(reg_val, reg);
-}
-
-static void sunxi_setbits(void __iomem *reg, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
-static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
-{
- u32 reg_val;
-
- reg_val = readl(reg);
- reg_val &= ~(clr_val);
- reg_val |= set_val;
- writel(reg_val, reg);
-}
-
static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
{
return (readl(reg) >> shift) & mask;
@@ -100,22 +73,21 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
writel(0, reg_base + AHCI_RWCR);
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
- (0x7 << 24),
- (0x5 << 24) | BIT(23) | BIT(18));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
- (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
- (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
- sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
- sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
- (0x7 << 20), (0x3 << 20));
- sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
- (0x1f << 5), (0x19 << 5));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 24),
+ (0x5 << 24) | BIT(23) | BIT(18));
+ clrsetbits_le32(reg_base + AHCI_PHYCS1R,
+ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
+ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
+ setbits_le32(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
+ clrbits_le32(reg_base + AHCI_PHYCS1R, BIT(19));
+ clrsetbits_le32(reg_base + AHCI_PHYCS0R,
+ (0x7 << 20), (0x3 << 20));
+ clrsetbits_le32(reg_base + AHCI_PHYCS2R,
+ (0x1f << 5), (0x19 << 5));
msleep(5);
- sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
+ setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19));
timeout = 250; /* Power up takes aprox 50 us */
do {
@@ -130,7 +102,7 @@ static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
udelay(1);
} while (1);
- sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
+ setbits_le32(reg_base + AHCI_PHYCS2R, (0x1 << 24));
timeout = 100; /* Calibration takes aprox 10 us */
do {
@@ -158,10 +130,10 @@ static void ahci_sunxi_start_engine(struct ata_port *ap)
struct ahci_host_priv *hpriv = ap->host->private_data;
/* Setup DMA before DMA start */
- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
+ clrsetbits_le32(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
/* Start DMA */
- sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
+ setbits_le32(port_mmio + PORT_CMD, PORT_CMD_START);
}
static const struct ata_port_info ahci_sunxi_port_info = {
--
2.18.1
^ permalink raw reply related
* [PATCH v3 3/7 DONOTMERGE] coccinelle: add xxxsetbits_leXX converting spatch
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch add a spatch which convert all open coded of setbits_le32/clrbits_le32/clrsetbits_le32
and their 64 bits counterparts.
Note that 64 and 32_relaxed are generated via
cp scripts/coccinelle/misc/setbits32.cocci scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,readl,readl_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,writel,writel_relaxed,' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,setbits_le32,setbits_le32_relaxed,g' scripts/coccinelle/misc/setbits32_relaxed.cocci
sed -i 's,clrbits_le32,clrbits_le32_relaxed,g' scripts/coccinelle/misc/setbits32_relaxed.cocci
cp scripts/coccinelle/misc/setbits32.cocci scripts/coccinelle/misc/setbits64.cocci
sed -i 's,readl,readq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,writel,writeq,' scripts/coccinelle/misc/setbits64.cocci
sed -i 's,le32,le64,' scripts/coccinelle/misc/setbits64.cocci
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
scripts/add_new_include_in_source.py | 61 +++
scripts/coccinelle/misc/setbits32.cocci | 487 ++++++++++++++++++
.../coccinelle/misc/setbits32_relaxed.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits64.cocci | 487 ++++++++++++++++++
scripts/coccinelle/misc/setbits_dev.cocci | 235 +++++++++
5 files changed, 1757 insertions(+)
create mode 100755 scripts/add_new_include_in_source.py
create mode 100644 scripts/coccinelle/misc/setbits32.cocci
create mode 100644 scripts/coccinelle/misc/setbits32_relaxed.cocci
create mode 100644 scripts/coccinelle/misc/setbits64.cocci
create mode 100644 scripts/coccinelle/misc/setbits_dev.cocci
diff --git a/scripts/add_new_include_in_source.py b/scripts/add_new_include_in_source.py
new file mode 100755
index 000000000000..a43ccfbf9921
--- /dev/null
+++ b/scripts/add_new_include_in_source.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python
+
+# add <linux/setbits.h>
+
+import os, sys
+import re
+import shutil
+
+if len(sys.argv) < 2:
+ print("Usage: %s pathtosourcefile" % (sys.argv[0]))
+ sys.exit(1)
+
+found_global_headers = False
+found_local_headers = False
+#first check it does already here
+with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if re.search("#include <linux/setbits.h>\n", line):
+ print("INFO: header already here")
+ sys.exit(0)
+ if re.search("^#include <", line):
+ found_global_headers = True
+ if re.search("^#include \"", line):
+ found_local_headers = True
+ fp.close()
+
+if not found_global_headers and not found_local_headers:
+ print("No header included do it at hand")
+ sys.exit(1)
+
+if found_global_headers:
+ done = False
+ inheader = False
+ with open("%s.new" % sys.argv[1], 'w') as fw:
+ with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if re.search("^#include <linux/", line):
+ inheader = True
+ if (not done and line[16] >= "s" and line[17] >= "e" and line[18] >= "t" and line[19] >= 'b'):
+ done = True
+ fw.write("#include <linux/setbits.h>\n")
+ if not done and not re.search("^#include <linux/", line) and inheader:
+ done = True
+ fw.write("#include <linux/setbits.h>\n")
+ fw.write(line)
+ fw.close()
+ fp.close()
+else:
+ done = False
+ with open("%s.new" % sys.argv[1], 'w') as fw:
+ with open(sys.argv[1], 'r') as fp:
+ for line in fp:
+ if not done and re.search("^#include \"", line):
+ fw.write("#include <linux/setbits.h>\n")
+ done = True
+ fw.write(line)
+ fw.close()
+ fp.close()
+
+shutil.move("%s.new" % sys.argv[1], sys.argv[1])
+print("%s done" % sys.argv[1])
diff --git a/scripts/coccinelle/misc/setbits32.cocci b/scripts/coccinelle/misc/setbits32.cocci
new file mode 100644
index 000000000000..71400cac6830
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l4@
+p1 << p_clrsetbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear | set;
+- writel(rr, addr);
++ clrsetbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_l3@
+p1 << p_clrsetbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) & ~mask | set, addr);
++ clrsetbits_le32(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p((readl(addr) & ~mask) | set, addr);
++ clrsetbits_le32(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set;
+- rr &= ~clear;
+- writel(rr, addr);
++ setclrbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_l4@
+p1 << p_setclrbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set & ~clear;
+- writel(rr, addr);
++ setclrbits_le32(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_l3@
+p1 << p_setclrbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) | set & ~mask, addr);
++ setclrbits_le32(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel@p((readl(addr) | set) & ~mask, addr);
++ setclrbits_le32(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+- writel(rr, addr);
++ clrbits_le32(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l3@
+p1 << p_clrbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- writel(rr & ~mask, addr);
++ clrbits_le32(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l2_a@
+p1 << p_clrbits_le32_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr) & ~mask;
+- writel(rr, addr);
++ clrbits_le32(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_l2_b@
+p1 << p_clrbits_le32_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writel@p(readl(addr) & ~mask, addr);
++ clrbits_le32(addr, mask);
+
+@script:python depends on p_clrbits_le32_oneliner@
+p1 << p_clrbits_le32_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le32_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_l3@
+p1 << p_setbits_le32_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le32_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr |= set1;
+- rr |= set2;
+- writel(rr, addr);
++ setbits_le32(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_l4@
+p1 << p_setbits_le32_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le32@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr);
+- rr |= set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le32_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr);
+- writel(rr | set, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le32_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl(addr) | set;
+- writel(rr, addr);
++ setbits_le32(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writel(readl(addr) | set, addr);
++ setbits_le32(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+ if (...)
+- rr |= set;
++ setbits_le32(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le32(addr, clear);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le32(addr, clear);
+ else
+- rr |= set;
++ setbits_le32(addr, set);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le32(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le32(addr, clear, set2);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le32(addr, clear, set);
++ else
++ setbits_le32(addr, set);
+- writel(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readl(addr) & ~mask);
+//- writel(rr, addr);
+//+ setmask_le32(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits32_relaxed.cocci b/scripts/coccinelle/misc/setbits32_relaxed.cocci
new file mode 100644
index 000000000000..edf8c39e939e
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits32_relaxed.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+- rr |= set;
+- writel_relaxed(rr, addr);
++ clrsetbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_relaxed_l4@
+p1 << p_clrsetbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear | set;
+- writel_relaxed(rr, addr);
++ clrsetbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le32_relaxed_l3@
+p1 << p_clrsetbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) & ~mask | set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p((readl_relaxed(addr) & ~mask) | set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set;
+- rr &= ~clear;
+- writel_relaxed(rr, addr);
++ setclrbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_relaxed_l4@
+p1 << p_setclrbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set & ~clear;
+- writel_relaxed(rr, addr);
++ setclrbits_le32_relaxed(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le32_relaxed_l3@
+p1 << p_setclrbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) | set & ~mask, addr);
++ setclrbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writel_relaxed@p((readl_relaxed(addr) | set) & ~mask, addr);
++ setclrbits_le32_relaxed(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+- writel_relaxed(rr, addr);
++ clrbits_le32_relaxed(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l3@
+p1 << p_clrbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- writel_relaxed(rr & ~mask, addr);
++ clrbits_le32_relaxed(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l2_a@
+p1 << p_clrbits_le32_relaxed_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr) & ~mask;
+- writel_relaxed(rr, addr);
++ clrbits_le32_relaxed(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le32_relaxed_l2_b@
+p1 << p_clrbits_le32_relaxed_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le32_relaxed_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writel_relaxed@p(readl_relaxed(addr) & ~mask, addr);
++ clrbits_le32_relaxed(addr, mask);
+
+@script:python depends on p_clrbits_le32_relaxed_oneliner@
+p1 << p_clrbits_le32_relaxed_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le32_relaxed_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_relaxed_l3@
+p1 << p_setbits_le32_relaxed_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le32_relaxed_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr |= set1;
+- rr |= set2;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le32_relaxed_l4@
+p1 << p_setbits_le32_relaxed_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le32_relaxed@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr);
+- rr |= set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le32_relaxed_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr);
+- writel_relaxed(rr | set, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le32_relaxed_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readl_relaxed(addr) | set;
+- writel_relaxed(rr, addr);
++ setbits_le32_relaxed(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writel_relaxed(readl_relaxed(addr) | set, addr);
++ setbits_le32_relaxed(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+ if (...)
+- rr |= set;
++ setbits_le32_relaxed(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le32_relaxed(addr, clear);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le32_relaxed(addr, clear);
+ else
+- rr |= set;
++ setbits_le32_relaxed(addr, set);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le32_relaxed(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le32_relaxed(addr, clear, set2);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readl_relaxed(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le32_relaxed(addr, clear, set);
++ else
++ setbits_le32_relaxed(addr, set);
+- writel_relaxed(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readl_relaxed(addr) & ~mask);
+//- writel_relaxed(rr, addr);
+//+ setmask_le32(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits64.cocci b/scripts/coccinelle/misc/setbits64.cocci
new file mode 100644
index 000000000000..00df21005b18
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits64.cocci
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+@p_clrsetbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+- rr |= set;
+- writeq(rr, addr);
++ clrsetbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le64_l4@
+p1 << p_clrsetbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear | set;
+- writeq(rr, addr);
++ clrsetbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrsetbits_le64_l3@
+p1 << p_clrsetbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_clrsetbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) & ~mask | set, addr);
++ clrsetbits_le64(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner@
+p1 << p_clrsetbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrsetbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p((readq(addr) & ~mask) | set, addr);
++ clrsetbits_le64(addr, mask, set);
+
+@script:python depends on p_clrsetbits_oneliner_b@
+p1 << p_clrsetbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+
+// setclrbits ==========================
+
+
+
+@p_setclrbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set;
+- rr &= ~clear;
+- writeq(rr, addr);
++ setclrbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le64_l4@
+p1 << p_setclrbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set & ~clear;
+- writeq(rr, addr);
++ setclrbits_le64(addr, clear, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setclrbits_le64_l3@
+p1 << p_setclrbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setclrbits_oneliner@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) | set & ~mask, addr);
++ setclrbits_le64(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner@
+p1 << p_setclrbits_oneliner.p;
+@@
+list.append(p1[0].file)
+
+@p_setclrbits_oneliner_b@
+expression addr;
+expression set;
+expression mask;
+position p;
+@@
+- writeq@p((readq(addr) | set) & ~mask, addr);
++ setclrbits_le64(addr, mask, set);
+
+@script:python depends on p_setclrbits_oneliner_b@
+p1 << p_setclrbits_oneliner_b.p;
+@@
+list.append(p1[0].file)
+
+
+// clr bits ===============================================
+
+@p_clrbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+- writeq(rr, addr);
++ clrbits_le64(addr, clear);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l3@
+p1 << p_clrbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_l2_a@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- writeq(rr & ~mask, addr);
++ clrbits_le64(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l2_a@
+p1 << p_clrbits_le64_l2_a.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_l2_b@
+local idexpression rr;
+expression addr;
+expression mask;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr) & ~mask;
+- writeq(rr, addr);
++ clrbits_le64(addr, mask);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_clrbits_le64_l2_b@
+p1 << p_clrbits_le64_l2_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_clrbits_le64_oneliner@
+expression addr;
+expression mask;
+position p;
+@@
+- writeq@p(readq(addr) & ~mask, addr);
++ clrbits_le64(addr, mask);
+
+@script:python depends on p_clrbits_le64_oneliner@
+p1 << p_clrbits_le64_oneliner.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+
+
+// set bits ======================================
+
+@p_setbits_le64_l3@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le64_l3@
+p1 << p_setbits_le64_l3.p;
+@@
+list.append(p1[0].file)
+
+
+@p_setbits_le64_l4@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr |= set1;
+- rr |= set2;
+- writeq(rr, addr);
++ setbits_le64(addr, set1 | set2);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_setbits_le64_l4@
+p1 << p_setbits_le64_l4.p;
+@@
+list.append(p1[0].file)
+
+
+
+
+
+@ppsetbits_le64@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr);
+- rr |= set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_le64_m2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr);
+- writeq(rr | set, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+@p_setbits_le64_l2@
+local idexpression rr;
+expression addr;
+expression set;
+expression e;
+@@
+
+- rr = readq(addr) | set;
+- writeq(rr, addr);
++ setbits_le64(addr, set);
+ ... when != rr
+? rr = e
+
+
+@p_setbits_oneliner@
+expression addr;
+expression set;
+@@
+- writeq(readq(addr) | set, addr);
++ setbits_le64(addr, set);
+
+
+
+
+
+// misc pattern ======================================
+
+
+@p_if_set_clr@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+ if (...)
+- rr |= set;
++ setbits_le64(addr, set);
+ else
+- rr &= ~clear;
++ clrbits_le64(addr, clear);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_set_clr@
+p1 << p_if_set_clr.p;
+@@
+//import subprocess
+list.append(p1[0].file)
+//file = p1[0].file
+//print("Add setbits header in %s" % file)
+//subprocess.call(["./add_header.py", file])
+
+
+@p_if_clr_set@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+ if (...)
+- rr &= ~clear;
++ clrbits_le64(addr, clear);
+ else
+- rr |= set;
++ setbits_le64(addr, set);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set@
+p1 << p_if_clr_set.p;
+@@
+list.append(p1[0].file)
+
+
+
+@p_if_clr_set_b@
+local idexpression rr;
+expression addr;
+expression set1;
+expression set2;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set1;
++ clrsetbits_le64(addr, clear, set1);
+ else
+- rr |= set2;
++ clrsetbits_le64(addr, clear, set2);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_b@
+p1 << p_if_clr_set_b.p;
+@@
+list.append(p1[0].file)
+
+
+@p_if_clr_set_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression clear;
+expression e;
+position p;
+@@
+
+- rr@p = readq(addr);
+- rr &= ~clear;
+ if (...)
+- rr |= set;
++ clrsetbits_le64(addr, clear, set);
++ else
++ setbits_le64(addr, set);
+- writeq(rr, addr);
+ ... when != rr
+? rr = e
+
+@script:python depends on p_if_clr_set_c@
+p1 << p_if_clr_set_c.p;
+@@
+list.append(p1[0].file)
+
+
+
+// to check decon_set_bits
+//@p_setmask_a@
+//local idexpression rr;
+//expression addr;
+//expression set;
+//expression mask;
+//@@
+//- rr = (set & mask) | (readq(addr) & ~mask);
+//- writeq(rr, addr);
+//+ setmask_le64(addr, set, mask);
+
+
+
+
+
+@initialize:python@
+@@
+list = []
+
+//@finalize:python depends on addr@
+@finalize:python@
+@@
+import subprocess
+for file in list:
+ print("Add setbits header in %s" % file)
+ subprocess.call(["./scripts/add_new_include_in_source.py", file])
+
diff --git a/scripts/coccinelle/misc/setbits_dev.cocci b/scripts/coccinelle/misc/setbits_dev.cocci
new file mode 100644
index 000000000000..859bd0526fcc
--- /dev/null
+++ b/scripts/coccinelle/misc/setbits_dev.cocci
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+// Confidence: High
+// Copyright: (c) 2018 Corentin LABBE
+
+virtual patch
+
+// ========================================================================
+// driver specific changes
+// to be removed after conversion
+
+
+// mtk_hdmi_phy_mask
+@p_setmask_b@
+local idexpression rr;
+expression addr;
+expression set;
+expression mask;
+@@
+- rr = readl(addr);
+- rr = (rr & ~mask) | (set & mask);
+- writel(rr, addr);
++ setmask_le32(addr, set, mask);
+
+@p_setmask_c@
+local idexpression rr;
+expression addr;
+expression set;
+expression mask;
+@@
+- rr = readl(addr);
+- rr = (set & mask) | (rr & ~mask);
+- writel(rr, addr);
++ setmask_le32(addr, set, mask);
+
+
+@p_net_meson_clean@
+@@
+- meson8b_dwmac_mask_bits(...) {
+- ...
+- }
+
+@p_net_meson@
+expression dwmac;
+expression addr;
+expression mask;
+expression value;
+@@
+
+- meson8b_dwmac_mask_bits(dwmac, addr, mask, value);
++ clrsetbits_le32(dwmac->regs + addr, mask, value);
+
+// meson DRM
+@p_meson_drm_writel@
+expression addr;
+expression set;
+expression mask;
+@@
+- writel_bits_relaxed(mask, set, addr);
++ clrsetbits_le32_relaxed(addr, mask, set);
+
+@p_mtu3_setbits@
+expression base;
+expression offset;
+expression value;
+@@
+
+- mtu3_setbits(base, offset, value);
++ setbits_le32(base + offset, value);
+
+@p_mtu3_clrbits@
+expression base;
+expression offset;
+expression mask;
+@@
+
+- mtu3_clrbits(base, offset, mask);
++ clrbits_le32(base + offset, mask);
+
+//
+@p_fimc_clean_set@
+@@
+- static void fimc_set_bits(...) {
+- ...
+- }
+
+@p_fimc_clean_clrt@
+@@
+- static void fimc_clear_bits(...) {
+- ...
+- }
+
+@p_fimc_setbits@
+expression fimc;
+expression offset;
+expression value;
+@@
+
+- fimc_set_bits(fimc, offset, value);
++ setbits_le32(fimc->regs + offset, value);
+
+@p_fimc_clrbits@
+expression fimc;
+expression offset;
+expression mask;
+@@
+
+- fimc_clear_bits(fimc, offset, mask);
++ clrbits_le32(fimc->regs + offset, mask);
+
+//
+@p_sif_clean_clr@
+@@
+- static void sif_clr_bit(...) {
+- ...
+- }
+
+@p_sif_clean_set@
+@@
+- static void sif_set_bit(...) {
+- ...
+- }
+
+@p_sif_setbits@
+expression sif;
+expression offset;
+expression value;
+@@
+
+- sif_set_bit(sif, offset, value);
++ setbits_le32(sif->regs + offset, value);
+
+@p_sif_clrbits@
+expression sif;
+expression offset;
+expression mask;
+@@
+
+- sif_clr_bit(sif, offset, mask);
++ clrbits_le32(sif->regs + offset, mask);
+
+// mediatek
+@p_mtk_clean_clr@
+@@
+- static void mtk_cec_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_clean_set@
+@@
+- static void mtk_cec_set_bits(...) {
+- ...
+- }
+
+@p_mtk_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_cec_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_cec_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+// mediatek HDMI
+@p_mtk_hdmi_clean_set@
+@@
+- static void mtk_hdmi_set_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_clean_clr@
+@@
+- static void mtk_hdmi_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_hdmi_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_hdmi_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_hdmi_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+// mediatek HDMI
+@p_mtk_hdmi_phy_clean_set@
+@@
+- static void mtk_hdmi_phy_set_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_phy_clean_clr@
+@@
+- static void mtk_hdmi_phy_clear_bits(...) {
+- ...
+- }
+
+@p_mtk_hdmi_phy_setbits@
+expression mtk;
+expression offset;
+expression value;
+@@
+
+- mtk_hdmi_phy_set_bits(mtk, offset, value);
++ setbits_le32(mtk->regs + offset, value);
+
+@p_mtk_hdmi_phy_clrbits@
+expression mtk;
+expression offset;
+expression mask;
+@@
+
+- mtk_hdmi_phy_clear_bits(mtk, offset, mask);
++ clrbits_le32(mtk->regs + offset, mask);
+
+
+
--
2.18.1
^ permalink raw reply related
* [PATCH v3 5/7] net: ethernet: stmmac: dwmac-sun8i: use xxxsetbits_le32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch convert dwmac-sun8i driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 62 +++++--------------
1 file changed, 16 insertions(+), 46 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index f9a61f90cfbc..74067a59af50 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -28,6 +28,7 @@
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/stmmac.h>
+#include <linux/setbits.h>
#include "stmmac.h"
#include "stmmac_platform.h"
@@ -342,50 +343,30 @@ static void sun8i_dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan)
static void sun8i_dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+ EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_enable_dma_transmission(void __iomem *ioaddr)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v |= EMAC_TX_DMA_START;
- v |= EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ setbits_le32(ioaddr + EMAC_TX_CTL1,
+ EMAC_TX_DMA_START | EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_TX_CTL1);
- v &= ~EMAC_TX_DMA_EN;
- writel(v, ioaddr + EMAC_TX_CTL1);
+ clrbits_le32(ioaddr + EMAC_TX_CTL1, EMAC_TX_DMA_EN);
}
static void sun8i_dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v |= EMAC_RX_DMA_START;
- v |= EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ setbits_le32(ioaddr + EMAC_RX_CTL1,
+ EMAC_RX_DMA_START | EMAC_RX_DMA_EN);
}
static void sun8i_dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan)
{
- u32 v;
-
- v = readl(ioaddr + EMAC_RX_CTL1);
- v &= ~EMAC_RX_DMA_EN;
- writel(v, ioaddr + EMAC_RX_CTL1);
+ clrbits_le32(ioaddr + EMAC_RX_CTL1, EMAC_RX_DMA_EN);
}
static int sun8i_dwmac_dma_interrupt(void __iomem *ioaddr,
@@ -578,7 +559,6 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
unsigned int reg_n)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
if (!addr) {
writel(0, ioaddr + EMAC_MACADDR_HI(reg_n));
@@ -588,9 +568,8 @@ static void sun8i_dwmac_set_umac_addr(struct mac_device_info *hw,
stmmac_set_mac_addr(ioaddr, addr, EMAC_MACADDR_HI(reg_n),
EMAC_MACADDR_LO(reg_n));
if (reg_n > 0) {
- v = readl(ioaddr + EMAC_MACADDR_HI(reg_n));
- v |= MAC_ADDR_TYPE_DST;
- writel(v, ioaddr + EMAC_MACADDR_HI(reg_n));
+ setbits_le32(ioaddr + EMAC_MACADDR_HI(reg_n),
+ MAC_ADDR_TYPE_DST);
}
}
@@ -608,11 +587,8 @@ static void sun8i_dwmac_get_umac_addr(struct mac_device_info *hw,
static int sun8i_dwmac_rx_ipc_enable(struct mac_device_info *hw)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
- v |= EMAC_RX_DO_CRC;
- writel(v, ioaddr + EMAC_RX_CTL0);
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_DO_CRC);
return 1;
}
@@ -662,21 +638,15 @@ static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
unsigned int pause_time, u32 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
- u32 v;
- v = readl(ioaddr + EMAC_RX_CTL0);
if (fc == FLOW_AUTO)
- v |= EMAC_RX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
else
- v &= ~EMAC_RX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_RX_CTL0);
-
- v = readl(ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_RX_CTL0, EMAC_RX_FLOW_CTL_EN);
if (fc == FLOW_AUTO)
- v |= EMAC_TX_FLOW_CTL_EN;
+ setbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
else
- v &= ~EMAC_TX_FLOW_CTL_EN;
- writel(v, ioaddr + EMAC_TX_FLOW_CTL);
+ clrbits_le32(ioaddr + EMAC_TX_FLOW_CTL, EMAC_TX_FLOW_CTL_EN);
}
static int sun8i_dwmac_reset(struct stmmac_priv *priv)
--
2.18.1
^ permalink raw reply related
* [PATCH v3 6/7] drm: meson: use xxxsetbits_le32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch convert meson DRM driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_crtc.c | 14 +++---
drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++++++------
drivers/gpu/drm/meson/meson_plane.c | 13 ++---
drivers/gpu/drm/meson/meson_registers.h | 3 --
drivers/gpu/drm/meson/meson_venc.c | 13 ++---
drivers/gpu/drm/meson/meson_venc_cvbs.c | 4 +-
drivers/gpu/drm/meson/meson_viu.c | 65 +++++++++++++------------
drivers/gpu/drm/meson/meson_vpp.c | 22 ++++-----
8 files changed, 86 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index 05520202c967..98f17ddd6b00 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -98,8 +99,8 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc,
writel(crtc_state->mode.hdisplay,
priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE);
priv->viu.osd1_enabled = true;
}
@@ -114,8 +115,8 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc,
priv->viu.osd1_commit = false;
/* Disable VPP Postblend */
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, 0);
if (crtc->state->event && !crtc->state->active) {
spin_lock_irq(&crtc->dev->event_lock);
@@ -199,8 +200,9 @@ void meson_crtc_irq(struct meson_drm *priv)
MESON_CANVAS_BLKMODE_LINEAR);
/* Enable OSD1 */
- writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_OSD1_POSTBLEND,
+ VPP_OSD1_POSTBLEND);
priv->viu.osd1_commit = false;
}
diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
index df7247cd93f9..99a136209e15 100644
--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
@@ -24,6 +24,7 @@
#include <linux/reset.h>
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include <drm/drm_edid.h>
@@ -427,10 +428,10 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Temporary Disable HDMI video stream to HDMI-TX */
- writel_bits_relaxed(0x3, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
- writel_bits_relaxed(0xf << 8, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING), 0x3,
+ 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, 0);
/* Re-Enable VENC video stream */
if (priv->venc.hdmi_use_enci)
@@ -439,16 +440,16 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Push back HDMI clock settings */
- writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8),
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0xf << 8, wr_clk & (0xf << 8));
/* Enable and Select HDMI video source for HDMI-TX */
if (priv->venc.hdmi_use_enci)
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCI);
else
- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING),
+ 0x3, MESON_VENC_SOURCE_ENCP);
return 0;
}
@@ -632,8 +633,8 @@ static void meson_venc_hdmi_encoder_disable(struct drm_encoder *encoder)
DRM_DEBUG_DRIVER("\n");
- writel_bits_relaxed(0x3, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING), 0x3,
+ 0);
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
@@ -857,10 +858,10 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
reset_control_reset(meson_dw_hdmi->hdmitx_phy);
/* Enable APB3 fail on error */
- writel_bits_relaxed(BIT(15), BIT(15),
- meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG);
- writel_bits_relaxed(BIT(15), BIT(15),
- meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG);
+ clrsetbits_le32_relaxed(meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG,
+ BIT(15), BIT(15));
+ clrsetbits_le32_relaxed(meson_dw_hdmi->hdmitx + HDMITX_DWC_CTRL_REG,
+ BIT(15), BIT(15));
/* Bring out of reset */
dw_hdmi_top_write(meson_dw_hdmi, HDMITX_TOP_SW_RESET, 0);
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 12c80dfcff59..7377aefcbb2a 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -25,6 +25,7 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/platform_device.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -115,15 +116,15 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
switch (fb->format->format) {
case DRM_FORMAT_XRGB8888:
/* For XRGB, replace the pixel's alpha by 0xFF */
- writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN,
- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_CTRL_STAT2),
+ OSD_REPLACE_EN, OSD_REPLACE_EN);
priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
OSD_COLOR_MATRIX_32_ARGB;
break;
case DRM_FORMAT_ARGB8888:
/* For ARGB, use the pixel's alpha */
- writel_bits_relaxed(OSD_REPLACE_EN, 0,
- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_CTRL_STAT2),
+ OSD_REPLACE_EN, 0);
priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
OSD_COLOR_MATRIX_32_ARGB;
break;
@@ -174,8 +175,8 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
struct meson_drm *priv = meson_plane->priv;
/* Disable OSD1 */
- writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_OSD1_POSTBLEND, 0);
}
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index bca87143e548..03ff452655f2 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -19,9 +19,6 @@
/* Shift all registers by 2 */
#define _REG(reg) ((reg) << 2)
-#define writel_bits_relaxed(mask, val, addr) \
- writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
-
/* vpp2 */
#define VPP2_DUMMY_DATA 0x1900
#define VPP2_LINE_IN_LENGTH 0x1901
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index 514245e69b38..eeb59a51f316 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include "meson_drv.h"
#include "meson_venc.h"
@@ -913,8 +914,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
hsync_pixels_venc *= 2;
/* Disable VDACs */
- writel_bits_relaxed(0xff, 0xff,
- priv->io_base + _REG(VENC_VDAC_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VENC_VDAC_SETTING), 0xff,
+ 0xff);
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
@@ -1250,8 +1251,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
/* Set DE signal’s polarity is active high */
- writel_bits_relaxed(BIT(14), BIT(14),
- priv->io_base + _REG(ENCP_VIDEO_MODE));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ENCP_VIDEO_MODE),
+ BIT(14), BIT(14));
/* Program DE timing */
de_h_begin = modulo(readl_relaxed(priv->io_base +
@@ -1549,8 +1550,8 @@ void meson_venc_init(struct meson_drm *priv)
regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
/* Disable HDMI */
- writel_bits_relaxed(0x3, 0,
- priv->io_base + _REG(VPU_HDMI_SETTING));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING), 0x3,
+ 0);
/* Disable all encoders */
writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c
index f7945bae3b4a..6fff94d69e85 100644
--- a/drivers/gpu/drm/meson/meson_venc_cvbs.c
+++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c
@@ -24,6 +24,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_graph.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include <drm/drm_edid.h>
@@ -177,7 +178,8 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder)
struct meson_drm *priv = meson_venc_cvbs->priv;
/* VDAC0 source is not from ATV */
- writel_bits_relaxed(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VENC_VDAC_DACSEL0),
+ BIT(5), 0);
if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu"))
regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1);
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index 6bcfa527c180..952b74e874af 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include "meson_drv.h"
#include "meson_viu.h"
@@ -131,16 +132,16 @@ void meson_viu_set_osd_matrix(struct meson_drm *priv,
writel(m[20] & 0xfff,
priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
- writel_bits_relaxed(3 << 30, m[21] << 30,
- priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
- writel_bits_relaxed(7 << 16, m[22] << 16,
- priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42),
+ 3 << 30, m[21] << 30);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42),
+ 7 << 16, m[22] << 16);
/* 23 reserved for clipping control */
- writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
- priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
- writel_bits_relaxed(BIT(1), 0,
- priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL),
+ BIT(0), csc_on ? BIT(0) : 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL),
+ BIT(1), 0);
} else if (m_select == VIU_MATRIX_OSD_EOTF) {
int i;
@@ -150,10 +151,10 @@ void meson_viu_set_osd_matrix(struct meson_drm *priv,
(m[i * 2 + 1] & 0x1fff), priv->io_base +
_REG(VIU_OSD1_EOTF_CTL + i + 1));
- writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0,
- priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
- writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0,
- priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_EOTF_CTL),
+ BIT(30), csc_on ? BIT(30) : 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_EOTF_CTL),
+ BIT(31), csc_on ? BIT(31) : 0);
}
}
@@ -203,11 +204,11 @@ void meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel,
priv->io_base + _REG(data_port));
if (csc_on)
- writel_bits_relaxed(0x7 << 29, 7 << 29,
- priv->io_base + _REG(ctrl_port));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ctrl_port),
+ 0x7 << 29, 7 << 29);
else
- writel_bits_relaxed(0x7 << 29, 0,
- priv->io_base + _REG(ctrl_port));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ctrl_port),
+ 0x7 << 29, 0);
} else if (lut_sel == VIU_LUT_OSD_EOTF) {
writel(0, priv->io_base + _REG(addr_port));
@@ -230,14 +231,14 @@ void meson_viu_set_osd_lut(struct meson_drm *priv, enum viu_lut_sel_e lut_sel,
priv->io_base + _REG(data_port));
if (csc_on)
- writel_bits_relaxed(7 << 27, 7 << 27,
- priv->io_base + _REG(ctrl_port));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ctrl_port),
+ 7 << 27, 7 << 27);
else
- writel_bits_relaxed(7 << 27, 0,
- priv->io_base + _REG(ctrl_port));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ctrl_port),
+ 7 << 27, 0);
- writel_bits_relaxed(BIT(31), BIT(31),
- priv->io_base + _REG(ctrl_port));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(ctrl_port),
+ BIT(31), BIT(31));
}
}
@@ -301,10 +302,10 @@ void meson_viu_init(struct meson_drm *priv)
uint32_t reg;
/* Disable OSDs */
- writel_bits_relaxed(BIT(0) | BIT(21), 0,
- priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
- writel_bits_relaxed(BIT(0) | BIT(21), 0,
- priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_CTRL_STAT),
+ BIT(0) | BIT(21), 0);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD2_CTRL_STAT),
+ BIT(0) | BIT(21), 0);
/* On GXL/GXM, Use the 10bit HDR conversion matrix */
if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") ||
@@ -322,12 +323,12 @@ void meson_viu_init(struct meson_drm *priv)
writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
/* Set OSD alpha replace value */
- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
- 0xff << OSD_REPLACE_SHIFT,
- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT,
- 0xff << OSD_REPLACE_SHIFT,
- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD1_CTRL_STAT2),
+ 0xff << OSD_REPLACE_SHIFT,
+ 0xff << OSD_REPLACE_SHIFT);
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_OSD2_CTRL_STAT2),
+ 0xff << OSD_REPLACE_SHIFT,
+ 0xff << OSD_REPLACE_SHIFT);
priv->viu.osd1_enabled = false;
priv->viu.osd1_commit = false;
diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
index 27356f81a0ab..f36254485486 100644
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/setbits.h>
#include <drm/drmP.h>
#include "meson_drv.h"
#include "meson_vpp.h"
@@ -128,30 +129,29 @@ void meson_vpp_init(struct meson_drm *priv)
if (meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu"))
writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu")) {
- writel_bits_relaxed(0xff << 16, 0xff << 16,
- priv->io_base + _REG(VIU_MISC_CTRL1));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VIU_MISC_CTRL1),
+ 0xff << 16, 0xff << 16);
writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));
writel_relaxed(0x1020080,
priv->io_base + _REG(VPP_DUMMY_DATA1));
}
/* Initialize vpu fifo control registers */
- writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |
- 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE));
+ setbits_le32_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE), 0x77f);
writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));
/* Turn off preblend */
- writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_PREBLEND_ENABLE, 0);
/* Turn off POSTBLEND */
- writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_POSTBLEND_ENABLE, 0);
/* Force all planes off */
- writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND |
- VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND, 0,
- priv->io_base + _REG(VPP_MISC));
+ clrsetbits_le32_relaxed(priv->io_base + _REG(VPP_MISC),
+ VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | VPP_VD1_POSTBLEND | VPP_VD2_POSTBLEND,
+ 0);
/* Disable Scalers */
writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
--
2.18.1
^ permalink raw reply related
* [PATCH v3 7/7] net: stmmac: dwmac-meson8b: use xxxsetbits_le32
From: Corentin Labbe @ 2018-10-24 7:35 UTC (permalink / raw)
To: Gilles.Muller, Julia.Lawall, agust, airlied, alexandre.torgue,
alistair, benh, carlo, davem, galak, joabreu, khilman,
matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, Corentin Labbe, linux-amlogic, linuxppc-dev,
cocci, linux-arm-kernel
In-Reply-To: <1540366553-18541-1-git-send-email-clabbe@baylibre.com>
This patch convert meson stmmac glue driver to use all xxxsetbits_le32 functions.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 56 ++++++++-----------
1 file changed, 22 insertions(+), 34 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
index c5979569fd60..abcf65588576 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c
@@ -23,6 +23,7 @@
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
#include <linux/stmmac.h>
+#include <linux/setbits.h>
#include "stmmac_platform.h"
@@ -75,18 +76,6 @@ struct meson8b_dwmac_clk_configs {
struct clk_gate rgmii_tx_en;
};
-static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
- u32 mask, u32 value)
-{
- u32 data;
-
- data = readl(dwmac->regs + reg);
- data &= ~mask;
- data |= (value & mask);
-
- writel(data, dwmac->regs + reg);
-}
-
static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
const char *name_suffix,
const char **parent_names,
@@ -192,14 +181,13 @@ static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE,
- PRG_ETH0_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ PRG_ETH0_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_RGMII_MODE, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_RGMII_MODE,
+ 0);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -218,15 +206,15 @@ static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* enable RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RGMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RGMII_MODE);
break;
case PHY_INTERFACE_MODE_RMII:
/* disable RGMII mode -> enables RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_EXT_PHY_MODE_MASK,
- PRG_ETH0_EXT_RMII_MODE);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_EXT_PHY_MODE_MASK,
+ PRG_ETH0_EXT_RMII_MODE);
break;
default:
dev_err(dwmac->dev, "fail to set phy-mode %s\n",
@@ -255,11 +243,11 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* only relevant for RMII mode -> disable in RGMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK, 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK, 0);
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
- tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK,
+ tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
/* Configure the 125MHz RGMII TX clock, the IP block changes
* the output automatically (= without us having to configure
@@ -287,13 +275,13 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
case PHY_INTERFACE_MODE_RMII:
/* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
- PRG_ETH0_INVERTED_RMII_CLK,
- PRG_ETH0_INVERTED_RMII_CLK);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0,
+ PRG_ETH0_INVERTED_RMII_CLK,
+ PRG_ETH0_INVERTED_RMII_CLK);
/* TX clock delay cannot be configured in RMII mode */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
- 0);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_TXDLY_MASK,
+ 0);
break;
@@ -304,8 +292,8 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
}
/* enable TX_CLK and PHY_REF_CLK generator */
- meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
- PRG_ETH0_TX_AND_PHY_REF_CLK);
+ clrsetbits_le32(dwmac->regs + PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
+ PRG_ETH0_TX_AND_PHY_REF_CLK);
return 0;
}
--
2.18.1
^ permalink raw reply related
* Re: [PATCH v3 4/7] ata: ahci_sunxi: use xxxsetbitsi_le32 functions
From: Sergei Shtylyov @ 2018-10-24 7:57 UTC (permalink / raw)
To: Corentin Labbe, Gilles.Muller, Julia.Lawall, agust, airlied,
alexandre.torgue, alistair, benh, carlo, davem, galak, joabreu,
khilman, matthias.bgg, maxime.ripard, michal.lkml, mpe, mporter,
narmstrong, nicolas.palix, oss, paulus, peppe.cavallaro, tj, vitb,
wens
Cc: netdev, linux-kernel, dri-devel, linux-ide, linux-sunxi,
linux-mediatek, linux-amlogic, linuxppc-dev, cocci,
linux-arm-kernel
In-Reply-To: <1540366553-18541-5-git-send-email-clabbe@baylibre.com>
Hello!
Typo in the subject: s/xxxsetbitsi/xxxsetbits/.
On 24.10.2018 10:35, Corentin Labbe wrote:
> This patch converts ahci_sunxi to use xxxsetbits_le32 functions
>
> Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH 1/4] treewide: remove unused address argument from pte_alloc functions (v2)
From: Peter Zijlstra @ 2018-10-24 8:37 UTC (permalink / raw)
To: Joel Fernandes (Google)
Cc: linux-mips, Rich Felker, linux-ia64, linux-sh, Catalin Marinas,
Dave Hansen, Will Deacon, Michal Hocko, linux-mm, lokeshgidra,
sparclinux, linux-riscv, elfring, Jonas Bonn, kvmarm, dancol,
Yoshinori Sato, linux-xtensa, linux-hexagon, Helge Deller,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), hughd,
James E.J. Bottomley, kasan-dev, anton.ivanov, Ingo Molnar,
Geert Uytterhoeven, Andrey Ryabinin, linux-snps-arc, kernel-team,
Sam Creasey, Fenghua Yu, linux-s390, Jeff Dike, linux-um,
Stefan Kristiansson, Julia Lawall, linux-m68k, Borislav Petkov,
Andy Lutomirski, nios2-dev, Kirill A . Shutemov, Stafford Horne,
Guan Xuetao, Chris Zankel, Tony Luck, Richard Weinberger,
linux-parisc, Max Filippov, pantin, linux-kernel, minchan,
Thomas Gleixner, linux-alpha, Ley Foon Tan, akpm, linuxppc-dev,
David S. Miller
In-Reply-To: <20181013013200.206928-2-joel@joelfernandes.org>
On Fri, Oct 12, 2018 at 06:31:57PM -0700, Joel Fernandes (Google) wrote:
> This series speeds up mremap(2) syscall by copying page tables at the
> PMD level even for non-THP systems. There is concern that the extra
> 'address' argument that mremap passes to pte_alloc may do something
> subtle architecture related in the future that may make the scheme not
> work. Also we find that there is no point in passing the 'address' to
> pte_alloc since its unused. So this patch therefore removes this
> argument tree-wide resulting in a nice negative diff as well. Also
> ensuring along the way that the enabled architectures do not do anything
> funky with 'address' argument that goes unnoticed by the optimization.
Did you happen to look at the history of where that address argument
came from? -- just being curious here. ISTR something vague about
architectures having different paging structure for different memory
ranges.
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox