* [PATCH 5/5] selftests/powerpc/cache_shape: Fix out-of-tree build
From: Michael Ellerman @ 2018-10-29 11:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: joel
In-Reply-To: <20181029112353.15805-1-mpe@ellerman.id.au>
Use TEST_GEN_PROGS and don't redefine all, this makes the out-of-tree
build work. We need to move the extra dependencies below the include
of lib.mk, because it adds the $(OUTPUT) prefix if it's defined.
We can also drop the clean rule, lib.mk does it for us.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/cache_shape/Makefile | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tools/testing/selftests/powerpc/cache_shape/Makefile b/tools/testing/selftests/powerpc/cache_shape/Makefile
index ede4d3dae750..689f6c8ebcd8 100644
--- a/tools/testing/selftests/powerpc/cache_shape/Makefile
+++ b/tools/testing/selftests/powerpc/cache_shape/Makefile
@@ -1,12 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
-TEST_PROGS := cache_shape
-
-all: $(TEST_PROGS)
-
-$(TEST_PROGS): ../harness.c ../utils.c
+TEST_GEN_PROGS := cache_shape
top_srcdir = ../../../../..
include ../../lib.mk
-clean:
- rm -f $(TEST_PROGS) *.o
+$(TEST_GEN_PROGS): ../harness.c ../utils.c
--
2.17.2
^ permalink raw reply related
* [PATCH 4/5] selftests/powerpc/switch_endian: Fix out-of-tree build
From: Michael Ellerman @ 2018-10-29 11:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: joel
In-Reply-To: <20181029112353.15805-1-mpe@ellerman.id.au>
For the out-of-tree build to work we need to tell switch_endian_test
to look for check-reversed.S in $(OUTPUT).
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/switch_endian/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/testing/selftests/powerpc/switch_endian/Makefile b/tools/testing/selftests/powerpc/switch_endian/Makefile
index fcd2dcb8972b..bdc081afedb0 100644
--- a/tools/testing/selftests/powerpc/switch_endian/Makefile
+++ b/tools/testing/selftests/powerpc/switch_endian/Makefile
@@ -8,6 +8,7 @@ EXTRA_CLEAN = $(OUTPUT)/*.o $(OUTPUT)/check-reversed.S
top_srcdir = ../../../../..
include ../../lib.mk
+$(OUTPUT)/switch_endian_test: ASFLAGS += -I $(OUTPUT)
$(OUTPUT)/switch_endian_test: $(OUTPUT)/check-reversed.S
$(OUTPUT)/check-reversed.o: $(OUTPUT)/check.o
--
2.17.2
^ permalink raw reply related
* [PATCH 3/5] selftests/powerpc/pmu: Link ebb tests with -no-pie
From: Michael Ellerman @ 2018-10-29 11:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: joel
In-Reply-To: <20181029112353.15805-1-mpe@ellerman.id.au>
From: Joel Stanley <joel@jms.id.au>
When running the ebb tests after building on a ppc64le Ubuntu machine:
$ pmu/ebb/reg_access_test: error while loading shared libraries:
R_PPC64_ADDR16_HI reloc at 0x000000013a965130 for symbol `' out of
range
This is because the Ubuntu toolchain builds has PIE enabled by default.
Change it to be always off instead.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/pmu/ebb/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/Makefile b/tools/testing/selftests/powerpc/pmu/ebb/Makefile
index bd5dfa509272..23f4caf48ffc 100644
--- a/tools/testing/selftests/powerpc/pmu/ebb/Makefile
+++ b/tools/testing/selftests/powerpc/pmu/ebb/Makefile
@@ -5,6 +5,9 @@ noarg:
# The EBB handler is 64-bit code and everything links against it
CFLAGS += -m64
+# Toolchains may build PIE by default which breaks the assembly
+LDFLAGS += -no-pie
+
TEST_GEN_PROGS := reg_access_test event_attributes_test cycles_test \
cycles_with_freeze_test pmc56_overflow_test \
ebb_vs_cpu_event_test cpu_event_vs_ebb_test \
--
2.17.2
^ permalink raw reply related
* [PATCH 2/5] selftests/powerpc/signal: Fix out-of-tree build
From: Michael Ellerman @ 2018-10-29 11:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: joel
In-Reply-To: <20181029112353.15805-1-mpe@ellerman.id.au>
From: Joel Stanley <joel@jms.id.au>
We should use TEST_GEN_PROGS, not TEST_PROGS. That tells the selftests
makefile (lib.mk) that those tests are generated (built), and so it
adds the $(OUTPUT) prefix for us, making the out-of-tree build work
correctly.
It also means we don't need our own clean rule, lib.mk does it.
We also have to update the signal_tm rule to use $(OUTPUT).
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/signal/Makefile | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/tools/testing/selftests/powerpc/signal/Makefile b/tools/testing/selftests/powerpc/signal/Makefile
index 1fca25c6ace0..209a958dca12 100644
--- a/tools/testing/selftests/powerpc/signal/Makefile
+++ b/tools/testing/selftests/powerpc/signal/Makefile
@@ -1,15 +1,10 @@
# SPDX-License-Identifier: GPL-2.0
-TEST_PROGS := signal signal_tm
-
-all: $(TEST_PROGS)
-
-$(TEST_PROGS): ../harness.c ../utils.c signal.S
+TEST_GEN_PROGS := signal signal_tm
CFLAGS += -maltivec
-signal_tm: CFLAGS += -mhtm
+$(OUTPUT)/signal_tm: CFLAGS += -mhtm
top_srcdir = ../../../../..
include ../../lib.mk
-clean:
- rm -f $(TEST_PROGS) *.o
+$(TEST_GEN_PROGS): ../harness.c ../utils.c signal.S
--
2.17.2
^ permalink raw reply related
* [PATCH 1/5] selftests/powerpc/ptrace: Fix out-of-tree build
From: Michael Ellerman @ 2018-10-29 11:23 UTC (permalink / raw)
To: linuxppc-dev; +Cc: joel
From: Joel Stanley <joel@jms.id.au>
We should use TEST_GEN_PROGS, not TEST_PROGS. That tells the selftests
makefile (lib.mk) that those tests are generated (built), and so it
adds the $(OUTPUT) prefix for us, making the out-of-tree build work
correctly.
It also means we don't need our own clean rule, lib.mk does it.
We also have to update the ptrace-pkey and core-pkey rules to use
$(OUTPUT).
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/ptrace/Makefile | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 9b35ca8e8f13..8d3f006c98cc 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-TEST_PROGS := ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
+TEST_GEN_PROGS := ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx \
ptrace-tm-spd-vsx ptrace-tm-spr ptrace-hwbreak ptrace-pkey core-pkey \
perf-hwbreak ptrace-syscall
@@ -7,14 +7,9 @@ TEST_PROGS := ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
top_srcdir = ../../../../..
include ../../lib.mk
-all: $(TEST_PROGS)
-
CFLAGS += -m64 -I../../../../../usr/include -I../tm -mhtm -fno-pie
-ptrace-pkey core-pkey: child.h
-ptrace-pkey core-pkey: LDLIBS += -pthread
-
-$(TEST_PROGS): ../harness.c ../utils.c ../lib/reg.S ptrace.h
+$(OUTPUT)/ptrace-pkey $(OUTPUT)/core-pkey: child.h
+$(OUTPUT)/ptrace-pkey $(OUTPUT)/core-pkey: LDLIBS += -pthread
-clean:
- rm -f $(TEST_PROGS) *.o
+$(TEST_GEN_PROGS): ../harness.c ../utils.c ../lib/reg.S ptrace.h
--
2.17.2
^ permalink raw reply related
* Re: [PATCH 0/8] add generic builtin command line
From: Russell King - ARM Linux @ 2018-10-29 10:44 UTC (permalink / raw)
To: Will Deacon
Cc: linux-mips, linux-efi, Ruslan Bilovol, Paul Mackerras,
H. Peter Anvin, Daniel Walker, Frank Rowand, x86, Ingo Molnar,
Catalin Marinas, James Hogan, Daniel Walker, devicetree,
Rob Herring, Borislav Petkov, Thomas Gleixner, Andrii Bordunov,
Ard Biesheuvel, linux-kernel, Ralf Baechle, Paul Burton,
Maksym Kokhan, Andrew Morton, linuxppc-dev
In-Reply-To: <20181029102914.GA14127@arm.com>
On Mon, Oct 29, 2018 at 10:29:15AM +0000, Will Deacon wrote:
> On Wed, Oct 24, 2018 at 10:07:32AM +0100, Russell King - ARM Linux wrote:
> > On Wed, Oct 24, 2018 at 11:57:44AM +0300, Maksym Kokhan wrote:
> > > Do you mean, that you haven't seen patch for ARM, which I sent on
> > > September 27 along with cover and patch 1? It is strange, because
> > > you was the one from recipients. If so, you can see this patch here:
> > > https://lore.kernel.org/patchwork/patch/992779/
> >
> > It seems that I have received patch 5, _but_ it's not threaded with
> > the cover message and patch 1. With 50k messages in my inbox, and 3k
> > messages since you sent the series, it's virtually impossible to find
> > it (I only found it by looking at my mail server logs from September
> > to find the subject, and then searching my mailbox for that subject.)
> >
> > This is unnecessarily difficult.
>
> This comes up surprisingly often, and I think part of the issue is that
> different maintainers have different preferences. I also prefer to receive
> the entire series and cover-letter, but I've seen people object to being
> CC'd on the whole series as well (how they manage to review things in
> isolation is another question...!)
This series has the odd situation where patch 1 is threaded to the
cover letter, but nothing else is - that makes it inconsistent.
Where I've seen people disagree with threading is when sending
follow-up series - whether that should be threaded to the previous
series or not - some people want it others hate it.
However, I haven't seen any disagreement is about having the patches
threaded to the cover.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up
^ permalink raw reply
* Re: [PATCH 0/8] add generic builtin command line
From: Will Deacon @ 2018-10-29 10:29 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: linux-mips, linux-efi, Ruslan Bilovol, Paul Mackerras,
H. Peter Anvin, Daniel Walker, Frank Rowand, x86, Ingo Molnar,
Catalin Marinas, James Hogan, Daniel Walker, devicetree,
Rob Herring, Borislav Petkov, Thomas Gleixner, Andrii Bordunov,
Ard Biesheuvel, linux-kernel, Ralf Baechle, Paul Burton,
Maksym Kokhan, Andrew Morton, linuxppc-dev
In-Reply-To: <20181024090732.GS30658@n2100.armlinux.org.uk>
On Wed, Oct 24, 2018 at 10:07:32AM +0100, Russell King - ARM Linux wrote:
> On Wed, Oct 24, 2018 at 11:57:44AM +0300, Maksym Kokhan wrote:
> > Do you mean, that you haven't seen patch for ARM, which I sent on
> > September 27 along with cover and patch 1? It is strange, because
> > you was the one from recipients. If so, you can see this patch here:
> > https://lore.kernel.org/patchwork/patch/992779/
>
> It seems that I have received patch 5, _but_ it's not threaded with
> the cover message and patch 1. With 50k messages in my inbox, and 3k
> messages since you sent the series, it's virtually impossible to find
> it (I only found it by looking at my mail server logs from September
> to find the subject, and then searching my mailbox for that subject.)
>
> This is unnecessarily difficult.
This comes up surprisingly often, and I think part of the issue is that
different maintainers have different preferences. I also prefer to receive
the entire series and cover-letter, but I've seen people object to being
CC'd on the whole series as well (how they manage to review things in
isolation is another question...!)
I wonder if we could have an entry in MAINTAINERS for this sort of
preference?
Maksym: in the short term, please just stick me and Russell on CC for the
entire thing.
Will
^ permalink raw reply
* arch/powerpc/kvm/trace.h:9:0: error: "TRACE_INCLUDE_PATH" redefined
From: Christian Zigotzky @ 2018-10-29 10:22 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <99266ac6-640c-b2a9-eef3-4e89ee1e0ad5@xenosoft.de>
Hello,
The latest Git kernel doesn't compile currently because of the following
error:
CC arch/powerpc/kvm/powerpc.o
In file included from arch/powerpc/kvm/powerpc.c:51:0:
arch/powerpc/kvm/trace.h:9:0: error: "TRACE_INCLUDE_PATH" redefined
[-Werror]
#define TRACE_INCLUDE_PATH .
^
In file included from arch/powerpc/kvm/../mm/mmu_decl.h:25:0,
from arch/powerpc/kvm/powerpc.c:48:
./arch/powerpc/include/asm/trace.h:224:0: note: this is the location of
the previous definition
#define TRACE_INCLUDE_PATH asm
^
cc1: all warnings being treated as errors
scripts/Makefile.build:305: die Regel für Ziel
„arch/powerpc/kvm/powerpc.o“ scheiterte
make[2]: *** [arch/powerpc/kvm/powerpc.o] Fehler 1
scripts/Makefile.build:546: die Regel für Ziel „arch/powerpc/kvm“ scheiterte
make[1]: *** [arch/powerpc/kvm] Fehler 2
Makefile:1052: die Regel für Ziel „arch/powerpc“ scheiterte
make: *** [arch/powerpc] Fehler 2
christian@christian-virtual-machine:~/Downloads/a$ env LANG=C make
CROSS_COMPILE=powerpc-linux-gnu- ARCH=powerpc uImage
CALL scripts/checksyscalls.sh
CHK include/generated/compile.h
CALL arch/powerpc/kernel/systbl_chk.sh
CC arch/powerpc/kvm/powerpc.o
In file included from arch/powerpc/kvm/powerpc.c:51:0:
arch/powerpc/kvm/trace.h:9:0: error: "TRACE_INCLUDE_PATH" redefined
[-Werror]
#define TRACE_INCLUDE_PATH .
^
In file included from arch/powerpc/kvm/../mm/mmu_decl.h:25:0,
from arch/powerpc/kvm/powerpc.c:48:
./arch/powerpc/include/asm/trace.h:224:0: note: this is the location of
the previous definition
#define TRACE_INCLUDE_PATH asm
^
cc1: all warnings being treated as errors
scripts/Makefile.build:305: recipe for target
'arch/powerpc/kvm/powerpc.o' failed
make[2]: *** [arch/powerpc/kvm/powerpc.o] Error 1
scripts/Makefile.build:546: recipe for target 'arch/powerpc/kvm' failed
make[1]: *** [arch/powerpc/kvm] Error 2
Makefile:1052: recipe for target 'arch/powerpc' failed
make: *** [arch/powerpc] Error 2
---
I deleted the definition of 'TRACE_INCLUDE_PATH' in
'arch/powerpc/kvm/trace.h'. After that the kernel compiled without any
problems.
-- Christian
^ permalink raw reply
* NXP P50XX/e5500: SMP doesn't work anymore with the latest Git kernel
From: Christian Zigotzky @ 2018-10-29 9:56 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <6bcb4b23-bb78-d1a5-7fd0-5f892115d302@xenosoft.de>
Hello,
I have figured out that the commit 'devicetree-for-4.20' [1] is
responsible for the SMP problem. I was able to revert this commit with
'git revert b27186abb37b7bd19e0ca434f4f425c807dbd708 -m 1' today.
[master ec81438] Revert "Merge tag 'devicetree-for-4.20' of
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux"
138 files changed, 931 insertions(+), 1538 deletions(-)
rename Documentation/devicetree/bindings/arm/{atmel-sysregs.txt =>
atmel-at91.txt} (67%)
delete mode 100644
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt
delete mode 100644
Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-scfg.txt
rename Documentation/devicetree/bindings/arm/{zte,sysctrl.txt =>
zte.txt} (62%)
delete mode 100644 Documentation/devicetree/bindings/misc/lwn-bk4.txt
create mode 100644 arch/c6x/boot/dts/linked_dtb.S
delete mode 100644 arch/nios2/boot/dts/Makefile
create mode 100644 arch/nios2/boot/linked_dtb.S
delete mode 100644 arch/powerpc/boot/dts/Makefile
delete mode 100644 arch/powerpc/boot/dts/fsl/Makefile
delete mode 100644 scripts/dtc/yamltree.c
It solves the SMP problem! SMP works again on my P5020 board and on
virtual e5500 QEMU machines.
QEMU command: ./qemu-system-ppc64 -M ppce500 -cpu e5500 -m 2048 -kernel
/home/christian/Downloads/uImage-4.20-alpha5 -drive
format=raw,file=/home/christian/Dokumente/ubuntu_MATE_16.04.3_LTS_PowerPC_QEMU/ubuntu_MATE_16.04_PowerPC.img,index=0,if=virtio
-nic user,model=e1000 -append "rw root=/dev/vda3" -device virtio-vga
-device virtio-mouse-pci -device virtio-keyboard-pci -soundhw es1370 -smp 4
Screenshot:
https://plus.google.com/u/0/photos/photo/115515624056477014971/6617705776207990082
Do we need a new dtb file or is it a bug?
Thanks,
Christian
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b27186abb37b7bd19e0ca434f4f425c807dbd708
On 28 October 2018 at 5:35PM, Christian Zigotzky wrote:
> Hello,
>
> SMP doesn't work anymore with the latest Git kernel (28/10/18 11:12AM
> GMT) on my P5020 board and on virtual e5500 QEMU machines.
>
> Board with P5020 dual core CPU:
>
> [ 0.000000] -----------------------------------------------------
> [ 0.000000] phys_mem_size = 0x200000000
> [ 0.000000] dcache_bsize = 0x40
> [ 0.000000] icache_bsize = 0x40
> [ 0.000000] cpu_features = 0x00000003008003b4
> [ 0.000000] possible = 0x00000003009003b4
> [ 0.000000] always = 0x00000003008003b4
> [ 0.000000] cpu_user_features = 0xcc008000 0x08000000
> [ 0.000000] mmu_features = 0x000a0010
> [ 0.000000] firmware_features = 0x0000000000000000
> [ 0.000000] -----------------------------------------------------
> [ 0.000000] CoreNet Generic board
>
> ...
>
> [ 0.002161] smp: Bringing up secondary CPUs ...
> [ 0.002339] No cpu-release-addr for cpu 1
> [ 0.002347] smp: failed starting cpu 1 (rc -2)
> [ 0.002401] smp: Brought up 1 node, 1 CPU
>
> Virtual e5500 quad core QEMU machine:
>
> [ 0.026394] smp: Bringing up secondary CPUs ...
> [ 0.027831] No cpu-release-addr for cpu 1
> [ 0.027989] smp: failed starting cpu 1 (rc -2)
> [ 0.030143] No cpu-release-addr for cpu 2
> [ 0.030304] smp: failed starting cpu 2 (rc -2)
> [ 0.032400] No cpu-release-addr for cpu 3
> [ 0.032533] smp: failed starting cpu 3 (rc -2)
> [ 0.033117] smp: Brought up 1 node, 1 CPU
>
> QEMU command: ./qemu-system-ppc64 -M ppce500 -cpu e5500 -m 2048
> -kernel
> /home/christian/Downloads/vmlinux-4.20-alpha4-AmigaOne_X1000_X5000/X5000_and_QEMU_e5500/uImage-4.20
> -drive
> format=raw,file=/home/christian/Downloads/MATE_PowerPC_Remix_2017_0.9.img,index=0,if=virtio
> -nic user,model=e1000 -append "rw root=/dev/vda" -device virtio-vga
> -device virtio-mouse-pci -device virtio-keyboard-pci -usb -soundhw
> es1370 -smp 4
>
> .config:
>
> ...
> CONFIG_SMP=y
> CONFIG_NR_CPUS=4
> ...
>
> Please test the latest Git kernel on your NXP P50XX boards.
>
> Thanks,
> Christian
>
^ permalink raw reply
* RE: [PATCH 3/7] dmaengine: fsl-qdma: Add qDMA controller driver for Layerscape SoCs
From: Peng Ma @ 2018-10-29 9:51 UTC (permalink / raw)
To: Leo Li
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Wen He, linuxppc-dev, lkml, Jiaheng Fan, Vinod, Rob Herring,
dmaengine@vger.kernel.org, Dan Williams, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CADRPPNRu3vEcLMegMC3-5xGe6D2JkZyb6+mmYzZFatffUosF3w@mail.gmail.com>
>-----Original Message-----
>From: Li Yang <leoyang.li@nxp.com>
>Sent: 2018年10月27日 4:48
>To: Peng Ma <peng.ma@nxp.com>
>Cc: Vinod <vkoul@kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark
>Rutland <mark.rutland@arm.com>; Shawn Guo <shawnguo@kernel.org>; Dan
>Williams <dan.j.williams@intel.com>; dmaengine@vger.kernel.org; open
>list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
><devicetree@vger.kernel.org>; lkml <linux-kernel@vger.kernel.org>;
>moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
><linux-arm-kernel@lists.infradead.org>; linuxppc-dev
><linuxppc-dev@lists.ozlabs.org>; Wen He <wen.he_1@nxp.com>; Jiaheng Fan
><jiaheng.fan@nxp.com>
>Subject: Re: [PATCH 3/7] dmaengine: fsl-qdma: Add qDMA controller driver for
>Layerscape SoCs
>
>On Fri, Oct 26, 2018 at 4:57 AM Peng Ma <peng.ma@nxp.com> wrote:
>>
>> NXP Queue DMA controller(qDMA) on Layerscape SoCs supports channel
>> virtuallization by allowing DMA jobs to be enqueued into different
>> command queues.
>>
>> Note that this module depends on NXP DPAA.
>
>It is not clear if you are saying that the driver can only work on
>SoCs with a DPAA hardware block, or the driver is actually depending
>on the DPAA drivers also. If it is the later case, you also should
>express that in the Kconfig you added below.
>
[Peng Ma] Ok, I will express it in the Kconfig.
>>
>> Signed-off-by: Wen He <wen.he_1@nxp.com>
>> Signed-off-by: Jiaheng Fan <jiaheng.fan@nxp.com>
>> Signed-off-by: Peng Ma <peng.ma@nxp.com>
>> ---
>> change in v10:
>> - no
>>
>> drivers/dma/Kconfig | 13 +
>> drivers/dma/Makefile | 1 +
>> drivers/dma/fsl-qdma.c | 1257
>++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1271 insertions(+), 0 deletions(-)
>> create mode 100644 drivers/dma/fsl-qdma.c
>>
>> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
>> index dacf3f4..50e19d7 100644
>> --- a/drivers/dma/Kconfig
>> +++ b/drivers/dma/Kconfig
>> @@ -218,6 +218,19 @@ config FSL_EDMA
>> multiplexing capability for DMA request sources(slot).
>> This module can be found on Freescale Vybrid and LS-1 SoCs.
>>
>> +config FSL_QDMA
>> + tristate "NXP Layerscape qDMA engine support"
>> + depends on ARM || ARM64
>> + select DMA_ENGINE
>> + select DMA_VIRTUAL_CHANNELS
>> + select DMA_ENGINE_RAID
>> + select ASYNC_TX_ENABLE_CHANNEL_SWITCH
>> + help
>> + Support the NXP Layerscape qDMA engine with command queue
>and legacy mode.
>> + Channel virtualization is supported through enqueuing of DMA
>jobs to,
>> + or dequeuing DMA jobs from, different work queues.
>> + This module can be found on NXP Layerscape SoCs.
>> +
>> config FSL_RAID
>> tristate "Freescale RAID engine Support"
>> depends on FSL_SOC
>&& !ASYNC_TX_ENABLE_CHANNEL_SWITCH
>> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
>> index c91702d..2d1b586 100644
>> --- a/drivers/dma/Makefile
>> +++ b/drivers/dma/Makefile
>> @@ -32,6 +32,7 @@ obj-$(CONFIG_DW_DMAC_CORE) += dw/
>> obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
>> obj-$(CONFIG_FSL_DMA) += fsldma.o
>> obj-$(CONFIG_FSL_EDMA) += fsl-edma.o
>> +obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
>> obj-$(CONFIG_FSL_RAID) += fsl_raid.o
>> obj-$(CONFIG_HSU_DMA) += hsu/
>> obj-$(CONFIG_IMG_MDC_DMA) += img-mdc-dma.o
>> diff --git a/drivers/dma/fsl-qdma.c b/drivers/dma/fsl-qdma.c
>> new file mode 100644
>> index 0000000..404869e
>> --- /dev/null
>> +++ b/drivers/dma/fsl-qdma.c
>> @@ -0,0 +1,1257 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +// Copyright 2018 NXP
>
>I'm not sure if this is really the case. The driver at least has been
>sent out in 2015. We should keep these copyright claims, even the
>legacy Freescale copyright claims.
>
[Peng Ma]
I am not sure this patch sent out in 2015, but the git log earliest shows the patch cteated at Dec 20 2017. so if i changed the "Copyright 2018 NXP" to " Copyright 2017-2018 NXP "
Best regards
Peng Ma
>> +
>> +/*
>> + * Driver for NXP Layerscape Queue Direct Memory Access Controller
>> + *
>> + * Author:
>> + * Wen He <wen.he_1@nxp.com>
>> + * Jiaheng Fan <jiaheng.fan@nxp.com>
>> + *
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/delay.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/of_dma.h>
>> +#include <linux/dma-mapping.h>
>> +
>> +#include "virt-dma.h"
>> +#include "fsldma.h"
>> +
>> +/* Register related definition */
>> +#define FSL_QDMA_DMR 0x0
>> +#define FSL_QDMA_DSR 0x4
>> +#define FSL_QDMA_DEIER 0xe00
>> +#define FSL_QDMA_DEDR 0xe04
>> +#define FSL_QDMA_DECFDW0R 0xe10
>> +#define FSL_QDMA_DECFDW1R 0xe14
>> +#define FSL_QDMA_DECFDW2R 0xe18
>> +#define FSL_QDMA_DECFDW3R 0xe1c
>> +#define FSL_QDMA_DECFQIDR 0xe30
>> +#define FSL_QDMA_DECBR 0xe34
>> +
>> +#define FSL_QDMA_BCQMR(x) (0xc0 + 0x100 * (x))
>> +#define FSL_QDMA_BCQSR(x) (0xc4 + 0x100 * (x))
>> +#define FSL_QDMA_BCQEDPA_SADDR(x) (0xc8 + 0x100 * (x))
>> +#define FSL_QDMA_BCQDPA_SADDR(x) (0xcc + 0x100 * (x))
>> +#define FSL_QDMA_BCQEEPA_SADDR(x) (0xd0 + 0x100 * (x))
>> +#define FSL_QDMA_BCQEPA_SADDR(x) (0xd4 + 0x100 * (x))
>> +#define FSL_QDMA_BCQIER(x) (0xe0 + 0x100 * (x))
>> +#define FSL_QDMA_BCQIDR(x) (0xe4 + 0x100 * (x))
>> +
>> +#define FSL_QDMA_SQDPAR 0x80c
>> +#define FSL_QDMA_SQEPAR 0x814
>> +#define FSL_QDMA_BSQMR 0x800
>> +#define FSL_QDMA_BSQSR 0x804
>> +#define FSL_QDMA_BSQICR 0x828
>> +#define FSL_QDMA_CQMR 0xa00
>> +#define FSL_QDMA_CQDSCR1 0xa08
>> +#define FSL_QDMA_CQDSCR2 0xa0c
>> +#define FSL_QDMA_CQIER 0xa10
>> +#define FSL_QDMA_CQEDR 0xa14
>> +#define FSL_QDMA_SQCCMR 0xa20
>> +
>> +/* Registers for bit and genmask */
>> +#define FSL_QDMA_CQIDR_SQT BIT(15)
>> +#define QDMA_CCDF_FOTMAT BIT(29)
>> +#define QDMA_CCDF_SER BIT(30)
>> +#define QDMA_SG_FIN BIT(30)
>> +#define QDMA_SG_LEN_MASK GENMASK(29, 0)
>> +#define QDMA_CCDF_MASK GENMASK(28, 20)
>> +
>> +#define FSL_QDMA_DEDR_CLEAR GENMASK(31, 0)
>> +#define FSL_QDMA_BCQIDR_CLEAR GENMASK(31, 0)
>> +#define FSL_QDMA_DEIER_CLEAR GENMASK(31, 0)
>> +
>> +#define FSL_QDMA_BCQIER_CQTIE BIT(15)
>> +#define FSL_QDMA_BCQIER_CQPEIE BIT(23)
>> +#define FSL_QDMA_BSQICR_ICEN BIT(31)
>> +
>> +#define FSL_QDMA_BSQICR_ICST(x) ((x) << 16)
>> +#define FSL_QDMA_CQIER_MEIE BIT(31)
>> +#define FSL_QDMA_CQIER_TEIE BIT(0)
>> +#define FSL_QDMA_SQCCMR_ENTER_WM BIT(21)
>> +
>> +#define FSL_QDMA_BCQMR_EN BIT(31)
>> +#define FSL_QDMA_BCQMR_EI BIT(30)
>> +#define FSL_QDMA_BCQMR_CD_THLD(x) ((x) << 20)
>> +#define FSL_QDMA_BCQMR_CQ_SIZE(x) ((x) << 16)
>> +
>> +#define FSL_QDMA_BCQSR_QF BIT(16)
>> +#define FSL_QDMA_BCQSR_XOFF BIT(0)
>> +
>> +#define FSL_QDMA_BSQMR_EN BIT(31)
>> +#define FSL_QDMA_BSQMR_DI BIT(30)
>> +#define FSL_QDMA_BSQMR_CQ_SIZE(x) ((x) << 16)
>> +
>> +#define FSL_QDMA_BSQSR_QE BIT(17)
>> +
>> +#define FSL_QDMA_DMR_DQD BIT(30)
>> +#define FSL_QDMA_DSR_DB BIT(31)
>> +
>> +/* Size related definition */
>> +#define FSL_QDMA_QUEUE_MAX 8
>> +#define FSL_QDMA_COMMAND_BUFFER_SIZE 64
>> +#define FSL_QDMA_DESCRIPTOR_BUFFER_SIZE 32
>> +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MIN 64
>> +#define FSL_QDMA_CIRCULAR_DESC_SIZE_MAX 16384
>> +#define FSL_QDMA_QUEUE_NUM_MAX 8
>> +
>> +/* Field definition for CMD */
>> +#define FSL_QDMA_CMD_RWTTYPE 0x4
>> +#define FSL_QDMA_CMD_LWC 0x2
>> +#define FSL_QDMA_CMD_RWTTYPE_OFFSET 28
>> +#define FSL_QDMA_CMD_NS_OFFSET 27
>> +#define FSL_QDMA_CMD_DQOS_OFFSET 24
>> +#define FSL_QDMA_CMD_WTHROTL_OFFSET 20
>> +#define FSL_QDMA_CMD_DSEN_OFFSET 19
>> +#define FSL_QDMA_CMD_LWC_OFFSET 16
>> +
>> +/* Field definition for Descriptor offset */
>> +#define QDMA_CCDF_STATUS 20
>> +#define QDMA_CCDF_OFFSET 20
>> +
>> +/* Field definition for safe loop count*/
>> +#define FSL_QDMA_HALT_COUNT 1500
>> +#define FSL_QDMA_MAX_SIZE 16385
>> +#define FSL_QDMA_COMP_TIMEOUT 1000
>> +#define FSL_COMMAND_QUEUE_OVERFLLOW 10
>> +
>> +#define FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma_engine, x)
>\
>> + (((fsl_qdma_engine)->block_offset) * (x))
>> +
>> +/**
>> + * struct fsl_qdma_format - This is the struct holding describing compound
>> + * descriptor format with qDMA.
>> + * @status: Command status and enqueue status
>notification.
>> + * @cfg: Frame offset and frame format.
>> + * @addr_lo: Holding the compound descriptor of the
>lower
>> + * 32-bits address in memory 40-bit address.
>> + * @addr_hi: Same as above member, but point high
>8-bits in
>> + * memory 40-bit address.
>> + * @__reserved1: Reserved field.
>> + * @cfg8b_w1: Compound descriptor command queue
>origin produced
>> + * by qDMA and dynamic debug field.
>> + * @data Pointer to the memory 40-bit address,
>describes DMA
>> + * source information and DMA destination
>information.
>> + */
>> +struct fsl_qdma_format {
>> + __le32 status;
>> + __le32 cfg;
>> + union {
>> + struct {
>> + __le32 addr_lo;
>> + u8 addr_hi;
>> + u8 __reserved1[2];
>> + u8 cfg8b_w1;
>> + } __packed;
>> + __le64 data;
>> + };
>> +} __packed;
>> +
>> +/* qDMA status notification pre information */
>> +struct fsl_pre_status {
>> + u64 addr;
>> + u8 queue;
>> +};
>> +
>> +static DEFINE_PER_CPU(struct fsl_pre_status, pre);
>> +
>> +struct fsl_qdma_chan {
>> + struct virt_dma_chan vchan;
>> + struct virt_dma_desc vdesc;
>> + enum dma_status status;
>> + struct fsl_qdma_engine *qdma;
>> + struct fsl_qdma_queue *queue;
>> +};
>> +
>> +struct fsl_qdma_queue {
>> + struct fsl_qdma_format *virt_head;
>> + struct fsl_qdma_format *virt_tail;
>> + struct list_head comp_used;
>> + struct list_head comp_free;
>> + struct dma_pool *comp_pool;
>> + struct dma_pool *desc_pool;
>> + spinlock_t queue_lock;
>> + dma_addr_t bus_addr;
>> + u32 n_cq;
>> + u32 id;
>> + struct fsl_qdma_format *cq;
>> + void __iomem *block_base;
>> +};
>> +
>> +struct fsl_qdma_comp {
>> + dma_addr_t bus_addr;
>> + dma_addr_t desc_bus_addr;
>> + struct fsl_qdma_format *virt_addr;
>> + struct fsl_qdma_format *desc_virt_addr;
>> + struct fsl_qdma_chan *qchan;
>> + struct virt_dma_desc vdesc;
>> + struct list_head list;
>> +};
>> +
>> +struct fsl_qdma_engine {
>> + struct dma_device dma_dev;
>> + void __iomem *ctrl_base;
>> + void __iomem *status_base;
>> + void __iomem *block_base;
>> + u32 n_chans;
>> + u32 n_queues;
>> + struct mutex fsl_qdma_mutex;
>> + int error_irq;
>> + int *queue_irq;
>> + u32 feature;
>> + struct fsl_qdma_queue *queue;
>> + struct fsl_qdma_queue **status;
>> + struct fsl_qdma_chan *chans;
>> + int block_number;
>> + int block_offset;
>> + int irq_base;
>> + int desc_allocated;
>> +
>> +};
>> +
>> +static inline u64
>> +qdma_ccdf_addr_get64(const struct fsl_qdma_format *ccdf)
>> +{
>> + return le64_to_cpu(ccdf->data) & (U64_MAX >> 24);
>> +}
>> +
>> +static inline void
>> +qdma_desc_addr_set64(struct fsl_qdma_format *ccdf, u64 addr)
>> +{
>> + ccdf->addr_hi = upper_32_bits(addr);
>> + ccdf->addr_lo = cpu_to_le32(lower_32_bits(addr));
>> +}
>> +
>> +static inline u8
>> +qdma_ccdf_get_queue(const struct fsl_qdma_format *ccdf)
>> +{
>> + return ccdf->cfg8b_w1 & U8_MAX;
>> +}
>> +
>> +static inline int
>> +qdma_ccdf_get_offset(const struct fsl_qdma_format *ccdf)
>> +{
>> + return (le32_to_cpu(ccdf->cfg) & QDMA_CCDF_MASK) >>
>QDMA_CCDF_OFFSET;
>> +}
>> +
>> +static inline void
>> +qdma_ccdf_set_format(struct fsl_qdma_format *ccdf, int offset)
>> +{
>> + ccdf->cfg = cpu_to_le32(QDMA_CCDF_FOTMAT | offset);
>> +}
>> +
>> +static inline int
>> +qdma_ccdf_get_status(const struct fsl_qdma_format *ccdf)
>> +{
>> + return (le32_to_cpu(ccdf->status) & QDMA_CCDF_MASK) >>
>QDMA_CCDF_STATUS;
>> +}
>> +
>> +static inline void
>> +qdma_ccdf_set_ser(struct fsl_qdma_format *ccdf, int status)
>> +{
>> + ccdf->status = cpu_to_le32(QDMA_CCDF_SER | status);
>> +}
>> +
>> +static inline void qdma_csgf_set_len(struct fsl_qdma_format *csgf, int len)
>> +{
>> + csgf->cfg = cpu_to_le32(len & QDMA_SG_LEN_MASK);
>> +}
>> +
>> +static inline void qdma_csgf_set_f(struct fsl_qdma_format *csgf, int len)
>> +{
>> + csgf->cfg = cpu_to_le32(QDMA_SG_FIN | (len &
>QDMA_SG_LEN_MASK));
>> +}
>> +
>> +static u32 qdma_readl(struct fsl_qdma_engine *qdma, void __iomem
>*addr)
>> +{
>> + return FSL_DMA_IN(qdma, addr, 32);
>> +}
>> +
>> +static void qdma_writel(struct fsl_qdma_engine *qdma, u32 val,
>> + void __iomem *addr)
>> +{
>> + FSL_DMA_OUT(qdma, addr, val, 32);
>> +}
>> +
>> +static struct fsl_qdma_chan *to_fsl_qdma_chan(struct dma_chan *chan)
>> +{
>> + return container_of(chan, struct fsl_qdma_chan, vchan.chan);
>> +}
>> +
>> +static struct fsl_qdma_comp *to_fsl_qdma_comp(struct virt_dma_desc *vd)
>> +{
>> + return container_of(vd, struct fsl_qdma_comp, vdesc);
>> +}
>> +
>> +static void fsl_qdma_free_chan_resources(struct dma_chan *chan)
>> +{
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
>> + struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
>> + struct fsl_qdma_comp *comp_temp, *_comp_temp;
>> + unsigned long flags;
>> + LIST_HEAD(head);
>> +
>> + spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
>> + vchan_get_all_descriptors(&fsl_chan->vchan, &head);
>> + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
>> +
>> + vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
>> +
>> + if (!fsl_queue->comp_pool && !fsl_queue->comp_pool)
>> + return;
>> +
>> + list_for_each_entry_safe(comp_temp, _comp_temp,
>> + &fsl_queue->comp_used, list) {
>> + dma_pool_free(fsl_queue->comp_pool,
>> + comp_temp->virt_addr,
>> + comp_temp->bus_addr);
>> + dma_pool_free(fsl_queue->desc_pool,
>> + comp_temp->desc_virt_addr,
>> + comp_temp->desc_bus_addr);
>> + list_del(&comp_temp->list);
>> + kfree(comp_temp);
>> + }
>> +
>> + list_for_each_entry_safe(comp_temp, _comp_temp,
>> + &fsl_queue->comp_free, list) {
>> + dma_pool_free(fsl_queue->comp_pool,
>> + comp_temp->virt_addr,
>> + comp_temp->bus_addr);
>> + dma_pool_free(fsl_queue->desc_pool,
>> + comp_temp->desc_virt_addr,
>> + comp_temp->desc_bus_addr);
>> + list_del(&comp_temp->list);
>> + kfree(comp_temp);
>> + }
>> +
>> + dma_pool_destroy(fsl_queue->comp_pool);
>> + dma_pool_destroy(fsl_queue->desc_pool);
>> +
>> + fsl_qdma->desc_allocated--;
>> + fsl_queue->comp_pool = NULL;
>> + fsl_queue->desc_pool = NULL;
>> +}
>> +
>> +static void fsl_qdma_comp_fill_memcpy(struct fsl_qdma_comp *fsl_comp,
>> + dma_addr_t dst, dma_addr_t
>src, u32 len)
>> +{
>> + struct fsl_qdma_format *sdf, *ddf;
>> + struct fsl_qdma_format *ccdf, *csgf_desc, *csgf_src, *csgf_dest;
>> +
>> + ccdf = fsl_comp->virt_addr;
>> + csgf_desc = fsl_comp->virt_addr + 1;
>> + csgf_src = fsl_comp->virt_addr + 2;
>> + csgf_dest = fsl_comp->virt_addr + 3;
>> + sdf = fsl_comp->desc_virt_addr;
>> + ddf = fsl_comp->desc_virt_addr + 1;
>> +
>> + memset(fsl_comp->virt_addr, 0,
>FSL_QDMA_COMMAND_BUFFER_SIZE);
>> + memset(fsl_comp->desc_virt_addr, 0,
>FSL_QDMA_DESCRIPTOR_BUFFER_SIZE);
>> + /* Head Command Descriptor(Frame Descriptor) */
>> + qdma_desc_addr_set64(ccdf, fsl_comp->bus_addr + 16);
>> + qdma_ccdf_set_format(ccdf, qdma_ccdf_get_offset(ccdf));
>> + qdma_ccdf_set_ser(ccdf, qdma_ccdf_get_status(ccdf));
>> + /* Status notification is enqueued to status queue. */
>> + /* Compound Command Descriptor(Frame List Table) */
>> + qdma_desc_addr_set64(csgf_desc, fsl_comp->desc_bus_addr);
>> + /* It must be 32 as Compound S/G Descriptor */
>> + qdma_csgf_set_len(csgf_desc, 32);
>> + qdma_desc_addr_set64(csgf_src, src);
>> + qdma_csgf_set_len(csgf_src, len);
>> + qdma_desc_addr_set64(csgf_dest, dst);
>> + qdma_csgf_set_len(csgf_dest, len);
>> + /* This entry is the last entry. */
>> + qdma_csgf_set_f(csgf_dest, len);
>> + /* Descriptor Buffer */
>> + sdf->data =
>> + cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> + ddf->data =
>> + cpu_to_le64(FSL_QDMA_CMD_RWTTYPE <<
>> + FSL_QDMA_CMD_RWTTYPE_OFFSET);
>> + ddf->data |=
>> + cpu_to_le64(FSL_QDMA_CMD_LWC <<
>FSL_QDMA_CMD_LWC_OFFSET);
>> +}
>> +
>> +/*
>> + * Pre-request full command descriptor for enqueue.
>> + */
>> +static int fsl_qdma_pre_request_enqueue_desc(struct fsl_qdma_queue
>*queue)
>> +{
>> + int i;
>> + struct fsl_qdma_comp *comp_temp, *_comp_temp;
>> +
>> + for (i = 0; i < queue->n_cq + FSL_COMMAND_QUEUE_OVERFLLOW;
>i++) {
>> + comp_temp = kzalloc(sizeof(*comp_temp),
>GFP_KERNEL);
>> + if (!comp_temp)
>> + goto err_alloc;
>> + comp_temp->virt_addr =
>> + dma_pool_alloc(queue->comp_pool,
>GFP_KERNEL,
>> + &comp_temp->bus_addr);
>> + if (!comp_temp->virt_addr)
>> + goto err_dma_alloc;
>> +
>> + comp_temp->desc_virt_addr =
>> + dma_pool_alloc(queue->desc_pool,
>GFP_KERNEL,
>> +
>&comp_temp->desc_bus_addr);
>> + if (!comp_temp->desc_virt_addr)
>> + goto err_desc_dma_alloc;
>> +
>> + list_add_tail(&comp_temp->list, &queue->comp_free);
>> + }
>> +
>> + return 0;
>> +
>> +err_desc_dma_alloc:
>> + dma_pool_free(queue->comp_pool, comp_temp->virt_addr,
>> + comp_temp->bus_addr);
>> +
>> +err_dma_alloc:
>> + kfree(comp_temp);
>> +
>> +err_alloc:
>> + list_for_each_entry_safe(comp_temp, _comp_temp,
>> + &queue->comp_free, list) {
>> + if (comp_temp->virt_addr)
>> + dma_pool_free(queue->comp_pool,
>> + comp_temp->virt_addr,
>> + comp_temp->bus_addr);
>> + if (comp_temp->desc_virt_addr)
>> + dma_pool_free(queue->desc_pool,
>> + comp_temp->desc_virt_addr,
>> +
>comp_temp->desc_bus_addr);
>> +
>> + list_del(&comp_temp->list);
>> + kfree(comp_temp);
>> + }
>> +
>> + return -ENOMEM;
>> +}
>> +
>> +/*
>> + * Request a command descriptor for enqueue.
>> + */
>> +static struct fsl_qdma_comp
>> +*fsl_qdma_request_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
>> +{
>> + unsigned long flags;
>> + struct fsl_qdma_comp *comp_temp;
>> + int timeout = FSL_QDMA_COMP_TIMEOUT;
>> + struct fsl_qdma_queue *queue = fsl_chan->queue;
>> +
>> + while (timeout--) {
>> + spin_lock_irqsave(&queue->queue_lock, flags);
>> + if (!list_empty(&queue->comp_free)) {
>> + comp_temp =
>list_first_entry(&queue->comp_free,
>> + struct
>fsl_qdma_comp,
>> + list);
>> + list_del(&comp_temp->list);
>> +
>> + spin_unlock_irqrestore(&queue->queue_lock,
>flags);
>> + comp_temp->qchan = fsl_chan;
>> + return comp_temp;
>> + }
>> + spin_unlock_irqrestore(&queue->queue_lock, flags);
>> + udelay(1);
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +static struct fsl_qdma_queue
>> +*fsl_qdma_alloc_queue_resources(struct platform_device *pdev,
>> + struct fsl_qdma_engine *fsl_qdma)
>> +{
>> + int ret, len, i, j;
>> + int queue_num, block_number;
>> + unsigned int queue_size[FSL_QDMA_QUEUE_MAX];
>> + struct fsl_qdma_queue *queue_head, *queue_temp;
>> +
>> + queue_num = fsl_qdma->n_queues;
>> + block_number = fsl_qdma->block_number;
>> +
>> + if (queue_num > FSL_QDMA_QUEUE_MAX)
>> + queue_num = FSL_QDMA_QUEUE_MAX;
>> + len = sizeof(*queue_head) * queue_num * block_number;
>> + queue_head = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
>> + if (!queue_head)
>> + return NULL;
>> +
>> + ret = device_property_read_u32_array(&pdev->dev, "queue-sizes",
>> + queue_size,
>queue_num);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get queue-sizes.\n");
>> + return NULL;
>> + }
>> + for (j = 0; j < block_number; j++) {
>> + for (i = 0; i < queue_num; i++) {
>> + if (queue_size[i] >
>FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
>> + queue_size[i] <
>FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
>> + dev_err(&pdev->dev,
>> + "Get wrong
>queue-sizes.\n");
>> + return NULL;
>> + }
>> + queue_temp = queue_head + i + (j *
>queue_num);
>> +
>> + queue_temp->cq =
>> + dma_alloc_coherent(&pdev->dev,
>> + sizeof(struct
>fsl_qdma_format) *
>> + queue_size[i],
>> +
>&queue_temp->bus_addr,
>> + GFP_KERNEL);
>> + if (!queue_temp->cq)
>> + return NULL;
>> + queue_temp->block_base =
>fsl_qdma->block_base +
>> +
>FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
>> + queue_temp->n_cq = queue_size[i];
>> + queue_temp->id = i;
>> + queue_temp->virt_head = queue_temp->cq;
>> + queue_temp->virt_tail = queue_temp->cq;
>> + /*
>> + * List for queue command buffer
>> + */
>> + INIT_LIST_HEAD(&queue_temp->comp_used);
>> + spin_lock_init(&queue_temp->queue_lock);
>> + }
>> + }
>> + return queue_head;
>> +}
>> +
>> +static struct fsl_qdma_queue
>> +*fsl_qdma_prep_status_queue(struct platform_device *pdev)
>> +{
>> + int ret;
>> + unsigned int status_size;
>> + struct fsl_qdma_queue *status_head;
>> + struct device_node *np = pdev->dev.of_node;
>> +
>> + ret = of_property_read_u32(np, "status-sizes", &status_size);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get status-sizes.\n");
>> + return NULL;
>> + }
>> + if (status_size > FSL_QDMA_CIRCULAR_DESC_SIZE_MAX ||
>> + status_size < FSL_QDMA_CIRCULAR_DESC_SIZE_MIN) {
>> + dev_err(&pdev->dev, "Get wrong status_size.\n");
>> + return NULL;
>> + }
>> + status_head = devm_kzalloc(&pdev->dev,
>> + sizeof(*status_head),
>GFP_KERNEL);
>> + if (!status_head)
>> + return NULL;
>> +
>> + /*
>> + * Buffer for queue command
>> + */
>> + status_head->cq = dma_alloc_coherent(&pdev->dev,
>> + sizeof(struct
>fsl_qdma_format) *
>> + status_size,
>> +
>&status_head->bus_addr,
>> + GFP_KERNEL);
>> + if (!status_head->cq) {
>> + devm_kfree(&pdev->dev, status_head);
>> + return NULL;
>> + }
>> + status_head->n_cq = status_size;
>> + status_head->virt_head = status_head->cq;
>> + status_head->virt_tail = status_head->cq;
>> + status_head->comp_pool = NULL;
>> +
>> + return status_head;
>> +}
>> +
>> +static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
>> +{
>> + u32 reg;
>> + int i, j, count = FSL_QDMA_HALT_COUNT;
>> + void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
>> +
>> + /* Disable the command queue and wait for idle state. */
>> + reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
>> + reg |= FSL_QDMA_DMR_DQD;
>> + qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
>> + for (j = 0; j < fsl_qdma->block_number; j++) {
>> + block = fsl_qdma->block_base +
>> + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
>> + for (i = 0; i < FSL_QDMA_QUEUE_NUM_MAX; i++)
>> + qdma_writel(fsl_qdma, 0, block +
>FSL_QDMA_BCQMR(i));
>> + }
>> + while (1) {
>> + reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
>> + if (!(reg & FSL_QDMA_DSR_DB))
>> + break;
>> + if (count-- < 0)
>> + return -EBUSY;
>> + udelay(100);
>> + }
>> +
>> + for (j = 0; j < fsl_qdma->block_number; j++) {
>> + block = fsl_qdma->block_base +
>> + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
>> +
>> + /* Disable status queue. */
>> + qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
>> +
>> + /*
>> + * clear the command queue interrupt detect register for
>> + * all queues.
>> + */
>> + qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
>> + block + FSL_QDMA_BCQIDR(0));
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int
>> +fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
>> + void *block,
>> + int id)
>> +{
>> + bool duplicate;
>> + u32 reg, i, count;
>> + struct fsl_qdma_queue *temp_queue;
>> + struct fsl_qdma_format *status_addr;
>> + struct fsl_qdma_comp *fsl_comp = NULL;
>> + struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
>> + struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
>> +
>> + count = FSL_QDMA_MAX_SIZE;
>> +
>> + while (count--) {
>> + duplicate = 0;
>> + reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
>> + if (reg & FSL_QDMA_BSQSR_QE)
>> + return 0;
>> +
>> + status_addr = fsl_status->virt_head;
>> +
>> + if (qdma_ccdf_get_queue(status_addr) ==
>> + __this_cpu_read(pre.queue) &&
>> + qdma_ccdf_addr_get64(status_addr) ==
>> + __this_cpu_read(pre.addr))
>> + duplicate = 1;
>> + i = qdma_ccdf_get_queue(status_addr) +
>> + id * fsl_qdma->n_queues;
>> + __this_cpu_write(pre.addr,
>qdma_ccdf_addr_get64(status_addr));
>> + __this_cpu_write(pre.queue,
>qdma_ccdf_get_queue(status_addr));
>> + temp_queue = fsl_queue + i;
>> +
>> + spin_lock(&temp_queue->queue_lock);
>> + if (list_empty(&temp_queue->comp_used)) {
>> + if (!duplicate) {
>> +
>spin_unlock(&temp_queue->queue_lock);
>> + return -EAGAIN;
>> + }
>> + } else {
>> + fsl_comp =
>list_first_entry(&temp_queue->comp_used,
>> + struct
>fsl_qdma_comp, list);
>> + if (fsl_comp->bus_addr + 16 !=
>> + __this_cpu_read(pre.addr)) {
>> + if (!duplicate) {
>> +
>spin_unlock(&temp_queue->queue_lock);
>> + return -EAGAIN;
>> + }
>> + }
>> + }
>> +
>> + if (duplicate) {
>> + reg = qdma_readl(fsl_qdma, block +
>FSL_QDMA_BSQMR);
>> + reg |= FSL_QDMA_BSQMR_DI;
>> + qdma_desc_addr_set64(status_addr, 0x0);
>> + fsl_status->virt_head++;
>> + if (fsl_status->virt_head == fsl_status->cq
>> + +
>fsl_status->n_cq)
>> + fsl_status->virt_head =
>fsl_status->cq;
>> + qdma_writel(fsl_qdma, reg, block +
>FSL_QDMA_BSQMR);
>> + spin_unlock(&temp_queue->queue_lock);
>> + continue;
>> + }
>> + list_del(&fsl_comp->list);
>> +
>> + reg = qdma_readl(fsl_qdma, block +
>FSL_QDMA_BSQMR);
>> + reg |= FSL_QDMA_BSQMR_DI;
>> + qdma_desc_addr_set64(status_addr, 0x0);
>> + fsl_status->virt_head++;
>> + if (fsl_status->virt_head == fsl_status->cq +
>fsl_status->n_cq)
>> + fsl_status->virt_head = fsl_status->cq;
>> + qdma_writel(fsl_qdma, reg, block +
>FSL_QDMA_BSQMR);
>> + spin_unlock(&temp_queue->queue_lock);
>> +
>> + spin_lock(&fsl_comp->qchan->vchan.lock);
>> + vchan_cookie_complete(&fsl_comp->vdesc);
>> + fsl_comp->qchan->status = DMA_COMPLETE;
>> + spin_unlock(&fsl_comp->qchan->vchan.lock);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static irqreturn_t fsl_qdma_error_handler(int irq, void *dev_id)
>> +{
>> + unsigned int intr;
>> + struct fsl_qdma_engine *fsl_qdma = dev_id;
>> + void __iomem *status = fsl_qdma->status_base;
>> +
>> + intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
>> +
>> + if (intr) {
>> + dev_err(fsl_qdma->dma_dev.dev, "DMA transaction
>error!\n");
>> + return IRQ_NONE;
>> + }
>> +
>> + qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status +
>FSL_QDMA_DEDR);
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t fsl_qdma_queue_handler(int irq, void *dev_id)
>> +{
>> + int id;
>> + unsigned int intr, reg;
>> + struct fsl_qdma_engine *fsl_qdma = dev_id;
>> + void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
>> +
>> + id = irq - fsl_qdma->irq_base;
>> + if (id < 0 && id > fsl_qdma->block_number) {
>> + dev_err(fsl_qdma->dma_dev.dev,
>> + "irq %d is wrong irq_base is %d\n",
>> + irq, fsl_qdma->irq_base);
>> + }
>> +
>> + block = fsl_qdma->block_base +
>> + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
>> +
>> + intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
>> +
>> + if ((intr & FSL_QDMA_CQIDR_SQT) != 0)
>> + intr = fsl_qdma_queue_transfer_complete(fsl_qdma,
>block, id);
>> +
>> + if (intr != 0) {
>> + reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
>> + reg |= FSL_QDMA_DMR_DQD;
>> + qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
>> + qdma_writel(fsl_qdma, 0, block +
>FSL_QDMA_BCQIER(0));
>> + dev_err(fsl_qdma->dma_dev.dev, "QDMA: status
>err!\n");
>> + }
>> +
>> + /* Clear all detected events and interrupts. */
>> + qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
>> + block + FSL_QDMA_BCQIDR(0));
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int
>> +fsl_qdma_irq_init(struct platform_device *pdev,
>> + struct fsl_qdma_engine *fsl_qdma)
>> +{
>> + int i;
>> + int cpu;
>> + int ret;
>> + char irq_name[20];
>> +
>> + fsl_qdma->error_irq =
>> + platform_get_irq_byname(pdev, "qdma-error");
>> + if (fsl_qdma->error_irq < 0) {
>> + dev_err(&pdev->dev, "Can't get qdma controller irq.\n");
>> + return fsl_qdma->error_irq;
>> + }
>> +
>> + ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
>> + fsl_qdma_error_handler, 0,
>> + "qDMA error", fsl_qdma);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't register qDMA controller
>IRQ.\n");
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < fsl_qdma->block_number; i++) {
>> + sprintf(irq_name, "qdma-queue%d", i);
>> + fsl_qdma->queue_irq[i] =
>> + platform_get_irq_byname(pdev,
>irq_name);
>> +
>> + if (fsl_qdma->queue_irq[i] < 0) {
>> + dev_err(&pdev->dev,
>> + "Can't get qdma queue %d irq.\n", i);
>> + return fsl_qdma->queue_irq[i];
>> + }
>> +
>> + ret = devm_request_irq(&pdev->dev,
>> + fsl_qdma->queue_irq[i],
>> + fsl_qdma_queue_handler,
>> + 0,
>> + "qDMA queue",
>> + fsl_qdma);
>> + if (ret) {
>> + dev_err(&pdev->dev,
>> + "Can't register qDMA queue
>IRQ.\n");
>> + return ret;
>> + }
>> +
>> + cpu = i % num_online_cpus();
>> + ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
>> + get_cpu_mask(cpu));
>> + if (ret) {
>> + dev_err(&pdev->dev,
>> + "Can't set cpu %d affinity to
>IRQ %d.\n",
>> + cpu,
>> + fsl_qdma->queue_irq[i]);
>> + return ret;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void fsl_qdma_irq_exit(struct platform_device *pdev,
>> + struct fsl_qdma_engine *fsl_qdma)
>> +{
>> + int i;
>> +
>> + devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
>> + for (i = 0; i < fsl_qdma->block_number; i++)
>> + devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[i],
>fsl_qdma);
>> +}
>> +
>> +static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
>> +{
>> + u32 reg;
>> + int i, j, ret;
>> + struct fsl_qdma_queue *temp;
>> + void __iomem *status = fsl_qdma->status_base;
>> + void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
>> + struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
>> +
>> + /* Try to halt the qDMA engine first. */
>> + ret = fsl_qdma_halt(fsl_qdma);
>> + if (ret) {
>> + dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
>> + return ret;
>> + }
>> +
>> + for (i = 0; i < fsl_qdma->block_number; i++) {
>> + /*
>> + * Clear the command queue interrupt detect register
>for
>> + * all queues.
>> + */
>> +
>> + block = fsl_qdma->block_base +
>> + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
>> + qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
>> + block + FSL_QDMA_BCQIDR(0));
>> + }
>> +
>> + for (j = 0; j < fsl_qdma->block_number; j++) {
>> + block = fsl_qdma->block_base +
>> + FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
>> + for (i = 0; i < fsl_qdma->n_queues; i++) {
>> + temp = fsl_queue + i + (j *
>fsl_qdma->n_queues);
>> + /*
>> + * Initialize Command Queue registers to
>> + * point to the first
>> + * command descriptor in memory.
>> + * Dequeue Pointer Address Registers
>> + * Enqueue Pointer Address Registers
>> + */
>> +
>> + qdma_writel(fsl_qdma, temp->bus_addr,
>> + block +
>FSL_QDMA_BCQDPA_SADDR(i));
>> + qdma_writel(fsl_qdma, temp->bus_addr,
>> + block +
>FSL_QDMA_BCQEPA_SADDR(i));
>> +
>> + /* Initialize the queue mode. */
>> + reg = FSL_QDMA_BCQMR_EN;
>> + reg |=
>FSL_QDMA_BCQMR_CD_THLD(ilog2(temp->n_cq) - 4);
>> + reg |=
>FSL_QDMA_BCQMR_CQ_SIZE(ilog2(temp->n_cq) - 6);
>> + qdma_writel(fsl_qdma, reg, block +
>FSL_QDMA_BCQMR(i));
>> + }
>> +
>> + /*
>> + * Workaround for erratum: ERR010812.
>> + * We must enable XOFF to avoid the enqueue rejection
>occurs.
>> + * Setting SQCCMR ENTER_WM to 0x20.
>> + */
>> +
>> + qdma_writel(fsl_qdma,
>FSL_QDMA_SQCCMR_ENTER_WM,
>> + block + FSL_QDMA_SQCCMR);
>> +
>> + /*
>> + * Initialize status queue registers to point to the first
>> + * command descriptor in memory.
>> + * Dequeue Pointer Address Registers
>> + * Enqueue Pointer Address Registers
>> + */
>> +
>> + qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
>> + block + FSL_QDMA_SQEPAR);
>> + qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
>> + block + FSL_QDMA_SQDPAR);
>> + /* Initialize status queue interrupt. */
>> + qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
>> + block + FSL_QDMA_BCQIER(0));
>> + qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
>> + FSL_QDMA_BSQICR_ICST(5) |
>0x8000,
>> + block + FSL_QDMA_BSQICR);
>> + qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
>> + FSL_QDMA_CQIER_TEIE,
>> + block + FSL_QDMA_CQIER);
>> +
>> + /* Initialize the status queue mode. */
>> + reg = FSL_QDMA_BSQMR_EN;
>> + reg |= FSL_QDMA_BSQMR_CQ_SIZE(ilog2
>> + (fsl_qdma->status[j]->n_cq) - 6);
>> +
>> + qdma_writel(fsl_qdma, reg, block +
>FSL_QDMA_BSQMR);
>> + reg = qdma_readl(fsl_qdma, block +
>FSL_QDMA_BSQMR);
>> + }
>> +
>> + /* Initialize controller interrupt register. */
>> + qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status +
>FSL_QDMA_DEDR);
>> + qdma_writel(fsl_qdma, FSL_QDMA_DEIER_CLEAR, status +
>FSL_QDMA_DEIER);
>> +
>> + reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
>> + reg &= ~FSL_QDMA_DMR_DQD;
>> + qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
>> +
>> + return 0;
>> +}
>> +
>> +static struct dma_async_tx_descriptor *
>> +fsl_qdma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst,
>> + dma_addr_t src, size_t len, unsigned long flags)
>> +{
>> + struct fsl_qdma_comp *fsl_comp;
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> +
>> + fsl_comp = fsl_qdma_request_enqueue_desc(fsl_chan);
>> +
>> + if (!fsl_comp)
>> + return NULL;
>> +
>> + fsl_qdma_comp_fill_memcpy(fsl_comp, dst, src, len);
>> +
>> + return vchan_tx_prep(&fsl_chan->vchan, &fsl_comp->vdesc, flags);
>> +}
>> +
>> +static void fsl_qdma_enqueue_desc(struct fsl_qdma_chan *fsl_chan)
>> +{
>> + u32 reg;
>> + struct virt_dma_desc *vdesc;
>> + struct fsl_qdma_comp *fsl_comp;
>> + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
>> + void __iomem *block = fsl_queue->block_base;
>> +
>> + reg = qdma_readl(fsl_chan->qdma, block +
>FSL_QDMA_BCQSR(fsl_queue->id));
>> + if (reg & (FSL_QDMA_BCQSR_QF | FSL_QDMA_BCQSR_XOFF))
>> + return;
>> + vdesc = vchan_next_desc(&fsl_chan->vchan);
>> + if (!vdesc)
>> + return;
>> + list_del(&vdesc->node);
>> + fsl_comp = to_fsl_qdma_comp(vdesc);
>> +
>> + memcpy(fsl_queue->virt_head++,
>> + fsl_comp->virt_addr, sizeof(struct fsl_qdma_format));
>> + if (fsl_queue->virt_head == fsl_queue->cq + fsl_queue->n_cq)
>> + fsl_queue->virt_head = fsl_queue->cq;
>> +
>> + list_add_tail(&fsl_comp->list, &fsl_queue->comp_used);
>> + barrier();
>> + reg = qdma_readl(fsl_chan->qdma, block +
>FSL_QDMA_BCQMR(fsl_queue->id));
>> + reg |= FSL_QDMA_BCQMR_EI;
>> + qdma_writel(fsl_chan->qdma, reg, block +
>FSL_QDMA_BCQMR(fsl_queue->id));
>> + fsl_chan->status = DMA_IN_PROGRESS;
>> +}
>> +
>> +static void fsl_qdma_free_desc(struct virt_dma_desc *vdesc)
>> +{
>> + unsigned long flags;
>> + struct fsl_qdma_comp *fsl_comp;
>> + struct fsl_qdma_queue *fsl_queue;
>> +
>> + fsl_comp = to_fsl_qdma_comp(vdesc);
>> + fsl_queue = fsl_comp->qchan->queue;
>> +
>> + spin_lock_irqsave(&fsl_queue->queue_lock, flags);
>> + list_add_tail(&fsl_comp->list, &fsl_queue->comp_free);
>> + spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
>> +}
>> +
>> +static void fsl_qdma_issue_pending(struct dma_chan *chan)
>> +{
>> + unsigned long flags;
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
>> +
>> + spin_lock_irqsave(&fsl_queue->queue_lock, flags);
>> + spin_lock(&fsl_chan->vchan.lock);
>> + if (vchan_issue_pending(&fsl_chan->vchan))
>> + fsl_qdma_enqueue_desc(fsl_chan);
>> + spin_unlock(&fsl_chan->vchan.lock);
>> + spin_unlock_irqrestore(&fsl_queue->queue_lock, flags);
>> +}
>> +
>> +static void fsl_qdma_synchronize(struct dma_chan *chan)
>> +{
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> +
>> + vchan_synchronize(&fsl_chan->vchan);
>> +}
>> +
>> +static int fsl_qdma_terminate_all(struct dma_chan *chan)
>> +{
>> + LIST_HEAD(head);
>> + unsigned long flags;
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> +
>> + spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
>> + vchan_get_all_descriptors(&fsl_chan->vchan, &head);
>> + spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
>> + vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
>> + return 0;
>> +}
>> +
>> +static int fsl_qdma_alloc_chan_resources(struct dma_chan *chan)
>> +{
>> + int ret;
>> + struct fsl_qdma_chan *fsl_chan = to_fsl_qdma_chan(chan);
>> + struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
>> + struct fsl_qdma_queue *fsl_queue = fsl_chan->queue;
>> +
>> + if (fsl_queue->comp_pool && fsl_queue->desc_pool)
>> + return fsl_qdma->desc_allocated;
>> +
>> + INIT_LIST_HEAD(&fsl_queue->comp_free);
>> +
>> + /*
>> + * The dma pool for queue command buffer
>> + */
>> + fsl_queue->comp_pool =
>> + dma_pool_create("comp_pool",
>> + chan->device->dev,
>> + FSL_QDMA_COMMAND_BUFFER_SIZE,
>> + 64, 0);
>> + if (!fsl_queue->comp_pool)
>> + return -ENOMEM;
>> +
>> + /*
>> + * The dma pool for Descriptor(SD/DD) buffer
>> + */
>> + fsl_queue->desc_pool =
>> + dma_pool_create("desc_pool",
>> + chan->device->dev,
>> + FSL_QDMA_DESCRIPTOR_BUFFER_SIZE,
>> + 32, 0);
>> + if (!fsl_queue->desc_pool)
>> + goto err_desc_pool;
>> +
>> + ret = fsl_qdma_pre_request_enqueue_desc(fsl_queue);
>> + if (ret) {
>> + dev_err(chan->device->dev,
>> + "failed to alloc dma buffer for S/G
>descriptor\n");
>> + goto err_mem;
>> + }
>> +
>> + fsl_qdma->desc_allocated++;
>> + return fsl_qdma->desc_allocated;
>> +
>> +err_mem:
>> + dma_pool_destroy(fsl_queue->desc_pool);
>> +err_desc_pool:
>> + dma_pool_destroy(fsl_queue->comp_pool);
>> + return -ENOMEM;
>> +}
>> +
>> +static int fsl_qdma_probe(struct platform_device *pdev)
>> +{
>> + int ret, i;
>> + int blk_num, blk_off;
>> + u32 len, chans, queues;
>> + struct resource *res;
>> + struct fsl_qdma_chan *fsl_chan;
>> + struct fsl_qdma_engine *fsl_qdma;
>> + struct device_node *np = pdev->dev.of_node;
>> +
>> + ret = of_property_read_u32(np, "dma-channels", &chans);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get dma-channels.\n");
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(np, "block-offset", &blk_off);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get block-offset.\n");
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(np, "block-number", &blk_num);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get block-number.\n");
>> + return ret;
>> + }
>> +
>> + blk_num = min_t(int, blk_num, num_online_cpus());
>> +
>> + len = sizeof(*fsl_qdma);
>> + fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
>> + if (!fsl_qdma)
>> + return -ENOMEM;
>> +
>> + len = sizeof(*fsl_chan) * chans;
>> + fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
>> + if (!fsl_qdma->chans)
>> + return -ENOMEM;
>> +
>> + len = sizeof(struct fsl_qdma_queue *) * blk_num;
>> + fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
>> + if (!fsl_qdma->status)
>> + return -ENOMEM;
>> +
>> + len = sizeof(int) * blk_num;
>> + fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len,
>GFP_KERNEL);
>> + if (!fsl_qdma->queue_irq)
>> + return -ENOMEM;
>> +
>> + ret = of_property_read_u32(np, "fsl,dma-queues", &queues);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't get queues.\n");
>> + return ret;
>> + }
>> +
>> + fsl_qdma->desc_allocated = 0;
>> + fsl_qdma->n_chans = chans;
>> + fsl_qdma->n_queues = queues;
>> + fsl_qdma->block_number = blk_num;
>> + fsl_qdma->block_offset = blk_off;
>> +
>> + mutex_init(&fsl_qdma->fsl_qdma_mutex);
>> +
>> + for (i = 0; i < fsl_qdma->block_number; i++) {
>> + fsl_qdma->status[i] =
>fsl_qdma_prep_status_queue(pdev);
>> + if (!fsl_qdma->status[i])
>> + return -ENOMEM;
>> + }
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + fsl_qdma->ctrl_base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(fsl_qdma->ctrl_base))
>> + return PTR_ERR(fsl_qdma->ctrl_base);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> + fsl_qdma->status_base = devm_ioremap_resource(&pdev->dev,
>res);
>> + if (IS_ERR(fsl_qdma->status_base))
>> + return PTR_ERR(fsl_qdma->status_base);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
>> + fsl_qdma->block_base = devm_ioremap_resource(&pdev->dev,
>res);
>> + if (IS_ERR(fsl_qdma->block_base))
>> + return PTR_ERR(fsl_qdma->block_base);
>> + fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev,
>fsl_qdma);
>> + if (!fsl_qdma->queue)
>> + return -ENOMEM;
>> +
>> + ret = fsl_qdma_irq_init(pdev, fsl_qdma);
>> + if (ret)
>> + return ret;
>> +
>> + fsl_qdma->irq_base = platform_get_irq_byname(pdev,
>"qdma-queue0");
>> + fsl_qdma->feature = of_property_read_bool(np, "big-endian");
>> + INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
>> +
>> + for (i = 0; i < fsl_qdma->n_chans; i++) {
>> + struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
>> +
>> + fsl_chan->qdma = fsl_qdma;
>> + fsl_chan->queue = fsl_qdma->queue + i %
>(fsl_qdma->n_queues *
>> +
>fsl_qdma->block_number);
>> + fsl_chan->vchan.desc_free = fsl_qdma_free_desc;
>> + vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
>> + }
>> +
>> + dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
>> +
>> + fsl_qdma->dma_dev.dev = &pdev->dev;
>> + fsl_qdma->dma_dev.device_free_chan_resources =
>> + fsl_qdma_free_chan_resources;
>> + fsl_qdma->dma_dev.device_alloc_chan_resources =
>> + fsl_qdma_alloc_chan_resources;
>> + fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
>> + fsl_qdma->dma_dev.device_prep_dma_memcpy =
>fsl_qdma_prep_memcpy;
>> + fsl_qdma->dma_dev.device_issue_pending =
>fsl_qdma_issue_pending;
>> + fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
>> + fsl_qdma->dma_dev.device_terminate_all =
>fsl_qdma_terminate_all;
>> +
>> + dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
>> +
>> + platform_set_drvdata(pdev, fsl_qdma);
>> +
>> + ret = dma_async_device_register(&fsl_qdma->dma_dev);
>> + if (ret) {
>> + dev_err(&pdev->dev,
>> + "Can't register NXP Layerscape qDMA
>engine.\n");
>> + return ret;
>> + }
>> +
>> + ret = fsl_qdma_reg_init(fsl_qdma);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Can't Initialize the qDMA
>engine.\n");
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void fsl_qdma_cleanup_vchan(struct dma_device *dmadev)
>> +{
>> + struct fsl_qdma_chan *chan, *_chan;
>> +
>> + list_for_each_entry_safe(chan, _chan,
>> + &dmadev->channels,
>vchan.chan.device_node) {
>> + list_del(&chan->vchan.chan.device_node);
>> + tasklet_kill(&chan->vchan.task);
>> + }
>> +}
>> +
>> +static int fsl_qdma_remove(struct platform_device *pdev)
>> +{
>> + int i;
>> + struct fsl_qdma_queue *status;
>> + struct device_node *np = pdev->dev.of_node;
>> + struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
>> +
>> + fsl_qdma_irq_exit(pdev, fsl_qdma);
>> + fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
>> + of_dma_controller_free(np);
>> + dma_async_device_unregister(&fsl_qdma->dma_dev);
>> +
>> + for (i = 0; i < fsl_qdma->block_number; i++) {
>> + status = fsl_qdma->status[i];
>> + dma_free_coherent(&pdev->dev, sizeof(struct
>fsl_qdma_format) *
>> + status->n_cq, status->cq,
>status->bus_addr);
>> + }
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id fsl_qdma_dt_ids[] = {
>> + { .compatible = "fsl,ls1021a-qdma", },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, fsl_qdma_dt_ids);
>> +
>> +static struct platform_driver fsl_qdma_driver = {
>> + .driver = {
>> + .name = "fsl-qdma",
>> + .of_match_table = fsl_qdma_dt_ids,
>> + },
>> + .probe = fsl_qdma_probe,
>> + .remove = fsl_qdma_remove,
>> +};
>> +
>> +module_platform_driver(fsl_qdma_driver);
>> +
>> +MODULE_ALIAS("platform:fsl-qdma");
>> +MODULE_DESCRIPTION("NXP Layerscape qDMA engine driver");
>> --
>> 1.7.1
>>
^ permalink raw reply
* [PATCH v7 6/6] arm64: dts: add LX2160ARDB board support
From: Vabhav Sharma @ 2018-10-29 8:58 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Horia Geanta, Udit Kumar, Priyanka Jain,
Pankaj Bansal, Ying Zhang, linux@armlinux.org.uk,
adrian.hunter@intel.com, Varun Sethi, Vabhav Sharma, Sriram Dash,
Ran Wang, Yinbo Zhu
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 119 ++++++++++++++++++++++
2 files changed, 120 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18ad..445b72b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..6481e5f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160ARDB
+//
+// Copyright 2018 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "NXP Layerscape LX2160ARDB";
+ compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "MC34717-3.3VSB";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+
+ power-monitor@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+ };
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ vcc-supply = <&sb_3v3>;
+ };
+
+ temperature-sensor@4d {
+ compatible = "nxp,sa56004";
+ reg = <0x4d>;
+ vcc-supply = <&sb_3v3>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ // IRQ10_B
+ interrupts = <0 150 0x4>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v7 5/6] arm64: dts: add QorIQ LX2160A SoC support
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Yogesh Narayan Gaur, Horia Geanta,
Udit Kumar, Priyanka Jain, Pankaj Bansal, Ying Zhang,
linux@armlinux.org.uk, adrian.hunter@intel.com, Ramneek Mehresh,
Varun Sethi, Vabhav Sharma, Nipun Gupta, Sriram Dash, Ran Wang,
Yinbo Zhu
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++++++
1 file changed, 766 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
index 0000000..a79f5c1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -0,0 +1,766 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+ compatible = "fsl,lx2160a";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // 8 clusters having 2 Cortex-A72 cores each
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x0>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x1>;
+ clocks = <&clockgen 1 0>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x100>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x101>;
+ clocks = <&clockgen 1 1>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x200>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x201>;
+ clocks = <&clockgen 1 2>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster2_l2>;
+ };
+
+ cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x300>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x301>;
+ clocks = <&clockgen 1 3>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster3_l2>;
+ };
+
+ cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x400>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@401 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x401>;
+ clocks = <&clockgen 1 4>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster4_l2>;
+ };
+
+ cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x500>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@501 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x501>;
+ clocks = <&clockgen 1 5>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster5_l2>;
+ };
+
+ cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x600>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@601 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x601>;
+ clocks = <&clockgen 1 6>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster6_l2>;
+ };
+
+ cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x700>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cpu@701 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ enable-method = "psci";
+ reg = <0x701>;
+ clocks = <&clockgen 1 7>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ i-cache-size = <0xC000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <192>;
+ next-level-cache = <&cluster7_l2>;
+ };
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster2_l2: l2-cache2 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster3_l2: l2-cache3 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster4_l2: l2-cache4 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster5_l2: l2-cache5 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster6_l2: l2-cache6 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+
+ cluster7_l2: l2-cache7 {
+ compatible = "cache";
+ cache-size = <0x100000>;
+ cache-line-size = <64>;
+ cache-sets = <1024>;
+ cache-level = <2>;
+ };
+ };
+
+ gic: interrupt-controller@6000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
+ <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
+ // SGI_base)
+ <0x0 0x0c0c0000 0 0x2000>, // GICC
+ <0x0 0x0c0d0000 0 0x1000>, // GICH
+ <0x0 0x0c0e0000 0 0x20000>; // GICV
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ its: gic-its@6020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0x6020000 0 0x20000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ memory@80000000 {
+ // DRAM space - 1, size : 2 GB DRAM
+ device_type = "memory";
+ reg = <0x00000000 0x80000000 0 0x80000000>;
+ };
+
+ ddr1: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ ddr2: memory-controller@1090000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1090000 0x0 0x1000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ little-endian;
+ };
+
+ // One clock unit-sysclk node which bootloader require during DT fix-up
+ sysclk: sysclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>; // fixed up by bootloader
+ clock-output-names = "sysclk";
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ crypto: crypto@8000000 {
+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+ fsl,sec-era = <10>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x8000000 0x100000>;
+ reg = <0x00 0x8000000 0x0 0x100000>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+
+ sec_jr0: jr@10000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x10000 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr@20000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x20000 0x10000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr@30000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x30000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr3: jr@40000 {
+ compatible = "fsl,sec-v5.0-job-ring",
+ "fsl,sec-v4.0-job-ring";
+ reg = <0x40000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ clockgen: clock-controller@1300000 {
+ compatible = "fsl,lx2160a-clockgen";
+ reg = <0 0x1300000 0 0xa0000>;
+ #clock-cells = <2>;
+ clocks = <&sysclk>;
+ };
+
+ dcfg: syscon@1e00000 {
+ compatible = "fsl,lx2160a-dcfg", "syscon";
+ reg = <0x0 0x1e00000 0x0 0x10000>;
+ little-endian;
+ };
+
+ i2c0: i2c@2000000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2010000 0x0 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2020000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2030000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2030000 0x0 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2040000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2040000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2050000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2050000 0x0 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@2060000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2060000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2070000 {
+ compatible = "fsl,vf610-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x2070000 0x0 0x10000>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "i2c";
+ clocks = <&clockgen 4 7>;
+ status = "disabled";
+ };
+
+ esdhc0: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ esdhc1: esdhc@2150000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2150000 0x0 0x10000>;
+ interrupts = <0 63 0x4>; /* Level high type */
+ clocks = <&clockgen 4 1>;
+ voltage-ranges = <1800 1800 3300 3300>;
+ sdhci,auto-cmd12;
+ broken-cd;
+ little-endian;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ uart0: serial@21c0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart1: serial@21d0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart2: serial@21e0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ uart3: serial@21f0000 {
+ compatible = "arm,sbsa-uart","arm,pl011";
+ reg = <0x0 0x21f0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2320000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2320000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-sec = <30>;
+ };
+
+ usb0: usb@3100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ usb1: usb@3110000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "host";
+ snps,quirk-frame-length-adjustment = <0x20>;
+ snps,dis_rxdet_inp3_quirk;
+ status = "disabled";
+ };
+
+ smmu: iommu@5000000 {
+ compatible = "arm,mmu-500";
+ reg = <0 0x5000000 0 0x800000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <14>;
+ // global secure fault
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ // combined secure
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ // global non-secure fault
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ // combined non-secure
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ // performance counter interrupts 0-9
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
+ // per context interrupt, 64 interrupts
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v7 4/6] clk: qoriq: Add clockgen support for lx2160a
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Yogesh Narayan Gaur, Andy Tang,
Udit Kumar, Pankaj Bansal, linux@armlinux.org.uk,
adrian.hunter@intel.com, Varun Sethi, Vabhav Sharma
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/clk/clk-qoriq.c | 12 ++++++++++++
drivers/cpufreq/qoriq-cpufreq.c | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index e152bfb..99675de 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_VER3 | CG_LITTLE_ENDIAN,
},
{
+ .compat = "fsl,lx2160a-clockgen",
+ .cmux_groups = {
+ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+ },
+ .cmux_to_group = {
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
+ },
+ .pll_mask = 0x37,
+ .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+ },
+ {
.compat = "fsl,p2041-clockgen",
.guts_compat = "fsl,qoriq-device-config-1.0",
.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
/* Legacy nodes */
CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = {
{ .compatible = "fsl,ls1046a-clockgen", },
{ .compatible = "fsl,ls1088a-clockgen", },
{ .compatible = "fsl,ls2080a-clockgen", },
+ { .compatible = "fsl,lx2160a-clockgen", },
{ .compatible = "fsl,p4080-clockgen", },
{ .compatible = "fsl,qoriq-clockgen-1.0", },
{ .compatible = "fsl,qoriq-clockgen-2.0", },
--
2.7.4
^ permalink raw reply related
* [PATCH v7 3/6] clk: qoriq: increase array size of cmux_to_group
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Yogesh Narayan Gaur, Udit Kumar,
Pankaj Bansal, linux@armlinux.org.uk, adrian.hunter@intel.com,
Varun Sethi, Vabhav Sharma
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Increase size of cmux_to_group array, to accomdate entry of
-1 termination.
Added -1, terminated, entry for 4080_cmux_grpX.
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
---
drivers/clk/clk-qoriq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..e152bfb 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
const struct clockgen_muxinfo *cmux_groups[2];
const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
void (*init_periph)(struct clockgen *cg);
- int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
+ int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
u32 pll_mask; /* 1 << n bit set if PLL n is valid */
u32 flags; /* CG_xxx */
};
@@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
&p4080_cmux_grp1, &p4080_cmux_grp2
},
.cmux_to_group = {
- 0, 0, 0, 0, 1, 1, 1, 1
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
},
.pll_mask = 0x1f,
},
--
2.7.4
^ permalink raw reply related
* [PATCH v7 2/6] soc/fsl/guts: Add definition for LX2160A
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Udit Kumar, Pankaj Bansal,
linux@armlinux.org.uk, adrian.hunter@intel.com, Varun Sethi,
Vabhav Sharma, Yinbo Zhu
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160 and SoC die
attribute definition for LX2160A
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
---
drivers/soc/fsl/guts.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..bcab1ee 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -100,6 +100,11 @@ static const struct fsl_soc_die_attr fsl_soc_die[] = {
.svr = 0x87000000,
.mask = 0xfff70000,
},
+ /* Die: LX2160A, SoC: LX2160A/LX2120A/LX2080A */
+ { .die = "LX2160A",
+ .svr = 0x87360000,
+ .mask = 0xff3f0000,
+ },
{ },
};
@@ -222,6 +227,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1088a-dcfg", },
{ .compatible = "fsl,ls1012a-dcfg", },
{ .compatible = "fsl,ls1046a-dcfg", },
+ { .compatible = "fsl,lx2160a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
--
2.7.4
^ permalink raw reply related
* [PATCH v7 1/6] dt-bindings: arm64: add compatible for LX2160A
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Udit Kumar, Pankaj Bansal,
linux@armlinux.org.uk, adrian.hunter@intel.com, Varun Sethi,
Vabhav Sharma
In-Reply-To: <1540759926-3641-1-git-send-email-vabhav.sharma@nxp.com>
Add compatible for LX2160A SoC,QDS and RDB board
Add lx2160a compatible for clockgen and dcfg
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/fsl.txt | 14 +++++++++++++-
Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 8a1baa2..71adce2 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -130,7 +130,7 @@ core start address and release the secondary core from holdoff and startup.
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
- ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
+ ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a.
- reg : should contain base address and length of DCFG memory-mapped registers
@@ -222,3 +222,15 @@ Required root node properties:
LS2088A ARMv8 based RDB Board
Required root node properties:
- compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
+
+LX2160A SoC
+Required root node properties:
+ - compatible = "fsl,lx2160a";
+
+LX2160A ARMv8 based QDS Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
+
+LX2160A ARMv8 based RDB Board
+Required root node properties:
+ - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 97f46ad..3fb9995 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -37,6 +37,7 @@ Required properties:
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
+ * "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
--
2.7.4
^ permalink raw reply related
* [PATCH v7 0/6] arm64: dts: NXP: add basic dts file for LX2160A SoC
From: Vabhav Sharma @ 2018-10-29 8:57 UTC (permalink / raw)
To: sudeep.holla@arm.com, oss@buserror.net,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
sboyd@kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel-owner@vger.kernel.org, catalin.marinas@arm.com,
will.deacon@arm.com, gregkh@linuxfoundation.org, arnd@arndb.de,
kstewart@linuxfoundation.org, yamada.masahiro@socionext.com,
Leo Li, shawnguo@kernel.org
Cc: ulf.hansson@linaro.org, Udit Kumar, Pankaj Bansal,
linux@armlinux.org.uk, adrian.hunter@intel.com, Varun Sethi,
Vabhav Sharma
Changes for v7:
- Comment for clock-frequency property fixed by bootloader
Changes for v6:
- Added comment for clock unit-sysclk node name in SoC device tree
Changes for v5:
- Updated temperature sensor regulator name in board device tree
- Sorted nodes alphabatically and unit-address in SoC/board device tree
- Identation, new line update in SoC/board device tree
- Updated nodes name as per DT spec generic name recommendation in SoC DT
- Updated macro define for interrupt/gpio property
- Updated i2c node property name scl-gpio
- Removed device_type property except cpu/memory node
- Added esdhc controller nodes in SoC/RDB board device tree
- Added aliases for uart/crypto nodes
- Add SoC die attribute definition for LX2160A
Changes for v4:
- Updated bindings for lx2160a clockgen and dcfg
- Modified commit message for lx2160a clockgen changes
- Updated interrupt property with macro definition
- Added required enable-method property to each core node with psci value
- Removed unused node syscon in device tree
- Removed blank lines in device tree fsl-lx2160a.dtsi
- Updated uart node compatible sbsa-uart first
- Added and defined vcc-supply property to temperature sensor node in
device tree fsl-lx2160a-rdb.dts
Changes for v3:
-Split clockgen support patch into below two patches:
- a)Updated array size of cmux_to_group[] with NUM_CMUX+1 to include -1
terminator and p4080 cmux_to_group[] array with -1 terminator
- b)Add clockgen support for lx2160a
Changes for v2:
- Modified cmux_to_group array to include -1 terminator
- Revert NUM_CMUX to original value 8 from 16
- Remove â LX2160A is 16 core, so modified value for NUM_CMUXX
in patch "[PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
lx2160a" description
- Populated cache properties for L1 and L2 cache in lx2160a device-tree.
- Removed reboot node from lx2160a device-tree as PSCI is implemented.
- Removed incorrect comment for timer node interrupt property in
lx2160a device-tree.
- Modified pmu node compatible property from "arm,armv8-pmuv3" to
"arm,cortex-a72-pmu" in lx2160a device-tree
- Non-standard aliases removed in lx2160a rdb board device-tree
- Updated i2c child nodes to generic name in lx2160a rdb device-tree.
Changes for v1:
- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
(Reference design board)
Vabhav Sharma (4):
dt-bindings: arm64: add compatible for LX2160A
soc/fsl/guts: Add definition for LX2160A
arm64: dts: add QorIQ LX2160A SoC support
arm64: dts: add LX2160ARDB board support
Yogesh Gaur (2):
clk: qoriq: increase array size of cmux_to_group
clk: qoriq: Add clockgen support for lx2160a
Documentation/devicetree/bindings/arm/fsl.txt | 14 +-
.../devicetree/bindings/clock/qoriq-clock.txt | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 119 ++++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766 +++++++++++++++++++++
drivers/clk/clk-qoriq.c | 16 +-
drivers/cpufreq/qoriq-cpufreq.c | 1 +
drivers/soc/fsl/guts.c | 6 +
8 files changed, 921 insertions(+), 3 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
--
2.7.4
^ permalink raw reply
* RE: [PATCH v6 5/6] arm64: dts: add QorIQ LX2160A SoC support
From: Vabhav Sharma @ 2018-10-29 8:56 UTC (permalink / raw)
To: Leo Li
Cc: Mark Rutland, Kate Stewart, Ulf Hansson, Yogesh Narayan Gaur,
linux-kernel-owner@vger.kernel.org, Catalin Marinas,
Michael Turquette, Will Deacon, Adrian Hunter,
yamada.masahiro@socionext.com, Sriram Dash, linux-clk,
Horia Geanta, Pankaj Bansal, Udit Kumar, Russell King,
Priyanka Jain, Viresh Kumar, Yinbo Zhu,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Arnd Bergmann, linux-pm@vger.kernel.org, linuxppc-dev, Scott Wood,
Rob Herring, Varun Sethi, Nipun Gupta,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Ramneek Mehresh, sboyd@kernel.org, Greg Kroah-Hartman, Ying Zhang,
Rafael J. Wysocki, lkml, Sudeep Holla, Ran Wang, Shawn Guo
In-Reply-To: <CADRPPNS4brR5f3PiAujLQSy3kpniaR+pzKRn0LhBSSsawJ-vag@mail.gmail.com>
> -----Original Message-----
> From: Li Yang <leoyang.li@nxp.com>
> Sent: Friday, October 26, 2018 1:19 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: Sudeep Holla <sudeep.holla@arm.com>; Scott Wood
> <oss@buserror.net>; lkml <linux-kernel@vger.kernel.org>; open list:OPEN
> FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <devicetree@vger.kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark
> Rutland <mark.rutland@arm.com>; linuxppc-dev <linuxppc-
> dev@lists.ozlabs.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; Michael Turquette
> <mturquette@baylibre.com>; sboyd@kernel.org; Rafael J. Wysocki
> <rjw@rjwysocki.net>; Viresh Kumar <viresh.kumar@linaro.org>; linux-clk
> <linux-clk@vger.kernel.org>; linux-pm@vger.kernel.org; linux-kernel-
> owner@vger.kernel.org; Catalin Marinas <catalin.marinas@arm.com>; Will
> Deacon <will.deacon@arm.com>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>; Kate
> Stewart <kstewart@linuxfoundation.org>; yamada.masahiro@socionext.com;
> Shawn Guo <shawnguo@kernel.org>; Russell King <linux@armlinux.org.uk>;
> Adrian Hunter <adrian.hunter@intel.com>; Ulf Hansson
> <ulf.hansson@linaro.org>; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar
> <udit.kumar@nxp.com>; Pankaj Bansal <pankaj.bansal@nxp.com>; Ramneek
> Mehresh <ramneek.mehresh@nxp.com>; Ying Zhang
> <ying.zhang22455@nxp.com>; Nipun Gupta <nipun.gupta@nxp.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Yogesh Narayan Gaur
> <yogeshnarayan.gaur@nxp.com>; Sriram Dash <sriram.dash@nxp.com>;
> Horia Geanta <horia.geanta@nxp.com>; Ran Wang <ran.wang_1@nxp.com>;
> Yinbo Zhu <yinbo.zhu@nxp.com>
> Subject: Re: [PATCH v6 5/6] arm64: dts: add QorIQ LX2160A SoC support
>
> On Thu, Oct 25, 2018 at 2:03 AM Vabhav Sharma <vabhav.sharma@nxp.com>
> wrote:
> >
> > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> >
> > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor
> > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8
> > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011
> > SBSA UARTs etc.
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > Signed-off-by: Horia Geanta <horia.geanta@nxp.com>
> > Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> > Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 766
> > +++++++++++++++++++++++++
> > 1 file changed, 766 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > new file mode 100644
> > index 0000000..9fcfd48
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -0,0 +1,766 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree
> > +Include file for Layerscape-LX2160A family SoC.
> > +//
> > +// Copyright 2018 NXP
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/memreserve/ 0x80000000 0x00010000;
> > +
> > +/ {
> > + compatible = "fsl,lx2160a";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + // 8 clusters having 2 Cortex-A72 cores each
> > + cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x0>;
> > + clocks = <&clockgen 1 0>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x1>;
> > + clocks = <&clockgen 1 0>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster0_l2>;
> > + };
> > +
> > + cpu@100 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x100>;
> > + clocks = <&clockgen 1 1>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cpu@101 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x101>;
> > + clocks = <&clockgen 1 1>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster1_l2>;
> > + };
> > +
> > + cpu@200 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x200>;
> > + clocks = <&clockgen 1 2>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster2_l2>;
> > + };
> > +
> > + cpu@201 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x201>;
> > + clocks = <&clockgen 1 2>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster2_l2>;
> > + };
> > +
> > + cpu@300 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x300>;
> > + clocks = <&clockgen 1 3>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster3_l2>;
> > + };
> > +
> > + cpu@301 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x301>;
> > + clocks = <&clockgen 1 3>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster3_l2>;
> > + };
> > +
> > + cpu@400 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x400>;
> > + clocks = <&clockgen 1 4>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster4_l2>;
> > + };
> > +
> > + cpu@401 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x401>;
> > + clocks = <&clockgen 1 4>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster4_l2>;
> > + };
> > +
> > + cpu@500 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x500>;
> > + clocks = <&clockgen 1 5>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster5_l2>;
> > + };
> > +
> > + cpu@501 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x501>;
> > + clocks = <&clockgen 1 5>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster5_l2>;
> > + };
> > +
> > + cpu@600 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x600>;
> > + clocks = <&clockgen 1 6>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster6_l2>;
> > + };
> > +
> > + cpu@601 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x601>;
> > + clocks = <&clockgen 1 6>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster6_l2>;
> > + };
> > +
> > + cpu@700 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x700>;
> > + clocks = <&clockgen 1 7>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster7_l2>;
> > + };
> > +
> > + cpu@701 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a72";
> > + enable-method = "psci";
> > + reg = <0x701>;
> > + clocks = <&clockgen 1 7>;
> > + d-cache-size = <0x8000>;
> > + d-cache-line-size = <64>;
> > + d-cache-sets = <128>;
> > + i-cache-size = <0xC000>;
> > + i-cache-line-size = <64>;
> > + i-cache-sets = <192>;
> > + next-level-cache = <&cluster7_l2>;
> > + };
> > +
> > + cluster0_l2: l2-cache0 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster1_l2: l2-cache1 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster2_l2: l2-cache2 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster3_l2: l2-cache3 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster4_l2: l2-cache4 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster5_l2: l2-cache5 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster6_l2: l2-cache6 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > +
> > + cluster7_l2: l2-cache7 {
> > + compatible = "cache";
> > + cache-size = <0x100000>;
> > + cache-line-size = <64>;
> > + cache-sets = <1024>;
> > + cache-level = <2>;
> > + };
> > + };
> > +
> > + gic: interrupt-controller@6000000 {
> > + compatible = "arm,gic-v3";
> > + reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
> > + <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
> > + // SGI_base)
> > + <0x0 0x0c0c0000 0 0x2000>, // GICC
> > + <0x0 0x0c0d0000 0 0x1000>, // GICH
> > + <0x0 0x0c0e0000 0 0x20000>; // GICV
> > + #interrupt-cells = <3>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + interrupt-controller;
> > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + its: gic-its@6020000 {
> > + compatible = "arm,gic-v3-its";
> > + msi-controller;
> > + reg = <0x0 0x6020000 0 0x20000>;
> > + };
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a72-pmu";
> > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + memory@80000000 {
> > + // DRAM space - 1, size : 2 GB DRAM
> > + device_type = "memory";
> > + reg = <0x00000000 0x80000000 0 0x80000000>;
> > + };
> > +
> > + ddr1: memory-controller@1080000 {
> > + compatible = "fsl,qoriq-memory-controller";
> > + reg = <0x0 0x1080000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + little-endian;
> > + };
> > +
> > + ddr2: memory-controller@1090000 {
> > + compatible = "fsl,qoriq-memory-controller";
> > + reg = <0x0 0x1090000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> > + little-endian;
> > + };
> > +
> > + // One clock unit-sysclk node which bootloader require during DT fix-
> up
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
>
> Would be even better if you can add a comment "fixed up by bootloader"
> to the property too.
Ok
>
> > + clock-output-names = "sysclk";
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + crypto: crypto@8000000 {
> > + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
> > + fsl,sec-era = <10>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x00 0x8000000 0x100000>;
> > + reg = <0x00 0x8000000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > + status = "disabled";
> > +
> > + sec_jr0: jr@10000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x10000 0x10000>;
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr1: jr@20000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x20000 0x10000>;
> > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr2: jr@30000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x30000 0x10000>;
> > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > + sec_jr3: jr@40000 {
> > + compatible = "fsl,sec-v5.0-job-ring",
> > + "fsl,sec-v4.0-job-ring";
> > + reg = <0x40000 0x10000>;
> > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > + };
> > +
> > + clockgen: clock-controller@1300000 {
> > + compatible = "fsl,lx2160a-clockgen";
> > + reg = <0 0x1300000 0 0xa0000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + };
> > +
> > + dcfg: syscon@1e00000 {
> > + compatible = "fsl,lx2160a-dcfg", "syscon";
> > + reg = <0x0 0x1e00000 0x0 0x10000>;
> > + little-endian;
> > + };
> > +
> > + i2c0: i2c@2000000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2000000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@2010000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2010000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c2: i2c@2020000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2020000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c3: i2c@2030000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2030000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c4: i2c@2040000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2040000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + i2c5: i2c@2050000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2050000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c6: i2c@2060000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2060000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + i2c7: i2c@2070000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2070000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "i2c";
> > + clocks = <&clockgen 4 7>;
> > + status = "disabled";
> > + };
> > +
> > + esdhc0: esdhc@2140000 {
> > + compatible = "fsl,esdhc";
> > + reg = <0x0 0x2140000 0x0 0x10000>;
> > + interrupts = <0 28 0x4>; /* Level high type */
> > + clocks = <&clockgen 4 1>;
> > + voltage-ranges = <1800 1800 3300 3300>;
> > + sdhci,auto-cmd12;
> > + little-endian;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + esdhc1: esdhc@2150000 {
> > + compatible = "fsl,esdhc";
> > + reg = <0x0 0x2150000 0x0 0x10000>;
> > + interrupts = <0 63 0x4>; /* Level high type */
> > + clocks = <&clockgen 4 1>;
> > + voltage-ranges = <1800 1800 3300 3300>;
> > + sdhci,auto-cmd12;
> > + broken-cd;
> > + little-endian;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart0: serial@21c0000 {
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21c0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@21d0000 {
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21d0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@21e0000 {
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21e0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@21f0000 {
> > + compatible = "arm,sbsa-uart","arm,pl011";
> > + reg = <0x0 0x21f0000 0x0 0x1000>;
> > + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> > + current-speed = <115200>;
> > + status = "disabled";
> > + };
> > +
> > + gpio0: gpio@2300000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2300000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio1: gpio@2310000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2310000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio2: gpio@2320000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2320000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio3: gpio@2330000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2330000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + little-endian;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + watchdog@23a0000 {
> > + compatible = "arm,sbsa-gwdt";
> > + reg = <0x0 0x23a0000 0 0x1000>,
> > + <0x0 0x2390000 0 0x1000>;
> > + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > + timeout-sec = <30>;
> > + };
> > +
> > + usb0: usb@3100000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0x3100000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "host";
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,dis_rxdet_inp3_quirk;
> > + status = "disabled";
> > + };
> > +
> > + usb1: usb@3110000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x0 0x3110000 0x0 0x10000>;
> > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> > + dr_mode = "host";
> > + snps,quirk-frame-length-adjustment = <0x20>;
> > + snps,dis_rxdet_inp3_quirk;
> > + status = "disabled";
> > + };
> > +
> > + smmu: iommu@5000000 {
> > + compatible = "arm,mmu-500";
> > + reg = <0 0x5000000 0 0x800000>;
> > + #iommu-cells = <1>;
> > + #global-interrupts = <14>;
> > + // global secure fault
> > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> > + // combined secure
> > + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> > + // global non-secure fault
> > + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> > + // combined non-secure
> > + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> > + // performance counter interrupts 0-9
> > + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
> > + // per context interrupt, 64 interrupts
> > + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
> > + dma-coherent;
> > + };
> > + };
> > +};
> > --
> > 2.7.4
> >
^ permalink raw reply
* RE: [PATCH 3/6] PCI: layerscape: Add the EP mode support
From: Xiaowei Bao @ 2018-10-29 2:35 UTC (permalink / raw)
To: Leo Li
Cc: Mark Rutland, Rob Herring, lorenzo.pieralisi@arm.com,
Arnd Bergmann, Roy Zang, Greg Kroah-Hartman, Kate Stewart,
niklas.cassel@axis.com, linux-pci@vger.kernel.org, lkml,
kishon@ti.com, M.h. Lian,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
cyrille.pitchen@free-electrons.com,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Philippe Ombredanne, Bjorn Helgaas, linuxppc-dev, Shawn Guo,
shawn.lin@rock-chips.com, Mingkai Hu
In-Reply-To: <CADRPPNRP5RORVr0O59=O-PhRRerirFkPeOmAcKq3pNumf4Mriw@mail.gmail.com>
-----Original Message-----
From: Li Yang <leoyang.li@nxp.com>
Sent: 2018年10月27日 4:29
To: Xiaowei Bao <xiaowei.bao@nxp.com>
Cc: Arnd Bergmann <arnd@arndb.de>; Rob Herring <robh@kernel.org>; Bjorn Helgaas <bhelgaas@google.com>; Mark Rutland <mark.rutland@arm.com>; Shawn Guo <shawnguo@kernel.org>; kishon@ti.com; lorenzo.pieralisi@arm.com; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; M.h. Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>; Kate Stewart <kstewart@linuxfoundation.org>; cyrille.pitchen@free-electrons.com; Philippe Ombredanne <pombredanne@nexb.com>; shawn.lin@rock-chips.com; niklas.cassel@axis.com; linux-pci@vger.kernel.org; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; lkml <linux-kernel@vger.kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; linuxppc-dev <linuxppc-dev@lists.ozlabs.org>
Subject: Re: [PATCH 3/6] PCI: layerscape: Add the EP mode support
On Fri, Oct 26, 2018 at 2:43 AM Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
>
>
>
> -----Original Message-----
> From: arndbergmann@gmail.com <arndbergmann@gmail.com> On Behalf Of
> Arnd Bergmann
> Sent: 2018年10月26日 15:01
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: Rob Herring <robh@kernel.org>; bhelgaas@google.com;
> mark.rutland@arm.com; shawnguo@kernel.org; Leo Li
> <leoyang.li@nxp.com>; kishon@ti.com; lorenzo.pieralisi@arm.com;
> gregkh@linuxfoundation.org; M.h. Lian <minghuan.lian@nxp.com>; Mingkai
> Hu <mingkai.hu@nxp.com>; Roy Zang <roy.zang@nxp.com>;
> kstewart@linuxfoundation.org; cyrille.pitchen@free-electrons.com;
> pombredanne@nexb.com; shawn.lin@rock-chips.com;
> niklas.cassel@axis.com; linux-pci@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH 3/6] PCI: layerscape: Add the EP mode support
>
> On 10/26/18, Xiaowei Bao <xiaowei.bao@nxp.com> wrote:
> > From: Rob Herring <robh@kernel.org>
> >> On Thu, Oct 25, 2018 at 07:08:58PM +0800, Xiaowei Bao wrote:
> >>> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
> >>> "fsl,ls2088a-pcie"
> >>> "fsl,ls1088a-pcie"
> >>> "fsl,ls1046a-pcie"
> >>> "fsl,ls1012a-pcie
> >>> + EP mode:
> >>> + "fsl,ls-pcie-ep"
> >>
> > > You need SoC specific compatibles for the same reasons as the RC.
> >
> > [Xiaowei Bao] I want to contains all layerscape platform use one
> > compatible if the PCIe controller work in EP mode.
>
> Do you mean only one of the SoCs that support RC mode has EP mode?
> I think you still need a SoC specific compatible as Rob explained, in case there will be a second one in the future.
>
> If you want to ensure that you don't have to update the device driver for each new chip that comes in when the EP mode is compatible, the way this is handled is to list multiple values in the compatible property, listing the first SoC that introduced the specific version of that IP block as the most generic type, e.g.
>
> copatible = "fsl,ls2088a-pcie-ep", "fsl,ls1012a-pcie-ep",
> "snps,dw-pcie-ep";
>
> For consistency, it probably is best to match each RC mode value with the corresponding EP mode string for each device that can support both (if there is more than one).
>
> Arnd
> [Xiaowei Bao] My mean is that the ls-pcie-ep compatibles will contain all layerscape SOCs of NXP, e.g: ls1046a-pcie-ep, fsl,ls2088a-pcie-ep, ls2088a-pcie-ep and so on, other layerscape SOCs have not test except the ls1046a, I think it is compatible if the new chip or other SOCs use the DW core, OK, I will discuss this issue internally, and reply to you later.
You can define a generic compatible string for the EP mode of all these platforms. But like Rob and Arnd mentioned, it is good to also define the SoC specific compatible strings just in case that we need special treatment for certain SoCs in the future.
Regards,
Leo
[Xiaowei Bao] Hi Leo, OK, I will add the SoC specific compatible strings in patch-v2, thanks a lot.
^ permalink raw reply
* Re: [PATCH 2/5] powerpc/futex: GUAP support for futex ops
From: Russell Currey @ 2018-10-29 1:08 UTC (permalink / raw)
To: LEROY Christophe; +Cc: mikey, linuxppc-dev, npiggin
In-Reply-To: <20181026183238.Horde.Qb6gGcTLnJI-ma8mXsMeBA1@messagerie.si.c-s.fr>
On Fri, 2018-10-26 at 18:32 +0200, LEROY Christophe wrote:
> Russell Currey <ruscur@russell.cc> a écrit :
>
> > Wrap the futex operations in GUAP locks and unlocks.
>
> Does it means futex doesn't work anymore once only patch 1 is
> applied
> ? If so, then you should split patch 1 in two parts and reorder
> patches so that guap can only be activated once all necessary
> changes
> are done. Otherwise the serie won't be bisectable
Yeah, I agree. I just wanted to remove some amount of breadth from
what already is one gigantic patch. Bisectability is more important
than that, however.
- Russell
>
> Christophe
>
> > Signed-off-by: Russell Currey <ruscur@russell.cc>
> > ---
> > arch/powerpc/include/asm/futex.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/powerpc/include/asm/futex.h
> > b/arch/powerpc/include/asm/futex.h
> > index 94542776a62d..3aed640ee9ef 100644
> > --- a/arch/powerpc/include/asm/futex.h
> > +++ b/arch/powerpc/include/asm/futex.h
> > @@ -35,6 +35,7 @@ static inline int
> > arch_futex_atomic_op_inuser(int
> > op, int oparg, int *oval,
> > {
> > int oldval = 0, ret;
> >
> > + unlock_user_access();
> > pagefault_disable();
> >
> > switch (op) {
> > @@ -62,6 +63,7 @@ static inline int
> > arch_futex_atomic_op_inuser(int
> > op, int oparg, int *oval,
> > if (!ret)
> > *oval = oldval;
> >
> > + lock_user_access();
> > return ret;
> > }
> >
> > @@ -75,6 +77,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32
> > __user *uaddr,
> > if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
> > return -EFAULT;
> >
> > + unlock_user_access();
> > __asm__ __volatile__ (
> > PPC_ATOMIC_ENTRY_BARRIER
> > "1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
> > @@ -95,6 +98,7 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32
> > __user *uaddr,
> > : "cc", "memory");
> >
> > *uval = prev;
> > + lock_user_access();
> > return ret;
> > }
> >
> > --
> > 2.19.1
>
>
^ permalink raw reply
* Re: [PATCH 5/5] powerpc/64s: Document that PPC supports nosmap
From: Russell Currey @ 2018-10-29 1:06 UTC (permalink / raw)
To: LEROY Christophe; +Cc: mikey, linuxppc-dev, npiggin
In-Reply-To: <20181026183525.Horde.tXUVv2_ZCCOci3XQBF4ZYw1@messagerie.si.c-s.fr>
On Fri, 2018-10-26 at 18:35 +0200, LEROY Christophe wrote:
> Why not call our new functionnality SMAP instead of calling it GUAP ?
mpe wasn't a fan of using the same terminology as other architectures.
Having a separate term does avoid some assumptions about how things
work or are implemented, but sharing compatibility with an existing
parameter is nice.
Personally I don't really care too much about the name.
- Russell
>
> Christophe
>
> Russell Currey <ruscur@russell.cc> a écrit :
>
> > Signed-off-by: Russell Currey <ruscur@russell.cc>
> > ---
> > Documentation/admin-guide/kernel-parameters.txt | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/admin-guide/kernel-parameters.txt
> > b/Documentation/admin-guide/kernel-parameters.txt
> > index a5ad67d5cb16..8f78e75965f0 100644
> > --- a/Documentation/admin-guide/kernel-parameters.txt
> > +++ b/Documentation/admin-guide/kernel-parameters.txt
> > @@ -2764,7 +2764,7 @@
> > noexec=on: enable non-executable mappings
> > (default)
> > noexec=off: disable non-executable mappings
> >
> > - nosmap [X86]
> > + nosmap [X86,PPC]
> > Disable SMAP (Supervisor Mode Access
> > Prevention)
> > even if it is supported by processor.
> >
> > --
> > 2.19.1
>
>
^ permalink raw reply
* Re: [PATCH 2/4] mm: speed up mremap by 500x on large regions (v2)
From: Balbir Singh @ 2018-10-28 22:40 UTC (permalink / raw)
To: Joel Fernandes
Cc: linux-mips, Rich Felker, linux-ia64, linux-sh, Peter Zijlstra,
Catalin Marinas, Dave Hansen, Will Deacon, mhocko, linux-mm,
lokeshgidra, sparclinux, linux-riscv, elfring, Jonas Bonn, kvmarm,
dancol, Yoshinori Sato, linux-xtensa, linux-hexagon, Helge Deller,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), hughd,
James E.J. Bottomley, kasan-dev, anton.ivanov, Ingo Molnar,
Geert Uytterhoeven, Andrey Ryabinin, linux-snps-arc, kernel-team,
Sam Creasey, Fenghua Yu, linux-s390, Jeff Dike, linux-um,
Stefan Kristiansson, Julia Lawall, linux-m68k, Borislav Petkov,
Andy Lutomirski, nios2-dev, Kirill A. Shutemov, Stafford Horne,
Guan Xuetao, Chris Zankel, Tony Luck, Richard Weinberger,
linux-parisc, pantin, Max Filippov, linux-kernel, minchan,
Thomas Gleixner, linux-alpha, Ley Foon Tan, akpm, linuxppc-dev,
David S. Miller
In-Reply-To: <20181027193917.GA51131@joelaf.mtv.corp.google.com>
On Sat, Oct 27, 2018 at 12:39:17PM -0700, Joel Fernandes wrote:
> Hi Balbir,
>
> On Sat, Oct 27, 2018 at 09:21:02PM +1100, Balbir Singh wrote:
> > On Wed, Oct 24, 2018 at 07:13:50PM -0700, Joel Fernandes wrote:
> > > On Wed, Oct 24, 2018 at 10:57:33PM +1100, Balbir Singh wrote:
> > > [...]
> > > > > > + pmd_t pmd;
> > > > > > +
> > > > > > + new_ptl = pmd_lockptr(mm, new_pmd);
> > > >
> > > >
> > > > Looks like this is largely inspired by move_huge_pmd(), I guess a lot of
> > > > the code applies, why not just reuse as much as possible? The same comments
> > > > w.r.t mmap_sem helping protect against lock order issues applies as well.
> > >
> > > I thought about this and when I looked into it, it seemed there are subtle
> > > differences that make such sharing not worth it (or not possible).
> > >
> >
> > Could you elaborate on them?
>
> The move_huge_page function is defined only for CONFIG_TRANSPARENT_HUGEPAGE
> so we cannot reuse it to begin with, since we have it disabled on our
> systems. I am not sure if it is a good idea to split that out and refactor it
> for reuse especially since our case is quite simple compared to huge pages.
>
> There are also a couple of subtle differences between the move_normal_pmd and
> the move_huge_pmd. Atleast 2 of them are:
>
> 1. We don't concern ourself with the PMD dirty bit, since the pages being
> moved are normal pages and at the soft-dirty bit accounting is at the PTE
> level, since we are not moving PTEs, we don't need to do that.
>
> 2. The locking is simpler as Kirill pointed, pmd_lock cannot fail however
> __pmd_trans_huge_lock can.
>
> I feel it is not super useful to refactor move_huge_pmd to support our case
> especially since move_normal_pmd is quite small, so IMHO the benefit of code
> reuse isn't there very much.
>
My big concern is that any bug fixes will need to monitor both paths.
Do you see a big overhead in checking the soft dirty bit? The locking is
a little different. Having said that, I am not strictly opposed to the
extra code, just concerned about missing fixes/updates as we find them.
> Do let me know your thoughts and thanks for your interest in this.
>
>
Balbir Singh.
^ permalink raw reply
* Re: ethernet "bus" number in DTS ?
From: Michal Suchánek @ 2018-10-28 18:25 UTC (permalink / raw)
To: Florian Fainelli
Cc: andrew@lunn.ch, netdev@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, robh
In-Reply-To: <27720d1a-a002-5090-d4fc-92ea59b5839a@gmail.com>
On Fri, 26 Oct 2018 15:57:15 -0700
Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 10/23/18 11:22 PM, Michal Suchánek wrote:
> > On Tue, 23 Oct 2018 11:20:36 -0700
> > Florian Fainelli <f.fainelli@gmail.com> wrote:
> >
> >> On 10/23/18 11:02 AM, Joakim Tjernlund wrote:
> >>> On Tue, 2018-10-23 at 10:03 -0700, Florian Fainelli wrote:
> >
> >>>
> >>> I also noted that using status = "disabled" didn't work either to
> >>> create a fix name scheme. Even worse, all the eth I/F after gets
> >>> renumbered. It seems to me there is value in having stability in
> >>> eth I/F naming at boot. Then userspace(udev) can rename if need
> >>> be.
> >>>
> >>> Sure would like to known more about why this feature is not
> >>> wanted ?
> >>>
> >>> I found
> >>> https://patchwork.kernel.org/patch/4122441/
> >>> You quote policy as reason but surely it must be better to
> >>> have something stable, connected to the hardware name, than
> >>> semirandom naming?
> >>
> >> If the Device Tree nodes are ordered by ascending base register
> >> address, my understanding is that you get the same order as far as
> >> platform_device creation goes, this may not be true in the future
> >> if Rob decides to randomize that, but AFAICT this is still true.
> >> This may not work well with status = disabled properties being
> >> inserted here and there, but we have used that here and it has
> >> worked for as far as I can remember doing it.
> >
> > So this is unstable in several respects. First is changing the
> > enabled/disabled status in the deivecetrees provided by the kernel.
> >
> > Second is if you have hardware hotplug mechanism either by firmware
> > or by loading device overlays.
> >
> > Third is the case when the devicetree is not built as part of the
> > kernel but is instead provided by firmware that initializes the
> > low-level hardware details. Then the ordering by address is not
> > guaranteed nor is that the same address will be used to access the
> > same interface every time. There might be multiple ways to
> > configure the hardware depending on firmware configuration and/or
> > version.
> >
> >
> >> Second, you might want to name network devices ethX, but what if I
> >> want to name them ethernetX or fooX or barX? Should we be
> >> accepting a mechanism in the kernel that would allow someone to
> >> name the interfaces the way they want straight from a name being
> >> provided in Device Tree?
> >
> > Clearly if there is text Ethernet1 printed above the Ethernet port
> > we should provide a mechanism to name the port Ethernet1 by
> > default.
>
> Yes, but then have a specific property that is flexible enough to
> retrieve things like "vital product information". For DSA switches, we
> have an optional "label" property which names the network device
> directly like it would be found on the product's case. Ideally this
> should be much more flexible such that it can point to the appropriate
> node/firmware service/whatever to get that name, which is what some
> people have been working on lately, see [1].
>
> [1]: https://lkml.org/lkml/2018/8/14/1039
That's nice for something unique per-device like MAC address. However,
for something per-model like port labels DT properties should suffice.
>
> The point is don't re-purpose the aliases which is something that
> exists within Device Tree to basically provide a shorter path to a
> specific set of nodes for the boot program to mangle and muck with
> instead of having to resolve a full path to a node. At least that is
> how I conceive it.
>
> Now what complicates the matter is that some OSes like Linux tend to
> use it to also generate seemingly stable index for peripherals that
> are numbered by index such as SPI, I2C, etc buses, which is why we are
> having this conversation here, see below for more.
>
> >
> >>
> >> Aliases are fine for providing relative stability within the Device
> >> Tree itself and boot programs that might need to modify the Device
> >> Tree (e.g: inserting MAC addresses) such that you don't have to
> >> encode logic to search for nodes by compatible strings etc. but
> >> outside of that use case, it seems to me that you can resolve every
> >> naming decision in user-space.
> >
> > However, this is pushing platform-specific knowledge to userspace.
> > The way the Ethernet interface is attached and hence the device
> > properties usable for identifying the device uniquely are
> > platform-specific.
>
> There is always going to be some amount of platform specific knowledge
> to user-space, what matters is the level of abstraction that is
> presented to you.
>
> >
> > On the other hand, aliases are universal when provided. If they are
> > good enough to assign a MAC address they are good enough to provide
> > a stable default name.
>
> We are not talking about the same aliases then. The special Device
> Tree node named "aliases" is a way to create shorted Device Tree node
> paths, it is not by any means an equivalent for what I would rather
> call a "label", or "port name" or silk screen annotation on a PCB for
> instance.
However, if the kernel ethN names are deterministic based on something
like aliases it is trivial to translate them to "port name". As it is
they are pretty much random which is the issue aliases *can* solve.
>
> >
> > I think this is indeed forcing the userspace to reinvent several
> > wheels for no good reason.
>
> udev or systemd will come up with some stable names for your network
> device right off the bat.
As has been already pointed out these names are not stable for various
reasons. *Making* them stable is the whole point of this discussion.
> If you are deeply embedded maybe you don't
> want those, but then use something like the full path in /sys to get
> some stable names based on the SoC's topology.
However, it some devices might be disabled depending on the device
configuration generating stable names is not that easy. Also if bus
topology may differ depending on device/firmware configuration you
cannot assign stable names based just on /sys hierarchy. Also it is
said that /sys hierarchy is not an ABI in the kernel docs so you should
not base your stable device names which *are* an ABI on the
unstable /sys hierarchy.
>
> >
> > What is the problem with adding the aliases?
>
> aliases is IMHO the wrong tool for the job because it is too limiting,
> you want it to be used to have Ethernet controller instance N to be
> named "ethN", what if someone tomorrows says, no this is not good, I
> want the aliases to automatically name my network devices
> "ethernet-controllerN" or "blahblahN"? You see where I am getting
> with that?
Then you can write udev rule to translate ethN to blahlbahN and so long
as the ethN is stable the translation is stable as well. Alternatively
you might want to use a different devicetree property if one existed.
>
> And yes, I do realize that Linux has traditionally named Ethernet
> adapters ethN, but also allows people to name interfaces just the way
> they want even from within the drivers themselves.
>
> Now imagine your platform uses ACPI, and there are no aliases there to
> point a node with a shorter name, how we would go about naming your
> Ethernet controller unless there is a specific VPD/label/sticker
> property that can be somehow be retried?
There is biosdevname for that which uses proprietary BIOS extensions to
look up device names in BIOS.
Thanks
Michal
^ permalink raw reply
* Re: [PATCH 1/5] powerpc/64s: Guarded Userspace Access Prevention
From: LEROY Christophe @ 2018-10-28 17:57 UTC (permalink / raw)
To: Russell Currey; +Cc: mikey, linuxppc-dev, npiggin
In-Reply-To: <20181026063513.30806-2-ruscur@russell.cc>
Russell Currey <ruscur@russell.cc> a écrit :
> Guarded Userspace Access Prevention (GUAP) utilises a feature of
> the Radix MMU which disallows read and write access to userspace
> addresses. By utilising this, the kernel is prevented from accessing
> user data from outside of trusted paths that perform proper safety checks,
> such as copy_{to/from}_user() and friends.
>
> Userspace access is disabled from early boot and is only enabled when:
>
> - exiting the kernel and entering userspace
> - performing an operation like copy_{to/from}_user()
> - context switching to a process that has access enabled
>
> and similarly, access is disabled again when exiting userspace and entering
> the kernel.
>
> This feature has a slight performance impact which I roughly measured to be
> 3% slower in the worst case (performing 1GB of 1 byte read()/write()
> syscalls), and is gated behind the CONFIG_PPC_RADIX_GUAP option for
> performance-critical builds.
>
> This feature can be tested by using the lkdtm driver (CONFIG_LKDTM=y) and
> performing the following:
>
> echo ACCESS_USERSPACE > [debugfs]/provoke-crash/DIRECT
>
> if enabled, this should send SIGSEGV to the thread.
>
> Signed-off-by: Russell Currey <ruscur@russell.cc>
I think this patch should be split in at least two parts:
First part for implementing the generic part, including the changes to
futex and csum, and a second part implementing the radix part.
> ---
> Since the previous version of this patchset (named KHRAP) there have been
> several changes, some of which include:
>
> - macro naming, suggested by Nick
> - builds should be fixed outside of 64s
> - no longer unlock heading out to userspace
> - removal of unnecessary isyncs
> - more config option testing
> - removal of save/restore
> - use pr_crit() and reword message on fault
>
> arch/powerpc/include/asm/exception-64e.h | 3 ++
> arch/powerpc/include/asm/exception-64s.h | 19 +++++++-
> arch/powerpc/include/asm/mmu.h | 7 +++
> arch/powerpc/include/asm/paca.h | 3 ++
> arch/powerpc/include/asm/reg.h | 1 +
> arch/powerpc/include/asm/uaccess.h | 57 ++++++++++++++++++++----
> arch/powerpc/kernel/asm-offsets.c | 1 +
> arch/powerpc/kernel/dt_cpu_ftrs.c | 4 ++
> arch/powerpc/kernel/entry_64.S | 17 ++++++-
> arch/powerpc/mm/fault.c | 12 +++++
> arch/powerpc/mm/pgtable-radix.c | 2 +
> arch/powerpc/mm/pkeys.c | 7 ++-
> arch/powerpc/platforms/Kconfig.cputype | 15 +++++++
> 13 files changed, 135 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/exception-64e.h
> b/arch/powerpc/include/asm/exception-64e.h
> index 555e22d5e07f..bf25015834ee 100644
> --- a/arch/powerpc/include/asm/exception-64e.h
> +++ b/arch/powerpc/include/asm/exception-64e.h
> @@ -215,5 +215,8 @@ exc_##label##_book3e:
> #define RFI_TO_USER \
> rfi
>
> +#define UNLOCK_USER_ACCESS(reg)
> +#define LOCK_USER_ACCESS(reg)
> +
> #endif /* _ASM_POWERPC_EXCEPTION_64E_H */
>
> diff --git a/arch/powerpc/include/asm/exception-64s.h
> b/arch/powerpc/include/asm/exception-64s.h
> index 3b4767ed3ec5..0cac5bd380ca 100644
> --- a/arch/powerpc/include/asm/exception-64s.h
> +++ b/arch/powerpc/include/asm/exception-64s.h
> @@ -264,6 +264,19 @@ BEGIN_FTR_SECTION_NESTED(943) \
> std ra,offset(r13); \
> END_FTR_SECTION_NESTED(ftr,ftr,943)
>
> +#define LOCK_USER_ACCESS(reg) \
> +BEGIN_MMU_FTR_SECTION_NESTED(944) \
> + LOAD_REG_IMMEDIATE(reg,AMR_LOCKED); \
> + mtspr SPRN_AMR,reg; \
> +END_MMU_FTR_SECTION_NESTED(MMU_FTR_RADIX_GUAP,MMU_FTR_RADIX_GUAP,944)
> +
> +#define UNLOCK_USER_ACCESS(reg) \
> +BEGIN_MMU_FTR_SECTION_NESTED(945) \
> + li reg,0; \
> + mtspr SPRN_AMR,reg; \
> + isync \
> +END_MMU_FTR_SECTION_NESTED(MMU_FTR_RADIX_GUAP,MMU_FTR_RADIX_GUAP,945)
> +
> #define EXCEPTION_PROLOG_0(area) \
> GET_PACA(r13); \
> std r9,area+EX_R9(r13); /* save r9 */ \
> @@ -500,7 +513,11 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
> beq 4f; /* if from kernel mode */ \
> ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
> SAVE_PPR(area, r9); \
> -4: EXCEPTION_PROLOG_COMMON_2(area) \
> +4: lbz r9,PACA_USER_ACCESS_ALLOWED(r13); \
> + cmpwi cr1,r9,0; \
> + beq 5f; \
> + LOCK_USER_ACCESS(r9); \
> +5: EXCEPTION_PROLOG_COMMON_2(area) \
> EXCEPTION_PROLOG_COMMON_3(n) \
> ACCOUNT_STOLEN_TIME
>
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index eb20eb3b8fb0..3b31ed702785 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -107,6 +107,10 @@
> */
> #define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
>
> +/* Supports GUAP (key 0 controlling userspace addresses) on radix
> + */
> +#define MMU_FTR_RADIX_GUAP ASM_CONST(0x80000000)
> +
> /* MMU feature bit sets for various CPUs */
> #define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
> MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
> @@ -143,6 +147,9 @@ enum {
> MMU_FTR_KERNEL_RO | MMU_FTR_68_BIT_VA |
> #ifdef CONFIG_PPC_RADIX_MMU
> MMU_FTR_TYPE_RADIX |
> +#endif
> +#ifdef CONFIG_PPC_RADIX_GUAP
> + MMU_FTR_RADIX_GUAP |
Can this exist without MMT_FTR_TYPE_RADIX ?
> #endif
> 0,
> };
> diff --git a/arch/powerpc/include/asm/paca.h
> b/arch/powerpc/include/asm/paca.h
> index e843bc5d1a0f..e905f09b2d38 100644
> --- a/arch/powerpc/include/asm/paca.h
> +++ b/arch/powerpc/include/asm/paca.h
> @@ -169,6 +169,9 @@ struct paca_struct {
> u64 saved_r1; /* r1 save for RTAS calls or PM or EE=0 */
> u64 saved_msr; /* MSR saved here by enter_rtas */
> u16 trap_save; /* Used when bad stack is encountered */
> +#ifdef CONFIG_PPC_RADIX_GUAP
> + u8 user_access_allowed; /* set when AMR allows user accesses */
> +#endif
> u8 irq_soft_mask; /* mask for irq soft masking */
> u8 irq_happened; /* irq happened while soft-disabled */
> u8 io_sync; /* writel() needs spin_unlock sync */
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 640a4d818772..b994099a906b 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -246,6 +246,7 @@
> #define SPRN_DSCR 0x11
> #define SPRN_CFAR 0x1c /* Come From Address Register */
> #define SPRN_AMR 0x1d /* Authority Mask Register */
> +#define AMR_LOCKED 0xC000000000000000ULL /* Read & Write disabled */
Why ULL ? mtspr() takes unsigned long arg.
> #define SPRN_UAMOR 0x9d /* User Authority Mask Override Register */
> #define SPRN_AMOR 0x15d /* Authority Mask Override Register */
> #define SPRN_ACOP 0x1F /* Available Coprocessor Register */
> diff --git a/arch/powerpc/include/asm/uaccess.h
> b/arch/powerpc/include/asm/uaccess.h
> index 15bea9a0f260..209bfc47c340 100644
> --- a/arch/powerpc/include/asm/uaccess.h
> +++ b/arch/powerpc/include/asm/uaccess.h
> @@ -62,6 +62,27 @@ static inline int __access_ok(unsigned long addr,
> unsigned long size,
>
> #endif
>
> +static inline void unlock_user_access(void)
> +{
> +#ifdef CONFIG_PPC_RADIX_GUAP
> + if (mmu_has_feature(MMU_FTR_RADIX_GUAP)) {
You need to include the .h which provides mmu_has_feature()
I think uaccess.h should only include the empty function for when
CONFIG_PPC_GUAP is not defined. Radix guap function should go in a
radix header file.
> + mtspr(SPRN_AMR, 0);
> + isync();
> + get_paca()->user_access_allowed = 1;
> + }
> +#endif
> +}
> +
> +static inline void lock_user_access(void)
> +{
> +#ifdef CONFIG_PPC_RADIX_GUAP
> + if (mmu_has_feature(MMU_FTR_RADIX_GUAP)) {
> + mtspr(SPRN_AMR, AMR_LOCKED);
> + get_paca()->user_access_allowed = 0;
> + }
> +#endif
> +}
> +
> #define access_ok(type, addr, size) \
> (__chk_user_ptr(addr), \
> __access_ok((__force unsigned long)(addr), (size), get_fs()))
> @@ -141,6 +162,7 @@ extern long __put_user_bad(void);
> #define __put_user_size(x, ptr, size, retval) \
> do { \
> retval = 0; \
> + unlock_user_access(); \
> switch (size) { \
> case 1: __put_user_asm(x, ptr, retval, "stb"); break; \
> case 2: __put_user_asm(x, ptr, retval, "sth"); break; \
> @@ -148,6 +170,7 @@ do { \
> case 8: __put_user_asm2(x, ptr, retval); break; \
> default: __put_user_bad(); \
> } \
> + lock_user_access(); \
> } while (0)
>
> #define __put_user_nocheck(x, ptr, size) \
> @@ -240,6 +263,7 @@ do { \
> __chk_user_ptr(ptr); \
> if (size > sizeof(x)) \
> (x) = __get_user_bad(); \
> + unlock_user_access(); \
> switch (size) { \
> case 1: __get_user_asm(x, ptr, retval, "lbz"); break; \
> case 2: __get_user_asm(x, ptr, retval, "lhz"); break; \
> @@ -247,6 +271,7 @@ do { \
> case 8: __get_user_asm2(x, ptr, retval); break; \
> default: (x) = __get_user_bad(); \
> } \
> + lock_user_access(); \
> } while (0)
>
> /*
> @@ -306,15 +331,20 @@ extern unsigned long __copy_tofrom_user(void
> __user *to,
> static inline unsigned long
> raw_copy_in_user(void __user *to, const void __user *from, unsigned long n)
> {
> - return __copy_tofrom_user(to, from, n);
> + unsigned long ret;
> + unlock_user_access(); \
> + ret = __copy_tofrom_user(to, from, n); \
> + lock_user_access(); \
> + return ret; \
> }
> #endif /* __powerpc64__ */
>
> static inline unsigned long raw_copy_from_user(void *to,
> const void __user *from, unsigned long n)
> {
> + unsigned long ret;
> if (__builtin_constant_p(n) && (n <= 8)) {
> - unsigned long ret = 1;
> + ret = 1;
>
> switch (n) {
> case 1:
> @@ -339,14 +369,18 @@ static inline unsigned long
> raw_copy_from_user(void *to,
> }
>
> barrier_nospec();
> - return __copy_tofrom_user((__force void __user *)to, from, n);
> + unlock_user_access();
> + ret = __copy_tofrom_user((__force void __user *)to, from, n);
> + lock_user_access();
> + return ret;
> }
>
> static inline unsigned long raw_copy_to_user(void __user *to,
> const void *from, unsigned long n)
> {
> + unsigned long ret;
> if (__builtin_constant_p(n) && (n <= 8)) {
> - unsigned long ret = 1;
> + ret = 1;
>
> switch (n) {
> case 1:
> @@ -366,17 +400,24 @@ static inline unsigned long
> raw_copy_to_user(void __user *to,
> return 0;
> }
>
> - return __copy_tofrom_user(to, (__force const void __user *)from, n);
> + unlock_user_access();
> + ret = __copy_tofrom_user(to, (__force const void __user *)from, n);
> + lock_user_access();
> + return ret;
> }
>
> extern unsigned long __clear_user(void __user *addr, unsigned long size);
>
> static inline unsigned long clear_user(void __user *addr, unsigned
> long size)
> {
> + unsigned long ret = size;
> might_fault();
> - if (likely(access_ok(VERIFY_WRITE, addr, size)))
> - return __clear_user(addr, size);
> - return size;
> + if (likely(access_ok(VERIFY_WRITE, addr, size))) {
> + unlock_user_access();
> + ret = __clear_user(addr, size);
> + lock_user_access();
> + }
> + return ret;
> }
>
> extern long strncpy_from_user(char *dst, const char __user *src,
> long count);
> diff --git a/arch/powerpc/kernel/asm-offsets.c
> b/arch/powerpc/kernel/asm-offsets.c
> index 10ef2e4db2fd..5050f15ad2f5 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -260,6 +260,7 @@ int main(void)
> OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
> OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
> OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
> + OFFSET(PACA_USER_ACCESS_ALLOWED, paca_struct, user_access_allowed);
> OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
> OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost);
> OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
> diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c
> b/arch/powerpc/kernel/dt_cpu_ftrs.c
> index f432054234a4..df4716624840 100644
> --- a/arch/powerpc/kernel/dt_cpu_ftrs.c
> +++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
> @@ -337,6 +337,10 @@ static int __init feat_enable_mmu_radix(struct
> dt_cpu_feature *f)
> cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
> cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
>
> +#ifdef CONFIG_PPC_RADIX_GUAP
> + cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_GUAP;
> +#endif
> +
> return 1;
> #endif
> return 0;
> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> index 7b1693adff2a..23f0944185d3 100644
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -297,7 +297,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> b . /* prevent speculative execution */
>
> /* exit to kernel */
> -1: ld r2,GPR2(r1)
> +1: /* if the AMR was unlocked before, unlock it again */
> + lbz r2,PACA_USER_ACCESS_ALLOWED(r13)
> + cmpwi cr1,0
> + bne 2f
> + UNLOCK_USER_ACCESS(r2)
> +2: ld r2,GPR2(r1)
> ld r1,GPR1(r1)
> mtlr r4
> mtcr r5
> @@ -965,6 +970,7 @@ BEGIN_FTR_SECTION
> ld r2,_PPR(r1)
> mtspr SPRN_PPR,r2
> END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> +
> ACCOUNT_CPU_USER_EXIT(r13, r2, r4)
> REST_GPR(13, r1)
>
> @@ -983,7 +989,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
> RFI_TO_USER
> b . /* prevent speculative execution */
>
> -1: mtspr SPRN_SRR1,r3
> +1: /* exit to kernel */
> + /* if the AMR was unlocked before, unlock it again */
> + lbz r2,PACA_USER_ACCESS_ALLOWED(r13)
> + cmpwi cr1,0
> + bne 2f
> + UNLOCK_USER_ACCESS(r2)
> +
> +2: mtspr SPRN_SRR1,r3
>
> ld r2,_CCR(r1)
> mtcrf 0xFF,r2
> diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
> index d51cf5f4e45e..17fd8c6b055b 100644
> --- a/arch/powerpc/mm/fault.c
> +++ b/arch/powerpc/mm/fault.c
> @@ -462,6 +462,18 @@ static int __do_page_fault(struct pt_regs
> *regs, unsigned long address,
> return bad_key_fault_exception(regs, address,
> get_mm_addr_key(mm, address));
>
> +#ifdef CONFIG_PPC_RADIX_SMAP
SMAP ?
> + if (mmu_has_feature(MMU_FTR_RADIX_GUAP)) {
> + if (unlikely(!is_user &&
> + (error_code & DSISR_PROTFAULT) &&
> + (mfspr(SPRN_AMR) & AMR_LOCKED))) {
Do you mean that in case of fault in user copy, we leave the
protection open for handling the exception ? What is the purpose of
the new paca flag then ?
> + pr_crit("Kernel attempted to access user data"
> + " unsafely, possible exploit attempt\n");
> + return bad_area_nosemaphore(regs, address);
> + }
> + }
Are we sure it is an access to user data ?
> +#endif
> +
> /*
> * We want to do this outside mmap_sem, because reading code around nip
> * can result in fault, which will cause a deadlock when called with
> diff --git a/arch/powerpc/mm/pgtable-radix.c
> b/arch/powerpc/mm/pgtable-radix.c
> index c879979faa73..9e5b98887a05 100644
> --- a/arch/powerpc/mm/pgtable-radix.c
> +++ b/arch/powerpc/mm/pgtable-radix.c
> @@ -29,6 +29,7 @@
> #include <asm/powernv.h>
> #include <asm/sections.h>
> #include <asm/trace.h>
> +#include <asm/uaccess.h>
>
> #include <trace/events/thp.h>
>
> @@ -608,6 +609,7 @@ void __init radix__early_init_mmu(void)
> mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
> radix_init_partition_table();
> radix_init_amor();
> + lock_user_access();
> } else {
> radix_init_pseries();
> }
> diff --git a/arch/powerpc/mm/pkeys.c b/arch/powerpc/mm/pkeys.c
> index b271b283c785..0b9bc320138c 100644
> --- a/arch/powerpc/mm/pkeys.c
> +++ b/arch/powerpc/mm/pkeys.c
> @@ -7,6 +7,7 @@
>
> #include <asm/mman.h>
> #include <asm/setup.h>
> +#include <asm/uaccess.h>
> #include <linux/pkeys.h>
> #include <linux/of_device.h>
>
> @@ -266,7 +267,8 @@ int __arch_set_user_pkey_access(struct
> task_struct *tsk, int pkey,
>
> void thread_pkey_regs_save(struct thread_struct *thread)
> {
> - if (static_branch_likely(&pkey_disabled))
> + if (static_branch_likely(&pkey_disabled) &&
> + !mmu_has_feature(MMU_FTR_RADIX_GUAP))
> return;
>
> /*
> @@ -280,7 +282,8 @@ void thread_pkey_regs_save(struct thread_struct *thread)
> void thread_pkey_regs_restore(struct thread_struct *new_thread,
> struct thread_struct *old_thread)
> {
> - if (static_branch_likely(&pkey_disabled))
> + if (static_branch_likely(&pkey_disabled) &&
> + !mmu_has_feature(MMU_FTR_RADIX_GUAP))
> return;
>
> if (old_thread->amr != new_thread->amr)
> diff --git a/arch/powerpc/platforms/Kconfig.cputype
> b/arch/powerpc/platforms/Kconfig.cputype
> index f4e2c5729374..6617d3e415a7 100644
> --- a/arch/powerpc/platforms/Kconfig.cputype
> +++ b/arch/powerpc/platforms/Kconfig.cputype
> @@ -351,6 +351,21 @@ config PPC_RADIX_MMU_DEFAULT
>
> If you're unsure, say Y.
>
> +config PPC_RADIX_GUAP
> + bool "Guarded Userspace Access Prevention on Radix"
> + depends on PPC_RADIX_MMU
> + default y
> + help
> + Enable support for Guarded Userspace Access Prevention (GUAP)
> + when using the Radix MMU. GUAP is a security feature
> + preventing the kernel from directly accessing userspace data
> + without going through the proper checks.
> +
> + GUAP has a minor performance impact on context switching and can be
> + disabled at boot time using the "nosmap" kernel command line option.
> +
> + If you're unsure, say Y.
> +
I think this should be a named in a generic way without the radix thing.
Then one day it will be reused by the 8xx
Christophe
> config ARCH_ENABLE_HUGEPAGE_MIGRATION
> def_bool y
> depends on PPC_BOOK3S_64 && HUGETLB_PAGE && MIGRATION
> --
> 2.19.1
^ permalink raw reply
* [PATCH] hwmon: (ibmpowernv) Remove bogus __init annotations
From: Geert Uytterhoeven @ 2018-10-28 17:16 UTC (permalink / raw)
To: Cédric Le Goater, Jean Delvare, Guenter Roeck,
Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linux-hwmon, Geert Uytterhoeven, linuxppc-dev, linux-kernel
If gcc decides not to inline make_sensor_label():
WARNING: vmlinux.o(.text+0x4df549c): Section mismatch in reference from the function .create_device_attrs() to the function .init.text:.make_sensor_label()
The function .create_device_attrs() references
the function __init .make_sensor_label().
This is often because .create_device_attrs lacks a __init
annotation or the annotation of .make_sensor_label is wrong.
As .probe() can be called after freeing of __init memory, all __init
annotiations in the driver are bogus, and should be removed.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
Compile-tested only.
---
drivers/hwmon/ibmpowernv.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/hwmon/ibmpowernv.c b/drivers/hwmon/ibmpowernv.c
index 0ccca87f527191dc..293dd1c6c7b36ef2 100644
--- a/drivers/hwmon/ibmpowernv.c
+++ b/drivers/hwmon/ibmpowernv.c
@@ -181,7 +181,7 @@ static ssize_t show_label(struct device *dev, struct device_attribute *devattr,
return sprintf(buf, "%s\n", sdata->label);
}
-static int __init get_logical_cpu(int hwcpu)
+static int get_logical_cpu(int hwcpu)
{
int cpu;
@@ -192,9 +192,8 @@ static int __init get_logical_cpu(int hwcpu)
return -ENOENT;
}
-static void __init make_sensor_label(struct device_node *np,
- struct sensor_data *sdata,
- const char *label)
+static void make_sensor_label(struct device_node *np,
+ struct sensor_data *sdata, const char *label)
{
u32 id;
size_t n;
--
2.17.1
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