* [PATCH v10 14/18] drivers/clocksource: timer-fsl-ftm: use common header for FlexTimer #defines
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, tglx, fabrice.gasnier, esben, shawnguo, linux-kernel,
leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Patrick Havelange <patrick.havelange@essensium.com>
Common #defines have been moved to "linux/fsl/ftm.h". Thus making use of
this file.
Also FTM_SC_CLK_SHIFT has been renamed to FTM_SC_CLK_MASK_SHIFT.
Reviewed-by: Esben Haabendal <esben@haabendal.dk>
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/clocksource/timer-fsl-ftm.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/clocksource/timer-fsl-ftm.c b/drivers/clocksource/timer-fsl-ftm.c
index 846d18daf893..e1c34b2f53a5 100644
--- a/drivers/clocksource/timer-fsl-ftm.c
+++ b/drivers/clocksource/timer-fsl-ftm.c
@@ -19,20 +19,9 @@
#include <linux/of_irq.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
+#include <linux/fsl/ftm.h>
-#define FTM_SC 0x00
-#define FTM_SC_CLK_SHIFT 3
-#define FTM_SC_CLK_MASK (0x3 << FTM_SC_CLK_SHIFT)
-#define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_SHIFT)
-#define FTM_SC_PS_MASK 0x7
-#define FTM_SC_TOIE BIT(6)
-#define FTM_SC_TOF BIT(7)
-
-#define FTM_CNT 0x04
-#define FTM_MOD 0x08
-#define FTM_CNTIN 0x4C
-
-#define FTM_PS_MAX 7
+#define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
struct ftm_clock_device {
void __iomem *clksrc_base;
--
2.21.0
^ permalink raw reply related
* [PATCH v10 13/18] drivers/pwm: pwm-fsl-ftm: use common header for FlexTimer #defines
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, tglx, fabrice.gasnier, esben, shawnguo, linux-kernel,
leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Patrick Havelange <patrick.havelange@essensium.com>
This also fixes the wrong value for the previously defined
FTM_MODE_INIT macro (it was not used).
Reviewed-by: Esben Haabendal <esben@haabendal.dk>
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/pwm/pwm-fsl-ftm.c | 44 +--------------------------------------
1 file changed, 1 insertion(+), 43 deletions(-)
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 883378d055c6..f21ea1b97116 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -22,51 +22,9 @@
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>
+#include <linux/fsl/ftm.h>
-#define FTM_SC 0x00
-#define FTM_SC_CLK_MASK_SHIFT 3
-#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT)
-#define FTM_SC_PS_MASK 0x7
-
-#define FTM_CNT 0x04
-#define FTM_MOD 0x08
-
-#define FTM_CSC_BASE 0x0C
-#define FTM_CSC_MSB BIT(5)
-#define FTM_CSC_MSA BIT(4)
-#define FTM_CSC_ELSB BIT(3)
-#define FTM_CSC_ELSA BIT(2)
-#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
-
-#define FTM_CV_BASE 0x10
-#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
-
-#define FTM_CNTIN 0x4C
-#define FTM_STATUS 0x50
-
-#define FTM_MODE 0x54
-#define FTM_MODE_FTMEN BIT(0)
-#define FTM_MODE_INIT BIT(2)
-#define FTM_MODE_PWMSYNC BIT(3)
-
-#define FTM_SYNC 0x58
-#define FTM_OUTINIT 0x5C
-#define FTM_OUTMASK 0x60
-#define FTM_COMBINE 0x64
-#define FTM_DEADTIME 0x68
-#define FTM_EXTTRIG 0x6C
-#define FTM_POL 0x70
-#define FTM_FMS 0x74
-#define FTM_FILTER 0x78
-#define FTM_FLTCTRL 0x7C
-#define FTM_QDCTRL 0x80
-#define FTM_CONF 0x84
-#define FTM_FLTPOL 0x88
-#define FTM_SYNCONF 0x8C
-#define FTM_INVCTRL 0x90
-#define FTM_SWOCTRL 0x94
-#define FTM_PWMLOAD 0x98
enum fsl_pwm_clk {
FSL_PWM_CLK_SYS,
--
2.21.0
^ permalink raw reply related
* [PATCH v10 12/18] include/fsl: add common FlexTimer #defines in a separate header.
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, tglx, fabrice.gasnier, esben, shawnguo, linux-kernel,
leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Patrick Havelange <patrick.havelange@essensium.com>
Several files are/will be using the same #defines to use the Flextimer
module. Regroup them in a common file.
Reviewed-by: Esben Haabendal <esben@haabendal.dk>
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
include/linux/fsl/ftm.h | 88 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 include/linux/fsl/ftm.h
diff --git a/include/linux/fsl/ftm.h b/include/linux/fsl/ftm.h
new file mode 100644
index 000000000000..d59011acf66c
--- /dev/null
+++ b/include/linux/fsl/ftm.h
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0
+#ifndef __FSL_FTM_H__
+#define __FSL_FTM_H__
+
+#define FTM_SC 0x0 /* Status And Control */
+#define FTM_CNT 0x4 /* Counter */
+#define FTM_MOD 0x8 /* Modulo */
+
+#define FTM_CNTIN 0x4C /* Counter Initial Value */
+#define FTM_STATUS 0x50 /* Capture And Compare Status */
+#define FTM_MODE 0x54 /* Features Mode Selection */
+#define FTM_SYNC 0x58 /* Synchronization */
+#define FTM_OUTINIT 0x5C /* Initial State For Channels Output */
+#define FTM_OUTMASK 0x60 /* Output Mask */
+#define FTM_COMBINE 0x64 /* Function For Linked Channels */
+#define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */
+#define FTM_EXTTRIG 0x6C /* FTM External Trigger */
+#define FTM_POL 0x70 /* Channels Polarity */
+#define FTM_FMS 0x74 /* Fault Mode Status */
+#define FTM_FILTER 0x78 /* Input Capture Filter Control */
+#define FTM_FLTCTRL 0x7C /* Fault Control */
+#define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */
+#define FTM_CONF 0x84 /* Configuration */
+#define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */
+#define FTM_SYNCONF 0x8C /* Synchronization Configuration */
+#define FTM_INVCTRL 0x90 /* FTM Inverting Control */
+#define FTM_SWOCTRL 0x94 /* FTM Software Output Control */
+#define FTM_PWMLOAD 0x98 /* FTM PWM Load */
+
+#define FTM_SC_CLK_MASK_SHIFT 3
+#define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT)
+#define FTM_SC_TOF 0x80
+#define FTM_SC_TOIE 0x40
+#define FTM_SC_CPWMS 0x20
+#define FTM_SC_CLKS 0x18
+#define FTM_SC_PS_1 0x0
+#define FTM_SC_PS_2 0x1
+#define FTM_SC_PS_4 0x2
+#define FTM_SC_PS_8 0x3
+#define FTM_SC_PS_16 0x4
+#define FTM_SC_PS_32 0x5
+#define FTM_SC_PS_64 0x6
+#define FTM_SC_PS_128 0x7
+#define FTM_SC_PS_MASK 0x7
+
+#define FTM_MODE_FAULTIE 0x80
+#define FTM_MODE_FAULTM 0x60
+#define FTM_MODE_CAPTEST 0x10
+#define FTM_MODE_PWMSYNC 0x8
+#define FTM_MODE_WPDIS 0x4
+#define FTM_MODE_INIT 0x2
+#define FTM_MODE_FTMEN 0x1
+
+/* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally
+ * and these bits cannot be set. Flextimer cannot use Filter in
+ * Quadrature Decoder Mode.
+ * https://community.nxp.com/thread/467648#comment-1010319
+ */
+#define FTM_QDCTRL_PHAFLTREN 0x80
+#define FTM_QDCTRL_PHBFLTREN 0x40
+#define FTM_QDCTRL_PHAPOL 0x20
+#define FTM_QDCTRL_PHBPOL 0x10
+#define FTM_QDCTRL_QUADMODE 0x8
+#define FTM_QDCTRL_QUADDIR 0x4
+#define FTM_QDCTRL_TOFDIR 0x2
+#define FTM_QDCTRL_QUADEN 0x1
+
+#define FTM_FMS_FAULTF 0x80
+#define FTM_FMS_WPEN 0x40
+#define FTM_FMS_FAULTIN 0x10
+#define FTM_FMS_FAULTF3 0x8
+#define FTM_FMS_FAULTF2 0x4
+#define FTM_FMS_FAULTF1 0x2
+#define FTM_FMS_FAULTF0 0x1
+
+#define FTM_CSC_BASE 0xC
+#define FTM_CSC_MSB 0x20
+#define FTM_CSC_MSA 0x10
+#define FTM_CSC_ELSB 0x8
+#define FTM_CSC_ELSA 0x4
+#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8))
+
+#define FTM_CV_BASE 0x10
+#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8))
+
+#define FTM_PS_MAX 7
+
+#endif
--
2.21.0
^ permalink raw reply related
* [PATCH v10 11/18] iio: counter: Add deprecation markings for IIO Counter attributes
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
The IIO counter subdirectory is now superceded by the Counter subsystem.
This patch adds deprecation warnings to the documentation of the
relevant IIO Counter sysfs attributes.
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
Documentation/ABI/testing/sysfs-bus-iio | 8 ++++++++
.../ABI/testing/sysfs-bus-iio-counter-104-quad-8 | 16 ++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
index 864f8efd12e5..6aef7dbbde44 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio
+++ b/Documentation/ABI/testing/sysfs-bus-iio
@@ -1656,6 +1656,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_raw
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Raw counter device counts from channel Y. For quadrature
counters, multiplication by an available [Y]_scale results in
the counts of a single quadrature signal phase from channel Y.
@@ -1664,6 +1666,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_raw
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Raw counter device index value from channel Y. This attribute
provides an absolute positional reference (e.g. a pulse once per
revolution) which may be used to home positional systems as
@@ -1673,6 +1677,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_count_count_direction_available
KernelVersion: 4.12
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
A list of possible counting directions which are:
- "up" : counter device is increasing.
- "down": counter device is decreasing.
@@ -1681,6 +1687,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_count_direction
KernelVersion: 4.12
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Raw counter device counters direction for channel Y.
What: /sys/bus/iio/devices/iio:deviceX/in_phaseY_raw
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8 b/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
index 7fac2c268d9a..bac3d0d48b7b 100644
--- a/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
+++ b/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
@@ -6,6 +6,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_index_synchronous_mode_available
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Discrete set of available values for the respective counter
configuration are listed in this file.
@@ -13,6 +15,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_count_mode
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Count mode for channel Y. Four count modes are available:
normal, range limit, non-recycle, and modulo-n. The preset value
for channel Y is used by the count mode where required.
@@ -47,6 +51,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_noise_error
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Read-only attribute that indicates whether excessive noise is
present at the channel Y count inputs in quadrature clock mode;
irrelevant in non-quadrature clock mode.
@@ -55,6 +61,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_preset
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
If the counter device supports preset registers, the preset
count for channel Y is provided by this attribute.
@@ -62,6 +70,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_quadrature_mode
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Configure channel Y counter for non-quadrature or quadrature
clock mode. Selecting non-quadrature clock mode will disable
synchronous load mode. In quadrature clock mode, the channel Y
@@ -83,6 +93,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_set_to_preset_on_index
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Whether to set channel Y counter with channel Y preset value
when channel Y index input is active, or continuously count.
Valid attribute values are boolean.
@@ -91,6 +103,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_index_polarity
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Active level of channel Y index input; irrelevant in
non-synchronous load mode.
@@ -98,6 +112,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_synchronous_mode
KernelVersion: 4.10
Contact: linux-iio@vger.kernel.org
Description:
+ This interface is deprecated; please use the Counter subsystem.
+
Configure channel Y counter for non-synchronous or synchronous
load mode. Synchronous load mode cannot be selected in
non-quadrature clock mode.
--
2.21.0
^ permalink raw reply related
* [PATCH v10 10/18] dt-bindings: counter: Adjust dt-bindings for STM32 lptimer move
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, Rob Herring, lars,
daniel.lezcano, linux-arm-kernel, devicetree, david,
William Breathitt Gray, robh+dt, tglx, fabrice.gasnier, esben,
shawnguo, linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev,
jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Fabrice Gasnier <fabrice.gasnier@st.com>
The STM32 LP Timer counter driver now resides under the Counter
subsystem. This patch adjusts dt-bindings to account for the STM32
lptimer driver move.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
.../devicetree/bindings/{iio => }/counter/stm32-lptimer-cnt.txt | 0
Documentation/devicetree/bindings/mfd/stm32-lptimer.txt | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/{iio => }/counter/stm32-lptimer-cnt.txt (100%)
diff --git a/Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-lptimer-cnt.txt
similarity index 100%
rename from Documentation/devicetree/bindings/iio/counter/stm32-lptimer-cnt.txt
rename to Documentation/devicetree/bindings/counter/stm32-lptimer-cnt.txt
diff --git a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt
index 2a9ff29db9c9..fb54e4dad5b3 100644
--- a/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt
+++ b/Documentation/devicetree/bindings/mfd/stm32-lptimer.txt
@@ -16,7 +16,7 @@ Required properties:
Optional subnodes:
- pwm: See ../pwm/pwm-stm32-lp.txt
-- counter: See ../iio/timer/stm32-lptimer-cnt.txt
+- counter: See ../counter/stm32-lptimer-cnt.txt
- trigger: See ../iio/timer/stm32-lptimer-trigger.txt
Example:
--
2.21.0
^ permalink raw reply related
* [PATCH v10 09/18] counter: stm32-lptimer: add counter device
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Fabrice Gasnier <fabrice.gasnier@st.com>
Add support for new counter device to stm32-lptimer.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/counter/Kconfig | 10 +
drivers/counter/Makefile | 1 +
drivers/{iio => }/counter/stm32-lptimer-cnt.c | 361 ++++++++++++++++--
drivers/iio/Kconfig | 1 -
drivers/iio/Makefile | 1 -
drivers/iio/counter/Kconfig | 17 -
drivers/iio/counter/Makefile | 7 -
7 files changed, 350 insertions(+), 48 deletions(-)
rename drivers/{iio => }/counter/stm32-lptimer-cnt.c (51%)
delete mode 100644 drivers/iio/counter/Kconfig
delete mode 100644 drivers/iio/counter/Makefile
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index 0bb2340d6087..87c491a19c63 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -38,4 +38,14 @@ config STM32_TIMER_CNT
To compile this driver as a module, choose M here: the
module will be called stm32-timer-cnt.
+config STM32_LPTIMER_CNT
+ tristate "STM32 LP Timer encoder counter driver"
+ depends on (MFD_STM32_LPTIMER || COMPILE_TEST) && IIO
+ help
+ Select this option to enable STM32 Low-Power Timer quadrature encoder
+ and counter driver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called stm32-lptimer-cnt.
+
endif # COUNTER
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
index 6b4a5be21b00..5589976d37f8 100644
--- a/drivers/counter/Makefile
+++ b/drivers/counter/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_COUNTER) += counter.o
obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
+obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
diff --git a/drivers/iio/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c
similarity index 51%
rename from drivers/iio/counter/stm32-lptimer-cnt.c
rename to drivers/counter/stm32-lptimer-cnt.c
index 2a49cce0edb4..bbc930a5962c 100644
--- a/drivers/iio/counter/stm32-lptimer-cnt.c
+++ b/drivers/counter/stm32-lptimer-cnt.c
@@ -11,6 +11,7 @@
*/
#include <linux/bitfield.h>
+#include <linux/counter.h>
#include <linux/iio/iio.h>
#include <linux/mfd/stm32-lptimer.h>
#include <linux/module.h>
@@ -18,10 +19,11 @@
#include <linux/platform_device.h>
struct stm32_lptim_cnt {
+ struct counter_device counter;
struct device *dev;
struct regmap *regmap;
struct clk *clk;
- u32 preset;
+ u32 ceiling;
u32 polarity;
u32 quadrature_mode;
bool enabled;
@@ -57,7 +59,7 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
}
/* LP timer must be enabled before writing CMP & ARR */
- ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->preset);
+ ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
if (ret)
return ret;
@@ -251,44 +253,57 @@ static const struct iio_enum stm32_lptim_cnt_polarity_en = {
.set = stm32_lptim_cnt_set_polarity,
};
-static ssize_t stm32_lptim_cnt_get_preset(struct iio_dev *indio_dev,
- uintptr_t private,
- const struct iio_chan_spec *chan,
- char *buf)
+static ssize_t stm32_lptim_cnt_get_ceiling(struct stm32_lptim_cnt *priv,
+ char *buf)
{
- struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
-
- return snprintf(buf, PAGE_SIZE, "%u\n", priv->preset);
+ return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
}
-static ssize_t stm32_lptim_cnt_set_preset(struct iio_dev *indio_dev,
- uintptr_t private,
- const struct iio_chan_spec *chan,
- const char *buf, size_t len)
+static ssize_t stm32_lptim_cnt_set_ceiling(struct stm32_lptim_cnt *priv,
+ const char *buf, size_t len)
{
- struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
int ret;
if (stm32_lptim_is_enabled(priv))
return -EBUSY;
- ret = kstrtouint(buf, 0, &priv->preset);
+ ret = kstrtouint(buf, 0, &priv->ceiling);
if (ret)
return ret;
- if (priv->preset > STM32_LPTIM_MAX_ARR)
+ if (priv->ceiling > STM32_LPTIM_MAX_ARR)
return -EINVAL;
return len;
}
+static ssize_t stm32_lptim_cnt_get_preset_iio(struct iio_dev *indio_dev,
+ uintptr_t private,
+ const struct iio_chan_spec *chan,
+ char *buf)
+{
+ struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
+
+ return stm32_lptim_cnt_get_ceiling(priv, buf);
+}
+
+static ssize_t stm32_lptim_cnt_set_preset_iio(struct iio_dev *indio_dev,
+ uintptr_t private,
+ const struct iio_chan_spec *chan,
+ const char *buf, size_t len)
+{
+ struct stm32_lptim_cnt *priv = iio_priv(indio_dev);
+
+ return stm32_lptim_cnt_set_ceiling(priv, buf, len);
+}
+
/* LP timer with encoder */
static const struct iio_chan_spec_ext_info stm32_lptim_enc_ext_info[] = {
{
.name = "preset",
.shared = IIO_SEPARATE,
- .read = stm32_lptim_cnt_get_preset,
- .write = stm32_lptim_cnt_set_preset,
+ .read = stm32_lptim_cnt_get_preset_iio,
+ .write = stm32_lptim_cnt_set_preset_iio,
},
IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
@@ -313,8 +328,8 @@ static const struct iio_chan_spec_ext_info stm32_lptim_cnt_ext_info[] = {
{
.name = "preset",
.shared = IIO_SEPARATE,
- .read = stm32_lptim_cnt_get_preset,
- .write = stm32_lptim_cnt_set_preset,
+ .read = stm32_lptim_cnt_get_preset_iio,
+ .write = stm32_lptim_cnt_set_preset_iio,
},
IIO_ENUM("polarity", IIO_SEPARATE, &stm32_lptim_cnt_polarity_en),
IIO_ENUM_AVAILABLE("polarity", &stm32_lptim_cnt_polarity_en),
@@ -331,11 +346,293 @@ static const struct iio_chan_spec stm32_lptim_cnt_channels = {
.indexed = 1,
};
+/**
+ * stm32_lptim_cnt_function - enumerates stm32 LPTimer counter & encoder modes
+ * @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
+ * @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
+ */
+enum stm32_lptim_cnt_function {
+ STM32_LPTIM_COUNTER_INCREASE,
+ STM32_LPTIM_ENCODER_BOTH_EDGE,
+};
+
+static enum counter_count_function stm32_lptim_cnt_functions[] = {
+ [STM32_LPTIM_COUNTER_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
+ [STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
+};
+
+enum stm32_lptim_synapse_action {
+ STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
+ STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
+ STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
+ STM32_LPTIM_SYNAPSE_ACTION_NONE,
+};
+
+static enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
+ /* Index must match with stm32_lptim_cnt_polarity[] (priv->polarity) */
+ [STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
+ [STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
+ [STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
+ [STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
+};
+
+static int stm32_lptim_cnt_read(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_count_read_value *val)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+ u32 cnt;
+ int ret;
+
+ ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
+ if (ret)
+ return ret;
+
+ counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt);
+
+ return 0;
+}
+
+static int stm32_lptim_cnt_function_get(struct counter_device *counter,
+ struct counter_count *count,
+ size_t *function)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+
+ if (!priv->quadrature_mode) {
+ *function = STM32_LPTIM_COUNTER_INCREASE;
+ return 0;
+ }
+
+ if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
+ *function = STM32_LPTIM_ENCODER_BOTH_EDGE;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int stm32_lptim_cnt_function_set(struct counter_device *counter,
+ struct counter_count *count,
+ size_t function)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+
+ if (stm32_lptim_is_enabled(priv))
+ return -EBUSY;
+
+ switch (function) {
+ case STM32_LPTIM_COUNTER_INCREASE:
+ priv->quadrature_mode = 0;
+ return 0;
+ case STM32_LPTIM_ENCODER_BOTH_EDGE:
+ priv->quadrature_mode = 1;
+ priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *private, char *buf)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+ int ret;
+
+ ret = stm32_lptim_is_enabled(priv);
+ if (ret < 0)
+ return ret;
+
+ return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
+}
+
+static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
+ struct counter_count *count,
+ void *private,
+ const char *buf, size_t len)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+ bool enable;
+ int ret;
+
+ ret = kstrtobool(buf, &enable);
+ if (ret)
+ return ret;
+
+ /* Check nobody uses the timer, or already disabled/enabled */
+ ret = stm32_lptim_is_enabled(priv);
+ if ((ret < 0) || (!ret && !enable))
+ return ret;
+ if (enable && ret)
+ return -EBUSY;
+
+ ret = stm32_lptim_setup(priv, enable);
+ if (ret)
+ return ret;
+
+ ret = stm32_lptim_set_enable_state(priv, enable);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *private, char *buf)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+
+ return stm32_lptim_cnt_get_ceiling(priv, buf);
+}
+
+static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
+ struct counter_count *count,
+ void *private,
+ const char *buf, size_t len)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+
+ return stm32_lptim_cnt_set_ceiling(priv, buf, len);
+}
+
+static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
+ {
+ .name = "enable",
+ .read = stm32_lptim_cnt_enable_read,
+ .write = stm32_lptim_cnt_enable_write
+ },
+ {
+ .name = "ceiling",
+ .read = stm32_lptim_cnt_ceiling_read,
+ .write = stm32_lptim_cnt_ceiling_write
+ },
+};
+
+static int stm32_lptim_cnt_action_get(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse,
+ size_t *action)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+ size_t function;
+ int err;
+
+ err = stm32_lptim_cnt_function_get(counter, count, &function);
+ if (err)
+ return err;
+
+ switch (function) {
+ case STM32_LPTIM_COUNTER_INCREASE:
+ /* LP Timer acts as up-counter on input 1 */
+ if (synapse->signal->id == count->synapses[0].signal->id)
+ *action = priv->polarity;
+ else
+ *action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
+ return 0;
+ case STM32_LPTIM_ENCODER_BOTH_EDGE:
+ *action = priv->polarity;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int stm32_lptim_cnt_action_set(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse,
+ size_t action)
+{
+ struct stm32_lptim_cnt *const priv = counter->priv;
+ size_t function;
+ int err;
+
+ if (stm32_lptim_is_enabled(priv))
+ return -EBUSY;
+
+ err = stm32_lptim_cnt_function_get(counter, count, &function);
+ if (err)
+ return err;
+
+ /* only set polarity when in counter mode (on input 1) */
+ if (function == STM32_LPTIM_COUNTER_INCREASE
+ && synapse->signal->id == count->synapses[0].signal->id) {
+ switch (action) {
+ case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
+ case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
+ case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
+ priv->polarity = action;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static const struct counter_ops stm32_lptim_cnt_ops = {
+ .count_read = stm32_lptim_cnt_read,
+ .function_get = stm32_lptim_cnt_function_get,
+ .function_set = stm32_lptim_cnt_function_set,
+ .action_get = stm32_lptim_cnt_action_get,
+ .action_set = stm32_lptim_cnt_action_set,
+};
+
+static struct counter_signal stm32_lptim_cnt_signals[] = {
+ {
+ .id = 0,
+ .name = "Channel 1 Quadrature A"
+ },
+ {
+ .id = 1,
+ .name = "Channel 1 Quadrature B"
+ }
+};
+
+static struct counter_synapse stm32_lptim_cnt_synapses[] = {
+ {
+ .actions_list = stm32_lptim_cnt_synapse_actions,
+ .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
+ .signal = &stm32_lptim_cnt_signals[0]
+ },
+ {
+ .actions_list = stm32_lptim_cnt_synapse_actions,
+ .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
+ .signal = &stm32_lptim_cnt_signals[1]
+ }
+};
+
+/* LP timer with encoder */
+static struct counter_count stm32_lptim_enc_counts = {
+ .id = 0,
+ .name = "LPTimer Count",
+ .functions_list = stm32_lptim_cnt_functions,
+ .num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
+ .synapses = stm32_lptim_cnt_synapses,
+ .num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
+ .ext = stm32_lptim_cnt_ext,
+ .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
+};
+
+/* LP timer without encoder (counter only) */
+static struct counter_count stm32_lptim_in1_counts = {
+ .id = 0,
+ .name = "LPTimer Count",
+ .functions_list = stm32_lptim_cnt_functions,
+ .num_functions = 1,
+ .synapses = stm32_lptim_cnt_synapses,
+ .num_synapses = 1,
+ .ext = stm32_lptim_cnt_ext,
+ .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
+};
+
static int stm32_lptim_cnt_probe(struct platform_device *pdev)
{
struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
struct stm32_lptim_cnt *priv;
struct iio_dev *indio_dev;
+ int ret;
if (IS_ERR_OR_NULL(ddata))
return -EINVAL;
@@ -348,8 +645,9 @@ static int stm32_lptim_cnt_probe(struct platform_device *pdev)
priv->dev = &pdev->dev;
priv->regmap = ddata->regmap;
priv->clk = ddata->clk;
- priv->preset = STM32_LPTIM_MAX_ARR;
+ priv->ceiling = STM32_LPTIM_MAX_ARR;
+ /* Initialize IIO device */
indio_dev->name = dev_name(&pdev->dev);
indio_dev->dev.parent = &pdev->dev;
indio_dev->dev.of_node = pdev->dev.of_node;
@@ -360,9 +658,28 @@ static int stm32_lptim_cnt_probe(struct platform_device *pdev)
indio_dev->channels = &stm32_lptim_cnt_channels;
indio_dev->num_channels = 1;
+ /* Initialize Counter device */
+ priv->counter.name = dev_name(&pdev->dev);
+ priv->counter.parent = &pdev->dev;
+ priv->counter.ops = &stm32_lptim_cnt_ops;
+ if (ddata->has_encoder) {
+ priv->counter.counts = &stm32_lptim_enc_counts;
+ priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
+ } else {
+ priv->counter.counts = &stm32_lptim_in1_counts;
+ priv->counter.num_signals = 1;
+ }
+ priv->counter.num_counts = 1;
+ priv->counter.signals = stm32_lptim_cnt_signals;
+ priv->counter.priv = priv;
+
platform_set_drvdata(pdev, priv);
- return devm_iio_device_register(&pdev->dev, indio_dev);
+ ret = devm_iio_device_register(&pdev->dev, indio_dev);
+ if (ret)
+ return ret;
+
+ return devm_counter_register(&pdev->dev, &priv->counter);
}
#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
index 014006d1cbb6..4243e35c25e9 100644
--- a/drivers/iio/Kconfig
+++ b/drivers/iio/Kconfig
@@ -74,7 +74,6 @@ source "drivers/iio/afe/Kconfig"
source "drivers/iio/amplifiers/Kconfig"
source "drivers/iio/chemical/Kconfig"
source "drivers/iio/common/Kconfig"
-source "drivers/iio/counter/Kconfig"
source "drivers/iio/dac/Kconfig"
source "drivers/iio/dummy/Kconfig"
source "drivers/iio/frequency/Kconfig"
diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
index cb5993251381..bff682ad1cfb 100644
--- a/drivers/iio/Makefile
+++ b/drivers/iio/Makefile
@@ -20,7 +20,6 @@ obj-y += amplifiers/
obj-y += buffer/
obj-y += chemical/
obj-y += common/
-obj-y += counter/
obj-y += dac/
obj-y += dummy/
obj-y += gyro/
diff --git a/drivers/iio/counter/Kconfig b/drivers/iio/counter/Kconfig
deleted file mode 100644
index eeb358122cbe..000000000000
--- a/drivers/iio/counter/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Counter devices
-#
-# When adding new entries keep the list in alphabetical order
-
-menu "Counters"
-
-config STM32_LPTIMER_CNT
- tristate "STM32 LP Timer encoder counter driver"
- depends on MFD_STM32_LPTIMER || COMPILE_TEST
- help
- Select this option to enable STM32 Low-Power Timer quadrature encoder
- and counter driver.
-
- To compile this driver as a module, choose M here: the
- module will be called stm32-lptimer-cnt.
-endmenu
diff --git a/drivers/iio/counter/Makefile b/drivers/iio/counter/Makefile
deleted file mode 100644
index 93933ba49280..000000000000
--- a/drivers/iio/counter/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for IIO counter devices
-#
-
-# When adding new entries keep the list in alphabetical order
-
-obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
--
2.21.0
^ permalink raw reply related
* [PATCH v10 08/18] dt-bindings: counter: Document stm32 quadrature encoder
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, Rob Herring, lars,
daniel.lezcano, linux-arm-kernel, devicetree, david,
William Breathitt Gray, robh+dt, tglx, fabrice.gasnier, esben,
shawnguo, linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev,
jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Benjamin Gaignard <benjamin.gaignard@st.com>
Add bindings for STM32 Timer quadrature encoder.
It is a sub-node of STM32 Timer which implement the
quadratic encoder part of the hardware.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
.../bindings/counter/stm32-timer-cnt.txt | 31 +++++++++++++++++++
.../devicetree/bindings/mfd/stm32-timers.txt | 7 +++++
2 files changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
diff --git a/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
new file mode 100644
index 000000000000..c52fcdd4bf6c
--- /dev/null
+++ b/Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
@@ -0,0 +1,31 @@
+STMicroelectronics STM32 Timer quadrature encoder
+
+STM32 Timer provides quadrature encoder to detect
+angular position and direction of rotary elements,
+from IN1 and IN2 input signals.
+
+Must be a sub-node of an STM32 Timer device tree node.
+See ../mfd/stm32-timers.txt for details about the parent node.
+
+Required properties:
+- compatible: Must be "st,stm32-timer-counter".
+- pinctrl-names: Set to "default".
+- pinctrl-0: List of phandles pointing to pin configuration nodes,
+ to set CH1/CH2 pins in mode of operation for STM32
+ Timer input on external pin.
+
+Example:
+ timers@40010000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-timers";
+ reg = <0x40010000 0x400>;
+ clocks = <&rcc 0 160>;
+ clock-names = "int";
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&tim1_in_pins>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mfd/stm32-timers.txt b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
index 0e900b52e895..15c3b87f51d9 100644
--- a/Documentation/devicetree/bindings/mfd/stm32-timers.txt
+++ b/Documentation/devicetree/bindings/mfd/stm32-timers.txt
@@ -28,6 +28,7 @@ Optional parameters:
Optional subnodes:
- pwm: See ../pwm/pwm-stm32.txt
- timer: See ../iio/timer/stm32-timer-trigger.txt
+- counter: See ../counter/stm32-timer-cnt.txt
Example:
timers@40010000 {
@@ -48,6 +49,12 @@ Example:
compatible = "st,stm32-timer-trigger";
reg = <0>;
};
+
+ counter {
+ compatible = "st,stm32-timer-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&tim1_in_pins>;
+ };
};
Example with all dmas:
--
2.21.0
^ permalink raw reply related
* [PATCH v10 07/18] counter: Add STM32 Timer quadrature encoder
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
From: Benjamin Gaignard <benjamin.gaignard@st.com>
Implement counter part of the STM32 timer hardware block by using
counter API. Hardware only supports X2 and X4 quadrature modes. A
ceiling value can be set to define the maximum value reachable by the
counter.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Co-authored-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/counter/Kconfig | 10 +
drivers/counter/Makefile | 1 +
drivers/counter/stm32-timer-cnt.c | 390 ++++++++++++++++++++++++++++++
3 files changed, 401 insertions(+)
create mode 100644 drivers/counter/stm32-timer-cnt.c
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index dd3add729529..0bb2340d6087 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -28,4 +28,14 @@ config 104_QUAD_8
The base port addresses for the devices may be configured via the base
array module parameter.
+config STM32_TIMER_CNT
+ tristate "STM32 Timer encoder counter driver"
+ depends on MFD_STM32_TIMERS || COMPILE_TEST
+ help
+ Select this option to enable STM32 Timer quadrature encoder
+ and counter driver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called stm32-timer-cnt.
+
endif # COUNTER
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
index aee0d2ddcf2c..6b4a5be21b00 100644
--- a/drivers/counter/Makefile
+++ b/drivers/counter/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_COUNTER) += counter.o
obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
+obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
new file mode 100644
index 000000000000..644ba18a72ad
--- /dev/null
+++ b/drivers/counter/stm32-timer-cnt.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * STM32 Timer Encoder and Counter driver
+ *
+ * Copyright (C) STMicroelectronics 2018
+ *
+ * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
+ *
+ */
+#include <linux/counter.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/types.h>
+#include <linux/mfd/stm32-timers.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#define TIM_CCMR_CCXS (BIT(8) | BIT(0))
+#define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
+ TIM_CCMR_IC1F | TIM_CCMR_IC2F)
+#define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
+ TIM_CCER_CC2P | TIM_CCER_CC2NP)
+
+struct stm32_timer_cnt {
+ struct counter_device counter;
+ struct regmap *regmap;
+ struct clk *clk;
+ u32 ceiling;
+};
+
+/**
+ * stm32_count_function - enumerates stm32 timer counter encoder modes
+ * @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1
+ * @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level
+ * @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level
+ * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges
+ */
+enum stm32_count_function {
+ STM32_COUNT_SLAVE_MODE_DISABLED = -1,
+ STM32_COUNT_ENCODER_MODE_1,
+ STM32_COUNT_ENCODER_MODE_2,
+ STM32_COUNT_ENCODER_MODE_3,
+};
+
+static enum counter_count_function stm32_count_functions[] = {
+ [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
+ [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B,
+ [STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
+};
+
+static int stm32_count_read(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_count_read_value *val)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 cnt;
+
+ regmap_read(priv->regmap, TIM_CNT, &cnt);
+ counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt);
+
+ return 0;
+}
+
+static int stm32_count_write(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_count_write_value *val)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 cnt;
+ int err;
+
+ err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val);
+ if (err)
+ return err;
+
+ if (cnt > priv->ceiling)
+ return -EINVAL;
+
+ return regmap_write(priv->regmap, TIM_CNT, cnt);
+}
+
+static int stm32_count_function_get(struct counter_device *counter,
+ struct counter_count *count,
+ size_t *function)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 smcr;
+
+ regmap_read(priv->regmap, TIM_SMCR, &smcr);
+
+ switch (smcr & TIM_SMCR_SMS) {
+ case 1:
+ *function = STM32_COUNT_ENCODER_MODE_1;
+ return 0;
+ case 2:
+ *function = STM32_COUNT_ENCODER_MODE_2;
+ return 0;
+ case 3:
+ *function = STM32_COUNT_ENCODER_MODE_3;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int stm32_count_function_set(struct counter_device *counter,
+ struct counter_count *count,
+ size_t function)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 cr1, sms;
+
+ switch (function) {
+ case STM32_COUNT_ENCODER_MODE_1:
+ sms = 1;
+ break;
+ case STM32_COUNT_ENCODER_MODE_2:
+ sms = 2;
+ break;
+ case STM32_COUNT_ENCODER_MODE_3:
+ sms = 3;
+ break;
+ default:
+ sms = 0;
+ break;
+ }
+
+ /* Store enable status */
+ regmap_read(priv->regmap, TIM_CR1, &cr1);
+
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+
+ /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
+ regmap_write(priv->regmap, TIM_ARR, priv->ceiling);
+
+ regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
+
+ /* Make sure that registers are updated */
+ regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+
+ /* Restore the enable status */
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
+
+ return 0;
+}
+
+static ssize_t stm32_count_direction_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *private, char *buf)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ const char *direction;
+ u32 cr1;
+
+ regmap_read(priv->regmap, TIM_CR1, &cr1);
+ direction = (cr1 & TIM_CR1_DIR) ? "backward" : "forward";
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n", direction);
+}
+
+static ssize_t stm32_count_ceiling_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *private, char *buf)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 arr;
+
+ regmap_read(priv->regmap, TIM_ARR, &arr);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", arr);
+}
+
+static ssize_t stm32_count_ceiling_write(struct counter_device *counter,
+ struct counter_count *count,
+ void *private,
+ const char *buf, size_t len)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ unsigned int ceiling;
+ int ret;
+
+ ret = kstrtouint(buf, 0, &ceiling);
+ if (ret)
+ return ret;
+
+ /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
+ regmap_write(priv->regmap, TIM_ARR, ceiling);
+
+ priv->ceiling = ceiling;
+ return len;
+}
+
+static ssize_t stm32_count_enable_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *private, char *buf)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ u32 cr1;
+
+ regmap_read(priv->regmap, TIM_CR1, &cr1);
+
+ return scnprintf(buf, PAGE_SIZE, "%d\n", (bool)(cr1 & TIM_CR1_CEN));
+}
+
+static ssize_t stm32_count_enable_write(struct counter_device *counter,
+ struct counter_count *count,
+ void *private,
+ const char *buf, size_t len)
+{
+ struct stm32_timer_cnt *const priv = counter->priv;
+ int err;
+ u32 cr1;
+ bool enable;
+
+ err = kstrtobool(buf, &enable);
+ if (err)
+ return err;
+
+ if (enable) {
+ regmap_read(priv->regmap, TIM_CR1, &cr1);
+ if (!(cr1 & TIM_CR1_CEN))
+ clk_enable(priv->clk);
+
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
+ TIM_CR1_CEN);
+ } else {
+ regmap_read(priv->regmap, TIM_CR1, &cr1);
+ regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+ if (cr1 & TIM_CR1_CEN)
+ clk_disable(priv->clk);
+ }
+
+ return len;
+}
+
+static const struct counter_count_ext stm32_count_ext[] = {
+ {
+ .name = "direction",
+ .read = stm32_count_direction_read,
+ },
+ {
+ .name = "enable",
+ .read = stm32_count_enable_read,
+ .write = stm32_count_enable_write
+ },
+ {
+ .name = "ceiling",
+ .read = stm32_count_ceiling_read,
+ .write = stm32_count_ceiling_write
+ },
+};
+
+enum stm32_synapse_action {
+ STM32_SYNAPSE_ACTION_NONE,
+ STM32_SYNAPSE_ACTION_BOTH_EDGES
+};
+
+static enum counter_synapse_action stm32_synapse_actions[] = {
+ [STM32_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
+ [STM32_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
+};
+
+static int stm32_action_get(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse,
+ size_t *action)
+{
+ size_t function;
+ int err;
+
+ /* Default action mode (e.g. STM32_COUNT_SLAVE_MODE_DISABLED) */
+ *action = STM32_SYNAPSE_ACTION_NONE;
+
+ err = stm32_count_function_get(counter, count, &function);
+ if (err)
+ return 0;
+
+ switch (function) {
+ case STM32_COUNT_ENCODER_MODE_1:
+ /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
+ if (synapse->signal->id == count->synapses[0].signal->id)
+ *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
+ break;
+ case STM32_COUNT_ENCODER_MODE_2:
+ /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
+ if (synapse->signal->id == count->synapses[1].signal->id)
+ *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
+ break;
+ case STM32_COUNT_ENCODER_MODE_3:
+ /* counts up/down on both TI1FP1 and TI2FP2 edges */
+ *action = STM32_SYNAPSE_ACTION_BOTH_EDGES;
+ break;
+ }
+
+ return 0;
+}
+
+static const struct counter_ops stm32_timer_cnt_ops = {
+ .count_read = stm32_count_read,
+ .count_write = stm32_count_write,
+ .function_get = stm32_count_function_get,
+ .function_set = stm32_count_function_set,
+ .action_get = stm32_action_get,
+};
+
+static struct counter_signal stm32_signals[] = {
+ {
+ .id = 0,
+ .name = "Channel 1 Quadrature A"
+ },
+ {
+ .id = 1,
+ .name = "Channel 1 Quadrature B"
+ }
+};
+
+static struct counter_synapse stm32_count_synapses[] = {
+ {
+ .actions_list = stm32_synapse_actions,
+ .num_actions = ARRAY_SIZE(stm32_synapse_actions),
+ .signal = &stm32_signals[0]
+ },
+ {
+ .actions_list = stm32_synapse_actions,
+ .num_actions = ARRAY_SIZE(stm32_synapse_actions),
+ .signal = &stm32_signals[1]
+ }
+};
+
+static struct counter_count stm32_counts = {
+ .id = 0,
+ .name = "Channel 1 Count",
+ .functions_list = stm32_count_functions,
+ .num_functions = ARRAY_SIZE(stm32_count_functions),
+ .synapses = stm32_count_synapses,
+ .num_synapses = ARRAY_SIZE(stm32_count_synapses),
+ .ext = stm32_count_ext,
+ .num_ext = ARRAY_SIZE(stm32_count_ext)
+};
+
+static int stm32_timer_cnt_probe(struct platform_device *pdev)
+{
+ struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
+ struct device *dev = &pdev->dev;
+ struct stm32_timer_cnt *priv;
+
+ if (IS_ERR_OR_NULL(ddata))
+ return -EINVAL;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->regmap = ddata->regmap;
+ priv->clk = ddata->clk;
+ priv->ceiling = ddata->max_arr;
+
+ priv->counter.name = dev_name(dev);
+ priv->counter.parent = dev;
+ priv->counter.ops = &stm32_timer_cnt_ops;
+ priv->counter.counts = &stm32_counts;
+ priv->counter.num_counts = 1;
+ priv->counter.signals = stm32_signals;
+ priv->counter.num_signals = ARRAY_SIZE(stm32_signals);
+ priv->counter.priv = priv;
+
+ /* Register Counter device */
+ return devm_counter_register(dev, &priv->counter);
+}
+
+static const struct of_device_id stm32_timer_cnt_of_match[] = {
+ { .compatible = "st,stm32-timer-counter", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
+
+static struct platform_driver stm32_timer_cnt_driver = {
+ .probe = stm32_timer_cnt_probe,
+ .driver = {
+ .name = "stm32-timer-counter",
+ .of_match_table = stm32_timer_cnt_of_match,
+ },
+};
+module_platform_driver(stm32_timer_cnt_driver);
+
+MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
+MODULE_ALIAS("platform:stm32-timer-counter");
+MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
+MODULE_LICENSE("GPL v2");
--
2.21.0
^ permalink raw reply related
* [PATCH v10 06/18] counter: 104-quad-8: Documentation: Add Generic Counter sysfs documentation
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch adds standard documentation for the Generic Counter interface
userspace sysfs attributes of the 104-QUAD-8 driver.
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
.../ABI/testing/sysfs-bus-counter-104-quad-8 | 36 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 37 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-counter-104-quad-8
diff --git a/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8 b/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8
new file mode 100644
index 000000000000..46b1f33b2fce
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-counter-104-quad-8
@@ -0,0 +1,36 @@
+What: /sys/bus/counter/devices/counterX/signalY/index_polarity
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Active level of index input Signal Y; irrelevant in
+ non-synchronous load mode.
+
+What: /sys/bus/counter/devices/counterX/signalY/index_polarity_available
+What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode_available
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Discrete set of available values for the respective Signal Y
+ configuration are listed in this file.
+
+What: /sys/bus/counter/devices/counterX/signalY/synchronous_mode
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Configure the counter associated with Signal Y for
+ non-synchronous or synchronous load mode. Synchronous load mode
+ cannot be selected in non-quadrature (Pulse-Direction) clock
+ mode.
+
+ non-synchronous:
+ A logic low level is the active level at this index
+ input. The index function (as enabled via preset_enable)
+ is performed directly on the active level of the index
+ input.
+
+ synchronous:
+ Intended for interfacing with encoder Index output in
+ quadrature clock mode. The active level is configured
+ via index_polarity. The index function (as enabled via
+ preset_enable) is performed synchronously with the
+ quadrature clock on the active level of the index input.
diff --git a/MAINTAINERS b/MAINTAINERS
index 663e7a62752a..d3d93a5d3b10 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -272,6 +272,7 @@ ACCES 104-QUAD-8 DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
+F: Documentation/ABI/testing/sysfs-bus-counter-104-quad-8
F: Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
F: drivers/counter/104-quad-8.c
--
2.21.0
^ permalink raw reply related
* [PATCH v10 05/18] counter: 104-quad-8: Add Generic Counter interface support
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch adds support for the Generic Counter interface to the
104-QUAD-8 driver. The existing 104-QUAD-8 device interface should not
be affected by this patch; all changes are intended as supplemental
additions as perceived by the user.
Generic Counter Counts are created for the eight quadrature channel
counts, as well as their respective quadrature A and B Signals (which
are associated via respective Synapse structures) and respective index
Signals.
The new Generic Counter interface sysfs attributes are intended to
expose the same functionality and data available via the existing
104-QUAD-8 IIO device interface; the Generic Counter interface serves
to provide the respective functionality and data in a standard way
expected of counter devices.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
MAINTAINERS | 4 +-
drivers/{iio => }/counter/104-quad-8.c | 772 ++++++++++++++++++++++++-
drivers/counter/Kconfig | 21 +
drivers/counter/Makefile | 2 +
drivers/iio/counter/Kconfig | 17 -
drivers/iio/counter/Makefile | 1 -
6 files changed, 783 insertions(+), 34 deletions(-)
rename drivers/{iio => }/counter/104-quad-8.c (44%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 208c92ff4801..663e7a62752a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -268,12 +268,12 @@ L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/gpio/gpio-104-idio-16.c
-ACCES 104-QUAD-8 IIO DRIVER
+ACCES 104-QUAD-8 DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
-F: drivers/iio/counter/104-quad-8.c
+F: drivers/counter/104-quad-8.c
ACCES PCI-IDIO-16 GPIO DRIVER
M: William Breathitt Gray <vilhelm.gray@gmail.com>
diff --git a/drivers/iio/counter/104-quad-8.c b/drivers/counter/104-quad-8.c
similarity index 44%
rename from drivers/iio/counter/104-quad-8.c
rename to drivers/counter/104-quad-8.c
index 72b6352e09f0..4fa2931dcb7b 100644
--- a/drivers/iio/counter/104-quad-8.c
+++ b/drivers/counter/104-quad-8.c
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * IIO driver for the ACCES 104-QUAD-8
+ * Counter driver for the ACCES 104-QUAD-8
* Copyright (C) 2016 William Breathitt Gray
*
* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
*/
#include <linux/bitops.h>
+#include <linux/counter.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/iio/iio.h>
@@ -29,6 +30,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
/**
* struct quad8_iio - IIO device private data structure
+ * @counter: instance of the counter_device
* @preset: array of preset values
* @count_mode: array of count mode configurations
* @quadrature_mode: array of quadrature mode configurations
@@ -40,6 +42,7 @@ MODULE_PARM_DESC(base, "ACCES 104-QUAD-8 base addresses");
* @base: base port address of the IIO device
*/
struct quad8_iio {
+ struct counter_device counter;
unsigned int preset[QUAD8_NUM_COUNTERS];
unsigned int count_mode[QUAD8_NUM_COUNTERS];
unsigned int quadrature_mode[QUAD8_NUM_COUNTERS];
@@ -83,6 +86,10 @@ struct quad8_iio {
#define QUAD8_RLD_CNTR_OUT 0x10
#define QUAD8_CHAN_OP_ENABLE_COUNTERS 0x00
#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
+#define QUAD8_CMR_QUADRATURE_X1 0x08
+#define QUAD8_CMR_QUADRATURE_X2 0x10
+#define QUAD8_CMR_QUADRATURE_X4 0x18
+
static int quad8_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val, int *val2, long mask)
@@ -338,13 +345,13 @@ static const char *const quad8_count_modes[] = {
};
static int quad8_set_count_mode(struct iio_dev *indio_dev,
- const struct iio_chan_spec *chan, unsigned int count_mode)
+ const struct iio_chan_spec *chan, unsigned int cnt_mode)
{
struct quad8_iio *const priv = iio_priv(indio_dev);
- unsigned int mode_cfg = count_mode << 1;
+ unsigned int mode_cfg = cnt_mode << 1;
const int base_offset = priv->base + 2 * chan->channel + 1;
- priv->count_mode[chan->channel] = count_mode;
+ priv->count_mode[chan->channel] = cnt_mode;
/* Add quadrature mode configuration */
if (priv->quadrature_mode[chan->channel])
@@ -554,24 +561,746 @@ static const struct iio_chan_spec quad8_channels[] = {
QUAD8_COUNT_CHAN(7), QUAD8_INDEX_CHAN(7)
};
+static int quad8_signal_read(struct counter_device *counter,
+ struct counter_signal *signal, struct counter_signal_read_value *val)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ unsigned int state;
+ enum counter_signal_level level;
+
+ /* Only Index signal levels can be read */
+ if (signal->id < 16)
+ return -EINVAL;
+
+ state = inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS)
+ & BIT(signal->id - 16);
+
+ level = (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW;
+
+ counter_signal_read_value_set(val, COUNTER_SIGNAL_LEVEL, &level);
+
+ return 0;
+}
+
+static int quad8_count_read(struct counter_device *counter,
+ struct counter_count *count, struct counter_count_read_value *val)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id;
+ unsigned int flags;
+ unsigned int borrow;
+ unsigned int carry;
+ unsigned long position;
+ int i;
+
+ flags = inb(base_offset + 1);
+ borrow = flags & QUAD8_FLAG_BT;
+ carry = !!(flags & QUAD8_FLAG_CT);
+
+ /* Borrow XOR Carry effectively doubles count range */
+ position = (unsigned long)(borrow ^ carry) << 24;
+
+ /* Reset Byte Pointer; transfer Counter to Output Latch */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
+ base_offset + 1);
+
+ for (i = 0; i < 3; i++)
+ position |= (unsigned long)inb(base_offset) << (8 * i);
+
+ counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &position);
+
+ return 0;
+}
+
+static int quad8_count_write(struct counter_device *counter,
+ struct counter_count *count, struct counter_count_write_value *val)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id;
+ int err;
+ unsigned long position;
+ int i;
+
+ err = counter_count_write_value_get(&position, COUNTER_COUNT_POSITION,
+ val);
+ if (err)
+ return err;
+
+ /* Only 24-bit values are supported */
+ if (position > 0xFFFFFF)
+ return -EINVAL;
+
+ /* Reset Byte Pointer */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+
+ /* Counter can only be set via Preset Register */
+ for (i = 0; i < 3; i++)
+ outb(position >> (8 * i), base_offset);
+
+ /* Transfer Preset Register to Counter */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1);
+
+ /* Reset Byte Pointer */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+
+ /* Set Preset Register back to original value */
+ position = priv->preset[count->id];
+ for (i = 0; i < 3; i++)
+ outb(position >> (8 * i), base_offset);
+
+ /* Reset Borrow, Carry, Compare, and Sign flags */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1);
+ /* Reset Error flag */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1);
+
+ return 0;
+}
+
+enum quad8_count_function {
+ QUAD8_COUNT_FUNCTION_PULSE_DIRECTION = 0,
+ QUAD8_COUNT_FUNCTION_QUADRATURE_X1,
+ QUAD8_COUNT_FUNCTION_QUADRATURE_X2,
+ QUAD8_COUNT_FUNCTION_QUADRATURE_X4
+};
+
+static enum counter_count_function quad8_count_functions_list[] = {
+ [QUAD8_COUNT_FUNCTION_PULSE_DIRECTION] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION,
+ [QUAD8_COUNT_FUNCTION_QUADRATURE_X1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A,
+ [QUAD8_COUNT_FUNCTION_QUADRATURE_X2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
+ [QUAD8_COUNT_FUNCTION_QUADRATURE_X4] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4
+};
+
+static int quad8_function_get(struct counter_device *counter,
+ struct counter_count *count, size_t *function)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const int id = count->id;
+ const unsigned int quadrature_mode = priv->quadrature_mode[id];
+ const unsigned int scale = priv->quadrature_scale[id];
+
+ if (quadrature_mode)
+ switch (scale) {
+ case 0:
+ *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X1;
+ break;
+ case 1:
+ *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X2;
+ break;
+ case 2:
+ *function = QUAD8_COUNT_FUNCTION_QUADRATURE_X4;
+ break;
+ }
+ else
+ *function = QUAD8_COUNT_FUNCTION_PULSE_DIRECTION;
+
+ return 0;
+}
+
+static int quad8_function_set(struct counter_device *counter,
+ struct counter_count *count, size_t function)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const int id = count->id;
+ unsigned int *const quadrature_mode = priv->quadrature_mode + id;
+ unsigned int *const scale = priv->quadrature_scale + id;
+ unsigned int mode_cfg = priv->count_mode[id] << 1;
+ unsigned int *const synchronous_mode = priv->synchronous_mode + id;
+ const unsigned int idr_cfg = priv->index_polarity[id] << 1;
+ const int base_offset = priv->base + 2 * id + 1;
+
+ if (function == QUAD8_COUNT_FUNCTION_PULSE_DIRECTION) {
+ *quadrature_mode = 0;
+
+ /* Quadrature scaling only available in quadrature mode */
+ *scale = 0;
+
+ /* Synchronous function not supported in non-quadrature mode */
+ if (*synchronous_mode) {
+ *synchronous_mode = 0;
+ /* Disable synchronous function mode */
+ outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
+ }
+ } else {
+ *quadrature_mode = 1;
+
+ switch (function) {
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
+ *scale = 0;
+ mode_cfg |= QUAD8_CMR_QUADRATURE_X1;
+ break;
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
+ *scale = 1;
+ mode_cfg |= QUAD8_CMR_QUADRATURE_X2;
+ break;
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
+ *scale = 2;
+ mode_cfg |= QUAD8_CMR_QUADRATURE_X4;
+ break;
+ }
+ }
+
+ /* Load mode configuration to Counter Mode Register */
+ outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
+
+ return 0;
+}
+
+static void quad8_direction_get(struct counter_device *counter,
+ struct counter_count *count, enum counter_count_direction *direction)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ unsigned int ud_flag;
+ const unsigned int flag_addr = priv->base + 2 * count->id + 1;
+
+ /* U/D flag: nonzero = up, zero = down */
+ ud_flag = inb(flag_addr) & QUAD8_FLAG_UD;
+
+ *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
+ COUNTER_COUNT_DIRECTION_BACKWARD;
+}
+
+enum quad8_synapse_action {
+ QUAD8_SYNAPSE_ACTION_NONE = 0,
+ QUAD8_SYNAPSE_ACTION_RISING_EDGE,
+ QUAD8_SYNAPSE_ACTION_FALLING_EDGE,
+ QUAD8_SYNAPSE_ACTION_BOTH_EDGES
+};
+
+static enum counter_synapse_action quad8_index_actions_list[] = {
+ [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
+ [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE
+};
+
+static enum counter_synapse_action quad8_synapse_actions_list[] = {
+ [QUAD8_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
+ [QUAD8_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
+ [QUAD8_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
+ [QUAD8_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES
+};
+
+static int quad8_action_get(struct counter_device *counter,
+ struct counter_count *count, struct counter_synapse *synapse,
+ size_t *action)
+{
+ struct quad8_iio *const priv = counter->priv;
+ int err;
+ size_t function = 0;
+ const size_t signal_a_id = count->synapses[0].signal->id;
+ enum counter_count_direction direction;
+
+ /* Handle Index signals */
+ if (synapse->signal->id >= 16) {
+ if (priv->preset_enable[count->id])
+ *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
+ else
+ *action = QUAD8_SYNAPSE_ACTION_NONE;
+
+ return 0;
+ }
+
+ err = quad8_function_get(counter, count, &function);
+ if (err)
+ return err;
+
+ /* Default action mode */
+ *action = QUAD8_SYNAPSE_ACTION_NONE;
+
+ /* Determine action mode based on current count function mode */
+ switch (function) {
+ case QUAD8_COUNT_FUNCTION_PULSE_DIRECTION:
+ if (synapse->signal->id == signal_a_id)
+ *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
+ break;
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X1:
+ if (synapse->signal->id == signal_a_id) {
+ quad8_direction_get(counter, count, &direction);
+
+ if (direction == COUNTER_COUNT_DIRECTION_FORWARD)
+ *action = QUAD8_SYNAPSE_ACTION_RISING_EDGE;
+ else
+ *action = QUAD8_SYNAPSE_ACTION_FALLING_EDGE;
+ }
+ break;
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X2:
+ if (synapse->signal->id == signal_a_id)
+ *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
+ break;
+ case QUAD8_COUNT_FUNCTION_QUADRATURE_X4:
+ *action = QUAD8_SYNAPSE_ACTION_BOTH_EDGES;
+ break;
+ }
+
+ return 0;
+}
+
+const struct counter_ops quad8_ops = {
+ .signal_read = quad8_signal_read,
+ .count_read = quad8_count_read,
+ .count_write = quad8_count_write,
+ .function_get = quad8_function_get,
+ .function_set = quad8_function_set,
+ .action_get = quad8_action_get
+};
+
+static int quad8_index_polarity_get(struct counter_device *counter,
+ struct counter_signal *signal, size_t *index_polarity)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const size_t channel_id = signal->id - 16;
+
+ *index_polarity = priv->index_polarity[channel_id];
+
+ return 0;
+}
+
+static int quad8_index_polarity_set(struct counter_device *counter,
+ struct counter_signal *signal, size_t index_polarity)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const size_t channel_id = signal->id - 16;
+ const unsigned int idr_cfg = priv->synchronous_mode[channel_id] |
+ index_polarity << 1;
+ const int base_offset = priv->base + 2 * channel_id + 1;
+
+ priv->index_polarity[channel_id] = index_polarity;
+
+ /* Load Index Control configuration to Index Control Register */
+ outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
+
+ return 0;
+}
+
+static struct counter_signal_enum_ext quad8_index_pol_enum = {
+ .items = quad8_index_polarity_modes,
+ .num_items = ARRAY_SIZE(quad8_index_polarity_modes),
+ .get = quad8_index_polarity_get,
+ .set = quad8_index_polarity_set
+};
+
+static int quad8_synchronous_mode_get(struct counter_device *counter,
+ struct counter_signal *signal, size_t *synchronous_mode)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const size_t channel_id = signal->id - 16;
+
+ *synchronous_mode = priv->synchronous_mode[channel_id];
+
+ return 0;
+}
+
+static int quad8_synchronous_mode_set(struct counter_device *counter,
+ struct counter_signal *signal, size_t synchronous_mode)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const size_t channel_id = signal->id - 16;
+ const unsigned int idr_cfg = synchronous_mode |
+ priv->index_polarity[channel_id] << 1;
+ const int base_offset = priv->base + 2 * channel_id + 1;
+
+ /* Index function must be non-synchronous in non-quadrature mode */
+ if (synchronous_mode && !priv->quadrature_mode[channel_id])
+ return -EINVAL;
+
+ priv->synchronous_mode[channel_id] = synchronous_mode;
+
+ /* Load Index Control configuration to Index Control Register */
+ outb(QUAD8_CTR_IDR | idr_cfg, base_offset);
+
+ return 0;
+}
+
+static struct counter_signal_enum_ext quad8_syn_mode_enum = {
+ .items = quad8_synchronous_modes,
+ .num_items = ARRAY_SIZE(quad8_synchronous_modes),
+ .get = quad8_synchronous_mode_get,
+ .set = quad8_synchronous_mode_set
+};
+
+static ssize_t quad8_count_floor_read(struct counter_device *counter,
+ struct counter_count *count, void *private, char *buf)
+{
+ /* Only a floor of 0 is supported */
+ return sprintf(buf, "0\n");
+}
+
+static int quad8_count_mode_get(struct counter_device *counter,
+ struct counter_count *count, size_t *cnt_mode)
+{
+ const struct quad8_iio *const priv = counter->priv;
+
+ /* Map 104-QUAD-8 count mode to Generic Counter count mode */
+ switch (priv->count_mode[count->id]) {
+ case 0:
+ *cnt_mode = COUNTER_COUNT_MODE_NORMAL;
+ break;
+ case 1:
+ *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
+ break;
+ case 2:
+ *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
+ break;
+ case 3:
+ *cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
+ break;
+ }
+
+ return 0;
+}
+
+static int quad8_count_mode_set(struct counter_device *counter,
+ struct counter_count *count, size_t cnt_mode)
+{
+ struct quad8_iio *const priv = counter->priv;
+ unsigned int mode_cfg;
+ const int base_offset = priv->base + 2 * count->id + 1;
+
+ /* Map Generic Counter count mode to 104-QUAD-8 count mode */
+ switch (cnt_mode) {
+ case COUNTER_COUNT_MODE_NORMAL:
+ cnt_mode = 0;
+ break;
+ case COUNTER_COUNT_MODE_RANGE_LIMIT:
+ cnt_mode = 1;
+ break;
+ case COUNTER_COUNT_MODE_NON_RECYCLE:
+ cnt_mode = 2;
+ break;
+ case COUNTER_COUNT_MODE_MODULO_N:
+ cnt_mode = 3;
+ break;
+ }
+
+ priv->count_mode[count->id] = cnt_mode;
+
+ /* Set count mode configuration value */
+ mode_cfg = cnt_mode << 1;
+
+ /* Add quadrature mode configuration */
+ if (priv->quadrature_mode[count->id])
+ mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3;
+
+ /* Load mode configuration to Counter Mode Register */
+ outb(QUAD8_CTR_CMR | mode_cfg, base_offset);
+
+ return 0;
+}
+
+static struct counter_count_enum_ext quad8_cnt_mode_enum = {
+ .items = counter_count_mode_str,
+ .num_items = ARRAY_SIZE(counter_count_mode_str),
+ .get = quad8_count_mode_get,
+ .set = quad8_count_mode_set
+};
+
+static ssize_t quad8_count_direction_read(struct counter_device *counter,
+ struct counter_count *count, void *priv, char *buf)
+{
+ enum counter_count_direction dir;
+
+ quad8_direction_get(counter, count, &dir);
+
+ return sprintf(buf, "%s\n", counter_count_direction_str[dir]);
+}
+
+static ssize_t quad8_count_enable_read(struct counter_device *counter,
+ struct counter_count *count, void *private, char *buf)
+{
+ const struct quad8_iio *const priv = counter->priv;
+
+ return sprintf(buf, "%u\n", priv->ab_enable[count->id]);
+}
+
+static ssize_t quad8_count_enable_write(struct counter_device *counter,
+ struct counter_count *count, void *private, const char *buf, size_t len)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id;
+ int err;
+ bool ab_enable;
+ unsigned int ior_cfg;
+
+ err = kstrtobool(buf, &ab_enable);
+ if (err)
+ return err;
+
+ priv->ab_enable[count->id] = ab_enable;
+
+ ior_cfg = ab_enable | priv->preset_enable[count->id] << 1;
+
+ /* Load I/O control configuration */
+ outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1);
+
+ return len;
+}
+
+static int quad8_error_noise_get(struct counter_device *counter,
+ struct counter_count *count, size_t *noise_error)
+{
+ const struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id + 1;
+
+ *noise_error = !!(inb(base_offset) & QUAD8_FLAG_E);
+
+ return 0;
+}
+
+static struct counter_count_enum_ext quad8_error_noise_enum = {
+ .items = quad8_noise_error_states,
+ .num_items = ARRAY_SIZE(quad8_noise_error_states),
+ .get = quad8_error_noise_get
+};
+
+static ssize_t quad8_count_preset_read(struct counter_device *counter,
+ struct counter_count *count, void *private, char *buf)
+{
+ const struct quad8_iio *const priv = counter->priv;
+
+ return sprintf(buf, "%u\n", priv->preset[count->id]);
+}
+
+static ssize_t quad8_count_preset_write(struct counter_device *counter,
+ struct counter_count *count, void *private, const char *buf, size_t len)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id;
+ unsigned int preset;
+ int ret;
+ int i;
+
+ ret = kstrtouint(buf, 0, &preset);
+ if (ret)
+ return ret;
+
+ /* Only 24-bit values are supported */
+ if (preset > 0xFFFFFF)
+ return -EINVAL;
+
+ priv->preset[count->id] = preset;
+
+ /* Reset Byte Pointer */
+ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1);
+
+ /* Set Preset Register */
+ for (i = 0; i < 3; i++)
+ outb(preset >> (8 * i), base_offset);
+
+ return len;
+}
+
+static ssize_t quad8_count_ceiling_read(struct counter_device *counter,
+ struct counter_count *count, void *private, char *buf)
+{
+ const struct quad8_iio *const priv = counter->priv;
+
+ /* Range Limit and Modulo-N count modes use preset value as ceiling */
+ switch (priv->count_mode[count->id]) {
+ case 1:
+ case 3:
+ return quad8_count_preset_read(counter, count, private, buf);
+ }
+
+ /* By default 0x1FFFFFF (25 bits unsigned) is maximum count */
+ return sprintf(buf, "33554431\n");
+}
+
+static ssize_t quad8_count_ceiling_write(struct counter_device *counter,
+ struct counter_count *count, void *private, const char *buf, size_t len)
+{
+ struct quad8_iio *const priv = counter->priv;
+
+ /* Range Limit and Modulo-N count modes use preset value as ceiling */
+ switch (priv->count_mode[count->id]) {
+ case 1:
+ case 3:
+ return quad8_count_preset_write(counter, count, private, buf,
+ len);
+ }
+
+ return len;
+}
+
+static ssize_t quad8_count_preset_enable_read(struct counter_device *counter,
+ struct counter_count *count, void *private, char *buf)
+{
+ const struct quad8_iio *const priv = counter->priv;
+
+ return sprintf(buf, "%u\n", !priv->preset_enable[count->id]);
+}
+
+static ssize_t quad8_count_preset_enable_write(struct counter_device *counter,
+ struct counter_count *count, void *private, const char *buf, size_t len)
+{
+ struct quad8_iio *const priv = counter->priv;
+ const int base_offset = priv->base + 2 * count->id + 1;
+ bool preset_enable;
+ int ret;
+ unsigned int ior_cfg;
+
+ ret = kstrtobool(buf, &preset_enable);
+ if (ret)
+ return ret;
+
+ /* Preset enable is active low in Input/Output Control register */
+ preset_enable = !preset_enable;
+
+ priv->preset_enable[count->id] = preset_enable;
+
+ ior_cfg = priv->ab_enable[count->id] | (unsigned int)preset_enable << 1;
+
+ /* Load I/O control configuration to Input / Output Control Register */
+ outb(QUAD8_CTR_IOR | ior_cfg, base_offset);
+
+ return len;
+}
+
+static const struct counter_signal_ext quad8_index_ext[] = {
+ COUNTER_SIGNAL_ENUM("index_polarity", &quad8_index_pol_enum),
+ COUNTER_SIGNAL_ENUM_AVAILABLE("index_polarity", &quad8_index_pol_enum),
+ COUNTER_SIGNAL_ENUM("synchronous_mode", &quad8_syn_mode_enum),
+ COUNTER_SIGNAL_ENUM_AVAILABLE("synchronous_mode", &quad8_syn_mode_enum)
+};
+
+#define QUAD8_QUAD_SIGNAL(_id, _name) { \
+ .id = (_id), \
+ .name = (_name) \
+}
+
+#define QUAD8_INDEX_SIGNAL(_id, _name) { \
+ .id = (_id), \
+ .name = (_name), \
+ .ext = quad8_index_ext, \
+ .num_ext = ARRAY_SIZE(quad8_index_ext) \
+}
+
+static struct counter_signal quad8_signals[] = {
+ QUAD8_QUAD_SIGNAL(0, "Channel 1 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(1, "Channel 1 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(2, "Channel 2 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(3, "Channel 2 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(4, "Channel 3 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(5, "Channel 3 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(6, "Channel 4 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(7, "Channel 4 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(8, "Channel 5 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(9, "Channel 5 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(10, "Channel 6 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(11, "Channel 6 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(12, "Channel 7 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(13, "Channel 7 Quadrature B"),
+ QUAD8_QUAD_SIGNAL(14, "Channel 8 Quadrature A"),
+ QUAD8_QUAD_SIGNAL(15, "Channel 8 Quadrature B"),
+ QUAD8_INDEX_SIGNAL(16, "Channel 1 Index"),
+ QUAD8_INDEX_SIGNAL(17, "Channel 2 Index"),
+ QUAD8_INDEX_SIGNAL(18, "Channel 3 Index"),
+ QUAD8_INDEX_SIGNAL(19, "Channel 4 Index"),
+ QUAD8_INDEX_SIGNAL(20, "Channel 5 Index"),
+ QUAD8_INDEX_SIGNAL(21, "Channel 6 Index"),
+ QUAD8_INDEX_SIGNAL(22, "Channel 7 Index"),
+ QUAD8_INDEX_SIGNAL(23, "Channel 8 Index")
+};
+
+#define QUAD8_COUNT_SYNAPSES(_id) { \
+ { \
+ .actions_list = quad8_synapse_actions_list, \
+ .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
+ .signal = quad8_signals + 2 * (_id) \
+ }, \
+ { \
+ .actions_list = quad8_synapse_actions_list, \
+ .num_actions = ARRAY_SIZE(quad8_synapse_actions_list), \
+ .signal = quad8_signals + 2 * (_id) + 1 \
+ }, \
+ { \
+ .actions_list = quad8_index_actions_list, \
+ .num_actions = ARRAY_SIZE(quad8_index_actions_list), \
+ .signal = quad8_signals + 2 * (_id) + 16 \
+ } \
+}
+
+static struct counter_synapse quad8_count_synapses[][3] = {
+ QUAD8_COUNT_SYNAPSES(0), QUAD8_COUNT_SYNAPSES(1),
+ QUAD8_COUNT_SYNAPSES(2), QUAD8_COUNT_SYNAPSES(3),
+ QUAD8_COUNT_SYNAPSES(4), QUAD8_COUNT_SYNAPSES(5),
+ QUAD8_COUNT_SYNAPSES(6), QUAD8_COUNT_SYNAPSES(7)
+};
+
+static const struct counter_count_ext quad8_count_ext[] = {
+ {
+ .name = "ceiling",
+ .read = quad8_count_ceiling_read,
+ .write = quad8_count_ceiling_write
+ },
+ {
+ .name = "floor",
+ .read = quad8_count_floor_read
+ },
+ COUNTER_COUNT_ENUM("count_mode", &quad8_cnt_mode_enum),
+ COUNTER_COUNT_ENUM_AVAILABLE("count_mode", &quad8_cnt_mode_enum),
+ {
+ .name = "direction",
+ .read = quad8_count_direction_read
+ },
+ {
+ .name = "enable",
+ .read = quad8_count_enable_read,
+ .write = quad8_count_enable_write
+ },
+ COUNTER_COUNT_ENUM("error_noise", &quad8_error_noise_enum),
+ COUNTER_COUNT_ENUM_AVAILABLE("error_noise", &quad8_error_noise_enum),
+ {
+ .name = "preset",
+ .read = quad8_count_preset_read,
+ .write = quad8_count_preset_write
+ },
+ {
+ .name = "preset_enable",
+ .read = quad8_count_preset_enable_read,
+ .write = quad8_count_preset_enable_write
+ }
+};
+
+#define QUAD8_COUNT(_id, _cntname) { \
+ .id = (_id), \
+ .name = (_cntname), \
+ .functions_list = quad8_count_functions_list, \
+ .num_functions = ARRAY_SIZE(quad8_count_functions_list), \
+ .synapses = quad8_count_synapses[(_id)], \
+ .num_synapses = 2, \
+ .ext = quad8_count_ext, \
+ .num_ext = ARRAY_SIZE(quad8_count_ext) \
+}
+
+static struct counter_count quad8_counts[] = {
+ QUAD8_COUNT(0, "Channel 1 Count"),
+ QUAD8_COUNT(1, "Channel 2 Count"),
+ QUAD8_COUNT(2, "Channel 3 Count"),
+ QUAD8_COUNT(3, "Channel 4 Count"),
+ QUAD8_COUNT(4, "Channel 5 Count"),
+ QUAD8_COUNT(5, "Channel 6 Count"),
+ QUAD8_COUNT(6, "Channel 7 Count"),
+ QUAD8_COUNT(7, "Channel 8 Count")
+};
+
static int quad8_probe(struct device *dev, unsigned int id)
{
struct iio_dev *indio_dev;
- struct quad8_iio *priv;
+ struct quad8_iio *quad8iio;
int i, j;
unsigned int base_offset;
+ int err;
- indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
- if (!indio_dev)
- return -ENOMEM;
-
- if (!devm_request_region(dev, base[id], QUAD8_EXTENT,
- dev_name(dev))) {
+ if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
base[id], base[id] + QUAD8_EXTENT);
return -EBUSY;
}
+ /* Allocate IIO device; this also allocates driver data structure */
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*quad8iio));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ /* Initialize IIO device */
indio_dev->info = &quad8_info;
indio_dev->modes = INDIO_DIRECT_MODE;
indio_dev->num_channels = ARRAY_SIZE(quad8_channels);
@@ -579,8 +1308,17 @@ static int quad8_probe(struct device *dev, unsigned int id)
indio_dev->name = dev_name(dev);
indio_dev->dev.parent = dev;
- priv = iio_priv(indio_dev);
- priv->base = base[id];
+ /* Initialize Counter device and driver data */
+ quad8iio = iio_priv(indio_dev);
+ quad8iio->counter.name = dev_name(dev);
+ quad8iio->counter.parent = dev;
+ quad8iio->counter.ops = &quad8_ops;
+ quad8iio->counter.counts = quad8_counts;
+ quad8iio->counter.num_counts = ARRAY_SIZE(quad8_counts);
+ quad8iio->counter.signals = quad8_signals;
+ quad8iio->counter.num_signals = ARRAY_SIZE(quad8_signals);
+ quad8iio->counter.priv = quad8iio;
+ quad8iio->base = base[id];
/* Reset all counters and disable interrupt function */
outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
@@ -606,7 +1344,13 @@ static int quad8_probe(struct device *dev, unsigned int id)
/* Enable all counters */
outb(QUAD8_CHAN_OP_ENABLE_COUNTERS, base[id] + QUAD8_REG_CHAN_OP);
- return devm_iio_device_register(dev, indio_dev);
+ /* Register IIO device */
+ err = devm_iio_device_register(dev, indio_dev);
+ if (err)
+ return err;
+
+ /* Register Counter device */
+ return devm_counter_register(dev, &quad8iio->counter);
}
static struct isa_driver quad8_driver = {
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index a74998400282..dd3add729529 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -8,3 +8,24 @@ menuconfig COUNTER
This enables counter device support through the Generic Counter
interface. You only need to enable this, if you also want to enable
one or more of the counter device drivers below.
+
+if COUNTER
+
+config 104_QUAD_8
+ tristate "ACCES 104-QUAD-8 driver"
+ depends on PC104 && X86 && IIO
+ select ISA_BUS_API
+ help
+ Say yes here to build support for the ACCES 104-QUAD-8 quadrature
+ encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
+
+ A counter's respective error flag may be cleared by performing a write
+ operation on the respective count value attribute. Although the
+ 104-QUAD-8 counters have a 25-bit range, only the lower 24 bits may be
+ set, either directly or via the counter's preset attribute. Interrupts
+ are not supported by this driver.
+
+ The base port addresses for the devices may be configured via the base
+ array module parameter.
+
+endif # COUNTER
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
index b1464604bdbe..aee0d2ddcf2c 100644
--- a/drivers/counter/Makefile
+++ b/drivers/counter/Makefile
@@ -3,3 +3,5 @@
#
obj-$(CONFIG_COUNTER) += counter.o
+
+obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
diff --git a/drivers/iio/counter/Kconfig b/drivers/iio/counter/Kconfig
index bf1e559ad7cd..eeb358122cbe 100644
--- a/drivers/iio/counter/Kconfig
+++ b/drivers/iio/counter/Kconfig
@@ -5,23 +5,6 @@
menu "Counters"
-config 104_QUAD_8
- tristate "ACCES 104-QUAD-8 driver"
- depends on PC104 && X86
- select ISA_BUS_API
- help
- Say yes here to build support for the ACCES 104-QUAD-8 quadrature
- encoder counter/interface device family (104-QUAD-8, 104-QUAD-4).
-
- Performing a write to a counter's IIO_CHAN_INFO_RAW sets the counter and
- also clears the counter's respective error flag. Although the counters
- have a 25-bit range, only the lower 24 bits may be set, either directly
- or via a counter's preset attribute. Interrupts are not supported by
- this driver.
-
- The base port addresses for the devices may be configured via the base
- array module parameter.
-
config STM32_LPTIMER_CNT
tristate "STM32 LP Timer encoder counter driver"
depends on MFD_STM32_LPTIMER || COMPILE_TEST
diff --git a/drivers/iio/counter/Makefile b/drivers/iio/counter/Makefile
index 1b9a896eb488..93933ba49280 100644
--- a/drivers/iio/counter/Makefile
+++ b/drivers/iio/counter/Makefile
@@ -4,5 +4,4 @@
# When adding new entries keep the list in alphabetical order
-obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o
obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
--
2.21.0
^ permalink raw reply related
* [PATCH v10 04/18] iio: 104-quad-8: Update license boilerplate
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, tglx, fabrice.gasnier, esben, shawnguo, linux-kernel,
leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch simplifies the boilerplate license text by making use of a
SPDX license identifier line.
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
drivers/iio/counter/104-quad-8.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/iio/counter/104-quad-8.c b/drivers/iio/counter/104-quad-8.c
index 92be8d0f7735..72b6352e09f0 100644
--- a/drivers/iio/counter/104-quad-8.c
+++ b/drivers/iio/counter/104-quad-8.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* IIO driver for the ACCES 104-QUAD-8
* Copyright (C) 2016 William Breathitt Gray
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
*/
#include <linux/bitops.h>
--
2.21.0
^ permalink raw reply related
* [PATCH v10 03/18] docs: Add Generic Counter interface documentation
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch adds high-level documentation about the Generic Counter
interface.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
Documentation/driver-api/generic-counter.rst | 342 +++++++++++++++++++
Documentation/driver-api/index.rst | 1 +
MAINTAINERS | 1 +
3 files changed, 344 insertions(+)
create mode 100644 Documentation/driver-api/generic-counter.rst
diff --git a/Documentation/driver-api/generic-counter.rst b/Documentation/driver-api/generic-counter.rst
new file mode 100644
index 000000000000..f51db893f595
--- /dev/null
+++ b/Documentation/driver-api/generic-counter.rst
@@ -0,0 +1,342 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+=========================
+Generic Counter Interface
+=========================
+
+Introduction
+============
+
+Counter devices are prevalent within a diverse spectrum of industries.
+The ubiquitous presence of these devices necessitates a common interface
+and standard of interaction and exposure. This driver API attempts to
+resolve the issue of duplicate code found among existing counter device
+drivers by introducing a generic counter interface for consumption. The
+Generic Counter interface enables drivers to support and expose a common
+set of components and functionality present in counter devices.
+
+Theory
+======
+
+Counter devices can vary greatly in design, but regardless of whether
+some devices are quadrature encoder counters or tally counters, all
+counter devices consist of a core set of components. This core set of
+components, shared by all counter devices, is what forms the essence of
+the Generic Counter interface.
+
+There are three core components to a counter:
+
+* Count:
+ Count data for a set of Signals.
+
+* Signal:
+ Input data that is evaluated by the counter to determine the count
+ data.
+
+* Synapse:
+ The association of a Signal with a respective Count.
+
+COUNT
+-----
+A Count represents the count data for a set of Signals. The Generic
+Counter interface provides the following available count data types:
+
+* COUNT_POSITION:
+ Unsigned integer value representing position.
+
+A Count has a count function mode which represents the update behavior
+for the count data. The Generic Counter interface provides the following
+available count function modes:
+
+* Increase:
+ Accumulated count is incremented.
+
+* Decrease:
+ Accumulated count is decremented.
+
+* Pulse-Direction:
+ Rising edges on signal A updates the respective count. The input level
+ of signal B determines direction.
+
+* Quadrature:
+ A pair of quadrature encoding signals are evaluated to determine
+ position and direction. The following Quadrature modes are available:
+
+ - x1 A:
+ If direction is forward, rising edges on quadrature pair signal A
+ updates the respective count; if the direction is backward, falling
+ edges on quadrature pair signal A updates the respective count.
+ Quadrature encoding determines the direction.
+
+ - x1 B:
+ If direction is forward, rising edges on quadrature pair signal B
+ updates the respective count; if the direction is backward, falling
+ edges on quadrature pair signal B updates the respective count.
+ Quadrature encoding determines the direction.
+
+ - x2 A:
+ Any state transition on quadrature pair signal A updates the
+ respective count. Quadrature encoding determines the direction.
+
+ - x2 B:
+ Any state transition on quadrature pair signal B updates the
+ respective count. Quadrature encoding determines the direction.
+
+ - x4:
+ Any state transition on either quadrature pair signals updates the
+ respective count. Quadrature encoding determines the direction.
+
+A Count has a set of one or more associated Signals.
+
+SIGNAL
+------
+A Signal represents a counter input data; this is the input data that is
+evaluated by the counter to determine the count data; e.g. a quadrature
+signal output line of a rotary encoder. Not all counter devices provide
+user access to the Signal data.
+
+The Generic Counter interface provides the following available signal
+data types for when the Signal data is available for user access:
+
+* SIGNAL_LEVEL:
+ Signal line state level. The following states are possible:
+
+ - SIGNAL_LEVEL_LOW:
+ Signal line is in a low state.
+
+ - SIGNAL_LEVEL_HIGH:
+ Signal line is in a high state.
+
+A Signal may be associated with one or more Counts.
+
+SYNAPSE
+-------
+A Synapse represents the association of a Signal with a respective
+Count. Signal data affects respective Count data, and the Synapse
+represents this relationship.
+
+The Synapse action mode specifies the Signal data condition which
+triggers the respective Count's count function evaluation to update the
+count data. The Generic Counter interface provides the following
+available action modes:
+
+* None:
+ Signal does not trigger the count function. In Pulse-Direction count
+ function mode, this Signal is evaluated as Direction.
+
+* Rising Edge:
+ Low state transitions to high state.
+
+* Falling Edge:
+ High state transitions to low state.
+
+* Both Edges:
+ Any state transition.
+
+A counter is defined as a set of input signals associated with count
+data that are generated by the evaluation of the state of the associated
+input signals as defined by the respective count functions. Within the
+context of the Generic Counter interface, a counter consists of Counts
+each associated with a set of Signals, whose respective Synapse
+instances represent the count function update conditions for the
+associated Counts.
+
+Paradigm
+========
+
+The most basic counter device may be expressed as a single Count
+associated with a single Signal via a single Synapse. Take for example
+a counter device which simply accumulates a count of rising edges on a
+source input line::
+
+ Count Synapse Signal
+ ----- ------- ------
+ +---------------------+
+ | Data: Count | Rising Edge ________
+ | Function: Increase | <------------- / Source \
+ | | ____________
+ +---------------------+
+
+In this example, the Signal is a source input line with a pulsing
+voltage, while the Count is a persistent count value which is repeatedly
+incremented. The Signal is associated with the respective Count via a
+Synapse. The increase function is triggered by the Signal data condition
+specified by the Synapse -- in this case a rising edge condition on the
+voltage input line. In summary, the counter device existence and
+behavior is aptly represented by respective Count, Signal, and Synapse
+components: a rising edge condition triggers an increase function on an
+accumulating count datum.
+
+A counter device is not limited to a single Signal; in fact, in theory
+many Signals may be associated with even a single Count. For example, a
+quadrature encoder counter device can keep track of position based on
+the states of two input lines::
+
+ Count Synapse Signal
+ ----- ------- ------
+ +-------------------------+
+ | Data: Position | Both Edges ___
+ | Function: Quadrature x4 | <------------ / A \
+ | | _______
+ | |
+ | | Both Edges ___
+ | | <------------ / B \
+ | | _______
+ +-------------------------+
+
+In this example, two Signals (quadrature encoder lines A and B) are
+associated with a single Count: a rising or falling edge on either A or
+B triggers the "Quadrature x4" function which determines the direction
+of movement and updates the respective position data. The "Quadrature
+x4" function is likely implemented in the hardware of the quadrature
+encoder counter device; the Count, Signals, and Synapses simply
+represent this hardware behavior and functionality.
+
+Signals associated with the same Count can have differing Synapse action
+mode conditions. For example, a quadrature encoder counter device
+operating in a non-quadrature Pulse-Direction mode could have one input
+line dedicated for movement and a second input line dedicated for
+direction::
+
+ Count Synapse Signal
+ ----- ------- ------
+ +---------------------------+
+ | Data: Position | Rising Edge ___
+ | Function: Pulse-Direction | <------------- / A \ (Movement)
+ | | _______
+ | |
+ | | None ___
+ | | <------------- / B \ (Direction)
+ | | _______
+ +---------------------------+
+
+Only Signal A triggers the "Pulse-Direction" update function, but the
+instantaneous state of Signal B is still required in order to know the
+direction so that the position data may be properly updated. Ultimately,
+both Signals are associated with the same Count via two respective
+Synapses, but only one Synapse has an active action mode condition which
+triggers the respective count function while the other is left with a
+"None" condition action mode to indicate its respective Signal's
+availability for state evaluation despite its non-triggering mode.
+
+Keep in mind that the Signal, Synapse, and Count are abstract
+representations which do not need to be closely married to their
+respective physical sources. This allows the user of a counter to
+divorce themselves from the nuances of physical components (such as
+whether an input line is differential or single-ended) and instead focus
+on the core idea of what the data and process represent (e.g. position
+as interpreted from quadrature encoding data).
+
+Userspace Interface
+===================
+
+Several sysfs attributes are generated by the Generic Counter interface,
+and reside under the /sys/bus/counter/devices/counterX directory, where
+counterX refers to the respective counter device. Please see
+Documentation/ABI/testing/sys-bus-counter-generic-sysfs for detailed
+information on each Generic Counter interface sysfs attribute.
+
+Through these sysfs attributes, programs and scripts may interact with
+the Generic Counter paradigm Counts, Signals, and Synapses of respective
+counter devices.
+
+Driver API
+==========
+
+Driver authors may utilize the Generic Counter interface in their code
+by including the include/linux/counter.h header file. This header file
+provides several core data structures, function prototypes, and macros
+for defining a counter device.
+
+.. kernel-doc:: include/linux/counter.h
+ :internal:
+
+.. kernel-doc:: drivers/counter/generic-counter.c
+ :export:
+
+Implementation
+==============
+
+To support a counter device, a driver must first allocate the available
+Counter Signals via counter_signal structures. These Signals should
+be stored as an array and set to the signals array member of an
+allocated counter_device structure before the Counter is registered to
+the system.
+
+Counter Counts may be allocated via counter_count structures, and
+respective Counter Signal associations (Synapses) made via
+counter_synapse structures. Associated counter_synapse structures are
+stored as an array and set to the the synapses array member of the
+respective counter_count structure. These counter_count structures are
+set to the counts array member of an allocated counter_device structure
+before the Counter is registered to the system.
+
+Driver callbacks should be provided to the counter_device structure via
+a constant counter_ops structure in order to communicate with the
+device: to read and write various Signals and Counts, and to set and get
+the "action mode" and "function mode" for various Synapses and Counts
+respectively.
+
+A defined counter_device structure may be registered to the system by
+passing it to the counter_register function, and unregistered by passing
+it to the counter_unregister function. Similarly, the
+devm_counter_register and devm_counter_unregister functions may be used
+if device memory-managed registration is desired.
+
+Extension sysfs attributes can be created for auxiliary functionality
+and data by passing in defined counter_device_ext, counter_count_ext,
+and counter_signal_ext structures. In these cases, the
+counter_device_ext structure is used for global configuration of the
+respective Counter device, while the counter_count_ext and
+counter_signal_ext structures allow for auxiliary exposure and
+configuration of a specific Count or Signal respectively.
+
+Architecture
+============
+
+When the Generic Counter interface counter module is loaded, the
+counter_init function is called which registers a bus_type named
+"counter" to the system. Subsequently, when the module is unloaded, the
+counter_exit function is called which unregisters the bus_type named
+"counter" from the system.
+
+Counter devices are registered to the system via the counter_register
+function, and later removed via the counter_unregister function. The
+counter_register function establishes a unique ID for the Counter
+device and creates a respective sysfs directory, where X is the
+mentioned unique ID:
+
+ /sys/bus/counter/devices/counterX
+
+Sysfs attributes are created within the counterX directory to expose
+functionality, configurations, and data relating to the Counts, Signals,
+and Synapses of the Counter device, as well as options and information
+for the Counter device itself.
+
+Each Signal has a directory created to house its relevant sysfs
+attributes, where Y is the unique ID of the respective Signal:
+
+ /sys/bus/counter/devices/counterX/signalY
+
+Similarly, each Count has a directory created to house its relevant
+sysfs attributes, where Y is the unique ID of the respective Count:
+
+ /sys/bus/counter/devices/counterX/countY
+
+For a more detailed breakdown of the available Generic Counter interface
+sysfs attributes, please refer to the
+Documentation/ABI/testing/sys-bus-counter file.
+
+The Signals and Counts associated with the Counter device are registered
+to the system as well by the counter_register function. The
+signal_read/signal_write driver callbacks are associated with their
+respective Signal attributes, while the count_read/count_write and
+function_get/function_set driver callbacks are associated with their
+respective Count attributes; similarly, the same is true for the
+action_get/action_set driver callbacks and their respective Synapse
+attributes. If a driver callback is left undefined, then the respective
+read/write permission is left disabled for the relevant attributes.
+
+Similarly, extension sysfs attributes are created for the defined
+counter_device_ext, counter_count_ext, and counter_signal_ext
+structures that are passed in.
diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst
index ab38ced66a44..37dce988c7fd 100644
--- a/Documentation/driver-api/index.rst
+++ b/Documentation/driver-api/index.rst
@@ -55,6 +55,7 @@ available subsections can be seen below.
slimbus
soundwire/index
fpga/index
+ generic-counter
.. only:: subproject and html
diff --git a/MAINTAINERS b/MAINTAINERS
index af701863a249..208c92ff4801 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3971,6 +3971,7 @@ M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
F: Documentation/ABI/testing/sysfs-bus-counter*
+F: Documentation/driver-api/generic-counter.rst
F: drivers/counter/
F: include/linux/counter.h
F: include/linux/counter_enum.h
--
2.21.0
^ permalink raw reply related
* [PATCH v10 02/18] counter: Documentation: Add Generic Counter sysfs documentation
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch adds standard documentation for the userspace sysfs
attributes of the Generic Counter interface.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
Documentation/ABI/testing/sysfs-bus-counter | 230 ++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 231 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-counter
diff --git a/Documentation/ABI/testing/sysfs-bus-counter b/Documentation/ABI/testing/sysfs-bus-counter
new file mode 100644
index 000000000000..566bd99fe0a5
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-counter
@@ -0,0 +1,230 @@
+What: /sys/bus/counter/devices/counterX/countY/count
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Count data of Count Y represented as a string.
+
+What: /sys/bus/counter/devices/counterX/countY/ceiling
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Count value ceiling for Count Y. This is the upper limit for the
+ respective counter.
+
+What: /sys/bus/counter/devices/counterX/countY/floor
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Count value floor for Count Y. This is the lower limit for the
+ respective counter.
+
+What: /sys/bus/counter/devices/counterX/countY/count_mode
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Count mode for channel Y. The ceiling and floor values for
+ Count Y are used by the count mode where required. The following
+ count modes are available:
+
+ normal:
+ Counting is continuous in either direction.
+
+ range limit:
+ An upper or lower limit is set, mimicking limit switches
+ in the mechanical counterpart. The upper limit is set to
+ the Count Y ceiling value, while the lower limit is set
+ to the Count Y floor value. The counter freezes at
+ count = ceiling when counting up, and at count = floor
+ when counting down. At either of these limits, the
+ counting is resumed only when the count direction is
+ reversed.
+
+ non-recycle:
+ The counter is disabled whenever a counter overflow or
+ underflow takes place. The counter is re-enabled when a
+ new count value is loaded to the counter via a preset
+ operation or direct write.
+
+ modulo-n:
+ A count value boundary is set between the Count Y floor
+ value and the Count Y ceiling value. The counter is
+ reset to the Count Y floor value at count = ceiling when
+ counting up, while the counter is set to the Count Y
+ ceiling value at count = floor when counting down; the
+ counter does not freeze at the boundary points, but
+ counts continuously throughout.
+
+What: /sys/bus/counter/devices/counterX/countY/count_mode_available
+What: /sys/bus/counter/devices/counterX/countY/error_noise_available
+What: /sys/bus/counter/devices/counterX/countY/function_available
+What: /sys/bus/counter/devices/counterX/countY/signalZ_action_available
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Discrete set of available values for the respective Count Y
+ configuration are listed in this file. Values are delimited by
+ newline characters.
+
+What: /sys/bus/counter/devices/counterX/countY/direction
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the count direction of Count
+ Y. Two count directions are available: forward and backward.
+
+ Some counter devices are able to determine the direction of
+ their counting. For example, quadrature encoding counters can
+ determine the direction of movement by evaluating the leading
+ phase of the respective A and B quadrature encoding signals.
+ This attribute exposes such count directions.
+
+What: /sys/bus/counter/devices/counterX/countY/enable
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Whether channel Y counter is enabled. Valid attribute values are
+ boolean.
+
+ This attribute is intended to serve as a pause/unpause mechanism
+ for Count Y. Suppose a counter device is used to count the total
+ movement of a conveyor belt: this attribute allows an operator
+ to temporarily pause the counter, service the conveyor belt,
+ and then finally unpause the counter to continue where it had
+ left off.
+
+What: /sys/bus/counter/devices/counterX/countY/error_noise
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates whether excessive noise is
+ present at the channel Y counter inputs.
+
+What: /sys/bus/counter/devices/counterX/countY/function
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Count function mode of Count Y; count function evaluation is
+ triggered by conditions specified by the Count Y signalZ_action
+ attributes. The following count functions are available:
+
+ increase:
+ Accumulated count is incremented.
+
+ decrease:
+ Accumulated count is decremented.
+
+ pulse-direction:
+ Rising edges on signal A updates the respective count.
+ The input level of signal B determines direction.
+
+ quadrature x1 a:
+ If direction is forward, rising edges on quadrature pair
+ signal A updates the respective count; if the direction
+ is backward, falling edges on quadrature pair signal A
+ updates the respective count. Quadrature encoding
+ determines the direction.
+
+ quadrature x1 b:
+ If direction is forward, rising edges on quadrature pair
+ signal B updates the respective count; if the direction
+ is backward, falling edges on quadrature pair signal B
+ updates the respective count. Quadrature encoding
+ determines the direction.
+
+ quadrature x2 a:
+ Any state transition on quadrature pair signal A updates
+ the respective count. Quadrature encoding determines the
+ direction.
+
+ quadrature x2 b:
+ Any state transition on quadrature pair signal B updates
+ the respective count. Quadrature encoding determines the
+ direction.
+
+ quadrature x4:
+ Any state transition on either quadrature pair signals
+ updates the respective count. Quadrature encoding
+ determines the direction.
+
+What: /sys/bus/counter/devices/counterX/countY/name
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the device-specific name of
+ Count Y. If possible, this should match the name of the
+ respective channel as it appears in the device datasheet.
+
+What: /sys/bus/counter/devices/counterX/countY/preset
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ If the counter device supports preset registers -- registers
+ used to load counter channels to a set count upon device-defined
+ preset operation trigger events -- the preset count for channel
+ Y is provided by this attribute.
+
+What: /sys/bus/counter/devices/counterX/countY/preset_enable
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Whether channel Y counter preset operation is enabled. Valid
+ attribute values are boolean.
+
+What: /sys/bus/counter/devices/counterX/countY/signalZ_action
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Action mode of Count Y for Signal Z. This attribute indicates
+ the condition of Signal Z that triggers the count function
+ evaluation for Count Y. The following action modes are
+ available:
+
+ none:
+ Signal does not trigger the count function. In
+ Pulse-Direction count function mode, this Signal is
+ evaluated as Direction.
+
+ rising edge:
+ Low state transitions to high state.
+
+ falling edge:
+ High state transitions to low state.
+
+ both edges:
+ Any state transition.
+
+What: /sys/bus/counter/devices/counterX/name
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the device-specific name of
+ the Counter. This should match the name of the device as it
+ appears in its respective datasheet.
+
+What: /sys/bus/counter/devices/counterX/num_counts
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the total number of Counts
+ belonging to the Counter.
+
+What: /sys/bus/counter/devices/counterX/num_signals
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the total number of Signals
+ belonging to the Counter.
+
+What: /sys/bus/counter/devices/counterX/signalY/signal
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Signal data of Signal Y represented as a string.
+
+What: /sys/bus/counter/devices/counterX/signalY/name
+KernelVersion: 5.2
+Contact: linux-iio@vger.kernel.org
+Description:
+ Read-only attribute that indicates the device-specific name of
+ Signal Y. If possible, this should match the name of the
+ respective signal as it appears in the device datasheet.
diff --git a/MAINTAINERS b/MAINTAINERS
index ef497d470501..af701863a249 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3970,6 +3970,7 @@ COUNTER SUBSYSTEM
M: William Breathitt Gray <vilhelm.gray@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
+F: Documentation/ABI/testing/sysfs-bus-counter*
F: drivers/counter/
F: include/linux/counter.h
F: include/linux/counter_enum.h
--
2.21.0
^ permalink raw reply related
* [PATCH v10 01/18] counter: Introduce the Generic Counter interface
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, Jonathan Cameron, tglx, fabrice.gasnier, esben, shawnguo,
linux-kernel, leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
In-Reply-To: <cover.1554184734.git.vilhelm.gray@gmail.com>
This patch introduces the Generic Counter interface for supporting
counter devices.
In the context of the Generic Counter interface, a counter is defined as
a device that reports one or more "counts" based on the state changes of
one or more "signals" as evaluated by a defined "count function."
Driver callbacks should be provided to communicate with the device: to
read and write various Signals and Counts, and to set and get the
"action mode" and "count function" for various Synapses and Counts
respectively.
To support a counter device, a driver must first allocate the available
Counter Signals via counter_signal structures. These Signals should
be stored as an array and set to the signals array member of an
allocated counter_device structure before the Counter is registered to
the system.
Counter Counts may be allocated via counter_count structures, and
respective Counter Signal associations (Synapses) made via
counter_synapse structures. Associated counter_synapse structures are
stored as an array and set to the the synapses array member of the
respective counter_count structure. These counter_count structures are
set to the counts array member of an allocated counter_device structure
before the Counter is registered to the system.
A counter device is registered to the system by passing the respective
initialized counter_device structure to the counter_register function;
similarly, the counter_unregister function unregisters the respective
Counter. The devm_counter_register and devm_counter_unregister functions
serve as device memory-managed versions of the counter_register and
counter_unregister functions respectively.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
---
MAINTAINERS | 8 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/counter/Kconfig | 10 +
drivers/counter/Makefile | 5 +
drivers/counter/counter.c | 1567 ++++++++++++++++++++++++++++++++++
include/linux/counter.h | 510 +++++++++++
include/linux/counter_enum.h | 45 +
8 files changed, 2148 insertions(+)
create mode 100644 drivers/counter/Kconfig
create mode 100644 drivers/counter/Makefile
create mode 100644 drivers/counter/counter.c
create mode 100644 include/linux/counter.h
create mode 100644 include/linux/counter_enum.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ff2c2f2e6da3..ef497d470501 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3966,6 +3966,14 @@ W: http://www.fi.muni.cz/~kas/cosa/
S: Maintained
F: drivers/net/wan/cosa*
+COUNTER SUBSYSTEM
+M: William Breathitt Gray <vilhelm.gray@gmail.com>
+L: linux-iio@vger.kernel.org
+S: Maintained
+F: drivers/counter/
+F: include/linux/counter.h
+F: include/linux/counter_enum.h
+
CPMAC ETHERNET DRIVER
M: Florian Fainelli <f.fainelli@gmail.com>
L: netdev@vger.kernel.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 4f9f99057ff8..e1fd5d783e39 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -228,4 +228,6 @@ source "drivers/siox/Kconfig"
source "drivers/slimbus/Kconfig"
+source "drivers/counter/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index e1ce029d28fd..7ea509ad6d43 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -186,3 +186,4 @@ obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
obj-$(CONFIG_SIOX) += siox/
obj-$(CONFIG_GNSS) += gnss/
+obj-$(CONFIG_COUNTER) += counter/
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
new file mode 100644
index 000000000000..a74998400282
--- /dev/null
+++ b/drivers/counter/Kconfig
@@ -0,0 +1,10 @@
+#
+# Counter devices
+#
+
+menuconfig COUNTER
+ tristate "Counter support"
+ help
+ This enables counter device support through the Generic Counter
+ interface. You only need to enable this, if you also want to enable
+ one or more of the counter device drivers below.
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
new file mode 100644
index 000000000000..b1464604bdbe
--- /dev/null
+++ b/drivers/counter/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Counter devices
+#
+
+obj-$(CONFIG_COUNTER) += counter.o
diff --git a/drivers/counter/counter.c b/drivers/counter/counter.c
new file mode 100644
index 000000000000..106bc7180cd8
--- /dev/null
+++ b/drivers/counter/counter.c
@@ -0,0 +1,1567 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Generic Counter interface
+ * Copyright (C) 2018 William Breathitt Gray
+ */
+#include <linux/counter.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/fs.h>
+#include <linux/gfp.h>
+#include <linux/idr.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+
+const char *const counter_count_direction_str[2] = {
+ [COUNTER_COUNT_DIRECTION_FORWARD] = "forward",
+ [COUNTER_COUNT_DIRECTION_BACKWARD] = "backward"
+};
+EXPORT_SYMBOL_GPL(counter_count_direction_str);
+
+const char *const counter_count_mode_str[4] = {
+ [COUNTER_COUNT_MODE_NORMAL] = "normal",
+ [COUNTER_COUNT_MODE_RANGE_LIMIT] = "range limit",
+ [COUNTER_COUNT_MODE_NON_RECYCLE] = "non-recycle",
+ [COUNTER_COUNT_MODE_MODULO_N] = "modulo-n"
+};
+EXPORT_SYMBOL_GPL(counter_count_mode_str);
+
+ssize_t counter_signal_enum_read(struct counter_device *counter,
+ struct counter_signal *signal, void *priv,
+ char *buf)
+{
+ const struct counter_signal_enum_ext *const e = priv;
+ int err;
+ size_t index;
+
+ if (!e->get)
+ return -EINVAL;
+
+ err = e->get(counter, signal, &index);
+ if (err)
+ return err;
+
+ if (index >= e->num_items)
+ return -EINVAL;
+
+ return sprintf(buf, "%s\n", e->items[index]);
+}
+EXPORT_SYMBOL_GPL(counter_signal_enum_read);
+
+ssize_t counter_signal_enum_write(struct counter_device *counter,
+ struct counter_signal *signal, void *priv,
+ const char *buf, size_t len)
+{
+ const struct counter_signal_enum_ext *const e = priv;
+ ssize_t index;
+ int err;
+
+ if (!e->set)
+ return -EINVAL;
+
+ index = __sysfs_match_string(e->items, e->num_items, buf);
+ if (index < 0)
+ return index;
+
+ err = e->set(counter, signal, index);
+ if (err)
+ return err;
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_signal_enum_write);
+
+ssize_t counter_signal_enum_available_read(struct counter_device *counter,
+ struct counter_signal *signal,
+ void *priv, char *buf)
+{
+ const struct counter_signal_enum_ext *const e = priv;
+ size_t i;
+ size_t len = 0;
+
+ if (!e->num_items)
+ return 0;
+
+ for (i = 0; i < e->num_items; i++)
+ len += sprintf(buf + len, "%s\n", e->items[i]);
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_signal_enum_available_read);
+
+ssize_t counter_count_enum_read(struct counter_device *counter,
+ struct counter_count *count, void *priv,
+ char *buf)
+{
+ const struct counter_count_enum_ext *const e = priv;
+ int err;
+ size_t index;
+
+ if (!e->get)
+ return -EINVAL;
+
+ err = e->get(counter, count, &index);
+ if (err)
+ return err;
+
+ if (index >= e->num_items)
+ return -EINVAL;
+
+ return sprintf(buf, "%s\n", e->items[index]);
+}
+EXPORT_SYMBOL_GPL(counter_count_enum_read);
+
+ssize_t counter_count_enum_write(struct counter_device *counter,
+ struct counter_count *count, void *priv,
+ const char *buf, size_t len)
+{
+ const struct counter_count_enum_ext *const e = priv;
+ ssize_t index;
+ int err;
+
+ if (!e->set)
+ return -EINVAL;
+
+ index = __sysfs_match_string(e->items, e->num_items, buf);
+ if (index < 0)
+ return index;
+
+ err = e->set(counter, count, index);
+ if (err)
+ return err;
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_count_enum_write);
+
+ssize_t counter_count_enum_available_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *priv, char *buf)
+{
+ const struct counter_count_enum_ext *const e = priv;
+ size_t i;
+ size_t len = 0;
+
+ if (!e->num_items)
+ return 0;
+
+ for (i = 0; i < e->num_items; i++)
+ len += sprintf(buf + len, "%s\n", e->items[i]);
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_count_enum_available_read);
+
+ssize_t counter_device_enum_read(struct counter_device *counter, void *priv,
+ char *buf)
+{
+ const struct counter_device_enum_ext *const e = priv;
+ int err;
+ size_t index;
+
+ if (!e->get)
+ return -EINVAL;
+
+ err = e->get(counter, &index);
+ if (err)
+ return err;
+
+ if (index >= e->num_items)
+ return -EINVAL;
+
+ return sprintf(buf, "%s\n", e->items[index]);
+}
+EXPORT_SYMBOL_GPL(counter_device_enum_read);
+
+ssize_t counter_device_enum_write(struct counter_device *counter, void *priv,
+ const char *buf, size_t len)
+{
+ const struct counter_device_enum_ext *const e = priv;
+ ssize_t index;
+ int err;
+
+ if (!e->set)
+ return -EINVAL;
+
+ index = __sysfs_match_string(e->items, e->num_items, buf);
+ if (index < 0)
+ return index;
+
+ err = e->set(counter, index);
+ if (err)
+ return err;
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_device_enum_write);
+
+ssize_t counter_device_enum_available_read(struct counter_device *counter,
+ void *priv, char *buf)
+{
+ const struct counter_device_enum_ext *const e = priv;
+ size_t i;
+ size_t len = 0;
+
+ if (!e->num_items)
+ return 0;
+
+ for (i = 0; i < e->num_items; i++)
+ len += sprintf(buf + len, "%s\n", e->items[i]);
+
+ return len;
+}
+EXPORT_SYMBOL_GPL(counter_device_enum_available_read);
+
+static const char *const counter_signal_level_str[] = {
+ [COUNTER_SIGNAL_LEVEL_LOW] = "low",
+ [COUNTER_SIGNAL_LEVEL_HIGH] = "high"
+};
+
+/**
+ * counter_signal_read_value_set - set counter_signal_read_value data
+ * @val: counter_signal_read_value structure to set
+ * @type: property Signal data represents
+ * @data: Signal data
+ *
+ * This function sets an opaque counter_signal_read_value structure with the
+ * provided Signal data.
+ */
+void counter_signal_read_value_set(struct counter_signal_read_value *const val,
+ const enum counter_signal_value_type type,
+ void *const data)
+{
+ if (type == COUNTER_SIGNAL_LEVEL)
+ val->len = sprintf(val->buf, "%s\n",
+ counter_signal_level_str[*(enum counter_signal_level *)data]);
+ else
+ val->len = 0;
+}
+EXPORT_SYMBOL_GPL(counter_signal_read_value_set);
+
+/**
+ * counter_count_read_value_set - set counter_count_read_value data
+ * @val: counter_count_read_value structure to set
+ * @type: property Count data represents
+ * @data: Count data
+ *
+ * This function sets an opaque counter_count_read_value structure with the
+ * provided Count data.
+ */
+void counter_count_read_value_set(struct counter_count_read_value *const val,
+ const enum counter_count_value_type type,
+ void *const data)
+{
+ switch (type) {
+ case COUNTER_COUNT_POSITION:
+ val->len = sprintf(val->buf, "%lu\n", *(unsigned long *)data);
+ break;
+ default:
+ val->len = 0;
+ }
+}
+EXPORT_SYMBOL_GPL(counter_count_read_value_set);
+
+/**
+ * counter_count_write_value_get - get counter_count_write_value data
+ * @data: Count data
+ * @type: property Count data represents
+ * @val: counter_count_write_value structure containing data
+ *
+ * This function extracts Count data from the provided opaque
+ * counter_count_write_value structure and stores it at the address provided by
+ * @data.
+ *
+ * RETURNS:
+ * 0 on success, negative error number on failure.
+ */
+int counter_count_write_value_get(void *const data,
+ const enum counter_count_value_type type,
+ const struct counter_count_write_value *const val)
+{
+ int err;
+
+ switch (type) {
+ case COUNTER_COUNT_POSITION:
+ err = kstrtoul(val->buf, 0, data);
+ if (err)
+ return err;
+ break;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(counter_count_write_value_get);
+
+struct counter_attr_parm {
+ struct counter_device_attr_group *group;
+ const char *prefix;
+ const char *name;
+ ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+ char *buf);
+ ssize_t (*store)(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t len);
+ void *component;
+};
+
+struct counter_device_attr {
+ struct device_attribute dev_attr;
+ struct list_head l;
+ void *component;
+};
+
+static int counter_attribute_create(const struct counter_attr_parm *const parm)
+{
+ struct counter_device_attr *counter_attr;
+ struct device_attribute *dev_attr;
+ int err;
+ struct list_head *const attr_list = &parm->group->attr_list;
+
+ /* Allocate a Counter device attribute */
+ counter_attr = kzalloc(sizeof(*counter_attr), GFP_KERNEL);
+ if (!counter_attr)
+ return -ENOMEM;
+ dev_attr = &counter_attr->dev_attr;
+
+ sysfs_attr_init(&dev_attr->attr);
+
+ /* Configure device attribute */
+ dev_attr->attr.name = kasprintf(GFP_KERNEL, "%s%s", parm->prefix,
+ parm->name);
+ if (!dev_attr->attr.name) {
+ err = -ENOMEM;
+ goto err_free_counter_attr;
+ }
+ if (parm->show) {
+ dev_attr->attr.mode |= 0444;
+ dev_attr->show = parm->show;
+ }
+ if (parm->store) {
+ dev_attr->attr.mode |= 0200;
+ dev_attr->store = parm->store;
+ }
+
+ /* Store associated Counter component with attribute */
+ counter_attr->component = parm->component;
+
+ /* Keep track of the attribute for later cleanup */
+ list_add(&counter_attr->l, attr_list);
+ parm->group->num_attr++;
+
+ return 0;
+
+err_free_counter_attr:
+ kfree(counter_attr);
+ return err;
+}
+
+#define to_counter_attr(_dev_attr) \
+ container_of(_dev_attr, struct counter_device_attr, dev_attr)
+
+struct counter_signal_unit {
+ struct counter_signal *signal;
+};
+
+static ssize_t counter_signal_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_signal_unit *const component = devattr->component;
+ struct counter_signal *const signal = component->signal;
+ int err;
+ struct counter_signal_read_value val = { .buf = buf };
+
+ err = counter->ops->signal_read(counter, signal, &val);
+ if (err)
+ return err;
+
+ return val.len;
+}
+
+struct counter_name_unit {
+ const char *name;
+};
+
+static ssize_t counter_device_attr_name_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ const struct counter_name_unit *const comp = to_counter_attr(attr)->component;
+
+ return sprintf(buf, "%s\n", comp->name);
+}
+
+static int counter_name_attribute_create(
+ struct counter_device_attr_group *const group,
+ const char *const name)
+{
+ struct counter_name_unit *name_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Skip if no name */
+ if (!name)
+ return 0;
+
+ /* Allocate name attribute component */
+ name_comp = kmalloc(sizeof(*name_comp), GFP_KERNEL);
+ if (!name_comp)
+ return -ENOMEM;
+ name_comp->name = name;
+
+ /* Allocate Signal name attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = "name";
+ parm.show = counter_device_attr_name_show;
+ parm.store = NULL;
+ parm.component = name_comp;
+ err = counter_attribute_create(&parm);
+ if (err)
+ goto err_free_name_comp;
+
+ return 0;
+
+err_free_name_comp:
+ kfree(name_comp);
+ return err;
+}
+
+struct counter_signal_ext_unit {
+ struct counter_signal *signal;
+ const struct counter_signal_ext *ext;
+};
+
+static ssize_t counter_signal_ext_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_signal_ext_unit *const comp = devattr->component;
+ const struct counter_signal_ext *const ext = comp->ext;
+
+ return ext->read(dev_get_drvdata(dev), comp->signal, ext->priv, buf);
+}
+
+static ssize_t counter_signal_ext_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_signal_ext_unit *const comp = devattr->component;
+ const struct counter_signal_ext *const ext = comp->ext;
+
+ return ext->write(dev_get_drvdata(dev), comp->signal, ext->priv, buf,
+ len);
+}
+
+static void counter_device_attr_list_free(struct list_head *attr_list)
+{
+ struct counter_device_attr *p, *n;
+
+ list_for_each_entry_safe(p, n, attr_list, l) {
+ /* free attribute name and associated component memory */
+ kfree(p->dev_attr.attr.name);
+ kfree(p->component);
+ list_del(&p->l);
+ kfree(p);
+ }
+}
+
+static int counter_signal_ext_register(
+ struct counter_device_attr_group *const group,
+ struct counter_signal *const signal)
+{
+ const size_t num_ext = signal->num_ext;
+ size_t i;
+ const struct counter_signal_ext *ext;
+ struct counter_signal_ext_unit *signal_ext_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Create an attribute for each extension */
+ for (i = 0 ; i < num_ext; i++) {
+ ext = signal->ext + i;
+
+ /* Allocate signal_ext attribute component */
+ signal_ext_comp = kmalloc(sizeof(*signal_ext_comp), GFP_KERNEL);
+ if (!signal_ext_comp) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+ signal_ext_comp->signal = signal;
+ signal_ext_comp->ext = ext;
+
+ /* Allocate a Counter device attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = ext->name;
+ parm.show = (ext->read) ? counter_signal_ext_show : NULL;
+ parm.store = (ext->write) ? counter_signal_ext_store : NULL;
+ parm.component = signal_ext_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(signal_ext_comp);
+ goto err_free_attr_list;
+ }
+ }
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+static int counter_signal_attributes_create(
+ struct counter_device_attr_group *const group,
+ const struct counter_device *const counter,
+ struct counter_signal *const signal)
+{
+ struct counter_signal_unit *signal_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Allocate Signal attribute component */
+ signal_comp = kmalloc(sizeof(*signal_comp), GFP_KERNEL);
+ if (!signal_comp)
+ return -ENOMEM;
+ signal_comp->signal = signal;
+
+ /* Create main Signal attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = "signal";
+ parm.show = (counter->ops->signal_read) ? counter_signal_show : NULL;
+ parm.store = NULL;
+ parm.component = signal_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(signal_comp);
+ return err;
+ }
+
+ /* Create Signal name attribute */
+ err = counter_name_attribute_create(group, signal->name);
+ if (err)
+ goto err_free_attr_list;
+
+ /* Register Signal extension attributes */
+ err = counter_signal_ext_register(group, signal);
+ if (err)
+ goto err_free_attr_list;
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+static int counter_signals_register(
+ struct counter_device_attr_group *const groups_list,
+ const struct counter_device *const counter)
+{
+ const size_t num_signals = counter->num_signals;
+ size_t i;
+ struct counter_signal *signal;
+ const char *name;
+ int err;
+
+ /* Register each Signal */
+ for (i = 0; i < num_signals; i++) {
+ signal = counter->signals + i;
+
+ /* Generate Signal attribute directory name */
+ name = kasprintf(GFP_KERNEL, "signal%d", signal->id);
+ if (!name) {
+ err = -ENOMEM;
+ goto err_free_attr_groups;
+ }
+ groups_list[i].attr_group.name = name;
+
+ /* Create all attributes associated with Signal */
+ err = counter_signal_attributes_create(groups_list + i, counter,
+ signal);
+ if (err)
+ goto err_free_attr_groups;
+ }
+
+ return 0;
+
+err_free_attr_groups:
+ do {
+ kfree(groups_list[i].attr_group.name);
+ counter_device_attr_list_free(&groups_list[i].attr_list);
+ } while (i--);
+ return err;
+}
+
+static const char *const counter_synapse_action_str[] = {
+ [COUNTER_SYNAPSE_ACTION_NONE] = "none",
+ [COUNTER_SYNAPSE_ACTION_RISING_EDGE] = "rising edge",
+ [COUNTER_SYNAPSE_ACTION_FALLING_EDGE] = "falling edge",
+ [COUNTER_SYNAPSE_ACTION_BOTH_EDGES] = "both edges"
+};
+
+struct counter_action_unit {
+ struct counter_synapse *synapse;
+ struct counter_count *count;
+};
+
+static ssize_t counter_action_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ int err;
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ const struct counter_action_unit *const component = devattr->component;
+ struct counter_count *const count = component->count;
+ struct counter_synapse *const synapse = component->synapse;
+ size_t action_index;
+ enum counter_synapse_action action;
+
+ err = counter->ops->action_get(counter, count, synapse, &action_index);
+ if (err)
+ return err;
+
+ synapse->action = action_index;
+
+ action = synapse->actions_list[action_index];
+ return sprintf(buf, "%s\n", counter_synapse_action_str[action]);
+}
+
+static ssize_t counter_action_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_action_unit *const component = devattr->component;
+ struct counter_synapse *const synapse = component->synapse;
+ size_t action_index;
+ const size_t num_actions = synapse->num_actions;
+ enum counter_synapse_action action;
+ int err;
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ struct counter_count *const count = component->count;
+
+ /* Find requested action mode */
+ for (action_index = 0; action_index < num_actions; action_index++) {
+ action = synapse->actions_list[action_index];
+ if (sysfs_streq(buf, counter_synapse_action_str[action]))
+ break;
+ }
+ /* If requested action mode not found */
+ if (action_index >= num_actions)
+ return -EINVAL;
+
+ err = counter->ops->action_set(counter, count, synapse, action_index);
+ if (err)
+ return err;
+
+ synapse->action = action_index;
+
+ return len;
+}
+
+struct counter_action_avail_unit {
+ const enum counter_synapse_action *actions_list;
+ size_t num_actions;
+};
+
+static ssize_t counter_synapse_action_available_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_action_avail_unit *const component = devattr->component;
+ size_t i;
+ enum counter_synapse_action action;
+ ssize_t len = 0;
+
+ for (i = 0; i < component->num_actions; i++) {
+ action = component->actions_list[i];
+ len += sprintf(buf + len, "%s\n",
+ counter_synapse_action_str[action]);
+ }
+
+ return len;
+}
+
+static int counter_synapses_register(
+ struct counter_device_attr_group *const group,
+ const struct counter_device *const counter,
+ struct counter_count *const count, const char *const count_attr_name)
+{
+ size_t i;
+ struct counter_synapse *synapse;
+ const char *prefix;
+ struct counter_action_unit *action_comp;
+ struct counter_attr_parm parm;
+ int err;
+ struct counter_action_avail_unit *avail_comp;
+
+ /* Register each Synapse */
+ for (i = 0; i < count->num_synapses; i++) {
+ synapse = count->synapses + i;
+
+ /* Generate attribute prefix */
+ prefix = kasprintf(GFP_KERNEL, "signal%d_",
+ synapse->signal->id);
+ if (!prefix) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+
+ /* Allocate action attribute component */
+ action_comp = kmalloc(sizeof(*action_comp), GFP_KERNEL);
+ if (!action_comp) {
+ err = -ENOMEM;
+ goto err_free_prefix;
+ }
+ action_comp->synapse = synapse;
+ action_comp->count = count;
+
+ /* Create action attribute */
+ parm.group = group;
+ parm.prefix = prefix;
+ parm.name = "action";
+ parm.show = (counter->ops->action_get) ? counter_action_show : NULL;
+ parm.store = (counter->ops->action_set) ? counter_action_store : NULL;
+ parm.component = action_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(action_comp);
+ goto err_free_prefix;
+ }
+
+ /* Allocate action available attribute component */
+ avail_comp = kmalloc(sizeof(*avail_comp), GFP_KERNEL);
+ if (!avail_comp) {
+ err = -ENOMEM;
+ goto err_free_prefix;
+ }
+ avail_comp->actions_list = synapse->actions_list;
+ avail_comp->num_actions = synapse->num_actions;
+
+ /* Create action_available attribute */
+ parm.group = group;
+ parm.prefix = prefix;
+ parm.name = "action_available";
+ parm.show = counter_synapse_action_available_show;
+ parm.store = NULL;
+ parm.component = avail_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(avail_comp);
+ goto err_free_prefix;
+ }
+
+ kfree(prefix);
+ }
+
+ return 0;
+
+err_free_prefix:
+ kfree(prefix);
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+struct counter_count_unit {
+ struct counter_count *count;
+};
+
+static ssize_t counter_count_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_unit *const component = devattr->component;
+ struct counter_count *const count = component->count;
+ int err;
+ struct counter_count_read_value val = { .buf = buf };
+
+ err = counter->ops->count_read(counter, count, &val);
+ if (err)
+ return err;
+
+ return val.len;
+}
+
+static ssize_t counter_count_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_unit *const component = devattr->component;
+ struct counter_count *const count = component->count;
+ int err;
+ struct counter_count_write_value val = { .buf = buf };
+
+ err = counter->ops->count_write(counter, count, &val);
+ if (err)
+ return err;
+
+ return len;
+}
+
+static const char *const counter_count_function_str[] = {
+ [COUNTER_COUNT_FUNCTION_INCREASE] = "increase",
+ [COUNTER_COUNT_FUNCTION_DECREASE] = "decrease",
+ [COUNTER_COUNT_FUNCTION_PULSE_DIRECTION] = "pulse-direction",
+ [COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A] = "quadrature x1 a",
+ [COUNTER_COUNT_FUNCTION_QUADRATURE_X1_B] = "quadrature x1 b",
+ [COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A] = "quadrature x2 a",
+ [COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B] = "quadrature x2 b",
+ [COUNTER_COUNT_FUNCTION_QUADRATURE_X4] = "quadrature x4"
+};
+
+static ssize_t counter_function_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int err;
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_unit *const component = devattr->component;
+ struct counter_count *const count = component->count;
+ size_t func_index;
+ enum counter_count_function function;
+
+ err = counter->ops->function_get(counter, count, &func_index);
+ if (err)
+ return err;
+
+ count->function = func_index;
+
+ function = count->functions_list[func_index];
+ return sprintf(buf, "%s\n", counter_count_function_str[function]);
+}
+
+static ssize_t counter_function_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_unit *const component = devattr->component;
+ struct counter_count *const count = component->count;
+ const size_t num_functions = count->num_functions;
+ size_t func_index;
+ enum counter_count_function function;
+ int err;
+ struct counter_device *const counter = dev_get_drvdata(dev);
+
+ /* Find requested Count function mode */
+ for (func_index = 0; func_index < num_functions; func_index++) {
+ function = count->functions_list[func_index];
+ if (sysfs_streq(buf, counter_count_function_str[function]))
+ break;
+ }
+ /* Return error if requested Count function mode not found */
+ if (func_index >= num_functions)
+ return -EINVAL;
+
+ err = counter->ops->function_set(counter, count, func_index);
+ if (err)
+ return err;
+
+ count->function = func_index;
+
+ return len;
+}
+
+struct counter_count_ext_unit {
+ struct counter_count *count;
+ const struct counter_count_ext *ext;
+};
+
+static ssize_t counter_count_ext_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_ext_unit *const comp = devattr->component;
+ const struct counter_count_ext *const ext = comp->ext;
+
+ return ext->read(dev_get_drvdata(dev), comp->count, ext->priv, buf);
+}
+
+static ssize_t counter_count_ext_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_count_ext_unit *const comp = devattr->component;
+ const struct counter_count_ext *const ext = comp->ext;
+
+ return ext->write(dev_get_drvdata(dev), comp->count, ext->priv, buf,
+ len);
+}
+
+static int counter_count_ext_register(
+ struct counter_device_attr_group *const group,
+ struct counter_count *const count)
+{
+ size_t i;
+ const struct counter_count_ext *ext;
+ struct counter_count_ext_unit *count_ext_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Create an attribute for each extension */
+ for (i = 0 ; i < count->num_ext; i++) {
+ ext = count->ext + i;
+
+ /* Allocate count_ext attribute component */
+ count_ext_comp = kmalloc(sizeof(*count_ext_comp), GFP_KERNEL);
+ if (!count_ext_comp) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+ count_ext_comp->count = count;
+ count_ext_comp->ext = ext;
+
+ /* Allocate count_ext attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = ext->name;
+ parm.show = (ext->read) ? counter_count_ext_show : NULL;
+ parm.store = (ext->write) ? counter_count_ext_store : NULL;
+ parm.component = count_ext_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(count_ext_comp);
+ goto err_free_attr_list;
+ }
+ }
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+struct counter_func_avail_unit {
+ const enum counter_count_function *functions_list;
+ size_t num_functions;
+};
+
+static ssize_t counter_count_function_available_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_func_avail_unit *const component = devattr->component;
+ const enum counter_count_function *const func_list = component->functions_list;
+ const size_t num_functions = component->num_functions;
+ size_t i;
+ enum counter_count_function function;
+ ssize_t len = 0;
+
+ for (i = 0; i < num_functions; i++) {
+ function = func_list[i];
+ len += sprintf(buf + len, "%s\n",
+ counter_count_function_str[function]);
+ }
+
+ return len;
+}
+
+static int counter_count_attributes_create(
+ struct counter_device_attr_group *const group,
+ const struct counter_device *const counter,
+ struct counter_count *const count)
+{
+ struct counter_count_unit *count_comp;
+ struct counter_attr_parm parm;
+ int err;
+ struct counter_count_unit *func_comp;
+ struct counter_func_avail_unit *avail_comp;
+
+ /* Allocate count attribute component */
+ count_comp = kmalloc(sizeof(*count_comp), GFP_KERNEL);
+ if (!count_comp)
+ return -ENOMEM;
+ count_comp->count = count;
+
+ /* Create main Count attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = "count";
+ parm.show = (counter->ops->count_read) ? counter_count_show : NULL;
+ parm.store = (counter->ops->count_write) ? counter_count_store : NULL;
+ parm.component = count_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(count_comp);
+ return err;
+ }
+
+ /* Allocate function attribute component */
+ func_comp = kmalloc(sizeof(*func_comp), GFP_KERNEL);
+ if (!func_comp) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+ func_comp->count = count;
+
+ /* Create Count function attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = "function";
+ parm.show = (counter->ops->function_get) ? counter_function_show : NULL;
+ parm.store = (counter->ops->function_set) ? counter_function_store : NULL;
+ parm.component = func_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(func_comp);
+ goto err_free_attr_list;
+ }
+
+ /* Allocate function available attribute component */
+ avail_comp = kmalloc(sizeof(*avail_comp), GFP_KERNEL);
+ if (!avail_comp) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+ avail_comp->functions_list = count->functions_list;
+ avail_comp->num_functions = count->num_functions;
+
+ /* Create Count function_available attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = "function_available";
+ parm.show = counter_count_function_available_show;
+ parm.store = NULL;
+ parm.component = avail_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(avail_comp);
+ goto err_free_attr_list;
+ }
+
+ /* Create Count name attribute */
+ err = counter_name_attribute_create(group, count->name);
+ if (err)
+ goto err_free_attr_list;
+
+ /* Register Count extension attributes */
+ err = counter_count_ext_register(group, count);
+ if (err)
+ goto err_free_attr_list;
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+static int counter_counts_register(
+ struct counter_device_attr_group *const groups_list,
+ const struct counter_device *const counter)
+{
+ size_t i;
+ struct counter_count *count;
+ const char *name;
+ int err;
+
+ /* Register each Count */
+ for (i = 0; i < counter->num_counts; i++) {
+ count = counter->counts + i;
+
+ /* Generate Count attribute directory name */
+ name = kasprintf(GFP_KERNEL, "count%d", count->id);
+ if (!name) {
+ err = -ENOMEM;
+ goto err_free_attr_groups;
+ }
+ groups_list[i].attr_group.name = name;
+
+ /* Register the Synapses associated with each Count */
+ err = counter_synapses_register(groups_list + i, counter, count,
+ name);
+ if (err)
+ goto err_free_attr_groups;
+
+ /* Create all attributes associated with Count */
+ err = counter_count_attributes_create(groups_list + i, counter,
+ count);
+ if (err)
+ goto err_free_attr_groups;
+ }
+
+ return 0;
+
+err_free_attr_groups:
+ do {
+ kfree(groups_list[i].attr_group.name);
+ counter_device_attr_list_free(&groups_list[i].attr_list);
+ } while (i--);
+ return err;
+}
+
+struct counter_size_unit {
+ size_t size;
+};
+
+static ssize_t counter_device_attr_size_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ const struct counter_size_unit *const comp = to_counter_attr(attr)->component;
+
+ return sprintf(buf, "%zu\n", comp->size);
+}
+
+static int counter_size_attribute_create(
+ struct counter_device_attr_group *const group,
+ const size_t size, const char *const name)
+{
+ struct counter_size_unit *size_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Allocate size attribute component */
+ size_comp = kmalloc(sizeof(*size_comp), GFP_KERNEL);
+ if (!size_comp)
+ return -ENOMEM;
+ size_comp->size = size;
+
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = name;
+ parm.show = counter_device_attr_size_show;
+ parm.store = NULL;
+ parm.component = size_comp;
+ err = counter_attribute_create(&parm);
+ if (err)
+ goto err_free_size_comp;
+
+ return 0;
+
+err_free_size_comp:
+ kfree(size_comp);
+ return err;
+}
+
+struct counter_ext_unit {
+ const struct counter_device_ext *ext;
+};
+
+static ssize_t counter_device_ext_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_ext_unit *const component = devattr->component;
+ const struct counter_device_ext *const ext = component->ext;
+
+ return ext->read(dev_get_drvdata(dev), ext->priv, buf);
+}
+
+static ssize_t counter_device_ext_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ const struct counter_device_attr *const devattr = to_counter_attr(attr);
+ const struct counter_ext_unit *const component = devattr->component;
+ const struct counter_device_ext *const ext = component->ext;
+
+ return ext->write(dev_get_drvdata(dev), ext->priv, buf, len);
+}
+
+static int counter_device_ext_register(
+ struct counter_device_attr_group *const group,
+ struct counter_device *const counter)
+{
+ size_t i;
+ struct counter_ext_unit *ext_comp;
+ struct counter_attr_parm parm;
+ int err;
+
+ /* Create an attribute for each extension */
+ for (i = 0 ; i < counter->num_ext; i++) {
+ /* Allocate extension attribute component */
+ ext_comp = kmalloc(sizeof(*ext_comp), GFP_KERNEL);
+ if (!ext_comp) {
+ err = -ENOMEM;
+ goto err_free_attr_list;
+ }
+
+ ext_comp->ext = counter->ext + i;
+
+ /* Allocate extension attribute */
+ parm.group = group;
+ parm.prefix = "";
+ parm.name = counter->ext[i].name;
+ parm.show = (counter->ext[i].read) ? counter_device_ext_show : NULL;
+ parm.store = (counter->ext[i].write) ? counter_device_ext_store : NULL;
+ parm.component = ext_comp;
+ err = counter_attribute_create(&parm);
+ if (err) {
+ kfree(ext_comp);
+ goto err_free_attr_list;
+ }
+ }
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+static int counter_global_attr_register(
+ struct counter_device_attr_group *const group,
+ struct counter_device *const counter)
+{
+ int err;
+
+ /* Create name attribute */
+ err = counter_name_attribute_create(group, counter->name);
+ if (err)
+ return err;
+
+ /* Create num_counts attribute */
+ err = counter_size_attribute_create(group, counter->num_counts,
+ "num_counts");
+ if (err)
+ goto err_free_attr_list;
+
+ /* Create num_signals attribute */
+ err = counter_size_attribute_create(group, counter->num_signals,
+ "num_signals");
+ if (err)
+ goto err_free_attr_list;
+
+ /* Register Counter device extension attributes */
+ err = counter_device_ext_register(group, counter);
+ if (err)
+ goto err_free_attr_list;
+
+ return 0;
+
+err_free_attr_list:
+ counter_device_attr_list_free(&group->attr_list);
+ return err;
+}
+
+static void counter_device_groups_list_free(
+ struct counter_device_attr_group *const groups_list,
+ const size_t num_groups)
+{
+ struct counter_device_attr_group *group;
+ size_t i;
+
+ /* loop through all attribute groups (signals, counts, global, etc.) */
+ for (i = 0; i < num_groups; i++) {
+ group = groups_list + i;
+
+ /* free all attribute group and associated attributes memory */
+ kfree(group->attr_group.name);
+ kfree(group->attr_group.attrs);
+ counter_device_attr_list_free(&group->attr_list);
+ }
+
+ kfree(groups_list);
+}
+
+static int counter_device_groups_list_prepare(
+ struct counter_device *const counter)
+{
+ const size_t total_num_groups =
+ counter->num_signals + counter->num_counts + 1;
+ struct counter_device_attr_group *groups_list;
+ size_t i;
+ int err;
+ size_t num_groups = 0;
+
+ /* Allocate space for attribute groups (signals, counts, and ext) */
+ groups_list = kcalloc(total_num_groups, sizeof(*groups_list),
+ GFP_KERNEL);
+ if (!groups_list)
+ return -ENOMEM;
+
+ /* Initialize attribute lists */
+ for (i = 0; i < total_num_groups; i++)
+ INIT_LIST_HEAD(&groups_list[i].attr_list);
+
+ /* Register Signals */
+ err = counter_signals_register(groups_list, counter);
+ if (err)
+ goto err_free_groups_list;
+ num_groups += counter->num_signals;
+
+ /* Register Counts and respective Synapses */
+ err = counter_counts_register(groups_list + num_groups, counter);
+ if (err)
+ goto err_free_groups_list;
+ num_groups += counter->num_counts;
+
+ /* Register Counter global attributes */
+ err = counter_global_attr_register(groups_list + num_groups, counter);
+ if (err)
+ goto err_free_groups_list;
+ num_groups++;
+
+ /* Store groups_list in device_state */
+ counter->device_state->groups_list = groups_list;
+ counter->device_state->num_groups = num_groups;
+
+ return 0;
+
+err_free_groups_list:
+ counter_device_groups_list_free(groups_list, num_groups);
+ return err;
+}
+
+static int counter_device_groups_prepare(
+ struct counter_device_state *const device_state)
+{
+ size_t i, j;
+ struct counter_device_attr_group *group;
+ int err;
+ struct counter_device_attr *p;
+
+ /* Allocate attribute groups for association with device */
+ device_state->groups = kcalloc(device_state->num_groups + 1,
+ sizeof(*device_state->groups),
+ GFP_KERNEL);
+ if (!device_state->groups)
+ return -ENOMEM;
+
+ /* Prepare each group of attributes for association */
+ for (i = 0; i < device_state->num_groups; i++) {
+ group = device_state->groups_list + i;
+
+ /* Allocate space for attribute pointers in attribute group */
+ group->attr_group.attrs = kcalloc(group->num_attr + 1,
+ sizeof(*group->attr_group.attrs), GFP_KERNEL);
+ if (!group->attr_group.attrs) {
+ err = -ENOMEM;
+ goto err_free_groups;
+ }
+
+ /* Add attribute pointers to attribute group */
+ j = 0;
+ list_for_each_entry(p, &group->attr_list, l)
+ group->attr_group.attrs[j++] = &p->dev_attr.attr;
+
+ /* Group attributes in attribute group */
+ device_state->groups[i] = &group->attr_group;
+ }
+ /* Associate attributes with device */
+ device_state->dev.groups = device_state->groups;
+
+ return 0;
+
+err_free_groups:
+ do {
+ group = device_state->groups_list + i;
+ kfree(group->attr_group.attrs);
+ group->attr_group.attrs = NULL;
+ } while (i--);
+ kfree(device_state->groups);
+ return err;
+}
+
+/* Provides a unique ID for each counter device */
+static DEFINE_IDA(counter_ida);
+
+static void counter_device_release(struct device *dev)
+{
+ struct counter_device *const counter = dev_get_drvdata(dev);
+ struct counter_device_state *const device_state = counter->device_state;
+
+ kfree(device_state->groups);
+ counter_device_groups_list_free(device_state->groups_list,
+ device_state->num_groups);
+ ida_simple_remove(&counter_ida, device_state->id);
+ kfree(device_state);
+}
+
+static struct device_type counter_device_type = {
+ .name = "counter_device",
+ .release = counter_device_release
+};
+
+static struct bus_type counter_bus_type = {
+ .name = "counter"
+};
+
+/**
+ * counter_register - register Counter to the system
+ * @counter: pointer to Counter to register
+ *
+ * This function registers a Counter to the system. A sysfs "counter" directory
+ * will be created and populated with sysfs attributes correlating with the
+ * Counter Signals, Synapses, and Counts respectively.
+ */
+int counter_register(struct counter_device *const counter)
+{
+ struct counter_device_state *device_state;
+ int err;
+
+ /* Allocate internal state container for Counter device */
+ device_state = kzalloc(sizeof(*device_state), GFP_KERNEL);
+ if (!device_state)
+ return -ENOMEM;
+ counter->device_state = device_state;
+
+ /* Acquire unique ID */
+ device_state->id = ida_simple_get(&counter_ida, 0, 0, GFP_KERNEL);
+ if (device_state->id < 0) {
+ err = device_state->id;
+ goto err_free_device_state;
+ }
+
+ /* Configure device structure for Counter */
+ device_state->dev.type = &counter_device_type;
+ device_state->dev.bus = &counter_bus_type;
+ if (counter->parent) {
+ device_state->dev.parent = counter->parent;
+ device_state->dev.of_node = counter->parent->of_node;
+ }
+ dev_set_name(&device_state->dev, "counter%d", device_state->id);
+ device_initialize(&device_state->dev);
+ dev_set_drvdata(&device_state->dev, counter);
+
+ /* Prepare device attributes */
+ err = counter_device_groups_list_prepare(counter);
+ if (err)
+ goto err_free_id;
+
+ /* Organize device attributes to groups and match to device */
+ err = counter_device_groups_prepare(device_state);
+ if (err)
+ goto err_free_groups_list;
+
+ /* Add device to system */
+ err = device_add(&device_state->dev);
+ if (err)
+ goto err_free_groups;
+
+ return 0;
+
+err_free_groups:
+ kfree(device_state->groups);
+err_free_groups_list:
+ counter_device_groups_list_free(device_state->groups_list,
+ device_state->num_groups);
+err_free_id:
+ ida_simple_remove(&counter_ida, device_state->id);
+err_free_device_state:
+ kfree(device_state);
+ return err;
+}
+EXPORT_SYMBOL_GPL(counter_register);
+
+/**
+ * counter_unregister - unregister Counter from the system
+ * @counter: pointer to Counter to unregister
+ *
+ * The Counter is unregistered from the system; all allocated memory is freed.
+ */
+void counter_unregister(struct counter_device *const counter)
+{
+ if (counter)
+ device_del(&counter->device_state->dev);
+}
+EXPORT_SYMBOL_GPL(counter_unregister);
+
+static void devm_counter_unreg(struct device *dev, void *res)
+{
+ counter_unregister(*(struct counter_device **)res);
+}
+
+/**
+ * devm_counter_register - Resource-managed counter_register
+ * @dev: device to allocate counter_device for
+ * @counter: pointer to Counter to register
+ *
+ * Managed counter_register. The Counter registered with this function is
+ * automatically unregistered on driver detach. This function calls
+ * counter_register internally. Refer to that function for more information.
+ *
+ * If an Counter registered with this function needs to be unregistered
+ * separately, devm_counter_unregister must be used.
+ *
+ * RETURNS:
+ * 0 on success, negative error number on failure.
+ */
+int devm_counter_register(struct device *dev,
+ struct counter_device *const counter)
+{
+ struct counter_device **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_counter_unreg, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = counter_register(counter);
+ if (!ret) {
+ *ptr = counter;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_counter_register);
+
+static int devm_counter_match(struct device *dev, void *res, void *data)
+{
+ struct counter_device **r = res;
+
+ if (!r || !*r) {
+ WARN_ON(!r || !*r);
+ return 0;
+ }
+
+ return *r == data;
+}
+
+/**
+ * devm_counter_unregister - Resource-managed counter_unregister
+ * @dev: device this counter_device belongs to
+ * @counter: pointer to Counter associated with the device
+ *
+ * Unregister Counter registered with devm_counter_register.
+ */
+void devm_counter_unregister(struct device *dev,
+ struct counter_device *const counter)
+{
+ int rc;
+
+ rc = devres_release(dev, devm_counter_unreg, devm_counter_match,
+ counter);
+ WARN_ON(rc);
+}
+EXPORT_SYMBOL_GPL(devm_counter_unregister);
+
+static int __init counter_init(void)
+{
+ return bus_register(&counter_bus_type);
+}
+
+static void __exit counter_exit(void)
+{
+ bus_unregister(&counter_bus_type);
+}
+
+subsys_initcall(counter_init);
+module_exit(counter_exit);
+
+MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
+MODULE_DESCRIPTION("Generic Counter interface");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/counter.h b/include/linux/counter.h
new file mode 100644
index 000000000000..a061cdcdef7c
--- /dev/null
+++ b/include/linux/counter.h
@@ -0,0 +1,510 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Counter interface
+ * Copyright (C) 2018 William Breathitt Gray
+ */
+#ifndef _COUNTER_H_
+#define _COUNTER_H_
+
+#include <linux/counter_enum.h>
+#include <linux/device.h>
+#include <linux/types.h>
+
+enum counter_count_direction {
+ COUNTER_COUNT_DIRECTION_FORWARD = 0,
+ COUNTER_COUNT_DIRECTION_BACKWARD
+};
+extern const char *const counter_count_direction_str[2];
+
+enum counter_count_mode {
+ COUNTER_COUNT_MODE_NORMAL = 0,
+ COUNTER_COUNT_MODE_RANGE_LIMIT,
+ COUNTER_COUNT_MODE_NON_RECYCLE,
+ COUNTER_COUNT_MODE_MODULO_N
+};
+extern const char *const counter_count_mode_str[4];
+
+struct counter_device;
+struct counter_signal;
+
+/**
+ * struct counter_signal_ext - Counter Signal extensions
+ * @name: attribute name
+ * @read: read callback for this attribute; may be NULL
+ * @write: write callback for this attribute; may be NULL
+ * @priv: data private to the driver
+ */
+struct counter_signal_ext {
+ const char *name;
+ ssize_t (*read)(struct counter_device *counter,
+ struct counter_signal *signal, void *priv, char *buf);
+ ssize_t (*write)(struct counter_device *counter,
+ struct counter_signal *signal, void *priv,
+ const char *buf, size_t len);
+ void *priv;
+};
+
+/**
+ * struct counter_signal - Counter Signal node
+ * @id: unique ID used to identify signal
+ * @name: device-specific Signal name; ideally, this should match the name
+ * as it appears in the datasheet documentation
+ * @ext: optional array of Counter Signal extensions
+ * @num_ext: number of Counter Signal extensions specified in @ext
+ * @priv: optional private data supplied by driver
+ */
+struct counter_signal {
+ int id;
+ const char *name;
+
+ const struct counter_signal_ext *ext;
+ size_t num_ext;
+
+ void *priv;
+};
+
+/**
+ * struct counter_signal_enum_ext - Signal enum extension attribute
+ * @items: Array of strings
+ * @num_items: Number of items specified in @items
+ * @set: Set callback function; may be NULL
+ * @get: Get callback function; may be NULL
+ *
+ * The counter_signal_enum_ext structure can be used to implement enum style
+ * Signal extension attributes. Enum style attributes are those which have a set
+ * of strings that map to unsigned integer values. The Generic Counter Signal
+ * enum extension helper code takes care of mapping between value and string, as
+ * well as generating a "_available" file which contains a list of all available
+ * items. The get callback is used to query the currently active item; the index
+ * of the item within the respective items array is returned via the 'item'
+ * parameter. The set callback is called when the attribute is updated; the
+ * 'item' parameter contains the index of the newly activated item within the
+ * respective items array.
+ */
+struct counter_signal_enum_ext {
+ const char * const *items;
+ size_t num_items;
+ int (*get)(struct counter_device *counter,
+ struct counter_signal *signal, size_t *item);
+ int (*set)(struct counter_device *counter,
+ struct counter_signal *signal, size_t item);
+};
+
+/**
+ * COUNTER_SIGNAL_ENUM() - Initialize Signal enum extension
+ * @_name: Attribute name
+ * @_e: Pointer to a counter_signal_enum_ext structure
+ *
+ * This should usually be used together with COUNTER_SIGNAL_ENUM_AVAILABLE()
+ */
+#define COUNTER_SIGNAL_ENUM(_name, _e) \
+{ \
+ .name = (_name), \
+ .read = counter_signal_enum_read, \
+ .write = counter_signal_enum_write, \
+ .priv = (_e) \
+}
+
+/**
+ * COUNTER_SIGNAL_ENUM_AVAILABLE() - Initialize Signal enum available extension
+ * @_name: Attribute name ("_available" will be appended to the name)
+ * @_e: Pointer to a counter_signal_enum_ext structure
+ *
+ * Creates a read only attribute that lists all the available enum items in a
+ * newline separated list. This should usually be used together with
+ * COUNTER_SIGNAL_ENUM()
+ */
+#define COUNTER_SIGNAL_ENUM_AVAILABLE(_name, _e) \
+{ \
+ .name = (_name "_available"), \
+ .read = counter_signal_enum_available_read, \
+ .priv = (_e) \
+}
+
+enum counter_synapse_action {
+ COUNTER_SYNAPSE_ACTION_NONE = 0,
+ COUNTER_SYNAPSE_ACTION_RISING_EDGE,
+ COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
+ COUNTER_SYNAPSE_ACTION_BOTH_EDGES
+};
+
+/**
+ * struct counter_synapse - Counter Synapse node
+ * @action: index of current action mode
+ * @actions_list: array of available action modes
+ * @num_actions: number of action modes specified in @actions_list
+ * @signal: pointer to associated signal
+ */
+struct counter_synapse {
+ size_t action;
+ const enum counter_synapse_action *actions_list;
+ size_t num_actions;
+
+ struct counter_signal *signal;
+};
+
+struct counter_count;
+
+/**
+ * struct counter_count_ext - Counter Count extension
+ * @name: attribute name
+ * @read: read callback for this attribute; may be NULL
+ * @write: write callback for this attribute; may be NULL
+ * @priv: data private to the driver
+ */
+struct counter_count_ext {
+ const char *name;
+ ssize_t (*read)(struct counter_device *counter,
+ struct counter_count *count, void *priv, char *buf);
+ ssize_t (*write)(struct counter_device *counter,
+ struct counter_count *count, void *priv,
+ const char *buf, size_t len);
+ void *priv;
+};
+
+enum counter_count_function {
+ COUNTER_COUNT_FUNCTION_INCREASE = 0,
+ COUNTER_COUNT_FUNCTION_DECREASE,
+ COUNTER_COUNT_FUNCTION_PULSE_DIRECTION,
+ COUNTER_COUNT_FUNCTION_QUADRATURE_X1_A,
+ COUNTER_COUNT_FUNCTION_QUADRATURE_X1_B,
+ COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A,
+ COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B,
+ COUNTER_COUNT_FUNCTION_QUADRATURE_X4
+};
+
+/**
+ * struct counter_count - Counter Count node
+ * @id: unique ID used to identify Count
+ * @name: device-specific Count name; ideally, this should match
+ * the name as it appears in the datasheet documentation
+ * @function: index of current function mode
+ * @functions_list: array available function modes
+ * @num_functions: number of function modes specified in @functions_list
+ * @synapses: array of synapses for initialization
+ * @num_synapses: number of synapses specified in @synapses
+ * @ext: optional array of Counter Count extensions
+ * @num_ext: number of Counter Count extensions specified in @ext
+ * @priv: optional private data supplied by driver
+ */
+struct counter_count {
+ int id;
+ const char *name;
+
+ size_t function;
+ const enum counter_count_function *functions_list;
+ size_t num_functions;
+
+ struct counter_synapse *synapses;
+ size_t num_synapses;
+
+ const struct counter_count_ext *ext;
+ size_t num_ext;
+
+ void *priv;
+};
+
+/**
+ * struct counter_count_enum_ext - Count enum extension attribute
+ * @items: Array of strings
+ * @num_items: Number of items specified in @items
+ * @set: Set callback function; may be NULL
+ * @get: Get callback function; may be NULL
+ *
+ * The counter_count_enum_ext structure can be used to implement enum style
+ * Count extension attributes. Enum style attributes are those which have a set
+ * of strings that map to unsigned integer values. The Generic Counter Count
+ * enum extension helper code takes care of mapping between value and string, as
+ * well as generating a "_available" file which contains a list of all available
+ * items. The get callback is used to query the currently active item; the index
+ * of the item within the respective items array is returned via the 'item'
+ * parameter. The set callback is called when the attribute is updated; the
+ * 'item' parameter contains the index of the newly activated item within the
+ * respective items array.
+ */
+struct counter_count_enum_ext {
+ const char * const *items;
+ size_t num_items;
+ int (*get)(struct counter_device *counter, struct counter_count *count,
+ size_t *item);
+ int (*set)(struct counter_device *counter, struct counter_count *count,
+ size_t item);
+};
+
+/**
+ * COUNTER_COUNT_ENUM() - Initialize Count enum extension
+ * @_name: Attribute name
+ * @_e: Pointer to a counter_count_enum_ext structure
+ *
+ * This should usually be used together with COUNTER_COUNT_ENUM_AVAILABLE()
+ */
+#define COUNTER_COUNT_ENUM(_name, _e) \
+{ \
+ .name = (_name), \
+ .read = counter_count_enum_read, \
+ .write = counter_count_enum_write, \
+ .priv = (_e) \
+}
+
+/**
+ * COUNTER_COUNT_ENUM_AVAILABLE() - Initialize Count enum available extension
+ * @_name: Attribute name ("_available" will be appended to the name)
+ * @_e: Pointer to a counter_count_enum_ext structure
+ *
+ * Creates a read only attribute that lists all the available enum items in a
+ * newline separated list. This should usually be used together with
+ * COUNTER_COUNT_ENUM()
+ */
+#define COUNTER_COUNT_ENUM_AVAILABLE(_name, _e) \
+{ \
+ .name = (_name "_available"), \
+ .read = counter_count_enum_available_read, \
+ .priv = (_e) \
+}
+
+/**
+ * struct counter_device_attr_group - internal container for attribute group
+ * @attr_group: Counter sysfs attributes group
+ * @attr_list: list to keep track of created Counter sysfs attributes
+ * @num_attr: number of Counter sysfs attributes
+ */
+struct counter_device_attr_group {
+ struct attribute_group attr_group;
+ struct list_head attr_list;
+ size_t num_attr;
+};
+
+/**
+ * struct counter_device_state - internal state container for a Counter device
+ * @id: unique ID used to identify the Counter
+ * @dev: internal device structure
+ * @groups_list: attribute groups list (for Signals, Counts, and ext)
+ * @num_groups: number of attribute groups containers
+ * @groups: Counter sysfs attribute groups (to populate @dev.groups)
+ */
+struct counter_device_state {
+ int id;
+ struct device dev;
+ struct counter_device_attr_group *groups_list;
+ size_t num_groups;
+ const struct attribute_group **groups;
+};
+
+/**
+ * struct counter_signal_read_value - Opaque Signal read value
+ * @buf: string representation of Signal read value
+ * @len: length of string in @buf
+ */
+struct counter_signal_read_value {
+ char *buf;
+ size_t len;
+};
+
+/**
+ * struct counter_count_read_value - Opaque Count read value
+ * @buf: string representation of Count read value
+ * @len: length of string in @buf
+ */
+struct counter_count_read_value {
+ char *buf;
+ size_t len;
+};
+
+/**
+ * struct counter_count_write_value - Opaque Count write value
+ * @buf: string representation of Count write value
+ */
+struct counter_count_write_value {
+ const char *buf;
+};
+
+/**
+ * struct counter_ops - Callbacks from driver
+ * @signal_read: optional read callback for Signal attribute. The read
+ * value of the respective Signal should be passed back via
+ * the val parameter. val points to an opaque type which
+ * should be set only by calling the
+ * counter_signal_read_value_set function from within the
+ * signal_read callback.
+ * @count_read: optional read callback for Count attribute. The read
+ * value of the respective Count should be passed back via
+ * the val parameter. val points to an opaque type which
+ * should be set only by calling the
+ * counter_count_read_value_set function from within the
+ * count_read callback.
+ * @count_write: optional write callback for Count attribute. The write
+ * value for the respective Count is passed in via the val
+ * parameter. val points to an opaque type which should be
+ * accessed only by calling the
+ * counter_count_write_value_get function.
+ * @function_get: function to get the current count function mode. Returns
+ * 0 on success and negative error code on error. The index
+ * of the respective Count's returned function mode should
+ * be passed back via the function parameter.
+ * @function_set: function to set the count function mode. function is the
+ * index of the requested function mode from the respective
+ * Count's functions_list array.
+ * @action_get: function to get the current action mode. Returns 0 on
+ * success and negative error code on error. The index of
+ * the respective Signal's returned action mode should be
+ * passed back via the action parameter.
+ * @action_set: function to set the action mode. action is the index of
+ * the requested action mode from the respective Synapse's
+ * actions_list array.
+ */
+struct counter_ops {
+ int (*signal_read)(struct counter_device *counter,
+ struct counter_signal *signal,
+ struct counter_signal_read_value *val);
+ int (*count_read)(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_count_read_value *val);
+ int (*count_write)(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_count_write_value *val);
+ int (*function_get)(struct counter_device *counter,
+ struct counter_count *count, size_t *function);
+ int (*function_set)(struct counter_device *counter,
+ struct counter_count *count, size_t function);
+ int (*action_get)(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse, size_t *action);
+ int (*action_set)(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse, size_t action);
+};
+
+/**
+ * struct counter_device_ext - Counter device extension
+ * @name: attribute name
+ * @read: read callback for this attribute; may be NULL
+ * @write: write callback for this attribute; may be NULL
+ * @priv: data private to the driver
+ */
+struct counter_device_ext {
+ const char *name;
+ ssize_t (*read)(struct counter_device *counter, void *priv, char *buf);
+ ssize_t (*write)(struct counter_device *counter, void *priv,
+ const char *buf, size_t len);
+ void *priv;
+};
+
+/**
+ * struct counter_device_enum_ext - Counter enum extension attribute
+ * @items: Array of strings
+ * @num_items: Number of items specified in @items
+ * @set: Set callback function; may be NULL
+ * @get: Get callback function; may be NULL
+ *
+ * The counter_device_enum_ext structure can be used to implement enum style
+ * Counter extension attributes. Enum style attributes are those which have a
+ * set of strings that map to unsigned integer values. The Generic Counter enum
+ * extension helper code takes care of mapping between value and string, as well
+ * as generating a "_available" file which contains a list of all available
+ * items. The get callback is used to query the currently active item; the index
+ * of the item within the respective items array is returned via the 'item'
+ * parameter. The set callback is called when the attribute is updated; the
+ * 'item' parameter contains the index of the newly activated item within the
+ * respective items array.
+ */
+struct counter_device_enum_ext {
+ const char * const *items;
+ size_t num_items;
+ int (*get)(struct counter_device *counter, size_t *item);
+ int (*set)(struct counter_device *counter, size_t item);
+};
+
+/**
+ * COUNTER_DEVICE_ENUM() - Initialize Counter enum extension
+ * @_name: Attribute name
+ * @_e: Pointer to a counter_device_enum_ext structure
+ *
+ * This should usually be used together with COUNTER_DEVICE_ENUM_AVAILABLE()
+ */
+#define COUNTER_DEVICE_ENUM(_name, _e) \
+{ \
+ .name = (_name), \
+ .read = counter_device_enum_read, \
+ .write = counter_device_enum_write, \
+ .priv = (_e) \
+}
+
+/**
+ * COUNTER_DEVICE_ENUM_AVAILABLE() - Initialize Counter enum available extension
+ * @_name: Attribute name ("_available" will be appended to the name)
+ * @_e: Pointer to a counter_device_enum_ext structure
+ *
+ * Creates a read only attribute that lists all the available enum items in a
+ * newline separated list. This should usually be used together with
+ * COUNTER_DEVICE_ENUM()
+ */
+#define COUNTER_DEVICE_ENUM_AVAILABLE(_name, _e) \
+{ \
+ .name = (_name "_available"), \
+ .read = counter_device_enum_available_read, \
+ .priv = (_e) \
+}
+
+/**
+ * struct counter_device - Counter data structure
+ * @name: name of the device as it appears in the datasheet
+ * @parent: optional parent device providing the counters
+ * @device_state: internal device state container
+ * @ops: callbacks from driver
+ * @signals: array of Signals
+ * @num_signals: number of Signals specified in @signals
+ * @counts: array of Counts
+ * @num_counts: number of Counts specified in @counts
+ * @ext: optional array of Counter device extensions
+ * @num_ext: number of Counter device extensions specified in @ext
+ * @priv: optional private data supplied by driver
+ */
+struct counter_device {
+ const char *name;
+ struct device *parent;
+ struct counter_device_state *device_state;
+
+ const struct counter_ops *ops;
+
+ struct counter_signal *signals;
+ size_t num_signals;
+ struct counter_count *counts;
+ size_t num_counts;
+
+ const struct counter_device_ext *ext;
+ size_t num_ext;
+
+ void *priv;
+};
+
+enum counter_signal_level {
+ COUNTER_SIGNAL_LEVEL_LOW = 0,
+ COUNTER_SIGNAL_LEVEL_HIGH
+};
+
+enum counter_signal_value_type {
+ COUNTER_SIGNAL_LEVEL = 0
+};
+
+enum counter_count_value_type {
+ COUNTER_COUNT_POSITION = 0,
+};
+
+void counter_signal_read_value_set(struct counter_signal_read_value *const val,
+ const enum counter_signal_value_type type,
+ void *const data);
+void counter_count_read_value_set(struct counter_count_read_value *const val,
+ const enum counter_count_value_type type,
+ void *const data);
+int counter_count_write_value_get(void *const data,
+ const enum counter_count_value_type type,
+ const struct counter_count_write_value *const val);
+
+int counter_register(struct counter_device *const counter);
+void counter_unregister(struct counter_device *const counter);
+int devm_counter_register(struct device *dev,
+ struct counter_device *const counter);
+void devm_counter_unregister(struct device *dev,
+ struct counter_device *const counter);
+
+#endif /* _COUNTER_H_ */
diff --git a/include/linux/counter_enum.h b/include/linux/counter_enum.h
new file mode 100644
index 000000000000..9f917298a88f
--- /dev/null
+++ b/include/linux/counter_enum.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Counter interface enum functions
+ * Copyright (C) 2018 William Breathitt Gray
+ */
+#ifndef _COUNTER_ENUM_H_
+#define _COUNTER_ENUM_H_
+
+#include <linux/types.h>
+
+struct counter_device;
+struct counter_signal;
+struct counter_count;
+
+ssize_t counter_signal_enum_read(struct counter_device *counter,
+ struct counter_signal *signal, void *priv,
+ char *buf);
+ssize_t counter_signal_enum_write(struct counter_device *counter,
+ struct counter_signal *signal, void *priv,
+ const char *buf, size_t len);
+
+ssize_t counter_signal_enum_available_read(struct counter_device *counter,
+ struct counter_signal *signal,
+ void *priv, char *buf);
+
+ssize_t counter_count_enum_read(struct counter_device *counter,
+ struct counter_count *count, void *priv,
+ char *buf);
+ssize_t counter_count_enum_write(struct counter_device *counter,
+ struct counter_count *count, void *priv,
+ const char *buf, size_t len);
+
+ssize_t counter_count_enum_available_read(struct counter_device *counter,
+ struct counter_count *count,
+ void *priv, char *buf);
+
+ssize_t counter_device_enum_read(struct counter_device *counter, void *priv,
+ char *buf);
+ssize_t counter_device_enum_write(struct counter_device *counter, void *priv,
+ const char *buf, size_t len);
+
+ssize_t counter_device_enum_available_read(struct counter_device *counter,
+ void *priv, char *buf);
+
+#endif /* _COUNTER_ENUM_H_ */
--
2.21.0
^ permalink raw reply related
* [PATCH v10 00/18] Introduce the Counter subsystem
From: William Breathitt Gray @ 2019-04-02 6:30 UTC (permalink / raw)
To: gregkh
Cc: mark.rutland, benjamin.gaignard, linux-pwm, linux-iio,
patrick.havelange, thierry.reding, pmeerw, lars, daniel.lezcano,
linux-arm-kernel, devicetree, david, William Breathitt Gray,
robh+dt, tglx, fabrice.gasnier, esben, shawnguo, linux-kernel,
leoyang.li, knaack.h, akpm, linuxppc-dev, jic23
Changes in v10:
- Fix minor typographical errors in documentation
- Merge the FlexTimer Module Quadrature decoder counter driver patches
This revision is functionally identical to the last; changes in this
version were made to fix minor typos in the documentation files and also
to pull in the new FTM quadrature decoder counter driver.
The Generic Counter API has been and is still in a feature freeze until
it is merged into the mainline. The following features will be
investigated after the merge: interrupt support for counter devices, and
a character device interface for low-latency applications.
Benjamin Gaignard (2):
counter: Add STM32 Timer quadrature encoder
dt-bindings: counter: Document stm32 quadrature encoder
Fabrice Gasnier (2):
counter: stm32-lptimer: add counter device
dt-bindings: counter: Adjust dt-bindings for STM32 lptimer move
Patrick Havelange (7):
include/fsl: add common FlexTimer #defines in a separate header.
drivers/pwm: pwm-fsl-ftm: use common header for FlexTimer #defines
drivers/clocksource: timer-fsl-ftm: use common header for FlexTimer
#defines
dt-bindings: counter: ftm-quaddec
counter: add FlexTimer Module Quadrature decoder counter driver
counter: ftm-quaddec: Documentation: Add specific counter sysfs
documentation
LS1021A: dtsi: add ftm quad decoder entries
William Breathitt Gray (7):
counter: Introduce the Generic Counter interface
counter: Documentation: Add Generic Counter sysfs documentation
docs: Add Generic Counter interface documentation
iio: 104-quad-8: Update license boilerplate
counter: 104-quad-8: Add Generic Counter interface support
counter: 104-quad-8: Documentation: Add Generic Counter sysfs
documentation
iio: counter: Add deprecation markings for IIO Counter attributes
Documentation/ABI/testing/sysfs-bus-counter | 230 +++
.../ABI/testing/sysfs-bus-counter-104-quad-8 | 36 +
.../ABI/testing/sysfs-bus-counter-ftm-quaddec | 16 +
Documentation/ABI/testing/sysfs-bus-iio | 8 +
.../testing/sysfs-bus-iio-counter-104-quad-8 | 16 +
.../bindings/counter/ftm-quaddec.txt | 18 +
.../{iio => }/counter/stm32-lptimer-cnt.txt | 0
.../bindings/counter/stm32-timer-cnt.txt | 31 +
.../devicetree/bindings/mfd/stm32-lptimer.txt | 2 +-
.../devicetree/bindings/mfd/stm32-timers.txt | 7 +
Documentation/driver-api/generic-counter.rst | 342 ++++
Documentation/driver-api/index.rst | 1 +
MAINTAINERS | 15 +-
arch/arm/boot/dts/ls1021a.dtsi | 28 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/clocksource/timer-fsl-ftm.c | 15 +-
drivers/{iio => }/counter/104-quad-8.c | 782 +++++++-
drivers/counter/Kconfig | 60 +
drivers/counter/Makefile | 10 +
drivers/counter/counter.c | 1567 +++++++++++++++++
drivers/counter/ftm-quaddec.c | 356 ++++
drivers/{iio => }/counter/stm32-lptimer-cnt.c | 361 +++-
drivers/counter/stm32-timer-cnt.c | 390 ++++
drivers/iio/Kconfig | 1 -
drivers/iio/Makefile | 1 -
drivers/iio/counter/Kconfig | 34 -
drivers/iio/counter/Makefile | 8 -
drivers/pwm/pwm-fsl-ftm.c | 44 +-
include/linux/counter.h | 510 ++++++
include/linux/counter_enum.h | 45 +
include/linux/fsl/ftm.h | 88 +
32 files changed, 4877 insertions(+), 148 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-bus-counter
create mode 100644 Documentation/ABI/testing/sysfs-bus-counter-104-quad-8
create mode 100644 Documentation/ABI/testing/sysfs-bus-counter-ftm-quaddec
create mode 100644 Documentation/devicetree/bindings/counter/ftm-quaddec.txt
rename Documentation/devicetree/bindings/{iio => }/counter/stm32-lptimer-cnt.txt (100%)
create mode 100644 Documentation/devicetree/bindings/counter/stm32-timer-cnt.txt
create mode 100644 Documentation/driver-api/generic-counter.rst
rename drivers/{iio => }/counter/104-quad-8.c (44%)
create mode 100644 drivers/counter/Kconfig
create mode 100644 drivers/counter/Makefile
create mode 100644 drivers/counter/counter.c
create mode 100644 drivers/counter/ftm-quaddec.c
rename drivers/{iio => }/counter/stm32-lptimer-cnt.c (51%)
create mode 100644 drivers/counter/stm32-timer-cnt.c
delete mode 100644 drivers/iio/counter/Kconfig
delete mode 100644 drivers/iio/counter/Makefile
create mode 100644 include/linux/counter.h
create mode 100644 include/linux/counter_enum.h
create mode 100644 include/linux/fsl/ftm.h
--
2.21.0
^ permalink raw reply
* Re: [PATCH stable v4.14 13/32] powerpc/fsl: Add barrier_nospec implementation for NXP PowerPC Book3E
From: Michael Ellerman @ 2019-04-02 6:19 UTC (permalink / raw)
To: Joakim Tjernlund, stable@vger.kernel.org,
gregkh@linuxfoundation.org
Cc: diana.craciun@nxp.com, linuxppc-dev@ozlabs.org, msuchanek@suse.de
In-Reply-To: <763028d666042f5642104b42aaa416c2867baa31.camel@infinera.com>
Joakim Tjernlund <Joakim.Tjernlund@infinera.com> writes:
> On Fri, 2019-03-29 at 22:26 +1100, Michael Ellerman wrote:
>> From: Diana Craciun <diana.craciun@nxp.com>
>>
>> commit ebcd1bfc33c7a90df941df68a6e5d4018c022fba upstream.
>>
>> Implement the barrier_nospec as a isync;sync instruction sequence.
>> The implementation uses the infrastructure built for BOOK3S 64.
>>
>> Signed-off-by: Diana Craciun <diana.craciun@nxp.com>
>> [mpe: Split out of larger patch]
>> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
>
> What is the performanc impact of these spectre fixes?
I've not seen any numbers from anyone.
It will depend on the workload, it's copy to/from user that is most
likely to show an impact.
We have a context switch benchmark in
tools/testing/selftests/powerpc/benchmarks/context_switch.c.
Running that with "--no-vector --no-altivec --no-fp --test=pipe" shows
about a 2.3% slow down vs booting with "nospectre_v1".
> Can I compile it away?
You can't actually, but you can disable it at runtime with
"nospectre_v1" on the kernel command line.
We could make it a user selectable compile time option if you really
want it to be.
cheers
^ permalink raw reply
* Re: [PATCH 2/5] powerpc: Fix vDSO clock_getres()
From: Christophe Leroy @ 2019-04-02 6:14 UTC (permalink / raw)
To: Vincenzo Frascino, linux-arch, linux-arm-kernel, linuxppc-dev,
linux-s390
Cc: Arnd Bergmann, Heiko Carstens, Catalin Marinas, Will Deacon,
Paul Mackerras, Greentime Hu, Martin Schwidefsky, Thomas Gleixner,
Vincent Chen, Shuah Khan
In-Reply-To: <20190401115152.32751-3-vincenzo.frascino@arm.com>
On 04/01/2019 11:51 AM, Vincenzo Frascino wrote:
> clock_getres in the vDSO library has to preserve the same behaviour
> of posix_get_hrtimer_res().
>
> In particular, posix_get_hrtimer_res() does:
> sec = 0;
> ns = hrtimer_resolution;
> and hrtimer_resolution depends on the enablement of the high
> resolution timers that can happen either at compile or at run time.
>
> Fix the powerpc vdso implementation of clock_getres keeping a copy of
> hrtimer_resolution in vdso data and using that directly.
>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/powerpc/include/asm/vdso_datapage.h | 2 ++
> arch/powerpc/kernel/asm-offsets.c | 2 +-
> arch/powerpc/kernel/time.c | 1 +
> arch/powerpc/kernel/vdso32/gettimeofday.S | 22 +++++++++++++++-------
> arch/powerpc/kernel/vdso64/gettimeofday.S | 22 +++++++++++++++-------
> 5 files changed, 34 insertions(+), 15 deletions(-)
>
[...]
> diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
> index 1e0bc5955a40..b21630079496 100644
> --- a/arch/powerpc/kernel/vdso32/gettimeofday.S
> +++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
> @@ -160,14 +160,21 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> cror cr0*4+eq,cr0*4+eq,cr1*4+eq
> bne cr0,99f
>
> - li r3,0
> - cmpli cr0,r4,0
> + mflr r12
> + .cfi_register lr,r12
> + mr r11,r4
> + bl __get_datapage@local
> + lwz r5,CLOCK_REALTIME_RES(r3)
> + li r4,0
> + cmplwi r11,0 /* check if res is NULL */
> + beq 1f
> +
> + stw r4,TSPC32_TV_SEC(r11)
> + stw r5,TSPC32_TV_NSEC(r11)
> +
> +1: mtlr r12
> crclr cr0*4+so
> - beqlr
> - lis r5,CLOCK_REALTIME_RES@h
> - ori r5,r5,CLOCK_REALTIME_RES@l
> - stw r3,TSPC32_TV_SEC(r4)
> - stw r5,TSPC32_TV_NSEC(r4)
> + li r3,0
> blr
The above can be done simpler, see below
@@ -160,12 +160,15 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
cror cr0*4+eq,cr0*4+eq,cr1*4+eq
bne cr0,99f
+ mflr r12
+ .cfi_register lr,r12
+ bl __get_datapage@local
+ lwz r5,CLOCK_REALTIME_RES(r3)
+ mtlr r12
li r3,0
cmpli cr0,r4,0
crclr cr0*4+so
beqlr
- lis r5,CLOCK_REALTIME_RES@h
- ori r5,r5,CLOCK_REALTIME_RES@l
stw r3,TSPC32_TV_SEC(r4)
stw r5,TSPC32_TV_NSEC(r4)
blr
Christophe
>
> /*
> @@ -175,6 +182,7 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> */
> 99:
> li r0,__NR_clock_getres
> + .cfi_restore lr
> sc
> blr
> .cfi_endproc
> diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
> index a4ed9edfd5f0..a7e49bddd475 100644
> --- a/arch/powerpc/kernel/vdso64/gettimeofday.S
> +++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
> @@ -190,14 +190,21 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> cror cr0*4+eq,cr0*4+eq,cr1*4+eq
> bne cr0,99f
>
> - li r3,0
> - cmpldi cr0,r4,0
> + mflr r12
> + .cfi_register lr,r12
> + mr r11, r4
> + bl V_LOCAL_FUNC(__get_datapage)
> + lwz r5,CLOCK_REALTIME_RES(r3)
> + li r4,0
> + cmpldi r11,0 /* check if res is NULL */
> + beq 1f
> +
> + std r4,TSPC64_TV_SEC(r11)
> + std r5,TSPC64_TV_NSEC(r11)
> +
> +1: mtlr r12
> crclr cr0*4+so
> - beqlr
> - lis r5,CLOCK_REALTIME_RES@h
> - ori r5,r5,CLOCK_REALTIME_RES@l
> - std r3,TSPC64_TV_SEC(r4)
> - std r5,TSPC64_TV_NSEC(r4)
> + li r3,0
> blr
The same type of simplification applies here too.
Christophe
>
> /*
> @@ -205,6 +212,7 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> */
> 99:
> li r0,__NR_clock_getres
> + .cfi_restore lr
> sc
> blr
> .cfi_endproc
>
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Add mmap to opal export sysfs nodes
From: Oliver @ 2019-04-02 6:07 UTC (permalink / raw)
To: Jordan Niethe; +Cc: linuxppc-dev
In-Reply-To: <20190315005420.20212-1-jniethe5@gmail.com>
On Fri, Mar 15, 2019 at 11:55 AM Jordan Niethe <jniethe5@gmail.com> wrote:
>
> The sysfs nodes created under /opal/exports/ do not currently support
> mmap. Skiboot trace buffers are not yet added to this location but
> this is a suitable for them to be exported to. Adding mmap support makes
> using these trace buffers more convenient. The state in the header of
> the trace buffer is needed to ensure the read position has not been
> overwritten. Thus the header of the buffer must be read, then the
> read position itself. Using lseek/read to do this introduces a delay
> that could result in incorrect reads if the read position is overwritten
> after the header is read.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> arch/powerpc/platforms/powernv/opal.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
> index 2b0eca104f86..3cfc683bb060 100644
> --- a/arch/powerpc/platforms/powernv/opal.c
> +++ b/arch/powerpc/platforms/powernv/opal.c
> @@ -714,6 +714,15 @@ static ssize_t export_attr_read(struct file *fp, struct kobject *kobj,
> bin_attr->size);
> }
>
> +static int export_attr_mmap(struct file *fp, struct kobject *kobj,
> + struct bin_attribute *attr,
> + struct vm_area_struct *vma)
> +{
> + return remap_pfn_range(vma, vma->vm_start,
> + __pa(attr->private) >> PAGE_SHIFT,
> + attr->size, PAGE_READONLY);
> +}
> +
> /*
> * opal_export_attrs: creates a sysfs node for each property listed in
> * the device-tree under /ibm,opal/firmware/exports/
> @@ -759,6 +768,7 @@ static void opal_export_attrs(void)
> attr->attr.name = kstrdup(prop->name, GFP_KERNEL);
> attr->attr.mode = 0400;
> attr->read = export_attr_read;
> + attr->mmap = export_attr_mmap;
You are assuming that it's safe to allow the export to be mmap()ed
here and that's not always the case. e.g.
[16:56 oliveroh@localhost .../firmware/exports]$ lsprop
symbol_map 00000000 30125640 00000000 0003598d
hdat_map 00000000 31200000 00000000 00800000
phandle 100002e8 (268436200)
name "exports"
The symbol_map export there does not start (or end) at a page
boundary. If you allow user programs to mmap() that export it will
make everything from 0x30120000 to 0x30160000 and the additional space
might contain internal firmware data structures that we'd rather not
allow userspace to access.You can protect against that by validating
the export starts and ends on a page boundary and only populating the
.mmap when it's safe to do so.
> attr->private = __va(vals[0]);
> attr->size = vals[1];
>
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH 2/5] powerpc: Fix vDSO clock_getres()
From: Christophe Leroy @ 2019-04-02 5:54 UTC (permalink / raw)
To: Vincenzo Frascino, linux-arch, linux-arm-kernel, linuxppc-dev,
linux-s390
Cc: Arnd Bergmann, Heiko Carstens, Catalin Marinas, Will Deacon,
Paul Mackerras, Greentime Hu, Martin Schwidefsky, Thomas Gleixner,
Vincent Chen, Shuah Khan
In-Reply-To: <20190401115152.32751-3-vincenzo.frascino@arm.com>
On 04/01/2019 11:51 AM, Vincenzo Frascino wrote:
> clock_getres in the vDSO library has to preserve the same behaviour
> of posix_get_hrtimer_res().
>
> In particular, posix_get_hrtimer_res() does:
> sec = 0;
> ns = hrtimer_resolution;
> and hrtimer_resolution depends on the enablement of the high
> resolution timers that can happen either at compile or at run time.
>
> Fix the powerpc vdso implementation of clock_getres keeping a copy of
> hrtimer_resolution in vdso data and using that directly.
>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/powerpc/include/asm/vdso_datapage.h | 2 ++
Conflicts with commit b5b4453e7912 ("powerpc/vdso64: Fix CLOCK_MONOTONIC
inconsistencies across Y2038")
Christophe
> arch/powerpc/kernel/asm-offsets.c | 2 +-
> arch/powerpc/kernel/time.c | 1 +
> arch/powerpc/kernel/vdso32/gettimeofday.S | 22 +++++++++++++++-------
> arch/powerpc/kernel/vdso64/gettimeofday.S | 22 +++++++++++++++-------
> 5 files changed, 34 insertions(+), 15 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/vdso_datapage.h b/arch/powerpc/include/asm/vdso_datapage.h
> index 1afe90ade595..4ae43fc77fe9 100644
> --- a/arch/powerpc/include/asm/vdso_datapage.h
> +++ b/arch/powerpc/include/asm/vdso_datapage.h
> @@ -86,6 +86,7 @@ struct vdso_data {
> __s32 wtom_clock_nsec;
> struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
> __u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
> + __u32 hrtimer_res; /* hrtimer resolution */
> __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of syscalls */
> __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
> };
> @@ -107,6 +108,7 @@ struct vdso_data {
> __s32 wtom_clock_nsec;
> struct timespec stamp_xtime; /* xtime as at tb_orig_stamp */
> __u32 stamp_sec_fraction; /* fractional seconds of stamp_xtime */
> + __u32 hrtimer_res; /* hrtimer resolution */
> __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of syscalls */
> __u32 dcache_block_size; /* L1 d-cache block size */
> __u32 icache_block_size; /* L1 i-cache block size */
> diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
> index 86a61e5f8285..52e4b98a8492 100644
> --- a/arch/powerpc/kernel/asm-offsets.c
> +++ b/arch/powerpc/kernel/asm-offsets.c
> @@ -383,6 +383,7 @@ int main(void)
> OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
> OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
> OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
> + OFFSET(CLOCK_REALTIME_RES, vdso_data, hrtimer_res);
> OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
> OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
> OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
> @@ -413,7 +414,6 @@ int main(void)
> DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
> DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
> DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
> - DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
>
> #ifdef CONFIG_BUG
> DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
> diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
> index bc0503ef9c9c..62c04a6746d8 100644
> --- a/arch/powerpc/kernel/time.c
> +++ b/arch/powerpc/kernel/time.c
> @@ -955,6 +955,7 @@ void update_vsyscall(struct timekeeper *tk)
> vdso_data->wtom_clock_nsec = tk->wall_to_monotonic.tv_nsec;
> vdso_data->stamp_xtime = xt;
> vdso_data->stamp_sec_fraction = frac_sec;
> + vdso_data->hrtimer_res = hrtimer_resolution;
> smp_wmb();
> ++(vdso_data->tb_update_count);
> }
> diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S
> index 1e0bc5955a40..b21630079496 100644
> --- a/arch/powerpc/kernel/vdso32/gettimeofday.S
> +++ b/arch/powerpc/kernel/vdso32/gettimeofday.S
> @@ -160,14 +160,21 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> cror cr0*4+eq,cr0*4+eq,cr1*4+eq
> bne cr0,99f
>
> - li r3,0
> - cmpli cr0,r4,0
> + mflr r12
> + .cfi_register lr,r12
> + mr r11,r4
> + bl __get_datapage@local
> + lwz r5,CLOCK_REALTIME_RES(r3)
> + li r4,0
> + cmplwi r11,0 /* check if res is NULL */
> + beq 1f
> +
> + stw r4,TSPC32_TV_SEC(r11)
> + stw r5,TSPC32_TV_NSEC(r11)
> +
> +1: mtlr r12
> crclr cr0*4+so
> - beqlr
> - lis r5,CLOCK_REALTIME_RES@h
> - ori r5,r5,CLOCK_REALTIME_RES@l
> - stw r3,TSPC32_TV_SEC(r4)
> - stw r5,TSPC32_TV_NSEC(r4)
> + li r3,0
> blr
>
> /*
> @@ -175,6 +182,7 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> */
> 99:
> li r0,__NR_clock_getres
> + .cfi_restore lr
> sc
> blr
> .cfi_endproc
> diff --git a/arch/powerpc/kernel/vdso64/gettimeofday.S b/arch/powerpc/kernel/vdso64/gettimeofday.S
> index a4ed9edfd5f0..a7e49bddd475 100644
> --- a/arch/powerpc/kernel/vdso64/gettimeofday.S
> +++ b/arch/powerpc/kernel/vdso64/gettimeofday.S
> @@ -190,14 +190,21 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> cror cr0*4+eq,cr0*4+eq,cr1*4+eq
> bne cr0,99f
>
> - li r3,0
> - cmpldi cr0,r4,0
> + mflr r12
> + .cfi_register lr,r12
> + mr r11, r4
> + bl V_LOCAL_FUNC(__get_datapage)
> + lwz r5,CLOCK_REALTIME_RES(r3)
> + li r4,0
> + cmpldi r11,0 /* check if res is NULL */
> + beq 1f
> +
> + std r4,TSPC64_TV_SEC(r11)
> + std r5,TSPC64_TV_NSEC(r11)
> +
> +1: mtlr r12
> crclr cr0*4+so
> - beqlr
> - lis r5,CLOCK_REALTIME_RES@h
> - ori r5,r5,CLOCK_REALTIME_RES@l
> - std r3,TSPC64_TV_SEC(r4)
> - std r5,TSPC64_TV_NSEC(r4)
> + li r3,0
> blr
>
> /*
> @@ -205,6 +212,7 @@ V_FUNCTION_BEGIN(__kernel_clock_getres)
> */
> 99:
> li r0,__NR_clock_getres
> + .cfi_restore lr
> sc
> blr
> .cfi_endproc
>
^ permalink raw reply
* Re: linux-next: build failure after merge of the sound-asoc tree
From: Mark Brown @ 2019-04-02 5:14 UTC (permalink / raw)
To: Michael Ellerman
Cc: Stephen Rothwell, Liam Girdwood, Annaliese McDermond,
Linux Kernel Mailing List, linuxppc-dev, Linux Next Mailing List,
Paul Mackerras
In-Reply-To: <87tvfiou8f.fsf@concordia.ellerman.id.au>
[-- Attachment #1: Type: text/plain, Size: 459 bytes --]
On Mon, Apr 01, 2019 at 10:11:44PM +1100, Michael Ellerman wrote:
> Anyway I think what you've done in next, make the code depend on
> COMMON_CLOCK, is the best option. If anyone cares about that driver on
> powerpc platforms that don't support COMMON_CLOCK they should speak up.
It's probably fine for now for this one driver but it's going to cause
issues going forwards since we're trying to make the framework's clock
handling more standard.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH kernel] powerpc/mm_iommu: Allow pinning large regions
From: Alexey Kardashevskiy @ 2019-04-02 4:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alexey Kardashevskiy, Aneesh Kumar K.V, David Gibson
When called with vmas_arg==NULL, get_user_pages_longterm() allocates
an array of nr_pages*8 which can easily get greater that the max order,
for example, registering memory for a 256GB guest does this and fails
in __alloc_pages_nodemask().
This adds a loop over chunks of entries to fit the max order limit.
Fixes: 678e174c4c16 ("powerpc/mm/iommu: allow migration of cma allocated pages during mm_iommu_do_alloc", 2019-03-05)
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
arch/powerpc/mm/mmu_context_iommu.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/mm/mmu_context_iommu.c b/arch/powerpc/mm/mmu_context_iommu.c
index 36a826e23d45..e058064b013c 100644
--- a/arch/powerpc/mm/mmu_context_iommu.c
+++ b/arch/powerpc/mm/mmu_context_iommu.c
@@ -131,6 +131,7 @@ long mm_iommu_new(struct mm_struct *mm, unsigned long ua, unsigned long entries,
unsigned int pageshift, mem_pageshift;
struct page **hpages;
phys_addr_t *hpas;
+ unsigned long entry, chunk, pinned;
mutex_lock(&mem_list_mutex);
if (mm_iommu_find(mm, ua, entries)) {
@@ -152,13 +153,29 @@ long mm_iommu_new(struct mm_struct *mm, unsigned long ua, unsigned long entries,
}
down_read(&mm->mmap_sem);
- ret = get_user_pages_longterm(ua, entries, FOLL_WRITE, hpages, NULL);
+ chunk = (1UL << (PAGE_SHIFT + MAX_ORDER - 1)) /
+ sizeof(struct vm_area_struct *);
+ chunk = min(chunk, entries);
+ for (entry = 0, pinned = 0; entry < entries; entry += chunk) {
+ unsigned long n = min(entries - entry, chunk);
+
+ ret = get_user_pages_longterm(ua + (entry << PAGE_SHIFT), n,
+ FOLL_WRITE, hpages + entry, NULL);
+ if (ret == n) {
+ pinned += n;
+ continue;
+ }
+ if (ret >= 0)
+ pinned += ret;
+ break;
+ }
up_read(&mm->mmap_sem);
- if (ret != entries) {
+ if (pinned != entries) {
/* free the reference taken */
- for (i = 0; i < ret; i++)
+ for (i = 0; i < pinned; i++)
put_page(hpages[i]);
- ret = -EFAULT;
+ if (!ret)
+ ret = -EFAULT;
goto cleanup_exit;
}
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 2/2] powerpc/perf: Add generic compat mode pmu driver
From: Madhavan Srinivasan @ 2019-04-02 3:44 UTC (permalink / raw)
To: kbuild test robot; +Cc: linuxppc-dev, kbuild-all
In-Reply-To: <201904011812.L1ZHWkLf%lkp@intel.com>
On 01/04/19 4:00 PM, kbuild test robot wrote:
> Hi Madhavan,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on v5.1-rc3 next-20190401]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
> url: https://github.com/0day-ci/linux/commits/Madhavan-Srinivasan/powerpc-perf-init-platform-pmu-driver-from-core-book3s/20190401-104458
> base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
> config: powerpc-pmac32_defconfig (attached as .config)
> compiler: powerpc-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> GCC_VERSION=7.2.0 make.cross ARCH=powerpc
>
> All errors (new ones prefixed by >>):
>
> arch/powerpc/perf/core-book3s.o: In function `init_ppc64_pmu':
> core-book3s.c:(.init.text+0xc): undefined reference to `init_power5_pmu'
> core-book3s.c:(.init.text+0x18): undefined reference to `init_power5p_pmu'
> core-book3s.c:(.init.text+0x24): undefined reference to `init_power6_pmu'
> core-book3s.c:(.init.text+0x30): undefined reference to `init_power7_pmu'
> core-book3s.c:(.init.text+0x3c): undefined reference to `init_power8_pmu'
> core-book3s.c:(.init.text+0x48): undefined reference to `init_power9_pmu'
> core-book3s.c:(.init.text+0x54): undefined reference to `init_ppc970_pmu'
>>> core-book3s.c:(.init.text+0x6c): undefined reference to `init_generic_compat_pmu'
My bad, missed to add the code under CONFIG_64.
will send out a newer version.
Maddy
> ---
> 0-DAY kernel test infrastructure Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* Re: [PATCH 06/13] soc/fsl/qbman_portals: add APIs to retrieve the probing status
From: Li Yang @ 2019-04-01 22:12 UTC (permalink / raw)
To: Laurentiu Tudor
Cc: madalin.bucur, Netdev, Roy Pledge, lkml, Linux IOMMU,
camelia.groza, linuxppc-dev, David Miller,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190329140014.8126-7-laurentiu.tudor@nxp.com>
On Fri, Mar 29, 2019 at 9:03 AM <laurentiu.tudor@nxp.com> wrote:
>
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> Add a couple of new APIs to check the probing status of the required
> cpu bound qman and bman portals:
> 'int bman_portals_probed()' and 'int qman_portals_probed()'.
> They return the following values.
> * 1 if qman/bman portals were all probed correctly
> * 0 if qman/bman portals were not yet probed
> * -1 if probing of qman/bman portals failed
> Portals are considered successful probed if no error occurred during
> the probing of any of the portals and if enough portals were probed
> to have one available for each cpu.
> The error handling paths were slightly rearranged in order to fit this
> new functionality without being too intrusive.
> Drivers that use qman/bman portal driver services are required to use
> these APIs before calling any functions exported by these drivers or
> otherwise they will crash the kernel.
> First user will be the dpaa1 ethernet driver, coming in a subsequent
> patch.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
> drivers/soc/fsl/qbman/bman_portal.c | 22 ++++++++++++++++++----
> drivers/soc/fsl/qbman/qman_portal.c | 23 +++++++++++++++++++----
> include/soc/fsl/bman.h | 8 ++++++++
> include/soc/fsl/qman.h | 9 +++++++++
> 4 files changed, 54 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/soc/fsl/qbman/bman_portal.c b/drivers/soc/fsl/qbman/bman_portal.c
> index 2c95cf59f3e7..7819bc29936d 100644
> --- a/drivers/soc/fsl/qbman/bman_portal.c
> +++ b/drivers/soc/fsl/qbman/bman_portal.c
> @@ -32,6 +32,7 @@
>
> static struct bman_portal *affine_bportals[NR_CPUS];
> static struct cpumask portal_cpus;
> +static int __bman_portals_probed;
> /* protect bman global registers and global data shared among portals */
> static DEFINE_SPINLOCK(bman_lock);
>
> @@ -87,6 +88,12 @@ static int bman_online_cpu(unsigned int cpu)
> return 0;
> }
>
> +int bman_portals_probed(void)
> +{
> + return __bman_portals_probed;
> +}
> +EXPORT_SYMBOL_GPL(bman_portals_probed);
> +
> static int bman_portal_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -104,8 +111,10 @@ static int bman_portal_probe(struct platform_device *pdev)
> }
>
> pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
> - if (!pcfg)
> + if (!pcfg) {
> + __bman_portals_probed = -1;
> return -ENOMEM;
> + }
>
> pcfg->dev = dev;
>
> @@ -113,14 +122,14 @@ static int bman_portal_probe(struct platform_device *pdev)
> DPAA_PORTAL_CE);
> if (!addr_phys[0]) {
> dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
>
> addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
> DPAA_PORTAL_CI);
> if (!addr_phys[1]) {
> dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
>
> pcfg->cpu = -1;
> @@ -128,7 +137,7 @@ static int bman_portal_probe(struct platform_device *pdev)
> irq = platform_get_irq(pdev, 0);
> if (irq <= 0) {
> dev_err(dev, "Can't get %pOF IRQ'\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
> pcfg->irq = irq;
>
> @@ -156,6 +165,9 @@ static int bman_portal_probe(struct platform_device *pdev)
> }
>
> cpumask_set_cpu(cpu, &portal_cpus);
> + if (!__bman_portals_probed &&
> + cpumask_weight(&portal_cpus) == num_online_cpus())
> + __bman_portals_probed = 1;
Given the fact that the portal_cpus bit will get set even for offline
cpus, this is not correct either. Probably the previous code for
checking cpu >= nr_cpu_ids is actually the right way to do it.
> spin_unlock(&bman_lock);
> pcfg->cpu = cpu;
>
> @@ -175,6 +187,8 @@ static int bman_portal_probe(struct platform_device *pdev)
> err_ioremap2:
> memunmap(pcfg->addr_virt_ce);
> err_ioremap1:
> + __bman_portals_probed = -1;
> +
> return -ENXIO;
> }
>
> diff --git a/drivers/soc/fsl/qbman/qman_portal.c b/drivers/soc/fsl/qbman/qman_portal.c
> index bce56da2b01f..11ba6c77c0d6 100644
> --- a/drivers/soc/fsl/qbman/qman_portal.c
> +++ b/drivers/soc/fsl/qbman/qman_portal.c
> @@ -39,6 +39,7 @@ EXPORT_SYMBOL(qman_dma_portal);
> #define CONFIG_FSL_DPA_PIRQ_FAST 1
>
> static struct cpumask portal_cpus;
> +static int __qman_portals_probed;
> /* protect qman global registers and global data shared among portals */
> static DEFINE_SPINLOCK(qman_lock);
>
> @@ -221,6 +222,12 @@ static int qman_online_cpu(unsigned int cpu)
> return 0;
> }
>
> +int qman_portals_probed(void)
> +{
> + return __qman_portals_probed;
> +}
> +EXPORT_SYMBOL_GPL(qman_portals_probed);
> +
> static int qman_portal_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -240,8 +247,10 @@ static int qman_portal_probe(struct platform_device *pdev)
> }
>
> pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
> - if (!pcfg)
> + if (!pcfg) {
> + __qman_portals_probed = -1;
> return -ENOMEM;
> + }
>
> pcfg->dev = dev;
>
> @@ -249,19 +258,20 @@ static int qman_portal_probe(struct platform_device *pdev)
> DPAA_PORTAL_CE);
> if (!addr_phys[0]) {
> dev_err(dev, "Can't get %pOF property 'reg::CE'\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
>
> addr_phys[1] = platform_get_resource(pdev, IORESOURCE_MEM,
> DPAA_PORTAL_CI);
> if (!addr_phys[1]) {
> dev_err(dev, "Can't get %pOF property 'reg::CI'\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
>
> err = of_property_read_u32(node, "cell-index", &val);
> if (err) {
> dev_err(dev, "Can't get %pOF property 'cell-index'\n", node);
> + __qman_portals_probed = -1;
> return err;
> }
> pcfg->channel = val;
> @@ -269,7 +279,7 @@ static int qman_portal_probe(struct platform_device *pdev)
> irq = platform_get_irq(pdev, 0);
> if (irq <= 0) {
> dev_err(dev, "Can't get %pOF IRQ\n", node);
> - return -ENXIO;
> + goto err_ioremap1;
> }
> pcfg->irq = irq;
>
> @@ -314,6 +324,9 @@ static int qman_portal_probe(struct platform_device *pdev)
> }
>
> cpumask_set_cpu(cpu, &portal_cpus);
> + if (!__qman_portals_probed &&
> + cpumask_weight(&portal_cpus) == num_online_cpus())
> + __qman_portals_probed = 1;
> spin_unlock(&qman_lock);
> pcfg->cpu = cpu;
>
> @@ -338,6 +351,8 @@ static int qman_portal_probe(struct platform_device *pdev)
> err_ioremap2:
> memunmap(pcfg->addr_virt_ce);
> err_ioremap1:
> + __qman_portals_probed = -1;
> +
> return -ENXIO;
> }
>
> diff --git a/include/soc/fsl/bman.h b/include/soc/fsl/bman.h
> index 5b99cb2ea5ef..173e4049d963 100644
> --- a/include/soc/fsl/bman.h
> +++ b/include/soc/fsl/bman.h
> @@ -133,5 +133,13 @@ int bman_acquire(struct bman_pool *pool, struct bm_buffer *bufs, u8 num);
> * failed to probe or 0 if the bman driver did not probed yet.
> */
> int bman_is_probed(void);
> +/**
> + * bman_portals_probed - Check if all cpu bound bman portals are probed
> + *
> + * Returns 1 if all the required cpu bound bman portals successfully probed,
> + * -1 if probe errors appeared or 0 if the bman portals did not yet finished
> + * probing.
> + */
> +int bman_portals_probed(void);
>
> #endif /* __FSL_BMAN_H */
> diff --git a/include/soc/fsl/qman.h b/include/soc/fsl/qman.h
> index 5cc7af06c1ba..aa31c05a103a 100644
> --- a/include/soc/fsl/qman.h
> +++ b/include/soc/fsl/qman.h
> @@ -1194,6 +1194,15 @@ int qman_release_cgrid(u32 id);
> */
> int qman_is_probed(void);
>
> +/**
> + * qman_portals_probed - Check if all cpu bound qman portals are probed
> + *
> + * Returns 1 if all the required cpu bound qman portals successfully probed,
> + * -1 if probe errors appeared or 0 if the qman portals did not yet finished
> + * probing.
> + */
> +int qman_portals_probed(void);
> +
> /**
> * qman_dqrr_get_ithresh - Get coalesce interrupt threshold
> * @portal: portal to get the value for
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH] ASoC: fsl_esai: Support synchronous mode
From: Nicolin Chen @ 2019-04-01 18:17 UTC (permalink / raw)
To: S.j. Wang
Cc: alsa-devel@alsa-project.org, timur@kernel.org,
Xiubo.Lee@gmail.com, festevam@gmail.com, broonie@kernel.org,
linuxppc-dev@lists.ozlabs.org
In-Reply-To: <1554118759-2403-1-git-send-email-shengjiu.wang@nxp.com>
Shengjiu,
On Mon, Apr 01, 2019 at 11:39:10AM +0000, S.j. Wang wrote:
> In ESAI synchronous mode, the clock is generated by Tx, So
> we should always set registers of Tx which relate with the
> bit clock and frame clock generation (TCCR, TCR, ECR), even
> there is only Rx is working.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
> ---
> sound/soc/fsl/fsl_esai.c | 28 +++++++++++++++++++++++++++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 3623aa9a6f2e..d9fcddd55c02 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -230,6 +230,21 @@ static int fsl_esai_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
> return -EINVAL;
> }
>
> + if (esai_priv->synchronous && !tx) {
> + switch (clk_id) {
> + case ESAI_HCKR_FSYS:
> + fsl_esai_set_dai_sysclk(dai, ESAI_HCKT_FSYS,
> + freq, dir);
> + break;
> + case ESAI_HCKR_EXTAL:
> + fsl_esai_set_dai_sysclk(dai, ESAI_HCKT_EXTAL,
> + freq, dir);
Not sure why you call set_dai_sysclk inside set_dai_sysclk again. It
feels very confusing to do so, especially without a comments.
> + break;
> + default:
> + return -EINVAL;
> + }
> + }
> +
> /* Bypass divider settings if the requirement doesn't change */
> if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
> return 0;
> @@ -537,10 +552,21 @@ static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
>
> bclk = params_rate(params) * slot_width * esai_priv->slots;
>
> - ret = fsl_esai_set_bclk(dai, tx, bclk);
> + ret = fsl_esai_set_bclk(dai, esai_priv->synchronous ? true : tx, bclk);
> if (ret)
> return ret;
>
> + if (esai_priv->synchronous && !tx) {
> + /* Use Normal mode to support monaural audio */
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
> + ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
> + ESAI_xCR_xMOD_NETWORK : 0);
> +
> + mask = ESAI_xCR_xSWS_MASK | ESAI_xCR_PADC;
> + val = ESAI_xCR_xSWS(slot_width, width) | ESAI_xCR_PADC;
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, mask, val);
> + }
Does synchronous mode require to set both TCR and RCR? or just TCR?
The code behind this part is doing the same setting to RCR. If that
is not needed any more for a synchronous recording, we should reuse
it instead of inserting a piece of redundant code. Otherwise, if we
need to set both, we should have two regmap_update_bits operations
back-to-back for TCR and RCR (and other registers too).
> +
> /* Use Normal mode to support monaural audio */
> regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
> ESAI_xCR_xMOD_MASK, params_channels(params) > 1 ?
In case that we only need to set TCR (more likely I feel), it would
feel less confusing to me, if we changed REG_ESAI_xCR(tx) here, for
example, to REG_ESAI_xCR(tx || sync). Yea, please add to the top a
'bool sync = esai_priv->synchronous;'.
Similarly, for ECR_ETO and ECR_ERO:
(tx || sync) ? ESAI_ECR_ETO : ESAI_ECR_ERO;
^ permalink raw reply
* [PATCH 5/5] kselftest: Extend vDSO selftest to clock_getres
From: Vincenzo Frascino @ 2019-04-01 11:51 UTC (permalink / raw)
To: linux-arch, linux-arm-kernel, linuxppc-dev, linux-s390
Cc: Arnd Bergmann, Heiko Carstens, Catalin Marinas, Will Deacon,
Paul Mackerras, Greentime Hu, Martin Schwidefsky, Thomas Gleixner,
Vincent Chen, Shuah Khan
In-Reply-To: <20190401115152.32751-1-vincenzo.frascino@arm.com>
The current version of the multiarch vDSO selftest verifies only
gettimeofday.
Extend the vDSO selftest to clock_getres, to verify that the
syscall and the vDSO library function return the same information.
The extension has been used to verify the hrtimer_resoltion fix.
Cc: Shuah Khan <shuah@kernel.org>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
---
tools/testing/selftests/vDSO/Makefile | 2 +
.../selftests/vDSO/vdso_clock_getres.c | 107 ++++++++++++++++++
2 files changed, 109 insertions(+)
create mode 100644 tools/testing/selftests/vDSO/vdso_clock_getres.c
diff --git a/tools/testing/selftests/vDSO/Makefile b/tools/testing/selftests/vDSO/Makefile
index 9e03d61f52fd..d5c5bfdf1ac1 100644
--- a/tools/testing/selftests/vDSO/Makefile
+++ b/tools/testing/selftests/vDSO/Makefile
@@ -5,6 +5,7 @@ uname_M := $(shell uname -m 2>/dev/null || echo not)
ARCH ?= $(shell echo $(uname_M) | sed -e s/i.86/x86/ -e s/x86_64/x86/)
TEST_GEN_PROGS := $(OUTPUT)/vdso_test
+TEST_GEN_PROGS += $(OUTPUT)/vdso_clock_getres
ifeq ($(ARCH),x86)
TEST_GEN_PROGS += $(OUTPUT)/vdso_standalone_test_x86
endif
@@ -18,6 +19,7 @@ endif
all: $(TEST_GEN_PROGS)
$(OUTPUT)/vdso_test: parse_vdso.c vdso_test.c
+$(OUTPUT)/vdso_clock_getres: vdso_clock_getres.c
$(OUTPUT)/vdso_standalone_test_x86: vdso_standalone_test_x86.c parse_vdso.c
$(CC) $(CFLAGS) $(CFLAGS_vdso_standalone_test_x86) \
vdso_standalone_test_x86.c parse_vdso.c \
diff --git a/tools/testing/selftests/vDSO/vdso_clock_getres.c b/tools/testing/selftests/vDSO/vdso_clock_getres.c
new file mode 100644
index 000000000000..589949f6ca90
--- /dev/null
+++ b/tools/testing/selftests/vDSO/vdso_clock_getres.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * vdso_clock_getres.c: Sample code to test clock_getres.
+ * Copyright (c) 2019 Arm Ltd.
+ *
+ * Compile with:
+ * gcc -std=gnu99 vdso_clock_getres.c
+ *
+ * Tested on ARM, ARM64, MIPS32, x86 (32-bit and 64-bit),
+ * Power (32-bit and 64-bit), S390x (32-bit and 64-bit).
+ * Might work on other architectures.
+ */
+#include <elf.h>
+#include <err.h>
+#include <fcntl.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <time.h>
+#include <sys/auxv.h>
+#include <sys/mman.h>
+#include <sys/time.h>
+#define _GNU_SOURCE
+#include <unistd.h>
+#include <sys/syscall.h>
+
+#include "../kselftest.h"
+
+static long syscall_clock_getres(clockid_t _clkid, struct timespec *_ts)
+{
+ long ret;
+
+ ret = syscall(SYS_clock_getres, _clkid, _ts);
+
+ return ret;
+}
+
+const char *vdso_clock_name[12] = {
+ "CLOCK_REALTIME",
+ "CLOCK_MONOTONIC",
+ "CLOCK_PROCESS_CPUTIME_ID",
+ "CLOCK_THREAD_CPUTIME_ID",
+ "CLOCK_MONOTONIC_RAW",
+ "CLOCK_REALTIME_COARSE",
+ "CLOCK_MONOTONIC_COARSE",
+ "CLOCK_BOOTTIME",
+ "CLOCK_REALTIME_ALARM",
+ "CLOCK_BOOTTIME_ALARM",
+ "CLOCK_SGI_CYCLE",
+ "CLOCK_TAI",
+};
+
+/*
+ * Macro to call clock_getres in vdso and by system call
+ * with different values for clock_id.
+ */
+#define vdso_test_clock(clock_id) \
+do { \
+ struct timespec x, y; \
+ printf("clock_id: %s", vdso_clock_name[clock_id]); \
+ clock_getres(clock_id, &x); \
+ syscall_clock_getres(clock_id, &y); \
+ if ((x.tv_sec != y.tv_sec) || (x.tv_sec != y.tv_sec)) { \
+ printf(" [FAIL]\n"); \
+ return KSFT_SKIP; \
+ } else { \
+ printf(" [PASS]\n"); \
+ } \
+} while (0)
+
+int main(int argc, char **argv)
+{
+
+#if _POSIX_TIMERS > 0
+
+#ifdef CLOCK_REALTIME
+ vdso_test_clock(CLOCK_REALTIME);
+#endif
+
+#ifdef CLOCK_BOOTTIME
+ vdso_test_clock(CLOCK_BOOTTIME);
+#endif
+
+#ifdef CLOCK_TAI
+ vdso_test_clock(CLOCK_TAI);
+#endif
+
+#ifdef CLOCK_REALTIME_COARSE
+ vdso_test_clock(CLOCK_REALTIME_COARSE);
+#endif
+
+#ifdef CLOCK_MONOTONIC
+ vdso_test_clock(CLOCK_MONOTONIC);
+#endif
+
+#ifdef CLOCK_MONOTONIC_RAW
+ vdso_test_clock(CLOCK_MONOTONIC_RAW);
+#endif
+
+#ifdef CLOCK_MONOTONIC_COARSE
+ vdso_test_clock(CLOCK_MONOTONIC_COARSE);
+#endif
+
+#endif
+
+ return 0;
+}
--
2.21.0
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