* [PATCH] powerpc: Use nid as fallback for chip_id
From: Srikar Dronamraju @ 2019-07-02 10:19 UTC (permalink / raw)
To: linuxppc-dev, Michael Ellerman, Vasant Hegde
Cc: Vaidyanathan Srinivasan, Srikar Dronamraju
One of the uses of chip_id is to find out all cores that are part of the same
chip. However ibm,chip_id property is not present in device-tree of PowerVM
Lpars. Hence lscpu output shows one core per socket and multiple cores.
Before the patch.
# lscpu
Architecture: ppc64le
Byte Order: Little Endian
CPU(s): 128
On-line CPU(s) list: 0-127
Thread(s) per core: 8
Core(s) per socket: 1
Socket(s): 16
NUMA node(s): 2
Model: 2.2 (pvr 004e 0202)
Model name: POWER9 (architected), altivec supported
Hypervisor vendor: pHyp
Virtualization type: para
L1d cache: 32K
L1i cache: 32K
L2 cache: 512K
L3 cache: 10240K
NUMA node0 CPU(s): 0-63
NUMA node1 CPU(s): 64-127
# cat /sys/devices/system/cpu/cpu0/topology/physical_package_id
-1
Signed-off-by: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
---
arch/powerpc/kernel/prom.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 7159e791a70d..0b8918b43580 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -867,18 +867,24 @@ EXPORT_SYMBOL(of_get_ibm_chip_id);
* @cpu: The logical cpu number.
*
* Return the value of the ibm,chip-id property corresponding to the given
- * logical cpu number. If the chip-id can not be found, returns -1.
+ * logical cpu number. If the chip-id can not be found, return nid.
+ *
*/
int cpu_to_chip_id(int cpu)
{
struct device_node *np;
+ int chip_id = -1;
np = of_get_cpu_node(cpu, NULL);
if (!np)
return -1;
+ chip_id = of_get_ibm_chip_id(np);
+ if (chip_id == -1)
+ chip_id = of_node_to_nid(np);
+
of_node_put(np);
- return of_get_ibm_chip_id(np);
+ return chip_id;
}
EXPORT_SYMBOL(cpu_to_chip_id);
--
2.18.1
^ permalink raw reply related
* Re: Re: [PATCH 1/3] arm64: mm: Add p?d_large() definitions
From: Will Deacon @ 2019-07-02 10:46 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Mark Rutland, Ard Biesheuvel, Catalin Marinas, Anshuman Khandual,
Will Deacon, Steven Price, linux-mm, Andrew Morton, linuxppc-dev,
linux-arm-kernel
In-Reply-To: <1562036522.cz5nnz6ri2.astroid@bobo.none>
On Tue, Jul 02, 2019 at 01:07:11PM +1000, Nicholas Piggin wrote:
> Will Deacon's on July 1, 2019 8:15 pm:
> > On Mon, Jul 01, 2019 at 11:03:51AM +0100, Steven Price wrote:
> >> On 01/07/2019 10:27, Will Deacon wrote:
> >> > On Sun, Jun 23, 2019 at 07:44:44PM +1000, Nicholas Piggin wrote:
> >> >> walk_page_range() is going to be allowed to walk page tables other than
> >> >> those of user space. For this it needs to know when it has reached a
> >> >> 'leaf' entry in the page tables. This information will be provided by the
> >> >> p?d_large() functions/macros.
> >> >
> >> > I can't remember whether or not I asked this before, but why not call
> >> > this macro p?d_leaf() if that's what it's identifying? "Large" and "huge"
> >> > are usually synonymous, so I find this naming needlessly confusing based
> >> > on this patch in isolation.
>
> Those page table macro names are horrible. Large, huge, leaf, wtf?
> They could do with a sensible renaming. But this series just follows
> naming that's alreay there on x86.
I realise that, and I wasn't meaning to have a go at you. Just wanted to
make my opinion clear by having a moan :)
Will
^ permalink raw reply
* [PATCH] powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state.
From: Madhavan Srinivasan @ 2019-07-02 10:58 UTC (permalink / raw)
To: mpe; +Cc: ego, Athira Rajeev, linuxppc-dev, npiggin, Madhavan Srinivasan
From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
commit 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
reimplemented book3S code to pltform/powernv/idle.c. But when doing so
missed to add the per-thread LDBAR update in the core_woken path of
the power9_idle_stop(). Patch fixes the same.
Fixes: 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
---
arch/powerpc/platforms/powernv/idle.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
index 2f4479b94ac3..fd14a6237954 100644
--- a/arch/powerpc/platforms/powernv/idle.c
+++ b/arch/powerpc/platforms/powernv/idle.c
@@ -758,7 +758,6 @@ static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on)
mtspr(SPRN_PTCR, sprs.ptcr);
mtspr(SPRN_RPR, sprs.rpr);
mtspr(SPRN_TSCR, sprs.tscr);
- mtspr(SPRN_LDBAR, sprs.ldbar);
if (pls >= pnv_first_tb_loss_level) {
/* TB loss */
@@ -790,6 +789,7 @@ static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on)
mtspr(SPRN_MMCR0, sprs.mmcr0);
mtspr(SPRN_MMCR1, sprs.mmcr1);
mtspr(SPRN_MMCR2, sprs.mmcr2);
+ mtspr(SPRN_LDBAR, sprs.ldbar);
mtspr(SPRN_SPRG3, local_paca->sprg_vdso);
--
2.20.1
^ permalink raw reply related
* [PATCH] powerpc/setup: Adjust six seq_printf() calls in show_cpuinfo()
From: Markus Elfring @ 2019-07-02 12:56 UTC (permalink / raw)
To: linuxppc-dev, Andrew Morton, Aneesh Kumar K.V,
Benjamin Herrenschmidt, Christophe Leroy, Michael Ellerman,
Mike Rapoport, Paul Mackerras
Cc: kernel-janitors, LKML
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Tue, 2 Jul 2019 14:41:42 +0200
A bit of information should be put into a sequence.
Thus improve the execution speed for this data output by better usage
of corresponding functions.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
arch/powerpc/kernel/setup-common.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 1f8db666468d..a381723b11bd 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -239,18 +239,17 @@ static int show_cpuinfo(struct seq_file *m, void *v)
maj = (pvr >> 8) & 0xFF;
min = pvr & 0xFF;
- seq_printf(m, "processor\t: %lu\n", cpu_id);
- seq_printf(m, "cpu\t\t: ");
+ seq_printf(m, "processor\t: %lu\ncpu\t\t: ", cpu_id);
if (cur_cpu_spec->pvr_mask && cur_cpu_spec->cpu_name)
- seq_printf(m, "%s", cur_cpu_spec->cpu_name);
+ seq_puts(m, cur_cpu_spec->cpu_name);
else
seq_printf(m, "unknown (%08x)", pvr);
if (cpu_has_feature(CPU_FTR_ALTIVEC))
- seq_printf(m, ", altivec supported");
+ seq_puts(m, ", altivec supported");
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
#ifdef CONFIG_TAU
if (cpu_has_feature(CPU_FTR_TAU)) {
@@ -332,7 +331,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
seq_printf(m, "bogomips\t: %lu.%02lu\n", loops_per_jiffy / (500000 / HZ),
(loops_per_jiffy / (5000 / HZ)) % 100);
- seq_printf(m, "\n");
+ seq_putc(m, '\n');
/* If this is the last cpu, print the summary */
if (cpumask_next(cpu_id, cpu_online_mask) >= nr_cpu_ids)
--
2.22.0
^ permalink raw reply related
* [PATCH -next] powerpc/powernv: Make some sysbols static
From: YueHaibing @ 2019-07-02 13:17 UTC (permalink / raw)
To: benh, paulus, mpe, robh, gregkh, tglx, allison, groug,
shilpa.bhat
Cc: YueHaibing, linuxppc-dev, linux-kernel
Fix sparse warnings:
arch/powerpc/platforms/powernv/opal-psr.c:20:1:
warning: symbol 'psr_mutex' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-psr.c:27:3:
warning: symbol 'psr_attrs' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-powercap.c:20:1:
warning: symbol 'powercap_mutex' was not declared. Should it be static?
arch/powerpc/platforms/powernv/opal-sensor-groups.c:20:1:
warning: symbol 'sg_mutex' was not declared. Should it be static?
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
arch/powerpc/platforms/powernv/opal-powercap.c | 2 +-
arch/powerpc/platforms/powernv/opal-psr.c | 4 ++--
arch/powerpc/platforms/powernv/opal-sensor-groups.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-powercap.c b/arch/powerpc/platforms/powernv/opal-powercap.c
index dc599e7..c16d44f 100644
--- a/arch/powerpc/platforms/powernv/opal-powercap.c
+++ b/arch/powerpc/platforms/powernv/opal-powercap.c
@@ -13,7 +13,7 @@
#include <asm/opal.h>
-DEFINE_MUTEX(powercap_mutex);
+static DEFINE_MUTEX(powercap_mutex);
static struct kobject *powercap_kobj;
diff --git a/arch/powerpc/platforms/powernv/opal-psr.c b/arch/powerpc/platforms/powernv/opal-psr.c
index b6ccb30..69d7e75 100644
--- a/arch/powerpc/platforms/powernv/opal-psr.c
+++ b/arch/powerpc/platforms/powernv/opal-psr.c
@@ -13,11 +13,11 @@
#include <asm/opal.h>
-DEFINE_MUTEX(psr_mutex);
+static DEFINE_MUTEX(psr_mutex);
static struct kobject *psr_kobj;
-struct psr_attr {
+static struct psr_attr {
u32 handle;
struct kobj_attribute attr;
} *psr_attrs;
diff --git a/arch/powerpc/platforms/powernv/opal-sensor-groups.c b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
index 31f13c1..f8ae1fb 100644
--- a/arch/powerpc/platforms/powernv/opal-sensor-groups.c
+++ b/arch/powerpc/platforms/powernv/opal-sensor-groups.c
@@ -13,7 +13,7 @@
#include <asm/opal.h>
-DEFINE_MUTEX(sg_mutex);
+static DEFINE_MUTEX(sg_mutex);
static struct kobject *sg_kobj;
--
2.7.4
^ permalink raw reply related
* Re: [v2 03/12] powerpc/mce: Add MCE notification chain
From: Reza Arbab @ 2019-07-02 14:55 UTC (permalink / raw)
To: Santosh Sivaraj
Cc: Aneesh Kumar K.V, Mahesh Salgaonkar, Nicholas Piggin,
Chandan Rajendra, linuxppc-dev
In-Reply-To: <20190702051932.511-4-santosh@fossix.org>
On Tue, Jul 02, 2019 at 10:49:23AM +0530, Santosh Sivaraj wrote:
>+static BLOCKING_NOTIFIER_HEAD(mce_notifier_list);
Mahesh suggested using an atomic notifier chain instead of blocking,
since we are in an interrupt.
--
Reza Arbab
^ permalink raw reply
* Re: [RFC PATCH] Replaces long number representation by BIT() macro
From: Michael Ellerman @ 2019-07-02 15:19 UTC (permalink / raw)
To: Leonardo Bras; +Cc: Leonardo Bras, Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <20190613180227.29558-1-leonardo@linux.ibm.com>
Hi Leonardo,
Leonardo Bras <leonardo@linux.ibm.com> writes:
> The main reason of this change is to make these bitmasks more readable.
>
> The macro ASM_CONST() just appends an UL to it's parameter, so it can be
> easily replaced by BIT_MASK, that already uses a UL representation.
>
> ASM_CONST() in this file may behave different if __ASSEMBLY__ is defined,
> as it is used on .S files, just leaving the parameter as is.
Thanks for the patch, but I don't consider this an improvement in
readability.
At boot we print the firmware features, eg:
firmware_features = 0x00000001c45ffc5f
And it's much easier to match that up to the full constants, than to the
bit numbers.
Similarly in memory or register dumps.
What we could do is switch to the `UL` macro from include/linux/const.h,
rather than using our own ASM_CONST.
cheers
> diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
> index 00bc42d95679..7a5b0cc0bc85 100644
> --- a/arch/powerpc/include/asm/firmware.h
> +++ b/arch/powerpc/include/asm/firmware.h
> @@ -14,46 +14,45 @@
>
> #ifdef __KERNEL__
>
> -#include <asm/asm-const.h>
> -
> +#include <linux/bits.h>
> /* firmware feature bitmask values */
>
> -#define FW_FEATURE_PFT ASM_CONST(0x0000000000000001)
> -#define FW_FEATURE_TCE ASM_CONST(0x0000000000000002)
> -#define FW_FEATURE_SPRG0 ASM_CONST(0x0000000000000004)
> -#define FW_FEATURE_DABR ASM_CONST(0x0000000000000008)
> -#define FW_FEATURE_COPY ASM_CONST(0x0000000000000010)
> -#define FW_FEATURE_ASR ASM_CONST(0x0000000000000020)
> -#define FW_FEATURE_DEBUG ASM_CONST(0x0000000000000040)
> -#define FW_FEATURE_TERM ASM_CONST(0x0000000000000080)
> -#define FW_FEATURE_PERF ASM_CONST(0x0000000000000100)
> -#define FW_FEATURE_DUMP ASM_CONST(0x0000000000000200)
> -#define FW_FEATURE_INTERRUPT ASM_CONST(0x0000000000000400)
> -#define FW_FEATURE_MIGRATE ASM_CONST(0x0000000000000800)
> -#define FW_FEATURE_PERFMON ASM_CONST(0x0000000000001000)
> -#define FW_FEATURE_CRQ ASM_CONST(0x0000000000002000)
> -#define FW_FEATURE_VIO ASM_CONST(0x0000000000004000)
> -#define FW_FEATURE_RDMA ASM_CONST(0x0000000000008000)
> -#define FW_FEATURE_LLAN ASM_CONST(0x0000000000010000)
> -#define FW_FEATURE_BULK_REMOVE ASM_CONST(0x0000000000020000)
> -#define FW_FEATURE_XDABR ASM_CONST(0x0000000000040000)
> -#define FW_FEATURE_MULTITCE ASM_CONST(0x0000000000080000)
> -#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
> -#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
> -#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
> -#define FW_FEATURE_HPT_RESIZE ASM_CONST(0x0000000001000000)
> -#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
> -#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
> -#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
> -#define FW_FEATURE_OPAL ASM_CONST(0x0000000010000000)
> -#define FW_FEATURE_SET_MODE ASM_CONST(0x0000000040000000)
> -#define FW_FEATURE_BEST_ENERGY ASM_CONST(0x0000000080000000)
> -#define FW_FEATURE_TYPE1_AFFINITY ASM_CONST(0x0000000100000000)
> -#define FW_FEATURE_PRRN ASM_CONST(0x0000000200000000)
> -#define FW_FEATURE_DRMEM_V2 ASM_CONST(0x0000000400000000)
> -#define FW_FEATURE_DRC_INFO ASM_CONST(0x0000000800000000)
> -#define FW_FEATURE_BLOCK_REMOVE ASM_CONST(0x0000001000000000)
> -#define FW_FEATURE_PAPR_SCM ASM_CONST(0x0000002000000000)
> +#define FW_FEATURE_PFT BIT(0)
> +#define FW_FEATURE_TCE BIT(1)
> +#define FW_FEATURE_SPRG0 BIT(2)
> +#define FW_FEATURE_DABR BIT(3)
> +#define FW_FEATURE_COPY BIT(4)
> +#define FW_FEATURE_ASR BIT(5)
> +#define FW_FEATURE_DEBUG BIT(6)
> +#define FW_FEATURE_TERM BIT(7)
> +#define FW_FEATURE_PERF BIT(8)
> +#define FW_FEATURE_DUMP BIT(9)
> +#define FW_FEATURE_INTERRUPT BIT(10)
> +#define FW_FEATURE_MIGRATE BIT(11)
> +#define FW_FEATURE_PERFMON BIT(12)
> +#define FW_FEATURE_CRQ BIT(13)
> +#define FW_FEATURE_VIO BIT(14)
> +#define FW_FEATURE_RDMA BIT(15)
> +#define FW_FEATURE_LLAN BIT(16)
> +#define FW_FEATURE_BULK_REMOVE BIT(17)
> +#define FW_FEATURE_XDABR BIT(18)
> +#define FW_FEATURE_MULTITCE BIT(19)
> +#define FW_FEATURE_SPLPAR BIT(20)
> +#define FW_FEATURE_LPAR BIT(22)
> +#define FW_FEATURE_PS3_LV1 BIT(23)
> +#define FW_FEATURE_HPT_RESIZE BIT(24)
> +#define FW_FEATURE_CMO BIT(25)
> +#define FW_FEATURE_VPHN BIT(26)
> +#define FW_FEATURE_XCMO BIT(27)
> +#define FW_FEATURE_OPAL BIT(28)
> +#define FW_FEATURE_SET_MODE BIT(30)
> +#define FW_FEATURE_BEST_ENERGY BIT(31)
> +#define FW_FEATURE_TYPE1_AFFINITY BIT(32)
> +#define FW_FEATURE_PRRN BIT(33)
> +#define FW_FEATURE_DRMEM_V2 BIT(34)
> +#define FW_FEATURE_DRC_INFO BIT(35)
> +#define FW_FEATURE_BLOCK_REMOVE BIT(36)
> +#define FW_FEATURE_PAPR_SCM BIT(37)
>
> #ifndef __ASSEMBLY__
>
> --
> 2.17.1
^ permalink raw reply
* [PATCH] powerpc: Enable CONFIG_IPV6 in ppc64_defconfig
From: sathnaga @ 2019-07-02 15:47 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Satheesh Rajendran
From: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>
Enable CONFIG_IPV6 in ppc64_defconfig to enable
certain network functionalities required for tests.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com>
---
arch/powerpc/configs/ppc64_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 91fdb619b484..93fd9792d030 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -89,7 +89,7 @@ CONFIG_SYN_COOKIES=y
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_ADVANCED is not set
CONFIG_BRIDGE=m
--
2.21.0
^ permalink raw reply related
* Re: ["RFC PATCH" 1/2] powerpc/mm: Fix node look up with numa=off boot
From: Nathan Lynch @ 2019-07-02 15:57 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: Vaibhav Jain, paulus, linuxppc-dev, npiggin
In-Reply-To: <0beef991-6e3a-9f88-3c83-f9ff97c5d454@linux.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
>> Just checking: do people still need numa=off? Seems like it's a
>> maintenance burden :-)
>>
>
> That is used in kdump kernel.
I see, thanks.
^ permalink raw reply
* Re: [RFC PATCH] Replaces long number representation by BIT() macro
From: Segher Boessenkool @ 2019-07-02 16:16 UTC (permalink / raw)
To: Michael Ellerman
Cc: Leonardo Bras, Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <87imskihvd.fsf@concordia.ellerman.id.au>
On Wed, Jul 03, 2019 at 01:19:34AM +1000, Michael Ellerman wrote:
> What we could do is switch to the `UL` macro from include/linux/const.h,
> rather than using our own ASM_CONST.
You need gas 2.28 or later for that though.
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=86b80085
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=e140100a
What is the minimum required (for powerpc) now?
Segher
^ permalink raw reply
* Re: [RFC PATCH] Replaces long number representation by BIT() macro
From: Segher Boessenkool @ 2019-07-02 16:48 UTC (permalink / raw)
To: Michael Ellerman
Cc: Leonardo Bras, Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <20190702161635.GO18316@gate.crashing.org>
On Tue, Jul 02, 2019 at 11:16:35AM -0500, Segher Boessenkool wrote:
> On Wed, Jul 03, 2019 at 01:19:34AM +1000, Michael Ellerman wrote:
> > What we could do is switch to the `UL` macro from include/linux/const.h,
> > rather than using our own ASM_CONST.
>
> You need gas 2.28 or later for that though.
Oh, but apparently I cannot read. That macro should work fine.
Segher
^ permalink raw reply
* Re: [PATCH net] net/ibmvnic: Report last valid speed and duplex values to ethtool
From: David Miller @ 2019-07-02 21:01 UTC (permalink / raw)
To: tlfalcon; +Cc: netdev, linuxppc-dev, bjking1, dnbanerg
In-Reply-To: <1561655353-17114-1-git-send-email-tlfalcon@linux.ibm.com>
From: Thomas Falcon <tlfalcon@linux.ibm.com>
Date: Thu, 27 Jun 2019 12:09:13 -0500
> This patch resolves an issue with sensitive bonding modes
> that require valid speed and duplex settings to function
> properly. Currently, the adapter will report that device
> speed and duplex is unknown if the communication link
> with firmware is unavailable. This decision can break LACP
> configurations if the timing is right.
>
> For example, if invalid speeds are reported, the slave
> device's link state is set to a transitional "fail" state
> and the LACP port is disabled. However, if valid speeds
> are reported later but the link state has not been altered,
> the LACP port will remain disabled. If the link state then
> transitions back to "up" from "fail," it results in a state
> such that the slave reports valid speed/duplex and is up,
> but the LACP port will remain disabled.
>
> Workaround this by reporting the last recorded speed
> and duplex settings unless the device has never been
> activated. In that case or when the hypervisor gives
> invalid values, continue to report unknown speed or
> duplex to ethtool.
>
> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
Like Andrew, I have my conerns about this.
If the firmware is unavailable, the link is effectively down. So
you should report link down and unknown link parameters.
Bonding and LACP should do the right thing when the firwmare is
reachable again after the migration and the link goes back up.
If bonding/LACP isn't doing that, then the bug is there.
^ permalink raw reply
* Re: [PATCH V2] mm/ioremap: Probe platform for p4d huge map support
From: Andrew Morton @ 2019-07-02 23:06 UTC (permalink / raw)
To: Anshuman Khandual
Cc: Stephen Rothwell, x86, Peter Zijlstra, Catalin Marinas,
Dave Hansen, Will Deacon, Michal Hocko, linux-mm, Ingo Molnar,
linux-arm-kernel, Andy Lutomirski, Thomas Gleixner, linuxppc-dev,
Kirill A . Shutemov
In-Reply-To: <1561699231-20991-1-git-send-email-anshuman.khandual@arm.com>
On Fri, 28 Jun 2019 10:50:31 +0530 Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> Finishing up what the commit c2febafc67734a ("mm: convert generic code to
> 5-level paging") started out while levelling up P4D huge mapping support
> at par with PUD and PMD. A new arch call back arch_ioremap_p4d_supported()
> is being added which just maintains status quo (P4D huge map not supported)
> on x86, arm64 and powerpc.
Does this have any runtime effects? If so, what are they and why? If
not, what's the actual point?
^ permalink raw reply
* Re: [PATCH] powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state.
From: Nicholas Piggin @ 2019-07-03 0:51 UTC (permalink / raw)
To: Madhavan Srinivasan, mpe; +Cc: ego, Athira Rajeev, linuxppc-dev
In-Reply-To: <20190702105836.26695-1-maddy@linux.vnet.ibm.com>
Madhavan Srinivasan's on July 2, 2019 8:58 pm:
> From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
>
> commit 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
> reimplemented book3S code to pltform/powernv/idle.c. But when doing so
> missed to add the per-thread LDBAR update in the core_woken path of
> the power9_idle_stop(). Patch fixes the same.
>
> Fixes: 10d91611f426 ("powerpc/64s: Reimplement book3s idle code in C")
> Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
> Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
> ---
> arch/powerpc/platforms/powernv/idle.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/platforms/powernv/idle.c b/arch/powerpc/platforms/powernv/idle.c
> index 2f4479b94ac3..fd14a6237954 100644
> --- a/arch/powerpc/platforms/powernv/idle.c
> +++ b/arch/powerpc/platforms/powernv/idle.c
> @@ -758,7 +758,6 @@ static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on)
> mtspr(SPRN_PTCR, sprs.ptcr);
> mtspr(SPRN_RPR, sprs.rpr);
> mtspr(SPRN_TSCR, sprs.tscr);
> - mtspr(SPRN_LDBAR, sprs.ldbar);
>
> if (pls >= pnv_first_tb_loss_level) {
> /* TB loss */
> @@ -790,6 +789,7 @@ static unsigned long power9_idle_stop(unsigned long psscr, bool mmu_on)
> mtspr(SPRN_MMCR0, sprs.mmcr0);
> mtspr(SPRN_MMCR1, sprs.mmcr1);
> mtspr(SPRN_MMCR2, sprs.mmcr2);
> + mtspr(SPRN_LDBAR, sprs.ldbar);
Oh that's another one I messed up, thanks for the fix. I must have
confused myself with the SPR table in the UM :(
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
^ permalink raw reply
* [PATCH 1/3] KVM: PPC: Book3S HV: Always save guest pmu for guest capable of nesting
From: Suraj Jitindar Singh @ 2019-07-03 1:20 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sjitindarsingh, kvm-ppc
The performance monitoring unit (PMU) registers are saved on guest exit
when the guest has set the pmcregs_in_use flag in its lppaca, if it
exists, or unconditionally if it doesn't. If a nested guest is being
run then the hypervisor doesn't, and in most cases can't, know if the
pmu registers are in use since it doesn't know the location of the lppaca
for the nested guest, although it may have one for its immediate guest.
This results in the values of these registers being lost across nested
guest entry and exit in the case where the nested guest was making use
of the performance monitoring facility while it's nested guest hypervisor
wasn't.
Further more the hypervisor could interrupt a guest hypervisor between
when it has loaded up the pmu registers and it calling H_ENTER_NESTED or
between returning from the nested guest to the guest hypervisor and the
guest hypervisor reading the pmu registers, in kvmhv_p9_guest_entry().
This means that it isn't sufficient to just save the pmu registers when
entering or exiting a nested guest, but that it is necessary to always
save the pmu registers whenever a guest is capable of running nested guests
to ensure the register values aren't lost in the context switch.
Ensure the pmu register values are preserved by always saving their
value into the vcpu struct when a guest is capable of running nested
guests.
This should have minimal performance impact however any impact can be
avoided by booting a guest with "-machine pseries,cap-nested-hv=false"
on the qemu commandline.
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index ec1804f822af..b682a429f3ef 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3654,6 +3654,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
vcpu->arch.vpa.dirty = 1;
save_pmu = lp->pmcregs_in_use;
}
+ /* Must save pmu if this guest is capable of running nested guests */
+ save_pmu |= nesting_enabled(vcpu->kvm);
kvmhv_save_guest_pmu(vcpu, save_pmu);
--
2.13.6
^ permalink raw reply related
* [PATCH 2/3] PPC: PMC: Set pmcregs_in_use in paca when running as LPAR
From: Suraj Jitindar Singh @ 2019-07-03 1:20 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sjitindarsingh, kvm-ppc
In-Reply-To: <20190703012022.15644-1-sjitindarsingh@gmail.com>
The ability to run nested guests under KVM means that a guest can also
act as a hypervisor for it's own nested guest. Currently
ppc_set_pmu_inuse() assumes that either FW_FEATURE_LPAR is set,
indicating a guest environment, and so sets the pmcregs_in_use flag in
the lppaca, or that it isn't set, indicating a hypervisor environment,
and so sets the pmcregs_in_use flag in the paca.
The pmcregs_in_use flag in the lppaca is used to communicate this
information to a hypervisor and so must be set in a guest environment.
The pmcregs_in_use flag in the paca is used by KVM code to determine
whether the host state of the performance monitoring unit (PMU) must be
saved and restored when running a guest.
Thus when a guest also acts as a hypervisor it must set this bit in both
places since it needs to ensure both that the real hypervisor saves it's
pmu registers when it runs (requires pmcregs_in_use flag in lppaca), and
that it saves it's own pmu registers when running a nested guest
(requires pmcregs_in_use flag in paca).
Modify ppc_set_pmu_inuse() so that the pmcregs_in_use bit is set in both
the lppaca and the paca when a guest (LPAR) is running with the
capability of running it's own guests (CONFIG_KVM_BOOK3S_HV_POSSIBLE).
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
arch/powerpc/include/asm/pmc.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/pmc.h b/arch/powerpc/include/asm/pmc.h
index dc9a1ca70edf..c6bbe9778d3c 100644
--- a/arch/powerpc/include/asm/pmc.h
+++ b/arch/powerpc/include/asm/pmc.h
@@ -27,11 +27,10 @@ static inline void ppc_set_pmu_inuse(int inuse)
#ifdef CONFIG_PPC_PSERIES
get_lppaca()->pmcregs_in_use = inuse;
#endif
- } else {
+ }
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
- get_paca()->pmcregs_in_use = inuse;
+ get_paca()->pmcregs_in_use = inuse;
#endif
- }
#endif
}
--
2.13.6
^ permalink raw reply related
* [PATCH 3/3] KVM: PPC: Book3S HV: Save and restore guest visible PSSCR bits on pseries
From: Suraj Jitindar Singh @ 2019-07-03 1:20 UTC (permalink / raw)
To: linuxppc-dev; +Cc: sjitindarsingh, kvm-ppc
In-Reply-To: <20190703012022.15644-1-sjitindarsingh@gmail.com>
The performance stop status and control register (PSSCR) is used to
control the power saving facilities of the processor. This register has
various fields, some of which can be modified only in hypervisor state,
and others which can be modified in both hypervisor and priviledged
non-hypervisor state. The bits which can be modified in priviledged
non-hypervisor state are referred to as guest visible.
Currently the L0 hypervisor saves and restores both it's own host value
as well as the guest value of the psscr when context switching between
the hypervisor and guest. However a nested hypervisor running it's own
nested guests (as indicated by kvmhv_on_pseries()) doesn't context
switch the psscr register. This means that if a nested (L2) guest
modified the psscr that the L1 guest hypervisor will run with this
value, and if the L1 guest hypervisor modified this value and then goes
to run the nested (L2) guest again that the L2 psscr value will be lost.
Fix this by having the (L1) nested hypervisor save and restore both its
host and the guest psscr value when entering and exiting a nested (L2)
guest. Note that only the guest visible parts of the psscr are context
switched since this is all the L1 nested hypervisor can access, this is
fine however as these are the only fields the L0 hypervisor provides
guest control of anyway and so all other fields are ignored.
This could also have been implemented by adding the psscr register to
the hv_regs passed to the L0 hypervisor as input to the H_ENTER_NESTED
hcall, however this would have meant updating the structure layout and
thus required modifications to both the L0 and L1 kernels. Whereas the
approach used doesn't require L0 kernel modifications while achieving
the same result.
Fixes: 95a6432ce903 "KVM: PPC: Book3S HV: Streamlined guest entry/exit path on P9 for radix guests"
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index b682a429f3ef..cde3f5a4b3e4 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -3569,9 +3569,18 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
mtspr(SPRN_DEC, vcpu->arch.dec_expires - mftb());
if (kvmhv_on_pseries()) {
+ /*
+ * We need to save and restore the guest visible part of the
+ * psscr (i.e. using SPRN_PSSCR_PR) since the hypervisor
+ * doesn't do this for us. Note only required if pseries since
+ * this is done in kvmhv_load_hv_regs_and_go() below otherwise.
+ */
+ unsigned long host_psscr;
/* call our hypervisor to load up HV regs and go */
struct hv_guest_state hvregs;
+ host_psscr = mfspr(SPRN_PSSCR_PR);
+ mtspr(SPRN_PSSCR_PR, vcpu->arch.psscr);
kvmhv_save_hv_regs(vcpu, &hvregs);
hvregs.lpcr = lpcr;
vcpu->arch.regs.msr = vcpu->arch.shregs.msr;
@@ -3590,6 +3599,8 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
vcpu->arch.shregs.msr = vcpu->arch.regs.msr;
vcpu->arch.shregs.dar = mfspr(SPRN_DAR);
vcpu->arch.shregs.dsisr = mfspr(SPRN_DSISR);
+ vcpu->arch.psscr = mfspr(SPRN_PSSCR_PR);
+ mtspr(SPRN_PSSCR_PR, host_psscr);
/* H_CEDE has to be handled now, not later */
if (trap == BOOK3S_INTERRUPT_SYSCALL && !vcpu->arch.nested &&
--
2.13.6
^ permalink raw reply related
* Re: [PATCH v2] powerpc/mm/nvdimm: Add an informative message if we fail to allocate altmap block
From: Oliver O'Halloran @ 2019-07-03 1:53 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: Paul Mackerras, linuxppc-dev, Nicholas Piggin
In-Reply-To: <20190701143338.16824-1-aneesh.kumar@linux.ibm.com>
On Tue, Jul 2, 2019 at 12:33 AM Aneesh Kumar K.V
<aneesh.kumar@linux.ibm.com> wrote:
>
> Allocation from altmap area can fail based on vmemmap page size used. Add kernel
> info message to indicate the failure. That allows the user to identify whether they
> are really using persistent memory reserved space for per-page metadata.
>
> The message looks like:
> [ 136.587212] altmap block allocation failed, falling back to system memory
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> arch/powerpc/mm/init_64.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
> index a4e17a979e45..f3b64f49082b 100644
> --- a/arch/powerpc/mm/init_64.c
> +++ b/arch/powerpc/mm/init_64.c
> @@ -194,8 +194,12 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node,
> * fail due to alignment issues when using 16MB hugepages, so
> * fall back to system memory if the altmap allocation fail.
> */
> - if (altmap)
> + if (altmap) {
> p = altmap_alloc_block_buf(page_size, altmap);
> + if (!p)
> + pr_debug("altmap block allocation failed, " \
> + "falling back to system memory");
> + }
> if (!p)
> p = vmemmap_alloc_block_buf(page_size, node);
> if (!p)
> --
> 2.21.0
>
I'll let mpe decide if he cares about the split line thing :)
Reviewed-by: Oliver O'Halloran <oohall@gmail.com>
^ permalink raw reply
* [PATCH AUTOSEL 5.1 09/39] selftests/powerpc: Add test of fork with mapping above 512TB
From: Sasha Levin @ 2019-07-03 2:14 UTC (permalink / raw)
To: linux-kernel, stable; +Cc: Sasha Levin, linuxppc-dev, linux-kselftest
In-Reply-To: <20190703021514.17727-1-sashal@kernel.org>
From: Michael Ellerman <mpe@ellerman.id.au>
[ Upstream commit 16391bfc862342f285195013b73c1394fab28b97 ]
This tests that when a process with a mapping above 512TB forks we
correctly separate the parent and child address spaces. This exercises
the bug in the context id handling fixed in the previous commit.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
tools/testing/selftests/powerpc/mm/.gitignore | 3 +-
tools/testing/selftests/powerpc/mm/Makefile | 4 +-
.../powerpc/mm/large_vm_fork_separation.c | 87 +++++++++++++++++++
3 files changed, 92 insertions(+), 2 deletions(-)
create mode 100644 tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
diff --git a/tools/testing/selftests/powerpc/mm/.gitignore b/tools/testing/selftests/powerpc/mm/.gitignore
index ba919308fe30..d503b8764a8e 100644
--- a/tools/testing/selftests/powerpc/mm/.gitignore
+++ b/tools/testing/selftests/powerpc/mm/.gitignore
@@ -3,4 +3,5 @@ subpage_prot
tempfile
prot_sao
segv_errors
-wild_bctr
\ No newline at end of file
+wild_bctr
+large_vm_fork_separation
\ No newline at end of file
diff --git a/tools/testing/selftests/powerpc/mm/Makefile b/tools/testing/selftests/powerpc/mm/Makefile
index 43d68420e363..f1fbc15800c4 100644
--- a/tools/testing/selftests/powerpc/mm/Makefile
+++ b/tools/testing/selftests/powerpc/mm/Makefile
@@ -2,7 +2,8 @@
noarg:
$(MAKE) -C ../
-TEST_GEN_PROGS := hugetlb_vs_thp_test subpage_prot prot_sao segv_errors wild_bctr
+TEST_GEN_PROGS := hugetlb_vs_thp_test subpage_prot prot_sao segv_errors wild_bctr \
+ large_vm_fork_separation
TEST_GEN_FILES := tempfile
top_srcdir = ../../../../..
@@ -13,6 +14,7 @@ $(TEST_GEN_PROGS): ../harness.c
$(OUTPUT)/prot_sao: ../utils.c
$(OUTPUT)/wild_bctr: CFLAGS += -m64
+$(OUTPUT)/large_vm_fork_separation: CFLAGS += -m64
$(OUTPUT)/tempfile:
dd if=/dev/zero of=$@ bs=64k count=1
diff --git a/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c b/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
new file mode 100644
index 000000000000..2363a7f3ab0d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/mm/large_vm_fork_separation.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2019, Michael Ellerman, IBM Corp.
+//
+// Test that allocating memory beyond the memory limit and then forking is
+// handled correctly, ie. the child is able to access the mappings beyond the
+// memory limit and the child's writes are not visible to the parent.
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <unistd.h>
+
+#include "utils.h"
+
+
+#ifndef MAP_FIXED_NOREPLACE
+#define MAP_FIXED_NOREPLACE MAP_FIXED // "Should be safe" above 512TB
+#endif
+
+
+static int test(void)
+{
+ int p2c[2], c2p[2], rc, status, c, *p;
+ unsigned long page_size;
+ pid_t pid;
+
+ page_size = sysconf(_SC_PAGESIZE);
+ SKIP_IF(page_size != 65536);
+
+ // Create a mapping at 512TB to allocate an extended_id
+ p = mmap((void *)(512ul << 40), page_size, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED_NOREPLACE, -1, 0);
+ if (p == MAP_FAILED) {
+ perror("mmap");
+ printf("Error: couldn't mmap(), confirm kernel has 4TB support?\n");
+ return 1;
+ }
+
+ printf("parent writing %p = 1\n", p);
+ *p = 1;
+
+ FAIL_IF(pipe(p2c) == -1 || pipe(c2p) == -1);
+
+ pid = fork();
+ if (pid == 0) {
+ FAIL_IF(read(p2c[0], &c, 1) != 1);
+
+ pid = getpid();
+ printf("child writing %p = %d\n", p, pid);
+ *p = pid;
+
+ FAIL_IF(write(c2p[1], &c, 1) != 1);
+ FAIL_IF(read(p2c[0], &c, 1) != 1);
+ exit(0);
+ }
+
+ c = 0;
+ FAIL_IF(write(p2c[1], &c, 1) != 1);
+ FAIL_IF(read(c2p[0], &c, 1) != 1);
+
+ // Prevent compiler optimisation
+ barrier();
+
+ rc = 0;
+ printf("parent reading %p = %d\n", p, *p);
+ if (*p != 1) {
+ printf("Error: BUG! parent saw child's write! *p = %d\n", *p);
+ rc = 1;
+ }
+
+ FAIL_IF(write(p2c[1], &c, 1) != 1);
+ FAIL_IF(waitpid(pid, &status, 0) == -1);
+ FAIL_IF(!WIFEXITED(status) || WEXITSTATUS(status));
+
+ if (rc == 0)
+ printf("success: test completed OK\n");
+
+ return rc;
+}
+
+int main(void)
+{
+ return test_harness(test, "large_vm_fork_separation");
+}
--
2.20.1
^ permalink raw reply related
* Re: [RFC PATCH v2 09/12] powerpc/ptrace: split out ADV_DEBUG_REGS related functions.
From: Ravi Bangoria @ 2019-07-03 2:52 UTC (permalink / raw)
To: Christophe Leroy; +Cc: mikey, linux-kernel, Paul Mackerras, linuxppc-dev
In-Reply-To: <79b765523f7d45f93cc3b636fec57055f52801b3.1561735588.git.christophe.leroy@c-s.fr>
On 6/28/19 9:17 PM, Christophe Leroy wrote:
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-adv.c b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> new file mode 100644
> index 000000000000..86e71fa6c5c8
> --- /dev/null
> +++ b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> @@ -0,0 +1,487 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +#include <linux/mm.h>
> +#include <linux/smp.h>
> +#include <linux/errno.h>
> +#include <linux/ptrace.h>
> +#include <linux/regset.h>
> +#include <linux/tracehook.h>
> +#include <linux/elf.h>
> +#include <linux/user.h>
> +#include <linux/security.h>
> +#include <linux/signal.h>
> +#include <linux/seccomp.h>
> +#include <linux/audit.h>
> +#include <trace/syscall.h>
> +#include <linux/hw_breakpoint.h>
> +#include <linux/perf_event.h>
> +#include <linux/context_tracking.h>
> +#include <linux/nospec.h>
> +
> +#include <linux/uaccess.h>
> +#include <linux/pkeys.h>
> +#include <asm/page.h>
> +#include <asm/pgtable.h>
> +#include <asm/switch_to.h>
> +#include <asm/tm.h>
> +#include <asm/asm-prototypes.h>
> +#include <asm/debug.h>
> +#include <asm/hw_breakpoint.h>
> +
> +#include <kernel/ptrace/ptrace-decl.h>
> +
> +void user_enable_single_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + task->thread.debug.dbcr0 &= ~DBCR0_BT;
> + task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
> + regs->msr |= MSR_DE;
> + }
> + set_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +void user_enable_block_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + task->thread.debug.dbcr0 &= ~DBCR0_IC;
> + task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
> + regs->msr |= MSR_DE;
> + }
> + set_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +void user_disable_single_step(struct task_struct *task)
> +{
> + struct pt_regs *regs = task->thread.regs;
> +
> + if (regs != NULL) {
> + /*
> + * The logic to disable single stepping should be as
> + * simple as turning off the Instruction Complete flag.
> + * And, after doing so, if all debug flags are off, turn
> + * off DBCR0(IDM) and MSR(DE) .... Torez
> + */
> + task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
> + /*
> + * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
> + */
> + if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
> + task->thread.debug.dbcr1)) {
> + /*
> + * All debug events were off.....
> + */
> + task->thread.debug.dbcr0 &= ~DBCR0_IDM;
> + regs->msr &= ~MSR_DE;
> + }
> + }
> + clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> +}
> +
> +int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data)
> +{
> + /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
> + * For embedded processors we support one DAC and no IAC's at the
> + * moment.
> + */
I guess mentioning DABR and IABR doesn't make sense in ptrace-adv.c?
> + if (addr > 0)
> + return -EINVAL;
> +
> + /* The bottom 3 bits in dabr are flags */
Same here.
> + if ((data & ~0x7UL) >= TASK_SIZE)
> + return -EIO;
> +
> + /* As described above, it was assumed 3 bits were passed with the data
> + * address, but we will assume only the mode bits will be passed
> + * as to not cause alignment restrictions for DAC-based processors.
> + */
> +
> + /* DAC's hold the whole address without any mode flags */
> + task->thread.debug.dac1 = data & ~0x3UL;
> +
> + if (task->thread.debug.dac1 == 0) {
> + dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
> + if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
> + task->thread.debug.dbcr1)) {
> + task->thread.regs->msr &= ~MSR_DE;
> + task->thread.debug.dbcr0 &= ~DBCR0_IDM;
> + }
> + return 0;
> + }
> +
> + /* Read or Write bits must be set */
> +
> + if (!(data & 0x3UL))
> + return -EINVAL;
> +
> + /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
> + register */
> + task->thread.debug.dbcr0 |= DBCR0_IDM;
> +
> + /* Check for write and read flags and set DBCR0
> + accordingly */
> + dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
> + if (data & 0x1UL)
> + dbcr_dac(task) |= DBCR_DAC1R;
> + if (data & 0x2UL)
> + dbcr_dac(task) |= DBCR_DAC1W;
> + task->thread.regs->msr |= MSR_DE;
> + return 0;
> +}
> +
> +static long set_instruction_bp(struct task_struct *child,
> + struct ppc_hw_breakpoint *bp_info)
> +{
> + int slot;
> + int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
> + int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
> + int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
> + int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
> +
> + if (dbcr_iac_range(child) & DBCR_IAC12MODE)
> + slot2_in_use = 1;
> + if (dbcr_iac_range(child) & DBCR_IAC34MODE)
> + slot4_in_use = 1;
> +
> + if (bp_info->addr >= TASK_SIZE)
> + return -EIO;
> +
> + if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
> +
> + /* Make sure range is valid. */
> + if (bp_info->addr2 >= TASK_SIZE)
> + return -EIO;
> +
> + /* We need a pair of IAC regsisters */
> + if ((!slot1_in_use) && (!slot2_in_use)) {
> + slot = 1;
> + child->thread.debug.iac1 = bp_info->addr;
> + child->thread.debug.iac2 = bp_info->addr2;
> + child->thread.debug.dbcr0 |= DBCR0_IAC1;
> + if (bp_info->addr_mode ==
> + PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
> + dbcr_iac_range(child) |= DBCR_IAC12X;
> + else
> + dbcr_iac_range(child) |= DBCR_IAC12I;
> +#if CONFIG_PPC_ADV_DEBUG_IACS > 2
> + } else if ((!slot3_in_use) && (!slot4_in_use)) {
> + slot = 3;
> + child->thread.debug.iac3 = bp_info->addr;
> + child->thread.debug.iac4 = bp_info->addr2;
> + child->thread.debug.dbcr0 |= DBCR0_IAC3;
> + if (bp_info->addr_mode ==
> + PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
> + dbcr_iac_range(child) |= DBCR_IAC34X;
> + else
> + dbcr_iac_range(child) |= DBCR_IAC34I;
> +#endif
> + } else
> + return -ENOSPC;
> + } else {
> + /* We only need one. If possible leave a pair free in
> + * case a range is needed later
> + */
> + if (!slot1_in_use) {
> + /*
> + * Don't use iac1 if iac1-iac2 are free and either
> + * iac3 or iac4 (but not both) are free
> + */
> + if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
> + slot = 1;
> + child->thread.debug.iac1 = bp_info->addr;
> + child->thread.debug.dbcr0 |= DBCR0_IAC1;
> + goto out;
> + }
> + }
> + if (!slot2_in_use) {
> + slot = 2;
> + child->thread.debug.iac2 = bp_info->addr;
> + child->thread.debug.dbcr0 |= DBCR0_IAC2;
> +#if CONFIG_PPC_ADV_DEBUG_IACS > 2
> + } else if (!slot3_in_use) {
> + slot = 3;
> + child->thread.debug.iac3 = bp_info->addr;
> + child->thread.debug.dbcr0 |= DBCR0_IAC3;
> + } else if (!slot4_in_use) {
> + slot = 4;
> + child->thread.debug.iac4 = bp_info->addr;
> + child->thread.debug.dbcr0 |= DBCR0_IAC4;
> +#endif
> + } else
> + return -ENOSPC;
> + }
> +out:
> + child->thread.debug.dbcr0 |= DBCR0_IDM;
> + child->thread.regs->msr |= MSR_DE;
> +
> + return slot;
> +}
> +
> +static int del_instruction_bp(struct task_struct *child, int slot)
> +{
> + switch (slot) {
> + case 1:
> + if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
> + return -ENOENT;
> +
> + if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
> + /* address range - clear slots 1 & 2 */
> + child->thread.debug.iac2 = 0;
> + dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
> + }
> + child->thread.debug.iac1 = 0;
> + child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
> + break;
> + case 2:
> + if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
> + return -ENOENT;
> +
> + if (dbcr_iac_range(child) & DBCR_IAC12MODE)
> + /* used in a range */
> + return -EINVAL;
> + child->thread.debug.iac2 = 0;
> + child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
> + break;
> +#if CONFIG_PPC_ADV_DEBUG_IACS > 2
> + case 3:
> + if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
> + return -ENOENT;
> +
> + if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
> + /* address range - clear slots 3 & 4 */
> + child->thread.debug.iac4 = 0;
> + dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
> + }
> + child->thread.debug.iac3 = 0;
> + child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
> + break;
> + case 4:
> + if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
> + return -ENOENT;
> +
> + if (dbcr_iac_range(child) & DBCR_IAC34MODE)
> + /* Used in a range */
> + return -EINVAL;
> + child->thread.debug.iac4 = 0;
> + child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
> + break;
> +#endif
> + default:
> + return -EINVAL;
> + }
> + return 0;
> +}
> +
> +static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
> +{
> + int byte_enable =
> + (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
> + & 0xf;
> + int condition_mode =
> + bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
> + int slot;
> +
> + if (byte_enable && (condition_mode == 0))
> + return -EINVAL;
> +
> + if (bp_info->addr >= TASK_SIZE)
> + return -EIO;
> +
> + if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
> + slot = 1;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
> + dbcr_dac(child) |= DBCR_DAC1R;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
> + dbcr_dac(child) |= DBCR_DAC1W;
> + child->thread.debug.dac1 = (unsigned long)bp_info->addr;
> +#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
> + if (byte_enable) {
> + child->thread.debug.dvc1 =
> + (unsigned long)bp_info->condition_value;
> + child->thread.debug.dbcr2 |=
> + ((byte_enable << DBCR2_DVC1BE_SHIFT) |
> + (condition_mode << DBCR2_DVC1M_SHIFT));
> + }
> +#endif
> +#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
> + } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
> + /* Both dac1 and dac2 are part of a range */
> + return -ENOSPC;
> +#endif
> + } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
> + slot = 2;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
> + dbcr_dac(child) |= DBCR_DAC2R;
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
> + dbcr_dac(child) |= DBCR_DAC2W;
> + child->thread.debug.dac2 = (unsigned long)bp_info->addr;
> +#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
> + if (byte_enable) {
> + child->thread.debug.dvc2 =
> + (unsigned long)bp_info->condition_value;
> + child->thread.debug.dbcr2 |=
> + ((byte_enable << DBCR2_DVC2BE_SHIFT) |
> + (condition_mode << DBCR2_DVC2M_SHIFT));
> + }
> +#endif
> + } else
> + return -ENOSPC;
> + child->thread.debug.dbcr0 |= DBCR0_IDM;
> + child->thread.regs->msr |= MSR_DE;
> +
> + return slot + 4;
> +}
> +
> +static int del_dac(struct task_struct *child, int slot)
> +{
> + if (slot == 1) {
> + if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
> + return -ENOENT;
> +
> + child->thread.debug.dac1 = 0;
> + dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
> +#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
> + if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
> + child->thread.debug.dac2 = 0;
> + child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
> + }
> + child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
> +#endif
> +#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
> + child->thread.debug.dvc1 = 0;
> +#endif
> + } else if (slot == 2) {
> + if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
> + return -ENOENT;
> +
> +#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
> + if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
> + /* Part of a range */
> + return -EINVAL;
> + child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
> +#endif
> +#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
> + child->thread.debug.dvc2 = 0;
> +#endif
> + child->thread.debug.dac2 = 0;
> + dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
> + } else
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
> +static int set_dac_range(struct task_struct *child,
> + struct ppc_hw_breakpoint *bp_info)
> +{
> + int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
> +
> + /* We don't allow range watchpoints to be used with DVC */
> + if (bp_info->condition_mode)
> + return -EINVAL;
> +
> + /*
> + * Best effort to verify the address range. The user/supervisor bits
> + * prevent trapping in kernel space, but let's fail on an obvious bad
> + * range. The simple test on the mask is not fool-proof, and any
> + * exclusive range will spill over into kernel space.
> + */
> + if (bp_info->addr >= TASK_SIZE)
> + return -EIO;
> + if (mode == PPC_BREAKPOINT_MODE_MASK) {
> + /*
> + * dac2 is a bitmask. Don't allow a mask that makes a
> + * kernel space address from a valid dac1 value
> + */
> + if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
> + return -EIO;
> + } else {
> + /*
> + * For range breakpoints, addr2 must also be a valid address
> + */
> + if (bp_info->addr2 >= TASK_SIZE)
> + return -EIO;
> + }
> +
> + if (child->thread.debug.dbcr0 &
> + (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
> + return -ENOSPC;
> +
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
> + child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
> + child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
> + child->thread.debug.dac1 = bp_info->addr;
> + child->thread.debug.dac2 = bp_info->addr2;
> + if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
> + child->thread.debug.dbcr2 |= DBCR2_DAC12M;
> + else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
> + child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
> + else /* PPC_BREAKPOINT_MODE_MASK */
> + child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
> + child->thread.regs->msr |= MSR_DE;
> +
> + return 5;
> +}
> +#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
> +
> +long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
> +{
> + if (bp_info->version != 1)
> + return -ENOTSUPP;
> + /*
> + * Check for invalid flags and combinations
> + */
> + if ((bp_info->trigger_type == 0) ||
> + (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
> + PPC_BREAKPOINT_TRIGGER_RW)) ||
> + (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
> + (bp_info->condition_mode &
> + ~(PPC_BREAKPOINT_CONDITION_MODE |
> + PPC_BREAKPOINT_CONDITION_BE_ALL)))
> + return -EINVAL;
> +#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
> + if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
> + return -EINVAL;
> +#endif
> +
> + if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
> + if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
> + (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
> + return -EINVAL;
> + return set_instruction_bp(child, bp_info);
> + }
> + if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
> + return set_dac(child, bp_info);
> +
> +#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
> + return set_dac_range(child, bp_info);
> +#else
> + return -EINVAL;
> +#endif
> +}
> +
> +long ppc_del_hwdebug(struct task_struct *child, long data)
> +{
> + int rc;
> +
> + if (data <= 4)
> + rc = del_instruction_bp(child, (int)data);
> + else
> + rc = del_dac(child, (int)data - 4);
> +
> + if (!rc) {
> + if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
> + child->thread.debug.dbcr1)) {
> + child->thread.debug.dbcr0 &= ~DBCR0_IDM;
> + child->thread.regs->msr &= ~MSR_DE;
> + }
> + }
> + return rc;
> +}
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> index e12f6615fc1d..bdba09a87aea 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
> +++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> @@ -174,3 +174,8 @@ int tm_cgpr32_set(struct task_struct *target, const struct user_regset *regset,
> /* ptrace-view */
>
> extern const struct user_regset_view user_ppc_native_view;
> +
> +/* ptrace-(no)adv */
> +int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data);
> +long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info);
> +long ppc_del_hwdebug(struct task_struct *child, long data);
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> new file mode 100644
> index 000000000000..7db330c94538
> --- /dev/null
> +++ b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
ptrace-noadv.c looks good to me.
^ permalink raw reply
* Re: [RFC PATCH v2 10/12] powerpc/ptrace: create ptrace_get_debugreg()
From: Ravi Bangoria @ 2019-07-03 3:03 UTC (permalink / raw)
To: Christophe Leroy
Cc: Ravi Bangoria, mikey, linux-kernel, Paul Mackerras, linuxppc-dev
In-Reply-To: <483ffd1c62d270d7079b41e1747f34d254390c24.1561735588.git.christophe.leroy@c-s.fr>
On 6/28/19 9:17 PM, Christophe Leroy wrote:
> Create ptrace_get_debugreg() to handle PTRACE_GET_DEBUGREG and
> reduce ifdef mess
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> arch/powerpc/kernel/ptrace/ptrace-adv.c | 9 +++++++++
> arch/powerpc/kernel/ptrace/ptrace-decl.h | 2 ++
> arch/powerpc/kernel/ptrace/ptrace-noadv.c | 13 +++++++++++++
> arch/powerpc/kernel/ptrace/ptrace.c | 18 ++----------------
> 4 files changed, 26 insertions(+), 16 deletions(-)
>
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-adv.c b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> index 86e71fa6c5c8..dcc765940344 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-adv.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace-adv.c
> @@ -83,6 +83,15 @@ void user_disable_single_step(struct task_struct *task)
> clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> }
>
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp)
> +{
> + /* We only support one DABR and no IABRS at the moment */
No DABR / IABR in ptrace-adv.c
> + if (addr > 0)
> + return -EINVAL;
> + return put_user(child->thread.debug.dac1, datalp);
> +}
> +
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data)
> {
> /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-decl.h b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> index bdba09a87aea..4b4b6a1d508a 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-decl.h
> +++ b/arch/powerpc/kernel/ptrace/ptrace-decl.h
> @@ -176,6 +176,8 @@ int tm_cgpr32_set(struct task_struct *target, const struct user_regset *regset,
> extern const struct user_regset_view user_ppc_native_view;
>
> /* ptrace-(no)adv */
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp);
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data);
> long ppc_set_hwdebug(struct task_struct *child, struct ppc_hw_breakpoint *bp_info);
> long ppc_del_hwdebug(struct task_struct *child, long data);
> diff --git a/arch/powerpc/kernel/ptrace/ptrace-noadv.c b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> index 7db330c94538..985cca136f85 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace-noadv.c
> @@ -64,6 +64,19 @@ void user_disable_single_step(struct task_struct *task)
> clear_tsk_thread_flag(task, TIF_SINGLESTEP);
> }
>
> +int ptrace_get_debugreg(struct task_struct *child, unsigned long addr,
> + unsigned long __user *datalp)
> +{
> + unsigned long dabr_fake;
> +
> + /* We only support one DABR and no IABRS at the moment */
> + if (addr > 0)
> + return -EINVAL;
> + dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
> + (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
> + return put_user(dabr_fake, datalp);
> +}
> +
> int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, unsigned long data)
> {
> #ifdef CONFIG_HAVE_HW_BREAKPOINT
> diff --git a/arch/powerpc/kernel/ptrace/ptrace.c b/arch/powerpc/kernel/ptrace/ptrace.c
> index 377e0e541d5f..e789afae6f56 100644
> --- a/arch/powerpc/kernel/ptrace/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace/ptrace.c
> @@ -211,23 +211,9 @@ long arch_ptrace(struct task_struct *child, long request,
> break;
> }
>
> - case PTRACE_GET_DEBUGREG: {
> -#ifndef CONFIG_PPC_ADV_DEBUG_REGS
> - unsigned long dabr_fake;
> -#endif
> - ret = -EINVAL;
> - /* We only support one DABR and no IABRS at the moment */
> - if (addr > 0)
> - break;
> -#ifdef CONFIG_PPC_ADV_DEBUG_REGS
> - ret = put_user(child->thread.debug.dac1, datalp);
> -#else
> - dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
> - (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
> - ret = put_user(dabr_fake, datalp);
> -#endif
> + case PTRACE_GET_DEBUGREG:
> + ret = ptrace_get_debugreg(child, addr, datalp);
> break;
> - }
>
> case PTRACE_SET_DEBUGREG:
> ret = ptrace_set_debugreg(child, addr, data);
>
Otherwise,
Reviewed-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
^ permalink raw reply
* Re: [RFC PATCH v2 12/12] powerpc/ptrace: move ptrace_triggered() into hw_breakpoint.c
From: Ravi Bangoria @ 2019-07-03 3:05 UTC (permalink / raw)
To: Christophe Leroy
Cc: Ravi Bangoria, mikey, linux-kernel, Paul Mackerras, linuxppc-dev
In-Reply-To: <91218c7e0ea432e188c6d164097d383360f3c2e0.1561735588.git.christophe.leroy@c-s.fr>
On 6/28/19 9:18 PM, Christophe Leroy wrote:
> ptrace_triggered() is declared in asm/hw_breakpoint.h and
> only needed when CONFIG_HW_BREAKPOINT is set, so move it
> into hw_breakpoint.c
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
^ permalink raw reply
* Re: [RFC PATCH v2 11/12] powerpc/ptrace: create ppc_gethwdinfo()
From: Ravi Bangoria @ 2019-07-03 3:18 UTC (permalink / raw)
To: Christophe Leroy
Cc: Ravi Bangoria, mikey, linux-kernel, Paul Mackerras, linuxppc-dev
In-Reply-To: <b25d2a4c5d6ea848b9b4e434bc4c67833c8e9268.1561735588.git.christophe.leroy@c-s.fr>
On 6/28/19 9:18 PM, Christophe Leroy wrote:
> Create ippc_gethwdinfo() to handle PPC_PTRACE_GETHWDBGINFO and
> reduce ifdef mess
>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
Reviewed-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com>
^ permalink raw reply
* Re: [PATCH v3 01/16] powerpc/fadump: move internal fadump code to a new file
From: Oliver O'Halloran @ 2019-07-03 3:30 UTC (permalink / raw)
To: Hari Bathini, linuxppc-dev
Cc: Ananth N Mavinakayanahalli, Mahesh J Salgaonkar, Vasant Hegde,
Nicholas Piggin, Stewart Smith, Daniel Axtens
In-Reply-To: <156149554689.9094.13274886908174068943.stgit@hbathini.in.ibm.com>
On Wed, 2019-06-26 at 02:15 +0530, Hari Bathini wrote:
> Refactoring fadump code means internal fadump code is referenced from
> different places. For ease, move internal code to a new file.
Can you elaborate a bit? I don't really get what the difference between
fadump and fadump-internal code is supposed to be. Why can't all this
just live in fadump.c?
^ permalink raw reply
* Re: [PATCH v3 03/16] pseries/fadump: move out platform specific support from generic code
From: Oliver O'Halloran @ 2019-07-03 4:04 UTC (permalink / raw)
To: Hari Bathini, linuxppc-dev
Cc: Ananth N Mavinakayanahalli, Mahesh J Salgaonkar, Vasant Hegde,
Nicholas Piggin, Stewart Smith, Daniel Axtens
In-Reply-To: <156149556436.9094.15834897273683011518.stgit@hbathini.in.ibm.com>
On Wed, 2019-06-26 at 02:16 +0530, Hari Bathini wrote:
> Introduce callbacks for platform specific operations like register,
> unregister, invalidate & such, and move pseries specific code into
> platform code.
Please don't move around large blocks of code *and* change the code in
a single patch. It makes reviewing the changes extremely tedious since
the changes are mixed in with hundreds of lines of nothing.
> Signed-off-by: Hari Bathini <hbathini@linux.ibm.com>
> ---
> arch/powerpc/include/asm/fadump.h | 75 ----
> arch/powerpc/kernel/fadump-common.h | 38 ++
> arch/powerpc/kernel/fadump.c | 500 ++-----------------------
> arch/powerpc/platforms/pseries/Makefile | 1
> arch/powerpc/platforms/pseries/rtas-fadump.c | 529 ++++++++++++++++++++++++++
> arch/powerpc/platforms/pseries/rtas-fadump.h | 96 +++++
> 6 files changed, 700 insertions(+), 539 deletions(-)
> create mode 100644 arch/powerpc/platforms/pseries/rtas-fadump.c
> create mode 100644 arch/powerpc/platforms/pseries/rtas-fadump.h
>
> +static struct fadump_ops pseries_fadump_ops = {
> + .init_fadump_mem_struct = pseries_init_fadump_mem_struct,
> + .register_fadump = pseries_register_fadump,
I realise you are just translating the existing interface, but why is
init_fadump_mem_struct() done as a seperate step and not as a part of
the registration function? The struct doesn't seem to be necessary
until the actual registration happens.
> + .unregister_fadump = pseries_unregister_fadump,
> + .invalidate_fadump = pseries_invalidate_fadump,
> + .process_fadump = pseries_process_fadump,
> + .fadump_region_show = pseries_fadump_region_show,
> + .crash_fadump = pseries_crash_fadump,
Rename this to fadump_trigger or something, it's not clear what it
does.
^ permalink raw reply
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