* [PATCH v2 12/16] powerpc/64s/exception: machine check move tramp code
From: Nicholas Piggin @ 2019-07-10 15:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh Salgaonkar, Nicholas Piggin, Aravinda Prasad
In-Reply-To: <20190710151950.31906-1-npiggin@gmail.com>
Following convention, move the tramp code (unrelocated) above the
common handlers (relocated).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3cc5ee6e4b56..9bb8c89e9e77 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -945,6 +945,17 @@ EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
EXC_REAL_END(machine_check, 0x200, 0x100)
EXC_VIRT_NONE(0x4200, 0x100)
+#ifdef CONFIG_PPC_PSERIES
+TRAMP_REAL_BEGIN(machine_check_fwnmi)
+ /* See comment at machine_check exception, don't turn on RI */
+ EXCEPTION_PROLOG_0 PACA_EXMC
+ EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 1, 1, 0
+ mfctr r10 /* save ctr */
+ BRANCH_TO_C000(r11, machine_check_early_common)
+#endif
+
+TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
+
EXC_COMMON_BEGIN(machine_check_early_common)
mtctr r10 /* Restore ctr */
mfspr r11,SPRN_SRR0
@@ -1018,17 +1029,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
b 1b
b . /* prevent speculative execution */
-#ifdef CONFIG_PPC_PSERIES
-TRAMP_REAL_BEGIN(machine_check_fwnmi)
- /* See comment at machine_check exception, don't turn on RI */
- EXCEPTION_PROLOG_0 PACA_EXMC
- EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 1, 1, 0
- mfctr r10 /* save ctr */
- BRANCH_TO_C000(r11, machine_check_early_common)
-#endif
-
-TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
-
EXC_COMMON_BEGIN(machine_check_common)
/*
* Machine check is different because we use a different
--
2.20.1
^ permalink raw reply related
* [PATCH v2 13/16] powerpc/64s/exception: simplify machine check early path
From: Nicholas Piggin @ 2019-07-10 15:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh Salgaonkar, Nicholas Piggin, Aravinda Prasad
In-Reply-To: <20190710151950.31906-1-npiggin@gmail.com>
machine_check_handle_early_common can reach machine_check_handle_early
directly now that it runs at the relocated address, so just branch
directly.
The rfi sequence is required to enable MSR[ME] but that step is moved
into a helper function, making the code easier to follow.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 31 ++++++++++++++++++++--------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 9bb8c89e9e77..2a17275296d5 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1006,16 +1006,13 @@ EXC_COMMON_BEGIN(machine_check_early_common)
std r3,_DAR(r1)
std r4,_DSISR(r1)
- mfmsr r11 /* get MSR value */
BEGIN_FTR_SECTION
- ori r11,r11,MSR_ME /* turn on ME bit */
+ bl enable_machine_check
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
- ori r11,r11,MSR_RI /* turn on RI bit */
- LOAD_HANDLER(r12, machine_check_handle_early)
-1: mtspr SPRN_SRR0,r12
- mtspr SPRN_SRR1,r11
- RFI_TO_KERNEL
- b . /* prevent speculative execution */
+ li r10,MSR_RI
+ mtmsrd r10,1
+ b machine_check_handle_early
+
2:
/* Stack overflow. Stay on emergency stack and panic.
* Keep the ME bit off while panic-ing, so that if we hit
@@ -1026,7 +1023,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
LOAD_HANDLER(r12, unrecover_mce)
li r10,MSR_ME
andc r11,r11,r10 /* Turn off MSR_ME */
- b 1b
+ mtspr SPRN_SRR0,r12
+ mtspr SPRN_SRR1,r11
+ RFI_TO_KERNEL
b . /* prevent speculative execution */
EXC_COMMON_BEGIN(machine_check_common)
@@ -2270,6 +2269,20 @@ CLOSE_FIXED_SECTION(virt_trampolines);
USE_TEXT_SECTION()
+/* MSR[RI] should be clear because this uses SRR[01] */
+enable_machine_check:
+ mflr r0
+ bcl 20,31,$+4
+0: mflr r3
+ addi r3,r3,(1f - 0b)
+ mtspr SPRN_SRR0,r3
+ mfmsr r3
+ ori r3,r3,MSR_ME
+ mtspr SPRN_SRR1,r3
+ RFI_TO_KERNEL
+1: mtlr r0
+ blr
+
/*
* Hash table stuff
*/
--
2.20.1
^ permalink raw reply related
* [PATCH v2 14/16] powerpc/64s/exception: machine check move unrecoverable handling out of line
From: Nicholas Piggin @ 2019-07-10 15:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh Salgaonkar, Nicholas Piggin, Aravinda Prasad
In-Reply-To: <20190710151950.31906-1-npiggin@gmail.com>
Similarly to the previous change, all callers of the unrecoverable
handler run relocated so can reach it with a direct branch. This makes
it easy to move out of line, which makes the "normal" path less
cluttered and easier to follow.
MSR[ME] manipulation still requires the rfi, so that is moved out of
line to its own function.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 87 ++++++++++++++--------------
1 file changed, 44 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 2a17275296d5..95dd7ff3ef04 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -992,9 +992,9 @@ EXC_COMMON_BEGIN(machine_check_early_common)
bne 1f
/* First machine check entry */
ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
-1: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
- /* Limit nested MCE to level 4 to avoid stack overflow */
- bge cr1,2f /* Check if we hit limit of 4 */
+1: /* Limit nested MCE to level 4 to avoid stack overflow */
+ bgt cr1,unrecoverable_mce /* Check if we hit limit of 4 */
+ subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
EXCEPTION_PROLOG_COMMON_1()
/* We don't touch AMR here, we never go to virtual mode */
@@ -1013,21 +1013,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
mtmsrd r10,1
b machine_check_handle_early
-2:
- /* Stack overflow. Stay on emergency stack and panic.
- * Keep the ME bit off while panic-ing, so that if we hit
- * another machine check we checkstop.
- */
- addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
- ld r11,PACAKMSR(r13)
- LOAD_HANDLER(r12, unrecover_mce)
- li r10,MSR_ME
- andc r11,r11,r10 /* Turn off MSR_ME */
- mtspr SPRN_SRR0,r12
- mtspr SPRN_SRR1,r11
- RFI_TO_KERNEL
- b . /* prevent speculative execution */
-
EXC_COMMON_BEGIN(machine_check_common)
/*
* Machine check is different because we use a different
@@ -1141,32 +1126,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
* If yes, then stay on emergency stack and panic.
*/
andi. r11,r12,MSR_RI
- bne 2f
-1: mfspr r11,SPRN_SRR0
- LOAD_HANDLER(r10,unrecover_mce)
- mtspr SPRN_SRR0,r10
- ld r10,PACAKMSR(r13)
- /*
- * We are going down. But there are chances that we might get hit by
- * another MCE during panic path and we may run into unstable state
- * with no way out. Hence, turn ME bit off while going down, so that
- * when another MCE is hit during panic path, system will checkstop
- * and hypervisor will get restarted cleanly by SP.
- */
- li r3,MSR_ME
- andc r10,r10,r3 /* Turn off MSR_ME */
- mtspr SPRN_SRR1,r10
- RFI_TO_KERNEL
- b .
-2:
+ beq unrecoverable_mce
+
/*
* Check if we have successfully handled/recovered from error, if not
* then stay on emergency stack and panic.
*/
ld r3,RESULT(r1) /* Load result */
cmpdi r3,0 /* see if we handled MCE successfully */
-
- beq 1b /* if !handled then panic */
+ beq unrecoverable_mce /* if !handled then panic */
/*
* Return from MC interrupt.
@@ -1189,17 +1157,35 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0
EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
-EXC_COMMON_BEGIN(unrecover_mce)
+EXC_COMMON_BEGIN(unrecoverable_mce)
+ /*
+ * We are going down. But there are chances that we might get hit by
+ * another MCE during panic path and we may run into unstable state
+ * with no way out. Hence, turn ME bit off while going down, so that
+ * when another MCE is hit during panic path, system will checkstop
+ * and hypervisor will get restarted cleanly by SP.
+ */
+BEGIN_FTR_SECTION
+ li r10,0 /* clear MSR_RI */
+ mtmsrd r10,1
+ bl disable_machine_check
+END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
+ ld r10,PACAKMSR(r13)
+ li r3,MSR_ME
+ andc r10,r10,r3
+ mtmsrd r10
+
/* Invoke machine_check_exception to print MCE event and panic. */
addi r3,r1,STACK_FRAME_OVERHEAD
bl machine_check_exception
+
/*
- * We will not reach here. Even if we did, there is no way out. Call
- * unrecoverable_exception and die.
+ * We will not reach here. Even if we did, there is no way out.
+ * Call unrecoverable_exception and die.
*/
-1: addi r3,r1,STACK_FRAME_OVERHEAD
+ addi r3,r1,STACK_FRAME_OVERHEAD
bl unrecoverable_exception
- b 1b
+ b .
EXC_REAL_BEGIN(data_access, 0x300, 0x80)
@@ -2283,6 +2269,21 @@ enable_machine_check:
1: mtlr r0
blr
+/* MSR[RI] should be clear because this uses SRR[01] */
+disable_machine_check:
+ mflr r0
+ bcl 20,31,$+4
+0: mflr r3
+ addi r3,r3,(1f - 0b)
+ mtspr SPRN_SRR0,r3
+ mfmsr r3
+ li r4,MSR_ME
+ andc r3,r3,r4
+ mtspr SPRN_SRR1,r3
+ RFI_TO_KERNEL
+1: mtlr r0
+ blr
+
/*
* Hash table stuff
*/
--
2.20.1
^ permalink raw reply related
* [PATCH v2 15/16] powerpc/64s/exception: untangle early machine check handler branch
From: Nicholas Piggin @ 2019-07-10 15:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh Salgaonkar, Nicholas Piggin, Aravinda Prasad
In-Reply-To: <20190710151950.31906-1-npiggin@gmail.com>
machine_check_early_common now branches to machine_check_handle_early
which is its only caller.
Move interleaving code out of the way, and remove the branch.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 129 +++++++++++++--------------
1 file changed, 62 insertions(+), 67 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 95dd7ff3ef04..d196558d4243 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -956,6 +956,16 @@ TRAMP_REAL_BEGIN(machine_check_fwnmi)
TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
+#define MACHINE_CHECK_HANDLER_WINDUP \
+ /* Clear MSR_RI before setting SRR0 and SRR1. */\
+ li r9,0; \
+ mtmsrd r9,1; /* Clear MSR_RI */ \
+ /* Decrement paca->in_mce now RI is clear. */ \
+ lhz r12,PACA_IN_MCE(r13); \
+ subi r12,r12,1; \
+ sth r12,PACA_IN_MCE(r13); \
+ EXCEPTION_RESTORE_REGS EXC_STD
+
EXC_COMMON_BEGIN(machine_check_early_common)
mtctr r10 /* Restore ctr */
mfspr r11,SPRN_SRR0
@@ -1011,74 +1021,7 @@ BEGIN_FTR_SECTION
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
li r10,MSR_RI
mtmsrd r10,1
- b machine_check_handle_early
-EXC_COMMON_BEGIN(machine_check_common)
- /*
- * Machine check is different because we use a different
- * save area: PACA_EXMC instead of PACA_EXGEN.
- */
- EXCEPTION_COMMON(PACA_EXMC, 0x200)
- FINISH_NAP
- RECONCILE_IRQ_STATE(r10, r11)
- ld r3,PACA_EXMC+EX_DAR(r13)
- lwz r4,PACA_EXMC+EX_DSISR(r13)
- /* Enable MSR_RI when finished with PACA_EXMC */
- li r10,MSR_RI
- mtmsrd r10,1
- std r3,_DAR(r1)
- std r4,_DSISR(r1)
- bl save_nvgprs
- addi r3,r1,STACK_FRAME_OVERHEAD
- bl machine_check_exception
- b ret_from_except
-
-#define MACHINE_CHECK_HANDLER_WINDUP \
- /* Clear MSR_RI before setting SRR0 and SRR1. */\
- li r9,0; \
- mtmsrd r9,1; /* Clear MSR_RI */ \
- /* Decrement paca->in_mce now RI is clear. */ \
- lhz r12,PACA_IN_MCE(r13); \
- subi r12,r12,1; \
- sth r12,PACA_IN_MCE(r13); \
- EXCEPTION_RESTORE_REGS EXC_STD
-
-#ifdef CONFIG_PPC_P7_NAP
-/*
- * This is an idle wakeup. Low level machine check has already been
- * done. Queue the event then call the idle code to do the wake up.
- */
-EXC_COMMON_BEGIN(machine_check_idle_common)
- bl machine_check_queue_event
-
- /*
- * We have not used any non-volatile GPRs here, and as a rule
- * most exception code including machine check does not.
- * Therefore PACA_NAPSTATELOST does not need to be set. Idle
- * wakeup will restore volatile registers.
- *
- * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
- *
- * Then decrement MCE nesting after finishing with the stack.
- */
- ld r3,_MSR(r1)
- ld r4,_LINK(r1)
-
- lhz r11,PACA_IN_MCE(r13)
- subi r11,r11,1
- sth r11,PACA_IN_MCE(r13)
-
- mtlr r4
- rlwinm r10,r3,47-31,30,31
- cmpwi cr1,r10,2
- bltlr cr1 /* no state loss, return to idle caller */
- b idle_return_gpr_loss
-#endif
- /*
- * Handle machine check early in real mode. We come here with
- * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
- */
-EXC_COMMON_BEGIN(machine_check_handle_early)
bl save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
bl machine_check_early
@@ -1157,6 +1100,58 @@ END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 1, 1, 0
EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
+EXC_COMMON_BEGIN(machine_check_common)
+ /*
+ * Machine check is different because we use a different
+ * save area: PACA_EXMC instead of PACA_EXGEN.
+ */
+ EXCEPTION_COMMON(PACA_EXMC, 0x200)
+ FINISH_NAP
+ RECONCILE_IRQ_STATE(r10, r11)
+ ld r3,PACA_EXMC+EX_DAR(r13)
+ lwz r4,PACA_EXMC+EX_DSISR(r13)
+ /* Enable MSR_RI when finished with PACA_EXMC */
+ li r10,MSR_RI
+ mtmsrd r10,1
+ std r3,_DAR(r1)
+ std r4,_DSISR(r1)
+ bl save_nvgprs
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ bl machine_check_exception
+ b ret_from_except
+
+#ifdef CONFIG_PPC_P7_NAP
+/*
+ * This is an idle wakeup. Low level machine check has already been
+ * done. Queue the event then call the idle code to do the wake up.
+ */
+EXC_COMMON_BEGIN(machine_check_idle_common)
+ bl machine_check_queue_event
+
+ /*
+ * We have not used any non-volatile GPRs here, and as a rule
+ * most exception code including machine check does not.
+ * Therefore PACA_NAPSTATELOST does not need to be set. Idle
+ * wakeup will restore volatile registers.
+ *
+ * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
+ *
+ * Then decrement MCE nesting after finishing with the stack.
+ */
+ ld r3,_MSR(r1)
+ ld r4,_LINK(r1)
+
+ lhz r11,PACA_IN_MCE(r13)
+ subi r11,r11,1
+ sth r11,PACA_IN_MCE(r13)
+
+ mtlr r4
+ rlwinm r10,r3,47-31,30,31
+ cmpwi cr1,r10,2
+ bltlr cr1 /* no state loss, return to idle caller */
+ b idle_return_gpr_loss
+#endif
+
EXC_COMMON_BEGIN(unrecoverable_mce)
/*
* We are going down. But there are chances that we might get hit by
--
2.20.1
^ permalink raw reply related
* [PATCH v2 16/16] powerpc/64s/exception: machine check improve labels and comments
From: Nicholas Piggin @ 2019-07-10 15:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Mahesh Salgaonkar, Nicholas Piggin, Aravinda Prasad
In-Reply-To: <20190710151950.31906-1-npiggin@gmail.com>
Short forward and backward branches can be given number labels,
but larger significant divergences in code path a more readable
if they're given descriptive names.
Also adjusts a comment to account for guest delivery.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/exceptions-64s.S | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index d196558d4243..a69f4599e304 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -1052,7 +1052,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
*/
lbz r11,HSTATE_IN_GUEST(r13)
cmpwi r11,0 /* Check if coming from guest */
- bne 9f /* continue if we are. */
+ bne mce_deliver /* continue if we are. */
#endif
/*
@@ -1060,7 +1060,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
* exception handler which will deliver the MC event to this kernel.
*/
andi. r11,r12,MSR_PR /* See if coming from user. */
- bne 9f /* continue in V mode if we are. */
+ bne mce_deliver /* continue in V mode if we are. */
/*
* At this point we are coming from kernel context.
@@ -1088,8 +1088,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
MACHINE_CHECK_HANDLER_WINDUP
RFI_TO_KERNEL
-9:
- /* Deliver the machine check to host kernel in V mode. */
+mce_deliver:
+ /*
+ * This is a host user or guest MCE. Restore all registers, then
+ * run the "late" handler. For host user, this will run the
+ * machine_check_exception handler in virtual mode like a normal
+ * interrupt handler. For guest, this will trigger the KVM test
+ * and branch to the KVM interrupt similarly to other interrupts.
+ */
BEGIN_FTR_SECTION
ld r10,ORIG_GPR3(r1)
mtspr SPRN_CFAR,r10
--
2.20.1
^ permalink raw reply related
* [Bug 204125] FTBFS on ppc64 big endian and gcc9 because of -mcall-aixdesc and missing __linux__
From: bugzilla-daemon @ 2019-07-10 15:37 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-204125-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=204125
Segher Boessenkool (segher@kernel.crashing.org) changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |segher@kernel.crashing.org
--- Comment #1 from Segher Boessenkool (segher@kernel.crashing.org) ---
(In reply to Daniel Kolesa from comment #0)
> On ppc64 big endian, the kernel builds with `-mcall-aixdesc` which since gcc
> 9.x removes `__linux__` from the list of macros being defined.
This is a bug. Please report at https://gcc.gnu.org/bugzilla .
> This behavior
> is supposed to be more correct (as it's in this case nothing but a hack, the
> flag should apparently only be used when building for AIX)
What makes you think that?
OTOH, why does the kernel use that option?
> but sadly it
> breaks build since several things within the tree rely on `__linux__` being
> defined and `#ifdef` some of their code based on said macro.
Those are bugs as well, then.
> Just removing `-mcall-aixdesc` (and using just `-mabi=elfv1`) is however not
> enough, as that instead causes countless undefined references to just about
> every symbol when linking `vmlinux`. It would seem that `-mcall-aixdesc`
> changes the way symbols are declared in a way that is not expected.
> Little endian is not affected because that one uses `-mabi=elfv2`
> exclusively.
Of course, that is the only defined ABI for powerpc64le after all.
> Also, is there any reason not to allow an ELFv2 kernel to be built on big
> endian?
Building it _on_ BE works just fine, of course. But you mean building a BE
kernel using the ELFv2 ABI. This is not supported; it would require writing
other versions for various low-level things.
ELFv2 is not supported in BE userland, either, btw.
> There are some supposed performance benefits, and ELFv2 itself
> supports either endianness. The current kbuild logic pretty much forces
> ELFv1 for big endian and ELFv2 for little endian.
ELFv2 has a few little benefits; it is newer, there were lessons learnt. It
would be surprising if it has better than trivial advantages for the BE kernel
though. But feel free to try, of course :-)
--
You are receiving this mail because:
You are watching the assignee of the bug.
^ permalink raw reply
* [Bug 204125] FTBFS on ppc64 big endian and gcc9 because of -mcall-aixdesc and missing __linux__
From: bugzilla-daemon @ 2019-07-10 15:41 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-204125-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=204125
--- Comment #2 from Daniel Kolesa (linux@octaforge.org) ---
ELFv2 works perfectly fine in BE userland, the musl libc *requires* ELFv2 on
both endians and glibc works okay using either. ELFv2 was defined for both
endians and there are distros that make use of it on BE (Adélie Linux supports
only BE with musl libc and ELFv2, Void Linux has both BE and LE on musl and
glibc, all using ELFv2).
--
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You are watching the assignee of the bug.
^ permalink raw reply
* [Bug 204125] FTBFS on ppc64 big endian and gcc9 because of -mcall-aixdesc and missing __linux__
From: bugzilla-daemon @ 2019-07-10 15:57 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-204125-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=204125
--- Comment #3 from Daniel Kolesa (linux@octaforge.org) ---
Also, reported in gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91135
Let's see what the compiler people have to say...
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* [Bug 204125] FTBFS on ppc64 big endian and gcc9 because of -mcall-aixdesc and missing __linux__
From: bugzilla-daemon @ 2019-07-10 16:04 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-204125-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=204125
--- Comment #5 from Daniel Kolesa (linux@octaforge.org) ---
I have an entire distro built with it. A small number of things require minor
patches. Some of these have been upstreamed, some of these are pending (for
example, to make OpenSSL assembly work on BE/ELFv2, it requires about 5 lines
of changes to pass all of the testsuite, and a PR for that is up). Glibc used
to not work about a year ago I think, these days it works perfectly fine and we
generally have no major issues with any software that already worked on BE in
the first place.
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* [Bug 204125] FTBFS on ppc64 big endian and gcc9 because of -mcall-aixdesc and missing __linux__
From: bugzilla-daemon @ 2019-07-10 16:01 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <bug-204125-206035@https.bugzilla.kernel.org/>
https://bugzilla.kernel.org/show_bug.cgi?id=204125
--- Comment #4 from Segher Boessenkool (segher@kernel.crashing.org) ---
I meant GNU userland. I don't know any project that officially support
BE ELFv2. No BE ELFv2 Linux ABI is defined, either, as far as I know.
It's great to hear that a lot of it works fine though :-)
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* Re: [PATCH v4 5/8] KVM: PPC: Ultravisor: Restrict flush of the partition tlb cache
From: Ram Pai @ 2019-07-10 17:09 UTC (permalink / raw)
To: janani
Cc: Madhavan Srinivasan, Michael Anderson, Claudio Carvalho, kvm-ppc,
Bharata B Rao, linuxppc-dev, Ryan Grimm, Sukadev Bhattiprolu,
Thiago Bauermann, Anshuman Khandual
In-Reply-To: <134bd0eb97ed6cc616ced38732b9b52c@linux.vnet.ibm.com>
On Mon, Jul 08, 2019 at 02:54:52PM -0500, janani wrote:
> On 2019-06-28 15:08, Claudio Carvalho wrote:
> >From: Ram Pai <linuxram@us.ibm.com>
> >
> >Ultravisor is responsible for flushing the tlb cache, since it manages
> >the PATE entries. Hence skip tlb flush, if the ultravisor firmware is
> >available.
> >
> >Signed-off-by: Ram Pai <linuxram@us.ibm.com>
> >Signed-off-by: Claudio Carvalho <cclaudio@linux.ibm.com>
> >---
> > arch/powerpc/mm/book3s64/pgtable.c | 33 +++++++++++++++++-------------
> > 1 file changed, 19 insertions(+), 14 deletions(-)
> >
> >diff --git a/arch/powerpc/mm/book3s64/pgtable.c
> >b/arch/powerpc/mm/book3s64/pgtable.c
> >index 224c5c7c2e3d..bc8eb2bf9810 100644
> >--- a/arch/powerpc/mm/book3s64/pgtable.c
> >+++ b/arch/powerpc/mm/book3s64/pgtable.c
> >@@ -224,6 +224,23 @@ void __init mmu_partition_table_init(void)
> > powernv_set_nmmu_ptcr(ptcr);
> > }
> >
> >+static void flush_partition(unsigned int lpid, unsigned long dw0)
> >+{
> >+ if (dw0 & PATB_HR) {
> >+ asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 1) : :
> >+ "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> >+ asm volatile(PPC_TLBIE_5(%0, %1, 2, 1, 1) : :
> >+ "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> >+ trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 1);
> >+ } else {
> >+ asm volatile(PPC_TLBIE_5(%0, %1, 2, 0, 0) : :
> >+ "r" (TLBIEL_INVAL_SET_LPID), "r" (lpid));
> >+ trace_tlbie(lpid, 0, TLBIEL_INVAL_SET_LPID, lpid, 2, 0, 0);
> >+ }
> >+ /* do we need fixup here ?*/
> >+ asm volatile("eieio; tlbsync; ptesync" : : : "memory");
> >+}
> >+
> > static void __mmu_partition_table_set_entry(unsigned int lpid,
> > unsigned long dw0,
> > unsigned long dw1)
> >@@ -238,20 +255,8 @@ static void
> >__mmu_partition_table_set_entry(unsigned int lpid,
> > * The type of flush (hash or radix) depends on what the previous
> > * use of this partition ID was, not the new use.
> > */
> >- asm volatile("ptesync" : : : "memory");
> Doesn't the line above that was deleted need to be added to the
> beginning of flush_partition()
It has to. It got dropped erroneously.
This is a good catch!
Thanks,
RP
^ permalink raw reply
* Re: [PATCH v3 5/7] kexec_elf: remove elf_addr_to_cpu macro
From: Sven Schnelle @ 2019-07-10 18:05 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linuxppc-dev, deller, kexec
In-Reply-To: <49206784-009c-391b-5f9a-11e9b1de930b@c-s.fr>
Hi Christophe,
On Wed, Jul 10, 2019 at 05:09:29PM +0200, Christophe Leroy wrote:
>
>
> Le 10/07/2019 à 16:29, Sven Schnelle a écrit :
> > It had only one definition, so just use the function directly.
>
> It had only one definition because it was for ppc64 only.
> But as far as I understand (at least from the name of the new file), you
> want it to be generic, don't you ? Therefore I get on 32 bits it would be
> elf32_to_cpu().
That brings up the question whether we need those endianess conversions. I would
assume that the ELF file has always the same endianess as the running kernel. So
i think we could just drop them. What do you think?
Regards
Sven
^ permalink raw reply
* Re: [PATCH V3 2/2] ASoC: fsl_esai: recover the channel swap after xrun
From: Nicolin Chen @ 2019-07-10 23:36 UTC (permalink / raw)
To: shengjiu.wang
Cc: alsa-devel, timur, Xiubo.Lee, festevam, linux-kernel, broonie,
linuxppc-dev
In-Reply-To: <a055d9d590124aad2de70e97266e50d2bae752c8.1562566531.git.shengjiu.wang@nxp.com>
Hi Shengjiu,
Mostly looks good to me, just some small comments.
On Mon, Jul 08, 2019 at 02:38:52PM +0800, shengjiu.wang@nxp.com wrote:
> +static void fsl_esai_hw_reset(unsigned long arg)
> +{
> + struct fsl_esai *esai_priv = (struct fsl_esai *)arg;
> + u32 saisr, tfcr, rfcr;
> + bool tx = true, rx = false, enabled[2];
Could we swap the lines of u32 and bool? It'd look better.
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
> + ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
> + ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
Let's add a line of comments for these two:
/* Enforce ESAI personal resets for both TX and RX */
> + /*
> + * Restore registers by regcache_sync, and ignore
> + * return value
> + */
Could fit into single-line?
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
> + ESAI_xCR_xPR_MASK, 0);
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
> + ESAI_xCR_xPR_MASK, 0);
> +
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
> + ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
> + regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
> + ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
Could remove the blank line and add a line of comments:
/* Remove ESAI personal resets by configuring PCRC and PRRC also */
Btw, I still feel this personal reset can be stuffed into one
of the wrapper functions. But let's keep this simple for now.
> + regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
Why do we read saisr here? All its bits would get cleared by
the hardware reset. If it's a must to clear again, we should
add a line of comments to emphasize it.
Thank you
^ permalink raw reply
* Re: pata-macio on PowerBook G3: stuck interrupt with MATSHITA CR-174 CD-ROM
From: Finn Thain @ 2019-07-11 0:26 UTC (permalink / raw)
To: linuxppc-dev, linux-ide; +Cc: Stan
In-Reply-To: <alpine.LNX.2.21.1906271717080.68@nippy.intranet>
On Fri, 28 Jun 2019, Finn Thain wrote:
> Hi All,
>
> I've received a bug report concerning the pata-macio driver, when running
> on a PowerBook G3 (Wallstreet).
>
> With CONFIG_PATA_MACIO=n && CONFIG_BLK_DEV_IDE_PMAC=y, everything works.
>
> With CONFIG_PATA_MACIO=y && CONFIG_BLK_DEV_IDE_PMAC=n, the CD-ROM fails.
>
> When the CD-ROM mediabay module is swapped for a DVD-ROM mediabay module,
> everything works (either pata-macio or ide-pmac driver works fine).
>
> I'm not familiar with ATA device drivers or the "Heathrow" chipset and its
> ATA interfaces so any hints as to how to debug this would be appreciated.
>
...
>
> These logs are from v4.20 but the problem is the same in v5.2-rc2.
>
In the linux-ide list archive I found the same bug reported in 2.6.33-rc2,
shortly after the pata-macio driver was merged.
https://lore.kernel.org/linux-ide/19254.17766.674348.933702@pilspetsen.it.uu.se/
That report also involves a Matshita CD-ROM and a Heathrow controller
(beige G3).
In that thread Ben suggested that the cause may be a firmware bug in the
drive. Is there a quirk or other workaround for that kind of bug?
I tried removing the controller reset but there was no improvement...
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
index 57f2ec71cfc3..b2fd5e20367f 100644
--- a/drivers/ata/pata_macio.c
+++ b/drivers/ata/pata_macio.c
@@ -1096,7 +1096,7 @@ static int pata_macio_common_init(struct pata_macio_priv *priv,
priv->host->ports[0]->private_data = priv;
/* hard-reset the controller */
- pata_macio_reset_hw(priv, 0);
+// pata_macio_reset_hw(priv, 0);
pata_macio_apply_timings(priv->host->ports[0], 0);
/* Enable bus master if necessary */
--
^ permalink raw reply related
* [PATCH 2/2] powerpc/64s: Remove idle workaround code from restore_cpu_cpufeatures
From: Nicholas Piggin @ 2019-07-11 2:24 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
In-Reply-To: <20190711022404.18132-1-npiggin@gmail.com>
Idle code no longer uses the .cpu_restore CPU operation to restore
SPRs, so this workaround is no longer required.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/dt_cpu_ftrs.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index c66fd3ce6478..78db3e6eb45e 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -71,7 +71,6 @@ static int hv_mode;
static struct {
u64 lpcr;
- u64 lpcr_clear;
u64 hfscr;
u64 fscr;
} system_registers;
@@ -80,24 +79,7 @@ static void (*init_pmu_registers)(void);
static void __restore_cpu_cpufeatures(void)
{
- u64 lpcr;
-
- /*
- * LPCR is restored by the power on engine already. It can be changed
- * after early init e.g., by radix enable, and we have no unified API
- * for saving and restoring such SPRs.
- *
- * This ->restore hook should really be removed from idle and register
- * restore moved directly into the idle restore code, because this code
- * doesn't know how idle is implemented or what it needs restored here.
- *
- * The best we can do to accommodate secondary boot and idle restore
- * for now is "or" LPCR with existing.
- */
- lpcr = mfspr(SPRN_LPCR);
- lpcr |= system_registers.lpcr;
- lpcr &= ~system_registers.lpcr_clear;
- mtspr(SPRN_LPCR, lpcr);
+ mtspr(SPRN_LPCR, system_registers.lpcr);
if (hv_mode) {
mtspr(SPRN_LPID, 0);
mtspr(SPRN_HFSCR, system_registers.hfscr);
@@ -318,7 +300,6 @@ static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
{
u64 lpcr;
- system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR);
lpcr = mfspr(SPRN_LPCR);
lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
mtspr(SPRN_LPCR, lpcr);
--
2.20.1
^ permalink raw reply related
* [PATCH 1/2] powerpc/64s: remplement power4_idle code in C
From: Nicholas Piggin @ 2019-07-11 2:24 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
This implements the tricky tracing and soft irq handling bits in C,
leaving the low level bit to asm.
A functional difference is that this redirects the interrupt exit to
a return stub to execute blr, rather than the lr address itself. This
is probably barely measurable on real hardware, but it keeps the link
stack balanced.
Tested with QEMU.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/processor.h | 3 +
arch/powerpc/kernel/Makefile | 3 +-
arch/powerpc/kernel/exceptions-64s.S | 9 ---
arch/powerpc/kernel/idle.c | 25 ++++++++
arch/powerpc/kernel/idle_book3s.S | 35 +++++++++++
arch/powerpc/kernel/idle_power4.S | 87 ----------------------------
arch/powerpc/platforms/Kconfig | 4 ++
7 files changed, 68 insertions(+), 98 deletions(-)
delete mode 100644 arch/powerpc/kernel/idle_power4.S
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 706ac5df546f..c0d870c57061 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -418,6 +418,9 @@ static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
+#ifdef CONFIG_PPC_970_NAP
+extern void power4_idle_nap(void);
+#endif
extern unsigned long cpuidle_disable;
enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 56dfa7a2a6f2..04c6d8cc241b 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -64,8 +64,7 @@ obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o idle_book3e.o
obj-$(CONFIG_PPC_BARRIER_NOSPEC) += security.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o
-obj-$(CONFIG_PPC_970_NAP) += idle_power4.o
-obj-$(CONFIG_PPC_P7_NAP) += idle_book3s.o
+obj-$(CONFIG_PPC_BOOK3S_IDLE) += idle_book3s.o
procfs-y := proc_powerpc.o
obj-$(CONFIG_PROC_FS) += $(procfs-y)
rtaspci-$(CONFIG_PPC64)-$(CONFIG_PCI) := rtas_pci.o
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index eee5bef736c8..64d5ffbb07d1 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -2286,15 +2286,6 @@ USE_FIXED_SECTION(virt_trampolines)
__end_interrupts:
DEFINE_FIXED_SYMBOL(__end_interrupts)
-#ifdef CONFIG_PPC_970_NAP
-EXC_COMMON_BEGIN(power4_fixup_nap)
- andc r9,r9,r10
- std r9,TI_LOCAL_FLAGS(r11)
- ld r10,_LINK(r1) /* make idle task do the */
- std r10,_NIP(r1) /* equivalent of a blr */
- blr
-#endif
-
CLOSE_FIXED_SECTION(real_vectors);
CLOSE_FIXED_SECTION(real_trampolines);
CLOSE_FIXED_SECTION(virt_vectors);
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index d7216c9abda1..605defde43b9 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -81,6 +81,31 @@ void arch_cpu_idle(void)
int powersave_nap;
+#ifdef CONFIG_PPC_970_NAP
+void power4_idle(void)
+{
+ if (!cpu_has_feature(CPU_FTR_CAN_NAP))
+ return;
+
+ if (!powersave_nap)
+ return;
+
+ if (!prep_irq_for_idle())
+ return;
+
+ if (cpu_has_feature(CPU_FTR_ALTIVEC))
+ asm volatile("DSSALL ; sync" ::: "memory");
+
+ power4_idle_nap();
+
+ /*
+ * power4_idle_nap returns with interrupts enabled (soft and hard).
+ * to our caller with interrupts enabled (soft and hard). Our caller
+ * can cope with either interrupts disabled or enabled upon return.
+ */
+}
+#endif
+
#ifdef CONFIG_SYSCTL
/*
* Register the sysctl to set/clear powersave_nap.
diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
index 2dfbd5d5b932..5afac9177fec 100644
--- a/arch/powerpc/kernel/idle_book3s.S
+++ b/arch/powerpc/kernel/idle_book3s.S
@@ -19,7 +19,9 @@
#include <asm/asm-offsets.h>
#include <asm/ppc-opcode.h>
#include <asm/cpuidle.h>
+#include <asm/thread_info.h> /* TLF_NAPPING */
+#ifdef CONFIG_PPC_P7_NAP
/*
* Desired PSSCR in r3
*
@@ -185,4 +187,37 @@ _GLOBAL(isa206_idle_insn_mayloss)
bne 2f
IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
2: IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
+#endif
+#ifdef CONFIG_PPC_970_NAP
+_GLOBAL(power4_idle_nap)
+ LOAD_REG_IMMEDIATE(r7, MSR_KERNEL|MSR_EE|MSR_POW)
+ ld r9,PACA_THREAD_INFO(r13)
+ ld r8,TI_LOCAL_FLAGS(r9)
+ ori r8,r8,_TLF_NAPPING
+ std r8,TI_LOCAL_FLAGS(r9)
+ /*
+ * NAPPING bit is set, from this point onward power4_fixup_nap
+ * will cause exceptions to return to power4_idle_nap_return.
+ */
+1: sync
+ isync
+ mtmsrd r7
+ isync
+ b 1b
+power4_idle_nap_return:
+ blr
+
+ /*
+ * Called by exception entry code if _TLF_NAPPING was set, this clear
+ * the NAPPING flag, and redirects the exception exit to
+ * power4_fixup_nap_return.
+ */
+ .globl power4_fixup_nap
+power4_fixup_nap:
+ andc r9,r9,r10
+ std r9,TI_LOCAL_FLAGS(r11)
+ LOAD_REG_ADDR(r10, power4_idle_nap_return)
+ std r10,_NIP(r1)
+ blr
+#endif
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
deleted file mode 100644
index a2fdb0a34b75..000000000000
--- a/arch/powerpc/kernel/idle_power4.S
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file contains the power_save function for 970-family CPUs.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/threads.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/thread_info.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/irqflags.h>
-#include <asm/hw_irq.h>
-#include <asm/feature-fixups.h>
-
-#undef DEBUG
-
- .text
-
-_GLOBAL(power4_idle)
-BEGIN_FTR_SECTION
- blr
-END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
- /* Now check if user or arch enabled NAP mode */
- LOAD_REG_ADDRBASE(r3,powersave_nap)
- lwz r4,ADDROFF(powersave_nap)(r3)
- cmpwi 0,r4,0
- beqlr
-
- /* This sequence is similar to prep_irq_for_idle() */
-
- /* Hard disable interrupts */
- mfmsr r7
- rldicl r0,r7,48,1
- rotldi r0,r0,16
- mtmsrd r0,1
-
- /* Check if something happened while soft-disabled */
- lbz r0,PACAIRQHAPPENED(r13)
- cmpwi cr0,r0,0
- bne- 2f
-
- /*
- * Soft-enable interrupts. This will make power4_fixup_nap return
- * to our caller with interrupts enabled (soft and hard). The caller
- * can cope with either interrupts disabled or enabled upon return.
- */
-#ifdef CONFIG_TRACE_IRQFLAGS
- /* Tell the tracer interrupts are on, because idle responds to them. */
- mflr r0
- std r0,16(r1)
- stdu r1,-128(r1)
- bl trace_hardirqs_on
- addi r1,r1,128
- ld r0,16(r1)
- mtlr r0
- mfmsr r7
-#endif /* CONFIG_TRACE_IRQFLAGS */
-
- li r0,IRQS_ENABLED
- stb r0,PACAIRQSOFTMASK(r13) /* we'll hard-enable shortly */
-BEGIN_FTR_SECTION
- DSSALL
- sync
-END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
- ld r9, PACA_THREAD_INFO(r13)
- ld r8,TI_LOCAL_FLAGS(r9) /* set napping bit */
- ori r8,r8,_TLF_NAPPING /* so when we take an exception */
- std r8,TI_LOCAL_FLAGS(r9) /* it will return to our caller */
- ori r7,r7,MSR_EE
- oris r7,r7,MSR_POW@h
-1: sync
- isync
- mtmsrd r7
- isync
- b 1b
-
-2: /* Return if an interrupt had happened while soft disabled */
- /* Set the HARD_DIS flag because interrupts are now hard disabled */
- ori r0,r0,PACA_IRQ_HARD_DIS
- stb r0,PACAIRQHAPPENED(r13)
- blr
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index f3fb79fccc72..736325451bc4 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -177,6 +177,10 @@ config PPC_970_NAP
config PPC_P7_NAP
bool
+config PPC_BOOK3S_IDLE
+ def_bool y
+ depends on (PPC_970_NAP || PPC_P7_NAP)
+
config PPC_INDIRECT_PIO
bool
select GENERIC_IOMAP
--
2.20.1
^ permalink raw reply related
* Re: [PATCH v2] powerpc/imc: Dont create debugfs files for cpu-less nodes
From: Michael Ellerman @ 2019-07-11 4:53 UTC (permalink / raw)
To: Madhavan Srinivasan; +Cc: Qian Cai, Madhavan Srinivasan, linuxppc-dev
In-Reply-To: <20190702092112.4015-1-maddy@linux.vnet.ibm.com>
Hi Maddy,
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> writes:
> diff --git a/arch/powerpc/platforms/powernv/opal-imc.c b/arch/powerpc/platforms/powernv/opal-imc.c
> index 186109bdd41b..e04b20625cb9 100644
> --- a/arch/powerpc/platforms/powernv/opal-imc.c
> +++ b/arch/powerpc/platforms/powernv/opal-imc.c
> @@ -69,20 +69,20 @@ static void export_imc_mode_and_cmd(struct device_node *node,
> if (of_property_read_u32(node, "cb_offset", &cb_offset))
> cb_offset = IMC_CNTL_BLK_OFFSET;
>
> - for_each_node(nid) {
> - loc = (u64)(pmu_ptr->mem_info[chip].vbase) + cb_offset;
> + while (ptr->vbase != NULL) {
This means you'll bail out as soon as you find a node with no vbase, but
it's possible we could have a CPU-less node intermingled with other
nodes.
So I think you want to keep the for loop, but continue if you see a NULL
vbase?
> + loc = (u64)(ptr->vbase) + cb_offset;
> imc_mode_addr = (u64 *)(loc + IMC_CNTL_BLK_MODE_OFFSET);
> - sprintf(mode, "imc_mode_%d", nid);
> + sprintf(mode, "imc_mode_%d", (u32)(ptr->id));
> if (!imc_debugfs_create_x64(mode, 0600, imc_debugfs_parent,
> imc_mode_addr))
> goto err;
>
> imc_cmd_addr = (u64 *)(loc + IMC_CNTL_BLK_CMD_OFFSET);
> - sprintf(cmd, "imc_cmd_%d", nid);
> + sprintf(cmd, "imc_cmd_%d", (u32)(ptr->id));
> if (!imc_debugfs_create_x64(cmd, 0600, imc_debugfs_parent,
> imc_cmd_addr))
> goto err;
> - chip++;
> + ptr++;
> }
> return;
cheers
^ permalink raw reply
* Re: [PATCH v5 1/7] kvmppc: HMM backend driver to manage pages of secure guest
From: Bharata B Rao @ 2019-07-11 5:08 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: linuxram, cclaudio, kvm-ppc, Linuxppc-dev, linux-mm, jglisse,
janani, aneesh.kumar, paulus, sukadev, linuxppc-dev
In-Reply-To: <20190710134734.GB2873@ziepe.ca>
On Wed, Jul 10, 2019 at 10:47:34AM -0300, Jason Gunthorpe wrote:
> On Tue, Jul 09, 2019 at 01:55:28PM -0500, janani wrote:
>
> > > +int kvmppc_hmm_init(void)
> > > +{
> > > + int ret = 0;
> > > + unsigned long size;
> > > +
> > > + size = kvmppc_get_secmem_size();
> > > + if (!size) {
> > > + ret = -ENODEV;
> > > + goto out;
> > > + }
> > > +
> > > + kvmppc_hmm.device = hmm_device_new(NULL);
> > > + if (IS_ERR(kvmppc_hmm.device)) {
> > > + ret = PTR_ERR(kvmppc_hmm.device);
> > > + goto out;
> > > + }
> > > +
> > > + kvmppc_hmm.devmem = hmm_devmem_add(&kvmppc_hmm_devmem_ops,
> > > + &kvmppc_hmm.device->device, size);
> > > + if (IS_ERR(kvmppc_hmm.devmem)) {
> > > + ret = PTR_ERR(kvmppc_hmm.devmem);
> > > + goto out_device;
> > > + }
>
> This 'hmm_device' API family was recently deleted from hmm:
Hmmm... I still find it in upstream, guess it will be removed soon?
I find the below commit in mmotm.
>
> commit 07ec38917e68f0114b9c8aeeb1c584b5e73e4dd6
> Author: Christoph Hellwig <hch@lst.de>
> Date: Wed Jun 26 14:27:01 2019 +0200
>
> mm: remove the struct hmm_device infrastructure
>
> This code is a trivial wrapper around device model helpers, which
> should have been integrated into the driver device model usage from
> the start. Assuming it actually had users, which it never had since
> the code was added more than 1 1/2 years ago.
>
> This patch should use the driver core directly instead.
>
> Regards,
> Jason
^ permalink raw reply
* Re: [PATCH V3 2/2] ASoC: fsl_esai: recover the channel swap after xrun
From: S.j. Wang @ 2019-07-11 6:09 UTC (permalink / raw)
To: Nicolin Chen
Cc: alsa-devel@alsa-project.org, timur@kernel.org,
Xiubo.Lee@gmail.com, festevam@gmail.com,
linux-kernel@vger.kernel.org, broonie@kernel.org,
linuxppc-dev@lists.ozlabs.org
>
> Hi Shengjiu,
>
> Mostly looks good to me, just some small comments.
>
> On Mon, Jul 08, 2019 at 02:38:52PM +0800, shengjiu.wang@nxp.com wrote:
>
> > +static void fsl_esai_hw_reset(unsigned long arg) {
> > + struct fsl_esai *esai_priv = (struct fsl_esai *)arg;
> > + u32 saisr, tfcr, rfcr;
> > + bool tx = true, rx = false, enabled[2];
>
> Could we swap the lines of u32 and bool? It'd look better.
>
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
> > + ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
> > + ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
>
> Let's add a line of comments for these two:
> /* Enforce ESAI personal resets for both TX and RX */
>
> > + /*
> > + * Restore registers by regcache_sync, and ignore
> > + * return value
> > + */
>
> Could fit into single-line?
>
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR,
> > + ESAI_xCR_xPR_MASK, 0);
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR,
> > + ESAI_xCR_xPR_MASK, 0);
> > +
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
> > + ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
> > + regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
> > + ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
>
> Could remove the blank line and add a line of comments:
> /* Remove ESAI personal resets by configuring PCRC and PRRC also */
>
> Btw, I still feel this personal reset can be stuffed into one of the wrapper
> functions. But let's keep this simple for now.
>
> > + regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
>
> Why do we read saisr here? All its bits would get cleared by the hardware
> reset. If it's a must to clear again, we should add a line of comments to
> emphasize it.
This line can be removed.
Best regards
Wang Shengjiu
^ permalink raw reply
* Re: Coccinelle: Checking of_node_put() calls with SmPL
From: wen.yang99 @ 2019-07-11 6:35 UTC (permalink / raw)
To: Markus.Elfring, julia.lawall
Cc: wang.yi59, linux-pm, rjw, daniel.lezcano, kernel-janitors,
linux-kernel, oss, paulus, xue.zhihong, linuxppc-dev,
cheng.shengyu
In-Reply-To: <9d515026-5b74-cf0c-0c64-4fe242d4104e@web.de>
[-- Attachment #1.1: Type: text/plain, Size: 1622 bytes --]
> > we developed a coccinelle script to detect such problems.
>
> Would you find the implementation of the function “dt_init_idle_driver”
> suspicious according to discussed source code search patterns?
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpuidle/dt_idle_states.c?id=e9a83bd2322035ed9d7dcf35753d3f984d76c6a5#n208
> https://elixir.bootlin.com/linux/v5.2/source/drivers/cpuidle/dt_idle_states.c#L208
>
>
> > This script is still being improved.
>
> Will corresponding software development challenges become more interesting?
Hello Markus,
This is the simplified code pattern for it:
172 for (i = 0; ; i++) {
173 state_node = of_parse_phandle(...); ---> Obtain here
...
177 match_id = of_match_node(matches, state_node);
178 if (!match_id) {
179 err = -ENODEV;
180 break; ---> Jump out of the loop without releasing it
181 }
182
183 if (!of_device_is_available(state_node)) {
184 of_node_put(state_node);
185 continue; ---> Release the object references within a loop
186 }
...
208 of_node_put(state_node); --> Release the object references within a loop
209 }
210
211 of_node_put(state_node); --> There may be double free here.
This code pattern is very interesting and the coccinelle software should also recognize this pattern.
Regards,
Wen
^ permalink raw reply
* Re: Coccinelle: Checking of_node_put() calls with SmPL
From: Julia Lawall @ 2019-07-11 6:46 UTC (permalink / raw)
To: wen.yang99
Cc: wang.yi59, linux-pm, kernel-janitors, daniel.lezcano, rjw,
linux-kernel, oss, Markus.Elfring, xue.zhihong, paulus,
linuxppc-dev, cheng.shengyu
In-Reply-To: <201907111435459627761@zte.com.cn>
[-- Attachment #1: Type: text/plain, Size: 1808 bytes --]
On Thu, 11 Jul 2019, wen.yang99@zte.com.cn wrote:
> > > we developed a coccinelle script to detect such problems.
> >
> > Would you find the implementation of the function “dt_init_idle_driver”
> > suspicious according to discussed source code search patterns?
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/cpuidle/dt_idle_states.c?id=e9a83bd2322035ed9d7dcf35753d3f984d76c6a5#n208
> > https://elixir.bootlin.com/linux/v5.2/source/drivers/cpuidle/dt_idle_states.c#L208
> >
> >
> > > This script is still being improved.
> >
> > Will corresponding software development challenges become more interesting?
>
> Hello Markus,
> This is the simplified code pattern for it:
>
> 172 for (i = 0; ; i++) {
> 173 state_node = of_parse_phandle(...); ---> Obtain here
> ...
> 177 match_id = of_match_node(matches, state_node);
> 178 if (!match_id) {
> 179 err = -ENODEV;
> 180 break; ---> Jump out of the loop without releasing it
> 181 }
> 182
> 183 if (!of_device_is_available(state_node)) {
> 184 of_node_put(state_node);
> 185 continue; ---> Release the object references within a loop
> 186 }
> ...
> 208 of_node_put(state_node); --> Release the object references within a loop
> 209 }
> 210
> 211 of_node_put(state_node); --> There may be double free here.
>
> This code pattern is very interesting and the coccinelle software should also recognize this pattern.
In my experience, when you start looking at these of_node_put things, all
sorts of strange things appear...
julia
^ permalink raw reply
* Re: [PATCH] powerpc/eeh: Handle hugepages in ioremap space
From: Sachin Sant @ 2019-07-11 7:47 UTC (permalink / raw)
To: Oliver O'Halloran; +Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20190710150517.27114-1-oohall@gmail.com>
> On 10-Jul-2019, at 8:35 PM, Oliver O'Halloran <oohall@gmail.com> wrote:
>
> In commit 4a7b06c157a2 ("powerpc/eeh: Handle hugepages in ioremap
> space") support for using hugepages in the vmalloc and ioremap areas was
> enabled for radix. Unfortunately this broke EEH MMIO error checking.
>
> Detection works by inserting a hook which checks the results of the
> ioreadXX() set of functions. When a read returns a 0xFFs response we
> need to check for an error which we do by mapping the (virtual) MMIO
> address back to a physical address, then mapping physical address to a
> PCI device via an interval tree.
>
> When translating virt -> phys we currently assume the ioremap space is
> only populated by PAGE_SIZE mappings. If a hugepage mapping is found we
> emit a WARN_ON(), but otherwise handles the check as though a normal
> page was found. In pathalogical cases such as copying a buffer
> containing a lot of 0xFFs from BAR memory this can result in the system
> not booting because it's too busy printing WARN_ON()s.
>
> There's no real reason to assume huge pages can't be present and we're
> prefectly capable of handling them, so do that.
>
> Cc: Nicholas Piggin <npiggin@gmail.com>
> Fixes: 4a7b06c157a2 ("powerpc/eeh: Handle hugepages in ioremap space")
> Reported-by: Sachin Sant <sachinp@linux.vnet.ibm.com>
> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Tested-by: Sachin Sant <sachinp@linux.vnet.ibm.com>
Thanks
-Sachin
^ permalink raw reply
* Re: Coccinelle: Checking of_node_put() calls with SmPL
From: Markus Elfring @ 2019-07-11 9:04 UTC (permalink / raw)
To: Wen Yang, linux-pm, kernel-janitors
Cc: Yi Wang, Daniel Lezcano, Rafael J. Wysocki, linux-kernel,
Scott Wood, Julia Lawall, Paul Mackerras, Xue Zhihong,
Cheng Shengyu, linuxppc-dev
In-Reply-To: <201907111435459627761@zte.com.cn>
> 180 break; ---> Jump out of the loop without releasing it
The device node reference is released behind this for loop.
> 183 if (!of_device_is_available(state_node)) {
> 184 of_node_put(state_node);
This function call was added by the commit “cpuidle: dt: Add missing 'of_node_put()'”
on 2017-06-12.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/cpuidle/dt_idle_states.c?id=b2cdd8e1b54849477a32d820acc2e87828a38f3d
> 185 continue; ---> Release the object references within a loop
I became curious on the applicability of an other coding style
(for a software refactoring) at this place.
How do you think about to achieve the same effect by using a goto statement
instead of two statements in such an if branch?
> 208 of_node_put(state_node); --> Release the object references within a loop
> 209 }
> 210
> 211 of_node_put(state_node); --> There may be double free here.
This information points a recurring challenge out for safe source code analysis.
How would you like to exclude the detection of false positives finally?
> This code pattern is very interesting
Thanks that you think also in this direction.
> and the coccinelle software should also recognize this pattern.
There are some open issues to consider for available analysis tools.
How will corresponding details be clarified then?
Regards,
Markus
^ permalink raw reply
* Re: Coccinelle: Checking of_node_put() calls with SmPL
From: Markus Elfring @ 2019-07-11 9:33 UTC (permalink / raw)
To: Julia Lawall, Wen Yang, kernel-janitors
Cc: Yi Wang, linux-pm, Daniel Lezcano, Rafael J. Wysocki,
linux-kernel, Scott Wood, Paul Mackerras, Xue Zhihong,
linuxppc-dev, Cheng Shengyu
In-Reply-To: <alpine.DEB.2.20.1907110845551.3626@hadrien>
> In my experience, when you start looking at these of_node_put things,
> all sorts of strange things appear...
How much will this situation influence the achievement of further improvements
also for your software?
Regards,
Markus
^ permalink raw reply
* Re: [v5 2/6] powerpc/mce: Fix MCE handling for huge pages
From: Nicholas Piggin @ 2019-07-11 9:38 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev, Santosh Sivaraj
Cc: Aneesh Kumar K.V, Mahesh Salgaonkar, Chandan Rajendra, Reza Arbab
In-Reply-To: <20190709121524.18762-3-santosh@fossix.org>
Santosh Sivaraj's on July 9, 2019 10:15 pm:
> From: Balbir Singh <bsingharora@gmail.com>
>
> The current code would fail on huge pages addresses, since the shift
> would be incorrect. Use the correct page shift value returned by
> __find_linux_pte() to get the correct pfn. The code is more generic
> and can handle both regular and compound pages.
>
> Fixes: ba41e1e1ccb9 ("powerpc/mce: Hookup derror (load/store) UE errors")
>
> Signed-off-by: Balbir Singh <bsingharora@gmail.com>
> [arbab@linux.ibm.com: Fixup pseries_do_memory_failure()]
> Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
> Signed-off-by: Santosh Sivaraj <santosh@fossix.org>
> ---
> arch/powerpc/include/asm/mce.h | 3 ++-
> arch/powerpc/kernel/mce_power.c | 26 ++++++++++++++++----------
> arch/powerpc/platforms/pseries/ras.c | 6 ++++--
> 3 files changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mce.h b/arch/powerpc/include/asm/mce.h
> index a4c6a74ad2fb..94888a7025b3 100644
> --- a/arch/powerpc/include/asm/mce.h
> +++ b/arch/powerpc/include/asm/mce.h
> @@ -209,7 +209,8 @@ extern void release_mce_event(void);
> extern void machine_check_queue_event(void);
> extern void machine_check_print_event_info(struct machine_check_event *evt,
> bool user_mode, bool in_guest);
> -unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr);
> +unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr,
> + unsigned int *shift);
> #ifdef CONFIG_PPC_BOOK3S_64
> void flush_and_reload_slb(void);
> #endif /* CONFIG_PPC_BOOK3S_64 */
> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
> index e39536aad30d..04666c0b40a8 100644
> --- a/arch/powerpc/kernel/mce_power.c
> +++ b/arch/powerpc/kernel/mce_power.c
> @@ -23,7 +23,8 @@
> * Convert an address related to an mm to a PFN. NOTE: we are in real
> * mode, we could potentially race with page table updates.
> */
> -unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
> +unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr,
> + unsigned int *shift)
> {
> pte_t *ptep;
> unsigned long flags;
> @@ -36,13 +37,15 @@ unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
>
> local_irq_save(flags);
> if (mm == current->mm)
> - ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
> + ptep = find_current_mm_pte(mm->pgd, addr, NULL, shift);
> else
> - ptep = find_init_mm_pte(addr, NULL);
> + ptep = find_init_mm_pte(addr, shift);
> local_irq_restore(flags);
> if (!ptep || pte_special(*ptep))
> return ULONG_MAX;
> - return pte_pfn(*ptep);
> + if (!*shift)
> + *shift = PAGE_SHIFT;
> + return (pte_val(*ptep) & PTE_RPN_MASK) >> *shift;
> }
>
> /* flush SLBs and reload */
Ah, the comment I made earlier to this patch I think missed some detail.
But what we should do here is return the pfn (which is always units
of PAGE_SIZE). So you have to adjust by the lower part of the address
here, rather than returning shift which is unnecessary.
Possibly even better is to just return the real address, which is
what all callers seem to want anyway.
> @@ -358,15 +361,16 @@ static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
> unsigned long pfn, instr_addr;
> struct instruction_op op;
> struct pt_regs tmp = *regs;
> + unsigned int shift;
>
> - pfn = addr_to_pfn(regs, regs->nip);
> + pfn = addr_to_pfn(regs, regs->nip, &shift);
> if (pfn != ULONG_MAX) {
> - instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
> + instr_addr = (pfn << shift) + (regs->nip & ((1 << shift) - 1));
This wants the exact real address.
> instr = *(unsigned int *)(instr_addr);
> if (!analyse_instr(&op, &tmp, instr)) {
> - pfn = addr_to_pfn(regs, op.ea);
> + pfn = addr_to_pfn(regs, op.ea, &shift);
> *addr = op.ea;
> - *phys_addr = (pfn << PAGE_SHIFT);
> + *phys_addr = (pfn << shift);
> return 0;
> }
I'm not sure this is really what we want. You do really want the
PAGE_SIZE pfn here. Say you have a failure in the nth small page
of a large page mapping, this gives the physical address of the
start of the large page, so memory failure will fail out the 0th
small page won't it?
> /*
> @@ -442,12 +446,14 @@ static int mce_handle_ierror(struct pt_regs *regs,
> if (mce_err->sync_error &&
> table[i].error_type == MCE_ERROR_TYPE_UE) {
> unsigned long pfn;
> + unsigned int shift;
>
> if (get_paca()->in_mce < MAX_MCE_DEPTH) {
> - pfn = addr_to_pfn(regs, regs->nip);
> + pfn = addr_to_pfn(regs, regs->nip,
> + &shift);
> if (pfn != ULONG_MAX) {
> *phys_addr =
> - (pfn << PAGE_SHIFT);
> + (pfn << shift);
> }
> }
> }
> diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
> index f16fdd0f71f7..5e43283d3300 100644
> --- a/arch/powerpc/platforms/pseries/ras.c
> +++ b/arch/powerpc/platforms/pseries/ras.c
> @@ -740,12 +740,14 @@ static void pseries_do_memory_failure(struct pt_regs *regs,
> paddr = be64_to_cpu(mce_log->logical_address);
> } else if (mce_log->sub_err_type & UE_EFFECTIVE_ADDR_PROVIDED) {
> unsigned long pfn;
> + unsigned int shift;
>
> pfn = addr_to_pfn(regs,
> - be64_to_cpu(mce_log->effective_address));
> + be64_to_cpu(mce_log->effective_address),
> + &shift);
> if (pfn == ULONG_MAX)
> return;
> - paddr = pfn << PAGE_SHIFT;
> + paddr = pfn << shift;
> } else {
> return;
> }
Same for all these.
Thanks,
Nick
^ permalink raw reply
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