* Re: [PATCH v6 08/10] mm/memory_hotplug: Don't check for "all holes" in shrink_zone_span()
From: David Hildenbrand @ 2020-02-04 14:42 UTC (permalink / raw)
To: Baoquan He
Cc: linux-s390, Michal Hocko, linux-ia64, Pavel Tatashin, linux-sh,
x86, linux-kernel, linux-mm, Wei Yang, Andrew Morton,
linuxppc-dev, Dan Williams, linux-arm-kernel, Oscar Salvador
In-Reply-To: <20200204142516.GD26758@MiWiFi-R3L-srv>
On 04.02.20 15:25, Baoquan He wrote:
> On 10/06/19 at 10:56am, David Hildenbrand wrote:
>> If we have holes, the holes will automatically get detected and removed
>> once we remove the next bigger/smaller section. The extra checks can
>> go.
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Oscar Salvador <osalvador@suse.de>
>> Cc: Michal Hocko <mhocko@suse.com>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Pavel Tatashin <pasha.tatashin@soleen.com>
>> Cc: Dan Williams <dan.j.williams@intel.com>
>> Cc: Wei Yang <richardw.yang@linux.intel.com>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> mm/memory_hotplug.c | 34 +++++++---------------------------
>> 1 file changed, 7 insertions(+), 27 deletions(-)
>>
>> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
>> index f294918f7211..8dafa1ba8d9f 100644
>> --- a/mm/memory_hotplug.c
>> +++ b/mm/memory_hotplug.c
>> @@ -393,6 +393,9 @@ static void shrink_zone_span(struct zone *zone, unsigned long start_pfn,
>> if (pfn) {
>> zone->zone_start_pfn = pfn;
>> zone->spanned_pages = zone_end_pfn - pfn;
>> + } else {
>> + zone->zone_start_pfn = 0;
>> + zone->spanned_pages = 0;
>> }
>> } else if (zone_end_pfn == end_pfn) {
>> /*
>> @@ -405,34 +408,11 @@ static void shrink_zone_span(struct zone *zone, unsigned long start_pfn,
>> start_pfn);
>> if (pfn)
>> zone->spanned_pages = pfn - zone_start_pfn + 1;
>> + else {
>> + zone->zone_start_pfn = 0;
>> + zone->spanned_pages = 0;
>
> Thinking in which case (zone_start_pfn != start_pfn) and it comes here.
Could only happen in case the zone_start_pfn would have been "out of the
zone already". If you ask me: unlikely :)
This change at least maintains the same result as before (where the
all-holes check would have caught it).
--
Thanks,
David / dhildenb
^ permalink raw reply
* Re: [PATCH] libnvdimm/of_pmem: Fix leaking bus_desc.provider_name in some paths
From: Aneesh Kumar K.V @ 2020-02-04 15:29 UTC (permalink / raw)
To: Vaibhav Jain, linuxppc-dev, linux-nvdimm; +Cc: Vaibhav Jain, stable
In-Reply-To: <20200123031847.149325-1-vaibhav@linux.ibm.com>
Vaibhav Jain <vaibhav@linux.ibm.com> writes:
> String 'bus_desc.provider_name' allocated inside
> of_pmem_region_probe() will leak in case call to nvdimm_bus_register()
> fails or when of_pmem_region_remove() is called.
>
> This minor patch ensures that 'bus_desc.provider_name' is freed in
> error path for of_pmem_region_probe() as well as in
> of_pmem_region_remove().
>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> Cc: stable@vger.kernel.org
> Fixes:49bddc73d15c2("libnvdimm/of_pmem: Provide a unique name for bus provider")
> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
> ---
> drivers/nvdimm/of_pmem.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/nvdimm/of_pmem.c b/drivers/nvdimm/of_pmem.c
> index 8224d1431ea9..9cb76f9837ad 100644
> --- a/drivers/nvdimm/of_pmem.c
> +++ b/drivers/nvdimm/of_pmem.c
> @@ -36,6 +36,7 @@ static int of_pmem_region_probe(struct platform_device *pdev)
>
> priv->bus = bus = nvdimm_bus_register(&pdev->dev, &priv->bus_desc);
> if (!bus) {
> + kfree(priv->bus_desc.provider_name);
> kfree(priv);
> return -ENODEV;
> }
> @@ -81,6 +82,7 @@ static int of_pmem_region_remove(struct platform_device *pdev)
> struct of_pmem_private *priv = platform_get_drvdata(pdev);
>
> nvdimm_bus_unregister(priv->bus);
> + kfree(priv->bus_desc.provider_name);
> kfree(priv);
>
> return 0;
> --
> 2.24.1
> _______________________________________________
> Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org
> To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
^ permalink raw reply
* Re: [PATCH] powerpc/drmem: cache LMBs in xarray to accelerate lookup
From: Scott Cheloha @ 2020-02-04 16:19 UTC (permalink / raw)
To: Nathan Lynch; +Cc: Nathan Fontenont, linuxppc-dev, linux-kernel, Rick Lindsley
In-Reply-To: <87pnf3i188.fsf@linux.ibm.com>
On Tue, Jan 28, 2020 at 05:56:55PM -0600, Nathan Lynch wrote:
> Scott Cheloha <cheloha@linux.ibm.com> writes:
> > LMB lookup is currently an O(n) linear search. This scales poorly when
> > there are many LMBs.
> >
> > If we cache each LMB by both its base address and its DRC index
> > in an xarray we can cut lookups to O(log n), greatly accelerating
> > drmem initialization and memory hotplug.
> >
> > This patch introduces two xarrays of of LMBs and fills them during
> > drmem initialization. The patch also adds two interfaces for LMB
> > lookup.
>
> Good but can you replace the array of LMBs altogether
> (drmem_info->lmbs)? xarray allows iteration over the members if needed.
I would like to try to "solve one problem at a time".
We can fix the linear search performance scaling problems without
removing the array of LMBs. As I've shown in my diff, we can do it
with minimal change to the existing code.
If it turns out that the PAPR guarantees the ordering of the memory
DRCs then in a subsequent patch (series) we can replace the LMB array
(__drmem_info.lmbs) with an xarray indexed by DRC and use e.g.
xa_for_each() in the hotplug code.
^ permalink raw reply
* Re: [PATCH v6 08/10] mm/memory_hotplug: Don't check for "all holes" in shrink_zone_span()
From: Baoquan He @ 2020-02-04 14:25 UTC (permalink / raw)
To: David Hildenbrand
Cc: linux-s390, Michal Hocko, linux-ia64, Pavel Tatashin, linux-sh,
x86, linux-kernel, linux-mm, Wei Yang, Andrew Morton,
linuxppc-dev, Dan Williams, linux-arm-kernel, Oscar Salvador
In-Reply-To: <20191006085646.5768-9-david@redhat.com>
On 10/06/19 at 10:56am, David Hildenbrand wrote:
> If we have holes, the holes will automatically get detected and removed
> once we remove the next bigger/smaller section. The extra checks can
> go.
>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Oscar Salvador <osalvador@suse.de>
> Cc: Michal Hocko <mhocko@suse.com>
> Cc: David Hildenbrand <david@redhat.com>
> Cc: Pavel Tatashin <pasha.tatashin@soleen.com>
> Cc: Dan Williams <dan.j.williams@intel.com>
> Cc: Wei Yang <richardw.yang@linux.intel.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> mm/memory_hotplug.c | 34 +++++++---------------------------
> 1 file changed, 7 insertions(+), 27 deletions(-)
>
> diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
> index f294918f7211..8dafa1ba8d9f 100644
> --- a/mm/memory_hotplug.c
> +++ b/mm/memory_hotplug.c
> @@ -393,6 +393,9 @@ static void shrink_zone_span(struct zone *zone, unsigned long start_pfn,
> if (pfn) {
> zone->zone_start_pfn = pfn;
> zone->spanned_pages = zone_end_pfn - pfn;
> + } else {
> + zone->zone_start_pfn = 0;
> + zone->spanned_pages = 0;
> }
> } else if (zone_end_pfn == end_pfn) {
> /*
> @@ -405,34 +408,11 @@ static void shrink_zone_span(struct zone *zone, unsigned long start_pfn,
> start_pfn);
> if (pfn)
> zone->spanned_pages = pfn - zone_start_pfn + 1;
> + else {
> + zone->zone_start_pfn = 0;
> + zone->spanned_pages = 0;
Thinking in which case (zone_start_pfn != start_pfn) and it comes here.
> + }
> }
> -
> - /*
> - * The section is not biggest or smallest mem_section in the zone, it
> - * only creates a hole in the zone. So in this case, we need not
> - * change the zone. But perhaps, the zone has only hole data. Thus
> - * it check the zone has only hole or not.
> - */
> - pfn = zone_start_pfn;
> - for (; pfn < zone_end_pfn; pfn += PAGES_PER_SUBSECTION) {
> - if (unlikely(!pfn_to_online_page(pfn)))
> - continue;
> -
> - if (page_zone(pfn_to_page(pfn)) != zone)
> - continue;
> -
> - /* Skip range to be removed */
> - if (pfn >= start_pfn && pfn < end_pfn)
> - continue;
> -
> - /* If we find valid section, we have nothing to do */
> - zone_span_writeunlock(zone);
> - return;
> - }
> -
> - /* The zone has no valid section */
> - zone->zone_start_pfn = 0;
> - zone->spanned_pages = 0;
> zone_span_writeunlock(zone);
> }
>
> --
> 2.21.0
>
>
^ permalink raw reply
* [PATCH] powerpc/vdso32: mark __kernel_datapage_offset as STV_PROTECTED
From: Fangrui Song @ 2020-02-05 0:50 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman,
Christophe Leroy
Cc: clang-built-linux, linuxppc-dev, linux-kernel, Fangrui Song
A PC-relative relocation (R_PPC_REL16_LO in this case) referencing a
preemptible symbol in a -shared link is not allowed. GNU ld's powerpc
port is permissive and allows it [1], but lld will report an error after
https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=ec0895f08f99515194e9fcfe1338becf6f759d38
Make the symbol protected so that it is non-preemptible but still
exported.
[1]: https://sourceware.org/bugzilla/show_bug.cgi?id=25500
Link: https://github.com/ClangBuiltLinux/linux/issues/851
Signed-off-by: Fangrui Song <maskray@google.com>
---
arch/powerpc/kernel/vdso32/datapage.S | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/vdso32/datapage.S b/arch/powerpc/kernel/vdso32/datapage.S
index 217bb630f8f9..2831a8676365 100644
--- a/arch/powerpc/kernel/vdso32/datapage.S
+++ b/arch/powerpc/kernel/vdso32/datapage.S
@@ -13,7 +13,8 @@
#include <asm/vdso_datapage.h>
.text
- .global __kernel_datapage_offset;
+ .global __kernel_datapage_offset
+ .protected __kernel_datapage_offset
__kernel_datapage_offset:
.long 0
--
2.25.0.341.g760bfbb309-goog
^ permalink raw reply related
* Re: [RFC] per-CPU usage in perf core-book3s
From: maddy @ 2020-02-05 1:40 UTC (permalink / raw)
To: Sebastian Andrzej Siewior, linux-kernel, linuxppc-dev
Cc: Mark Rutland, Peter Zijlstra, Arnaldo Carvalho de Melo,
Alexander Shishkin, Ingo Molnar, Paul Mackerras, Namhyung Kim,
Thomas Gleixner, Jiri Olsa
In-Reply-To: <20200127150620.taio2txyqreg4kn6@linutronix.de>
On 1/27/20 8:36 PM, Sebastian Andrzej Siewior wrote:
> I've been looking at usage of per-CPU variable cpu_hw_events in
> arch/powerpc/perf/core-book3s.c.
>
> power_pmu_enable() and power_pmu_disable() (pmu::pmu_enable() and
> pmu::pmu_disable()) are accessing the variable and the callbacks are
> invoked always with disabled interrupts.
>
> power_pmu_event_init() (pmu::event_init()) is invoked from preemptible
> context and uses get_cpu_var() to obtain a stable pointer (by disabling
> preemption).
>
> pmu::pmu_enable() and pmu::pmu_disable() can be invoked via a hrtimer
> (perf_mux_hrtimer_handler()) and it invokes pmu::pmu_enable() and
> pmu::pmu_disable() as part of the callback.
>
> Is there anything that prevents the timer callback to interrupt
> pmu::event_init() while it is accessing per-CPU data?
Sorry for the delayed response.
Yes, currently we dont have anything that prevents the timer
callback to interrupt pmu::event_init. Nice catch. Thanks for
pointing this out.
Looking at the code, per-cpu variable access are made to
check for constraints and for Branch Stack (BHRB). So could
wrap this block of pmu::event_init with local_irq_save/restore.
Will send a patch to fix it.
Maddy
>
> Sebastian
^ permalink raw reply
* Re: [PATCH 2/5] mm/memremap_pages: Introduce memremap_compat_align()
From: Michael Ellerman @ 2020-02-05 3:05 UTC (permalink / raw)
To: Dan Williams, linux-nvdimm
Cc: Aneesh Kumar K.V, linux-kernel, Jeff Moyer, Paul Mackerras,
vishal.l.verma, linuxppc-dev, hch
In-Reply-To: <158041476763.3889308.13149849631980018039.stgit@dwillia2-desk3.amr.corp.intel.com>
Dan Williams <dan.j.williams@intel.com> writes:
> The "sub-section memory hotplug" facility allows memremap_pages() users
> like libnvdimm to compensate for hardware platforms like x86 that have a
> section size larger than their hardware memory mapping granularity. The
> compensation that sub-section support affords is being tolerant of
> physical memory resources shifting by units smaller (64MiB on x86) than
> the memory-hotplug section size (128 MiB). Where the platform
> physical-memory mapping granularity is limited by the number and
> capability of address-decode-registers in the memory controller.
>
> While the sub-section support allows memremap_pages() to operate on
> sub-section (2MiB) granularity, the Power architecture may still
> require 16MiB alignment on "!radix_enabled()" platforms.
>
> In order for libnvdimm to be able to detect and manage this per-arch
> limitation, introduce memremap_compat_align() as a common minimum
> alignment across all driver-facing memory-mapping interfaces, and let
> Power override it to 16MiB in the "!radix_enabled()" case.
>
> The assumption / requirement for 16MiB to be a viable
> memremap_compat_align() value is that Power does not have platforms
> where its equivalent of address-decode-registers never hardware remaps a
> persistent memory resource on smaller than 16MiB boundaries.
>
> Based on an initial patch by Aneesh.
>
> Link: http://lore.kernel.org/r/CAPcyv4gBGNP95APYaBcsocEa50tQj9b5h__83vgngjq3ouGX_Q@mail.gmail.com
> Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> Reported-by: Jeff Moyer <jmoyer@redhat.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> arch/powerpc/include/asm/io.h | 10 ++++++++++
> drivers/nvdimm/pfn_devs.c | 2 +-
> include/linux/io.h | 23 +++++++++++++++++++++++
> include/linux/mmzone.h | 1 +
> 4 files changed, 35 insertions(+), 1 deletion(-)
The powerpc change here looks fine to me.
Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
cheers
> diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
> index a63ec938636d..0fa2dc483008 100644
> --- a/arch/powerpc/include/asm/io.h
> +++ b/arch/powerpc/include/asm/io.h
> @@ -734,6 +734,16 @@ extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
> unsigned long size, pgprot_t prot);
> extern void __iounmap_at(void *ea, unsigned long size);
>
> +#ifdef CONFIG_SPARSEMEM
> +static inline unsigned long memremap_compat_align(void)
> +{
> + if (radix_enabled())
> + return SUBSECTION_SIZE;
> + return (1UL << mmu_psize_defs[mmu_linear_psize].shift);
> +}
> +#define memremap_compat_align memremap_compat_align
> +#endif
> +
> /*
> * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
> * which needs some additional definitions here. They basically allow PIO
^ permalink raw reply
* [PATCH v2 4/6] powerpc/fsl_booke/64: do not clear the BSS for the second pass
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
The BSS section has already cleared out in the first pass. No need to
clear it again. This can save some time when booting with KASLR
enabled.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
arch/powerpc/kernel/head_64.S | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index b4ececc4323d..9ae7fd8bbf7c 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -914,6 +914,13 @@ start_here_multiplatform:
bl relative_toc
tovirt(r2,r2)
+ /* Do not clear the BSS for the second pass if randomized */
+ LOAD_REG_ADDR(r3, kernstart_virt_addr)
+ lwz r3,0(r3)
+ LOAD_REG_IMMEDIATE(r4, KERNELBASE)
+ cmpw r3,r4
+ bne 4f
+
/* Clear out the BSS. It may have been done in prom_init,
* already but that's irrelevant since prom_init will soon
* be detached from the kernel completely. Besides, we need
--
2.17.2
^ permalink raw reply related
* [PATCH v2 0/6] implement KASLR for powerpc/fsl_booke/64
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
This is a try to implement KASLR for Freescale BookE64 which is based on
my earlier implementation for Freescale BookE32:
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=131718
The implementation for Freescale BookE64 is similar as BookE32. One
difference is that Freescale BookE64 set up a TLB mapping of 1G during
booting. Another difference is that ppc64 needs the kernel to be
64K-aligned. So we can randomize the kernel in this 1G mapping and make
it 64K-aligned. This can save some code to creat another TLB map at
early boot. The disadvantage is that we only have about 1G/64K = 16384
slots to put the kernel in.
KERNELBASE
64K |--> kernel <--|
| | |
+--+--+--+ +--+--+--+--+--+--+--+--+--+ +--+--+
| | | |....| | | | | | | | | |....| | |
+--+--+--+ +--+--+--+--+--+--+--+--+--+ +--+--+
| | 1G
|-----> offset <-----|
kernstart_virt_addr
I'm not sure if the slot numbers is enough or the design has any
defects. If you have some better ideas, I would be happy to hear that.
Thank you all.
v1->v2:
Add __kaslr_offset for the secondary cpu boot up.
Jason Yan (6):
powerpc/fsl_booke/kaslr: refactor kaslr_legal_offset() and
kaslr_early_init()
powerpc/fsl_booke/64: introduce reloc_kernel_entry() helper
powerpc/fsl_booke/64: implement KASLR for fsl_booke64
powerpc/fsl_booke/64: do not clear the BSS for the second pass
powerpc/fsl_booke/64: clear the original kernel if randomized
powerpc/fsl_booke/kaslr: rename kaslr-booke32.rst to kaslr-booke.rst
and add 64bit part
.../{kaslr-booke32.rst => kaslr-booke.rst} | 35 +++++++--
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/exceptions-64e.S | 21 ++++++
arch/powerpc/kernel/head_64.S | 14 ++++
arch/powerpc/kernel/setup_64.c | 4 +-
arch/powerpc/mm/mmu_decl.h | 3 +-
arch/powerpc/mm/nohash/kaslr_booke.c | 71 +++++++++++++------
7 files changed, 122 insertions(+), 28 deletions(-)
rename Documentation/powerpc/{kaslr-booke32.rst => kaslr-booke.rst} (59%)
--
2.17.2
^ permalink raw reply
* [PATCH v2 3/6] powerpc/fsl_booke/64: implement KASLR for fsl_booke64
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
The implementation for Freescale BookE64 is similar as BookE32. One
difference is that Freescale BookE64 set up a TLB mapping of 1G during
booting. Another difference is that ppc64 needs the kernel to be
64K-aligned. So we can randomize the kernel in this 1G mapping and make
it 64K-aligned. This can save some code to creat another TLB map at
early boot. The disadvantage is that we only have about 1G/64K = 16384
slots to put the kernel in.
To support secondary cpu boot up, a variable __kaslr_offset was added in
first_256B section. This can help secondary cpu get the kaslr offset
before the 1:1 mapping has been setup.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/kernel/exceptions-64e.S | 8 +++++++
arch/powerpc/kernel/head_64.S | 7 ++++++
arch/powerpc/kernel/setup_64.c | 4 +++-
arch/powerpc/mm/nohash/kaslr_booke.c | 33 +++++++++++++++++++++++++---
5 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c150a9d49343..754aeb96bb1c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -568,7 +568,7 @@ config RELOCATABLE
config RANDOMIZE_BASE
bool "Randomize the address of the kernel image"
- depends on (FSL_BOOKE && FLATMEM && PPC32)
+ depends on (PPC_FSL_BOOK3E && FLATMEM)
depends on RELOCATABLE
help
Randomizes the virtual address at which the kernel image is
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 1b9b174bee86..121daeaf573d 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -1378,6 +1378,7 @@ skpinv: addi r6,r6,1 /* Increment */
1: mflr r6
addi r6,r6,(2f - 1b)
tovirt(r6,r6)
+ add r6,r6,r19
lis r7,MSR_KERNEL@h
ori r7,r7,MSR_KERNEL@l
mtspr SPRN_SRR0,r6
@@ -1400,6 +1401,7 @@ skpinv: addi r6,r6,1 /* Increment */
/* We translate LR and return */
tovirt(r8,r8)
+ add r8,r8,r19
mtlr r8
blr
@@ -1528,6 +1530,7 @@ a2_tlbinit_code_end:
*/
_GLOBAL(start_initialization_book3e)
mflr r28
+ li r19, 0
/* First, we need to setup some initial TLBs to map the kernel
* text, data and bss at PAGE_OFFSET. We don't have a real mode
@@ -1570,6 +1573,10 @@ _GLOBAL(book3e_secondary_core_init)
cmplwi r4,0
bne 2f
+ LOAD_REG_ADDR_PIC(r19, __kaslr_offset)
+ lwz r19,0(r19)
+ rlwinm r19,r19,0,0,5
+
/* Setup TLB for this core */
bl initial_tlb_book3e
@@ -1602,6 +1609,7 @@ _GLOBAL(book3e_secondary_core_init)
lis r3,PAGE_OFFSET@highest
sldi r3,r3,32
or r28,r28,r3
+ add r28,r28,r19
1: mtlr r28
blr
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index ad79fddb974d..b4ececc4323d 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -104,6 +104,13 @@ __secondary_hold_acknowledge:
.8byte 0x0
#ifdef CONFIG_RELOCATABLE
+#ifdef CONFIG_PPC_BOOK3E
+ . = 0x58
+ .globl __kaslr_offset
+__kaslr_offset:
+DEFINE_FIXED_SYMBOL(__kaslr_offset)
+ .long 0
+#endif
/* This flag is set to 1 by a loader if the kernel should run
* at the loaded address instead of the linked address. This
* is used by kexec-tools to keep the the kdump kernel in the
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index 6104917a282d..a16b970a8d1a 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -66,7 +66,7 @@
#include <asm/feature-fixups.h>
#include <asm/kup.h>
#include <asm/early_ioremap.h>
-
+#include <mm/mmu_decl.h>
#include "setup.h"
int spinning_secondaries;
@@ -300,6 +300,8 @@ void __init early_setup(unsigned long dt_ptr)
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
+ kaslr_early_init(__va(dt_ptr), 0);
+
udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
/*
diff --git a/arch/powerpc/mm/nohash/kaslr_booke.c b/arch/powerpc/mm/nohash/kaslr_booke.c
index 07b036e98353..c6f5c1db1394 100644
--- a/arch/powerpc/mm/nohash/kaslr_booke.c
+++ b/arch/powerpc/mm/nohash/kaslr_booke.c
@@ -231,7 +231,7 @@ static __init unsigned long get_usable_address(const void *fdt,
unsigned long pa;
unsigned long pa_end;
- for (pa = offset; (long)pa > (long)start; pa -= SZ_16K) {
+ for (pa = offset; (long)pa > (long)start; pa -= SZ_64K) {
pa_end = pa + regions.kernel_size;
if (overlaps_region(fdt, pa, pa_end))
continue;
@@ -265,14 +265,14 @@ static unsigned long __init kaslr_legal_offset(void *dt_ptr, unsigned long rando
{
unsigned long koffset = 0;
unsigned long start;
- unsigned long index;
unsigned long offset;
+#ifdef CONFIG_PPC32
/*
* Decide which 64M we want to start
* Only use the low 8 bits of the random seed
*/
- index = random & 0xFF;
+ unsigned long index = random & 0xFF;
index %= regions.linear_sz / SZ_64M;
/* Decide offset inside 64M */
@@ -287,6 +287,15 @@ static unsigned long __init kaslr_legal_offset(void *dt_ptr, unsigned long rando
break;
index--;
}
+#else
+ /* Decide kernel offset inside 1G */
+ offset = random % (SZ_1G - regions.kernel_size);
+ offset = round_down(offset, SZ_64K);
+
+ start = memstart_addr;
+ offset = memstart_addr + offset;
+ koffset = get_usable_address(dt_ptr, start, offset);
+#endif
if (koffset != 0)
koffset -= memstart_addr;
@@ -325,6 +334,7 @@ static unsigned long __init kaslr_choose_location(void *dt_ptr, phys_addr_t size
else
pr_warn("KASLR: No safe seed for randomizing the kernel base.\n");
+#ifdef CONFIG_PPC32
ram = min_t(phys_addr_t, __max_low_memory, size);
ram = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM, true);
linear_sz = min_t(unsigned long, ram, SZ_512M);
@@ -332,6 +342,7 @@ static unsigned long __init kaslr_choose_location(void *dt_ptr, phys_addr_t size
/* If the linear size is smaller than 64M, do not randmize */
if (linear_sz < SZ_64M)
return 0;
+#endif
/* check for a reserved-memory node and record its cell sizes */
regions.reserved_mem = fdt_path_offset(dt_ptr, "/reserved-memory");
@@ -363,6 +374,17 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
unsigned long offset;
unsigned long kernel_sz;
+#ifdef CONFIG_PPC64
+ unsigned int *__kaslr_offset = (unsigned int *)(KERNELBASE + 0x58);
+ unsigned int *__run_at_load = (unsigned int *)(KERNELBASE + 0x5c);
+
+ if (*__run_at_load == 1)
+ return;
+
+ /* Setup flat device-tree pointer */
+ initial_boot_params = dt_ptr;
+#endif
+
kernel_sz = (unsigned long)_end - (unsigned long)_stext;
offset = kaslr_choose_location(dt_ptr, size, kernel_sz);
@@ -372,6 +394,7 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
kernstart_virt_addr += offset;
kernstart_addr += offset;
+#ifdef CONFIG_PPC32
is_second_reloc = 1;
if (offset >= SZ_64M) {
@@ -381,6 +404,10 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
/* Create kernel map to relocate in */
create_kaslr_tlb_entry(1, tlb_virt, tlb_phys);
}
+#else
+ *__kaslr_offset = kernstart_virt_addr - KERNELBASE;
+ *__run_at_load = 1;
+#endif
/* Copy the kernel to it's new location and run */
memcpy((void *)kernstart_virt_addr, (void *)_stext, kernel_sz);
--
2.17.2
^ permalink raw reply related
* [PATCH v2 2/6] powerpc/fsl_booke/64: introduce reloc_kernel_entry() helper
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
Like the 32bit code, we introduce reloc_kernel_entry() helper to prepare
for the KASLR 64bit version. And move the C declaration of this function
out of CONFIG_PPC32 and use long instead of int for the parameter 'addr'.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
arch/powerpc/kernel/exceptions-64e.S | 13 +++++++++++++
arch/powerpc/mm/mmu_decl.h | 3 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index e4076e3c072d..1b9b174bee86 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -1679,3 +1679,16 @@ _GLOBAL(setup_ehv_ivors)
_GLOBAL(setup_lrat_ivor)
SET_IVOR(42, 0x340) /* LRAT Error */
blr
+
+/*
+ * Return to the start of the relocated kernel and run again
+ * r3 - virtual address of fdt
+ * r4 - entry of the kernel
+ */
+_GLOBAL(reloc_kernel_entry)
+ mfmsr r7
+ rlwinm r7, r7, 0, ~(MSR_IS | MSR_DS)
+
+ mtspr SPRN_SRR0,r4
+ mtspr SPRN_SRR1,r7
+ rfi
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 8e99649c24fc..3e1c85c7d10b 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -140,9 +140,10 @@ extern void adjust_total_lowmem(void);
extern int switch_to_as1(void);
extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
void create_kaslr_tlb_entry(int entry, unsigned long virt, phys_addr_t phys);
-void reloc_kernel_entry(void *fdt, int addr);
extern int is_second_reloc;
#endif
+
+void reloc_kernel_entry(void *fdt, long addr);
extern void loadcam_entry(unsigned int index);
extern void loadcam_multi(int first_idx, int num, int tmp_idx);
--
2.17.2
^ permalink raw reply related
* [PATCH v2 5/6] powerpc/fsl_booke/64: clear the original kernel if randomized
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
The original kernel still exists in the memory, clear it now.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
arch/powerpc/mm/nohash/kaslr_booke.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/mm/nohash/kaslr_booke.c b/arch/powerpc/mm/nohash/kaslr_booke.c
index c6f5c1db1394..ed1277059368 100644
--- a/arch/powerpc/mm/nohash/kaslr_booke.c
+++ b/arch/powerpc/mm/nohash/kaslr_booke.c
@@ -378,8 +378,10 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
unsigned int *__kaslr_offset = (unsigned int *)(KERNELBASE + 0x58);
unsigned int *__run_at_load = (unsigned int *)(KERNELBASE + 0x5c);
- if (*__run_at_load == 1)
+ if (*__run_at_load == 1) {
+ kaslr_late_init();
return;
+ }
/* Setup flat device-tree pointer */
initial_boot_params = dt_ptr;
--
2.17.2
^ permalink raw reply related
* [PATCH v2 6/6] powerpc/fsl_booke/kaslr: rename kaslr-booke32.rst to kaslr-booke.rst and add 64bit part
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
Now we support both 32 and 64 bit KASLR for fsl booke. Add document for
64 bit part and rename kaslr-booke32.rst to kaslr-booke.rst.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
.../{kaslr-booke32.rst => kaslr-booke.rst} | 35 ++++++++++++++++---
1 file changed, 31 insertions(+), 4 deletions(-)
rename Documentation/powerpc/{kaslr-booke32.rst => kaslr-booke.rst} (59%)
diff --git a/Documentation/powerpc/kaslr-booke32.rst b/Documentation/powerpc/kaslr-booke.rst
similarity index 59%
rename from Documentation/powerpc/kaslr-booke32.rst
rename to Documentation/powerpc/kaslr-booke.rst
index 8b259fdfdf03..42121fed8249 100644
--- a/Documentation/powerpc/kaslr-booke32.rst
+++ b/Documentation/powerpc/kaslr-booke.rst
@@ -1,15 +1,18 @@
.. SPDX-License-Identifier: GPL-2.0
-===========================
-KASLR for Freescale BookE32
-===========================
+=========================
+KASLR for Freescale BookE
+=========================
The word KASLR stands for Kernel Address Space Layout Randomization.
This document tries to explain the implementation of the KASLR for
-Freescale BookE32. KASLR is a security feature that deters exploit
+Freescale BookE. KASLR is a security feature that deters exploit
attempts relying on knowledge of the location of kernel internals.
+KASLR for Freescale BookE32
+-------------------------
+
Since CONFIG_RELOCATABLE has already supported, what we need to do is
map or copy kernel to a proper place and relocate. Freescale Book-E
parts expect lowmem to be mapped by fixed TLB entries(TLB1). The TLB1
@@ -38,5 +41,29 @@ bit of the entropy to decide the index of the 64M zone. Then we chose a
kernstart_virt_addr
+
+KASLR for Freescale BookE64
+---------------------------
+
+The implementation for Freescale BookE64 is similar as BookE32. One
+difference is that Freescale BookE64 set up a TLB mapping of 1G during
+booting. Another difference is that ppc64 needs the kernel to be
+64K-aligned. So we can randomize the kernel in this 1G mapping and make
+it 64K-aligned. This can save some code to creat another TLB map at early
+boot. The disadvantage is that we only have about 1G/64K = 16384 slots to
+put the kernel in::
+
+ KERNELBASE
+
+ 64K |--> kernel <--|
+ | | |
+ +--+--+--+ +--+--+--+--+--+--+--+--+--+ +--+--+
+ | | | |....| | | | | | | | | |....| | |
+ +--+--+--+ +--+--+--+--+--+--+--+--+--+ +--+--+
+ | | 1G
+ |-----> offset <-----|
+
+ kernstart_virt_addr
+
To enable KASLR, set CONFIG_RANDOMIZE_BASE = y. If KASLR is enable and you
want to disable it at runtime, add "nokaslr" to the kernel cmdline.
--
2.17.2
^ permalink raw reply related
* [PATCH v2 1/6] powerpc/fsl_booke/kaslr: refactor kaslr_legal_offset() and kaslr_early_init()
From: Jason Yan @ 2020-02-05 2:55 UTC (permalink / raw)
To: mpe, linuxppc-dev, diana.craciun, christophe.leroy, benh, paulus,
npiggin, keescook, kernel-hardening, oss
Cc: Jason Yan, linux-kernel, zhaohongjiang
In-Reply-To: <20200205025527.28640-1-yanaijie@huawei.com>
Some code refactor in kaslr_legal_offset() and kaslr_early_init(). No
functional change. This is a preparation for KASLR fsl_booke64.
Signed-off-by: Jason Yan <yanaijie@huawei.com>
Cc: Scott Wood <oss@buserror.net>
Cc: Diana Craciun <diana.craciun@nxp.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Nicholas Piggin <npiggin@gmail.com>
Cc: Kees Cook <keescook@chromium.org>
---
arch/powerpc/mm/nohash/kaslr_booke.c | 40 ++++++++++++++--------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/mm/nohash/kaslr_booke.c b/arch/powerpc/mm/nohash/kaslr_booke.c
index 4a75f2d9bf0e..07b036e98353 100644
--- a/arch/powerpc/mm/nohash/kaslr_booke.c
+++ b/arch/powerpc/mm/nohash/kaslr_booke.c
@@ -25,6 +25,7 @@ struct regions {
unsigned long pa_start;
unsigned long pa_end;
unsigned long kernel_size;
+ unsigned long linear_sz;
unsigned long dtb_start;
unsigned long dtb_end;
unsigned long initrd_start;
@@ -260,11 +261,23 @@ static __init void get_cell_sizes(const void *fdt, int node, int *addr_cells,
*size_cells = fdt32_to_cpu(*prop);
}
-static unsigned long __init kaslr_legal_offset(void *dt_ptr, unsigned long index,
- unsigned long offset)
+static unsigned long __init kaslr_legal_offset(void *dt_ptr, unsigned long random)
{
unsigned long koffset = 0;
unsigned long start;
+ unsigned long index;
+ unsigned long offset;
+
+ /*
+ * Decide which 64M we want to start
+ * Only use the low 8 bits of the random seed
+ */
+ index = random & 0xFF;
+ index %= regions.linear_sz / SZ_64M;
+
+ /* Decide offset inside 64M */
+ offset = random % (SZ_64M - regions.kernel_size);
+ offset = round_down(offset, SZ_16K);
while ((long)index >= 0) {
offset = memstart_addr + index * SZ_64M + offset;
@@ -289,10 +302,9 @@ static inline __init bool kaslr_disabled(void)
static unsigned long __init kaslr_choose_location(void *dt_ptr, phys_addr_t size,
unsigned long kernel_sz)
{
- unsigned long offset, random;
+ unsigned long random;
unsigned long ram, linear_sz;
u64 seed;
- unsigned long index;
kaslr_get_cmdline(dt_ptr);
if (kaslr_disabled())
@@ -333,22 +345,12 @@ static unsigned long __init kaslr_choose_location(void *dt_ptr, phys_addr_t size
regions.dtb_start = __pa(dt_ptr);
regions.dtb_end = __pa(dt_ptr) + fdt_totalsize(dt_ptr);
regions.kernel_size = kernel_sz;
+ regions.linear_sz = linear_sz;
get_initrd_range(dt_ptr);
get_crash_kernel(dt_ptr, ram);
- /*
- * Decide which 64M we want to start
- * Only use the low 8 bits of the random seed
- */
- index = random & 0xFF;
- index %= linear_sz / SZ_64M;
-
- /* Decide offset inside 64M */
- offset = random % (SZ_64M - kernel_sz);
- offset = round_down(offset, SZ_16K);
-
- return kaslr_legal_offset(dt_ptr, index, offset);
+ return kaslr_legal_offset(dt_ptr, random);
}
/*
@@ -358,8 +360,6 @@ static unsigned long __init kaslr_choose_location(void *dt_ptr, phys_addr_t size
*/
notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
{
- unsigned long tlb_virt;
- phys_addr_t tlb_phys;
unsigned long offset;
unsigned long kernel_sz;
@@ -375,8 +375,8 @@ notrace void __init kaslr_early_init(void *dt_ptr, phys_addr_t size)
is_second_reloc = 1;
if (offset >= SZ_64M) {
- tlb_virt = round_down(kernstart_virt_addr, SZ_64M);
- tlb_phys = round_down(kernstart_addr, SZ_64M);
+ unsigned long tlb_virt = round_down(kernstart_virt_addr, SZ_64M);
+ phys_addr_t tlb_phys = round_down(kernstart_addr, SZ_64M);
/* Create kernel map to relocate in */
create_kaslr_tlb_entry(1, tlb_virt, tlb_phys);
--
2.17.2
^ permalink raw reply related
* Re: [PATCH 2/3] powerpc/sysfs: Show idle_purr and idle_spurr for every CPU
From: Gautham R Shenoy @ 2020-02-05 4:19 UTC (permalink / raw)
To: Naveen N. Rao
Cc: Nathan Lynch, ego, Tyrel Datwyler, linux-kernel, Kamalesh Babulal,
Vaidyanathan Srinivasan, linuxppc-dev
In-Reply-To: <1580802180.jpxk9s8apz.naveen@linux.ibm.com>
Hi Naveen,
On Tue, Feb 04, 2020 at 01:22:19PM +0530, Naveen N. Rao wrote:
> Gautham R Shenoy wrote:
> >Hi Naveen,
> >
> >On Thu, Dec 05, 2019 at 10:23:58PM +0530, Naveen N. Rao wrote:
> >>>diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
> >>>index 80a676d..42ade55 100644
> >>>--- a/arch/powerpc/kernel/sysfs.c
> >>>+++ b/arch/powerpc/kernel/sysfs.c
> >>>@@ -1044,6 +1044,36 @@ static ssize_t show_physical_id(struct device *dev,
> >>> }
> >>> static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
> >>>
> >>>+static ssize_t idle_purr_show(struct device *dev,
> >>>+ struct device_attribute *attr, char *buf)
> >>>+{
> >>>+ struct cpu *cpu = container_of(dev, struct cpu, dev);
> >>>+ unsigned int cpuid = cpu->dev.id;
> >>>+ struct lppaca *cpu_lppaca_ptr = paca_ptrs[cpuid]->lppaca_ptr;
> >>>+ u64 idle_purr_cycles = be64_to_cpu(cpu_lppaca_ptr->wait_state_cycles);
> >>>+
> >>>+ return sprintf(buf, "%llx\n", idle_purr_cycles);
> >>>+}
> >>>+static DEVICE_ATTR_RO(idle_purr);
> >>>+
> >>>+DECLARE_PER_CPU(u64, idle_spurr_cycles);
> >>>+static ssize_t idle_spurr_show(struct device *dev,
> >>>+ struct device_attribute *attr, char *buf)
> >>>+{
> >>>+ struct cpu *cpu = container_of(dev, struct cpu, dev);
> >>>+ unsigned int cpuid = cpu->dev.id;
> >>>+ u64 *idle_spurr_cycles_ptr = per_cpu_ptr(&idle_spurr_cycles, cpuid);
> >>
> >>Is it possible for a user to read stale values if a particular cpu is in an
> >>extended cede? Is it possible to use smp_call_function_single() to force the
> >>cpu out of idle?
> >
> >Yes, if the CPU whose idle_spurr cycle is being read is still in idle,
> >then we will miss reporting the delta spurr cycles for this last
> >idle-duration. Yes, we can use an smp_call_function_single(), though
> >that will introduce IPI noise. How often will idle_[s]purr be read ?
>
> Since it is possible for a cpu to go into extended cede for multiple seconds
> during which time it is possible to mis-report utilization, I think it is
> better to ensure that the sysfs interface for idle_[s]purr report the proper
> values through use of IPI.
>
Fair enough.
> With repect to lparstat, the read interval is user-specified and just gets
> passed onto sleep().
Ok. So I guess currently you will be sending smp_call_function every
time you read a PURR and SPURR. That number will now increase by 2
times when we read idle_purr and idle_spurr.
>
> - Naveen
>
--
Thanks and Regards
gautham.
^ permalink raw reply
* Re: [PATCH v2 1/3] powerpc/tm: Clear the current thread's MSR[TS] after treclaim
From: Michael Neuling @ 2020-02-05 4:58 UTC (permalink / raw)
To: Gustavo Luiz Duarte, linuxppc-dev; +Cc: stable, gromero
In-Reply-To: <20200203160906.24482-1-gustavold@linux.ibm.com>
Other than the minor things below that I think you need, the patch good with me.
Acked-by: Michael Neuling <mikey@neuling.org>
> Subject: Re: [PATCH v2 1/3] powerpc/tm: Clear the current thread's MSR[TS] after treclaim
The subject should mention "signals".
On Mon, 2020-02-03 at 13:09 -0300, Gustavo Luiz Duarte wrote:
> After a treclaim, we expect to be in non-transactional state. If we don't
> immediately clear the current thread's MSR[TS] and we get preempted, then
> tm_recheckpoint_new_task() will recheckpoint and we get rescheduled in
> suspended transaction state.
It's not "immediately", it's before re-enabling preemption.
There is a similar comment in the code that needs to be fixed too.
> When handling a signal caught in transactional state, handle_rt_signal64()
> calls get_tm_stackpointer() that treclaims the transaction using
> tm_reclaim_current() but without clearing the thread's MSR[TS]. This can cause
> the TM Bad Thing exception below if later we pagefault and get preempted trying
> to access the user's sigframe, using __put_user(). Afterwards, when we are
> rescheduled back into do_page_fault() (but now in suspended state since the
> thread's MSR[TS] was not cleared), upon executing 'rfid' after completion of
> the page fault handling, the exception is raised because a transition from
> suspended to non-transactional state is invalid.
>
> Unexpected TM Bad Thing exception at c00000000000de44 (msr 0x8000000302a03031) tm_scratch=800000010280b033
> Oops: Unrecoverable exception, sig: 6 [#1]
> LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries
> Modules linked in: nft_chain_nat nf_nat nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ip6_tables ip_tables nft_compat ip_set nf_tables nfnetlink xts vmx_crypto sg virtio_balloon
> r_mod cdrom virtio_net net_failover virtio_blk virtio_scsi failover dm_mirror dm_region_hash dm_log dm_mod
> CPU: 25 PID: 15547 Comm: a.out Not tainted 5.4.0-rc2 #32
> NIP: c00000000000de44 LR: c000000000034728 CTR: 0000000000000000
> REGS: c00000003fe7bd70 TRAP: 0700 Not tainted (5.4.0-rc2)
> MSR: 8000000302a03031 <SF,VEC,VSX,FP,ME,IR,DR,LE,TM[SE]> CR: 44000884 XER: 00000000
> CFAR: c00000000000dda4 IRQMASK: 0
> PACATMSCRATCH: 800000010280b033
> GPR00: c000000000034728 c000000f65a17c80 c000000001662800 00007fffacf3fd78
> GPR04: 0000000000001000 0000000000001000 0000000000000000 c000000f611f8af0
> GPR08: 0000000000000000 0000000078006001 0000000000000000 000c000000000000
> GPR12: c000000f611f84b0 c00000003ffcb200 0000000000000000 0000000000000000
> GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
> GPR20: 0000000000000000 0000000000000000 0000000000000000 c000000f611f8140
> GPR24: 0000000000000000 00007fffacf3fd68 c000000f65a17d90 c000000f611f7800
> GPR28: c000000f65a17e90 c000000f65a17e90 c000000001685e18 00007fffacf3f000
> NIP [c00000000000de44] fast_exception_return+0xf4/0x1b0
> LR [c000000000034728] handle_rt_signal64+0x78/0xc50
> Call Trace:
> [c000000f65a17c80] [c000000000034710] handle_rt_signal64+0x60/0xc50 (unreliable)
> [c000000f65a17d30] [c000000000023640] do_notify_resume+0x330/0x460
> [c000000f65a17e20] [c00000000000dcc4] ret_from_except_lite+0x70/0x74
> Instruction dump:
> 7c4ff120 e8410170 7c5a03a6 38400000 f8410060 e8010070 e8410080 e8610088
> 60000000 60000000 e8810090 e8210078 <4c000024> 48000000 e8610178 88ed0989
> ---[ end trace 93094aa44b442f87 ]---
>
> The simplified sequence of events that triggers the above exception is:
>
> ... # userspace in NON-TRANSACTIONAL state
> tbegin # userspace in TRANSACTIONAL state
> signal delivery # kernelspace in SUSPENDED state
> handle_rt_signal64()
> get_tm_stackpointer()
> treclaim # kernelspace in NON-TRANSACTIONAL state
> __put_user()
> page fault happens. We will never get back here because of the TM Bad Thing exception.
>
> page fault handling kicks in and we voluntarily preempt ourselves
> do_page_fault()
> __schedule()
> __switch_to(other_task)
>
> our task is rescheduled and we recheckpoint because the thread's MSR[TS] was not cleared
> __switch_to(our_task)
> switch_to_tm()
> tm_recheckpoint_new_task()
> trechkpt # kernelspace in SUSPENDED state
>
> The page fault handling resumes, but now we are in suspended transaction state
> do_page_fault() completes
> rfid <----- trying to get back where the page fault happened (we were non-transactional back then)
> TM Bad Thing # illegal transition from suspended to non-transactional
>
> This patch fixes that issue by clearing the current thread's MSR[TS] just after
> treclaim in get_tm_stackpointer() so that we stay in non-transactional state in
> case we are preempted. In order to make treclaim and clearing the thread's
> MSR[TS] atomic from a preemption perspective when CONFIG_PREEMPT is set,
> preempt_disable/enable() is used. It's also necessary to save the previous
> value of the thread's MSR before get_tm_stackpointer() is called so that it can
> be exposed to the signal handler later in setup_tm_sigcontexts() to inform the
> userspace MSR at the moment of the signal delivery.
>
> Found with tm-signal-context-force-tm kernel selftest on P8 KVM.
Why are you mentioning KVM?
>
> v2: Fix build failure when tm is disabled.
>
> Fixes: 2b0a576d15e0 ("powerpc: Add new transactional memory state to the signal context")
> Cc: stable@vger.kernel.org # v3.9
> Signed-off-by: Gustavo Luiz Duarte <gustavold@linux.ibm.com>
> ---
> arch/powerpc/kernel/signal.c | 17 +++++++++++++++--
> arch/powerpc/kernel/signal_32.c | 28 ++++++++++++++--------------
> arch/powerpc/kernel/signal_64.c | 22 ++++++++++------------
> 3 files changed, 39 insertions(+), 28 deletions(-)
>
> diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
> index e6c30cee6abf..1660be1061ac 100644
> --- a/arch/powerpc/kernel/signal.c
> +++ b/arch/powerpc/kernel/signal.c
> @@ -200,14 +200,27 @@ unsigned long get_tm_stackpointer(struct task_struct *tsk)
> * normal/non-checkpointed stack pointer.
> */
>
> + unsigned long ret = tsk->thread.regs->gpr[1];
> +
> #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> BUG_ON(tsk != current);
>
> if (MSR_TM_ACTIVE(tsk->thread.regs->msr)) {
> + preempt_disable();
> tm_reclaim_current(TM_CAUSE_SIGNAL);
> if (MSR_TM_TRANSACTIONAL(tsk->thread.regs->msr))
> - return tsk->thread.ckpt_regs.gpr[1];
> + ret = tsk->thread.ckpt_regs.gpr[1];
> +
> + /* If we treclaim, we must immediately clear the current
> + * thread's TM bits. Otherwise we might be preempted and have
> + * the live MSR[TS] changed behind our back
> + * (tm_recheckpoint_new_task() would recheckpoint).
> + * Besides, we enter the signal handler in non-transactional
> + * state.
> + */
> + tsk->thread.regs->msr &= ~MSR_TS_MASK;
> + preempt_enable();
> }
> #endif
> - return tsk->thread.regs->gpr[1];
> + return ret;
> }
> diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
> index 98600b276f76..1b090a76b444 100644
> --- a/arch/powerpc/kernel/signal_32.c
> +++ b/arch/powerpc/kernel/signal_32.c
> @@ -489,19 +489,11 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
> */
> static int save_tm_user_regs(struct pt_regs *regs,
> struct mcontext __user *frame,
> - struct mcontext __user *tm_frame, int sigret)
> + struct mcontext __user *tm_frame, int sigret,
> + unsigned long msr)
> {
> - unsigned long msr = regs->msr;
> -
> WARN_ON(tm_suspend_disabled);
>
> - /* Remove TM bits from thread's MSR. The MSR in the sigcontext
> - * just indicates to userland that we were doing a transaction, but we
> - * don't want to return in transactional state. This also ensures
> - * that flush_fp_to_thread won't set TIF_RESTORE_TM again.
> - */
> - regs->msr &= ~MSR_TS_MASK;
> -
> /* Save both sets of general registers */
> if (save_general_regs(¤t->thread.ckpt_regs, frame)
> || save_general_regs(regs, tm_frame))
> @@ -912,6 +904,10 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset,
> int sigret;
> unsigned long tramp;
> struct pt_regs *regs = tsk->thread.regs;
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> + /* Save the thread's msr before get_tm_stackpointer() changes it */
> + unsigned long msr = regs->msr;
> +#endif
>
> BUG_ON(tsk != current);
>
> @@ -944,13 +940,13 @@ int handle_rt_signal32(struct ksignal *ksig, sigset_t *oldset,
>
> #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> tm_frame = &rt_sf->uc_transact.uc_mcontext;
> - if (MSR_TM_ACTIVE(regs->msr)) {
> + if (MSR_TM_ACTIVE(msr)) {
> if (__put_user((unsigned long)&rt_sf->uc_transact,
> &rt_sf->uc.uc_link) ||
> __put_user((unsigned long)tm_frame,
> &rt_sf->uc_transact.uc_regs))
> goto badframe;
> - if (save_tm_user_regs(regs, frame, tm_frame, sigret))
> + if (save_tm_user_regs(regs, frame, tm_frame, sigret, msr))
> goto badframe;
> }
> else
> @@ -1369,6 +1365,10 @@ int handle_signal32(struct ksignal *ksig, sigset_t *oldset,
> int sigret;
> unsigned long tramp;
> struct pt_regs *regs = tsk->thread.regs;
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> + /* Save the thread's msr before get_tm_stackpointer() changes it */
> + unsigned long msr = regs->msr;
> +#endif
>
> BUG_ON(tsk != current);
>
> @@ -1402,9 +1402,9 @@ int handle_signal32(struct ksignal *ksig, sigset_t *oldset,
>
> #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> tm_mctx = &frame->mctx_transact;
> - if (MSR_TM_ACTIVE(regs->msr)) {
> + if (MSR_TM_ACTIVE(msr)) {
> if (save_tm_user_regs(regs, &frame->mctx, &frame->mctx_transact,
> - sigret))
> + sigret, msr))
> goto badframe;
> }
> else
> diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
> index 117515564ec7..84ed2e77ef9c 100644
> --- a/arch/powerpc/kernel/signal_64.c
> +++ b/arch/powerpc/kernel/signal_64.c
> @@ -192,7 +192,8 @@ static long setup_sigcontext(struct sigcontext __user *sc,
> static long setup_tm_sigcontexts(struct sigcontext __user *sc,
> struct sigcontext __user *tm_sc,
> struct task_struct *tsk,
> - int signr, sigset_t *set, unsigned long handler)
> + int signr, sigset_t *set, unsigned long handler,
> + unsigned long msr)
> {
> /* When CONFIG_ALTIVEC is set, we _always_ setup v_regs even if the
> * process never used altivec yet (MSR_VEC is zero in pt_regs of
> @@ -207,12 +208,11 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc,
> elf_vrreg_t __user *tm_v_regs = sigcontext_vmx_regs(tm_sc);
> #endif
> struct pt_regs *regs = tsk->thread.regs;
> - unsigned long msr = tsk->thread.regs->msr;
> long err = 0;
>
> BUG_ON(tsk != current);
>
> - BUG_ON(!MSR_TM_ACTIVE(regs->msr));
> + BUG_ON(!MSR_TM_ACTIVE(msr));
>
> WARN_ON(tm_suspend_disabled);
>
> @@ -222,13 +222,6 @@ static long setup_tm_sigcontexts(struct sigcontext __user *sc,
> */
> msr |= tsk->thread.ckpt_regs.msr & (MSR_FP | MSR_VEC | MSR_VSX);
>
> - /* Remove TM bits from thread's MSR. The MSR in the sigcontext
> - * just indicates to userland that we were doing a transaction, but we
> - * don't want to return in transactional state. This also ensures
> - * that flush_fp_to_thread won't set TIF_RESTORE_TM again.
> - */
> - regs->msr &= ~MSR_TS_MASK;
> -
> #ifdef CONFIG_ALTIVEC
> err |= __put_user(v_regs, &sc->v_regs);
> err |= __put_user(tm_v_regs, &tm_sc->v_regs);
> @@ -824,6 +817,10 @@ int handle_rt_signal64(struct ksignal *ksig, sigset_t *set,
> unsigned long newsp = 0;
> long err = 0;
> struct pt_regs *regs = tsk->thread.regs;
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> + /* Save the thread's msr before get_tm_stackpointer() changes it */
> + unsigned long msr = regs->msr;
> +#endif
>
> BUG_ON(tsk != current);
>
> @@ -841,7 +838,7 @@ int handle_rt_signal64(struct ksignal *ksig, sigset_t *set,
> err |= __put_user(0, &frame->uc.uc_flags);
> err |= __save_altstack(&frame->uc.uc_stack, regs->gpr[1]);
> #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> - if (MSR_TM_ACTIVE(regs->msr)) {
> + if (MSR_TM_ACTIVE(msr)) {
> /* The ucontext_t passed to userland points to the second
> * ucontext_t (for transactional state) with its uc_link ptr.
> */
> @@ -849,7 +846,8 @@ int handle_rt_signal64(struct ksignal *ksig, sigset_t *set,
> err |= setup_tm_sigcontexts(&frame->uc.uc_mcontext,
> &frame->uc_transact.uc_mcontext,
> tsk, ksig->sig, NULL,
> - (unsigned long)ksig->ka.sa.sa_handler);
> + (unsigned long)ksig->ka.sa.sa_handler,
> + msr);
> } else
> #endif
> {
^ permalink raw reply
* Re: [PATCH v2 3/6] powerpc/fsl_booke/64: implement KASLR for fsl_booke64
From: kbuild test robot @ 2020-02-05 5:13 UTC (permalink / raw)
To: Jason Yan
Cc: oss, kbuild-all, keescook, kernel-hardening, Jason Yan,
linux-kernel, npiggin, diana.craciun, paulus, zhaohongjiang,
linuxppc-dev
In-Reply-To: <20200205025527.28640-4-yanaijie@huawei.com>
[-- Attachment #1: Type: text/plain, Size: 5630 bytes --]
Hi Jason,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.5 next-20200204]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Jason-Yan/implement-KASLR-for-powerpc-fsl_booke-64/20200205-105837
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 7.5.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.5.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
arch/powerpc/kernel/setup_64.c: In function 'early_setup':
>> arch/powerpc/kernel/setup_64.c:303:2: error: implicit declaration of function 'kaslr_early_init'; did you mean 'udbg_early_init'? [-Werror=implicit-function-declaration]
kaslr_early_init(__va(dt_ptr), 0);
^~~~~~~~~~~~~~~~
udbg_early_init
cc1: all warnings being treated as errors
vim +303 arch/powerpc/kernel/setup_64.c
262
263 /*
264 * Early initialization entry point. This is called by head.S
265 * with MMU translation disabled. We rely on the "feature" of
266 * the CPU that ignores the top 2 bits of the address in real
267 * mode so we can access kernel globals normally provided we
268 * only toy with things in the RMO region. From here, we do
269 * some early parsing of the device-tree to setup out MEMBLOCK
270 * data structures, and allocate & initialize the hash table
271 * and segment tables so we can start running with translation
272 * enabled.
273 *
274 * It is this function which will call the probe() callback of
275 * the various platform types and copy the matching one to the
276 * global ppc_md structure. Your platform can eventually do
277 * some very early initializations from the probe() routine, but
278 * this is not recommended, be very careful as, for example, the
279 * device-tree is not accessible via normal means at this point.
280 */
281
282 void __init early_setup(unsigned long dt_ptr)
283 {
284 static __initdata struct paca_struct boot_paca;
285
286 /* -------- printk is _NOT_ safe to use here ! ------- */
287
288 /* Try new device tree based feature discovery ... */
289 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
290 /* Otherwise use the old style CPU table */
291 identify_cpu(0, mfspr(SPRN_PVR));
292
293 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
294 initialise_paca(&boot_paca, 0);
295 setup_paca(&boot_paca);
296 fixup_boot_paca();
297
298 /* -------- printk is now safe to use ------- */
299
300 /* Enable early debugging if any specified (see udbg.h) */
301 udbg_early_init();
302
> 303 kaslr_early_init(__va(dt_ptr), 0);
304
305 udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
306
307 /*
308 * Do early initialization using the flattened device
309 * tree, such as retrieving the physical memory map or
310 * calculating/retrieving the hash table size.
311 */
312 early_init_devtree(__va(dt_ptr));
313
314 /* Now we know the logical id of our boot cpu, setup the paca. */
315 if (boot_cpuid != 0) {
316 /* Poison paca_ptrs[0] again if it's not the boot cpu */
317 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
318 }
319 setup_paca(paca_ptrs[boot_cpuid]);
320 fixup_boot_paca();
321
322 /*
323 * Configure exception handlers. This include setting up trampolines
324 * if needed, setting exception endian mode, etc...
325 */
326 configure_exceptions();
327
328 /*
329 * Configure Kernel Userspace Protection. This needs to happen before
330 * feature fixups for platforms that implement this using features.
331 */
332 setup_kup();
333
334 /* Apply all the dynamic patching */
335 apply_feature_fixups();
336 setup_feature_keys();
337
338 early_ioremap_setup();
339
340 /* Initialize the hash table or TLB handling */
341 early_init_mmu();
342
343 /*
344 * After firmware and early platform setup code has set things up,
345 * we note the SPR values for configurable control/performance
346 * registers, and use those as initial defaults.
347 */
348 record_spr_defaults();
349
350 /*
351 * At this point, we can let interrupts switch to virtual mode
352 * (the MMU has been setup), so adjust the MSR in the PACA to
353 * have IR and DR set and enable AIL if it exists
354 */
355 cpu_ready_for_interrupts();
356
357 /*
358 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
359 * will only actually get enabled on the boot cpu much later once
360 * ftrace itself has been initialized.
361 */
362 this_cpu_enable_ftrace();
363
364 udbg_printf(" <- %s()\n", __func__);
365
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 25667 bytes --]
^ permalink raw reply
* [PATCH v2] libnvdimm: Update persistence domain value for of_pmem and papr_scm device
From: Aneesh Kumar K.V @ 2020-02-05 5:20 UTC (permalink / raw)
To: dan.j.williams; +Cc: Aneesh Kumar K.V, linuxppc-dev, linux-nvdimm
Currently, kernel shows the below values
"persistence_domain":"cpu_cache"
"persistence_domain":"memory_controller"
"persistence_domain":"unknown"
"cpu_cache" indicates no extra instructions is needed to ensure the persistence
of data in the pmem media on power failure.
"memory_controller" indicates platform provided instructions need to be issued
as per documented sequence to make sure data get flushed so that it is
guaranteed to be on pmem media in case of system power loss.
Based on the above use memory_controller for non volatile regions on ppc64.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/platforms/pseries/papr_scm.c | 7 ++++++-
drivers/nvdimm/of_pmem.c | 4 +++-
include/linux/libnvdimm.h | 1 -
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
index 7525635a8536..ffcd0d7a867c 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -359,8 +359,13 @@ static int papr_scm_nvdimm_init(struct papr_scm_priv *p)
if (p->is_volatile)
p->region = nvdimm_volatile_region_create(p->bus, &ndr_desc);
- else
+ else {
+ /*
+ * We need to flush things correctly to guarantee persistance
+ */
+ set_bit(ND_REGION_PERSIST_MEMCTRL, &ndr_desc.flags);
p->region = nvdimm_pmem_region_create(p->bus, &ndr_desc);
+ }
if (!p->region) {
dev_err(dev, "Error registering region %pR from %pOF\n",
ndr_desc.res, p->dn);
diff --git a/drivers/nvdimm/of_pmem.c b/drivers/nvdimm/of_pmem.c
index 8224d1431ea9..6826a274a1f1 100644
--- a/drivers/nvdimm/of_pmem.c
+++ b/drivers/nvdimm/of_pmem.c
@@ -62,8 +62,10 @@ static int of_pmem_region_probe(struct platform_device *pdev)
if (is_volatile)
region = nvdimm_volatile_region_create(bus, &ndr_desc);
- else
+ else {
+ set_bit(ND_REGION_PERSIST_MEMCTRL, &ndr_desc.flags);
region = nvdimm_pmem_region_create(bus, &ndr_desc);
+ }
if (!region)
dev_warn(&pdev->dev, "Unable to register region %pR from %pOF\n",
diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h
index 0f366706b0aa..771d888a5ed7 100644
--- a/include/linux/libnvdimm.h
+++ b/include/linux/libnvdimm.h
@@ -54,7 +54,6 @@ enum {
/*
* Platform provides mechanisms to automatically flush outstanding
* write data from memory controler to pmem on system power loss.
- * (ADR)
*/
ND_REGION_PERSIST_MEMCTRL = 2,
--
2.24.1
^ permalink raw reply related
* Re: [PATCH v2 2/3] selftests/powerpc: Add tm-signal-pagefault test
From: Michael Ellerman @ 2020-02-05 5:27 UTC (permalink / raw)
To: Gustavo Luiz Duarte, linuxppc-dev; +Cc: mikey, gromero, Gustavo Luiz Duarte
In-Reply-To: <20200203160906.24482-2-gustavold@linux.ibm.com>
Gustavo Luiz Duarte <gustavold@linux.ibm.com> writes:
> This test triggers a TM Bad Thing by raising a signal in transactional state
> and forcing a pagefault to happen in kernelspace when the kernel signal
> handling code first touches the user signal stack.
>
> This is inspired by the test tm-signal-context-force-tm but uses userfaultfd to
> make the test deterministic. While this test always triggers the bug in one
> run, I had to execute tm-signal-context-force-tm several times (the test runs
> 5000 times each execution) to trigger the same bug.
Using userfaultfd is a very nice touch. But it's not always enabled,
which leads to eg:
root@mpe-ubuntu-le:~# /home/michael/tm-signal-pagefault
test: tm_signal_pagefault
tags: git_version:v5.5-9354-gc1e346e7fc44
userfaultfd() failed: Function not implemented
failure: tm_signal_pagefault
It would be nice if that resulted in a skip, not a failure.
It looks like it shouldn't be too hard to skip if the userfaultfd call
returns ENOSYS.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/vdso32: mark __kernel_datapage_offset as STV_PROTECTED
From: Christophe Leroy @ 2020-02-05 6:25 UTC (permalink / raw)
To: Fangrui Song, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman
Cc: clang-built-linux, linuxppc-dev, linux-kernel
In-Reply-To: <20200205005054.k72fuikf6rwrgfe4@google.com>
Le 05/02/2020 à 01:50, Fangrui Song a écrit :
> A PC-relative relocation (R_PPC_REL16_LO in this case) referencing a
> preemptible symbol in a -shared link is not allowed. GNU ld's powerpc
> port is permissive and allows it [1], but lld will report an error after
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id=ec0895f08f99515194e9fcfe1338becf6f759d38
Note that there is a series whose first two patches aim at dropping
__kernel_datapage_offset . See
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=156045
and especially patches https://patchwork.ozlabs.org/patch/1231467/ and
https://patchwork.ozlabs.org/patch/1231461/
Those patches can be applied independentely of the rest.
Christophe
>
> Make the symbol protected so that it is non-preemptible but still
> exported.
>
> [1]: https://sourceware.org/bugzilla/show_bug.cgi?id=25500
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/851
> Signed-off-by: Fangrui Song <maskray@google.com>
> ---
> arch/powerpc/kernel/vdso32/datapage.S | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/kernel/vdso32/datapage.S b/arch/powerpc/kernel/vdso32/datapage.S
> index 217bb630f8f9..2831a8676365 100644
> --- a/arch/powerpc/kernel/vdso32/datapage.S
> +++ b/arch/powerpc/kernel/vdso32/datapage.S
> @@ -13,7 +13,8 @@
> #include <asm/vdso_datapage.h>
>
> .text
> - .global __kernel_datapage_offset;
> + .global __kernel_datapage_offset
> + .protected __kernel_datapage_offset
> __kernel_datapage_offset:
> .long 0
>
>
^ permalink raw reply
* Re: [PATCH 2/3] powerpc/sysfs: Show idle_purr and idle_spurr for every CPU
From: Naveen N. Rao @ 2020-02-05 6:58 UTC (permalink / raw)
To: ego
Cc: Nathan Lynch, Tyrel Datwyler, linux-kernel, Kamalesh Babulal,
Vaidyanathan Srinivasan, linuxppc-dev
In-Reply-To: <20200205041956.GA5401@in.ibm.com>
Gautham R Shenoy wrote:
>
>> With repect to lparstat, the read interval is user-specified and just gets
>> passed onto sleep().
>
> Ok. So I guess currently you will be sending smp_call_function every
> time you read a PURR and SPURR. That number will now increase by 2
> times when we read idle_purr and idle_spurr.
Yes, not really efficient. I just wanted to point out that we can't have
stale data being returned if we choose to add another sysfs file.
We should be able to use any other interface too, if you have a
different interface in mind.
- Naveen
^ permalink raw reply
* Re: [PATCH 2/3] powerpc/sysfs: Show idle_purr and idle_spurr for every CPU
From: Christophe Leroy @ 2020-02-05 7:08 UTC (permalink / raw)
To: Gautham R. Shenoy, Michael Ellerman, Vaidyanathan Srinivasan,
Nathan Lynch, Kamalesh Babulal, Naveen N. Rao, Tyrel Datwyler
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <1574856072-30972-3-git-send-email-ego@linux.vnet.ibm.com>
Le 27/11/2019 à 13:01, Gautham R. Shenoy a écrit :
> From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
>
> On Pseries LPARs, to calculate utilization, we need to know the
> [S]PURR ticks when the CPUs were busy or idle.
>
> The total PURR and SPURR ticks are already exposed via the per-cpu
> sysfs files /sys/devices/system/cpu/cpuX/purr and
> /sys/devices/system/cpu/cpuX/spurr.
>
> This patch adds support for exposing the idle PURR and SPURR ticks via
> /sys/devices/system/cpu/cpuX/idle_purr and
> /sys/devices/system/cpu/cpuX/idle_spurr.
Might be a candid question, but I see in arch/powerpc/kernel/time.c that
PURR/SPURR are already taken into account by the kernel to calculate
utilisation when CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is selected.
As far as I understand, you are wanting to expose this to userland to
redo the calculation there. What is wrong with the values reported by
the kernel ?
Christophe
>
> Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/sysfs.c | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
> index 80a676d..42ade55 100644
> --- a/arch/powerpc/kernel/sysfs.c
> +++ b/arch/powerpc/kernel/sysfs.c
> @@ -1044,6 +1044,36 @@ static ssize_t show_physical_id(struct device *dev,
> }
> static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
>
> +static ssize_t idle_purr_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct cpu *cpu = container_of(dev, struct cpu, dev);
> + unsigned int cpuid = cpu->dev.id;
> + struct lppaca *cpu_lppaca_ptr = paca_ptrs[cpuid]->lppaca_ptr;
> + u64 idle_purr_cycles = be64_to_cpu(cpu_lppaca_ptr->wait_state_cycles);
> +
> + return sprintf(buf, "%llx\n", idle_purr_cycles);
> +}
> +static DEVICE_ATTR_RO(idle_purr);
> +
> +DECLARE_PER_CPU(u64, idle_spurr_cycles);
> +static ssize_t idle_spurr_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct cpu *cpu = container_of(dev, struct cpu, dev);
> + unsigned int cpuid = cpu->dev.id;
> + u64 *idle_spurr_cycles_ptr = per_cpu_ptr(&idle_spurr_cycles, cpuid);
> +
> + return sprintf(buf, "%llx\n", *idle_spurr_cycles_ptr);
> +}
> +static DEVICE_ATTR_RO(idle_spurr);
> +
> +static void create_idle_purr_spurr_sysfs_entry(struct device *cpudev)
> +{
> + device_create_file(cpudev, &dev_attr_idle_purr);
> + device_create_file(cpudev, &dev_attr_idle_spurr);
> +}
> +
> static int __init topology_init(void)
> {
> int cpu, r;
> @@ -1067,6 +1097,8 @@ static int __init topology_init(void)
> register_cpu(c, cpu);
>
> device_create_file(&c->dev, &dev_attr_physical_id);
> + if (firmware_has_feature(FW_FEATURE_SPLPAR))
> + create_idle_purr_spurr_sysfs_entry(&c->dev);
> }
> }
> r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
>
^ permalink raw reply
* Re: [PATCH 2/3] powerpc/sysfs: Show idle_purr and idle_spurr for every CPU
From: Naveen N. Rao @ 2020-02-05 8:07 UTC (permalink / raw)
To: Christophe Leroy, Gautham R. Shenoy, Kamalesh Babulal,
Michael Ellerman, Nathan Lynch, Vaidyanathan Srinivasan,
Tyrel Datwyler
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <b26cedb0-8b12-71b6-63d2-990186cd49e5@c-s.fr>
Christophe Leroy wrote:
>
>
> Le 27/11/2019 à 13:01, Gautham R. Shenoy a écrit :
>> From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
>>
>> On Pseries LPARs, to calculate utilization, we need to know the
>> [S]PURR ticks when the CPUs were busy or idle.
>>
>> The total PURR and SPURR ticks are already exposed via the per-cpu
>> sysfs files /sys/devices/system/cpu/cpuX/purr and
>> /sys/devices/system/cpu/cpuX/spurr.
>>
>> This patch adds support for exposing the idle PURR and SPURR ticks via
>> /sys/devices/system/cpu/cpuX/idle_purr and
>> /sys/devices/system/cpu/cpuX/idle_spurr.
>
> Might be a candid question, but I see in arch/powerpc/kernel/time.c that
> PURR/SPURR are already taken into account by the kernel to calculate
> utilisation when CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is selected.
>
> As far as I understand, you are wanting to expose this to userland to
> redo the calculation there. What is wrong with the values reported by
> the kernel ?
As you point out, it is only done with
CONFIG_VIRT_CPU_ACCOUNTING_NATIVE, but isn't available with NO_HZ_FULL,
which happens to be the distro default nowadays.
- Naveen
^ permalink raw reply
* Re: [PATCH v6 07/10] mm/memory_hotplug: We always have a zone in find_(smallest|biggest)_section_pfn
From: Wei Yang @ 2020-02-05 8:57 UTC (permalink / raw)
To: David Hildenbrand
Cc: linux-s390, Michal Hocko, linux-ia64, Pavel Tatashin, linux-sh,
x86, linux-kernel, linux-mm, Wei Yang, Andrew Morton,
linuxppc-dev, Dan Williams, linux-arm-kernel, Oscar Salvador
In-Reply-To: <20191006085646.5768-8-david@redhat.com>
On Sun, Oct 06, 2019 at 10:56:43AM +0200, David Hildenbrand wrote:
>With shrink_pgdat_span() out of the way, we now always have a valid
>zone.
>
>Cc: Andrew Morton <akpm@linux-foundation.org>
>Cc: Oscar Salvador <osalvador@suse.de>
>Cc: David Hildenbrand <david@redhat.com>
>Cc: Michal Hocko <mhocko@suse.com>
>Cc: Pavel Tatashin <pasha.tatashin@soleen.com>
>Cc: Dan Williams <dan.j.williams@intel.com>
>Cc: Wei Yang <richardw.yang@linux.intel.com>
>Signed-off-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Wei Yang <richardw.yang@linux.intel.com>
--
Wei Yang
Help you, Help me
^ permalink raw reply
* Re: [PATCH v6 07/10] mm/memory_hotplug: We always have a zone in find_(smallest|biggest)_section_pfn
From: David Hildenbrand @ 2020-02-05 8:59 UTC (permalink / raw)
To: Wei Yang
Cc: linux-s390, Michal Hocko, linux-ia64, Pavel Tatashin, linux-sh,
x86, linux-kernel, linux-mm, Andrew Morton, linuxppc-dev,
Dan Williams, linux-arm-kernel, Oscar Salvador
In-Reply-To: <20200205085709.GA24162@richard>
On 05.02.20 09:57, Wei Yang wrote:
> On Sun, Oct 06, 2019 at 10:56:43AM +0200, David Hildenbrand wrote:
>> With shrink_pgdat_span() out of the way, we now always have a valid
>> zone.
>>
>> Cc: Andrew Morton <akpm@linux-foundation.org>
>> Cc: Oscar Salvador <osalvador@suse.de>
>> Cc: David Hildenbrand <david@redhat.com>
>> Cc: Michal Hocko <mhocko@suse.com>
>> Cc: Pavel Tatashin <pasha.tatashin@soleen.com>
>> Cc: Dan Williams <dan.j.williams@intel.com>
>> Cc: Wei Yang <richardw.yang@linux.intel.com>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>
> Reviewed-by: Wei Yang <richardw.yang@linux.intel.com>
Just FYI, the patches are now upstream, so the rb's can no longer be
applied. (but we can send fixes if we find that something is broken ;)
). Thanks!
--
Thanks,
David / dhildenb
^ permalink raw reply
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