* Re: [PATCH v4 06/16] powerpc: Use a function for getting the instruction op code
From: Jordan Niethe @ 2020-03-23 9:35 UTC (permalink / raw)
To: Balamuruhan S
Cc: Alistair Popple, Nicholas Piggin, linuxppc-dev, Daniel Axtens
In-Reply-To: <250cbed1e5966c5a740e840b9127ed7964e241d6.camel@linux.ibm.com>
On Mon, Mar 23, 2020 at 5:54 PM Balamuruhan S <bala24@linux.ibm.com> wrote:
>
> On Fri, 2020-03-20 at 16:17 +1100, Jordan Niethe wrote:
> > In preparation for using a data type for instructions that can not be
> > directly used with the '>>' operator use a function for getting the op
> > code of an instruction.
>
> we need to adopt this in sstep.c and vecemu.c
Thank you, I had forgotten about vecemu.c.
>
> -- Bala
> >
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> > v4: New to series
> > ---
> > arch/powerpc/kernel/align.c | 4 ++--
> > arch/powerpc/lib/code-patching.c | 4 ++--
> > 2 files changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> > index 38542fffa179..77c49dfdc1b4 100644
> > --- a/arch/powerpc/kernel/align.c
> > +++ b/arch/powerpc/kernel/align.c
> > @@ -313,8 +313,8 @@ int fix_alignment(struct pt_regs *regs)
> > }
> >
> > #ifdef CONFIG_SPE
> > - if ((instr >> 26) == 0x4) {
> > - int reg = (instr >> 21) & 0x1f;
> > + if (ppc_inst_opcode(instr) == 0x4) {
> > + int reg = (ppc_inst_word(instr) >> 21) & 0x1f;
> > PPC_WARN_ALIGNMENT(spe, regs);
> > return emulate_spe(regs, reg, instr);
> > }
> > diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-
> > patching.c
> > index e2ba23fd6f4d..04a303c059e2 100644
> > --- a/arch/powerpc/lib/code-patching.c
> > +++ b/arch/powerpc/lib/code-patching.c
> > @@ -228,7 +228,7 @@ bool is_offset_in_branch_range(long offset)
> > */
> > bool is_conditional_branch(ppc_inst instr)
> > {
> > - unsigned int opcode = instr >> 26;
> > + unsigned int opcode = ppc_inst_opcode(instr);
> >
> > if (opcode == 16) /* bc, bca, bcl, bcla */
> > return true;
> > @@ -286,7 +286,7 @@ unsigned int create_cond_branch(const unsigned int *addr,
> >
> > static unsigned int branch_opcode(ppc_inst instr)
> > {
> > - return (instr >> 26) & 0x3F;
> > + return ppc_inst_opcode(instr) & 0x3F;
> > }
> >
> > static int instr_is_branch_iform(ppc_inst instr)
>
^ permalink raw reply
* Re: [PATCH v4 13/16] powerpc: Support prefixed instructions in alignment handler
From: Jordan Niethe @ 2020-03-23 9:35 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Alistair Popple, Balamuruhan S, linuxppc-dev, Daniel Axtens
In-Reply-To: <1584947091.jsvdec8of0.astroid@bobo.none>
On Mon, Mar 23, 2020 at 6:09 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Alignment interrupts can be caused by prefixed instructions accessing
> > memory. Prefixed instructions are not permitted to cross 64-byte
> > boundaries. If they do the alignment interrupt is invoked with SRR1
> > BOUNDARY bit set. If this occurs send a SIGBUS to the offending process
> > if in user mode. If in kernel mode call bad_page_fault().
> >
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> > v2: - Move __get_user_instr() and __get_user_instr_inatomic() to this
> > commit (previously in "powerpc sstep: Prepare to support prefixed
> > instructions").
> > - Rename sufx to suffix
> > - Use a macro for calculating instruction length
> > v3: Move __get_user_{instr(), instr_inatomic()} up with the other
> > get_user definitions and remove nested if.
> > v4: Just do the things for alignment_exception(). Other changes handled
> > elsewhere.
> > ---
> > arch/powerpc/kernel/traps.c | 21 ++++++++++++++++++++-
> > 1 file changed, 20 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
> > index a4764b039749..cd8b3043c268 100644
> > --- a/arch/powerpc/kernel/traps.c
> > +++ b/arch/powerpc/kernel/traps.c
> > @@ -583,6 +583,10 @@ static inline int check_io_access(struct pt_regs *regs)
> > #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
> > #define REASON_PRIVILEGED ESR_PPR
> > #define REASON_TRAP ESR_PTR
> > +#define REASON_PREFIXED 0
> > +#define REASON_BOUNDARY 0
> > +
> > +#define inst_length(reason) 4
> >
> > /* single-step stuff */
> > #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
> > @@ -597,6 +601,10 @@ static inline int check_io_access(struct pt_regs *regs)
> > #define REASON_ILLEGAL SRR1_PROGILL
> > #define REASON_PRIVILEGED SRR1_PROGPRIV
> > #define REASON_TRAP SRR1_PROGTRAP
> > +#define REASON_PREFIXED SRR1_PREFIXED
> > +#define REASON_BOUNDARY SRR1_BOUNDARY
> > +
> > +#define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
>
> Looks good. If you define REASON_BOUNDARY 0, then this will constant
> fold away so no need to define it twice.
Good point.
>
> Thanks,
> Nick
^ permalink raw reply
* Re: [PATCH v4 03/16] powerpc: Use a datatype for instructions
From: Nicholas Piggin @ 2020-03-23 9:51 UTC (permalink / raw)
To: Jordan Niethe; +Cc: Alistair Popple, Balamuruhan S, linuxppc-dev, Daniel Axtens
In-Reply-To: <CACzsE9qy7dUv+sbcCN-i0EeYiH=DacutULunpBdgV0h8D0m2yQ@mail.gmail.com>
Jordan Niethe's on March 23, 2020 7:28 pm:
> On Mon, Mar 23, 2020 at 5:27 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:17 pm:
>> > Currently unsigned ints are used to represent instructions on powerpc.
>> > This has worked well as instructions have always been 4 byte words.
>> > However, a future ISA version will introduce some changes to
>> > instructions that mean this scheme will no longer work as well. This
>> > change is Prefixed Instructions. A prefixed instruction is made up of a
>> > word prefix followed by a word suffix to make an 8 byte double word
>> > instruction. No matter the endianess of the system the prefix always
>> > comes first. Prefixed instructions are only planned for powerpc64.
>> >
>> > Introduce a ppc_inst type to represent both prefixed and word
>> > instructions on powerpc64 while keeping it possible to exclusively have
>> > word instructions on powerpc32, A latter patch will expand the type to
>> > include prefixed instructions but for now just typedef it to a u32.
>> >
>> > Later patches will introduce helper functions and macros for
>> > manipulating the instructions so that powerpc64 and powerpc32 might
>> > maintain separate type definitions.
>>
>> ppc_inst_t I would slightly prefer for a typedef like this.
> Are _t types meant to be reserved?
No, just convention that structs are not normally typedefed unless
they are a pervasive interface that gets passed around a lot but
does not get accessed without accessor functions much. When you do
typedef them, add a _t (or less frequently _s/_u/etc). pte_t,
cpumask_t, atomic_t.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v4 16/16] powerpc sstep: Add support for prefixed fixed-point arithmetic
From: Balamuruhan S @ 2020-03-23 10:05 UTC (permalink / raw)
To: Jordan Niethe, linuxppc-dev; +Cc: alistair, npiggin, dja
In-Reply-To: <20200320051809.24332-17-jniethe5@gmail.com>
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> This adds emulation support for the following prefixed Fixed-Point
> Arithmetic instructions:
> * Prefixed Add Immediate (paddi)
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Reviewed-by: Balamuruhan S <bala24@linux.ibm.com>
> ---
> v3: Since we moved the prefixed loads/stores into the load/store switch
> statement it no longer makes sense to have paddi in there, so move it
> out.
> ---
> arch/powerpc/lib/sstep.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> index daef70eb8e22..6862fc019258 100644
> --- a/arch/powerpc/lib/sstep.c
> +++ b/arch/powerpc/lib/sstep.c
> @@ -1335,6 +1335,26 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> switch (opcode) {
> #ifdef __powerpc64__
> + case 1:
> + prefix_r = word & (1ul << 20);
> + ra = (suffix >> 16) & 0x1f;
> + rd = (suffix >> 21) & 0x1f;
> + op->reg = rd;
> + op->val = regs->gpr[rd];
> + suffixopcode = suffix >> 26;
> + prefixtype = (word >> 24) & 0x3;
> + switch (prefixtype) {
> + case 2:
> + if (prefix_r && ra)
> + return 0;
> + switch (suffixopcode) {
> + case 14: /* paddi */
> + op->type = COMPUTE | PREFIXED;
> + op->val = mlsd_8lsd_ea(word, suffix, regs);
> + goto compute_done;
> + }
> + }
> + break;
> case 2: /* tdi */
> if (rd & trap_compare(regs->gpr[ra], (short) word))
> goto trap;
^ permalink raw reply
* Re: [PATCH v4 09/16] powerpc: Use a function for reading instructions
From: Jordan Niethe @ 2020-03-23 10:09 UTC (permalink / raw)
To: Nicholas Piggin
Cc: Alistair Popple, Balamuruhan S, linuxppc-dev, Daniel Axtens
In-Reply-To: <1584946118.tw98vo7hqx.astroid@bobo.none>
On Mon, Mar 23, 2020 at 7:03 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>
> Jordan Niethe's on March 20, 2020 3:18 pm:
> > Prefixed instructions will mean there are instructions of different
> > length. As a result dereferencing a pointer to an instruction will not
> > necessarily give the desired result. Introduce a function for reading
> > instructions from memory into the instruction data type.
> >
> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> > ---
> > v4: New to series
> > ---
> > arch/powerpc/include/asm/uprobes.h | 4 ++--
> > arch/powerpc/kernel/kprobes.c | 8 ++++----
> > arch/powerpc/kernel/mce_power.c | 2 +-
> > arch/powerpc/kernel/optprobes.c | 6 +++---
> > arch/powerpc/kernel/trace/ftrace.c | 33 +++++++++++++++++++-----------
> > arch/powerpc/kernel/uprobes.c | 2 +-
> > arch/powerpc/lib/code-patching.c | 22 ++++++++++----------
> > arch/powerpc/lib/feature-fixups.c | 6 +++---
> > arch/powerpc/xmon/xmon.c | 6 +++---
> > 9 files changed, 49 insertions(+), 40 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h
> > index 2bbdf27d09b5..fff3c5fc90b5 100644
> > --- a/arch/powerpc/include/asm/uprobes.h
> > +++ b/arch/powerpc/include/asm/uprobes.h
> > @@ -23,8 +23,8 @@ typedef ppc_opcode_t uprobe_opcode_t;
> >
> > struct arch_uprobe {
> > union {
> > - u32 insn;
> > - u32 ixol;
> > + u8 insn[MAX_UINSN_BYTES];
> > + u8 ixol[MAX_UINSN_BYTES];
> > };
> > };
>
> Hmm. I wonder if this should be a different patch. Not sure if raw
> bytes is a good idea here. ppc probes also has a ppc_opcode_t, maybe
> could be replaced with ppc_insn_t and used here instead?
You are right this should not really be in this patch. I felt bytes
made sense as we have MAX_UINSN_BYTES, which could be updated once
prefixed instructions were introduced.
By replace do you mean define uprobe_opcode_t as ppc_inst_t instead of
ppc_opcode_t? That will not really work with the arch indep code in
places like:
bool __weak is_swbp_insn(uprobe_opcode_t *insn)
{
return *insn == UPROBE_SWBP_INSN;
}
Or do you mean something like this:
struct arch_uprobe {
union {
- u32 insn;
- u32 ixol;
+ pcc_inst_t insn;
+ ppc_inst_t ixol;
};
};
>
> Also can't find where you define ppc_inst_read.
>
> > diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c
> > index 7614a9f537fd..ad451205f268 100644
> > --- a/arch/powerpc/kernel/trace/ftrace.c
> > +++ b/arch/powerpc/kernel/trace/ftrace.c
> > @@ -41,6 +41,12 @@
> > #define NUM_FTRACE_TRAMPS 8
> > static unsigned long ftrace_tramps[NUM_FTRACE_TRAMPS];
> >
> > +static long
> > +read_inst(ppc_inst *inst, const void *src)
> > +{
> > + return probe_kernel_read((void *)inst, src, MCOUNT_INSN_SIZE);
> > +}
>
> Humbly suggest probe_kernel_inst_read.
The other probe_kernel_* functions were from generic code so I
thought it might be misleading to call it that.
>
> Thanks,
> Nick
>
^ permalink raw reply
* Re: [PATCH v4 00/16] Initial Prefixed Instruction support
From: Nicholas Piggin @ 2020-03-23 10:17 UTC (permalink / raw)
To: Jordan Niethe; +Cc: Alistair Popple, Balamuruhan S, linuxppc-dev, Daniel Axtens
In-Reply-To: <CACzsE9r5uvL-zp34VrCqO_RTEsXPbLrt2iu+MHL-apapydOugA@mail.gmail.com>
Jordan Niethe's on March 23, 2020 7:25 pm:
> On Mon, Mar 23, 2020 at 5:22 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:17 pm:
>> > A future revision of the ISA will introduce prefixed instructions. A
>> > prefixed instruction is composed of a 4-byte prefix followed by a
>> > 4-byte suffix.
>> >
>> > All prefixes have the major opcode 1. A prefix will never be a valid
>> > word instruction. A suffix may be an existing word instruction or a
>> > new instruction.
>> >
>> > This series enables prefixed instructions and extends the instruction
>> > emulation to support them. Then the places where prefixed instructions
>> > might need to be emulated are updated.
>> >
>> > The series is based on top of:
>> > https://patchwork.ozlabs.org/patch/1232619/ as this will effect
>> > kprobes.
>> >
>> > v4 is based on feedback from Nick Piggins, Christophe Leroy and Daniel Axtens.
>> > The major changes:
>> > - Move xmon breakpoints from data section to text section
>> > - Introduce a data type for instructions on powerpc
>>
>> Thanks for doing this, looks like a lot of work, I hope it works out :)
>>
> Yes it did end up touching a lot of places. I started thinking that
> that maybe it would be simpler to just use a u64 instead of the struct
> for instructions.
> If we always keep the word instruction / prefix in the lower bytes,
> all of the current masking should still work and we can use operators
> again instead of ppc_inst_equal(), etc.
Yeah.. I think now that you've done it, I prefer it this way.
> It also makes printing easier. We could just #define INST_FMT %llx or
> #define INST_FMT %x on powerpc32 and use that for printing out
> instructions.
Well, not sure about that. Would it make endian concerns more
complicated? Print format for prefix might be '%016llx', but we
don't want that for all instructions only prefixed ones, and I
don't know if that is the way to go either.
We'll want to adopt some convention for displaying prefixed
instruction bytes, but I don't know what what works best. I wonder
if binutils or any userspace tools have a convention.
Which reminds me, you might have missed show_instructions()?
Although maybe you don't need that until we start using them in
the kernel.
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH] powerpc/64: allow rtas to be called in real-mode, use this in machine check
From: Nicholas Piggin @ 2020-03-23 10:29 UTC (permalink / raw)
To: Ganesh, linuxppc-dev; +Cc: Mahesh Salgaonkar
In-Reply-To: <8435e728-8cb4-c6b2-f228-44ebb0b0cc29@linux.ibm.com>
Ganesh's on March 23, 2020 8:19 pm:
>
>
> On 3/20/20 8:58 PM, Nicholas Piggin wrote:
>> rtas_call allocates and uses memory in failure paths, which is
>> not safe for RMA. It also calls local_irq_save() which may not be safe
>> in all real mode contexts.
>>
>> Particularly machine check may run with interrupts not "reconciled",
>> and it may have hit while it was in tracing code that should not be
>> rentered.
>>
>> Create minimal rtas call that should be usable by guest machine check
>> code, use it there to call "ibm,nmi-interlock".
>>
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>> arch/powerpc/include/asm/rtas.h | 1 +
>> arch/powerpc/kernel/entry_64.S | 12 ++++++--
>> arch/powerpc/kernel/rtas.c | 43 ++++++++++++++++++++++++++++
>> arch/powerpc/platforms/pseries/ras.c | 2 +-
>> 4 files changed, 54 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
>> index 3c1887351c71..4ffc499ce1ac 100644
>> --- a/arch/powerpc/include/asm/rtas.h
>> +++ b/arch/powerpc/include/asm/rtas.h
>> @@ -352,6 +352,7 @@ extern struct rtas_t rtas;
>> extern int rtas_token(const char *service);
>> extern int rtas_service_present(const char *service);
>> extern int rtas_call(int token, int, int, int *, ...);
>> +extern int raw_rtas_call(int token, int, int, int *, ...);
>> void rtas_call_unlocked(struct rtas_args *args, int token, int nargs,
>> int nret, ...);
>> extern void __noreturn rtas_restart(char *cmd);
>> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
>> index 51c5b681f70c..309abb677788 100644
>> --- a/arch/powerpc/kernel/entry_64.S
>> +++ b/arch/powerpc/kernel/entry_64.S
>> @@ -759,6 +759,13 @@ _GLOBAL(enter_rtas)
>> li r0,0
>> mtcr r0
>>
>> + /* enter_rtas called from real-mode may not have irqs reconciled
>> + * but will always have interrupts disabled.
>> + */
>> + mfmsr r6
>> + andi. r7,r6,(MSR_IR|MSR_DR)
>> + beq 2f
>> +
>> #ifdef CONFIG_BUG
>> /* There is no way it is acceptable to get here with interrupts enabled,
>> * check it with the asm equivalent of WARN_ON
>> @@ -769,10 +776,10 @@ _GLOBAL(enter_rtas)
>> #endif
>>
>> /* Hard-disable interrupts */
>> - mfmsr r6
>> rldicl r7,r6,48,1
>> rotldi r7,r7,16
>> mtmsrd r7,1
>> +2:
>>
>> /* Unfortunately, the stack pointer and the MSR are also clobbered,
>> * so they are saved in the PACA which allows us to restore
>> @@ -795,7 +802,6 @@ _GLOBAL(enter_rtas)
>> ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE
>> andc r6,r0,r9
>>
>> -__enter_rtas:
>> sync /* disable interrupts so SRR0/1 */
>> mtmsrd r0 /* don't get trashed */
>>
>> @@ -837,7 +843,7 @@ rtas_return_loc:
>> mtspr SPRN_SRR1,r4
>> RFI_TO_KERNEL
>> b . /* prevent speculative execution */
>> -_ASM_NOKPROBE_SYMBOL(__enter_rtas)
>> +_ASM_NOKPROBE_SYMBOL(enter_rtas)
>> _ASM_NOKPROBE_SYMBOL(rtas_return_loc)
>>
>> .align 3
>> diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
>> index c5fa251b8950..a058dcfb6726 100644
>> --- a/arch/powerpc/kernel/rtas.c
>> +++ b/arch/powerpc/kernel/rtas.c
>> @@ -450,6 +450,8 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
>> char *buff_copy = NULL;
>> int ret;
>>
>> + WARN_ON_ONCE((mfmsr() & (MSR_IR|MSR_DR)) != (MSR_IR|MSR_DR));
>> +
>> if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE)
>> return -1;
>>
>> @@ -483,6 +485,47 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...)
>> }
>> EXPORT_SYMBOL(rtas_call);
>>
>> +/*
>> + * Like rtas_call but no kmalloc or printk etc in error handling, so
>> + * error won't go through log_error. No tracing, may be called in real mode.
>> + */
>> +int notrace raw_rtas_call(int token, int nargs, int nret, int *outputs, ...)
>> +{
>> + va_list list;
>> + int i;
>> + struct rtas_args *rtas_args;
>> + int ret;
>> +
>> + WARN_ON_ONCE((mfmsr() & MSR_EE));
>> +
>> + if (!rtas.entry || token == RTAS_UNKNOWN_SERVICE)
>> + return -1;
>> +
>> + /*
>> + * Real mode must have MSR[EE]=0 and we prefer not to touch any
>> + * irq or preempt state (this may be called in machine check).
>> + */
>> + preempt_disable_notrace();
>> + arch_spin_lock(&rtas.lock);
>
> I wonder, if its ok to attempt for this lock in nested MCE.
It's not. It will deadlock if an MCE hits after "ibm,nmi-interlock" is
called and before the lock is released on the same CPU.
The struct actually isn't even that big, 84 bytes or so, and we're in
the dedicated machine check stack here so we could just put it on
stack AFAIKS?
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v4 09/16] powerpc: Use a function for reading instructions
From: Nicholas Piggin @ 2020-03-23 10:36 UTC (permalink / raw)
To: Jordan Niethe; +Cc: Alistair Popple, Balamuruhan S, linuxppc-dev, Daniel Axtens
In-Reply-To: <CACzsE9qL6FhFuMbHy1Qz6EvOEeuA-2rjK=nuqwikZEapS9VmNA@mail.gmail.com>
Jordan Niethe's on March 23, 2020 8:09 pm:
> On Mon, Mar 23, 2020 at 7:03 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> Jordan Niethe's on March 20, 2020 3:18 pm:
>> > Prefixed instructions will mean there are instructions of different
>> > length. As a result dereferencing a pointer to an instruction will not
>> > necessarily give the desired result. Introduce a function for reading
>> > instructions from memory into the instruction data type.
>> >
>> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
>> > ---
>> > v4: New to series
>> > ---
>> > arch/powerpc/include/asm/uprobes.h | 4 ++--
>> > arch/powerpc/kernel/kprobes.c | 8 ++++----
>> > arch/powerpc/kernel/mce_power.c | 2 +-
>> > arch/powerpc/kernel/optprobes.c | 6 +++---
>> > arch/powerpc/kernel/trace/ftrace.c | 33 +++++++++++++++++++-----------
>> > arch/powerpc/kernel/uprobes.c | 2 +-
>> > arch/powerpc/lib/code-patching.c | 22 ++++++++++----------
>> > arch/powerpc/lib/feature-fixups.c | 6 +++---
>> > arch/powerpc/xmon/xmon.c | 6 +++---
>> > 9 files changed, 49 insertions(+), 40 deletions(-)
>> >
>> > diff --git a/arch/powerpc/include/asm/uprobes.h b/arch/powerpc/include/asm/uprobes.h
>> > index 2bbdf27d09b5..fff3c5fc90b5 100644
>> > --- a/arch/powerpc/include/asm/uprobes.h
>> > +++ b/arch/powerpc/include/asm/uprobes.h
>> > @@ -23,8 +23,8 @@ typedef ppc_opcode_t uprobe_opcode_t;
>> >
>> > struct arch_uprobe {
>> > union {
>> > - u32 insn;
>> > - u32 ixol;
>> > + u8 insn[MAX_UINSN_BYTES];
>> > + u8 ixol[MAX_UINSN_BYTES];
>> > };
>> > };
>>
>> Hmm. I wonder if this should be a different patch. Not sure if raw
>> bytes is a good idea here. ppc probes also has a ppc_opcode_t, maybe
>> could be replaced with ppc_insn_t and used here instead?
> You are right this should not really be in this patch. I felt bytes
> made sense as we have MAX_UINSN_BYTES, which could be updated once
> prefixed instructions were introduced.
Okay.
> By replace do you mean define uprobe_opcode_t as ppc_inst_t instead of
> ppc_opcode_t? That will not really work with the arch indep code in
> places like:
>
> bool __weak is_swbp_insn(uprobe_opcode_t *insn)
> {
> return *insn == UPROBE_SWBP_INSN;
> }
Ah, yeah I did mean that, you probably told me that already.
> Or do you mean something like this:
> struct arch_uprobe {
> union {
> - u32 insn;
> - u32 ixol;
> + pcc_inst_t insn;
> + ppc_inst_t ixol;
> };
> };
I didn't mean that, but it would be nicer than the change you've got,
if it works.
>> Also can't find where you define ppc_inst_read.
>>
>> > diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c
>> > index 7614a9f537fd..ad451205f268 100644
>> > --- a/arch/powerpc/kernel/trace/ftrace.c
>> > +++ b/arch/powerpc/kernel/trace/ftrace.c
>> > @@ -41,6 +41,12 @@
>> > #define NUM_FTRACE_TRAMPS 8
>> > static unsigned long ftrace_tramps[NUM_FTRACE_TRAMPS];
>> >
>> > +static long
>> > +read_inst(ppc_inst *inst, const void *src)
>> > +{
>> > + return probe_kernel_read((void *)inst, src, MCOUNT_INSN_SIZE);
>> > +}
>>
>> Humbly suggest probe_kernel_inst_read.
> The other probe_kernel_* functions were from generic code so I
> thought it might be misleading to call it that.
It's probably not too bad, you could add a __ or ppc_ prefix if
it would help?
Thanks,
Nick
^ permalink raw reply
* Re: [PATCH v4 08/16] powerpc: Use an accessor for word instructions
From: Balamuruhan S @ 2020-03-23 11:12 UTC (permalink / raw)
To: Jordan Niethe, linuxppc-dev; +Cc: alistair, npiggin, dja
In-Reply-To: <20200320051809.24332-9-jniethe5@gmail.com>
On Fri, 2020-03-20 at 16:18 +1100, Jordan Niethe wrote:
> In preparation for prefixed instructions where all instructions are no
> longer words, use an accessor for getting a word instruction as a u32
> from the instruction data type.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> ---
> v4: New to series
> ---
> arch/powerpc/kernel/align.c | 2 +-
> arch/powerpc/kernel/kprobes.c | 2 +-
> arch/powerpc/kernel/trace/ftrace.c | 16 +-
> arch/powerpc/lib/code-patching.c | 2 +-
> arch/powerpc/lib/feature-fixups.c | 4 +-
> arch/powerpc/lib/sstep.c | 270 ++++++++++++++-------------
> arch/powerpc/lib/test_emulate_step.c | 4 +-
> arch/powerpc/xmon/xmon.c | 4 +-
> 8 files changed, 153 insertions(+), 151 deletions(-)
>
> diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
> index 77c49dfdc1b4..b246ca124931 100644
> --- a/arch/powerpc/kernel/align.c
> +++ b/arch/powerpc/kernel/align.c
> @@ -309,7 +309,7 @@ int fix_alignment(struct pt_regs *regs)
> /* We don't handle PPC little-endian any more... */
> if (cpu_has_feature(CPU_FTR_PPC_LE))
> return -EIO;
> - instr = PPC_INST(swab32(instr));
> + instr = PPC_INST(swab32(ppc_inst_word(instr)));
> }
>
> #ifdef CONFIG_SPE
> diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
> index 4c2b656615a6..0c600b6e4ead 100644
> --- a/arch/powerpc/kernel/kprobes.c
> +++ b/arch/powerpc/kernel/kprobes.c
> @@ -242,7 +242,7 @@ static int try_to_emulate(struct kprobe *p, struct
> pt_regs *regs)
> * So, we should never get here... but, its still
> * good to catch them, just in case...
> */
> - printk("Can't step on instruction %x\n", insn);
> + printk("Can't step on instruction %x\n", ppc_inst_word(insn));
> BUG();
> } else {
> /*
> diff --git a/arch/powerpc/kernel/trace/ftrace.c
> b/arch/powerpc/kernel/trace/ftrace.c
> index b3645b664819..7614a9f537fd 100644
> --- a/arch/powerpc/kernel/trace/ftrace.c
> +++ b/arch/powerpc/kernel/trace/ftrace.c
> @@ -74,7 +74,7 @@ ftrace_modify_code(unsigned long ip, ppc_inst old, ppc_inst
> new)
> /* Make sure it is what we expect it to be */
> if (!ppc_inst_equal(replaced, old)) {
> pr_err("%p: replaced (%#x) != old (%#x)",
> - (void *)ip, replaced, old);
> + (void *)ip, ppc_inst_word(replaced), ppc_inst_word(old));
> return -EINVAL;
> }
>
> @@ -136,7 +136,7 @@ __ftrace_make_nop(struct module *mod,
>
> /* Make sure that that this is still a 24bit jump */
> if (!is_bl_op(op)) {
> - pr_err("Not expected bl: opcode is %x\n", op);
> + pr_err("Not expected bl: opcode is %x\n", ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -171,7 +171,7 @@ __ftrace_make_nop(struct module *mod,
> /* We expect either a mflr r0, or a std r0, LRSAVE(r1) */
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_MFLR)) &&
> !ppc_inst_equal(op, PPC_INST(PPC_INST_STD_LR))) {
> - pr_err("Unexpected instruction %08x around bl _mcount\n", op);
> + pr_err("Unexpected instruction %08x around bl _mcount\n",
> ppc_inst_word(op));
> return -EINVAL;
> }
> #else
> @@ -201,7 +201,7 @@ __ftrace_make_nop(struct module *mod,
> }
>
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_LD_TOC))) {
> - pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC, op);
> + pr_err("Expected %08x found %08x\n", PPC_INST_LD_TOC,
> ppc_inst_word(op));
> return -EINVAL;
> }
> #endif /* CONFIG_MPROFILE_KERNEL */
> @@ -401,7 +401,7 @@ static int __ftrace_make_nop_kernel(struct dyn_ftrace
> *rec, unsigned long addr)
>
> /* Make sure that that this is still a 24bit jump */
> if (!is_bl_op(op)) {
> - pr_err("Not expected bl: opcode is %x\n", op);
> + pr_err("Not expected bl: opcode is %x\n", ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -525,7 +525,7 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long
> addr)
>
> if (!expected_nop_sequence(ip, op[0], op[1])) {
> pr_err("Unexpected call sequence at %p: %x %x\n",
> - ip, op[0], op[1]);
> + ip, ppc_inst_word(op[0]), ppc_inst_word(op[1]));
> return -EINVAL;
> }
>
> @@ -644,7 +644,7 @@ static int __ftrace_make_call_kernel(struct dyn_ftrace
> *rec, unsigned long addr)
> }
>
> if (!ppc_inst_equal(op, PPC_INST(PPC_INST_NOP))) {
> - pr_err("Unexpected call sequence at %p: %x\n", ip, op);
> + pr_err("Unexpected call sequence at %p: %x\n", ip,
> ppc_inst_word(op));
> return -EINVAL;
> }
>
> @@ -723,7 +723,7 @@ __ftrace_modify_call(struct dyn_ftrace *rec, unsigned
> long old_addr,
>
> /* Make sure that that this is still a 24bit jump */
> if (!is_bl_op(op)) {
> - pr_err("Not expected bl: opcode is %x\n", op);
> + pr_err("Not expected bl: opcode is %x\n", ppc_inst_word(op));
> return -EINVAL;
> }
>
> diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-
> patching.c
> index ec3abe1a6927..849eee63df3d 100644
> --- a/arch/powerpc/lib/code-patching.c
> +++ b/arch/powerpc/lib/code-patching.c
> @@ -233,7 +233,7 @@ bool is_conditional_branch(ppc_inst instr)
> if (opcode == 16) /* bc, bca, bcl, bcla */
> return true;
> if (opcode == 19) {
> - switch ((instr >> 1) & 0x3ff) {
> + switch ((ppc_inst_word(instr) >> 1) & 0x3ff) {
> case 16: /* bclr, bclrl */
> case 528: /* bcctr, bcctrl */
> case 560: /* bctar, bctarl */
> diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-
> fixups.c
> index 552106d1f64a..fe8ec099aa96 100644
> --- a/arch/powerpc/lib/feature-fixups.c
> +++ b/arch/powerpc/lib/feature-fixups.c
> @@ -54,8 +54,8 @@ static int patch_alt_instruction(unsigned int *src,
> unsigned int *dest,
>
> /* Branch within the section doesn't need translating */
> if (target < alt_start || target > alt_end) {
> - instr = translate_branch(dest, src);
> - if (ppc_inst_null(instr))
> + instr = ppc_inst_word(translate_branch((ppc_inst
> *)dest, (ppc_inst *)src));
> + if (!instr)
> return 1;
> }
> }
> diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
> index 1d9c766a89fe..bae878a83fa5 100644
> --- a/arch/powerpc/lib/sstep.c
> +++ b/arch/powerpc/lib/sstep.c
> @@ -1169,26 +1169,28 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> unsigned long int imm;
> unsigned long int val, val2;
> unsigned int mb, me, sh;
> + unsigned int word;
> long ival;
>
> + word = ppc_inst_word(instr);
> op->type = COMPUTE;
>
> - opcode = instr >> 26;
> + opcode = word >> 26;
> switch (opcode) {
> case 16: /* bc */
> op->type = BRANCH;
> - imm = (signed short)(instr & 0xfffc);
> - if ((instr & 2) == 0)
> + imm = (signed short)(word & 0xfffc);
> + if ((word & 2) == 0)
> imm += regs->nip;
> op->val = truncate_if_32bit(regs->msr, imm);
> - if (instr & 1)
> + if (word & 1)
> op->type |= SETLK;
> - if (branch_taken(instr, regs, op))
> + if (branch_taken(word, regs, op))
> op->type |= BRTAKEN;
> return 1;
> #ifdef CONFIG_PPC64
> case 17: /* sc */
> - if ((instr & 0xfe2) == 2)
> + if ((word & 0xfe2) == 2)
> op->type = SYSCALL;
> else
> op->type = UNKNOWN;
> @@ -1196,21 +1198,21 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> #endif
> case 18: /* b */
> op->type = BRANCH | BRTAKEN;
> - imm = instr & 0x03fffffc;
> + imm = word & 0x03fffffc;
> if (imm & 0x02000000)
> imm -= 0x04000000;
> - if ((instr & 2) == 0)
> + if ((word & 2) == 0)
> imm += regs->nip;
> op->val = truncate_if_32bit(regs->msr, imm);
> - if (instr & 1)
> + if (word & 1)
> op->type |= SETLK;
> return 1;
> case 19:
> - switch ((instr >> 1) & 0x3ff) {
> + switch ((word >> 1) & 0x3ff) {
> case 0: /* mcrf */
> op->type = COMPUTE + SETCC;
> - rd = 7 - ((instr >> 23) & 0x7);
> - ra = 7 - ((instr >> 18) & 0x7);
> + rd = 7 - ((word >> 23) & 0x7);
> + ra = 7 - ((word >> 18) & 0x7);
> rd *= 4;
> ra *= 4;
> val = (regs->ccr >> ra) & 0xf;
> @@ -1220,11 +1222,11 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 16: /* bclr */
> case 528: /* bcctr */
> op->type = BRANCH;
> - imm = (instr & 0x400)? regs->ctr: regs->link;
> + imm = (word & 0x400)? regs->ctr: regs->link;
> op->val = truncate_if_32bit(regs->msr, imm);
> - if (instr & 1)
> + if (word & 1)
> op->type |= SETLK;
> - if (branch_taken(instr, regs, op))
> + if (branch_taken(word, regs, op))
> op->type |= BRTAKEN;
> return 1;
>
> @@ -1247,23 +1249,23 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 417: /* crorc */
> case 449: /* cror */
> op->type = COMPUTE + SETCC;
> - ra = (instr >> 16) & 0x1f;
> - rb = (instr >> 11) & 0x1f;
> - rd = (instr >> 21) & 0x1f;
> + ra = (word >> 16) & 0x1f;
> + rb = (word >> 11) & 0x1f;
> + rd = (word >> 21) & 0x1f;
can't we use your accessors for all these operations ?
> ra = (regs->ccr >> (31 - ra)) & 1;
> rb = (regs->ccr >> (31 - rb)) & 1;
> - val = (instr >> (6 + ra * 2 + rb)) & 1;
> + val = (word >> (6 + ra * 2 + rb)) & 1;
> op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
> (val << (31 - rd));
> return 1;
> }
> break;
> case 31:
> - switch ((instr >> 1) & 0x3ff) {
> + switch ((word >> 1) & 0x3ff) {
> case 598: /* sync */
> op->type = BARRIER + BARRIER_SYNC;
> #ifdef __powerpc64__
> - switch ((instr >> 21) & 3) {
> + switch ((word >> 21) & 3) {
> case 1: /* lwsync */
> op->type = BARRIER + BARRIER_LWSYNC;
> break;
> @@ -1285,20 +1287,20 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> if (!FULL_REGS(regs))
> return -1;
>
> - rd = (instr >> 21) & 0x1f;
> - ra = (instr >> 16) & 0x1f;
> - rb = (instr >> 11) & 0x1f;
> - rc = (instr >> 6) & 0x1f;
> + rd = (word >> 21) & 0x1f;
> + ra = (word >> 16) & 0x1f;
> + rb = (word >> 11) & 0x1f;
> + rc = (word >> 6) & 0x1f;
same here and in similar such places.
-- Bala
>
> switch (opcode) {
> #ifdef __powerpc64__
> case 2: /* tdi */
> - if (rd & trap_compare(regs->gpr[ra], (short) instr))
> + if (rd & trap_compare(regs->gpr[ra], (short) word))
> goto trap;
> return 1;
> #endif
> case 3: /* twi */
> - if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
> + if (rd & trap_compare((int)regs->gpr[ra], (short) word))
> goto trap;
> return 1;
>
> @@ -1307,7 +1309,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> if (!cpu_has_feature(CPU_FTR_ARCH_300))
> return -1;
>
> - switch (instr & 0x3f) {
> + switch (word & 0x3f) {
> case 48: /* maddhd */
> asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
> "=r" (op->val) : "r" (regs->gpr[ra]),
> @@ -1335,16 +1337,16 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> #endif
>
> case 7: /* mulli */
> - op->val = regs->gpr[ra] * (short) instr;
> + op->val = regs->gpr[ra] * (short) word;
> goto compute_done;
>
> case 8: /* subfic */
> - imm = (short) instr;
> + imm = (short) word;
> add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
> return 1;
>
> case 10: /* cmpli */
> - imm = (unsigned short) instr;
> + imm = (unsigned short) word;
> val = regs->gpr[ra];
> #ifdef __powerpc64__
> if ((rd & 1) == 0)
> @@ -1354,7 +1356,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 1;
>
> case 11: /* cmpi */
> - imm = (short) instr;
> + imm = (short) word;
> val = regs->gpr[ra];
> #ifdef __powerpc64__
> if ((rd & 1) == 0)
> @@ -1364,35 +1366,35 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 1;
>
> case 12: /* addic */
> - imm = (short) instr;
> + imm = (short) word;
> add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
> return 1;
>
> case 13: /* addic. */
> - imm = (short) instr;
> + imm = (short) word;
> add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
> set_cr0(regs, op);
> return 1;
>
> case 14: /* addi */
> - imm = (short) instr;
> + imm = (short) word;
> if (ra)
> imm += regs->gpr[ra];
> op->val = imm;
> goto compute_done;
>
> case 15: /* addis */
> - imm = ((short) instr) << 16;
> + imm = ((short) word) << 16;
> if (ra)
> imm += regs->gpr[ra];
> op->val = imm;
> goto compute_done;
>
> case 19:
> - if (((instr >> 1) & 0x1f) == 2) {
> + if (((word >> 1) & 0x1f) == 2) {
> /* addpcis */
> - imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
> - imm |= (instr >> 15) & 0x3e; /* d1 field */
> + imm = (short) (word & 0xffc1); /* d0 + d2 fields */
> + imm |= (word >> 15) & 0x3e; /* d1 field */
> op->val = regs->nip + (imm << 16) + 4;
> goto compute_done;
> }
> @@ -1400,65 +1402,65 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 0;
>
> case 20: /* rlwimi */
> - mb = (instr >> 6) & 0x1f;
> - me = (instr >> 1) & 0x1f;
> + mb = (word >> 6) & 0x1f;
> + me = (word >> 1) & 0x1f;
> val = DATA32(regs->gpr[rd]);
> imm = MASK32(mb, me);
> op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
> goto logical_done;
>
> case 21: /* rlwinm */
> - mb = (instr >> 6) & 0x1f;
> - me = (instr >> 1) & 0x1f;
> + mb = (word >> 6) & 0x1f;
> + me = (word >> 1) & 0x1f;
> val = DATA32(regs->gpr[rd]);
> op->val = ROTATE(val, rb) & MASK32(mb, me);
> goto logical_done;
>
> case 23: /* rlwnm */
> - mb = (instr >> 6) & 0x1f;
> - me = (instr >> 1) & 0x1f;
> + mb = (word >> 6) & 0x1f;
> + me = (word >> 1) & 0x1f;
> rb = regs->gpr[rb] & 0x1f;
> val = DATA32(regs->gpr[rd]);
> op->val = ROTATE(val, rb) & MASK32(mb, me);
> goto logical_done;
>
> case 24: /* ori */
> - op->val = regs->gpr[rd] | (unsigned short) instr;
> + op->val = regs->gpr[rd] | (unsigned short) word;
> goto logical_done_nocc;
>
> case 25: /* oris */
> - imm = (unsigned short) instr;
> + imm = (unsigned short) word;
> op->val = regs->gpr[rd] | (imm << 16);
> goto logical_done_nocc;
>
> case 26: /* xori */
> - op->val = regs->gpr[rd] ^ (unsigned short) instr;
> + op->val = regs->gpr[rd] ^ (unsigned short) word;
> goto logical_done_nocc;
>
> case 27: /* xoris */
> - imm = (unsigned short) instr;
> + imm = (unsigned short) word;
> op->val = regs->gpr[rd] ^ (imm << 16);
> goto logical_done_nocc;
>
> case 28: /* andi. */
> - op->val = regs->gpr[rd] & (unsigned short) instr;
> + op->val = regs->gpr[rd] & (unsigned short) word;
> set_cr0(regs, op);
> goto logical_done_nocc;
>
> case 29: /* andis. */
> - imm = (unsigned short) instr;
> + imm = (unsigned short) word;
> op->val = regs->gpr[rd] & (imm << 16);
> set_cr0(regs, op);
> goto logical_done_nocc;
>
> #ifdef __powerpc64__
> case 30: /* rld* */
> - mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
> + mb = ((word >> 6) & 0x1f) | (word & 0x20);
> val = regs->gpr[rd];
> - if ((instr & 0x10) == 0) {
> - sh = rb | ((instr & 2) << 4);
> + if ((word & 0x10) == 0) {
> + sh = rb | ((word & 2) << 4);
> val = ROTATE(val, sh);
> - switch ((instr >> 2) & 3) {
> + switch ((word >> 2) & 3) {
> case 0: /* rldicl */
> val &= MASK64_L(mb);
> break;
> @@ -1478,7 +1480,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> } else {
> sh = regs->gpr[rb] & 0x3f;
> val = ROTATE(val, sh);
> - switch ((instr >> 1) & 7) {
> + switch ((word >> 1) & 7) {
> case 0: /* rldcl */
> op->val = val & MASK64_L(mb);
> goto logical_done;
> @@ -1493,8 +1495,8 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> case 31:
> /* isel occupies 32 minor opcodes */
> - if (((instr >> 1) & 0x1f) == 15) {
> - mb = (instr >> 6) & 0x1f; /* bc field */
> + if (((word >> 1) & 0x1f) == 15) {
> + mb = (word >> 6) & 0x1f; /* bc field */
> val = (regs->ccr >> (31 - mb)) & 1;
> val2 = (ra) ? regs->gpr[ra] : 0;
>
> @@ -1502,7 +1504,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> goto compute_done;
> }
>
> - switch ((instr >> 1) & 0x3ff) {
> + switch ((word >> 1) & 0x3ff) {
> case 4: /* tw */
> if (rd == 0x1f ||
> (rd & trap_compare((int)regs->gpr[ra],
> @@ -1536,17 +1538,17 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> op->reg = rd;
> /* only MSR_EE and MSR_RI get changed if bit 15 set */
> /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
> - imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
> + imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
> op->val = imm;
> return 0;
> #endif
>
> case 19: /* mfcr */
> imm = 0xffffffffUL;
> - if ((instr >> 20) & 1) {
> + if ((word >> 20) & 1) {
> imm = 0xf0000000UL;
> for (sh = 0; sh < 8; ++sh) {
> - if (instr & (0x80000 >> sh))
> + if (word & (0x80000 >> sh))
> break;
> imm >>= 4;
> }
> @@ -1560,7 +1562,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> val = regs->gpr[rd];
> op->ccval = regs->ccr;
> for (sh = 0; sh < 8; ++sh) {
> - if (instr & (0x80000 >> sh))
> + if (word & (0x80000 >> sh))
> op->ccval = (op->ccval & ~imm) |
> (val & imm);
> imm >>= 4;
> @@ -1568,7 +1570,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 1;
>
> case 339: /* mfspr */
> - spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
> + spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
> op->type = MFSPR;
> op->reg = rd;
> op->spr = spr;
> @@ -1578,7 +1580,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 0;
>
> case 467: /* mtspr */
> - spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
> + spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
> op->type = MTSPR;
> op->val = regs->gpr[rd];
> op->spr = spr;
> @@ -1948,7 +1950,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 826: /* sradi with sh_5 = 0 */
> case 827: /* sradi with sh_5 = 1 */
> op->type = COMPUTE + SETREG + SETXER;
> - sh = rb | ((instr & 2) << 4);
> + sh = rb | ((word & 2) << 4);
> ival = (signed long int) regs->gpr[rd];
> op->val = ival >> sh;
> op->xerval = regs->xer;
> @@ -1964,7 +1966,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> if (!cpu_has_feature(CPU_FTR_ARCH_300))
> return -1;
> op->type = COMPUTE + SETREG;
> - sh = rb | ((instr & 2) << 4);
> + sh = rb | ((word & 2) << 4);
> val = (signed int) regs->gpr[rd];
> if (sh)
> op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
> @@ -1979,34 +1981,34 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> */
> case 54: /* dcbst */
> op->type = MKOP(CACHEOP, DCBST, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> return 0;
>
> case 86: /* dcbf */
> op->type = MKOP(CACHEOP, DCBF, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> return 0;
>
> case 246: /* dcbtst */
> op->type = MKOP(CACHEOP, DCBTST, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> op->reg = rd;
> return 0;
>
> case 278: /* dcbt */
> op->type = MKOP(CACHEOP, DCBTST, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> op->reg = rd;
> return 0;
>
> case 982: /* icbi */
> op->type = MKOP(CACHEOP, ICBI, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> return 0;
>
> case 1014: /* dcbz */
> op->type = MKOP(CACHEOP, DCBZ, 0);
> - op->ea = xform_ea(instr, regs);
> + op->ea = xform_ea(word, regs);
> return 0;
> }
> break;
> @@ -2019,14 +2021,14 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> op->update_reg = ra;
> op->reg = rd;
> op->val = regs->gpr[rd];
> - u = (instr >> 20) & UPDATE;
> + u = (word >> 20) & UPDATE;
> op->vsx_flags = 0;
>
> switch (opcode) {
> case 31:
> - u = instr & UPDATE;
> - op->ea = xform_ea(instr, regs);
> - switch ((instr >> 1) & 0x3ff) {
> + u = word & UPDATE;
> + op->ea = xform_ea(word, regs);
> + switch ((word >> 1) & 0x3ff) {
> case 20: /* lwarx */
> op->type = MKOP(LARX, 0, 4);
> break;
> @@ -2271,25 +2273,25 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> #ifdef CONFIG_VSX
> case 12: /* lxsiwzx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 4);
> op->element_size = 8;
> break;
>
> case 76: /* lxsiwax */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
> op->element_size = 8;
> break;
>
> case 140: /* stxsiwx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 4);
> op->element_size = 8;
> break;
>
> case 268: /* lxvx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 16;
> op->vsx_flags = VSX_CHECK_VEC;
> @@ -2298,33 +2300,33 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 269: /* lxvl */
> case 301: { /* lxvll */
> int nb;
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->ea = ra ? regs->gpr[ra] : 0;
> nb = regs->gpr[rb] & 0xff;
> if (nb > 16)
> nb = 16;
> op->type = MKOP(LOAD_VSX, 0, nb);
> op->element_size = 16;
> - op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
> + op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
> VSX_CHECK_VEC;
> break;
> }
> case 332: /* lxvdsx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 8);
> op->element_size = 8;
> op->vsx_flags = VSX_SPLAT;
> break;
>
> case 364: /* lxvwsx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 4);
> op->element_size = 4;
> op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
> break;
>
> case 396: /* stxvx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 16;
> op->vsx_flags = VSX_CHECK_VEC;
> @@ -2333,118 +2335,118 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 397: /* stxvl */
> case 429: { /* stxvll */
> int nb;
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->ea = ra ? regs->gpr[ra] : 0;
> nb = regs->gpr[rb] & 0xff;
> if (nb > 16)
> nb = 16;
> op->type = MKOP(STORE_VSX, 0, nb);
> op->element_size = 16;
> - op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
> + op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
> VSX_CHECK_VEC;
> break;
> }
> case 524: /* lxsspx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 4);
> op->element_size = 8;
> op->vsx_flags = VSX_FPCONV;
> break;
>
> case 588: /* lxsdx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 8);
> op->element_size = 8;
> break;
>
> case 652: /* stxsspx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 4);
> op->element_size = 8;
> op->vsx_flags = VSX_FPCONV;
> break;
>
> case 716: /* stxsdx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 8);
> op->element_size = 8;
> break;
>
> case 780: /* lxvw4x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 4;
> break;
>
> case 781: /* lxsibzx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 1);
> op->element_size = 8;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 812: /* lxvh8x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 2;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 813: /* lxsihzx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 2);
> op->element_size = 8;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 844: /* lxvd2x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 8;
> break;
>
> case 876: /* lxvb16x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 1;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 908: /* stxvw4x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 4;
> break;
>
> case 909: /* stxsibx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 1);
> op->element_size = 8;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 940: /* stxvh8x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 2;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 941: /* stxsihx */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 2);
> op->element_size = 8;
> op->vsx_flags = VSX_CHECK_VEC;
> break;
>
> case 972: /* stxvd2x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 8;
> break;
>
> case 1004: /* stxvb16x */
> - op->reg = rd | ((instr & 1) << 5);
> + op->reg = rd | ((word & 1) << 5);
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 1;
> op->vsx_flags = VSX_CHECK_VEC;
> @@ -2457,80 +2459,80 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 32: /* lwz */
> case 33: /* lwzu */
> op->type = MKOP(LOAD, u, 4);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 34: /* lbz */
> case 35: /* lbzu */
> op->type = MKOP(LOAD, u, 1);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 36: /* stw */
> case 37: /* stwu */
> op->type = MKOP(STORE, u, 4);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 38: /* stb */
> case 39: /* stbu */
> op->type = MKOP(STORE, u, 1);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 40: /* lhz */
> case 41: /* lhzu */
> op->type = MKOP(LOAD, u, 2);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 42: /* lha */
> case 43: /* lhau */
> op->type = MKOP(LOAD, SIGNEXT | u, 2);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 44: /* sth */
> case 45: /* sthu */
> op->type = MKOP(STORE, u, 2);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 46: /* lmw */
> if (ra >= rd)
> break; /* invalid form, ra in range to load
> */
> op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 47: /* stmw */
> op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> #ifdef CONFIG_PPC_FPU
> case 48: /* lfs */
> case 49: /* lfsu */
> op->type = MKOP(LOAD_FP, u | FPCONV, 4);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 50: /* lfd */
> case 51: /* lfdu */
> op->type = MKOP(LOAD_FP, u, 8);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 52: /* stfs */
> case 53: /* stfsu */
> op->type = MKOP(STORE_FP, u | FPCONV, 4);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
>
> case 54: /* stfd */
> case 55: /* stfdu */
> op->type = MKOP(STORE_FP, u, 8);
> - op->ea = dform_ea(instr, regs);
> + op->ea = dform_ea(word, regs);
> break;
> #endif
>
> @@ -2538,14 +2540,14 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> case 56: /* lq */
> if (!((rd & 1) || (rd == ra)))
> op->type = MKOP(LOAD, 0, 16);
> - op->ea = dqform_ea(instr, regs);
> + op->ea = dqform_ea(word, regs);
> break;
> #endif
>
> #ifdef CONFIG_VSX
> case 57: /* lfdp, lxsd, lxssp */
> - op->ea = dsform_ea(instr, regs);
> - switch (instr & 3) {
> + op->ea = dsform_ea(word, regs);
> + switch (word & 3) {
> case 0: /* lfdp */
> if (rd & 1)
> break; /* reg must be even */
> @@ -2569,8 +2571,8 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> #ifdef __powerpc64__
> case 58: /* ld[u], lwa */
> - op->ea = dsform_ea(instr, regs);
> - switch (instr & 3) {
> + op->ea = dsform_ea(word, regs);
> + switch (word & 3) {
> case 0: /* ld */
> op->type = MKOP(LOAD, 0, 8);
> break;
> @@ -2586,16 +2588,16 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> #ifdef CONFIG_VSX
> case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
> - switch (instr & 7) {
> + switch (word & 7) {
> case 0: /* stfdp with LSB of DS field = 0 */
> case 4: /* stfdp with LSB of DS field = 1 */
> - op->ea = dsform_ea(instr, regs);
> + op->ea = dsform_ea(word, regs);
> op->type = MKOP(STORE_FP, 0, 16);
> break;
>
> case 1: /* lxv */
> - op->ea = dqform_ea(instr, regs);
> - if (instr & 8)
> + op->ea = dqform_ea(word, regs);
> + if (word & 8)
> op->reg = rd + 32;
> op->type = MKOP(LOAD_VSX, 0, 16);
> op->element_size = 16;
> @@ -2604,7 +2606,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> case 2: /* stxsd with LSB of DS field = 0 */
> case 6: /* stxsd with LSB of DS field = 1 */
> - op->ea = dsform_ea(instr, regs);
> + op->ea = dsform_ea(word, regs);
> op->reg = rd + 32;
> op->type = MKOP(STORE_VSX, 0, 8);
> op->element_size = 8;
> @@ -2613,7 +2615,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> case 3: /* stxssp with LSB of DS field = 0 */
> case 7: /* stxssp with LSB of DS field = 1 */
> - op->ea = dsform_ea(instr, regs);
> + op->ea = dsform_ea(word, regs);
> op->reg = rd + 32;
> op->type = MKOP(STORE_VSX, 0, 4);
> op->element_size = 8;
> @@ -2621,8 +2623,8 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> break;
>
> case 5: /* stxv */
> - op->ea = dqform_ea(instr, regs);
> - if (instr & 8)
> + op->ea = dqform_ea(word, regs);
> + if (word & 8)
> op->reg = rd + 32;
> op->type = MKOP(STORE_VSX, 0, 16);
> op->element_size = 16;
> @@ -2634,8 +2636,8 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
>
> #ifdef __powerpc64__
> case 62: /* std[u] */
> - op->ea = dsform_ea(instr, regs);
> - switch (instr & 3) {
> + op->ea = dsform_ea(word, regs);
> + switch (word & 3) {
> case 0: /* std */
> op->type = MKOP(STORE, 0, 8);
> break;
> @@ -2663,7 +2665,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 0;
>
> logical_done:
> - if (instr & 1)
> + if (word & 1)
> set_cr0(regs, op);
> logical_done_nocc:
> op->reg = ra;
> @@ -2671,7 +2673,7 @@ int analyse_instr(struct instruction_op *op, const
> struct pt_regs *regs,
> return 1;
>
> arith_done:
> - if (instr & 1)
> + if (word & 1)
> set_cr0(regs, op);
> compute_done:
> op->reg = rd;
> diff --git a/arch/powerpc/lib/test_emulate_step.c
> b/arch/powerpc/lib/test_emulate_step.c
> index 486e057e5be1..d6275a9b8ce6 100644
> --- a/arch/powerpc/lib/test_emulate_step.c
> +++ b/arch/powerpc/lib/test_emulate_step.c
> @@ -851,7 +851,7 @@ static int __init emulate_compute_instr(struct pt_regs
> *regs,
>
> if (analyse_instr(&op, regs, instr) != 1 ||
> GETTYPE(op.type) != COMPUTE) {
> - pr_info("emulation failed, instruction = 0x%08x\n", instr);
> + pr_info("emulation failed, instruction = 0x%08x\n",
> ppc_inst_word(instr));
> return -EFAULT;
> }
>
> @@ -871,7 +871,7 @@ static int __init execute_compute_instr(struct pt_regs
> *regs,
> /* Patch the NOP with the actual instruction */
> patch_instruction_site(&patch__exec_instr, instr);
> if (exec_instr(regs)) {
> - pr_info("execution failed, instruction = 0x%08x\n", instr);
> + pr_info("execution failed, instruction = 0x%08x\n",
> ppc_inst_word(instr));
> return -EFAULT;
> }
>
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index d045e583f1c9..dec522fa8201 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -2871,9 +2871,9 @@ generic_inst_dump(unsigned long adr, long count, int
> praddr,
> dotted = 0;
> last_inst = inst;
> if (praddr)
> - printf(REG" %.8x", adr, inst);
> + printf(REG" %.8x", adr, ppc_inst_word(inst));
> printf("\t");
> - dump_func(inst, adr);
> + dump_func(ppc_inst_word(inst), adr);
> printf("\n");
> }
> return adr - first_adr;
^ permalink raw reply
* [PATCH] powerpc xmon: drop the option `i` in cacheflush
From: Balamuruhan S @ 2020-03-23 11:25 UTC (permalink / raw)
To: mpe
Cc: ravi.bangoria, jniethe5, Balamuruhan S, paulus, sandipan,
naveen.n.rao, linuxppc-dev
Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
designs prior to PowerPC architecture version 2.01 and got obsolete
from version 2.01. Attempt to use of this illegal instruction results
in a hypervisor emulation assistance interrupt. So, drop the option
`i` in cacheflush xmon and continue using `dcbf`.
0:mon> fi
cpu 0x0: Vector: 700 (Program Check) at [c000000003be74a0]
pc: c000000000102030: cacheflush+0x180/0x1a0
lr: c000000000101f3c: cacheflush+0x8c/0x1a0
sp: c000000003be7730
msr: 8000000000081033
current = 0xc0000000035e5c00
paca = 0xc000000001910000 irqmask: 0x03 irq_happened: 0x01
pid = 1025, comm = bash
Linux version 5.6.0-rc5-g5aa19adac (root@ltc-wspoon6) (gcc version 7.4.0
(Ubuntu 7.4.0-1ubuntu1~18.04.1)) #1 SMP Tue Mar 10 04:38:41 CDT 2020
cpu 0x0: Exception 700 (Program Check) in xmon, returning to main loop
[c000000003be7c50] c00000000084abb0 __handle_sysrq+0xf0/0x2a0
[c000000003be7d00] c00000000084b3c0 write_sysrq_trigger+0xb0/0xe0
[c000000003be7d30] c0000000004d1edc proc_reg_write+0x8c/0x130
[c000000003be7d60] c00000000040dc7c __vfs_write+0x3c/0x70
[c000000003be7d80] c000000000410e70 vfs_write+0xd0/0x210
[c000000003be7dd0] c00000000041126c ksys_write+0xdc/0x130
[c000000003be7e20] c00000000000b9d0 system_call+0x5c/0x68
--- Exception: c01 (System Call) at 00007fffa345e420
SP (7ffff0b08ab0) is in userspace
Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
---
arch/powerpc/xmon/xmon.c | 22 ++--------------------
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 0ec9640335bb..d287bf2a54be 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -335,11 +335,6 @@ static inline void cflush(void *p)
asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p));
}
-static inline void cinval(void *p)
-{
- asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p));
-}
-
/**
* write_ciabr() - write the CIABR SPR
* @ciabr: The value to write.
@@ -1791,29 +1786,16 @@ static void prregs(struct pt_regs *fp)
static void cacheflush(void)
{
- int cmd;
unsigned long nflush;
- cmd = inchar();
- if (cmd != 'i')
- termch = cmd;
- scanhex((void *)&adrs);
- if (termch != '\n')
- termch = 0;
nflush = 1;
scanhex(&nflush);
nflush = (nflush + L1_CACHE_BYTES - 1) / L1_CACHE_BYTES;
if (setjmp(bus_error_jmp) == 0) {
catch_memory_errors = 1;
sync();
-
- if (cmd != 'i') {
- for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
- cflush((void *) adrs);
- } else {
- for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
- cinval((void *) adrs);
- }
+ for (; nflush > 0; --nflush, adrs += L1_CACHE_BYTES)
+ cflush((void *)adrs);
sync();
/* wait a little while to see if we get a machine check */
__delay(200);
base-commit: a87b93bdf800a4d7a42d95683624a4516e516b4f
--
2.24.1
^ permalink raw reply related
* Re: [PATCH v8 03/14] powerpc/vas: Define nx_fault_stamp in coprocessor_request_block
From: Michael Ellerman @ 2020-03-23 11:32 UTC (permalink / raw)
To: Nicholas Piggin, Haren Myneni
Cc: mikey, ajd, hch, oohall, sukadev, linuxppc-dev, herbert
In-Reply-To: <1584923120.arc9bj6gmg.astroid@bobo.none>
Nicholas Piggin <npiggin@gmail.com> writes:
> Haren Myneni's on March 19, 2020 4:13 pm:
>>
>> Kernel sets fault address and status in CRB for NX page fault on user
>> space address after processing page fault. User space gets the signal
>> and handles the fault mentioned in CRB by bringing the page in to
>> memory and send NX request again.
>>
>> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>> Signed-off-by: Haren Myneni <haren@linux.ibm.com>
>> ---
>> arch/powerpc/include/asm/icswx.h | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/include/asm/icswx.h b/arch/powerpc/include/asm/icswx.h
>> index 9872f85..b233d1e 100644
>> --- a/arch/powerpc/include/asm/icswx.h
>> +++ b/arch/powerpc/include/asm/icswx.h
>
> "icswx" is not a thing anymore, after 6ff4d3e96652 ("powerpc: Remove old
> unused icswx based coprocessor support").
Yeah that commit ripped out some parts of the previous attempt at a user
visible API for this sort of "coprocessor" stuff. VAS is yet another
attempt to do something useful with most of the same pieces but some
slightly different details.
> I guess NX is reusing some
> things from it, but it would be good to get rid of the cruft and re-name
> this file and and relevant names.
> NX already uses this file, so I guesss that can happen after this series.
A lot of the CRB/CSB stuff is still the same, and P8 still uses icswx.
But I'd be happy if the header was renamed eventually, as icswx is now a
legacy name.
cheers
^ permalink raw reply
* Re: [RFC PATCH 0/3] Use per-CPU temporary mappings for patching
From: Christophe Leroy @ 2020-03-23 11:30 UTC (permalink / raw)
To: Christopher M. Riedl, linuxppc-dev
In-Reply-To: <20200323045205.20314-1-cmr@informatik.wtf>
On 03/23/2020 04:52 AM, Christopher M. Riedl wrote:
> When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create
> temporary mappings when patching itself. These mappings temporarily
> override the strict RWX text protections to permit a write. Currently,
> powerpc allocates a per-CPU VM area for patching. Patching occurs as
> follows:
>
> 1. Map page of text to be patched to per-CPU VM area w/
> PAGE_KERNEL protection
> 2. Patch text
> 3. Remove the temporary mapping
>
> While the VM area is per-CPU, the mapping is actually inserted into the
> kernel page tables. Presumably, this could allow another CPU to access
> the normally write-protected text - either malicously or accidentally -
> via this same mapping if the address of the VM area is known. Ideally,
> the mapping should be kept local to the CPU doing the patching (or any
> other sensitive operations requiring temporarily overriding memory
> protections) [0].
>
> x86 introduced "temporary mm" structs which allow the creation of
> mappings local to a particular CPU [1]. This series intends to bring the
> notion of a temporary mm to powerpc and harden powerpc by using such a
> mapping for patching a kernel with strict RWX permissions.
>
> The first patch introduces the temporary mm struct and API for powerpc
> along with a new function to retrieve a current hw breakpoint.
>
> The second patch uses the `poking_init` init hook added by the x86
> patches to initialize a temporary mm and patching address. The patching
> address is randomized between 0 and DEFAULT_MAP_WINDOW-PAGE_SIZE. The
> upper limit is necessary due to how the hash MMU operates - by default
> the space above DEFAULT_MAP_WINDOW is not available. For now, both hash
> and radix randomize inside this range. The number of possible random
> addresses is dependent on PAGE_SIZE and limited by DEFAULT_MAP_WINDOW.
>
> Bits of entropy with 64K page size on BOOK3S_64:
>
> bits-o-entropy = log2(DEFAULT_MAP_WINDOW_USER64 / PAGE_SIZE)
>
> PAGE_SIZE=64K, DEFAULT_MAP_WINDOW_USER64=128TB
> bits-o-entropy = log2(128TB / 64K)
> bits-o-entropy = 31
>
> Currently, randomization occurs only once during initialization at boot.
>
> The third patch replaces the VM area with the temporary mm in the
> patching code. The page for patching has to be mapped PAGE_SHARED with
> the hash MMU since hash prevents the kernel from accessing userspace
> pages with PAGE_PRIVILEGED bit set. There is on-going work on my side to
> explore if this is actually necessary in the hash codepath.
>
> Testing so far is limited to booting on QEMU (power8 and power9 targets)
> and a POWER8 VM along with setting some simple xmon breakpoints (which
> makes use of code-patching). A POC lkdtm test is in-progress to actually
> exploit the existing vulnerability (ie. the mapping during patching is
> exposed in kernel page tables and accessible by other CPUS) - this will
> accompany a future v1 of this series.
Got following failures on an 8xx. Note that "fault blocked by AP
register !" means an unauthorised access from Kernel to Userspace.
[ 6.113538] ------------[ cut here ]------------
[ 6.117852] Bug: fault blocked by AP register !
[ 6.117977] WARNING: CPU: 0 PID: 1 at
./arch/powerpc/include/asm/nohash/32/kup-8xx.h:67 do_page_fault+0x660/0x6ec
[ 6.132532] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.142484] NIP: c000f148 LR: c000f148 CTR: 00000000
[ 6.147490] REGS: c9023ca8 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.157185] MSR: 00021032 <ME,IR,DR,RI> CR: 39023333 XER: a0002100
[ 6.163553]
[ 6.163553] GPR00: c000f148 c9023d60 c60ec000 00000023 c0924862
0000000b c0921f7a 6c742062
[ 6.163553] GPR08: 00001032 c088e534 00000000 00000004 39023333
00000000 c0003964 00000000
[ 6.163553] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.163553] GPR24: 00000000 00000000 c0730000 00000300 c60dc000
23085188 82000000 c9023db0
[ 6.198284] NIP [c000f148] do_page_fault+0x660/0x6ec
[ 6.203182] LR [c000f148] do_page_fault+0x660/0x6ec
[ 6.207958] Call Trace:
[ 6.210412] [c9023d60] [c000f148] do_page_fault+0x660/0x6ec (unreliable)
[ 6.217037] [c9023da0] [c000e2f0] handle_page_fault+0x8/0x34
[ 6.222684] --- interrupt: 301 at __patch_instruction+0x4/0x2c
[ 6.222684] LR = patch_instruction+0x144/0x324
[ 6.233138] [c9023e68] [c0013408] patch_instruction+0x120/0x324
(unreliable)
[ 6.240108] [c9023ee8] [c00114fc] mmu_mark_initmem_nx+0x44/0x124
[ 6.246039] [c9023f18] [c000f42c] free_initmem+0x20/0x58
[ 6.251292] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.256538] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 6.262605] Instruction dump:
[ 6.265542] 4182fc30 39200002 912a0610 7fa5eb78 38800002 38600007
4801e8a9 38600000
[ 6.273200] 4bfffa78 3c60c06d 38632f0c 4800eb95 <0fe00000> 3860000b
4bfffa60 73490040
[ 6.281034] ---[ end trace 18702eef58b6f5ff ]---
[ 6.285638] ------------[ cut here ]------------
[ 6.290233] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 6.299575] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.309527] NIP: c00134f4 LR: c00134ec CTR: 00000000
[ 6.314533] REGS: c9023db0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.324229] MSR: 00021032 <ME,IR,DR,RI> CR: 55000933 XER: a0002100
[ 6.330597]
[ 6.330597] GPR00: 3d6a4000 c9023e68 c60ec000 00000001 c9023ea8
00000004 c0001188 00000004
[ 6.330597] GPR08: 00000000 00000000 00000000 c53720f0 33000333
00000000 c0003964 00000000
[ 6.330597] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.330597] GPR24: 00000000 00000000 c0730000 00009032 c0734b50
c0730000 c0001188 00000000
[ 6.365337] NIP [c00134f4] patch_instruction+0x20c/0x324
[ 6.370576] LR [c00134ec] patch_instruction+0x204/0x324
[ 6.375690] Call Trace:
[ 6.378150] [c9023e68] [c00134b8] patch_instruction+0x1d0/0x324
(unreliable)
[ 6.385121] [c9023ee8] [c00114fc] mmu_mark_initmem_nx+0x44/0x124
[ 6.391051] [c9023f18] [c000f42c] free_initmem+0x20/0x58
[ 6.396303] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.401550] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 6.407617] Instruction dump:
[ 6.410554] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 6.418212] 7fc3f378 4800086d 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 6.426046] ---[ end trace 18702eef58b6f600 ]---
[ 6.430941] ------------[ cut here ]------------
[ 6.435243] Bug: fault blocked by AP register !
[ 6.435363] WARNING: CPU: 0 PID: 1 at
./arch/powerpc/include/asm/nohash/32/kup-8xx.h:67 do_page_fault+0x660/0x6ec
[ 6.449923] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.459875] NIP: c000f148 LR: c000f148 CTR: 00000000
[ 6.464881] REGS: c9023ca8 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.474577] MSR: 00021032 <ME,IR,DR,RI> CR: 39023333 XER: a0002100
[ 6.480945]
[ 6.480945] GPR00: c000f148 c9023d60 c60ec000 00000023 c0924862
0000000b c0921f7a 6c742062
[ 6.480945] GPR08: 00001032 c088e534 00000000 00000004 39023333
00000000 c0003964 00000000
[ 6.480945] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.480945] GPR24: 00000000 00000000 c0730000 00000300 c60dc000
2308511c 82000000 c9023db0
[ 6.515670] NIP [c000f148] do_page_fault+0x660/0x6ec
[ 6.520573] LR [c000f148] do_page_fault+0x660/0x6ec
[ 6.525350] Call Trace:
[ 6.527804] [c9023d60] [c000f148] do_page_fault+0x660/0x6ec (unreliable)
[ 6.534428] [c9023da0] [c000e2f0] handle_page_fault+0x8/0x34
[ 6.540072] --- interrupt: 301 at __patch_instruction+0x4/0x2c
[ 6.540072] LR = patch_instruction+0x144/0x324
[ 6.550531] [c9023e68] [c0013408] patch_instruction+0x120/0x324
(unreliable)
[ 6.557500] [c9023ee8] [c0011534] mmu_mark_initmem_nx+0x7c/0x124
[ 6.563431] [c9023f18] [c000f42c] free_initmem+0x20/0x58
[ 6.568683] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.573931] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 6.579996] Instruction dump:
[ 6.582934] 4182fc30 39200002 912a0610 7fa5eb78 38800002 38600007
4801e8a9 38600000
[ 6.590592] 4bfffa78 3c60c06d 38632f0c 4800eb95 <0fe00000> 3860000b
4bfffa60 73490040
[ 6.598425] ---[ end trace 18702eef58b6f601 ]---
[ 6.603026] ------------[ cut here ]------------
[ 6.607623] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 6.616968] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.626919] NIP: c00134f4 LR: c00134ec CTR: 00000000
[ 6.631925] REGS: c9023db0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.641621] MSR: 00021032 <ME,IR,DR,RI> CR: 55000933 XER: a0002100
[ 6.647988]
[ 6.647988] GPR00: 2b8ac060 c9023e68 c60ec000 00000001 c9023ea8
00000004 c000111c 00000004
[ 6.647988] GPR08: 00000000 00000000 00000000 c53720f0 33000333
00000000 c0003964 00000000
[ 6.647988] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.647988] GPR24: 00000000 00000000 c0730000 00009032 c0734b50
c0730000 c000111c 00000000
[ 6.682728] NIP [c00134f4] patch_instruction+0x20c/0x324
[ 6.687968] LR [c00134ec] patch_instruction+0x204/0x324
[ 6.693082] Call Trace:
[ 6.695542] [c9023e68] [c00134b8] patch_instruction+0x1d0/0x324
(unreliable)
[ 6.702512] [c9023ee8] [c0011534] mmu_mark_initmem_nx+0x7c/0x124
[ 6.708443] [c9023f18] [c000f42c] free_initmem+0x20/0x58
[ 6.713694] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.718942] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 6.725008] Instruction dump:
[ 6.727946] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 6.735604] 7fc3f378 4800086d 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 6.743437] ---[ end trace 18702eef58b6f602 ]---
[ 6.759669] Freeing unused kernel memory: 496K
[ 6.764014] ------------[ cut here ]------------
[ 6.768382] Bug: fault blocked by AP register !
[ 6.768515] WARNING: CPU: 0 PID: 1 at
./arch/powerpc/include/asm/nohash/32/kup-8xx.h:67 do_page_fault+0x660/0x6ec
[ 6.783065] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.793016] NIP: c000f148 LR: c000f148 CTR: 00000000
[ 6.798022] REGS: c9023c98 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.807717] MSR: 00021032 <ME,IR,DR,RI> CR: 39023333 XER: a0002100
[ 6.814085]
[ 6.814085] GPR00: c000f148 c9023d50 c60ec000 00000023 c0924862
0000000b c0921f7a 6c742062
[ 6.814085] GPR08: 00001032 c088e534 00000000 00000004 39023333
00000000 c0003964 00000000
[ 6.814085] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.814085] GPR24: 00000000 00000000 c0730000 00000300 c60dc000
230852b0 82000000 c9023da0
[ 6.848811] NIP [c000f148] do_page_fault+0x660/0x6ec
[ 6.853714] LR [c000f148] do_page_fault+0x660/0x6ec
[ 6.858491] Call Trace:
[ 6.860944] [c9023d50] [c000f148] do_page_fault+0x660/0x6ec (unreliable)
[ 6.867569] [c9023d90] [c000e2f0] handle_page_fault+0x8/0x34
[ 6.873215] --- interrupt: 301 at __patch_instruction+0x4/0x2c
[ 6.873215] LR = patch_instruction+0x144/0x324
[ 6.883670] [c9023e58] [c0013408] patch_instruction+0x120/0x324
(unreliable)
[ 6.890640] [c9023ed8] [c0011624] mmu_mark_rodata_ro+0x48/0xf8
[ 6.896401] [c9023f08] [c000fe50] mark_rodata_ro+0xc4/0xd8
[ 6.901824] [c9023f28] [c0003998] kernel_init+0x34/0x130
[ 6.907072] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 6.913137] Instruction dump:
[ 6.916074] 4182fc30 39200002 912a0610 7fa5eb78 38800002 38600007
4801e8a9 38600000
[ 6.923732] 4bfffa78 3c60c06d 38632f0c 4800eb95 <0fe00000> 3860000b
4bfffa60 73490040
[ 6.931565] ---[ end trace 18702eef58b6f603 ]---
[ 6.936166] ------------[ cut here ]------------
[ 6.940763] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 6.950108] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3524
[ 6.960059] NIP: c00134f4 LR: c00134ec CTR: 00000000
[ 6.965067] REGS: c9023da0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.974761] MSR: 00021032 <ME,IR,DR,RI> CR: 99000333 XER: a0002100
[ 6.981129]
[ 6.981129] GPR00: 3d6aff80 c9023e58 c60ec000 00000001 c9023e98
00000004 c00012b0 00000004
[ 6.981129] GPR08: 00000000 fffffffe 00000000 00000000 39000335
00000000 c0003964 00000000
[ 6.981129] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.981129] GPR24: 00000000 00000000 c0730000 00009032 c0734b50
c0730000 c00012b0 00000000
[ 7.015870] NIP [c00134f4] patch_instruction+0x20c/0x324
[ 7.021109] LR [c00134ec] patch_instruction+0x204/0x324
[ 7.026222] Call Trace:
[ 7.028683] [c9023e58] [c00134b8] patch_instruction+0x1d0/0x324
(unreliable)
[ 7.035653] [c9023ed8] [c0011624] mmu_mark_rodata_ro+0x48/0xf8
[ 7.041415] [c9023f08] [c000fe50] mark_rodata_ro+0xc4/0xd8
[ 7.046835] [c9023f28] [c0003998] kernel_init+0x34/0x130
[ 7.052083] [c9023f38] [c000e184] ret_from_kernel_thread+0x14/0x1c
[ 7.058149] Instruction dump:
[ 7.061086] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 7.068744] 7fc3f378 4800086d 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 7.076578] ---[ end trace 18702eef58b6f604 ]---
Christophe
^ permalink raw reply
* Re: [PATCH v8 04/14] powerpc/vas: Alloc and setup IRQ and trigger port address
From: Cédric Le Goater @ 2020-03-23 9:27 UTC (permalink / raw)
To: Haren Myneni, mpe
Cc: mikey, herbert, Frederic Barrat, npiggin, hch, oohall, sukadev,
linuxppc-dev, ajd
In-Reply-To: <396db62b-5342-a1b3-eade-a219afd98fc7@kaod.org>
On 3/23/20 10:06 AM, Cédric Le Goater wrote:
> On 3/19/20 7:14 AM, Haren Myneni wrote:
>>
>> Alloc IRQ and get trigger port address for each VAS instance. Kernel
>> register this IRQ per VAS instance and sets this port for each send
>> window. NX interrupts the kernel when it sees page fault.
>
> I don't understand why this is not done by the OPAL driver for each VAS
> of the system. Is the VAS unit very different from OpenCAPI regarding
> the fault ?
I checked the previous patchsets and I see that v3 was more like I expected
it: one interrupt for faults allocated by the skiboot driver and exposed
in the DT.
What made you change your mind ?
This version is hijacking the lowlevel routines of the XIVE irqchip which
is not the best approach. OCXL is doing that because it needs to allocate
interrupts for the user space processes using the AFU and we should rework
that part.
However, the translation fault interrupt is allocated by skiboot.
Sorry for the noise, I would like to understand more how this works. I also
have passthrough in mind.
C.
^ permalink raw reply
* Re: [PATCH v4 3/9] powerpc/vas: Add VAS user space API
From: Michael Ellerman @ 2020-03-23 12:15 UTC (permalink / raw)
To: Daniel Axtens, Haren Myneni, herbert
Cc: mikey, sukadev, linuxppc-dev, linux-crypto, npiggin
In-Reply-To: <878sjrwm72.fsf@dja-thinkpad.axtens.net>
Daniel Axtens <dja@axtens.net> writes:
> Haren Myneni <haren@linux.ibm.com> writes:
>
>> On power9, userspace can send GZIP compression requests directly to NX
>> once kernel establishes NX channel / window with VAS. This patch provides
>> user space API which allows user space to establish channel using open
>> VAS_TX_WIN_OPEN ioctl, mmap and close operations.
>>
>> Each window corresponds to file descriptor and application can open
>> multiple windows. After the window is opened, VAS_TX_WIN_OPEN icoctl to
>> open a window on specific VAS instance, mmap() system call to map
>> the hardware address of engine's request queue into the application's
>> virtual address space.
>>
>> Then the application can then submit one or more requests to the the
>> engine by using the copy/paste instructions and pasting the CRBs to
>> the virtual address (aka paste_address) returned by mmap().
>>
>> Only NX GZIP coprocessor type is supported right now and allow GZIP
>> engine access via /dev/crypto/nx-gzip device node.
>>
>> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>> Signed-off-by: Haren Myneni <haren@linux.ibm.com>
>> ---
>> arch/powerpc/include/asm/vas.h | 11 ++
>> arch/powerpc/platforms/powernv/Makefile | 2 +-
>> arch/powerpc/platforms/powernv/vas-api.c | 257 ++++++++++++++++++++++++++++
>> arch/powerpc/platforms/powernv/vas-window.c | 6 +-
>> arch/powerpc/platforms/powernv/vas.h | 2 +
>> 5 files changed, 274 insertions(+), 4 deletions(-)
>> create mode 100644 arch/powerpc/platforms/powernv/vas-api.c
>>
>> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
>> index f93e6b0..e064953 100644
>> --- a/arch/powerpc/include/asm/vas.h
>> +++ b/arch/powerpc/include/asm/vas.h
>> @@ -163,4 +163,15 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
>> */
>> int vas_paste_crb(struct vas_window *win, int offset, bool re);
>>
>> +/*
>> + * Register / unregister coprocessor type to VAS API which will be exported
>> + * to user space. Applications can use this API to open / close window
>> + * which can be used to send / receive requests directly to cooprcessor.
>> + *
>> + * Only NX GZIP coprocessor type is supported now, but this API can be
>> + * used for others in future.
>> + */
>> +int vas_register_coproc_api(struct module *mod);
>> +void vas_unregister_coproc_api(void);
>> +
>> #endif /* __ASM_POWERPC_VAS_H */
>> diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
>> index 395789f..fe3f0fb 100644
>> --- a/arch/powerpc/platforms/powernv/Makefile
>> +++ b/arch/powerpc/platforms/powernv/Makefile
>> @@ -17,7 +17,7 @@ obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o
>> obj-$(CONFIG_OPAL_PRD) += opal-prd.o
>> obj-$(CONFIG_PERF_EVENTS) += opal-imc.o
>> obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o
>> -obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o
>> +obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o vas-api.o
>> obj-$(CONFIG_OCXL_BASE) += ocxl.o
>> obj-$(CONFIG_SCOM_DEBUGFS) += opal-xscom.o
>> obj-$(CONFIG_PPC_SECURE_BOOT) += opal-secvar.o
>> diff --git a/arch/powerpc/platforms/powernv/vas-api.c b/arch/powerpc/platforms/powernv/vas-api.c
>> new file mode 100644
>> index 0000000..7d049af
>> --- /dev/null
>> +++ b/arch/powerpc/platforms/powernv/vas-api.c
>> @@ -0,0 +1,257 @@
...
>> +
>> +static int coproc_mmap(struct file *fp, struct vm_area_struct *vma)
>> +{
>> + struct vas_window *txwin = fp->private_data;
>> + unsigned long pfn;
>> + u64 paste_addr;
>> + pgprot_t prot;
>> + int rc;
>> +
>> + if ((vma->vm_end - vma->vm_start) > PAGE_SIZE) {
>
> I think you said this should be 4096 rather than 64k, regardless of what
> PAGE_SIZE you are compiled with?
You can't mmap less than a page, a page is PAGE_SIZE bytes.
So if that checked for 4K explicitly it would prevent mmap on 64K
kernels always, which seems like not what you want?
cheers
^ permalink raw reply
* Re: [PATCH 1/2] dma-mapping: add a dma_ops_bypass flag to struct device
From: Robin Murphy @ 2020-03-23 12:14 UTC (permalink / raw)
To: Christoph Hellwig, iommu@lists.linux-foundation.org,
Alexey Kardashevskiy
Cc: Greg Kroah-Hartman, Joerg Roedel, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org, Lu Baolu
In-Reply-To: <20200320141640.366360-2-hch@lst.de>
On 2020-03-20 2:16 pm, Christoph Hellwig wrote:
> Several IOMMU drivers have a bypass mode where they can use a direct
> mapping if the devices DMA mask is large enough. Add generic support
> to the core dma-mapping code to do that to switch those drivers to
> a common solution.
Hmm, this is _almost_, but not quite the same as the case where drivers
are managing their own IOMMU mappings, but still need to use streaming
DMA for cache maintenance on the underlying pages. For that we need the
ops bypass to be a "true" bypass and also avoid SWIOTLB regardless of
the device's DMA mask. That behaviour should in fact be fine for the
opportunistic bypass case here as well, since the mask being "big
enough" implies by definition that this should never need to bounce either.
For the (hopefully less common) third case where, due to groups or user
overrides, we end up giving an identity DMA domain to a device with
limited DMA masks which _does_ need SWIOTLB, I'd like to think we can
solve that by not giving the device IOMMU DMA ops in the first place,
such that it never needs to engage the bypass mechanism at all.
Thoughts?
Robin.
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> include/linux/device.h | 6 ++++++
> include/linux/dma-mapping.h | 30 ++++++++++++++++++------------
> kernel/dma/mapping.c | 36 +++++++++++++++++++++++++++---------
> 3 files changed, 51 insertions(+), 21 deletions(-)
>
> diff --git a/include/linux/device.h b/include/linux/device.h
> index 0cd7c647c16c..09be8bb2c4a6 100644
> --- a/include/linux/device.h
> +++ b/include/linux/device.h
> @@ -525,6 +525,11 @@ struct dev_links_info {
> * sync_state() callback.
> * @dma_coherent: this particular device is dma coherent, even if the
> * architecture supports non-coherent devices.
> + * @dma_ops_bypass: If set to %true then the dma_ops are bypassed for the
> + * streaming DMA operations (->map_* / ->unmap_* / ->sync_*),
> + * and optionall (if the coherent mask is large enough) also
> + * for dma allocations. This flag is managed by the dma ops
> + * instance from ->dma_supported.
> *
> * At the lowest level, every device in a Linux system is represented by an
> * instance of struct device. The device structure contains the information
> @@ -625,6 +630,7 @@ struct device {
> defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL)
> bool dma_coherent:1;
> #endif
> + bool dma_ops_bypass : 1;
> };
>
> static inline struct device *kobj_to_dev(struct kobject *kobj)
> diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
> index 330ad58fbf4d..c3af0cf5e435 100644
> --- a/include/linux/dma-mapping.h
> +++ b/include/linux/dma-mapping.h
> @@ -188,9 +188,15 @@ static inline int dma_mmap_from_global_coherent(struct vm_area_struct *vma,
> }
> #endif /* CONFIG_DMA_DECLARE_COHERENT */
>
> -static inline bool dma_is_direct(const struct dma_map_ops *ops)
> +/*
> + * Check if the devices uses a direct mapping for streaming DMA operations.
> + * This allows IOMMU drivers to set a bypass mode if the DMA mask is large
> + * enough.
> + */
> +static inline bool dma_map_direct(struct device *dev,
> + const struct dma_map_ops *ops)
> {
> - return likely(!ops);
> + return likely(!ops) || dev->dma_ops_bypass;
> }
>
> /*
> @@ -279,7 +285,7 @@ static inline dma_addr_t dma_map_page_attrs(struct device *dev,
> dma_addr_t addr;
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
> else
> addr = ops->map_page(dev, page, offset, size, dir, attrs);
> @@ -294,7 +300,7 @@ static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_unmap_page(dev, addr, size, dir, attrs);
> else if (ops->unmap_page)
> ops->unmap_page(dev, addr, size, dir, attrs);
> @@ -313,7 +319,7 @@ static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
> int ents;
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> ents = dma_direct_map_sg(dev, sg, nents, dir, attrs);
> else
> ents = ops->map_sg(dev, sg, nents, dir, attrs);
> @@ -331,7 +337,7 @@ static inline void dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg
>
> BUG_ON(!valid_dma_direction(dir));
> debug_dma_unmap_sg(dev, sg, nents, dir);
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_unmap_sg(dev, sg, nents, dir, attrs);
> else if (ops->unmap_sg)
> ops->unmap_sg(dev, sg, nents, dir, attrs);
> @@ -352,7 +358,7 @@ static inline dma_addr_t dma_map_resource(struct device *dev,
> if (WARN_ON_ONCE(pfn_valid(PHYS_PFN(phys_addr))))
> return DMA_MAPPING_ERROR;
>
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> addr = dma_direct_map_resource(dev, phys_addr, size, dir, attrs);
> else if (ops->map_resource)
> addr = ops->map_resource(dev, phys_addr, size, dir, attrs);
> @@ -368,7 +374,7 @@ static inline void dma_unmap_resource(struct device *dev, dma_addr_t addr,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (!dma_is_direct(ops) && ops->unmap_resource)
> + if (!dma_map_direct(dev, ops) && ops->unmap_resource)
> ops->unmap_resource(dev, addr, size, dir, attrs);
> debug_dma_unmap_resource(dev, addr, size, dir);
> }
> @@ -380,7 +386,7 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t addr,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_sync_single_for_cpu(dev, addr, size, dir);
> else if (ops->sync_single_for_cpu)
> ops->sync_single_for_cpu(dev, addr, size, dir);
> @@ -394,7 +400,7 @@ static inline void dma_sync_single_for_device(struct device *dev,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_sync_single_for_device(dev, addr, size, dir);
> else if (ops->sync_single_for_device)
> ops->sync_single_for_device(dev, addr, size, dir);
> @@ -408,7 +414,7 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_sync_sg_for_cpu(dev, sg, nelems, dir);
> else if (ops->sync_sg_for_cpu)
> ops->sync_sg_for_cpu(dev, sg, nelems, dir);
> @@ -422,7 +428,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> dma_direct_sync_sg_for_device(dev, sg, nelems, dir);
> else if (ops->sync_sg_for_device)
> ops->sync_sg_for_device(dev, sg, nelems, dir);
> diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c
> index 12ff766ec1fa..fdea45574345 100644
> --- a/kernel/dma/mapping.c
> +++ b/kernel/dma/mapping.c
> @@ -105,6 +105,24 @@ void *dmam_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
> }
> EXPORT_SYMBOL(dmam_alloc_attrs);
>
> +static bool dma_alloc_direct(struct device *dev, const struct dma_map_ops *ops)
> +{
> + if (!ops)
> + return true;
> +
> + /*
> + * Allows IOMMU drivers to bypass dynamic translations if the DMA mask
> + * is large enough.
> + */
> + if (dev->dma_ops_bypass) {
> + if (min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit) >=
> + dma_direct_get_required_mask(dev))
> + return true;
> + }
> +
> + return false;
> +}
> +
> /*
> * Create scatter-list for the already allocated DMA buffer.
> */
> @@ -138,7 +156,7 @@ int dma_get_sgtable_attrs(struct device *dev, struct sg_table *sgt,
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> return dma_direct_get_sgtable(dev, sgt, cpu_addr, dma_addr,
> size, attrs);
> if (!ops->get_sgtable)
> @@ -206,7 +224,7 @@ bool dma_can_mmap(struct device *dev)
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> return dma_direct_can_mmap(dev);
> return ops->mmap != NULL;
> }
> @@ -231,7 +249,7 @@ int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> return dma_direct_mmap(dev, vma, cpu_addr, dma_addr, size,
> attrs);
> if (!ops->mmap)
> @@ -244,7 +262,7 @@ u64 dma_get_required_mask(struct device *dev)
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> return dma_direct_get_required_mask(dev);
> if (ops->get_required_mask)
> return ops->get_required_mask(dev);
> @@ -275,7 +293,7 @@ void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
> /* let the implementation decide on the zone to allocate from: */
> flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
>
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
> else if (ops->alloc)
> cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
> @@ -307,7 +325,7 @@ void dma_free_attrs(struct device *dev, size_t size, void *cpu_addr,
> return;
>
> debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> dma_direct_free(dev, size, cpu_addr, dma_handle, attrs);
> else if (ops->free)
> ops->free(dev, size, cpu_addr, dma_handle, attrs);
> @@ -318,7 +336,7 @@ int dma_supported(struct device *dev, u64 mask)
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> - if (dma_is_direct(ops))
> + if (!ops)
> return dma_direct_supported(dev, mask);
> if (!ops->dma_supported)
> return 1;
> @@ -374,7 +392,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
>
> BUG_ON(!valid_dma_direction(dir));
>
> - if (dma_is_direct(ops))
> + if (dma_alloc_direct(dev, ops))
> arch_dma_cache_sync(dev, vaddr, size, dir);
> else if (ops->cache_sync)
> ops->cache_sync(dev, vaddr, size, dir);
> @@ -386,7 +404,7 @@ size_t dma_max_mapping_size(struct device *dev)
> const struct dma_map_ops *ops = get_dma_ops(dev);
> size_t size = SIZE_MAX;
>
> - if (dma_is_direct(ops))
> + if (dma_map_direct(dev, ops))
> size = dma_direct_max_mapping_size(dev);
> else if (ops && ops->max_mapping_size)
> size = ops->max_mapping_size(dev);
>
^ permalink raw reply
* Re: [PATCH] powerpc xmon: drop the option `i` in cacheflush
From: Segher Boessenkool @ 2020-03-23 12:46 UTC (permalink / raw)
To: Balamuruhan S
Cc: ravi.bangoria, paulus, sandipan, jniethe5, naveen.n.rao,
linuxppc-dev
In-Reply-To: <20200323112548.1077440-1-bala24@linux.ibm.com>
On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
> Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
> designs prior to PowerPC architecture version 2.01 and got obsolete
> from version 2.01.
It was added back in 2.03. It also exists in 64-bit designs (using
category embedded), in 2.07 still even.
Segher
^ permalink raw reply
* Re: [PATCH 1/2] dma-mapping: add a dma_ops_bypass flag to struct device
From: Christoph Hellwig @ 2020-03-23 12:55 UTC (permalink / raw)
To: Robin Murphy
Cc: Alexey Kardashevskiy, Greg Kroah-Hartman, Joerg Roedel,
linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
linuxppc-dev@lists.ozlabs.org, Christoph Hellwig, Lu Baolu
In-Reply-To: <0a6003e5-8003-4509-4014-4b286d5e8fe0@arm.com>
On Mon, Mar 23, 2020 at 12:14:08PM +0000, Robin Murphy wrote:
> On 2020-03-20 2:16 pm, Christoph Hellwig wrote:
>> Several IOMMU drivers have a bypass mode where they can use a direct
>> mapping if the devices DMA mask is large enough. Add generic support
>> to the core dma-mapping code to do that to switch those drivers to
>> a common solution.
>
> Hmm, this is _almost_, but not quite the same as the case where drivers are
> managing their own IOMMU mappings, but still need to use streaming DMA for
> cache maintenance on the underlying pages.
In that case they should simply not call the DMA API at all. We'll just
need versions of the cache maintainance APIs that tie in with the raw
IOMMU API.
> For that we need the ops bypass
> to be a "true" bypass and also avoid SWIOTLB regardless of the device's DMA
> mask. That behaviour should in fact be fine for the opportunistic bypass
> case here as well, since the mask being "big enough" implies by definition
> that this should never need to bounce either.
In practice it does. But that means adding yet another code path
vs the simple direct call to dma_direct_* vs calling the DMA ops
which I'd rather avoid.
^ permalink raw reply
* Re: [PATCH] powerpc xmon: drop the option `i` in cacheflush
From: Naveen N. Rao @ 2020-03-23 13:22 UTC (permalink / raw)
To: Balamuruhan S, Segher Boessenkool
Cc: ravi.bangoria, jniethe5, paulus, sandipan, linuxppc-dev
In-Reply-To: <20200323124630.GP22482@gate.crashing.org>
Segher Boessenkool wrote:
> On Mon, Mar 23, 2020 at 04:55:48PM +0530, Balamuruhan S wrote:
>> Data Cache Block Invalidate (dcbi) instruction implemented in 32-bit
>> designs prior to PowerPC architecture version 2.01 and got obsolete
>> from version 2.01.
>
> It was added back in 2.03. It also exists in 64-bit designs (using
> category embedded), in 2.07 still even.
Indeed, it has been part of Book3e.
It isn't clear if this is still useful in this context (xmon) though,
since 'dcbf' seems to be equivalent in most respects. At the very least,
we should restrict this to Book3e, if it is of value there.
- Naveen
^ permalink raw reply
* Re: [PATCH] mm/debug: Add tests validating arch page table helpers for core features
From: Anshuman Khandual @ 2020-03-23 13:26 UTC (permalink / raw)
To: Christophe Leroy
Cc: Catalin Marinas, Heiko Carstens, linux-mm, Paul Mackerras,
H. Peter Anvin, linux-riscv, Will Deacon, linux-arch, linux-s390,
x86, Mike Rapoport, Christian Borntraeger, Ingo Molnar,
linux-snps-arc, Vasily Gorbik, Borislav Petkov, Paul Walmsley,
Kirill A . Shutemov, Thomas Gleixner, linux-arm-kernel,
Vineet Gupta, linux-kernel, Palmer Dabbelt, Andrew Morton,
linuxppc-dev
In-Reply-To: <20200302222443.Horde.3Vn7_PzcWbAADKFWloR-kw8@messagerie.si.c-s.fr>
On 03/03/2020 02:54 AM, Christophe Leroy wrote:
> Anshuman Khandual <anshuman.khandual@arm.com> a écrit :
>
>> On 02/27/2020 04:59 PM, Christophe Leroy wrote:
>>>
>>>
>>> Le 27/02/2020 à 11:33, Anshuman Khandual a écrit :
>>>> This adds new tests validating arch page table helpers for these following
>>>> core memory features. These tests create and test specific mapping types at
>>>> various page table levels.
>>>>
>>>> * SPECIAL mapping
>>>> * PROTNONE mapping
>>>> * DEVMAP mapping
>>>> * SOFTDIRTY mapping
>>>> * SWAP mapping
>>>> * MIGRATION mapping
>>>> * HUGETLB mapping
>>>> * THP mapping
>>>>
>>>> Cc: Andrew Morton <akpm@linux-foundation.org>
>>>> Cc: Mike Rapoport <rppt@linux.ibm.com>
>>>> Cc: Vineet Gupta <vgupta@synopsys.com>
>>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>>> Cc: Will Deacon <will@kernel.org>
>>>> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>> Cc: Paul Mackerras <paulus@samba.org>
>>>> Cc: Michael Ellerman <mpe@ellerman.id.au>
>>>> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
>>>> Cc: Vasily Gorbik <gor@linux.ibm.com>
>>>> Cc: Christian Borntraeger <borntraeger@de.ibm.com>
>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>> Cc: Ingo Molnar <mingo@redhat.com>
>>>> Cc: Borislav Petkov <bp@alien8.de>
>>>> Cc: "H. Peter Anvin" <hpa@zytor.com>
>>>> Cc: Kirill A. Shutemov <kirill@shutemov.name>
>>>> Cc: Paul Walmsley <paul.walmsley@sifive.com>
>>>> Cc: Palmer Dabbelt <palmer@dabbelt.com>
>>>> Cc: linux-snps-arc@lists.infradead.org
>>>> Cc: linux-arm-kernel@lists.infradead.org
>>>> Cc: linuxppc-dev@lists.ozlabs.org
>>>> Cc: linux-s390@vger.kernel.org
>>>> Cc: linux-riscv@lists.infradead.org
>>>> Cc: x86@kernel.org
>>>> Cc: linux-arch@vger.kernel.org
>>>> Cc: linux-kernel@vger.kernel.org
>>>> Suggested-by: Catalin Marinas <catalin.marinas@arm.com>
>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>>>> ---
>>>> Tested on arm64 and x86 platforms without any test failures. But this has
>>>> only been built tested on several other platforms. Individual tests need
>>>> to be verified on all current enabling platforms for the test i.e s390,
>>>> ppc32, arc etc.
>>>>
>>>> This patch must be applied on v5.6-rc3 after these patches
>>>>
>>>> 1. https://patchwork.kernel.org/patch/11385057/
>>>> 2. https://patchwork.kernel.org/patch/11407715/
>>>>
>>>> OR
>>>>
>>>> This patch must be applied on linux-next (next-20200227) after this patch
>>>>
>>>> 2. https://patchwork.kernel.org/patch/11407715/
>>>>
>>>> mm/debug_vm_pgtable.c | 310 +++++++++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 309 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>>>> index 96dd7d574cef..3fb90d5b604e 100644
>>>> --- a/mm/debug_vm_pgtable.c
>>>> +++ b/mm/debug_vm_pgtable.c
>>>> @@ -41,6 +41,44 @@
>>>> * wrprotect(entry) = A write protected and not a write entry
>>>> * pxx_bad(entry) = A mapped and non-table entry
>>>> * pxx_same(entry1, entry2) = Both entries hold the exact same value
>>>> + *
>>>> + * Specific feature operations
>>>> + *
>>>> + * pte_mkspecial(entry) = Creates a special entry at PTE level
>>>> + * pte_special(entry) = Tests a special entry at PTE level
>>>> + *
>>>> + * pte_protnone(entry) = Tests a no access entry at PTE level
>>>> + * pmd_protnone(entry) = Tests a no access entry at PMD level
>>>> + *
>>>> + * pte_mkdevmap(entry) = Creates a device entry at PTE level
>>>> + * pmd_mkdevmap(entry) = Creates a device entry at PMD level
>>>> + * pud_mkdevmap(entry) = Creates a device entry at PUD level
>>>> + * pte_devmap(entry) = Tests a device entry at PTE level
>>>> + * pmd_devmap(entry) = Tests a device entry at PMD level
>>>> + * pud_devmap(entry) = Tests a device entry at PUD level
>>>> + *
>>>> + * pte_mksoft_dirty(entry) = Creates a soft dirty entry at PTE level
>>>> + * pmd_mksoft_dirty(entry) = Creates a soft dirty entry at PMD level
>>>> + * pte_swp_mksoft_dirty(entry) = Creates a soft dirty swap entry at PTE level
>>>> + * pmd_swp_mksoft_dirty(entry) = Creates a soft dirty swap entry at PMD level
>>>> + * pte_soft_dirty(entry) = Tests a soft dirty entry at PTE level
>>>> + * pmd_soft_dirty(entry) = Tests a soft dirty entry at PMD level
>>>> + * pte_swp_soft_dirty(entry) = Tests a soft dirty swap entry at PTE level
>>>> + * pmd_swp_soft_dirty(entry) = Tests a soft dirty swap entry at PMD level
>>>> + * pte_clear_soft_dirty(entry) = Clears a soft dirty entry at PTE level
>>>> + * pmd_clear_soft_dirty(entry) = Clears a soft dirty entry at PMD level
>>>> + * pte_swp_clear_soft_dirty(entry) = Clears a soft dirty swap entry at PTE level
>>>> + * pmd_swp_clear_soft_dirty(entry) = Clears a soft dirty swap entry at PMD level
>>>> + *
>>>> + * pte_mkhuge(entry) = Creates a HugeTLB entry at given level
>>>> + * pte_huge(entry) = Tests a HugeTLB entry at given level
>>>> + *
>>>> + * pmd_trans_huge(entry) = Tests a trans huge page at PMD level
>>>> + * pud_trans_huge(entry) = Tests a trans huge page at PUD level
>>>> + * pmd_present(entry) = Tests an entry points to memory at PMD level
>>>> + * pud_present(entry) = Tests an entry points to memory at PUD level
>>>> + * pmd_mknotpresent(entry) = Invalidates an PMD entry for MMU
>>>> + * pud_mknotpresent(entry) = Invalidates an PUD entry for MMU
>>>> */
>>>> #define VMFLAGS (VM_READ|VM_WRITE|VM_EXEC)
>>>> @@ -287,6 +325,233 @@ static void __init pmd_populate_tests(struct mm_struct *mm, pmd_t *pmdp,
>>>> WARN_ON(pmd_bad(pmd));
>>>> }
>>>> +#ifdef CONFIG_ARCH_HAS_PTE_SPECIAL
>>>
>>> Can we avoid ifdefs unless necessary ?
>>>
>>> In mm/memory.c I see things like the following, it means pte_special() always exist and a #ifdef is not necessary.
>>
>> True, #ifdef here can be dropped here, done.
>>
>>>
>>> if (IS_ENABLED(CONFIG_ARCH_HAS_PTE_SPECIAL)) {
>>> if (likely(!pte_special(pte)))
>>> goto check_pfn;
>>> if (vma->vm_ops && vma->vm_ops->find_special_page)
>>> return vma->vm_ops->find_special_page(vma, addr);
>>> if (vma->vm_flags & (VM_PFNMAP | VM_MIXEDMAP))
>>> return NULL;
>>> if (is_zero_pfn(pfn))
>>> return NULL;
>>> if (pte_devmap(pte))
>>> return NULL;
>>>
>>> print_bad_pte(vma, addr, pte, NULL);
>>> return NULL;
>>> }
>>>
>>>> +static void __init pte_special_tests(unsigned long pfn, pgprot_t prot)
>>>> +{
>>>> + pte_t pte = pfn_pte(pfn, prot);
>>>> +
>>>> + WARN_ON(!pte_special(pte_mkspecial(pte)));
>>>> +}
>>>> +#else
>>>> +static void __init pte_special_tests(unsigned long pfn, pgprot_t prot) { }
>>>> +#endif
>>>> +
>>>> +#ifdef CONFIG_NUMA_BALANCING
>>>
>>> Same here, this ifdef shouldn't be necessary because in /include/asm-generic/pgtable.h we have the following, so a if (IS_ENABLED()) should be enough.
>>>
>>> #ifndef CONFIG_NUMA_BALANCING
>>> /*
>>> * Technically a PTE can be PROTNONE even when not doing NUMA balancing but
>>> * the only case the kernel cares is for NUMA balancing and is only ever set
>>> * when the VMA is accessible. For PROT_NONE VMAs, the PTEs are not marked
>>> * _PAGE_PROTNONE so by by default, implement the helper as "always no". It
>>> * is the responsibility of the caller to distinguish between PROT_NONE
>>> * protections and NUMA hinting fault protections.
>>> */
>>> static inline int pte_protnone(pte_t pte)
>>> {
>>> return 0;
>>> }
>>>
>>> static inline int pmd_protnone(pmd_t pmd)
>>> {
>>> return 0;
>>> }
>>> #endif /* CONFIG_NUMA_BALANCING */
>>
>> True, #ifdef here can be dropped, done. There is something I had missed
>> before, pfn_pmd() requires #ifdef CONFIG_TRANSPARENT_HUGEPAGE instead. We
>> need a pmd_t here with given prot. We cannot go via pfn_pte() followed by
>> pte_pmd(), as the later is platform specific and not available in general.
>
> As many things require CONFIG_TRANSPARENT_HUGEPAGE, maybe it would be worth creating an additional C file with the related functions and build it conditionnaly to CONFIG_TRANSPARENT_HUGEPAGE
>
Apologies for the delayed response here. Any split in the test will break it's
monolithic structure which is not desirable. Also lack of an explicit dependency
between HAVE_ARCH_TRANSPARENT_HUGEPAGE and HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD
makes it difficult to group together fallback dummy stubs from various THP
related test functions here. I am planning to re-spin this patch sooner with
some more tests while also accommodating other previous comments. Hence, will
probably note down this aspect which can then be discussed further if required.
> Christophe
^ permalink raw reply
* Re: [PATCH v4 3/9] powerpc/vas: Add VAS user space API
From: Daniel Axtens @ 2020-03-23 13:32 UTC (permalink / raw)
To: Michael Ellerman, Haren Myneni, herbert
Cc: mikey, sukadev, linuxppc-dev, linux-crypto, npiggin
In-Reply-To: <878sjrclmz.fsf@mpe.ellerman.id.au>
Michael Ellerman <mpe@ellerman.id.au> writes:
> Daniel Axtens <dja@axtens.net> writes:
>> Haren Myneni <haren@linux.ibm.com> writes:
>>
>>> On power9, userspace can send GZIP compression requests directly to NX
>>> once kernel establishes NX channel / window with VAS. This patch provides
>>> user space API which allows user space to establish channel using open
>>> VAS_TX_WIN_OPEN ioctl, mmap and close operations.
>>>
>>> Each window corresponds to file descriptor and application can open
>>> multiple windows. After the window is opened, VAS_TX_WIN_OPEN icoctl to
>>> open a window on specific VAS instance, mmap() system call to map
>>> the hardware address of engine's request queue into the application's
>>> virtual address space.
>>>
>>> Then the application can then submit one or more requests to the the
>>> engine by using the copy/paste instructions and pasting the CRBs to
>>> the virtual address (aka paste_address) returned by mmap().
>>>
>>> Only NX GZIP coprocessor type is supported right now and allow GZIP
>>> engine access via /dev/crypto/nx-gzip device node.
>>>
>>> Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
>>> Signed-off-by: Haren Myneni <haren@linux.ibm.com>
>>> ---
>>> arch/powerpc/include/asm/vas.h | 11 ++
>>> arch/powerpc/platforms/powernv/Makefile | 2 +-
>>> arch/powerpc/platforms/powernv/vas-api.c | 257 ++++++++++++++++++++++++++++
>>> arch/powerpc/platforms/powernv/vas-window.c | 6 +-
>>> arch/powerpc/platforms/powernv/vas.h | 2 +
>>> 5 files changed, 274 insertions(+), 4 deletions(-)
>>> create mode 100644 arch/powerpc/platforms/powernv/vas-api.c
>>>
>>> diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
>>> index f93e6b0..e064953 100644
>>> --- a/arch/powerpc/include/asm/vas.h
>>> +++ b/arch/powerpc/include/asm/vas.h
>>> @@ -163,4 +163,15 @@ struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
>>> */
>>> int vas_paste_crb(struct vas_window *win, int offset, bool re);
>>>
>>> +/*
>>> + * Register / unregister coprocessor type to VAS API which will be exported
>>> + * to user space. Applications can use this API to open / close window
>>> + * which can be used to send / receive requests directly to cooprcessor.
>>> + *
>>> + * Only NX GZIP coprocessor type is supported now, but this API can be
>>> + * used for others in future.
>>> + */
>>> +int vas_register_coproc_api(struct module *mod);
>>> +void vas_unregister_coproc_api(void);
>>> +
>>> #endif /* __ASM_POWERPC_VAS_H */
>>> diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
>>> index 395789f..fe3f0fb 100644
>>> --- a/arch/powerpc/platforms/powernv/Makefile
>>> +++ b/arch/powerpc/platforms/powernv/Makefile
>>> @@ -17,7 +17,7 @@ obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o
>>> obj-$(CONFIG_OPAL_PRD) += opal-prd.o
>>> obj-$(CONFIG_PERF_EVENTS) += opal-imc.o
>>> obj-$(CONFIG_PPC_MEMTRACE) += memtrace.o
>>> -obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o
>>> +obj-$(CONFIG_PPC_VAS) += vas.o vas-window.o vas-debug.o vas-fault.o vas-api.o
>>> obj-$(CONFIG_OCXL_BASE) += ocxl.o
>>> obj-$(CONFIG_SCOM_DEBUGFS) += opal-xscom.o
>>> obj-$(CONFIG_PPC_SECURE_BOOT) += opal-secvar.o
>>> diff --git a/arch/powerpc/platforms/powernv/vas-api.c b/arch/powerpc/platforms/powernv/vas-api.c
>>> new file mode 100644
>>> index 0000000..7d049af
>>> --- /dev/null
>>> +++ b/arch/powerpc/platforms/powernv/vas-api.c
>>> @@ -0,0 +1,257 @@
> ...
>>> +
>>> +static int coproc_mmap(struct file *fp, struct vm_area_struct *vma)
>>> +{
>>> + struct vas_window *txwin = fp->private_data;
>>> + unsigned long pfn;
>>> + u64 paste_addr;
>>> + pgprot_t prot;
>>> + int rc;
>>> +
>>> + if ((vma->vm_end - vma->vm_start) > PAGE_SIZE) {
>>
>> I think you said this should be 4096 rather than 64k, regardless of what
>> PAGE_SIZE you are compiled with?
>
> You can't mmap less than a page, a page is PAGE_SIZE bytes.
>
> So if that checked for 4K explicitly it would prevent mmap on 64K
> kernels always, which seems like not what you want?
Ah. My bad. Carry on then :)
Regards,
Daniel
>
> cheers
^ permalink raw reply
* Re: [PATCH 00/15] powerpc/watchpoint: Preparation for more than one watchpoint
From: Ravi Bangoria @ 2020-03-23 13:37 UTC (permalink / raw)
To: Christophe Leroy
Cc: apopple, mikey, Ravi Bangoria, peterz, oleg, npiggin,
linux-kernel, paulus, jolsa, fweisbec, naveen.n.rao, linuxppc-dev,
mingo
In-Reply-To: <429c04e9-7267-55a9-a6f9-1fe9b21ae033@linux.ibm.com>
On 3/18/20 6:22 PM, Ravi Bangoria wrote:
>
>
> On 3/16/20 8:35 PM, Christophe Leroy wrote:
>>
>>
>> Le 09/03/2020 à 09:57, Ravi Bangoria a écrit :
>>> So far, powerpc Book3S code has been written with an assumption of only
>>> one watchpoint. But future power architecture is introducing second
>>> watchpoint register (DAWR). Even though this patchset does not enable
>>> 2nd DAWR, it make the infrastructure ready so that enabling 2nd DAWR
>>> should just be a matter of changing count.
>>
>> Some book3s (e300 family for instance, I think G2 as well) already have a DABR2 in addition to DABR.
>> Will this series allow to use it as well ?
>
> I wasn't aware of that. I'll take a look at their specs and check if they
> can piggyback on this series for 2nd DABR.
There are some differences between G2/e300 DABRs and Book3S DAWRs. G2/e300
DABRs provides some functionalities like "Match if EA less/greater than DABR",
"combined mode" etc. are not present with DAWRs. DBCR on G2/e300 also provides
which DABR caused the exception. So this series might not directly allow to
use DABR2 but, I guess, it should work as base infrastructure.
Ravi
^ permalink raw reply
* [PATCH v4 00/17] Convert cpu_up/down to device_online/offline
From: Qais Yousef @ 2020-03-23 13:50 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Juergen Gross, Fenghua Yu, Tony Luck, linux-ia64, linux-parisc,
Paul E. McKenney, David S. Miller, Catalin Marinas, Helge Deller,
x86, Russell King, linux-kernel, Lorenzo Pieralisi,
Greg Kroah-Hartman, sparclinux, xen-devel, Mark Rutland,
linuxppc-dev, Qais Yousef, linux-arm-kernel
=============
Changes in v4
=============
* Split arm and arm64 patches so that the change to use reboot_cpu goes
into its own separate patch (Russell)
* Collected new Acked-by
* Rebased on top of v5.6-rc6
* Trimmed the CC list on the cover letter as lists were rejecting it
git clone git://linux-arm.org/linux-qy.git -b cpu-hp-cleanup-v4
Older post can be found here
----------------------------
https://lore.kernel.org/lkml/20200223192942.18420-2-qais.yousef@arm.com/
=============
Test Coverage
=============
All tests ran with LOCKDEP enabled.
Platform: Juno-r2: arm64
------------------------
* Overnight rcutorture
* Overnight locktorture
* kexec -f Image --command="$(cat /proc/cmdline) reboot=s[0-5]"
* Hibernate to disk (using suspend option)
* Userspace hotplug via sysfs
* PSCI firemware checker
Notes:
* Couldn't convince Juno to hibernate using [reboot] or [shutdown]
options.
Platform: qemu (8 vCPUs) and VM (2 vCPUs): x86_64
-------------------------------------------------
* Overnight rcutorture
* Overnight locktorture
* Userspace hotplug via sysfs
* echo mmiotrace > /sys/kernel/debug/tracing/current_tracer &&
echo nop > /sys/kernel/debug/tracing/current_tracer
* Ran with CONFIG_DEBUG_HOTPLUG_CPU0 and CONFIG_BOOTPARAM_HOTPLUG_CPU0
Notes:
* qemu failed to bring cpu0 after offlining. Same behavior observed on
vanilla v5.6-rc6. Worked fine on the VM.
* mmiotrace successfully brought down all cpus when enabled,
then back online again when disabled. Including when cpu0 was
offline.
* My xen shenanigans are too 'humble' too create environment to test
the change in xen yet..
=====================
Original Cover Letter
=====================
Using cpu_up/down directly to bring cpus online/offline loses synchronization
with sysfs and could suffer from a race similar to what is described in
commit a6717c01ddc2 ("powerpc/rtas: use device model APIs and serialization
during LPM").
cpu_up/down seem to be more of a internal implementation detail for the cpu
subsystem to use to boot up cpus, perform suspend/resume and low level hotplug
operations. Users outside of the cpu subsystem would be better using the device
core API to bring a cpu online/offline which is the interface used to hotplug
memory and other system devices.
Several users have already migrated to use the device core API, this series
converts the remaining users and hides cpu_up/down from internal users at the
end.
I noticed this problem while working on a hack to disable offlining
a particular CPU but noticed that setting the offline_disabled attribute in the
device struct isn't enough because users can easily bypass the device core.
While my hack isn't a valid use case but it did highlight the inconsistency in
the way cpus are being onlined/offlined and this attempt hopefully improves on
this.
The first patch introduces new API to {add,remove}_cpu() using device_{online,
offline}() with correct locks held and export it.
The following 10 patches fix arch users.
The remaining 6 patches fix generic code users. Particularly creating a new
special exported API for the device core to use instead of cpu_up/down.
The last patch removes cpu_up/down from cpu.h and unexport the functions.
In some cases where the use of cpu_up/down seemed legitimate, I encapsulated
the logic in a higher level - special purposed function; and converted the code
to use that instead.
CC: Thomas Gleixner <tglx@linutronix.de>
CC: Tony Luck <tony.luck@intel.com>
CC: Fenghua Yu <fenghua.yu@intel.com>
CC: Russell King <linux@armlinux.org.uk>
CC: Catalin Marinas <catalin.marinas@arm.com>
CC: Michael Ellerman <mpe@ellerman.id.au>
CC: "David S. Miller" <davem@davemloft.net>
CC: Helge Deller <deller@gmx.de>
CC: Juergen Gross <jgross@suse.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: "Paul E. McKenney" <paulmck@kernel.org>
CC: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CC: xen-devel@lists.xenproject.org
CC: linux-parisc@vger.kernel.org
CC: sparclinux@vger.kernel.org
CC: linuxppc-dev@lists.ozlabs.org
CC: x86@kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-ia64@vger.kernel.org
CC: linux-kernel@vger.kernel.org
Qais Yousef (17):
cpu: Add new {add,remove}_cpu() functions
smp: Create a new function to shutdown nonboot cpus
ia64: Replace cpu_down with smp_shutdown_nonboot_cpus()
arm: Don't use disable_nonboot_cpus()
arm: Use reboot_cpu instead of hardcoding it to 0
arm64: Don't use disable_nonboot_cpus()
arm64: Use reboot_cpu instead of hardconding it to 0
arm64: hibernate.c: Create a new function to handle cpu_up(sleep_cpu)
x86: Replace cpu_up/down with add/remove_cpu
powerpc: Replace cpu_up/down with add/remove_cpu
sparc: Replace cpu_up/down with add/remove_cpu
parisc: Replace cpu_up/down with add/remove_cpu
driver: xen: Replace cpu_up/down with device_online/offline
firmware: psci: Replace cpu_up/down with add/remove_cpu
torture: Replace cpu_up/down with add/remove_cpu
smp: Create a new function to bringup nonboot cpus online
cpu: Hide cpu_up/down
arch/arm/kernel/reboot.c | 4 +-
arch/arm64/kernel/hibernate.c | 13 +--
arch/arm64/kernel/process.c | 4 +-
arch/ia64/kernel/process.c | 8 +-
arch/parisc/kernel/processor.c | 2 +-
arch/powerpc/kexec/core_64.c | 2 +-
arch/sparc/kernel/ds.c | 4 +-
arch/x86/kernel/topology.c | 22 ++---
arch/x86/mm/mmio-mod.c | 4 +-
arch/x86/xen/smp.c | 2 +-
drivers/base/cpu.c | 4 +-
drivers/firmware/psci/psci_checker.c | 4 +-
drivers/xen/cpu_hotplug.c | 2 +-
include/linux/cpu.h | 10 +-
kernel/cpu.c | 134 ++++++++++++++++++++++++++-
kernel/smp.c | 9 +-
kernel/torture.c | 9 +-
17 files changed, 172 insertions(+), 65 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH v4 01/17] cpu: Add new {add,remove}_cpu() functions
From: Qais Yousef @ 2020-03-23 13:50 UTC (permalink / raw)
To: Thomas Gleixner
Cc: Juergen Gross, Mark Rutland, Lorenzo Pieralisi, linux-parisc,
Paul E. McKenney, Helge Deller, x86, linux-kernel, Qais Yousef,
sparclinux, xen-devel, linuxppc-dev, David S. Miller,
linux-arm-kernel
In-Reply-To: <20200323135110.30522-1-qais.yousef@arm.com>
The new functions use device_{online,offline}() which are userspace
safe.
This is in preparation to move cpu_{up, down} kernel users to use
a safer interface that is not racy with userspace.
Suggested-by: "Paul E. McKenney" <paulmck@kernel.org>
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: "Paul E. McKenney" <paulmck@kernel.org>
CC: Helge Deller <deller@gmx.de>
CC: Michael Ellerman <mpe@ellerman.id.au>
CC: "David S. Miller" <davem@davemloft.net>
CC: Juergen Gross <jgross@suse.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: xen-devel@lists.xenproject.org
CC: linux-parisc@vger.kernel.org
CC: sparclinux@vger.kernel.org
CC: linuxppc-dev@lists.ozlabs.org
CC: linux-arm-kernel@lists.infradead.org
CC: x86@kernel.org
CC: linux-kernel@vger.kernel.org
---
include/linux/cpu.h | 2 ++
kernel/cpu.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 1ca2baf817ed..cf8cf38dca43 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -89,6 +89,7 @@ extern ssize_t arch_cpu_release(const char *, size_t);
#ifdef CONFIG_SMP
extern bool cpuhp_tasks_frozen;
int cpu_up(unsigned int cpu);
+int add_cpu(unsigned int cpu);
void notify_cpu_starting(unsigned int cpu);
extern void cpu_maps_update_begin(void);
extern void cpu_maps_update_done(void);
@@ -118,6 +119,7 @@ extern void cpu_hotplug_disable(void);
extern void cpu_hotplug_enable(void);
void clear_tasks_mm_cpumask(int cpu);
int cpu_down(unsigned int cpu);
+int remove_cpu(unsigned int cpu);
#else /* CONFIG_HOTPLUG_CPU */
diff --git a/kernel/cpu.c b/kernel/cpu.c
index 9c706af713fb..069802f7010f 100644
--- a/kernel/cpu.c
+++ b/kernel/cpu.c
@@ -1057,6 +1057,18 @@ int cpu_down(unsigned int cpu)
}
EXPORT_SYMBOL(cpu_down);
+int remove_cpu(unsigned int cpu)
+{
+ int ret;
+
+ lock_device_hotplug();
+ ret = device_offline(get_cpu_device(cpu));
+ unlock_device_hotplug();
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(remove_cpu);
+
#else
#define takedown_cpu NULL
#endif /*CONFIG_HOTPLUG_CPU*/
@@ -1209,6 +1221,18 @@ int cpu_up(unsigned int cpu)
}
EXPORT_SYMBOL_GPL(cpu_up);
+int add_cpu(unsigned int cpu)
+{
+ int ret;
+
+ lock_device_hotplug();
+ ret = device_online(get_cpu_device(cpu));
+ unlock_device_hotplug();
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(add_cpu);
+
#ifdef CONFIG_PM_SLEEP_SMP
static cpumask_var_t frozen_cpus;
--
2.17.1
^ permalink raw reply related
* [PATCH v4 10/17] powerpc: Replace cpu_up/down with add/remove_cpu
From: Qais Yousef @ 2020-03-23 13:51 UTC (permalink / raw)
To: Thomas Gleixner
Cc: linuxppc-dev, Ram Pai, linux-kernel, Nicholas Piggin,
Paul Mackerras, Enrico Weigelt, Qais Yousef,
Thiago Jung Bauermann
In-Reply-To: <20200323135110.30522-1-qais.yousef@arm.com>
The core device API performs extra housekeeping bits that are missing
from directly calling cpu_up/down.
See commit a6717c01ddc2 ("powerpc/rtas: use device model APIs and
serialization during LPM") for an example description of what might go
wrong.
This also prepares to make cpu_up/down a private interface for anything
but the cpu subsystem.
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Qais Yousef <qais.yousef@arm.com>
CC: Benjamin Herrenschmidt <benh@kernel.crashing.org>
CC: Paul Mackerras <paulus@samba.org>
CC: Michael Ellerman <mpe@ellerman.id.au>
CC: Enrico Weigelt <info@metux.net>
CC: Ram Pai <linuxram@us.ibm.com>
CC: Nicholas Piggin <npiggin@gmail.com>
CC: Thiago Jung Bauermann <bauerman@linux.ibm.com>
CC: Christophe Leroy <christophe.leroy@c-s.fr>
CC: Thomas Gleixner <tglx@linutronix.de>
CC: linuxppc-dev@lists.ozlabs.org
CC: linux-kernel@vger.kernel.org
---
arch/powerpc/kexec/core_64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kexec/core_64.c b/arch/powerpc/kexec/core_64.c
index 04a7cba58eff..b4184092172a 100644
--- a/arch/powerpc/kexec/core_64.c
+++ b/arch/powerpc/kexec/core_64.c
@@ -212,7 +212,7 @@ static void wake_offline_cpus(void)
if (!cpu_online(cpu)) {
printk(KERN_INFO "kexec: Waking offline cpu %d.\n",
cpu);
- WARN_ON(cpu_up(cpu));
+ WARN_ON(add_cpu(cpu));
}
}
}
--
2.17.1
^ permalink raw reply related
* Re: [RFC PATCH 0/3] Use per-CPU temporary mappings for patching
From: Christophe Leroy @ 2020-03-23 14:04 UTC (permalink / raw)
To: Christopher M. Riedl, linuxppc-dev
In-Reply-To: <173d34a7-a178-ed52-df92-eac8e47d347c@c-s.fr>
On 03/23/2020 11:30 AM, Christophe Leroy wrote:
>
>
> On 03/23/2020 04:52 AM, Christopher M. Riedl wrote:
>> When compiled with CONFIG_STRICT_KERNEL_RWX, the kernel must create
>> temporary mappings when patching itself. These mappings temporarily
>> override the strict RWX text protections to permit a write. Currently,
>> powerpc allocates a per-CPU VM area for patching. Patching occurs as
>> follows:
>>
>> 1. Map page of text to be patched to per-CPU VM area w/
>> PAGE_KERNEL protection
>> 2. Patch text
>> 3. Remove the temporary mapping
>>
>> While the VM area is per-CPU, the mapping is actually inserted into the
>> kernel page tables. Presumably, this could allow another CPU to access
>> the normally write-protected text - either malicously or accidentally -
>> via this same mapping if the address of the VM area is known. Ideally,
>> the mapping should be kept local to the CPU doing the patching (or any
>> other sensitive operations requiring temporarily overriding memory
>> protections) [0].
>>
>> x86 introduced "temporary mm" structs which allow the creation of
>> mappings local to a particular CPU [1]. This series intends to bring the
>> notion of a temporary mm to powerpc and harden powerpc by using such a
>> mapping for patching a kernel with strict RWX permissions.
>>
>> The first patch introduces the temporary mm struct and API for powerpc
>> along with a new function to retrieve a current hw breakpoint.
>>
>> The second patch uses the `poking_init` init hook added by the x86
>> patches to initialize a temporary mm and patching address. The patching
>> address is randomized between 0 and DEFAULT_MAP_WINDOW-PAGE_SIZE. The
>> upper limit is necessary due to how the hash MMU operates - by default
>> the space above DEFAULT_MAP_WINDOW is not available. For now, both hash
>> and radix randomize inside this range. The number of possible random
>> addresses is dependent on PAGE_SIZE and limited by DEFAULT_MAP_WINDOW.
>>
>> Bits of entropy with 64K page size on BOOK3S_64:
>>
>> bits-o-entropy = log2(DEFAULT_MAP_WINDOW_USER64 / PAGE_SIZE)
>>
>> PAGE_SIZE=64K, DEFAULT_MAP_WINDOW_USER64=128TB
>> bits-o-entropy = log2(128TB / 64K)
>> bits-o-entropy = 31
>>
>> Currently, randomization occurs only once during initialization at boot.
>>
>> The third patch replaces the VM area with the temporary mm in the
>> patching code. The page for patching has to be mapped PAGE_SHARED with
>> the hash MMU since hash prevents the kernel from accessing userspace
>> pages with PAGE_PRIVILEGED bit set. There is on-going work on my side to
>> explore if this is actually necessary in the hash codepath.
>>
>> Testing so far is limited to booting on QEMU (power8 and power9 targets)
>> and a POWER8 VM along with setting some simple xmon breakpoints (which
>> makes use of code-patching). A POC lkdtm test is in-progress to actually
>> exploit the existing vulnerability (ie. the mapping during patching is
>> exposed in kernel page tables and accessible by other CPUS) - this will
>> accompany a future v1 of this series.
>
> Got following failures on an 8xx. Note that "fault blocked by AP
> register !" means an unauthorised access from Kernel to Userspace.
>
Still a problem even without CONFIG_PPC_KUAP:
[ 5.901899] ------------[ cut here ]------------
[ 5.906329] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 5.915658] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 5.925610] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 5.930614] REGS: c9023db0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 5.940310] MSR: 00021032 <ME,IR,DR,RI> CR: 44000822 XER: 20000000
[ 5.946677]
[ 5.946677] GPR00: 3d6a4000 c9023e68 c60ec000 00000001 c9023ea8
00000004 c0001188 00000004
[ 5.946677] GPR08: 00000000 00000000 00000000 c53720f0 22000222
00000000 c0003964 00000000
[ 5.946677] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 5.946677] GPR24: 00000000 00000000 c0730000 00009032 c0734a88
c0730000 c0001188 00000000
[ 5.981416] NIP [c0012468] patch_instruction+0x20c/0x324
[ 5.986656] LR [c0012460] patch_instruction+0x204/0x324
[ 5.991772] Call Trace:
[ 5.994231] [c9023e68] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 6.001201] [c9023ee8] [c0010470] mmu_mark_initmem_nx+0x44/0x124
[ 6.007132] [c9023f18] [c000e3cc] free_initmem+0x20/0x58
[ 6.012383] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.017630] [c9023f38] [c000d174] ret_from_kernel_thread+0x14/0x1c
[ 6.023698] Instruction dump:
[ 6.026635] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 6.034293] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 6.042128] ---[ end trace c46738768244c84e ]---
[ 6.047021] ------------[ cut here ]------------
[ 6.051422] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 6.060756] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 6.070708] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 6.075712] REGS: c9023db0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.085408] MSR: 00021032 <ME,IR,DR,RI> CR: 44000822 XER: 20000000
[ 6.091775]
[ 6.091775] GPR00: 2b8ac060 c9023e68 c60ec000 00000001 c9023ea8
00000004 c000111c 00000004
[ 6.091775] GPR08: 00000000 00000000 00000000 c53720f0 22000222
00000000 c0003964 00000000
[ 6.091775] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.091775] GPR24: 00000000 00000000 c0730000 00009032 c0734a88
c0730000 c000111c 00000000
[ 6.126510] NIP [c0012468] patch_instruction+0x20c/0x324
[ 6.131754] LR [c0012460] patch_instruction+0x204/0x324
[ 6.136870] Call Trace:
[ 6.139329] [c9023e68] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 6.146299] [c9023ee8] [c00104a8] mmu_mark_initmem_nx+0x7c/0x124
[ 6.152229] [c9023f18] [c000e3cc] free_initmem+0x20/0x58
[ 6.157480] [c9023f28] [c0003980] kernel_init+0x1c/0x130
[ 6.162729] [c9023f38] [c000d174] ret_from_kernel_thread+0x14/0x1c
[ 6.168796] Instruction dump:
[ 6.171733] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 6.179391] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 6.187226] ---[ end trace c46738768244c84f ]---
[ 6.203450] Freeing unused kernel memory: 496K
[ 6.207700] ------------[ cut here ]------------
[ 6.212280] WARNING: CPU: 0 PID: 1 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 6.221605] CPU: 0 PID: 1 Comm: swapper Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 6.231556] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 6.236559] REGS: c9023da0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 6.246256] MSR: 00021032 <ME,IR,DR,RI> CR: 88000222 XER: 20000000
[ 6.252622]
[ 6.252622] GPR00: 3d6aff80 c9023e58 c60ec000 00000001 c9023e98
00000004 c00012b0 00000004
[ 6.252622] GPR08: 00000000 fffffffe 00000000 00000000 28000224
00000000 c0003964 00000000
[ 6.252622] GPR16: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 6.252622] GPR24: 00000000 00000000 c0730000 00009032 c0734a88
c0730000 c00012b0 00000000
[ 6.287362] NIP [c0012468] patch_instruction+0x20c/0x324
[ 6.292602] LR [c0012460] patch_instruction+0x204/0x324
[ 6.297718] Call Trace:
[ 6.300178] [c9023e58] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 6.307148] [c9023ed8] [c0010598] mmu_mark_rodata_ro+0x48/0xf8
[ 6.312907] [c9023f08] [c000edf0] mark_rodata_ro+0xc4/0xd8
[ 6.318327] [c9023f28] [c0003998] kernel_init+0x34/0x130
[ 6.323576] [c9023f38] [c000d174] ret_from_kernel_thread+0x14/0x1c
[ 6.329643] Instruction dump:
[ 6.332580] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 6.340238] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 6.348074] ---[ end trace c46738768244c850 ]---
[ 10.024271] ------------[ cut here ]------------
[ 10.028719] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 10.038218] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 10.047999] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 10.053003] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 10.062699] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 10.069066]
[ 10.069066] GPR00: 48000028 ca473a18 c65f2ae0 00000001 ca473a58
00000004 c045b304 00000004
[ 10.069066] GPR08: 00000000 00000000 00000000 00000004 c6276b2c
10093080 00000000 00000000
[ 10.069066] GPR16: 00000000 c0665cac 00000000 c6619050 c6619070
00000000 c63e5800 ca473bb0
[ 10.069066] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c045b304 00000000
[ 10.103800] NIP [c0012468] patch_instruction+0x20c/0x324
[ 10.109041] LR [c0012460] patch_instruction+0x204/0x324
[ 10.114161] Call Trace:
[ 10.116617] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 10.123592] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 10.129353] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 10.136324] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 10.142512] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 10.148458] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 10.154395] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 10.160415] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 10.165943] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 10.171610] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 10.177281] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 10.182873] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 10.188304] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 10.193638] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 10.199143] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 10.204645] --- interrupt: c01 at 0xfd95304
[ 10.204645] LR = 0xfd952e4
[ 10.211752] Instruction dump:
[ 10.214688] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 10.222346] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 10.230182] ---[ end trace c46738768244c851 ]---
[ 10.235177] ------------[ cut here ]------------
[ 10.239561] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 10.249067] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 10.258848] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 10.263852] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 10.273547] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 10.279915]
[ 10.279915] GPR00: 4800001c ca473a18 c65f2ae0 00000001 ca473a58
00000004 c045f8b8 00000004
[ 10.279915] GPR08: 00000000 00000000 00000000 00000004 c6276b4c
10093080 00000000 00000000
[ 10.279915] GPR16: 00000000 c0665cac 00000000 c661909c c66190bc
00000000 c63e5800 ca473bb0
[ 10.279915] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c045f8b8 00000000
[ 10.314647] NIP [c0012468] patch_instruction+0x20c/0x324
[ 10.319890] LR [c0012460] patch_instruction+0x204/0x324
[ 10.325009] Call Trace:
[ 10.327465] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 10.334439] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 10.340202] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 10.347173] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 10.353361] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 10.359308] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 10.365243] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 10.371263] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 10.376792] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 10.382459] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 10.388130] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 10.393721] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 10.399150] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 10.404486] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 10.409993] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 10.415494] --- interrupt: c01 at 0xfd95304
[ 10.415494] LR = 0xfd952e4
[ 10.422600] Instruction dump:
[ 10.425536] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 10.433195] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 10.441030] ---[ end trace c46738768244c852 ]---
[ 10.445997] ------------[ cut here ]------------
[ 10.450411] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 10.459916] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 10.469696] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 10.474700] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 10.484396] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 10.490763]
[ 10.490763] GPR00: 480000f8 ca473a18 c65f2ae0 00000001 ca473a58
00000004 c048eaf0 00000004
[ 10.490763] GPR08: 00000000 00000000 00000000 00000004 c6276b4c
10093080 00000000 00000000
[ 10.490763] GPR16: 00000000 c0665cac 00000000 c661909c c66190bc
00000000 c63e5800 ca473bb0
[ 10.490763] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c048eaf0 00000000
[ 10.525498] NIP [c0012468] patch_instruction+0x20c/0x324
[ 10.530738] LR [c0012460] patch_instruction+0x204/0x324
[ 10.535858] Call Trace:
[ 10.538313] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 10.545287] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 10.551049] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 10.558022] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 10.564209] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 10.570155] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 10.576092] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 10.582112] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 10.587639] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 10.593307] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 10.598978] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 10.604569] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 10.609999] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 10.615334] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 10.620841] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 10.626342] --- interrupt: c01 at 0xfd95304
[ 10.626342] LR = 0xfd952e4
[ 10.633449] Instruction dump:
[ 10.636385] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 10.644043] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 10.651879] ---[ end trace c46738768244c853 ]---
[ 10.656931] ------------[ cut here ]------------
[ 10.661347] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 10.670850] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 10.680631] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 10.685635] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 10.695330] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 10.701699]
[ 10.701699] GPR00: 4800008c ca473a18 c65f2ae0 00000001 ca473a58
00000004 c045ca54 00000004
[ 10.701699] GPR08: 00000000 00000000 00000000 00000004 c6276b6c
10093080 00000000 00000000
[ 10.701699] GPR16: 00000000 c0665cac 00000000 c66190e8 c6619108
00000000 c63e5800 ca473bb0
[ 10.701699] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c045ca54 00000000
[ 10.736428] NIP [c0012468] patch_instruction+0x20c/0x324
[ 10.741673] LR [c0012460] patch_instruction+0x204/0x324
[ 10.746792] Call Trace:
[ 10.749249] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 10.756222] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 10.761986] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 10.768956] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 10.775144] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 10.781091] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 10.787026] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 10.793046] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 10.798576] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 10.804241] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 10.809913] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 10.815505] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 10.820933] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 10.826268] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 10.831776] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 10.837277] --- interrupt: c01 at 0xfd95304
[ 10.837277] LR = 0xfd952e4
[ 10.844383] Instruction dump:
[ 10.847319] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 10.854978] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 10.862813] ---[ end trace c46738768244c854 ]---
[ 10.867709] ------------[ cut here ]------------
[ 10.872107] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 10.881612] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 10.891393] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 10.896397] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 10.906092] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 10.912460]
[ 10.912460] GPR00: 48000008 ca473a18 c65f2ae0 00000001 ca473a58
00000004 c04bdcf8 00000004
[ 10.912460] GPR08: 00000000 00000000 00000000 00000004 c6276b6c
10093080 00000000 00000000
[ 10.912460] GPR16: 00000000 c0665cac 00000000 c66190e8 c6619108
00000000 c63e5800 ca473bb0
[ 10.912460] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c04bdcf8 00000000
[ 10.947193] NIP [c0012468] patch_instruction+0x20c/0x324
[ 10.952435] LR [c0012460] patch_instruction+0x204/0x324
[ 10.957555] Call Trace:
[ 10.960011] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 10.966984] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 10.972747] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 10.979720] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 10.985907] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 10.991853] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 10.997790] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 11.003808] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 11.009337] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 11.015005] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 11.020675] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 11.026267] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 11.031696] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 11.037031] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 11.042537] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 11.048039] --- interrupt: c01 at 0xfd95304
[ 11.048039] LR = 0xfd952e4
[ 11.055146] Instruction dump:
[ 11.058082] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 11.065741] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 11.073576] ---[ end trace c46738768244c855 ]---
[ 11.078537] ------------[ cut here ]------------
[ 11.082954] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 11.092461] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 11.102242] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 11.107246] REGS: ca473960 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 11.116941] MSR: 00021032 <ME,IR,DR,RI> CR: 48008842 XER: 20000000
[ 11.123309]
[ 11.123309] GPR00: 4bfffdd8 ca473a18 c65f2ae0 00000001 ca473a58
00000004 c04bdf28 00000004
[ 11.123309] GPR08: 00000000 00000000 00000000 00000004 c6276b6c
10093080 00000000 00000000
[ 11.123309] GPR16: 00000000 c0665cac 00000000 c66190e8 c6619108
00000000 c63e5800 ca473bb0
[ 11.123309] GPR24: 00000001 00000001 c0730000 00009032 c0734a88
c0730000 c04bdf28 00000000
[ 11.158041] NIP [c0012468] patch_instruction+0x20c/0x324
[ 11.163283] LR [c0012460] patch_instruction+0x204/0x324
[ 11.168403] Call Trace:
[ 11.170859] [ca473a18] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 11.177834] [ca473a98] [c00bfdd8] jump_label_update+0xe0/0x128
[ 11.183596] [ca473ac8] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 11.190567] [ca473ad8] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 11.196754] [ca473b08] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 11.202701] [ca473b28] [c0440230] nf_tables_newchain+0x894/0xc04
[ 11.208637] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 11.214656] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 11.220185] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 11.225852] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 11.231524] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 11.237115] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 11.242545] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 11.247880] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 11.253386] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 11.258888] --- interrupt: c01 at 0xfd95304
[ 11.258888] LR = 0xfd952e4
[ 11.265994] Instruction dump:
[ 11.268931] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 11.276588] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 11.284424] ---[ end trace c46738768244c856 ]---
[ 11.289492] ------------[ cut here ]------------
[ 11.293889] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 11.303396] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 11.313176] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 11.318180] REGS: ca4738d0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 11.327876] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 11.334243]
[ 11.334243] GPR00: 48000104 ca473988 c65f2ae0 00000001 ca4739c8
00000004 c045a954 00000004
[ 11.334243] GPR08: 00000000 00000000 00000000 00000004 c6276b8c
10093080 00000000 00000000
[ 11.334243] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 11.334243] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c045a954 00000000
[ 11.368977] NIP [c0012468] patch_instruction+0x20c/0x324
[ 11.374218] LR [c0012460] patch_instruction+0x204/0x324
[ 11.379338] Call Trace:
[ 11.381794] [ca473988] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 11.388767] [ca473a08] [c00bfdd8] jump_label_update+0xe0/0x128
[ 11.394530] [ca473a38] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 11.401500] [ca473a48] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 11.407689] [ca473a78] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 11.413628] [ca473a98] [c041c778] nf_register_net_hooks+0x44/0xac
[ 11.419665] [ca473ab8] [c04caaf4] nf_defrag_ipv4_enable+0x80/0x94
[ 11.425704] [ca473ad8] [c0426a00] nf_ct_netns_do_get+0x164/0x1d4
[ 11.431642] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 11.437898] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 11.443234] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 11.449003] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 11.455023] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 11.460548] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 11.466220] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 11.471891] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 11.477482] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 11.482910] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 11.488246] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 11.493753] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 11.499255] --- interrupt: c01 at 0xfd95304
[ 11.499255] LR = 0xfd952e4
[ 11.506361] Instruction dump:
[ 11.509298] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 11.516956] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 11.524792] ---[ end trace c46738768244c857 ]---
[ 11.529687] ------------[ cut here ]------------
[ 11.534086] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 11.543591] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 11.553372] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 11.558377] REGS: ca4738d0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 11.568071] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 11.574438]
[ 11.574438] GPR00: 48000010 ca473988 c65f2ae0 00000001 ca4739c8
00000004 c045b3dc 00000004
[ 11.574438] GPR08: 00000000 00000000 00000000 00000004 c6276b8c
10093080 00000000 00000000
[ 11.574438] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 11.574438] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c045b3dc 00000000
[ 11.609176] NIP [c0012468] patch_instruction+0x20c/0x324
[ 11.614413] LR [c0012460] patch_instruction+0x204/0x324
[ 11.619533] Call Trace:
[ 11.621989] [ca473988] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 11.628963] [ca473a08] [c00bfdd8] jump_label_update+0xe0/0x128
[ 11.634725] [ca473a38] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 11.641697] [ca473a48] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 11.647885] [ca473a78] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 11.653823] [ca473a98] [c041c778] nf_register_net_hooks+0x44/0xac
[ 11.659862] [ca473ab8] [c04caaf4] nf_defrag_ipv4_enable+0x80/0x94
[ 11.665899] [ca473ad8] [c0426a00] nf_ct_netns_do_get+0x164/0x1d4
[ 11.671837] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 11.678092] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 11.683430] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 11.689200] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 11.695219] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 11.700744] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 11.706417] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 11.712087] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 11.717678] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 11.723106] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 11.728442] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 11.733949] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 11.739450] --- interrupt: c01 at 0xfd95304
[ 11.739450] LR = 0xfd952e4
[ 11.746556] Instruction dump:
[ 11.749492] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 11.757151] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 11.764987] ---[ end trace c46738768244c858 ]---
[ 11.769879] ------------[ cut here ]------------
[ 11.774281] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 11.783787] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 11.793567] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 11.798571] REGS: ca4738d0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 11.808266] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 11.814633]
[ 11.814633] GPR00: 48000048 ca473988 c65f2ae0 00000001 ca4739c8
00000004 c04ce9d8 00000004
[ 11.814633] GPR08: 00000000 00000000 00000000 00000004 c6276b8c
10093080 00000000 00000000
[ 11.814633] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 11.814633] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c04ce9d8 00000000
[ 11.849366] NIP [c0012468] patch_instruction+0x20c/0x324
[ 11.854610] LR [c0012460] patch_instruction+0x204/0x324
[ 11.859728] Call Trace:
[ 11.862184] [ca473988] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 11.869161] [ca473a08] [c00bfdd8] jump_label_update+0xe0/0x128
[ 11.874920] [ca473a38] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 11.881891] [ca473a48] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 11.888080] [ca473a78] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 11.894018] [ca473a98] [c041c778] nf_register_net_hooks+0x44/0xac
[ 11.900055] [ca473ab8] [c04caaf4] nf_defrag_ipv4_enable+0x80/0x94
[ 11.906096] [ca473ad8] [c0426a00] nf_ct_netns_do_get+0x164/0x1d4
[ 11.912034] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 11.918287] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 11.923625] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 11.929393] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 11.935414] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 11.940938] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 11.946610] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 11.952282] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 11.957873] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 11.963303] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 11.968637] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 11.974144] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 11.979646] --- interrupt: c01 at 0xfd95304
[ 11.979646] LR = 0xfd952e4
[ 11.986751] Instruction dump:
[ 11.989688] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 11.997346] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 12.005182] ---[ end trace c46738768244c859 ]---
[ 12.010129] ------------[ cut here ]------------
[ 12.014564] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 12.024068] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 12.033847] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 12.038852] REGS: ca4738f0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 12.048547] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 12.054914]
[ 12.054914] GPR00: 48000008 ca4739a8 c65f2ae0 00000001 ca4739e8
00000004 c0460db8 00000004
[ 12.054914] GPR08: 00000000 00000000 00000000 c66a4508 c6276bac
10093080 00000000 00000000
[ 12.054914] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 12.054914] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c0460db8 00000000
[ 12.089649] NIP [c0012468] patch_instruction+0x20c/0x324
[ 12.094891] LR [c0012460] patch_instruction+0x204/0x324
[ 12.100009] Call Trace:
[ 12.102466] [ca4739a8] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 12.109439] [ca473a28] [c00bfdd8] jump_label_update+0xe0/0x128
[ 12.115202] [ca473a58] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 12.122172] [ca473a68] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 12.128361] [ca473a98] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 12.134299] [ca473ab8] [c041c778] nf_register_net_hooks+0x44/0xac
[ 12.140354] [ca473ad8] [c0426a28] nf_ct_netns_do_get+0x18c/0x1d4
[ 12.146290] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 12.152545] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 12.157883] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 12.163650] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 12.169671] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 12.175195] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 12.180868] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 12.186539] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 12.192130] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 12.197558] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 12.202894] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 12.208401] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 12.213903] --- interrupt: c01 at 0xfd95304
[ 12.213903] LR = 0xfd952e4
[ 12.221008] Instruction dump:
[ 12.223945] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 12.231603] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 12.239438] ---[ end trace c46738768244c85a ]---
[ 12.244413] ------------[ cut here ]------------
[ 12.248824] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 12.258325] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 12.268105] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 12.273110] REGS: ca4738f0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 12.282804] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 12.289171]
[ 12.289171] GPR00: 4800009c ca4739a8 c65f2ae0 00000001 ca4739e8
00000004 c0460e6c 00000004
[ 12.289171] GPR08: 00000000 00000000 00000000 c66a4508 c6276bac
10093080 00000000 00000000
[ 12.289171] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 12.289171] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c0460e6c 00000000
[ 12.323909] NIP [c0012468] patch_instruction+0x20c/0x324
[ 12.329146] LR [c0012460] patch_instruction+0x204/0x324
[ 12.334267] Call Trace:
[ 12.336722] [ca4739a8] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 12.343696] [ca473a28] [c00bfdd8] jump_label_update+0xe0/0x128
[ 12.349458] [ca473a58] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 12.356430] [ca473a68] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 12.362618] [ca473a98] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 12.368556] [ca473ab8] [c041c778] nf_register_net_hooks+0x44/0xac
[ 12.374607] [ca473ad8] [c0426a28] nf_ct_netns_do_get+0x18c/0x1d4
[ 12.380551] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 12.386801] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 12.392139] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 12.397909] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 12.403928] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 12.409452] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 12.415125] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 12.420795] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 12.426387] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 12.431814] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 12.437151] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 12.442658] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 12.448160] --- interrupt: c01 at 0xfd95304
[ 12.448160] LR = 0xfd952e4
[ 12.455265] Instruction dump:
[ 12.458202] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 12.465860] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 12.473696] ---[ end trace c46738768244c85b ]---
[ 12.478748] ------------[ cut here ]------------
[ 12.483165] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 12.492667] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 12.502449] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 12.507453] REGS: ca4738f0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 12.517147] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 12.523515]
[ 12.523515] GPR00: 48000008 ca4739a8 c65f2ae0 00000001 ca4739e8
00000004 c0460e84 00000004
[ 12.523515] GPR08: 00000000 00000000 00000000 c66a4508 c6276bac
10093080 00000000 00000000
[ 12.523515] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 12.523515] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c0460e84 00000000
[ 12.558246] NIP [c0012468] patch_instruction+0x20c/0x324
[ 12.563490] LR [c0012460] patch_instruction+0x204/0x324
[ 12.568609] Call Trace:
[ 12.571066] [ca4739a8] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 12.578040] [ca473a28] [c00bfdd8] jump_label_update+0xe0/0x128
[ 12.583802] [ca473a58] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 12.590772] [ca473a68] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 12.596961] [ca473a98] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 12.602899] [ca473ab8] [c041c778] nf_register_net_hooks+0x44/0xac
[ 12.608952] [ca473ad8] [c0426a28] nf_ct_netns_do_get+0x18c/0x1d4
[ 12.614892] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 12.621144] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 12.626482] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 12.632251] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 12.638271] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 12.643795] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 12.649467] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 12.655139] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 12.660730] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 12.666159] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 12.671495] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 12.677000] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 12.682503] --- interrupt: c01 at 0xfd95304
[ 12.682503] LR = 0xfd952e4
[ 12.689609] Instruction dump:
[ 12.692545] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 12.700203] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 12.708039] ---[ end trace c46738768244c85c ]---
[ 12.713016] ------------[ cut here ]------------
[ 12.717423] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 12.726924] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 12.736705] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 12.741710] REGS: ca4738f0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 12.751404] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 12.757772]
[ 12.757772] GPR00: 48000028 ca4739a8 c65f2ae0 00000001 ca4739e8
00000004 c046102c 00000004
[ 12.757772] GPR08: 00000000 00000000 00000000 c66a4508 c6276bac
10093080 00000000 00000000
[ 12.757772] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 12.757772] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c046102c 00000000
[ 12.792504] NIP [c0012468] patch_instruction+0x20c/0x324
[ 12.797747] LR [c0012460] patch_instruction+0x204/0x324
[ 12.802867] Call Trace:
[ 12.805323] [ca4739a8] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 12.812295] [ca473a28] [c00bfdd8] jump_label_update+0xe0/0x128
[ 12.818059] [ca473a58] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 12.825030] [ca473a68] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 12.831217] [ca473a98] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 12.837156] [ca473ab8] [c041c778] nf_register_net_hooks+0x44/0xac
[ 12.843211] [ca473ad8] [c0426a28] nf_ct_netns_do_get+0x18c/0x1d4
[ 12.849148] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 12.855401] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 12.860740] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 12.866507] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 12.872528] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 12.878053] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 12.883725] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 12.889395] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 12.894987] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 12.900414] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 12.905751] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 12.911258] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 12.916760] --- interrupt: c01 at 0xfd95304
[ 12.916760] LR = 0xfd952e4
[ 12.923865] Instruction dump:
[ 12.926802] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 12.934460] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 12.942296] ---[ end trace c46738768244c85d ]---
[ 12.947193] ------------[ cut here ]------------
[ 12.951591] WARNING: CPU: 0 PID: 153 at
arch/powerpc/lib/code-patching.c:182 patch_instruction+0x20c/0x324
[ 12.961095] CPU: 0 PID: 153 Comm: nft Tainted: G W
5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5 #3526
[ 12.970876] NIP: c0012468 LR: c0012460 CTR: 00000000
[ 12.975881] REGS: ca4738f0 TRAP: 0700 Tainted: G W
(5.6.0-rc6-s3k-dev-00903-g70f8a9483ed5)
[ 12.985575] MSR: 00021032 <ME,IR,DR,RI> CR: 44008442 XER: 20000000
[ 12.991942]
[ 12.991942] GPR00: 48000028 ca4739a8 c65f2ae0 00000001 ca4739e8
00000004 c04cf028 00000004
[ 12.991942] GPR08: 00000000 00000000 00000000 c66a4508 c6276bac
10093080 00000000 00000000
[ 12.991942] GPR16: 00000000 c0665dd8 00000000 c6619134 c08e7340
c63e5800 ca473c34 c625d6b0
[ 12.991942] GPR24: 00000002 00000001 c0730000 00009032 c0734a88
c0730000 c04cf028 00000000
[ 13.026676] NIP [c0012468] patch_instruction+0x20c/0x324
[ 13.031919] LR [c0012460] patch_instruction+0x204/0x324
[ 13.037037] Call Trace:
[ 13.039493] [ca4739a8] [c001242c] patch_instruction+0x1d0/0x324
(unreliable)
[ 13.046468] [ca473a28] [c00bfdd8] jump_label_update+0xe0/0x128
[ 13.052229] [ca473a58] [c00bfff0]
static_key_slow_inc_cpuslocked+0x108/0x114
[ 13.059197] [ca473a68] [c041c3e8] __nf_register_net_hook+0xb0/0x1a4
[ 13.065389] [ca473a98] [c041c6c8] nf_register_net_hook+0x28/0x94
[ 13.071328] [ca473ab8] [c041c778] nf_register_net_hooks+0x44/0xac
[ 13.077378] [ca473ad8] [c0426a28] nf_ct_netns_do_get+0x18c/0x1d4
[ 13.083323] [ca473af8] [c044e894] nft_ct_helper_obj_init+0x154/0x1d0
[ 13.089572] [ca473b28] [c043f450] nft_obj_init+0xd4/0x178
[ 13.094910] [ca473b48] [c0442b80] nf_tables_newobj+0x2e8/0x444
[ 13.100680] [ca473ba8] [c041ede0] nfnetlink_rcv_batch+0x438/0x4c0
[ 13.106699] [ca473ca8] [c041ef80] nfnetlink_rcv+0x118/0x138
[ 13.112223] [ca473cd8] [c040f138] netlink_unicast+0x18c/0x240
[ 13.117895] [ca473d08] [c040fa14] netlink_sendmsg+0x278/0x398
[ 13.123566] [ca473d58] [c03ace48] ____sys_sendmsg+0xac/0x1e4
[ 13.129158] [ca473db8] [c03ad174] ___sys_sendmsg+0x64/0x88
[ 13.134585] [ca473ea8] [c03aeea0] __sys_sendmsg+0x44/0x88
[ 13.139922] [ca473f08] [c03af3d8] sys_socketcall+0xf4/0x1fc
[ 13.145429] [ca473f38] [c000d0c0] ret_from_syscall+0x0/0x34
[ 13.150931] --- interrupt: c01 at 0xfd95304
[ 13.150931] LR = 0xfd952e4
[ 13.158036] Instruction dump:
[ 13.160973] 2f890000 91220000 409e0010 81220070 712a0004 40820120
38a00004 38810040
[ 13.168631] 7fc3f378 48000855 3123ffff 7c691910 <0f030000> 7f600124
7fe9fb78 80010084
[ 13.176467] ---[ end trace c46738768244c85e ]---
Christophe
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