* [PATCH v2 6/7] powerpc/dt_cpu_ftrs: Add MMA feature
From: Alistair Popple @ 2020-05-19 0:31 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mikey, npiggin, aneesh.kumar, Alistair Popple
In-Reply-To: <20200519003157.31946-1-alistair@popple.id.au>
Matrix multiple accumulate (MMA) is a new feature added to ISAv3.1 and
POWER10. Support on powernv can be selected via a firmware CPU device
tree feature which enables it via a PCR bit.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
---
arch/powerpc/include/asm/reg.h | 3 ++-
arch/powerpc/kernel/dt_cpu_ftrs.c | 17 ++++++++++++++++-
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1931b1142599..c446863a40cf 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -479,7 +479,8 @@
#define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
#define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
#define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
-#define PCR_HIGH_BITS (PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
+#define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
+#define PCR_HIGH_BITS (PCR_MMA_DIS | PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
/*
* These bits are used in the function kvmppc_set_arch_compat() to specify and
* determine both the compatibility level which we want to emulate and the
diff --git a/arch/powerpc/kernel/dt_cpu_ftrs.c b/arch/powerpc/kernel/dt_cpu_ftrs.c
index 93c340906aad..e7540ee5cad8 100644
--- a/arch/powerpc/kernel/dt_cpu_ftrs.c
+++ b/arch/powerpc/kernel/dt_cpu_ftrs.c
@@ -75,6 +75,7 @@ static struct {
u64 lpcr_clear;
u64 hfscr;
u64 fscr;
+ u64 pcr;
} system_registers;
static void (*init_pmu_registers)(void);
@@ -102,7 +103,7 @@ static void __restore_cpu_cpufeatures(void)
if (hv_mode) {
mtspr(SPRN_LPID, 0);
mtspr(SPRN_HFSCR, system_registers.hfscr);
- mtspr(SPRN_PCR, PCR_MASK);
+ mtspr(SPRN_PCR, system_registers.pcr);
}
mtspr(SPRN_FSCR, system_registers.fscr);
@@ -555,6 +556,18 @@ static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
return 1;
}
+static int __init feat_enable_mma(struct dt_cpu_feature *f)
+{
+ u64 pcr;
+
+ feat_enable(f);
+ pcr = mfspr(SPRN_PCR);
+ pcr &= ~PCR_MMA_DIS;
+ mtspr(SPRN_PCR, pcr);
+
+ return 1;
+}
+
struct dt_cpu_feature_match {
const char *name;
int (*enable)(struct dt_cpu_feature *f);
@@ -629,6 +642,7 @@ static struct dt_cpu_feature_match __initdata
{"vector-binary16", feat_enable, 0},
{"wait-v3", feat_enable, 0},
{"prefix-instructions", feat_enable, 0},
+ {"matrix-multiply-accumulate", feat_enable_mma, 0},
};
static bool __initdata using_dt_cpu_ftrs;
@@ -779,6 +793,7 @@ static void __init cpufeatures_setup_finished(void)
system_registers.lpcr = mfspr(SPRN_LPCR);
system_registers.hfscr = mfspr(SPRN_HFSCR);
system_registers.fscr = mfspr(SPRN_FSCR);
+ system_registers.pcr = mfspr(SPRN_PCR);
pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
--
2.20.1
^ permalink raw reply related
* [PATCH v2 7/7] powerpc: Add POWER10 architected mode
From: Alistair Popple @ 2020-05-19 0:31 UTC (permalink / raw)
To: linuxppc-dev
Cc: mikey, npiggin, aneesh.kumar, Alistair Popple,
Cédric Le Goater
In-Reply-To: <20200519003157.31946-1-alistair@popple.id.au>
PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10).
This is used by phyp and kvm when booting as a pseries guest to detect
the presence of new P10 features and to enable the appropriate hwcap and
facility bits.
Signed-off-by: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/cputable.h | 15 ++++++++++++--
arch/powerpc/include/asm/mmu.h | 1 +
arch/powerpc/include/asm/prom.h | 1 +
arch/powerpc/kernel/cpu_setup_power.S | 20 ++++++++++++++++--
arch/powerpc/kernel/cputable.c | 30 +++++++++++++++++++++++++++
arch/powerpc/kernel/prom_init.c | 12 +++++++++--
6 files changed, 73 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 36f894dea9e7..10b6d93c9d0b 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
CPU_FTR_P9_TM_HV_ASSIST | \
CPU_FTR_P9_TM_XER_SO_BUG)
+#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
+ CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
+ CPU_FTR_MMCRA | CPU_FTR_SMT | \
+ CPU_FTR_COHERENT_ICACHE | \
+ CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
+ CPU_FTR_DSCR | CPU_FTR_SAO | \
+ CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
+ CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
+ CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
+ CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
+ CPU_FTR_ARCH_31)
#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
- CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+ CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
#else
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
- CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
+ CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
#endif /* CONFIG_CPU_LITTLE_ENDIAN */
#endif
#else
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index 0699cfeeb8c9..17b19510f204 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -122,6 +122,7 @@
#define MMU_FTRS_POWER7 MMU_FTRS_POWER6
#define MMU_FTRS_POWER8 MMU_FTRS_POWER6
#define MMU_FTRS_POWER9 MMU_FTRS_POWER6
+#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 94e3fd54f2c8..324a13351749 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
#define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */
#define OV1_PPC_3_00 0x80 /* set if we support PowerPC 3.00 */
+#define OV1_PPC_3_1 0x40 /* set if we support PowerPC 3.1 */
/* Option vector 2: Open Firmware options supported */
#define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..f3730cf904fa 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
mtlr r11
blr
+_GLOBAL(__setup_cpu_power10)
+ mflr r11
+ bl __init_FSCR_P10
+ b 1f
+
_GLOBAL(__setup_cpu_power9)
mflr r11
bl __init_FSCR
- bl __init_PMU
+1: bl __init_PMU
bl __init_hvmode_206
mtlr r11
beqlr
@@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
mtlr r11
blr
+_GLOBAL(__restore_cpu_power10)
+ mflr r11
+ bl __init_FSCR_P10
+ b 1f
+
_GLOBAL(__restore_cpu_power9)
mflr r11
bl __init_FSCR
- bl __init_PMU
+1: bl __init_PMU
mfmsr r3
rldicl. r0,r3,4,63
mtlr r11
@@ -182,6 +192,12 @@ __init_LPCR_ISA300:
isync
blr
+__init_FSCR_P10:
+ mfspr r3,SPRN_FSCR
+ ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB|FSCR_PREFIX
+ mtspr SPRN_FSCR,r3
+ blr
+
__init_FSCR:
mfspr r3,SPRN_FSCR
ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 13eba2eb46fe..a17eeb311cdb 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -70,6 +70,8 @@ extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power8(void);
extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_power9(void);
+extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
+extern void __restore_cpu_power10(void);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
@@ -119,6 +121,10 @@ extern void __restore_cpu_e6500(void);
PPC_FEATURE2_ARCH_3_00 | \
PPC_FEATURE2_HAS_IEEE128 | \
PPC_FEATURE2_DARN )
+#define COMMON_USER_POWER10 COMMON_USER_POWER9
+#define COMMON_USER2_POWER10 (COMMON_USER2_POWER9 | \
+ PPC_FEATURE2_ARCH_3_1 | \
+ PPC_FEATURE2_MMA)
#ifdef CONFIG_PPC_BOOK3E_64
#define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
@@ -127,6 +133,14 @@ extern void __restore_cpu_e6500(void);
PPC_FEATURE_BOOKE)
#endif
+#ifdef CONFIG_PPC64
+static void setup_cpu_power10(unsigned long offset, struct cpu_spec* spec)
+{
+ __setup_cpu_power10(offset, spec);
+ current->thread.fscr |= FSCR_PREFIX;
+}
+#endif
+
static struct cpu_spec __initdata cpu_specs[] = {
#ifdef CONFIG_PPC_BOOK3S_64
{ /* PPC970 */
@@ -367,6 +381,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
.cpu_restore = __restore_cpu_power9,
.platform = "power9",
},
+ { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
+ .pvr_mask = 0xffffffff,
+ .pvr_value = 0x0f000006,
+ .cpu_name = "POWER10 (architected)",
+ .cpu_features = CPU_FTRS_POWER10,
+ .cpu_user_features = COMMON_USER_POWER10,
+ .cpu_user_features2 = COMMON_USER2_POWER10,
+ .mmu_features = MMU_FTRS_POWER10,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .oprofile_type = PPC_OPROFILE_INVALID,
+ .oprofile_cpu_type = "ppc64/ibm-compat-v1",
+ .cpu_setup = setup_cpu_power10,
+ .cpu_restore = __restore_cpu_power10,
+ .platform = "power10",
+ },
{ /* Power7 */
.pvr_mask = 0xffff0000,
.pvr_value = 0x003f0000,
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 806be751c336..1ecadbd7e8b2 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -920,7 +920,7 @@ struct option_vector6 {
} __packed;
struct ibm_arch_vec {
- struct { u32 mask, val; } pvrs[12];
+ struct { u32 mask, val; } pvrs[14];
u8 num_vectors;
@@ -973,6 +973,14 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
.mask = cpu_to_be32(0xffff0000), /* POWER9 */
.val = cpu_to_be32(0x004e0000),
},
+ {
+ .mask = cpu_to_be32(0xffff0000), /* POWER10 */
+ .val = cpu_to_be32(0x00800000),
+ },
+ {
+ .mask = cpu_to_be32(0xffffffff), /* all 3.1-compliant */
+ .val = cpu_to_be32(0x0f000006),
+ },
{
.mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */
.val = cpu_to_be32(0x0f000005),
@@ -1002,7 +1010,7 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
.byte1 = 0,
.arch_versions = OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
- .arch_versions3 = OV1_PPC_3_00,
+ .arch_versions3 = OV1_PPC_3_00 | OV1_PPC_3_1,
},
.vec2_len = VECTOR_LENGTH(sizeof(struct option_vector2)),
--
2.20.1
^ permalink raw reply related
* Re: [PATCH V3 07/15] arch/kunmap_atomic: Consolidate duplicate code
From: Guenter Roeck @ 2020-05-19 2:50 UTC (permalink / raw)
To: Ira Weiny
Cc: Peter Zijlstra, Dave Hansen, dri-devel, linux-mips,
James E.J. Bottomley, Max Filippov, Paul Mackerras,
H. Peter Anvin, sparclinux, Dan Williams, Helge Deller, x86,
linux-csky, Christoph Hellwig, Ingo Molnar, linux-snps-arc,
linux-xtensa, Borislav Petkov, Al Viro, Andy Lutomirski,
Thomas Gleixner, linux-arm-kernel, Chris Zankel,
Thomas Bogendoerfer, linux-parisc, linux-kernel, Christian Koenig,
Andrew Morton, linuxppc-dev, David S. Miller
In-Reply-To: <20200519000352.GF3025231@iweiny-DESK2.sc.intel.com>
Hi Ira,
On 5/18/20 5:03 PM, Ira Weiny wrote:
> On Sun, May 17, 2020 at 09:29:32PM -0700, Guenter Roeck wrote:
>> On Sun, May 17, 2020 at 08:49:39PM -0700, Ira Weiny wrote:
>>> On Sat, May 16, 2020 at 03:33:06PM -0700, Guenter Roeck wrote:
>>>> On Thu, May 07, 2020 at 07:59:55AM -0700, ira.weiny@intel.com wrote:
>>>>> From: Ira Weiny <ira.weiny@intel.com>
>>>>>
>>>>> Every single architecture (including !CONFIG_HIGHMEM) calls...
>>>>>
>>>>> pagefault_enable();
>>>>> preempt_enable();
>>>>>
>>>>> ... before returning from __kunmap_atomic(). Lift this code into the
>>>>> kunmap_atomic() macro.
>>>>>
>>>>> While we are at it rename __kunmap_atomic() to kunmap_atomic_high() to
>>>>> be consistent.
>>>>>
>>>>> Reviewed-by: Christoph Hellwig <hch@lst.de>
>>>>> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
>>>>
>>>> This patch results in:
>>>>
>>>> Starting init: /bin/sh exists but couldn't execute it (error -14)
>>>>
>>>> when trying to boot microblazeel:petalogix-ml605 in qemu.
>>>
>>> Thanks for the report. I'm not readily seeing the issue.
>>>
>>> Do you have a kernel config? Specifically is CONFIG_HIGHMEM set?
>>>
>> See below. Yes, CONFIG_HIGHMEM is set.
>>
>> The scripts used to build and boot the image are at:
>>
>> https://github.com/groeck/linux-build-test/tree/master/rootfs/microblazeel
>
> Despite finding the obvious error earlier today I've still been trying to get
> this to work.
>
> I had to make some slight modifications to use the 0-day cross compile build
> and my local qemu build. But those were pretty minor modifications. I'm
> running on x86_64 host.
>
> With those slight mods to the scripts I get the following error even without my
> patch set on 5.7-rc4. I have 1 cpu pegged at 100% while it is running... Is
> there anything I can do to get more debug output? Perhaps I just need to let
> it run longer?
>
I don't think so. Try running it with "-d" parameter (run-qemu-microblazeel.sh
-d petalogix-s3adsp1800); that gives you the qemu command line. Once it says
"running", abort the script and execute qemu directly. Oh, and please update
the repository; turns out I didn't push for a while and made a number of
changes.
My compiler was compiled with buildroot (a long time ago). I don't recall if
it needed something special in the configuration, unfortunately.
Guenter
> Thanks,
> Ira
>
> 16:46:54 > ../linux-build-test/rootfs/microblazeel/run-qemu-microblazeel.sh
> Build reference: v5.7-rc4-2-g7c2411d7fb6a
>
> Building microblaze:petalogix-s3adsp1800:qemu_microblazeel_defconfig ...
> running ................ failed (silent)
> ------------
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
> ------------
> Building microblaze:petalogix-ml605:qemu_microblazeel_ml605_defconfig ...
> running ................ failed (silent)
> ------------
> qemu log:
> qemu-system-microblazeel: terminating on signal 15 from pid 3277686 (/bin/bash)
> ------------
>
> <env changes>
> 16:47:23 > git di
> diff --git a/rootfs/microblazeel/run-qemu-microblazeel.sh b/rootfs/microblazeel/run-qemu-microblazeel.sh
> index 68d4de39ab50..0d6a4f85308f 100755
> --- a/rootfs/microblazeel/run-qemu-microblazeel.sh
> +++ b/rootfs/microblazeel/run-qemu-microblazeel.sh
> @@ -3,7 +3,8 @@
> dir=$(cd $(dirname $0); pwd)
> . ${dir}/../scripts/common.sh
>
> -QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +#QEMU=${QEMU:-${QEMU_BIN}/qemu-system-microblazeel}
> +QEMU=/home/iweiny/dev/qemu/microblazeel-softmmu/qemu-system-microblazeel
> PREFIX=microblazeel-linux-
> ARCH=microblaze
> PATH_MICROBLAZE=/opt/kernel/microblazeel/gcc-4.9.1/usr/bin
> diff --git a/rootfs/scripts/common.sh b/rootfs/scripts/common.sh
> index 8fa6a9be2b2f..c4550a27beaa 100644
> --- a/rootfs/scripts/common.sh
> +++ b/rootfs/scripts/common.sh
> @@ -1,5 +1,9 @@
> #!/bin/bash
>
> +# Set up make.cross
> +export COMPILER_INSTALL_PATH=$HOME/0day
> +export GCC_VERSION=6.5.0
> +
> # Set the following variable to true to skip DC395/AM53C97 build tests
> __skip_dc395=0
>
> @@ -569,7 +573,7 @@ doclean()
> then
> git clean -x -d -f -q
> else
> - make ARCH=${ARCH} mrproper >/dev/null 2>&1
> + make.cross ARCH=${ARCH} mrproper >/dev/null 2>&1
> fi
> }
>
> @@ -669,7 +673,7 @@ __setup_config()
> cp ${__progdir}/${defconfig} arch/${arch}/configs
> fi
>
> - if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${defconfig} >/dev/null 2>&1 </dev/null; then
> + if ! make.cross ARCH=${ARCH} ${defconfig} >/dev/null 2>&1 </dev/null; then
> return 2
> fi
>
> @@ -687,7 +691,7 @@ __setup_config()
> if [[ "${rel}" = "v3.16" ]]; then
> target="oldconfig"
> fi
> - if ! make ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${target} >/dev/null 2>&1 </dev/null; then
> + if ! make.cross ARCH=${ARCH} ${target} >/dev/null 2>&1 </dev/null; then
> return 1
> fi
> fi
> @@ -1038,7 +1042,7 @@ dosetup()
> rootfs="$(setup_rootfs ${dynamic} ${rootfs})"
> __common_fixups "${fixups}" "${rootfs}"
>
> - make -j${maxload} ARCH=${ARCH} CROSS_COMPILE=${PREFIX} ${EXTRAS} </dev/null >/dev/null 2>${logfile}
> + make.cross -j${maxload} ARCH=${ARCH} ${EXTRAS} </dev/null >/dev/null 2>${logfile}
> rv=$?
> if [ ${rv} -ne 0 ]
> then
>
> </env changes>
>
^ permalink raw reply
* Re: [PATCH v2 1/7] powerpc: Add new HWCAP bits
From: Michael Neuling @ 2020-05-19 3:20 UTC (permalink / raw)
To: Alistair Popple, linuxppc-dev; +Cc: npiggin, aneesh.kumar
In-Reply-To: <20200519003157.31946-2-alistair@popple.id.au>
On Tue, 2020-05-19 at 10:31 +1000, Alistair Popple wrote:
> POWER10 introduces two new architectural features - ISAv3.1 and matrix
> multiply accumulate (MMA) instructions. Userspace detects the presence
> of these features via two HWCAP bits introduced in this patch. These
> bits have been agreed to by the compiler and binutils team.
>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
I've test booted this series + powerpc/next (30df74d67d) on top of powervm and
OPAL on a P10 simulator.
In both cases, it enables MMA and prefix instructions and advertises them via
HWCAP2 MMA + ISA 3.1. Hence:
Tested-by: Michael Neuling <mikey@neuling.org>
> ---
> arch/powerpc/include/uapi/asm/cputable.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/powerpc/include/uapi/asm/cputable.h
> b/arch/powerpc/include/uapi/asm/cputable.h
> index 540592034740..2692a56bf20b 100644
> --- a/arch/powerpc/include/uapi/asm/cputable.h
> +++ b/arch/powerpc/include/uapi/asm/cputable.h
> @@ -50,6 +50,8 @@
> #define PPC_FEATURE2_DARN 0x00200000 /* darn random number insn */
> #define PPC_FEATURE2_SCV 0x00100000 /* scv syscall */
> #define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 /* TM w/out suspended state
> */
> +#define PPC_FEATURE2_ARCH_3_1 0x00040000 /* ISA 3.1 */
> +#define PPC_FEATURE2_MMA 0x00020000 /* Matrix Multiply Accumulate
> */
>
> /*
> * IMPORTANT!
^ permalink raw reply
* RE: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size() helper
From: Qiang Zhao @ 2020-05-19 3:37 UTC (permalink / raw)
To: Gustavo A. R. Silva, Leo Li
Cc: Kees Cook, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Gustavo A. R. Silva
In-Reply-To: <20200518221904.GA22274@embeddedor>
On 2020/5/19 6:19, Gustavo A. R. Silva <gustavoars@kernel.org> wrote:
> -----Original Message-----
> From: Gustavo A. R. Silva <gustavoars@kernel.org>
> Sent: 2020年5月19日 6:19
> To: Qiang Zhao <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Gustavo A. R. Silva <gustavo@embeddedor.com>;
> Kees Cook <keescook@chromium.org>
> Subject: [PATCH] soc: fsl: qe: Replace one-element array and use struct_size()
> helper
>
> The current codebase makes use of one-element arrays in the following
> form:
>
> struct something {
> int length;
> u8 data[1];
> };
>
> struct something *instance;
>
> instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
> instance->length = size;
> memcpy(instance->data, source, size);
>
> but the preferred mechanism to declare variable-length types such as these
> ones is a flexible array member[1][2], introduced in C99:
>
> struct foo {
> int stuff;
> struct boo array[];
> };
>
> By making use of the mechanism above, we will get a compiler warning in case
> the flexible array does not occur last in the structure, which will help us prevent
> some kind of undefined behavior bugs from being inadvertently introduced[3]
> to the codebase from now on. So, replace the one-element array with a
> flexible-array member.
>
> Also, make use of the new struct_size() helper to properly calculate the size of
> struct qe_firmware.
>
> This issue was found with the help of Coccinelle and, audited and fixed
> _manually_.
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgcc.gnu.
> org%2Fonlinedocs%2Fgcc%2FZero-Length.html&data=02%7C01%7Cqiang.
> zhao%40nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C637254368610203908&sdata=70
> a6VBg3oWQf9a5KICuCEuIj6gw57NKYhNv2JL8JdDY%3D&reserved=0
> [2]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.c
> om%2FKSPP%2Flinux%2Fissues%2F21&data=02%7C01%7Cqiang.zhao%40
> nxp.com%7Cb058bcb9af134df8446808d7fb78cfa9%7C686ea1d3bc2b4c6fa92c
> d99c5c301635%7C0%7C0%7C637254368610213901&sdata=kVyNBYHbm
> a5jCO9pbkoHMetHEYGvWDq6Xw%2BBeC7uHII%3D&reserved=0
> [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour")
>
> Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
> ---
> drivers/soc/fsl/qe/qe.c | 4 ++--
> include/soc/fsl/qe/qe.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index
> 447146861c2c1..2df20d6f85fa4 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -448,7 +448,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> unsigned int i;
> unsigned int j;
> u32 crc;
> - size_t calc_size = sizeof(struct qe_firmware);
> + size_t calc_size;
> size_t length;
> const struct qe_header *hdr;
>
> @@ -480,7 +480,7 @@ int qe_upload_firmware(const struct qe_firmware
> *firmware)
> }
>
> /* Validate the length and check if there's a CRC */
> - calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
> + calc_size = struct_size(firmware, microcode, firmware->count);
>
> for (i = 0; i < firmware->count; i++)
> /*
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h index
> e282ac01ec081..3feddfec9f87d 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -307,7 +307,7 @@ struct qe_firmware {
> u8 revision; /* The microcode version revision */
> u8 padding; /* Reserved, for alignment */
> u8 reserved[4]; /* Reserved, for future expansion */
> - } __attribute__ ((packed)) microcode[1];
> + } __packed microcode[];
> /* All microcode binaries should be located here */
> /* CRC32 should be located here, after the microcode binaries */ }
> __attribute__ ((packed));
> --
> 2.26.2
[>]
Reviewed-by: Qiang Zhao <qiang.zhao@nxp.com>
Best Regards
Qiang Zhao
^ permalink raw reply
* Re: [PATCH v2 7/7] powerpc: Add POWER10 architected mode
From: Jordan Niethe @ 2020-05-19 3:58 UTC (permalink / raw)
To: Alistair Popple
Cc: aneesh.kumar, mikey, linuxppc-dev, Cédric Le Goater,
Nicholas Piggin
In-Reply-To: <20200519003157.31946-8-alistair@popple.id.au>
On Tue, May 19, 2020 at 10:48 AM Alistair Popple <alistair@popple.id.au> wrote:
>
> PVR value of 0x0F000006 means we are arch v3.1 compliant (i.e. POWER10).
> This is used by phyp and kvm when booting as a pseries guest to detect
> the presence of new P10 features and to enable the appropriate hwcap and
> facility bits.
>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/powerpc/include/asm/cputable.h | 15 ++++++++++++--
> arch/powerpc/include/asm/mmu.h | 1 +
> arch/powerpc/include/asm/prom.h | 1 +
> arch/powerpc/kernel/cpu_setup_power.S | 20 ++++++++++++++++--
> arch/powerpc/kernel/cputable.c | 30 +++++++++++++++++++++++++++
> arch/powerpc/kernel/prom_init.c | 12 +++++++++--
> 6 files changed, 73 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
> index 36f894dea9e7..10b6d93c9d0b 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -468,6 +468,17 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
> CPU_FTR_P9_TM_HV_ASSIST | \
> CPU_FTR_P9_TM_XER_SO_BUG)
> +#define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
> + CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
> + CPU_FTR_MMCRA | CPU_FTR_SMT | \
> + CPU_FTR_COHERENT_ICACHE | \
> + CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
> + CPU_FTR_DSCR | CPU_FTR_SAO | \
> + CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
> + CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
> + CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
> + CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
> + CPU_FTR_ARCH_31)
> #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
> CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
> @@ -486,14 +497,14 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTRS_POSSIBLE \
> (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
> CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
> - CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> + CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
> #else
> #define CPU_FTRS_POSSIBLE \
> (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
> CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
> CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
> CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
> - CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
> + CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
> #endif /* CONFIG_CPU_LITTLE_ENDIAN */
> #endif
> #else
> diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
> index 0699cfeeb8c9..17b19510f204 100644
> --- a/arch/powerpc/include/asm/mmu.h
> +++ b/arch/powerpc/include/asm/mmu.h
> @@ -122,6 +122,7 @@
> #define MMU_FTRS_POWER7 MMU_FTRS_POWER6
> #define MMU_FTRS_POWER8 MMU_FTRS_POWER6
> #define MMU_FTRS_POWER9 MMU_FTRS_POWER6
> +#define MMU_FTRS_POWER10 MMU_FTRS_POWER6
> #define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
> MMU_FTR_CI_LARGE_PAGE
> #define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
> diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
> index 94e3fd54f2c8..324a13351749 100644
> --- a/arch/powerpc/include/asm/prom.h
> +++ b/arch/powerpc/include/asm/prom.h
> @@ -117,6 +117,7 @@ extern int of_read_drc_info_cell(struct property **prop,
> #define OV1_PPC_2_07 0x01 /* set if we support PowerPC 2.07 */
>
> #define OV1_PPC_3_00 0x80 /* set if we support PowerPC 3.00 */
> +#define OV1_PPC_3_1 0x40 /* set if we support PowerPC 3.1 */
>
> /* Option vector 2: Open Firmware options supported */
> #define OV2_REAL_MODE 0x20 /* set if we want OF in real mode */
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index a460298c7ddb..f3730cf904fa 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -91,10 +91,15 @@ _GLOBAL(__restore_cpu_power8)
> mtlr r11
> blr
>
> +_GLOBAL(__setup_cpu_power10)
> + mflr r11
> + bl __init_FSCR_P10
> + b 1f
> +
> _GLOBAL(__setup_cpu_power9)
> mflr r11
> bl __init_FSCR
> - bl __init_PMU
> +1: bl __init_PMU
> bl __init_hvmode_206
> mtlr r11
> beqlr
> @@ -116,10 +121,15 @@ _GLOBAL(__setup_cpu_power9)
> mtlr r11
> blr
>
> +_GLOBAL(__restore_cpu_power10)
> + mflr r11
> + bl __init_FSCR_P10
> + b 1f
> +
> _GLOBAL(__restore_cpu_power9)
> mflr r11
> bl __init_FSCR
> - bl __init_PMU
> +1: bl __init_PMU
> mfmsr r3
> rldicl. r0,r3,4,63
> mtlr r11
> @@ -182,6 +192,12 @@ __init_LPCR_ISA300:
> isync
> blr
>
> +__init_FSCR_P10:
> + mfspr r3,SPRN_FSCR
> + ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB|FSCR_PREFIX
> + mtspr SPRN_FSCR,r3
> + blr
> +
> __init_FSCR:
> mfspr r3,SPRN_FSCR
> ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
> index 13eba2eb46fe..a17eeb311cdb 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -70,6 +70,8 @@ extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
> extern void __restore_cpu_power8(void);
> extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
> extern void __restore_cpu_power9(void);
> +extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
> +extern void __restore_cpu_power10(void);
> extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
> extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
> extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
> @@ -119,6 +121,10 @@ extern void __restore_cpu_e6500(void);
> PPC_FEATURE2_ARCH_3_00 | \
> PPC_FEATURE2_HAS_IEEE128 | \
> PPC_FEATURE2_DARN )
> +#define COMMON_USER_POWER10 COMMON_USER_POWER9
> +#define COMMON_USER2_POWER10 (COMMON_USER2_POWER9 | \
> + PPC_FEATURE2_ARCH_3_1 | \
> + PPC_FEATURE2_MMA)
>
> #ifdef CONFIG_PPC_BOOK3E_64
> #define COMMON_USER_BOOKE (COMMON_USER_PPC64 | PPC_FEATURE_BOOKE)
> @@ -127,6 +133,14 @@ extern void __restore_cpu_e6500(void);
> PPC_FEATURE_BOOKE)
> #endif
>
> +#ifdef CONFIG_PPC64
> +static void setup_cpu_power10(unsigned long offset, struct cpu_spec* spec)
> +{
> + __setup_cpu_power10(offset, spec);
> + current->thread.fscr |= FSCR_PREFIX;
> +}
> +#endif
> +
> static struct cpu_spec __initdata cpu_specs[] = {
> #ifdef CONFIG_PPC_BOOK3S_64
> { /* PPC970 */
> @@ -367,6 +381,22 @@ static struct cpu_spec __initdata cpu_specs[] = {
> .cpu_restore = __restore_cpu_power9,
> .platform = "power9",
> },
> + { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
> + .pvr_mask = 0xffffffff,
> + .pvr_value = 0x0f000006,
> + .cpu_name = "POWER10 (architected)",
> + .cpu_features = CPU_FTRS_POWER10,
> + .cpu_user_features = COMMON_USER_POWER10,
> + .cpu_user_features2 = COMMON_USER2_POWER10,
> + .mmu_features = MMU_FTRS_POWER10,
> + .icache_bsize = 128,
> + .dcache_bsize = 128,
> + .oprofile_type = PPC_OPROFILE_INVALID,
> + .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> + .cpu_setup = setup_cpu_power10,
> + .cpu_restore = __restore_cpu_power10,
> + .platform = "power10",
> + },
> { /* Power7 */
> .pvr_mask = 0xffff0000,
> .pvr_value = 0x003f0000,
> diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
> index 806be751c336..1ecadbd7e8b2 100644
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -920,7 +920,7 @@ struct option_vector6 {
> } __packed;
>
> struct ibm_arch_vec {
> - struct { u32 mask, val; } pvrs[12];
> + struct { u32 mask, val; } pvrs[14];
>
> u8 num_vectors;
>
> @@ -973,6 +973,14 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
> .mask = cpu_to_be32(0xffff0000), /* POWER9 */
> .val = cpu_to_be32(0x004e0000),
> },
> + {
> + .mask = cpu_to_be32(0xffff0000), /* POWER10 */
> + .val = cpu_to_be32(0x00800000),
Should there be a POWER10 (raw) entry added to cpu_specs[] for this?
> + },
> + {
> + .mask = cpu_to_be32(0xffffffff), /* all 3.1-compliant */
> + .val = cpu_to_be32(0x0f000006),
> + },
> {
> .mask = cpu_to_be32(0xffffffff), /* all 3.00-compliant */
> .val = cpu_to_be32(0x0f000005),
> @@ -1002,7 +1010,7 @@ static const struct ibm_arch_vec ibm_architecture_vec_template __initconst = {
> .byte1 = 0,
> .arch_versions = OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
> OV1_PPC_2_04 | OV1_PPC_2_05 | OV1_PPC_2_06 | OV1_PPC_2_07,
> - .arch_versions3 = OV1_PPC_3_00,
> + .arch_versions3 = OV1_PPC_3_00 | OV1_PPC_3_1,
> },
>
> .vec2_len = VECTOR_LENGTH(sizeof(struct option_vector2)),
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1
From: Jordan Niethe @ 2020-05-19 4:04 UTC (permalink / raw)
To: Alistair Popple; +Cc: aneesh.kumar, mikey, linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200519003157.31946-3-alistair@popple.id.au>
On Tue, May 19, 2020 at 10:39 AM Alistair Popple <alistair@popple.id.au> wrote:
>
> Newer ISA versions are enabled by clearing all bits in the PCR
> associated with previous versions of the ISA. Enable ISA v3.1 support
> by updating the PCR mask to include ISA v3.0. This ensures all PCR
> bits corresponding to earlier architecture versions get cleared
> thereby enabling ISA v3.1 if supported by the hardware.
>
> Signed-off-by: Alistair Popple <alistair@popple.id.au>
> ---
> arch/powerpc/include/asm/cputable.h | 1 +
> arch/powerpc/include/asm/reg.h | 3 ++-
> arch/powerpc/kvm/book3s_hv.c | 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
> index 40a4d3c6fd99..36f894dea9e7 100644
> --- a/arch/powerpc/include/asm/cputable.h
> +++ b/arch/powerpc/include/asm/cputable.h
> @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
> #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
> #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
> #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
> +#define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
>
> #ifndef __ASSEMBLY__
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 773f76402392..1931b1142599 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -485,10 +485,11 @@
> * determine both the compatibility level which we want to emulate and the
> * compatibility level which the host is capable of emulating.
> */
> +#define PCR_ARCH_300 0x10 /* Architecture 3.00 */
> #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
> #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
> #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
> -#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> +#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 | PCR_ARCH_300)
> #define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
> #define SPRN_HEIR 0x153 /* Hypervisor Emulated Instruction Register */
> #define SPRN_TLBINDEXR 0x154 /* P7 TLB control register */
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 93493f0cbfe8..532215040f3e 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32 pvr)
> vcpu->arch.pvr = pvr;
> }
>
> -/* Dummy value used in computing PCR value below */
> -#define PCR_ARCH_300 (PCR_ARCH_207 << 1)
> -
Later will we need
+/* Dummy value used in computing PCR value below */
+#define PCR_ARCH_310 (PCR_ARCH_300 << 1)
?
> static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
> {
> unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v8 12/30] powerpc: Use a function for reading instructions
From: Michael Ellerman @ 2020-05-19 4:05 UTC (permalink / raw)
To: Jordan Niethe, Christophe Leroy
Cc: Christophe Leroy, Alistair Popple, Nicholas Piggin, Balamuruhan S,
naveen.n.rao, linuxppc-dev, Daniel Axtens
In-Reply-To: <CACzsE9qBXBsv0s25DWugjWUaTUZfYpHyONW5ryE4dnLKP5P7cA@mail.gmail.com>
Jordan Niethe <jniethe5@gmail.com> writes:
> On Sun, May 17, 2020 at 4:39 AM Christophe Leroy
> <christophe.leroy@csgroup.eu> wrote:
>>
>> Le 06/05/2020 à 05:40, Jordan Niethe a écrit :
>> > Prefixed instructions will mean there are instructions of different
>> > length. As a result dereferencing a pointer to an instruction will not
>> > necessarily give the desired result. Introduce a function for reading
>> > instructions from memory into the instruction data type.
>>
>>
>> Shouldn't this function be used in mmu_patch_addis() in mm/nohash/8xx.c ?
>>
>> Christophe
> Yes, that would be a good idea.
> mpe here is a fix, along with one I'll
> post for [PATCH v8 11/30] powerpc: Use a datatype for instructions.
I didn't fold this in because I'd prefer one of you send me a patch on
top of the series that converts that code to use the new type.
That way it can be tested separately from this big series.
cheers
> diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
> --- a/arch/powerpc/mm/nohash/8xx.c
> +++ b/arch/powerpc/mm/nohash/8xx.c
> @@ -98,7 +98,7 @@ static void mmu_patch_cmp_limit(s32 *site, unsigned
> long mapped)
>
> static void mmu_patch_addis(s32 *site, long simm)
> {
> - struct ppc_inst instr = *(struct ppc_inst *)patch_site_addr(site);
> + struct ppc_inst instr = ppc_inst_read((struct ppc_inst
> *)patch_site_addr(site));
> unsigned int val = ppc_inst_val(instr);
>
> val &= 0xffff0000;
> --
>>
>> >
>> > Reviewed-by: Alistair Popple <alistair@popple.id.au>
>> > Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
>> > ---
>> > v4: New to series
>> > v5: - Rename read_inst() -> probe_kernel_read_inst()
>> > - No longer modify uprobe probe type in this patch
>> > v6: - feature-fixups.c: do_final_fixups(): Use here
>> > - arch_prepare_kprobe(): patch_instruction(): no longer part of this
>> > patch
>> > - Move probe_kernel_read_inst() out of this patch
>> > - Use in uprobes
>> > v8: style
>> > ---
>> > arch/powerpc/include/asm/inst.h | 5 +++++
>> > arch/powerpc/kernel/kprobes.c | 6 +++---
>> > arch/powerpc/kernel/mce_power.c | 2 +-
>> > arch/powerpc/kernel/optprobes.c | 4 ++--
>> > arch/powerpc/kernel/trace/ftrace.c | 4 ++--
>> > arch/powerpc/kernel/uprobes.c | 2 +-
>> > arch/powerpc/lib/code-patching.c | 26 ++++++++++++++------------
>> > arch/powerpc/lib/feature-fixups.c | 4 ++--
>> > arch/powerpc/xmon/xmon.c | 6 +++---
>> > 9 files changed, 33 insertions(+), 26 deletions(-)
>> >
>> > diff --git a/arch/powerpc/include/asm/inst.h b/arch/powerpc/include/asm/inst.h
>> > index 19d8bb7a1c2b..552e953bf04f 100644
>> > --- a/arch/powerpc/include/asm/inst.h
>> > +++ b/arch/powerpc/include/asm/inst.h
>> > @@ -27,6 +27,11 @@ static inline struct ppc_inst ppc_inst_swab(struct ppc_inst x)
>> > return ppc_inst(swab32(ppc_inst_val(x)));
>> > }
>> >
>> > +static inline struct ppc_inst ppc_inst_read(const struct ppc_inst *ptr)
>> > +{
>> > + return *ptr;
>> > +}
>> > +
>> > static inline bool ppc_inst_equal(struct ppc_inst x, struct ppc_inst y)
>> > {
>> > return ppc_inst_val(x) == ppc_inst_val(y);
>> > diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
>> > index a08ae5803622..f64312dca84f 100644
>> > --- a/arch/powerpc/kernel/kprobes.c
>> > +++ b/arch/powerpc/kernel/kprobes.c
>> > @@ -106,7 +106,7 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, unsigned int offset)
>> > int arch_prepare_kprobe(struct kprobe *p)
>> > {
>> > int ret = 0;
>> > - struct ppc_inst insn = *(struct ppc_inst *)p->addr;
>> > + struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->addr);
>> >
>> > if ((unsigned long)p->addr & 0x03) {
>> > printk("Attempt to register kprobe at an unaligned address\n");
>> > @@ -127,7 +127,7 @@ int arch_prepare_kprobe(struct kprobe *p)
>> > if (!ret) {
>> > memcpy(p->ainsn.insn, p->addr,
>> > MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
>> > - p->opcode = *p->addr;
>> > + p->opcode = ppc_inst_val(insn);
>> > flush_icache_range((unsigned long)p->ainsn.insn,
>> > (unsigned long)p->ainsn.insn + sizeof(kprobe_opcode_t));
>> > }
>> > @@ -217,7 +217,7 @@ NOKPROBE_SYMBOL(arch_prepare_kretprobe);
>> > static int try_to_emulate(struct kprobe *p, struct pt_regs *regs)
>> > {
>> > int ret;
>> > - struct ppc_inst insn = *(struct ppc_inst *)p->ainsn.insn;
>> > + struct ppc_inst insn = ppc_inst_read((struct ppc_inst *)p->ainsn.insn);
>> >
>> > /* regs->nip is also adjusted if emulate_step returns 1 */
>> > ret = emulate_step(regs, insn);
>> > diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
>> > index cd23218c60bb..45c51ba0071b 100644
>> > --- a/arch/powerpc/kernel/mce_power.c
>> > +++ b/arch/powerpc/kernel/mce_power.c
>> > @@ -374,7 +374,7 @@ static int mce_find_instr_ea_and_phys(struct pt_regs *regs, uint64_t *addr,
>> > pfn = addr_to_pfn(regs, regs->nip);
>> > if (pfn != ULONG_MAX) {
>> > instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
>> > - instr = *(struct ppc_inst *)(instr_addr);
>> > + instr = ppc_inst_read((struct ppc_inst *)instr_addr);
>> > if (!analyse_instr(&op, &tmp, instr)) {
>> > pfn = addr_to_pfn(regs, op.ea);
>> > *addr = op.ea;
>> > diff --git a/arch/powerpc/kernel/optprobes.c b/arch/powerpc/kernel/optprobes.c
>> > index 5a71fef71c22..52c1ab3f85aa 100644
>> > --- a/arch/powerpc/kernel/optprobes.c
>> > +++ b/arch/powerpc/kernel/optprobes.c
>> > @@ -100,9 +100,9 @@ static unsigned long can_optimize(struct kprobe *p)
>> > * Ensure that the instruction is not a conditional branch,
>> > * and that can be emulated.
>> > */
>> > - if (!is_conditional_branch(*(struct ppc_inst *)p->ainsn.insn) &&
>> > + if (!is_conditional_branch(ppc_inst_read((struct ppc_inst *)p->ainsn.insn)) &&
>> > analyse_instr(&op, ®s,
>> > - *(struct ppc_inst *)p->ainsn.insn) == 1) {
>> > + ppc_inst_read((struct ppc_inst *)p->ainsn.insn)) == 1) {
>> > emulate_update_regs(®s, &op);
>> > nip = regs.nip;
>> > }
>> > diff --git a/arch/powerpc/kernel/trace/ftrace.c b/arch/powerpc/kernel/trace/ftrace.c
>> > index 3117ed675735..acd5b889815f 100644
>> > --- a/arch/powerpc/kernel/trace/ftrace.c
>> > +++ b/arch/powerpc/kernel/trace/ftrace.c
>> > @@ -848,7 +848,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
>> > struct ppc_inst old, new;
>> > int ret;
>> >
>> > - old = *(struct ppc_inst *)&ftrace_call;
>> > + old = ppc_inst_read((struct ppc_inst *)&ftrace_call);
>> > new = ftrace_call_replace(ip, (unsigned long)func, 1);
>> > ret = ftrace_modify_code(ip, old, new);
>> >
>> > @@ -856,7 +856,7 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
>> > /* Also update the regs callback function */
>> > if (!ret) {
>> > ip = (unsigned long)(&ftrace_regs_call);
>> > - old = *(struct ppc_inst *)&ftrace_regs_call;
>> > + old = ppc_inst_read((struct ppc_inst *)&ftrace_regs_call);
>> > new = ftrace_call_replace(ip, (unsigned long)func, 1);
>> > ret = ftrace_modify_code(ip, old, new);
>> > }
>> > diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
>> > index 31c870287f2b..6893d40a48c5 100644
>> > --- a/arch/powerpc/kernel/uprobes.c
>> > +++ b/arch/powerpc/kernel/uprobes.c
>> > @@ -174,7 +174,7 @@ bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
>> > * emulate_step() returns 1 if the insn was successfully emulated.
>> > * For all other cases, we need to single-step in hardware.
>> > */
>> > - ret = emulate_step(regs, auprobe->insn);
>> > + ret = emulate_step(regs, ppc_inst_read(&auprobe->insn));
>> > if (ret > 0)
>> > return true;
>> >
>> > diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
>> > index 1dff9d9d6645..435fc8e9f45d 100644
>> > --- a/arch/powerpc/lib/code-patching.c
>> > +++ b/arch/powerpc/lib/code-patching.c
>> > @@ -348,9 +348,9 @@ static unsigned long branch_bform_target(const struct ppc_inst *instr)
>> >
>> > unsigned long branch_target(const struct ppc_inst *instr)
>> > {
>> > - if (instr_is_branch_iform(*instr))
>> > + if (instr_is_branch_iform(ppc_inst_read(instr)))
>> > return branch_iform_target(instr);
>> > - else if (instr_is_branch_bform(*instr))
>> > + else if (instr_is_branch_bform(ppc_inst_read(instr)))
>> > return branch_bform_target(instr);
>> >
>> > return 0;
>> > @@ -358,7 +358,8 @@ unsigned long branch_target(const struct ppc_inst *instr)
>> >
>> > int instr_is_branch_to_addr(const struct ppc_inst *instr, unsigned long addr)
>> > {
>> > - if (instr_is_branch_iform(*instr) || instr_is_branch_bform(*instr))
>> > + if (instr_is_branch_iform(ppc_inst_read(instr)) ||
>> > + instr_is_branch_bform(ppc_inst_read(instr)))
>> > return branch_target(instr) == addr;
>> >
>> > return 0;
>> > @@ -368,13 +369,14 @@ int translate_branch(struct ppc_inst *instr, const struct ppc_inst *dest,
>> > const struct ppc_inst *src)
>> > {
>> > unsigned long target;
>> > -
>> > target = branch_target(src);
>> >
>> > - if (instr_is_branch_iform(*src))
>> > - return create_branch(instr, dest, target, ppc_inst_val(*src));
>> > - else if (instr_is_branch_bform(*src))
>> > - return create_cond_branch(instr, dest, target, ppc_inst_val(*src));
>> > + if (instr_is_branch_iform(ppc_inst_read(src)))
>> > + return create_branch(instr, dest, target,
>> > + ppc_inst_val(ppc_inst_read(src)));
>> > + else if (instr_is_branch_bform(ppc_inst_read(src)))
>> > + return create_cond_branch(instr, dest, target,
>> > + ppc_inst_val(ppc_inst_read(src)));
>> >
>> > return 1;
>> > }
>> > @@ -598,7 +600,7 @@ static void __init test_translate_branch(void)
>> > patch_instruction(q, instr);
>> > check(instr_is_branch_to_addr(p, addr));
>> > check(instr_is_branch_to_addr(q, addr));
>> > - check(ppc_inst_equal(*q, ppc_inst(0x4a000000)));
>> > + check(ppc_inst_equal(ppc_inst_read(q), ppc_inst(0x4a000000)));
>> >
>> > /* Maximum positive case, move x to x - 32 MB + 4 */
>> > p = buf + 0x2000000;
>> > @@ -609,7 +611,7 @@ static void __init test_translate_branch(void)
>> > patch_instruction(q, instr);
>> > check(instr_is_branch_to_addr(p, addr));
>> > check(instr_is_branch_to_addr(q, addr));
>> > - check(ppc_inst_equal(*q, ppc_inst(0x49fffffc)));
>> > + check(ppc_inst_equal(ppc_inst_read(q), ppc_inst(0x49fffffc)));
>> >
>> > /* Jump to x + 16 MB moved to x + 20 MB */
>> > p = buf;
>> > @@ -655,7 +657,7 @@ static void __init test_translate_branch(void)
>> > patch_instruction(q, instr);
>> > check(instr_is_branch_to_addr(p, addr));
>> > check(instr_is_branch_to_addr(q, addr));
>> > - check(ppc_inst_equal(*q, ppc_inst(0x43ff8000)));
>> > + check(ppc_inst_equal(ppc_inst_read(q), ppc_inst(0x43ff8000)));
>> >
>> > /* Maximum positive case, move x to x - 32 KB + 4 */
>> > p = buf + 0x8000;
>> > @@ -667,7 +669,7 @@ static void __init test_translate_branch(void)
>> > patch_instruction(q, instr);
>> > check(instr_is_branch_to_addr(p, addr));
>> > check(instr_is_branch_to_addr(q, addr));
>> > - check(ppc_inst_equal(*q, ppc_inst(0x43ff7ffc)));
>> > + check(ppc_inst_equal(ppc_inst_read(q), ppc_inst(0x43ff7ffc)));
>> >
>> > /* Jump to x + 12 KB moved to x + 20 KB */
>> > p = buf;
>> > diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
>> > index fb6e8e8abf4e..c0d3ed4efb7e 100644
>> > --- a/arch/powerpc/lib/feature-fixups.c
>> > +++ b/arch/powerpc/lib/feature-fixups.c
>> > @@ -48,7 +48,7 @@ static int patch_alt_instruction(struct ppc_inst *src, struct ppc_inst *dest,
>> > int err;
>> > struct ppc_inst instr;
>> >
>> > - instr = *src;
>> > + instr = ppc_inst_read(src);
>> >
>> > if (instr_is_relative_branch(*src)) {
>> > struct ppc_inst *target = (struct ppc_inst *)branch_target(src);
>> > @@ -403,7 +403,7 @@ static void do_final_fixups(void)
>> > length = (__end_interrupts - _stext) / sizeof(struct ppc_inst);
>> >
>> > while (length--) {
>> > - raw_patch_instruction(dest, *src);
>> > + raw_patch_instruction(dest, ppc_inst_read(src));
>> > src++;
>> > dest++;
>> > }
>> > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
>> > index e0132d6d24d0..68e0b05d9226 100644
>> > --- a/arch/powerpc/xmon/xmon.c
>> > +++ b/arch/powerpc/xmon/xmon.c
>> > @@ -702,13 +702,13 @@ static int xmon_core(struct pt_regs *regs, int fromipi)
>> > if ((regs->msr & (MSR_IR|MSR_PR|MSR_64BIT)) == (MSR_IR|MSR_64BIT)) {
>> > bp = at_breakpoint(regs->nip);
>> > if (bp != NULL) {
>> > - int stepped = emulate_step(regs, bp->instr[0]);
>> > + int stepped = emulate_step(regs, ppc_inst_read(bp->instr));
>> > if (stepped == 0) {
>> > regs->nip = (unsigned long) &bp->instr[0];
>> > atomic_inc(&bp->ref_count);
>> > } else if (stepped < 0) {
>> > printf("Couldn't single-step %s instruction\n",
>> > - (IS_RFID(bp->instr[0])? "rfid": "mtmsrd"));
>> > + IS_RFID(ppc_inst_read(bp->instr))? "rfid": "mtmsrd");
>> > }
>> > }
>> > }
>> > @@ -949,7 +949,7 @@ static void remove_bpts(void)
>> > if (mread(bp->address, &instr, 4) == 4
>> > && ppc_inst_equal(instr, ppc_inst(bpinstr))
>> > && patch_instruction(
>> > - (struct ppc_inst *)bp->address, bp->instr[0]) != 0)
>> > + (struct ppc_inst *)bp->address, ppc_inst_read(bp->instr)) != 0)
>> > printf("Couldn't remove breakpoint at %lx\n",
>> > bp->address);
>> > }
>> >
^ permalink raw reply
* [PATCH] powerpc/configs: Add LIBNVDIMM to ppc64_defconfig
From: Michael Neuling @ 2020-05-19 4:30 UTC (permalink / raw)
To: mpe; +Cc: Michael Neuling, linuxppc-dev
This gives us OF_PMEM which is useful in mambo.
This adds 153K to the text of ppc64le_defconfig which 0.8% of the
total text.
LIBNVDIMM text data bss dec hex
Without 18574833 5518150 1539240 25632223 1871ddf
With 18727834 5546206 1539368 25813408 189e1a0
Signed-off-by: Michael Neuling <mikey@neuling.org>
---
arch/powerpc/configs/ppc64_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index bae8170d74..0a92549924 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -281,6 +281,7 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=y
CONFIG_VIRTIO_PCI=m
CONFIG_VIRTIO_BALLOON=m
+CONFIG_LIBNVDIMM=y
CONFIG_RAS=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v8 12/30] powerpc: Use a function for reading instructions
From: Christophe Leroy @ 2020-05-19 5:03 UTC (permalink / raw)
To: Michael Ellerman, Jordan Niethe
Cc: Christophe Leroy, Alistair Popple, Nicholas Piggin, Balamuruhan S,
naveen.n.rao, linuxppc-dev, Daniel Axtens
In-Reply-To: <877dx84liy.fsf@mpe.ellerman.id.au>
Le 19/05/2020 à 06:05, Michael Ellerman a écrit :
> Jordan Niethe <jniethe5@gmail.com> writes:
>> On Sun, May 17, 2020 at 4:39 AM Christophe Leroy
>> <christophe.leroy@csgroup.eu> wrote:
>>>
>>> Le 06/05/2020 à 05:40, Jordan Niethe a écrit :
>>>> Prefixed instructions will mean there are instructions of different
>>>> length. As a result dereferencing a pointer to an instruction will not
>>>> necessarily give the desired result. Introduce a function for reading
>>>> instructions from memory into the instruction data type.
>>>
>>>
>>> Shouldn't this function be used in mmu_patch_addis() in mm/nohash/8xx.c ?
>>>
>>> Christophe
>
>> Yes, that would be a good idea.
>
>> mpe here is a fix, along with one I'll
>> post for [PATCH v8 11/30] powerpc: Use a datatype for instructions.
>
> I didn't fold this in because I'd prefer one of you send me a patch on
> top of the series that converts that code to use the new type.
>
> That way it can be tested separately from this big series.
>
All this code is going away with the series implementing the use of
hugepages for kernel mappings on 8xx
(https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=176094)
that I hope will go in 5.8, so there is no point in sending a patch to
change that I guess.
Is there anything special I need to do to secure the merging of that
series in 5.8 ?
Christophe
^ permalink raw reply
* Re: [PATCH v2 3/5] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier
From: Aneesh Kumar K.V @ 2020-05-19 5:30 UTC (permalink / raw)
To: Dan Williams; +Cc: alistair, linuxppc-dev, linux-nvdimm
In-Reply-To: <CAPcyv4iAdrdMiSzVr1UL9Naya+Rq70WVuKqCCNFHe1C4n+E6Tw@mail.gmail.com>
Hi Dan,
Apologies for the delay in response. I was waiting for feedback from
hardware team before responding to this email.
Dan Williams <dan.j.williams@intel.com> writes:
> On Tue, May 12, 2020 at 8:47 PM Aneesh Kumar K.V
> <aneesh.kumar@linux.ibm.com> wrote:
>>
>> Architectures like ppc64 provide persistent memory specific barriers
>> that will ensure that all stores for which the modifications are
>> written to persistent storage by preceding dcbfps and dcbstps
>> instructions have updated persistent storage before any data
>> access or data transfer caused by subsequent instructions is initiated.
>> This is in addition to the ordering done by wmb()
>>
>> Update nvdimm core such that architecture can use barriers other than
>> wmb to ensure all previous writes are architecturally visible for
>> the platform buffer flush.
>
> This seems like an exceedingly bad idea, maybe I'm missing something.
> This implies that the deployed base of DAX applications using the old
> instruction sequence are going to regress on new hardware that
> requires the new instructions to be deployed.
pmdk support for ppc64 is still work in progress and there is pull
request to switch pmdk to use new instruction.
https://github.com/tuliom/pmdk/commit/fix-flush
All userspace applications will be switched to use the new
instructions. The new instructions are designed such that when running on P8
and P9 they behave as 'dcbf' and 'hwsync'.
Applications using new instructions will behave as expected when running
on P8 and P9. Only future hardware will differentiate between 'dcbf' and
'dcbfps'
> I'm thinking the kernel
> should go as far as to disable DAX operation by default on new
> hardware until userspace asserts that it is prepared to switch to the
> new implementation. Is there any other way to ensure the forward
> compatibility of deployed ppc64 DAX applications?
AFAIU there is no released persistent memory hardware on ppc64 platform
and we need to make sure before applications get enabled to use these
persistent memory devices, they should switch to use the new
instruction?
>
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> ---
>> drivers/nvdimm/region_devs.c | 8 ++++----
>> include/linux/libnvdimm.h | 4 ++++
>> 2 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c
>> index ccbb5b43b8b2..88ea34a9c7fd 100644
>> --- a/drivers/nvdimm/region_devs.c
>> +++ b/drivers/nvdimm/region_devs.c
>> @@ -1216,13 +1216,13 @@ int generic_nvdimm_flush(struct nd_region *nd_region)
>> idx = this_cpu_add_return(flush_idx, hash_32(current->pid + idx, 8));
>>
>> /*
>> - * The first wmb() is needed to 'sfence' all previous writes
>> - * such that they are architecturally visible for the platform
>> - * buffer flush. Note that we've already arranged for pmem
>> + * The first arch_pmem_flush_barrier() is needed to 'sfence' all
>> + * previous writes such that they are architecturally visible for
>> + * the platform buffer flush. Note that we've already arranged for pmem
>> * writes to avoid the cache via memcpy_flushcache(). The final
>> * wmb() ensures ordering for the NVDIMM flush write.
>> */
>> - wmb();
>> + arch_pmem_flush_barrier();
>> for (i = 0; i < nd_region->ndr_mappings; i++)
>> if (ndrd_get_flush_wpq(ndrd, i, 0))
>> writeq(1, ndrd_get_flush_wpq(ndrd, i, idx));
>> diff --git a/include/linux/libnvdimm.h b/include/linux/libnvdimm.h
>> index 18da4059be09..66f6c65bd789 100644
>> --- a/include/linux/libnvdimm.h
>> +++ b/include/linux/libnvdimm.h
>> @@ -286,4 +286,8 @@ static inline void arch_invalidate_pmem(void *addr, size_t size)
>> }
>> #endif
>>
>> +#ifndef arch_pmem_flush_barrier
>> +#define arch_pmem_flush_barrier() wmb()
>> +#endif
>> +
>> #endif /* __LIBNVDIMM_H__ */
>> --
>> 2.26.2
>>
> _______________________________________________
> Linux-nvdimm mailing list -- linux-nvdimm@lists.01.org
> To unsubscribe send an email to linux-nvdimm-leave@lists.01.org
^ permalink raw reply
* Re: [PATCH v2 2/7] powerpc: Add support for ISA v3.1
From: Alistair Popple @ 2020-05-19 5:45 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Jordan Niethe, mikey, Nicholas Piggin, aneesh.kumar
In-Reply-To: <CACzsE9pF6Q01eMtzM1esnGC1k=BWZuq8gPMRZC4uaHNoQ=VdzA@mail.gmail.com>
On Tuesday, 19 May 2020 2:04:51 PM AEST Jordan Niethe wrote:
> On Tue, May 19, 2020 at 10:39 AM Alistair Popple <alistair@popple.id.au>
wrote:
> > Newer ISA versions are enabled by clearing all bits in the PCR
> > associated with previous versions of the ISA. Enable ISA v3.1 support
> > by updating the PCR mask to include ISA v3.0. This ensures all PCR
> > bits corresponding to earlier architecture versions get cleared
> > thereby enabling ISA v3.1 if supported by the hardware.
> >
> > Signed-off-by: Alistair Popple <alistair@popple.id.au>
> > ---
> >
> > arch/powerpc/include/asm/cputable.h | 1 +
> > arch/powerpc/include/asm/reg.h | 3 ++-
> > arch/powerpc/kvm/book3s_hv.c | 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/powerpc/include/asm/cputable.h
> > b/arch/powerpc/include/asm/cputable.h index 40a4d3c6fd99..36f894dea9e7
> > 100644
> > --- a/arch/powerpc/include/asm/cputable.h
> > +++ b/arch/powerpc/include/asm/cputable.h
> > @@ -213,6 +213,7 @@ static inline void cpu_feature_keys_init(void) { }
> >
> > #define CPU_FTR_P9_TIDR
> > LONG_ASM_CONST(0x0000800000000000) #define CPU_FTR_P9_TLBIE_ERAT_BUG
> > LONG_ASM_CONST(0x0001000000000000) #define
> > CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)>
> > +#define CPU_FTR_ARCH_31
> > LONG_ASM_CONST(0x0004000000000000)>
> > #ifndef __ASSEMBLY__
> >
> > diff --git a/arch/powerpc/include/asm/reg.h
> > b/arch/powerpc/include/asm/reg.h index 773f76402392..1931b1142599 100644
> > --- a/arch/powerpc/include/asm/reg.h
> > +++ b/arch/powerpc/include/asm/reg.h
> > @@ -485,10 +485,11 @@
> >
> > * determine both the compatibility level which we want to emulate and
> > the
> > * compatibility level which the host is capable of emulating.
> > */
> >
> > +#define PCR_ARCH_300 0x10 /* Architecture 3.00 */
> >
> > #define PCR_ARCH_207 0x8 /* Architecture 2.07 */
> > #define PCR_ARCH_206 0x4 /* Architecture 2.06 */
> > #define PCR_ARCH_205 0x2 /* Architecture 2.05 */
> >
> > -#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
> > +#define PCR_LOW_BITS (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205 |
> > PCR_ARCH_300)>
> > #define PCR_MASK ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved
> > Bits */ #define SPRN_HEIR 0x153 /* Hypervisor Emulated
> > Instruction Register */ #define SPRN_TLBINDEXR 0x154 /* P7 TLB control
> > register */
> >
> > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> > index 93493f0cbfe8..532215040f3e 100644
> > --- a/arch/powerpc/kvm/book3s_hv.c
> > +++ b/arch/powerpc/kvm/book3s_hv.c
> > @@ -344,9 +344,6 @@ static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu,
> > u32 pvr)>
> > vcpu->arch.pvr = pvr;
> >
> > }
> >
> > -/* Dummy value used in computing PCR value below */
> > -#define PCR_ARCH_300 (PCR_ARCH_207 << 1)
> > -
>
> Later will we need
> +/* Dummy value used in computing PCR value below */
> +#define PCR_ARCH_310 (PCR_ARCH_300 << 1)
> ?
Correct. I left that out of this patch series though as I am putting together
a separate series for basic P10 KVM enablement which will add the definition
for ARCH 3.1.
- Alistair
> > static int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
> > {
> >
> > unsigned long host_pcr_bit = 0, guest_pcr_bit = 0;
> >
> > --
> > 2.20.1
^ permalink raw reply
* [PATCH v4 01/45] powerpc/kasan: Fix error detection on memory allocation
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
In case (k_start & PAGE_MASK) doesn't equal (kstart), 'va' will never be
NULL allthough 'block' is NULL
Check the return of memblock_alloc() directly instead of
the resulting address in the loop.
Fixes: 509cd3f2b473 ("powerpc/32: Simplify KASAN init")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/kasan/kasan_init_32.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c b/arch/powerpc/mm/kasan/kasan_init_32.c
index cbcad369fcb2..8b15fe09b967 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -76,15 +76,14 @@ static int __init kasan_init_region(void *start, size_t size)
return ret;
block = memblock_alloc(k_end - k_start, PAGE_SIZE);
+ if (!block)
+ return -ENOMEM;
for (k_cur = k_start & PAGE_MASK; k_cur < k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_ptr_k(k_cur);
void *va = block + k_cur - k_start;
pte_t pte = pfn_pte(PHYS_PFN(__pa(va)), PAGE_KERNEL);
- if (!va)
- return -ENOMEM;
-
__set_pte_at(&init_mm, k_cur, pte_offset_kernel(pmd, k_cur), pte, 0);
}
flush_tlb_kernel_range(k_start, k_end);
--
2.25.0
^ permalink raw reply related
* [PATCH v4 00/45] Use hugepages to map kernel mem on 8xx
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
The main purpose of this big series is to:
- reorganise huge page handling to avoid using mm_slices.
- use huge pages to map kernel memory on the 8xx.
The 8xx supports 4 page sizes: 4k, 16k, 512k and 8M.
It uses 2 Level page tables, PGD having 1024 entries, each entry
covering 4M address space. Then each page table has 1024 entries.
At the time being, page sizes are managed in PGD entries, implying
the use of mm_slices as it can't mix several pages of the same size
in one page table.
The first purpose of this series is to reorganise things so that
standard page tables can also handle 512k pages. This is done by
adding a new _PAGE_HUGE flag which will be copied into the Level 1
entry in the TLB miss handler. That done, we have 2 types of pages:
- PGD entries to regular page tables handling 4k/16k and 512k pages
- PGD entries to hugepd tables handling 8M pages.
There is no need to mix 8M pages with other sizes, because a 8M page
will use more than what a single PGD covers.
Then comes the second purpose of this series. At the time being, the
8xx has implemented special handling in the TLB miss handlers in order
to transparently map kernel linear address space and the IMMR using
huge pages by building the TLB entries in assembly at the time of the
exception.
As mm_slices is only for user space pages, and also because it would
anyway not be convenient to slice kernel address space, it was not
possible to use huge pages for kernel address space. But after step
one of the series, it is now more flexible to use huge pages.
This series drop all assembly 'just in time' handling of huge pages
and use huge pages in page tables instead.
Once the above is done, then comes icing on the cake:
- Use huge pages for KASAN shadow mapping
- Allow pinned TLBs with strict kernel rwx
- Allow pinned TLBs with debug pagealloc
Then, last but not least, those modifications for the 8xx allows the
following improvement on book3s/32:
- Mapping KASAN shadow with BATs
- Allowing BATs with debug pagealloc
All this allows to considerably simplify TLB miss handlers and associated
initialisation. The overhead of reading page tables is negligible
compared to the reduction of the miss handlers.
While we were at touching pte_update(), some cleanup was done
there too.
Tested widely on 8xx and 832x. Boot tested on QEMU MAC99.
Changes in v4:
- Rebased on top of powerpc/next following the merge of prefix instructions series.
Changes in v3:
- Fixed the handling of leaf pages page size which didn't build on PPC64 and was invisibily bogus on PPC32 (patch 12)
Changes in v2:
- Selecting HUGETLBFS instead of HUGETLB_PAGE which leads to link failure.
- Rebase on latest powerpc/merge branch
- Reworked the way TLB 28 to 31 are pinned because it was not working.
Christophe Leroy (45):
powerpc/kasan: Fix error detection on memory allocation
powerpc/kasan: Fix issues by lowering KASAN_SHADOW_END
powerpc/kasan: Fix shadow pages allocation failure
powerpc/kasan: Remove unnecessary page table locking
powerpc/kasan: Refactor update of early shadow mappings
powerpc/kasan: Declare kasan_init_region() weak
powerpc/ptdump: Limit size of flags text to 1/2 chars on PPC32
powerpc/ptdump: Reorder flags
powerpc/ptdump: Add _PAGE_COHERENT flag
powerpc/ptdump: Display size of BATs
powerpc/ptdump: Standardise display of BAT flags
powerpc/ptdump: Properly handle non standard page size
powerpc/ptdump: Handle hugepd at PGD level
powerpc/32s: Don't warn when mapping RO data ROX.
powerpc/mm: Allocate static page tables for fixmap
powerpc/mm: Fix conditions to perform MMU specific management by
blocks on PPC32.
powerpc/mm: PTE_ATOMIC_UPDATES is only for 40x
powerpc/mm: Refactor pte_update() on nohash/32
powerpc/mm: Refactor pte_update() on book3s/32
powerpc/mm: Standardise __ptep_test_and_clear_young() params between
PPC32 and PPC64
powerpc/mm: Standardise pte_update() prototype between PPC32 and PPC64
powerpc/mm: Create a dedicated pte_update() for 8xx
powerpc/mm: Reduce hugepd size for 8M hugepages on 8xx
powerpc/8xx: Drop CONFIG_8xx_COPYBACK option
powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.
powerpc/8xx: Manage 512k huge pages as standard pages.
powerpc/8xx: Only 8M pages are hugepte pages now
powerpc/8xx: MM_SLICE is not needed anymore
powerpc/8xx: Move PPC_PIN_TLB options into 8xx Kconfig
powerpc/8xx: Add function to set pinned TLBs
powerpc/8xx: Don't set IMMR map anymore at boot
powerpc/8xx: Always pin TLBs at startup.
powerpc/8xx: Drop special handling of Linear and IMMR mappings in I/D
TLB handlers
powerpc/8xx: Remove now unused TLB miss functions
powerpc/8xx: Move DTLB perf handling closer.
powerpc/mm: Don't be too strict with _etext alignment on PPC32
powerpc/8xx: Refactor kernel address boundary comparison
powerpc/8xx: Add a function to early map kernel via huge pages
powerpc/8xx: Map IMMR with a huge page
powerpc/8xx: Map linear memory with huge pages
powerpc/8xx: Allow STRICT_KERNEL_RwX with pinned TLB
powerpc/8xx: Allow large TLBs with DEBUG_PAGEALLOC
powerpc/8xx: Implement dedicated kasan_init_region()
powerpc/32s: Allow mapping with BATs with DEBUG_PAGEALLOC
powerpc/32s: Implement dedicated kasan_init_region()
arch/powerpc/Kconfig | 62 +--
arch/powerpc/configs/adder875_defconfig | 1 -
arch/powerpc/configs/ep88xc_defconfig | 1 -
arch/powerpc/configs/mpc866_ads_defconfig | 1 -
arch/powerpc/configs/mpc885_ads_defconfig | 1 -
arch/powerpc/configs/tqm8xx_defconfig | 1 -
arch/powerpc/include/asm/book3s/32/pgtable.h | 78 ++--
arch/powerpc/include/asm/fixmap.h | 4 +
arch/powerpc/include/asm/hugetlb.h | 4 -
arch/powerpc/include/asm/kasan.h | 10 +-
.../include/asm/nohash/32/hugetlb-8xx.h | 32 +-
arch/powerpc/include/asm/nohash/32/mmu-8xx.h | 74 +---
arch/powerpc/include/asm/nohash/32/pgtable.h | 104 +++--
arch/powerpc/include/asm/nohash/32/pte-8xx.h | 4 +-
arch/powerpc/include/asm/nohash/32/slice.h | 20 -
arch/powerpc/include/asm/nohash/64/pgtable.h | 28 +-
arch/powerpc/include/asm/nohash/pgtable.h | 2 +-
arch/powerpc/include/asm/pgtable.h | 2 +
arch/powerpc/include/asm/slice.h | 2 -
arch/powerpc/kernel/head_8xx.S | 354 ++++++++----------
arch/powerpc/kernel/setup_32.c | 2 +-
arch/powerpc/kernel/vmlinux.lds.S | 3 +-
arch/powerpc/mm/book3s32/mmu.c | 12 +-
arch/powerpc/mm/hugetlbpage.c | 41 +-
arch/powerpc/mm/init_32.c | 12 +-
arch/powerpc/mm/kasan/8xx.c | 74 ++++
arch/powerpc/mm/kasan/Makefile | 2 +
arch/powerpc/mm/kasan/book3s_32.c | 57 +++
arch/powerpc/mm/kasan/kasan_init_32.c | 88 ++---
arch/powerpc/mm/mmu_decl.h | 4 +
arch/powerpc/mm/nohash/8xx.c | 226 ++++++-----
arch/powerpc/mm/pgtable.c | 34 +-
arch/powerpc/mm/pgtable_32.c | 22 +-
arch/powerpc/mm/ptdump/8xx.c | 52 +--
arch/powerpc/mm/ptdump/bats.c | 41 +-
arch/powerpc/mm/ptdump/ptdump.c | 71 +++-
arch/powerpc/mm/ptdump/ptdump.h | 3 +
arch/powerpc/mm/ptdump/shared.c | 58 +--
arch/powerpc/perf/8xx-pmu.c | 10 -
arch/powerpc/platforms/8xx/Kconfig | 50 ++-
arch/powerpc/platforms/Kconfig.cputype | 2 +-
arch/powerpc/sysdev/cpm_common.c | 2 +
42 files changed, 853 insertions(+), 798 deletions(-)
delete mode 100644 arch/powerpc/include/asm/nohash/32/slice.h
create mode 100644 arch/powerpc/mm/kasan/8xx.c
create mode 100644 arch/powerpc/mm/kasan/book3s_32.c
--
2.25.0
^ permalink raw reply
* [PATCH v4 02/45] powerpc/kasan: Fix issues by lowering KASAN_SHADOW_END
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
At the time being, KASAN_SHADOW_END is 0x100000000, which
is 0 in 32 bits representation.
This leads to a couple of issues:
- kasan_remap_early_shadow_ro() does nothing because the comparison
k_cur < k_end is always false.
- In ptdump, address comparison for markers display fails and the
marker's name is printed at the start of the KASAN area instead of
being printed at the end.
However, there is no need to shadow the KASAN shadow area itself,
so the KASAN shadow area can stop shadowing memory at the start
of itself.
With a PAGE_OFFSET set to 0xc0000000, KASAN shadow area is then going
from 0xf8000000 to 0xff000000.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Fixes: cbd18991e24f ("powerpc/mm: Fix an Oops in kasan_mmu_init()")
Cc: stable@vger.kernel.org
---
arch/powerpc/include/asm/kasan.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index fbff9ff9032e..fc900937f653 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -23,9 +23,7 @@
#define KASAN_SHADOW_OFFSET ASM_CONST(CONFIG_KASAN_SHADOW_OFFSET)
-#define KASAN_SHADOW_END 0UL
-
-#define KASAN_SHADOW_SIZE (KASAN_SHADOW_END - KASAN_SHADOW_START)
+#define KASAN_SHADOW_END (-(-KASAN_SHADOW_START >> KASAN_SHADOW_SCALE_SHIFT))
#ifdef CONFIG_KASAN
void kasan_early_init(void);
--
2.25.0
^ permalink raw reply related
* [PATCH v4 03/45] powerpc/kasan: Fix shadow pages allocation failure
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
Doing kasan pages allocation in MMU_init is too early, kernel doesn't
have access yet to the entire memory space and memblock_alloc() fails
when the kernel is a bit big.
Do it from kasan_init() instead.
Fixes: 2edb16efc899 ("powerpc/32: Add KASAN support")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/kasan.h | 2 --
arch/powerpc/mm/init_32.c | 2 --
arch/powerpc/mm/kasan/kasan_init_32.c | 4 +++-
3 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index fc900937f653..4769bbf7173a 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -27,12 +27,10 @@
#ifdef CONFIG_KASAN
void kasan_early_init(void);
-void kasan_mmu_init(void);
void kasan_init(void);
void kasan_late_init(void);
#else
static inline void kasan_init(void) { }
-static inline void kasan_mmu_init(void) { }
static inline void kasan_late_init(void) { }
#endif
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index 872df48ae41b..a6991ef8727d 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -170,8 +170,6 @@ void __init MMU_init(void)
btext_unmap();
#endif
- kasan_mmu_init();
-
setup_kup();
/* Shortly after that, the entire linear mapping will be available */
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c b/arch/powerpc/mm/kasan/kasan_init_32.c
index 8b15fe09b967..b7c287adfd59 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -131,7 +131,7 @@ static void __init kasan_unmap_early_shadow_vmalloc(void)
flush_tlb_kernel_range(k_start, k_end);
}
-void __init kasan_mmu_init(void)
+static void __init kasan_mmu_init(void)
{
int ret;
struct memblock_region *reg;
@@ -159,6 +159,8 @@ void __init kasan_mmu_init(void)
void __init kasan_init(void)
{
+ kasan_mmu_init();
+
kasan_remap_early_shadow_ro();
clear_page(kasan_early_shadow_page);
--
2.25.0
^ permalink raw reply related
* [PATCH v4 04/45] powerpc/kasan: Remove unnecessary page table locking
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
Commit 45ff3c559585 ("powerpc/kasan: Fix parallel loading of
modules.") added spinlocks to manage parallele module loading.
Since then commit 47febbeeec44 ("powerpc/32: Force KASAN_VMALLOC for
modules") converted the module loading to KASAN_VMALLOC.
The spinlocking has then become unneeded and can be removed to
simplify kasan_init_shadow_page_tables()
Also remove inclusion of linux/moduleloader.h and linux/vmalloc.h
which are not needed anymore since the removal of modules management.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/kasan/kasan_init_32.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c b/arch/powerpc/mm/kasan/kasan_init_32.c
index b7c287adfd59..91e2ade75192 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -5,9 +5,7 @@
#include <linux/kasan.h>
#include <linux/printk.h>
#include <linux/memblock.h>
-#include <linux/moduleloader.h>
#include <linux/sched/task.h>
-#include <linux/vmalloc.h>
#include <asm/pgalloc.h>
#include <asm/code-patching.h>
#include <mm/mmu_decl.h>
@@ -34,31 +32,22 @@ static int __init kasan_init_shadow_page_tables(unsigned long k_start, unsigned
{
pmd_t *pmd;
unsigned long k_cur, k_next;
- pte_t *new = NULL;
pmd = pmd_ptr_k(k_start);
for (k_cur = k_start; k_cur != k_end; k_cur = k_next, pmd++) {
+ pte_t *new;
+
k_next = pgd_addr_end(k_cur, k_end);
if ((void *)pmd_page_vaddr(*pmd) != kasan_early_shadow_pte)
continue;
- if (!new)
- new = memblock_alloc(PTE_FRAG_SIZE, PTE_FRAG_SIZE);
+ new = memblock_alloc(PTE_FRAG_SIZE, PTE_FRAG_SIZE);
if (!new)
return -ENOMEM;
kasan_populate_pte(new, PAGE_KERNEL);
-
- smp_wmb(); /* See comment in __pte_alloc */
-
- spin_lock(&init_mm.page_table_lock);
- /* Has another populated it ? */
- if (likely((void *)pmd_page_vaddr(*pmd) == kasan_early_shadow_pte)) {
- pmd_populate_kernel(&init_mm, pmd, new);
- new = NULL;
- }
- spin_unlock(&init_mm.page_table_lock);
+ pmd_populate_kernel(&init_mm, pmd, new);
}
return 0;
}
--
2.25.0
^ permalink raw reply related
* [PATCH v4 05/45] powerpc/kasan: Refactor update of early shadow mappings
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
kasan_remap_early_shadow_ro() and kasan_unmap_early_shadow_vmalloc()
are both updating the early shadow mapping: the first one sets
the mapping read-only while the other clears the mapping.
Refactor and create kasan_update_early_region()
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/kasan/kasan_init_32.c | 39 +++++++++++++--------------
1 file changed, 18 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c b/arch/powerpc/mm/kasan/kasan_init_32.c
index 91e2ade75192..10481d904fea 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -79,45 +79,42 @@ static int __init kasan_init_region(void *start, size_t size)
return 0;
}
-static void __init kasan_remap_early_shadow_ro(void)
+static void __init
+kasan_update_early_region(unsigned long k_start, unsigned long k_end, pte_t pte)
{
- pgprot_t prot = kasan_prot_ro();
- unsigned long k_start = KASAN_SHADOW_START;
- unsigned long k_end = KASAN_SHADOW_END;
unsigned long k_cur;
phys_addr_t pa = __pa(kasan_early_shadow_page);
- kasan_populate_pte(kasan_early_shadow_pte, prot);
-
- for (k_cur = k_start & PAGE_MASK; k_cur != k_end; k_cur += PAGE_SIZE) {
+ for (k_cur = k_start; k_cur != k_end; k_cur += PAGE_SIZE) {
pmd_t *pmd = pmd_ptr_k(k_cur);
pte_t *ptep = pte_offset_kernel(pmd, k_cur);
if ((pte_val(*ptep) & PTE_RPN_MASK) != pa)
continue;
- __set_pte_at(&init_mm, k_cur, ptep, pfn_pte(PHYS_PFN(pa), prot), 0);
+ __set_pte_at(&init_mm, k_cur, ptep, pte, 0);
}
- flush_tlb_kernel_range(KASAN_SHADOW_START, KASAN_SHADOW_END);
+
+ flush_tlb_kernel_range(k_start, k_end);
}
-static void __init kasan_unmap_early_shadow_vmalloc(void)
+static void __init kasan_remap_early_shadow_ro(void)
{
- unsigned long k_start = (unsigned long)kasan_mem_to_shadow((void *)VMALLOC_START);
- unsigned long k_end = (unsigned long)kasan_mem_to_shadow((void *)VMALLOC_END);
- unsigned long k_cur;
+ pgprot_t prot = kasan_prot_ro();
phys_addr_t pa = __pa(kasan_early_shadow_page);
- for (k_cur = k_start & PAGE_MASK; k_cur < k_end; k_cur += PAGE_SIZE) {
- pmd_t *pmd = pmd_offset(pud_offset(pgd_offset_k(k_cur), k_cur), k_cur);
- pte_t *ptep = pte_offset_kernel(pmd, k_cur);
+ kasan_populate_pte(kasan_early_shadow_pte, prot);
- if ((pte_val(*ptep) & PTE_RPN_MASK) != pa)
- continue;
+ kasan_update_early_region(KASAN_SHADOW_START, KASAN_SHADOW_END,
+ pfn_pte(PHYS_PFN(pa), prot));
+}
- __set_pte_at(&init_mm, k_cur, ptep, __pte(0), 0);
- }
- flush_tlb_kernel_range(k_start, k_end);
+static void __init kasan_unmap_early_shadow_vmalloc(void)
+{
+ unsigned long k_start = (unsigned long)kasan_mem_to_shadow((void *)VMALLOC_START);
+ unsigned long k_end = (unsigned long)kasan_mem_to_shadow((void *)VMALLOC_END);
+
+ kasan_update_early_region(k_start, k_end, __pte(0));
}
static void __init kasan_mmu_init(void)
--
2.25.0
^ permalink raw reply related
* [PATCH v4 06/45] powerpc/kasan: Declare kasan_init_region() weak
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
In order to alloc sub-arches to alloc KASAN regions using optimised
methods (Huge pages on 8xx, BATs on BOOK3S, ...), declare
kasan_init_region() weak.
Also make kasan_init_shadow_page_tables() accessible from outside,
so that it can be called from the specific kasan_init_region()
functions if needed.
And populate remaining KASAN address space only once performed
the region mapping, to allow 8xx to allocate hugepd instead of
standard page tables for mapping via 8M hugepages.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/include/asm/kasan.h | 3 +++
arch/powerpc/mm/kasan/kasan_init_32.c | 21 +++++++++++----------
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/kasan.h b/arch/powerpc/include/asm/kasan.h
index 4769bbf7173a..107a24c3f7b3 100644
--- a/arch/powerpc/include/asm/kasan.h
+++ b/arch/powerpc/include/asm/kasan.h
@@ -34,5 +34,8 @@ static inline void kasan_init(void) { }
static inline void kasan_late_init(void) { }
#endif
+int kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end);
+int kasan_init_region(void *start, size_t size);
+
#endif /* __ASSEMBLY */
#endif
diff --git a/arch/powerpc/mm/kasan/kasan_init_32.c b/arch/powerpc/mm/kasan/kasan_init_32.c
index 10481d904fea..76d418af4ce8 100644
--- a/arch/powerpc/mm/kasan/kasan_init_32.c
+++ b/arch/powerpc/mm/kasan/kasan_init_32.c
@@ -28,7 +28,7 @@ static void __init kasan_populate_pte(pte_t *ptep, pgprot_t prot)
__set_pte_at(&init_mm, va, ptep, pfn_pte(PHYS_PFN(pa), prot), 0);
}
-static int __init kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end)
+int __init kasan_init_shadow_page_tables(unsigned long k_start, unsigned long k_end)
{
pmd_t *pmd;
unsigned long k_cur, k_next;
@@ -52,7 +52,7 @@ static int __init kasan_init_shadow_page_tables(unsigned long k_start, unsigned
return 0;
}
-static int __init kasan_init_region(void *start, size_t size)
+int __init __weak kasan_init_region(void *start, size_t size)
{
unsigned long k_start = (unsigned long)kasan_mem_to_shadow(start);
unsigned long k_end = (unsigned long)kasan_mem_to_shadow(start + size);
@@ -122,14 +122,6 @@ static void __init kasan_mmu_init(void)
int ret;
struct memblock_region *reg;
- if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ||
- IS_ENABLED(CONFIG_KASAN_VMALLOC)) {
- ret = kasan_init_shadow_page_tables(KASAN_SHADOW_START, KASAN_SHADOW_END);
-
- if (ret)
- panic("kasan: kasan_init_shadow_page_tables() failed");
- }
-
for_each_memblock(memory, reg) {
phys_addr_t base = reg->base;
phys_addr_t top = min(base + reg->size, total_lowmem);
@@ -141,6 +133,15 @@ static void __init kasan_mmu_init(void)
if (ret)
panic("kasan: kasan_init_region() failed");
}
+
+ if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE) ||
+ IS_ENABLED(CONFIG_KASAN_VMALLOC)) {
+ ret = kasan_init_shadow_page_tables(KASAN_SHADOW_START, KASAN_SHADOW_END);
+
+ if (ret)
+ panic("kasan: kasan_init_shadow_page_tables() failed");
+ }
+
}
void __init kasan_init(void)
--
2.25.0
^ permalink raw reply related
* [PATCH v4 07/45] powerpc/ptdump: Limit size of flags text to 1/2 chars on PPC32
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
In order to have all flags fit on a 80 chars wide screen,
reduce the flags to 1 char (2 where ambiguous).
No cache is 'i'
User is 'ur' (Supervisor would be sr)
Shared (for 8xx) becomes 'sh' (it was 'user' when not shared but
that was ambiguous because that's not entirely right)
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/8xx.c | 33 ++++++++++++++++---------------
arch/powerpc/mm/ptdump/shared.c | 35 +++++++++++++++++----------------
2 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index 9e2d8e847d6e..ca9ce94672f5 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -12,9 +12,9 @@
static const struct flag_info flag_array[] = {
{
.mask = _PAGE_SH,
- .val = 0,
- .set = "user",
- .clear = " ",
+ .val = _PAGE_SH,
+ .set = "sh",
+ .clear = " ",
}, {
.mask = _PAGE_RO | _PAGE_NA,
.val = 0,
@@ -30,37 +30,38 @@ static const struct flag_info flag_array[] = {
}, {
.mask = _PAGE_EXEC,
.val = _PAGE_EXEC,
- .set = " X ",
- .clear = " ",
+ .set = "x",
+ .clear = " ",
}, {
.mask = _PAGE_PRESENT,
.val = _PAGE_PRESENT,
- .set = "present",
- .clear = " ",
+ .set = "p",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val = _PAGE_GUARDED,
- .set = "guarded",
- .clear = " ",
+ .set = "g",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val = _PAGE_DIRTY,
- .set = "dirty",
- .clear = " ",
+ .set = "d",
+ .clear = " ",
}, {
.mask = _PAGE_ACCESSED,
.val = _PAGE_ACCESSED,
- .set = "accessed",
- .clear = " ",
+ .set = "a",
+ .clear = " ",
}, {
.mask = _PAGE_NO_CACHE,
.val = _PAGE_NO_CACHE,
- .set = "no cache",
- .clear = " ",
+ .set = "i",
+ .clear = " ",
}, {
.mask = _PAGE_SPECIAL,
.val = _PAGE_SPECIAL,
- .set = "special",
+ .set = "s",
+ .clear = " ",
}
};
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index f7ed2f187cb0..44a8a64a664f 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -13,8 +13,8 @@ static const struct flag_info flag_array[] = {
{
.mask = _PAGE_USER,
.val = _PAGE_USER,
- .set = "user",
- .clear = " ",
+ .set = "ur",
+ .clear = " ",
}, {
.mask = _PAGE_RW,
.val = _PAGE_RW,
@@ -23,42 +23,43 @@ static const struct flag_info flag_array[] = {
}, {
.mask = _PAGE_EXEC,
.val = _PAGE_EXEC,
- .set = " X ",
- .clear = " ",
+ .set = "x",
+ .clear = " ",
}, {
.mask = _PAGE_PRESENT,
.val = _PAGE_PRESENT,
- .set = "present",
- .clear = " ",
+ .set = "p",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val = _PAGE_GUARDED,
- .set = "guarded",
- .clear = " ",
+ .set = "g",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val = _PAGE_DIRTY,
- .set = "dirty",
- .clear = " ",
+ .set = "d",
+ .clear = " ",
}, {
.mask = _PAGE_ACCESSED,
.val = _PAGE_ACCESSED,
- .set = "accessed",
- .clear = " ",
+ .set = "a",
+ .clear = " ",
}, {
.mask = _PAGE_WRITETHRU,
.val = _PAGE_WRITETHRU,
- .set = "write through",
- .clear = " ",
+ .set = "w",
+ .clear = " ",
}, {
.mask = _PAGE_NO_CACHE,
.val = _PAGE_NO_CACHE,
- .set = "no cache",
- .clear = " ",
+ .set = "i",
+ .clear = " ",
}, {
.mask = _PAGE_SPECIAL,
.val = _PAGE_SPECIAL,
- .set = "special",
+ .set = "s",
+ .clear = " ",
}
};
--
2.25.0
^ permalink raw reply related
* [PATCH v4 09/45] powerpc/ptdump: Add _PAGE_COHERENT flag
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
For platforms using shared.c (4xx, Book3e, Book3s/32),
also handle the _PAGE_COHERENT flag with corresponds to the
M bit of the WIMG flags.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/shared.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index dab5d8028a9b..634b83aa3487 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -40,6 +40,11 @@ static const struct flag_info flag_array[] = {
.val = _PAGE_NO_CACHE,
.set = "i",
.clear = " ",
+ }, {
+ .mask = _PAGE_COHERENT,
+ .val = _PAGE_COHERENT,
+ .set = "m",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val = _PAGE_GUARDED,
--
2.25.0
^ permalink raw reply related
* [PATCH v4 08/45] powerpc/ptdump: Reorder flags
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
Reorder flags in a more logical way:
- Page size (huge) first
- User
- RWX
- Present
- WIMG
- Special
- Dirty and Accessed
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/8xx.c | 30 +++++++++++++++---------------
arch/powerpc/mm/ptdump/shared.c | 30 +++++++++++++++---------------
2 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/8xx.c b/arch/powerpc/mm/ptdump/8xx.c
index ca9ce94672f5..a3169677dced 100644
--- a/arch/powerpc/mm/ptdump/8xx.c
+++ b/arch/powerpc/mm/ptdump/8xx.c
@@ -11,11 +11,6 @@
static const struct flag_info flag_array[] = {
{
- .mask = _PAGE_SH,
- .val = _PAGE_SH,
- .set = "sh",
- .clear = " ",
- }, {
.mask = _PAGE_RO | _PAGE_NA,
.val = 0,
.set = "rw",
@@ -37,11 +32,26 @@ static const struct flag_info flag_array[] = {
.val = _PAGE_PRESENT,
.set = "p",
.clear = " ",
+ }, {
+ .mask = _PAGE_NO_CACHE,
+ .val = _PAGE_NO_CACHE,
+ .set = "i",
+ .clear = " ",
}, {
.mask = _PAGE_GUARDED,
.val = _PAGE_GUARDED,
.set = "g",
.clear = " ",
+ }, {
+ .mask = _PAGE_SH,
+ .val = _PAGE_SH,
+ .set = "sh",
+ .clear = " ",
+ }, {
+ .mask = _PAGE_SPECIAL,
+ .val = _PAGE_SPECIAL,
+ .set = "s",
+ .clear = " ",
}, {
.mask = _PAGE_DIRTY,
.val = _PAGE_DIRTY,
@@ -52,16 +62,6 @@ static const struct flag_info flag_array[] = {
.val = _PAGE_ACCESSED,
.set = "a",
.clear = " ",
- }, {
- .mask = _PAGE_NO_CACHE,
- .val = _PAGE_NO_CACHE,
- .set = "i",
- .clear = " ",
- }, {
- .mask = _PAGE_SPECIAL,
- .val = _PAGE_SPECIAL,
- .set = "s",
- .clear = " ",
}
};
diff --git a/arch/powerpc/mm/ptdump/shared.c b/arch/powerpc/mm/ptdump/shared.c
index 44a8a64a664f..dab5d8028a9b 100644
--- a/arch/powerpc/mm/ptdump/shared.c
+++ b/arch/powerpc/mm/ptdump/shared.c
@@ -30,21 +30,6 @@ static const struct flag_info flag_array[] = {
.val = _PAGE_PRESENT,
.set = "p",
.clear = " ",
- }, {
- .mask = _PAGE_GUARDED,
- .val = _PAGE_GUARDED,
- .set = "g",
- .clear = " ",
- }, {
- .mask = _PAGE_DIRTY,
- .val = _PAGE_DIRTY,
- .set = "d",
- .clear = " ",
- }, {
- .mask = _PAGE_ACCESSED,
- .val = _PAGE_ACCESSED,
- .set = "a",
- .clear = " ",
}, {
.mask = _PAGE_WRITETHRU,
.val = _PAGE_WRITETHRU,
@@ -55,11 +40,26 @@ static const struct flag_info flag_array[] = {
.val = _PAGE_NO_CACHE,
.set = "i",
.clear = " ",
+ }, {
+ .mask = _PAGE_GUARDED,
+ .val = _PAGE_GUARDED,
+ .set = "g",
+ .clear = " ",
}, {
.mask = _PAGE_SPECIAL,
.val = _PAGE_SPECIAL,
.set = "s",
.clear = " ",
+ }, {
+ .mask = _PAGE_DIRTY,
+ .val = _PAGE_DIRTY,
+ .set = "d",
+ .clear = " ",
+ }, {
+ .mask = _PAGE_ACCESSED,
+ .val = _PAGE_ACCESSED,
+ .set = "a",
+ .clear = " ",
}
};
--
2.25.0
^ permalink raw reply related
* [PATCH v4 10/45] powerpc/ptdump: Display size of BATs
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
Display the size of areas mapped with BATs.
For that, the size display for pages is refactorised.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2: Add missing include of linux/seq_file.h (Thanks to kbuild test robot)
---
arch/powerpc/mm/ptdump/bats.c | 4 ++++
arch/powerpc/mm/ptdump/ptdump.c | 23 ++++++++++++++---------
arch/powerpc/mm/ptdump/ptdump.h | 3 +++
3 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c
index d3a5d6b318d1..d6c660f63d71 100644
--- a/arch/powerpc/mm/ptdump/bats.c
+++ b/arch/powerpc/mm/ptdump/bats.c
@@ -10,6 +10,8 @@
#include <asm/pgtable.h>
#include <asm/cpu_has_feature.h>
+#include "ptdump.h"
+
static char *pp_601(int k, int pp)
{
if (pp == 0)
@@ -42,6 +44,7 @@ static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper)
#else
seq_printf(m, "0x%08x ", pbn);
#endif
+ pt_dump_size(m, size);
seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp));
@@ -88,6 +91,7 @@ static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool
#else
seq_printf(m, "0x%08x ", brpn);
#endif
+ pt_dump_size(m, size);
if (k == 1)
seq_puts(m, "User ");
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index d92bb8ea229c..1f97668853e3 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -112,6 +112,19 @@ static struct addr_marker address_markers[] = {
seq_putc(m, c); \
})
+void pt_dump_size(struct seq_file *m, unsigned long size)
+{
+ static const char units[] = "KMGTPE";
+ const char *unit = units;
+
+ /* Work out what appropriate unit to use */
+ while (!(size & 1023) && unit[1]) {
+ size >>= 10;
+ unit++;
+ }
+ pt_dump_seq_printf(m, "%9lu%c ", size, *unit);
+}
+
static void dump_flag_info(struct pg_state *st, const struct flag_info
*flag, u64 pte, int num)
{
@@ -146,8 +159,6 @@ static void dump_flag_info(struct pg_state *st, const struct flag_info
static void dump_addr(struct pg_state *st, unsigned long addr)
{
- static const char units[] = "KMGTPE";
- const char *unit = units;
unsigned long delta;
#ifdef CONFIG_PPC64
@@ -164,13 +175,7 @@ static void dump_addr(struct pg_state *st, unsigned long addr)
pt_dump_seq_printf(st->seq, " " REG " ", st->start_pa);
delta = (addr - st->start_address) >> 10;
}
- /* Work out what appropriate unit to use */
- while (!(delta & 1023) && unit[1]) {
- delta >>= 10;
- unit++;
- }
- pt_dump_seq_printf(st->seq, "%9lu%c", delta, *unit);
-
+ pt_dump_size(st->seq, delta);
}
static void note_prot_wx(struct pg_state *st, unsigned long addr)
diff --git a/arch/powerpc/mm/ptdump/ptdump.h b/arch/powerpc/mm/ptdump/ptdump.h
index 5d513636de73..154efae96ae0 100644
--- a/arch/powerpc/mm/ptdump/ptdump.h
+++ b/arch/powerpc/mm/ptdump/ptdump.h
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/types.h>
+#include <linux/seq_file.h>
struct flag_info {
u64 mask;
@@ -17,3 +18,5 @@ struct pgtable_level {
};
extern struct pgtable_level pg_level[5];
+
+void pt_dump_size(struct seq_file *m, unsigned long delta);
--
2.25.0
^ permalink raw reply related
* [PATCH v4 11/45] powerpc/ptdump: Standardise display of BAT flags
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
Display BAT flags the same way as page flags: rwx and wimg
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/mm/ptdump/bats.c | 37 ++++++++++++++---------------------
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c
index d6c660f63d71..cebb58c7e289 100644
--- a/arch/powerpc/mm/ptdump/bats.c
+++ b/arch/powerpc/mm/ptdump/bats.c
@@ -15,12 +15,12 @@
static char *pp_601(int k, int pp)
{
if (pp == 0)
- return k ? "NA" : "RWX";
+ return k ? " " : "rwx";
if (pp == 1)
- return k ? "ROX" : "RWX";
+ return k ? "r x" : "rwx";
if (pp == 2)
- return k ? "RWX" : "RWX";
- return k ? "ROX" : "ROX";
+ return "rwx";
+ return "r x";
}
static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper)
@@ -48,12 +48,9 @@ static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper)
seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp));
- if (lower & _PAGE_WRITETHRU)
- seq_puts(m, "write through ");
- if (lower & _PAGE_NO_CACHE)
- seq_puts(m, "no cache ");
- if (lower & _PAGE_COHERENT)
- seq_puts(m, "coherent ");
+ seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " ");
+ seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " ");
+ seq_puts(m, lower & _PAGE_COHERENT ? "m " : " ");
seq_puts(m, "\n");
}
@@ -101,20 +98,16 @@ static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool
seq_puts(m, "Kernel/User ");
if (lower & BPP_RX)
- seq_puts(m, is_d ? "RO " : "EXEC ");
+ seq_puts(m, is_d ? "r " : " x ");
else if (lower & BPP_RW)
- seq_puts(m, is_d ? "RW " : "EXEC ");
+ seq_puts(m, is_d ? "rw " : " x ");
else
- seq_puts(m, is_d ? "NA " : "NX ");
-
- if (lower & _PAGE_WRITETHRU)
- seq_puts(m, "write through ");
- if (lower & _PAGE_NO_CACHE)
- seq_puts(m, "no cache ");
- if (lower & _PAGE_COHERENT)
- seq_puts(m, "coherent ");
- if (lower & _PAGE_GUARDED)
- seq_puts(m, "guarded ");
+ seq_puts(m, is_d ? " " : " ");
+
+ seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " ");
+ seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " ");
+ seq_puts(m, lower & _PAGE_COHERENT ? "m " : " ");
+ seq_puts(m, lower & _PAGE_GUARDED ? "g " : " ");
seq_puts(m, "\n");
}
--
2.25.0
^ permalink raw reply related
* [PATCH v4 13/45] powerpc/ptdump: Handle hugepd at PGD level
From: Christophe Leroy @ 2020-05-19 5:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1589866984.git.christophe.leroy@csgroup.eu>
The 8xx is about to map kernel linear space and IMMR using huge
pages.
In order to display those pages properly, ptdump needs to handle
hugepd tables at PGD level.
For the time being do it only at PGD level. Further patches may
add handling of hugepd tables at lower level for other platforms
when needed in the future.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v3: notepage() now takes page size instead of page shift
---
arch/powerpc/mm/ptdump/ptdump.c | 29 ++++++++++++++++++++++++++---
1 file changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/ptdump/ptdump.c b/arch/powerpc/mm/ptdump/ptdump.c
index 98d82dcf6f0b..5fc880e30175 100644
--- a/arch/powerpc/mm/ptdump/ptdump.c
+++ b/arch/powerpc/mm/ptdump/ptdump.c
@@ -23,6 +23,7 @@
#include <linux/const.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
+#include <asm/hugetlb.h>
#include <mm/mmu_decl.h>
@@ -269,6 +270,26 @@ static void walk_pte(struct pg_state *st, pmd_t *pmd, unsigned long start)
}
}
+static void walk_hugepd(struct pg_state *st, hugepd_t *phpd, unsigned long start,
+ int pdshift, int level)
+{
+#ifdef CONFIG_ARCH_HAS_HUGEPD
+ unsigned int i;
+ int shift = hugepd_shift(*phpd);
+ int ptrs_per_hpd = pdshift - shift > 0 ? 1 << (pdshift - shift) : 1;
+
+ if (start & ((1 << shift) - 1))
+ return;
+
+ for (i = 0; i < ptrs_per_hpd; i++) {
+ unsigned long addr = start + (i << shift);
+ pte_t *pte = hugepte_offset(*phpd, addr, pdshift);
+
+ note_page(st, addr, level + 1, pte_val(*pte), 1 << shift);
+ }
+#endif
+}
+
static void walk_pmd(struct pg_state *st, pud_t *pud, unsigned long start)
{
pmd_t *pmd = pmd_offset(pud, 0);
@@ -312,11 +333,13 @@ static void walk_pagetables(struct pg_state *st)
* the hash pagetable.
*/
for (i = pgd_index(addr); i < PTRS_PER_PGD; i++, pgd++, addr += PGDIR_SIZE) {
- if (!pgd_none(*pgd) && !pgd_is_leaf(*pgd))
+ if (pgd_none(*pgd) || pgd_is_leaf(*pgd))
+ note_page(st, addr, 1, pgd_val(*pgd), PGDIR_SIZE);
+ else if (is_hugepd(__hugepd(pgd_val(*pgd))))
+ walk_hugepd(st, (hugepd_t *)pgd, addr, PGDIR_SHIFT, 1);
+ else
/* pgd exists */
walk_pud(st, pgd, addr);
- else
- note_page(st, addr, 1, pgd_val(*pgd), PGDIR_SIZE);
}
}
--
2.25.0
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