* Re: [PATCH] powerpc/powernv: Add a print indicating when an IODA PE is released
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: Oliver O'Halloran, linuxppc-dev
In-Reply-To: <20200408112213.5549-1-oohall@gmail.com>
On Wed, 8 Apr 2020 21:22:13 +1000, Oliver O'Halloran wrote:
> Quite useful to know in some cases.
Applied to powerpc/next.
[1/1] powerpc/powernv: Add a print indicating when an IODA PE is released
https://git.kernel.org/powerpc/c/e5500ab657c51bec5af8dcf564a096de48e7a132
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/powernv/pci: Add an explaination for PNV_IODA_PE_BUS_ALL
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: Oliver O'Halloran, linuxppc-dev
In-Reply-To: <20200414233502.758-1-oohall@gmail.com>
On Wed, 15 Apr 2020 09:35:02 +1000, Oliver O'Halloran wrote:
> It's pretty obsecure and confused me for a long time so I figured it's
> worth documenting properly.
Applied to powerpc/next.
[1/1] powerpc/powernv/pci: Add an explaination for PNV_IODA_PE_BUS_ALL
https://git.kernel.org/powerpc/c/9d0879a2dbc3d0c15f8c71490079c1c38f9f3800
cheers
^ permalink raw reply
* Re: [PATCH 1/7] powerpc/powernv/npu: Clean up compound table group initialisation
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: Oliver O'Halloran, linuxppc-dev; +Cc: aik
In-Reply-To: <20200406030745.24595-2-oohall@gmail.com>
On Mon, 6 Apr 2020 13:07:39 +1000, Oliver O'Halloran wrote:
> Re-work the control flow a bit so what's going on is a little clearer.
> This also ensures the table_group is only initialised once in the P9
> case. This shouldn't be a functional change since all the GPU PCI
> devices should have the same table_group configuration, but it does
> look strange.
Applied to powerpc/next.
[1/7] powerpc/powernv/npu: Clean up compound table group initialisation
https://git.kernel.org/powerpc/c/6984856865b55c9c1ee0814c30296119cd8ba511
[2/7] powerpc/powernv/iov: Don't add VFs to iommu group during PE config
https://git.kernel.org/powerpc/c/6cff91b2b97b1b40a52971c9b1e99980dd49fd54
[3/7] powerpc/powernv/pci: Register iommu group at PE DMA setup
https://git.kernel.org/powerpc/c/9b9408c55935ecc3b1c27b3eeb5a507394113cbb
[4/7] powerpc/powernv/pci: Add device to iommu group during dma_dev_setup()
https://git.kernel.org/powerpc/c/84d8cc076723058cc294f4360db6ff7758c25b74
[5/7] powerpc/powernv/pci: Delete old iommu recursive iommu setup
https://git.kernel.org/powerpc/c/f39b8b10fcc5d4617d2be5f2910e017a55444b43
[6/7] powerpc/powernv/pci: Move tce size parsing to pci-ioda-tce.c
https://git.kernel.org/powerpc/c/96e2006a9dbc02cb1c103521405d457438a2e260
[7/7] powerpc/powernv/npu: Move IOMMU group setup into npu-dma.c
https://git.kernel.org/powerpc/c/03b7bf341c18ff19129cc2825b62bb0e212463f1
cheers
^ permalink raw reply
* Re: [PATCH] hw_breakpoint: Fix build warnings with clang
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: Ravi Bangoria, mpe
Cc: christophe.leroy, apopple, mikey, linux-kernel, npiggin, paulus,
naveen.n.rao, linuxppc-dev
In-Reply-To: <20200602041208.128913-1-ravi.bangoria@linux.ibm.com>
On Tue, 2 Jun 2020 09:42:08 +0530, Ravi Bangoria wrote:
> kbuild test robot reported few build warnings with hw_breakpoint code
> when compiled with clang[1]. Fix those.
>
> [1]: https://lore.kernel.org/linuxppc-dev/202005192233.oi9CjRtA%25lkp@intel.com/
Applied to powerpc/next.
[1/1] hw-breakpoints: Fix build warnings with clang
https://git.kernel.org/powerpc/c/ef3534a94fdbdeab4c89d18d0164be2ad5d6dbb7
cheers
^ permalink raw reply
* Re: [PATCH v2] powerpc/pseries: Make vio and ibmebus initcalls pseries specific
From: Michael Ellerman @ 2020-06-09 5:29 UTC (permalink / raw)
To: Oliver O'Halloran, linuxppc-dev; +Cc: Tyrel Datwyler
In-Reply-To: <20200421081539.7485-1-oohall@gmail.com>
On Tue, 21 Apr 2020 18:15:39 +1000, Oliver O'Halloran wrote:
> The vio and ibmebus buses are used for pseries specific paravirtualised
> devices and currently they're initialised by the generic initcall types.
> This is mostly fine, but it can result in some nuisance errors in dmesg
> when booting on PowerNV on some OSes, e.g.
>
> [ 2.984439] synth uevent: /devices/vio: failed to send uevent
> [ 2.984442] vio vio: uevent: failed to send synthetic uevent
> [ 17.968551] synth uevent: /devices/vio: failed to send uevent
> [ 17.968554] vio vio: uevent: failed to send synthetic uevent
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/pseries: Make vio and ibmebus initcalls pseries specific
https://git.kernel.org/powerpc/c/4336b9337824a60a0b10013c622caeee99460db5
cheers
^ permalink raw reply
* Re: [PATCH v8 22.5/30] powerpc/optprobes: Add register argument to patch_imm64_load_insns()
From: Michael Ellerman @ 2020-06-09 5:51 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: christophe.leroy, jniethe5
In-Reply-To: <20200516115449.4168796-1-mpe@ellerman.id.au>
On Sat, 2020-05-16 at 11:54:49 UTC, Michael Ellerman wrote:
> From: Jordan Niethe <jniethe5@gmail.com>
>
> Currently patch_imm32_load_insns() is used to load an instruction to
> r4 to be emulated by emulate_step(). For prefixed instructions we
> would like to be able to load a 64bit immediate to r4. To prepare for
> this make patch_imm64_load_insns() take an argument that decides which
> register to load an immediate to - rather than hardcoding r3.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Applied to powerpc next.
https://git.kernel.org/powerpc/c/7a8818e0df5c6b53c89c7c928498668a2bbb3de0
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/kprobes: Use probe_address() to read instructions
From: Christoph Hellwig @ 2020-06-09 5:53 UTC (permalink / raw)
To: Michael Ellerman
Cc: Christophe Leroy, linux-kernel, Paul Mackerras, naveen.n.rao,
linuxppc-dev
In-Reply-To: <159168034650.1381411.840854749818290996.b4-ty@ellerman.id.au>
On Tue, Jun 09, 2020 at 03:28:38PM +1000, Michael Ellerman wrote:
> On Mon, 24 Feb 2020 18:02:10 +0000 (UTC), Christophe Leroy wrote:
> > In order to avoid Oopses, use probe_address() to read the
> > instruction at the address where the trap happened.
>
> Applied to powerpc/next.
>
> [1/1] powerpc/kprobes: Use probe_address() to read instructions
> https://git.kernel.org/powerpc/c/9ed5df69b79a22b40b20bc2132ba2495708b19c4
probe_addresss has been renamed to get_kernel_nofault in the -mm
queue that Andrew sent off to Linus last night.
^ permalink raw reply
* Re: [PATCH 0/6] assorted kuap fixes (try again)
From: Michael Ellerman @ 2020-06-09 5:54 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
In-Reply-To: <20200429065654.1677541-1-npiggin@gmail.com>
On Wed, 29 Apr 2020 16:56:48 +1000, Nicholas Piggin wrote:
> Well the last series was a disaster, I'll try again sending the
> patches with proper subject and changelogs written.
>
> Nicholas Piggin (6):
> powerpc/64/kuap: move kuap checks out of MSR[RI]=0 regions of exit
> code
> powerpc/64s/kuap: kuap_restore missing isync
> powerpc/64/kuap: interrupt exit conditionally restore AMR
> powerpc/64s/kuap: restore AMR in system reset exception
> powerpc/64s/kuap: restore AMR in fast_interrupt_return
> powerpc/64s/kuap: conditionally restore AMR in kuap_restore_amr asm
>
> [...]
Patches 2, 3 and 6 applied to powerpc/next.
[2/6] powerpc/64s/kuap: Add missing isync to KUAP restore paths
https://git.kernel.org/powerpc/c/cb2b53cbffe3c388cd676b63f34e54ceb2643ae2
[3/6] powerpc/64/kuap: Conditionally restore AMR in interrupt exit
https://git.kernel.org/powerpc/c/579940bb451c2dd33396d2d56ce6ef5d92154b3b
[6/6] powerpc/64s/kuap: Conditionally restore AMR in kuap_restore_amr asm
https://git.kernel.org/powerpc/c/d4539074b0e9c5fa6508e8c33aaf51abc8ff6e91
cheers
^ permalink raw reply
* Re: [PATCH v3 7/9] powerpc/ps3: Add check for otheros image size
From: Michael Ellerman @ 2020-06-09 5:56 UTC (permalink / raw)
To: Geoff Levand
Cc: Geert Uytterhoeven, linuxppc-dev, Markus Elfring,
Emmanuel Nicolet
In-Reply-To: <897c2a59-378e-7c9b-3976-d0a0def90913@infradead.org>
On Sat, 2020-05-16 at 16:20:46 UTC, Geoff Levand wrote:
> The ps3's otheros flash loader has a size limit of 16 MiB for the
> uncompressed image. If that limit will be reached output the
> flash image file as 'otheros-too-big.bld'.
>
> Signed-off-by: Geoff Levand <geoff@infradead.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/aa3bc365ee73765af5059678bf55b0f3e4a3e6c4
cheers
^ permalink raw reply
* Re: [PATCH v3 2/5] powerpc: module_[32|64].c: replace swap function with built-in one
From: Michael Ellerman @ 2020-06-09 5:58 UTC (permalink / raw)
To: Andrey Abramov, vgupta, benh, paulus, tglx, mingo, bp, hpa, x86,
mark, jlbec, richard, dedekind1, adrian.hunter, gregkh,
naveen.n.rao, jpoimboe, Dave Chinner, darrick.wong,
ard.biesheuvel, George Spelvin, linux-snps-arc,
Linux Kernel Mailing List, linuxppc-dev, ocfs2-devel, linux-mtd,
sfr
Cc: malat, yamada.masahiro, npiggin
In-Reply-To: <994931554238042@iva8-b333b7f98ab0.qloud-c.yandex.net>
On Tue, 2019-04-02 at 20:47:22 UTC, Andrey Abramov wrote:
> Replace relaswap with built-in one, because relaswap
> does a simple byte to byte swap.
>
> Since Spectre mitigations have made indirect function calls more
> expensive, and the default simple byte copies swap is implemented
> without them, an "optimized" custom swap function is now
> a waste of time as well as code.
>
> Signed-off-by: Andrey Abramov <st5pub@yandex.ru>
> Reviewed by: George Spelvin <lkml@sdf.org>
> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc)
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/bac7ca7b985b72873bd4ac2553b13b5af5b1f08a
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/powernv: Fix a warning message
From: Michael Ellerman @ 2020-06-09 5:59 UTC (permalink / raw)
To: Christophe JAILLET, benh, paulus, npiggin, tglx, maddy, cclaudio,
zhangshaokun, atrajeev, akshay.adiga, ego
Cc: Christophe JAILLET, kernel-janitors, linuxppc-dev, linux-kernel
In-Reply-To: <20200502115949.139000-1-christophe.jaillet@wanadoo.fr>
On Sat, 2020-05-02 at 11:59:49 UTC, Christophe JAILLET wrote:
> Fix a cut'n'paste error in a warning message. This should be
> 'cpu-idle-state-residency-ns' to match the property searched in the
> previous 'of_property_read_u32_array()'
>
> Fixes: 9c7b185ab2fe ("powernv/cpuidle: Parse dt idle properties into global structure")
> Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/2f62870ca5bc9d305f3c212192320c29e9dbdc54
cheers
^ permalink raw reply
* Re: [PATCH] selftests: powerpc: Fix online CPU selection
From: Sandipan Das @ 2020-06-09 6:12 UTC (permalink / raw)
To: mpe; +Cc: shiganta, linuxppc-dev, nasastry, srikar, kamalesh
In-Reply-To: <20200608144212.985144-1-sandipan@linux.ibm.com>
On 08/06/20 8:12 pm, Sandipan Das wrote:
> The size of the cpu set must be large enough for systems
> with a very large number of CPUs. Otherwise, tests which
> try to determine the first online CPU by calling
> sched_getaffinity() will fail. This makes sure that the
> size of the allocated cpu set is dependent on the number
> of CPUs as reported by get_nprocs().
>
> Fixes: 3752e453f6ba ("selftests/powerpc: Add tests of PMU EBBs")
> Reported-by: Shirisha Ganta <shiganta@in.ibm.com>
> Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
> ---
> tools/testing/selftests/powerpc/utils.c | 33 ++++++++++++++++---------
> 1 file changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/tools/testing/selftests/powerpc/utils.c b/tools/testing/selftests/powerpc/utils.c
> index 933678f1ed0a..bb8e402752c0 100644
> --- a/tools/testing/selftests/powerpc/utils.c
> +++ b/tools/testing/selftests/powerpc/utils.c
> @@ -16,6 +16,7 @@
> @@ -88,28 +89,36 @@ void *get_auxv_entry(int type)
> [...]
> int pick_online_cpu(void)
> {
> - cpu_set_t mask;
> - int cpu;
> + int ncpus, cpu = -1;
> + cpu_set_t *mask;
> + size_t size;
>
> - CPU_ZERO(&mask);
> + ncpus = get_nprocs();
> + size = CPU_ALLOC_SIZE(ncpus);
> + mask = CPU_ALLOC(ncpus);
>
> - if (sched_getaffinity(0, sizeof(mask), &mask)) {
> + CPU_ZERO_S(size, mask);
> +
> + if (sched_getaffinity(0, size, mask)) {
> perror("sched_getaffinity");
> - return -1;
> + goto done;
> }
>
> /* We prefer a primary thread, but skip 0 */
> - for (cpu = 8; cpu < CPU_SETSIZE; cpu += 8)
> - if (CPU_ISSET(cpu, &mask))
> - return cpu;
> + for (cpu = 8; cpu < ncpus; cpu += 8)
> + if (CPU_ISSET_S(cpu, size, mask))
> + goto done;
>
> /* Search for anything, but in reverse */
> - for (cpu = CPU_SETSIZE - 1; cpu >= 0; cpu--)
> - if (CPU_ISSET(cpu, &mask))
> - return cpu;
> + for (cpu = ncpus - 1; cpu >= 0; cpu--)
> + if (CPU_ISSET_S(cpu, size, mask))
> + goto done;
>
> printf("No cpus in affinity mask?!\n");
> - return -1;
There's a bug here as cpu should have been set to -1.
Will send v2 with this fix.
> +
> +done:
> + CPU_FREE(mask);
> + return cpu;
> }
>
> bool is_ppc64le(void)
>
- Sandipan
^ permalink raw reply
* [PATCH 0/7] powerpc: branch cache flush changes
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
This series allows the link stack to be flushed with the speical
bcctr 2,0,0 flush instruction that also flushes the count cache if
the processor supports it.
Firmware does not support this at the moment, but I've tested it in
simulator with a patched firmware to advertise support.
Thanks,
Nick
Nicholas Piggin (7):
powerpc/security: re-name count cache flush to branch cache flush
powerpc/security: change link stack flush state to the flush type enum
powerpc/security: make display of branch cache flush more consistent
powerpc/security: split branch cache flush toggle from code patching
powerpc/64s: Move branch cache flushing bcctr variant to ppc-ops.h
powerpc/security: Allow for processors that flush the link stack using
the special bcctr
powerpc/64s: advertise hardware link stack flush
arch/powerpc/include/asm/asm-prototypes.h | 4 +-
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/ppc-opcode.h | 2 +
arch/powerpc/include/asm/security_features.h | 2 +
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kernel/entry_64.S | 13 +-
arch/powerpc/kernel/security.c | 139 +++++++++++--------
arch/powerpc/kvm/powerpc.c | 9 +-
arch/powerpc/platforms/powernv/setup.c | 3 +
arch/powerpc/platforms/pseries/setup.c | 3 +
tools/arch/powerpc/include/uapi/asm/kvm.h | 1 +
11 files changed, 106 insertions(+), 72 deletions(-)
--
2.23.0
^ permalink raw reply
* [PATCH 1/7] powerpc/security: re-name count cache flush to branch cache flush
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
The count cache flush mostly refers to both count cache and link stack
flushing. As a first step to untangling these a bit, re-name the bits
that apply to both.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/asm-prototypes.h | 4 +--
arch/powerpc/kernel/entry_64.S | 7 ++---
arch/powerpc/kernel/security.c | 36 +++++++++++------------
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h
index 7d81e86a1e5d..fa9057360e88 100644
--- a/arch/powerpc/include/asm/asm-prototypes.h
+++ b/arch/powerpc/include/asm/asm-prototypes.h
@@ -144,13 +144,13 @@ void _kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
/* Patch sites */
-extern s32 patch__call_flush_count_cache;
+extern s32 patch__call_flush_branch_caches;
extern s32 patch__flush_count_cache_return;
extern s32 patch__flush_link_stack_return;
extern s32 patch__call_kvm_flush_link_stack;
extern s32 patch__memset_nocache, patch__memcpy_nocache;
-extern long flush_count_cache;
+extern long flush_branch_caches;
extern long kvm_flush_link_stack;
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 9d49338e0c85..2ba25b3b701e 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -259,8 +259,7 @@ _ASM_NOKPROBE_SYMBOL(save_nvgprs);
#define FLUSH_COUNT_CACHE \
1: nop; \
- patch_site 1b, patch__call_flush_count_cache
-
+ patch_site 1b, patch__call_flush_branch_caches
#define BCCTR_FLUSH .long 0x4c400420
@@ -271,8 +270,8 @@ _ASM_NOKPROBE_SYMBOL(save_nvgprs);
.endm
.balign 32
-.global flush_count_cache
-flush_count_cache:
+.global flush_branch_caches
+flush_branch_caches:
/* Save LR into r9 */
mflr r9
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index d86701ce116b..df2a3eff950b 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -21,12 +21,12 @@
u64 powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
-enum count_cache_flush_type {
- COUNT_CACHE_FLUSH_NONE = 0x1,
- COUNT_CACHE_FLUSH_SW = 0x2,
- COUNT_CACHE_FLUSH_HW = 0x4,
+enum branch_cache_flush_type {
+ BRANCH_CACHE_FLUSH_NONE = 0x1,
+ BRANCH_CACHE_FLUSH_SW = 0x2,
+ BRANCH_CACHE_FLUSH_HW = 0x4,
};
-static enum count_cache_flush_type count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
+static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
static bool link_stack_flush_enabled;
bool barrier_nospec_enabled;
@@ -222,10 +222,10 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (link_stack_flush_enabled)
seq_buf_printf(&s, ", Software link stack flush");
- } else if (count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
+ } else if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
seq_buf_printf(&s, "Mitigation: Software count cache flush");
- if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW)
seq_buf_printf(&s, " (hardware accelerated)");
if (link_stack_flush_enabled)
@@ -429,18 +429,18 @@ device_initcall(stf_barrier_debugfs_init);
static void no_count_cache_flush(void)
{
- count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
pr_info("count-cache-flush: software flush disabled.\n");
}
-static void toggle_count_cache_flush(bool enable)
+static void toggle_branch_cache_flush(bool enable)
{
if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE) &&
!security_ftr_enabled(SEC_FTR_FLUSH_LINK_STACK))
enable = false;
if (!enable) {
- patch_instruction_site(&patch__call_flush_count_cache,
+ patch_instruction_site(&patch__call_flush_branch_caches,
ppc_inst(PPC_INST_NOP));
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
patch_instruction_site(&patch__call_kvm_flush_link_stack,
@@ -452,9 +452,9 @@ static void toggle_count_cache_flush(bool enable)
return;
}
- // This enables the branch from _switch to flush_count_cache
- patch_branch_site(&patch__call_flush_count_cache,
- (u64)&flush_count_cache, BRANCH_SET_LINK);
+ // This enables the branch from _switch to flush_branch_caches
+ patch_branch_site(&patch__call_flush_branch_caches,
+ (u64)&flush_branch_caches, BRANCH_SET_LINK);
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
// This enables the branch from guest_exit_cont to kvm_flush_link_stack
@@ -474,13 +474,13 @@ static void toggle_count_cache_flush(bool enable)
}
if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
- count_cache_flush_type = COUNT_CACHE_FLUSH_SW;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_SW;
pr_info("count-cache-flush: full software flush sequence enabled.\n");
return;
}
patch_instruction_site(&patch__flush_count_cache_return, ppc_inst(PPC_INST_BLR));
- count_cache_flush_type = COUNT_CACHE_FLUSH_HW;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_HW;
pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
}
@@ -505,7 +505,7 @@ void setup_count_cache_flush(void)
security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE))
security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
- toggle_count_cache_flush(enable);
+ toggle_branch_cache_flush(enable);
}
#ifdef CONFIG_DEBUG_FS
@@ -520,14 +520,14 @@ static int count_cache_flush_set(void *data, u64 val)
else
return -EINVAL;
- toggle_count_cache_flush(enable);
+ toggle_branch_cache_flush(enable);
return 0;
}
static int count_cache_flush_get(void *data, u64 *val)
{
- if (count_cache_flush_type == COUNT_CACHE_FLUSH_NONE)
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE)
*val = 0;
else
*val = 1;
--
2.23.0
^ permalink raw reply related
* [PATCH 2/7] powerpc/security: change link stack flush state to the flush type enum
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
Prepare to allow for hardware link stack flushing by using the
none/sw/hw type, same as the count cache state.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/security.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index df2a3eff950b..28f4cb062f69 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -27,7 +27,7 @@ enum branch_cache_flush_type {
BRANCH_CACHE_FLUSH_HW = 0x4,
};
static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
-static bool link_stack_flush_enabled;
+static enum branch_cache_flush_type link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
bool barrier_nospec_enabled;
static bool no_nospec;
@@ -219,7 +219,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (ccd)
seq_buf_printf(&s, "Indirect branch cache disabled");
- if (link_stack_flush_enabled)
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
seq_buf_printf(&s, ", Software link stack flush");
} else if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
@@ -228,7 +228,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW)
seq_buf_printf(&s, " (hardware accelerated)");
- if (link_stack_flush_enabled)
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
seq_buf_printf(&s, ", Software link stack flush");
} else if (btb_flush_enabled) {
@@ -447,7 +447,7 @@ static void toggle_branch_cache_flush(bool enable)
ppc_inst(PPC_INST_NOP));
#endif
pr_info("link-stack-flush: software flush disabled.\n");
- link_stack_flush_enabled = false;
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
no_count_cache_flush();
return;
}
@@ -463,7 +463,7 @@ static void toggle_branch_cache_flush(bool enable)
#endif
pr_info("link-stack-flush: software flush enabled.\n");
- link_stack_flush_enabled = true;
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
// If we just need to flush the link stack, patch an early return
if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
--
2.23.0
^ permalink raw reply related
* [PATCH 3/7] powerpc/security: make display of branch cache flush more consistent
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
Make the count-cache and link-stack messages look the same
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/security.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 28f4cb062f69..659ef6a92bb9 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -430,7 +430,7 @@ device_initcall(stf_barrier_debugfs_init);
static void no_count_cache_flush(void)
{
count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
- pr_info("count-cache-flush: software flush disabled.\n");
+ pr_info("count-cache-flush: flush disabled.\n");
}
static void toggle_branch_cache_flush(bool enable)
@@ -446,7 +446,7 @@ static void toggle_branch_cache_flush(bool enable)
patch_instruction_site(&patch__call_kvm_flush_link_stack,
ppc_inst(PPC_INST_NOP));
#endif
- pr_info("link-stack-flush: software flush disabled.\n");
+ pr_info("link-stack-flush: flush disabled.\n");
link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
no_count_cache_flush();
return;
@@ -475,13 +475,13 @@ static void toggle_branch_cache_flush(bool enable)
if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
count_cache_flush_type = BRANCH_CACHE_FLUSH_SW;
- pr_info("count-cache-flush: full software flush sequence enabled.\n");
+ pr_info("count-cache-flush: software flush enabled.\n");
return;
}
patch_instruction_site(&patch__flush_count_cache_return, ppc_inst(PPC_INST_BLR));
count_cache_flush_type = BRANCH_CACHE_FLUSH_HW;
- pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
+ pr_info("count-cache-flush: hardware flush enabled.\n");
}
void setup_count_cache_flush(void)
--
2.23.0
^ permalink raw reply related
* [PATCH 4/7] powerpc/security: split branch cache flush toggle from code patching
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
Branch cache flushing code patching has inter-dependencies on both the
link stack and the count cache flushing state.
To make the code clearer and to separate the link stack and count
cache handling, split the "toggle" (setting up variables and printing
enable/disable) from the code patching.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/security.c | 94 ++++++++++++++++++----------------
1 file changed, 51 insertions(+), 43 deletions(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 659ef6a92bb9..2a413af21124 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -427,61 +427,69 @@ static __init int stf_barrier_debugfs_init(void)
device_initcall(stf_barrier_debugfs_init);
#endif /* CONFIG_DEBUG_FS */
-static void no_count_cache_flush(void)
+static void update_branch_cache_flush(void)
{
- count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
- pr_info("count-cache-flush: flush disabled.\n");
-}
-
-static void toggle_branch_cache_flush(bool enable)
-{
- if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE) &&
- !security_ftr_enabled(SEC_FTR_FLUSH_LINK_STACK))
- enable = false;
-
- if (!enable) {
- patch_instruction_site(&patch__call_flush_branch_caches,
- ppc_inst(PPC_INST_NOP));
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
+ // This controls the branch from guest_exit_cont to kvm_flush_link_stack
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_NONE) {
patch_instruction_site(&patch__call_kvm_flush_link_stack,
ppc_inst(PPC_INST_NOP));
-#endif
- pr_info("link-stack-flush: flush disabled.\n");
- link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
- no_count_cache_flush();
- return;
+ } else {
+ patch_branch_site(&patch__call_kvm_flush_link_stack,
+ (u64)&kvm_flush_link_stack, BRANCH_SET_LINK);
}
-
- // This enables the branch from _switch to flush_branch_caches
- patch_branch_site(&patch__call_flush_branch_caches,
- (u64)&flush_branch_caches, BRANCH_SET_LINK);
-
-#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
- // This enables the branch from guest_exit_cont to kvm_flush_link_stack
- patch_branch_site(&patch__call_kvm_flush_link_stack,
- (u64)&kvm_flush_link_stack, BRANCH_SET_LINK);
#endif
- pr_info("link-stack-flush: software flush enabled.\n");
- link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
+ // This controls the branch from _switch to flush_branch_caches
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE &&
+ link_stack_flush_type == BRANCH_CACHE_FLUSH_NONE) {
+ patch_instruction_site(&patch__call_flush_branch_caches,
+ ppc_inst(PPC_INST_NOP));
+ } else {
+ patch_branch_site(&patch__call_flush_branch_caches,
+ (u64)&flush_branch_caches, BRANCH_SET_LINK);
+
+ // If we just need to flush the link stack, early return
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE) {
+ patch_instruction_site(&patch__flush_link_stack_return,
+ ppc_inst(PPC_INST_BLR));
+
+ // If we have flush instruction, early return
+ } else if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW) {
+ patch_instruction_site(&patch__flush_count_cache_return,
+ ppc_inst(PPC_INST_BLR));
+ }
+ }
+}
- // If we just need to flush the link stack, patch an early return
- if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
- patch_instruction_site(&patch__flush_link_stack_return,
- ppc_inst(PPC_INST_BLR));
- no_count_cache_flush();
- return;
+static void toggle_branch_cache_flush(bool enable)
+{
+ if (!enable || !security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
+ if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
+ pr_info("count-cache-flush: flush disabled.\n");
+ }
+ } else {
+ if (security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_HW;
+ pr_info("count-cache-flush: hardware flush enabled.\n");
+ } else {
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_SW;
+ pr_info("count-cache-flush: software flush enabled.\n");
+ }
}
- if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
- count_cache_flush_type = BRANCH_CACHE_FLUSH_SW;
- pr_info("count-cache-flush: software flush enabled.\n");
- return;
+ if (!enable || !security_ftr_enabled(SEC_FTR_FLUSH_LINK_STACK)) {
+ if (link_stack_flush_type != BRANCH_CACHE_FLUSH_NONE) {
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
+ pr_info("link-stack-flush: flush disabled.\n");
+ }
+ } else {
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
+ pr_info("link-stack-flush: software flush enabled.\n");
}
- patch_instruction_site(&patch__flush_count_cache_return, ppc_inst(PPC_INST_BLR));
- count_cache_flush_type = BRANCH_CACHE_FLUSH_HW;
- pr_info("count-cache-flush: hardware flush enabled.\n");
+ update_branch_cache_flush();
}
void setup_count_cache_flush(void)
--
2.23.0
^ permalink raw reply related
* [PATCH 5/7] powerpc/64s: Move branch cache flushing bcctr variant to ppc-ops.h
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/ppc-opcode.h | 2 ++
arch/powerpc/kernel/entry_64.S | 6 ++----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 2a39c716c343..79d511a38bbb 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -195,6 +195,7 @@
#define OP_LQ 56
/* sorted alphabetically */
+#define PPC_INST_BCCTR_FLUSH 0x4c400420
#define PPC_INST_BHRBE 0x7c00025c
#define PPC_INST_CLRBHRB 0x7c00035c
#define PPC_INST_COPY 0x7c20060c
@@ -432,6 +433,7 @@
#endif
/* Deal with instructions that older assemblers aren't aware of */
+#define PPC_BCCTR_FLUSH stringify_in_c(.long PPC_INST_BCCTR_FLUSH)
#define PPC_CP_ABORT stringify_in_c(.long PPC_INST_CP_ABORT)
#define PPC_COPY(a, b) stringify_in_c(.long PPC_INST_COPY | \
___PPC_RA(a) | ___PPC_RB(b))
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 2ba25b3b701e..a115aeb2983a 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -261,8 +261,6 @@ _ASM_NOKPROBE_SYMBOL(save_nvgprs);
1: nop; \
patch_site 1b, patch__call_flush_branch_caches
-#define BCCTR_FLUSH .long 0x4c400420
-
.macro nops number
.rept \number
nop
@@ -293,7 +291,7 @@ flush_branch_caches:
li r9,0x7fff
mtctr r9
- BCCTR_FLUSH
+ PPC_BCCTR_FLUSH
2: nop
patch_site 2b patch__flush_count_cache_return
@@ -302,7 +300,7 @@ flush_branch_caches:
.rept 278
.balign 32
- BCCTR_FLUSH
+ PPC_BCCTR_FLUSH
nops 7
.endr
--
2.23.0
^ permalink raw reply related
* [PATCH 6/7] powerpc/security: Allow for processors that flush the link stack using the special bcctr
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
If both count cache and link stack are to be flushed, and can be flushed
with the special bcctr, patch that in directly to the flush/branch nop
site.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/security_features.h | 2 ++
arch/powerpc/kernel/security.c | 27 ++++++++++++++------
2 files changed, 21 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/include/asm/security_features.h b/arch/powerpc/include/asm/security_features.h
index 7c05e95a5c44..fbb8fa32150f 100644
--- a/arch/powerpc/include/asm/security_features.h
+++ b/arch/powerpc/include/asm/security_features.h
@@ -63,6 +63,8 @@ static inline bool security_ftr_enabled(u64 feature)
// bcctr 2,0,0 triggers a hardware assisted count cache flush
#define SEC_FTR_BCCTR_FLUSH_ASSIST 0x0000000000000800ull
+// bcctr 2,0,0 triggers a hardware assisted link stack flush
+#define SEC_FTR_BCCTR_LINK_FLUSH_ASSIST 0x0000000000002000ull
// Features indicating need for Spectre/Meltdown mitigations
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index 2a413af21124..6ad5c753d47c 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -219,24 +219,25 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (ccd)
seq_buf_printf(&s, "Indirect branch cache disabled");
- if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
- seq_buf_printf(&s, ", Software link stack flush");
-
} else if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
seq_buf_printf(&s, "Mitigation: Software count cache flush");
if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW)
seq_buf_printf(&s, " (hardware accelerated)");
- if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
- seq_buf_printf(&s, ", Software link stack flush");
-
} else if (btb_flush_enabled) {
seq_buf_printf(&s, "Mitigation: Branch predictor state flush");
} else {
seq_buf_printf(&s, "Vulnerable");
}
+ if (bcs || ccd || count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
+ if (link_stack_flush_type != BRANCH_CACHE_FLUSH_NONE)
+ seq_buf_printf(&s, ", Software link stack flush");
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_HW)
+ seq_buf_printf(&s, " (hardware accelerated)");
+ }
+
seq_buf_printf(&s, "\n");
return s.len;
@@ -435,6 +436,7 @@ static void update_branch_cache_flush(void)
patch_instruction_site(&patch__call_kvm_flush_link_stack,
ppc_inst(PPC_INST_NOP));
} else {
+ // Could use HW flush, but that could also flush count cache
patch_branch_site(&patch__call_kvm_flush_link_stack,
(u64)&kvm_flush_link_stack, BRANCH_SET_LINK);
}
@@ -445,6 +447,10 @@ static void update_branch_cache_flush(void)
link_stack_flush_type == BRANCH_CACHE_FLUSH_NONE) {
patch_instruction_site(&patch__call_flush_branch_caches,
ppc_inst(PPC_INST_NOP));
+ } else if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW &&
+ link_stack_flush_type == BRANCH_CACHE_FLUSH_HW) {
+ patch_instruction_site(&patch__call_flush_branch_caches,
+ ppc_inst(PPC_INST_BCCTR_FLUSH));
} else {
patch_branch_site(&patch__call_flush_branch_caches,
(u64)&flush_branch_caches, BRANCH_SET_LINK);
@@ -485,8 +491,13 @@ static void toggle_branch_cache_flush(bool enable)
pr_info("link-stack-flush: flush disabled.\n");
}
} else {
- link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
- pr_info("link-stack-flush: software flush enabled.\n");
+ if (security_ftr_enabled(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST)) {
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_HW;
+ pr_info("link-stack-flush: hardware flush enabled.\n");
+ } else {
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
+ pr_info("link-stack-flush: software flush enabled.\n");
+ }
}
update_branch_cache_flush();
--
2.23.0
^ permalink raw reply related
* [PATCH 7/7] powerpc/64s: advertise hardware link stack flush
From: Nicholas Piggin @ 2020-06-09 6:16 UTC (permalink / raw)
Cc: linuxppc-dev, Nicholas Piggin
In-Reply-To: <20200609061631.844390-1-npiggin@gmail.com>
For testing only at the moment, firmware does not define these bits.
---
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/powerpc.c | 9 +++++++--
arch/powerpc/platforms/powernv/setup.c | 3 +++
arch/powerpc/platforms/pseries/setup.c | 3 +++
tools/arch/powerpc/include/uapi/asm/kvm.h | 1 +
6 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index e90c073e437e..a92a07c89b6f 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -373,6 +373,7 @@
#define H_CPU_CHAR_THREAD_RECONFIG_CTRL (1ull << 57) // IBM bit 6
#define H_CPU_CHAR_COUNT_CACHE_DISABLED (1ull << 56) // IBM bit 7
#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54) // IBM bit 9
+#define H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST (1ull << 53) // IBM bit 10
#define H_CPU_BEHAV_FAVOUR_SECURITY (1ull << 63) // IBM bit 0
#define H_CPU_BEHAV_L1D_FLUSH_PR (1ull << 62) // IBM bit 1
diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
index 264e266a85bf..dd229d5f46ee 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -464,6 +464,7 @@ struct kvm_ppc_cpu_char {
#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54)
+#define KVM_PPC_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST (1ull << 53)
#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 27ccff612903..fa981ee09dec 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -2221,7 +2221,8 @@ static int pseries_get_cpu_char(struct kvm_ppc_cpu_char *cp)
KVM_PPC_CPU_CHAR_BR_HINT_HONOURED |
KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF |
KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS |
- KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST;
+ KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST |
+ KVM_PPC_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST;
cp->behaviour_mask = KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY |
KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR |
KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR |
@@ -2287,13 +2288,17 @@ static int kvmppc_get_cpu_char(struct kvm_ppc_cpu_char *cp)
if (have_fw_feat(fw_features, "enabled",
"fw-count-cache-flush-bcctr2,0,0"))
cp->character |= KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST;
+ if (have_fw_feat(fw_features, "enabled",
+ "fw-link-stack-flush-bcctr2,0,0"))
+ cp->character |= KVM_PPC_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST;
cp->character_mask = KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31 |
KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED |
KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30 |
KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2 |
KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV |
KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS |
- KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST;
+ KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST |
+ KVM_PPC_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST;
if (have_fw_feat(fw_features, "enabled",
"speculation-policy-favor-security"))
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index 3bc188da82ba..1a06d3b4c0a9 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -78,6 +78,9 @@ static void init_fw_feat_flags(struct device_node *np)
if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
+ if (fw_feature_is("enabled", "fw-link-stack-flush-bcctr2,0,0", np))
+ security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST);
+
if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 64d18f4bf093..70c9264f23c5 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -517,6 +517,9 @@ static void init_cpu_char_feature_flags(struct h_cpu_char_result *result)
if (result->character & H_CPU_CHAR_BCCTR_FLUSH_ASSIST)
security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
+ if (result->character & H_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST)
+ security_ftr_set(SEC_FTR_BCCTR_LINK_FLUSH_ASSIST);
+
if (result->behaviour & H_CPU_BEHAV_FLUSH_COUNT_CACHE)
security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
diff --git a/tools/arch/powerpc/include/uapi/asm/kvm.h b/tools/arch/powerpc/include/uapi/asm/kvm.h
index 264e266a85bf..dd229d5f46ee 100644
--- a/tools/arch/powerpc/include/uapi/asm/kvm.h
+++ b/tools/arch/powerpc/include/uapi/asm/kvm.h
@@ -464,6 +464,7 @@ struct kvm_ppc_cpu_char {
#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF (1ULL << 57)
#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS (1ULL << 56)
#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST (1ull << 54)
+#define KVM_PPC_CPU_CHAR_BCCTR_LINK_FLUSH_ASSIST (1ull << 53)
#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY (1ULL << 63)
#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR (1ULL << 62)
--
2.23.0
^ permalink raw reply related
* Re: [PATCH] selftests: powerpc: Fix online CPU selection
From: Sandipan Das @ 2020-06-09 6:20 UTC (permalink / raw)
To: mpe; +Cc: shiganta, linuxppc-dev, nasastry, srikar, kamalesh
In-Reply-To: <20200608144212.985144-1-sandipan@linux.ibm.com>
On 08/06/20 8:12 pm, Sandipan Das wrote:
> The size of the cpu set must be large enough for systems
> with a very large number of CPUs. Otherwise, tests which
> try to determine the first online CPU by calling
> sched_getaffinity() will fail. This makes sure that the
> size of the allocated cpu set is dependent on the number
> of CPUs as reported by get_nprocs().
>
> Fixes: 3752e453f6ba ("selftests/powerpc: Add tests of PMU EBBs")
> Reported-by: Shirisha Ganta <shiganta@in.ibm.com>
> Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
> ---
> tools/testing/selftests/powerpc/utils.c | 33 ++++++++++++++++---------
> 1 file changed, 21 insertions(+), 12 deletions(-)
>
> diff --git a/tools/testing/selftests/powerpc/utils.c b/tools/testing/selftests/powerpc/utils.c
> index 933678f1ed0a..bb8e402752c0 100644
> --- a/tools/testing/selftests/powerpc/utils.c
> +++ b/tools/testing/selftests/powerpc/utils.c
> @@ -16,6 +16,7 @@
> [...]
>
> int pick_online_cpu(void)
> {
> - cpu_set_t mask;
> - int cpu;
> + int ncpus, cpu = -1;
> + cpu_set_t *mask;
> + size_t size;
>
> - CPU_ZERO(&mask);
> + ncpus = get_nprocs();
> + size = CPU_ALLOC_SIZE(ncpus);
> + mask = CPU_ALLOC(ncpus);
>
> - if (sched_getaffinity(0, sizeof(mask), &mask)) {
> + CPU_ZERO_S(size, mask);
> +
> + if (sched_getaffinity(0, size, mask)) {
> perror("sched_getaffinity");
> - return -1;
> + goto done;
> }
>
> /* We prefer a primary thread, but skip 0 */
> - for (cpu = 8; cpu < CPU_SETSIZE; cpu += 8)
> - if (CPU_ISSET(cpu, &mask))
> - return cpu;
> + for (cpu = 8; cpu < ncpus; cpu += 8)
> + if (CPU_ISSET_S(cpu, size, mask))
> + goto done;
>
> /* Search for anything, but in reverse */
> - for (cpu = CPU_SETSIZE - 1; cpu >= 0; cpu--)
> - if (CPU_ISSET(cpu, &mask))
> - return cpu;
> + for (cpu = ncpus - 1; cpu >= 0; cpu--)
> + if (CPU_ISSET_S(cpu, size, mask))
> + goto done;
>
> printf("No cpus in affinity mask?!\n");
> - return -1;
Missed the fact that the for loop before this would anyway make 'cpu'
count down to -1 if no online CPU is found. Please ignore the previous
message.
> +
> +done:
> + CPU_FREE(mask);
> + return cpu;
> }
>
> bool is_ppc64le(void)
>
- Sandipan
^ permalink raw reply
* Re: [PATCH v2] selftests: powerpc: Fix CPU affinity for child process
From: Satheesh Rajendran @ 2020-06-09 6:32 UTC (permalink / raw)
To: Harish; +Cc: srikar, kamalesh, shiganta, sandipan, linuxppc-dev
In-Reply-To: <20200609034005.520137-1-harish@linux.ibm.com>
On Tue, Jun 09, 2020 at 09:10:05AM +0530, Harish wrote:
> On systems with large number of cpus, test fails trying to set
> affinity for child process by calling sched_setaffinity() with
> smaller size for cpuset. This patch fixes it by making sure that
> the size of allocated cpu set is dependent on the number of CPUs
> as reported by get_nprocs().
>
> Fixes: 00b7ec5c9cf3 ("selftests/powerpc: Import Anton's context_switch2 benchmark")
> Reported-by: Shirisha Ganta <shiganta@in.ibm.com>
> Signed-off-by: Harish <harish@linux.ibm.com>
> Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
> ---
> .../powerpc/benchmarks/context_switch.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/tools/testing/selftests/powerpc/benchmarks/context_switch.c b/tools/testing/selftests/powerpc/benchmarks/context_switch.c
> index a2e8c9da7fa5..de6c49d6f88f 100644
> --- a/tools/testing/selftests/powerpc/benchmarks/context_switch.c
> +++ b/tools/testing/selftests/powerpc/benchmarks/context_switch.c
> @@ -19,6 +19,7 @@
> #include <limits.h>
> #include <sys/time.h>
> #include <sys/syscall.h>
> +#include <sys/sysinfo.h>
> #include <sys/types.h>
> #include <sys/shm.h>
> #include <linux/futex.h>
> @@ -104,8 +105,9 @@ static void start_thread_on(void *(*fn)(void *), void *arg, unsigned long cpu)
>
> static void start_process_on(void *(*fn)(void *), void *arg, unsigned long cpu)
> {
> - int pid;
> - cpu_set_t cpuset;
> + int pid, ncpus;
> + cpu_set_t *cpuset;
> + size_t size;
>
> pid = fork();
> if (pid == -1) {
> @@ -116,12 +118,16 @@ static void start_process_on(void *(*fn)(void *), void *arg, unsigned long cpu)
> if (pid)
> return;
>
> - CPU_ZERO(&cpuset);
> - CPU_SET(cpu, &cpuset);
> + size = CPU_ALLOC_SIZE(ncpus);
> + ncpus = get_nprocs();
above two lines should be interchanged, ncpus not assigned while getting used to get size.
> + cpuset = CPU_ALLOC(ncpus);
> + CPU_ZERO_S(size, cpuset);
> + CPU_SET_S(cpu, size, cpuset);
>
> - if (sched_setaffinity(0, sizeof(cpuset), &cpuset)) {
> + if (sched_setaffinity(0, size, cpuset)) {
> perror("sched_setaffinity");
> - exit(1);
> + CPU_FREE(cpuset);
> + exit(-1);
do we need to change the return value here?
probably other framework might rely on previous value?
Regards,
-Satheesh.
> }
>
> fn(arg);
> --
> 2.24.1
>
^ permalink raw reply
* [PATCH 0/7] powerpc: branch cache flush changes
From: Nicholas Piggin @ 2020-06-09 7:06 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
This series allows the link stack to be flushed with the speical
bcctr 2,0,0 flush instruction that also flushes the count cache if
the processor supports it.
Firmware does not support this at the moment, but I've tested it in
simulator with a patched firmware to advertise support.
Thanks,
Nick
Nicholas Piggin (7):
powerpc/security: re-name count cache flush to branch cache flush
powerpc/security: change link stack flush state to the flush type enum
powerpc/security: make display of branch cache flush more consistent
powerpc/security: split branch cache flush toggle from code patching
powerpc/64s: Move branch cache flushing bcctr variant to ppc-ops.h
powerpc/security: Allow for processors that flush the link stack using
the special bcctr
powerpc/64s: advertise hardware link stack flush
arch/powerpc/include/asm/asm-prototypes.h | 4 +-
arch/powerpc/include/asm/hvcall.h | 1 +
arch/powerpc/include/asm/ppc-opcode.h | 2 +
arch/powerpc/include/asm/security_features.h | 2 +
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kernel/entry_64.S | 13 +-
arch/powerpc/kernel/security.c | 139 +++++++++++--------
arch/powerpc/kvm/powerpc.c | 9 +-
arch/powerpc/platforms/powernv/setup.c | 3 +
arch/powerpc/platforms/pseries/setup.c | 3 +
tools/arch/powerpc/include/uapi/asm/kvm.h | 1 +
11 files changed, 106 insertions(+), 72 deletions(-)
--
2.23.0
^ permalink raw reply
* [PATCH 1/7] powerpc/security: re-name count cache flush to branch cache flush
From: Nicholas Piggin @ 2020-06-09 7:06 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
In-Reply-To: <20200609070610.846703-1-npiggin@gmail.com>
The count cache flush mostly refers to both count cache and link stack
flushing. As a first step to untangling these a bit, re-name the bits
that apply to both.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/asm-prototypes.h | 4 +--
arch/powerpc/kernel/entry_64.S | 7 ++---
arch/powerpc/kernel/security.c | 36 +++++++++++------------
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/arch/powerpc/include/asm/asm-prototypes.h b/arch/powerpc/include/asm/asm-prototypes.h
index 7d81e86a1e5d..fa9057360e88 100644
--- a/arch/powerpc/include/asm/asm-prototypes.h
+++ b/arch/powerpc/include/asm/asm-prototypes.h
@@ -144,13 +144,13 @@ void _kvmppc_restore_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
void _kvmppc_save_tm_pr(struct kvm_vcpu *vcpu, u64 guest_msr);
/* Patch sites */
-extern s32 patch__call_flush_count_cache;
+extern s32 patch__call_flush_branch_caches;
extern s32 patch__flush_count_cache_return;
extern s32 patch__flush_link_stack_return;
extern s32 patch__call_kvm_flush_link_stack;
extern s32 patch__memset_nocache, patch__memcpy_nocache;
-extern long flush_count_cache;
+extern long flush_branch_caches;
extern long kvm_flush_link_stack;
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 9d49338e0c85..2ba25b3b701e 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -259,8 +259,7 @@ _ASM_NOKPROBE_SYMBOL(save_nvgprs);
#define FLUSH_COUNT_CACHE \
1: nop; \
- patch_site 1b, patch__call_flush_count_cache
-
+ patch_site 1b, patch__call_flush_branch_caches
#define BCCTR_FLUSH .long 0x4c400420
@@ -271,8 +270,8 @@ _ASM_NOKPROBE_SYMBOL(save_nvgprs);
.endm
.balign 32
-.global flush_count_cache
-flush_count_cache:
+.global flush_branch_caches
+flush_branch_caches:
/* Save LR into r9 */
mflr r9
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index d86701ce116b..df2a3eff950b 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -21,12 +21,12 @@
u64 powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
-enum count_cache_flush_type {
- COUNT_CACHE_FLUSH_NONE = 0x1,
- COUNT_CACHE_FLUSH_SW = 0x2,
- COUNT_CACHE_FLUSH_HW = 0x4,
+enum branch_cache_flush_type {
+ BRANCH_CACHE_FLUSH_NONE = 0x1,
+ BRANCH_CACHE_FLUSH_SW = 0x2,
+ BRANCH_CACHE_FLUSH_HW = 0x4,
};
-static enum count_cache_flush_type count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
+static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
static bool link_stack_flush_enabled;
bool barrier_nospec_enabled;
@@ -222,10 +222,10 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (link_stack_flush_enabled)
seq_buf_printf(&s, ", Software link stack flush");
- } else if (count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
+ } else if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
seq_buf_printf(&s, "Mitigation: Software count cache flush");
- if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW)
seq_buf_printf(&s, " (hardware accelerated)");
if (link_stack_flush_enabled)
@@ -429,18 +429,18 @@ device_initcall(stf_barrier_debugfs_init);
static void no_count_cache_flush(void)
{
- count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
pr_info("count-cache-flush: software flush disabled.\n");
}
-static void toggle_count_cache_flush(bool enable)
+static void toggle_branch_cache_flush(bool enable)
{
if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE) &&
!security_ftr_enabled(SEC_FTR_FLUSH_LINK_STACK))
enable = false;
if (!enable) {
- patch_instruction_site(&patch__call_flush_count_cache,
+ patch_instruction_site(&patch__call_flush_branch_caches,
ppc_inst(PPC_INST_NOP));
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
patch_instruction_site(&patch__call_kvm_flush_link_stack,
@@ -452,9 +452,9 @@ static void toggle_count_cache_flush(bool enable)
return;
}
- // This enables the branch from _switch to flush_count_cache
- patch_branch_site(&patch__call_flush_count_cache,
- (u64)&flush_count_cache, BRANCH_SET_LINK);
+ // This enables the branch from _switch to flush_branch_caches
+ patch_branch_site(&patch__call_flush_branch_caches,
+ (u64)&flush_branch_caches, BRANCH_SET_LINK);
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
// This enables the branch from guest_exit_cont to kvm_flush_link_stack
@@ -474,13 +474,13 @@ static void toggle_count_cache_flush(bool enable)
}
if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
- count_cache_flush_type = COUNT_CACHE_FLUSH_SW;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_SW;
pr_info("count-cache-flush: full software flush sequence enabled.\n");
return;
}
patch_instruction_site(&patch__flush_count_cache_return, ppc_inst(PPC_INST_BLR));
- count_cache_flush_type = COUNT_CACHE_FLUSH_HW;
+ count_cache_flush_type = BRANCH_CACHE_FLUSH_HW;
pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
}
@@ -505,7 +505,7 @@ void setup_count_cache_flush(void)
security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE))
security_ftr_set(SEC_FTR_FLUSH_LINK_STACK);
- toggle_count_cache_flush(enable);
+ toggle_branch_cache_flush(enable);
}
#ifdef CONFIG_DEBUG_FS
@@ -520,14 +520,14 @@ static int count_cache_flush_set(void *data, u64 val)
else
return -EINVAL;
- toggle_count_cache_flush(enable);
+ toggle_branch_cache_flush(enable);
return 0;
}
static int count_cache_flush_get(void *data, u64 *val)
{
- if (count_cache_flush_type == COUNT_CACHE_FLUSH_NONE)
+ if (count_cache_flush_type == BRANCH_CACHE_FLUSH_NONE)
*val = 0;
else
*val = 1;
--
2.23.0
^ permalink raw reply related
* [PATCH 2/7] powerpc/security: change link stack flush state to the flush type enum
From: Nicholas Piggin @ 2020-06-09 7:06 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Nicholas Piggin
In-Reply-To: <20200609070610.846703-1-npiggin@gmail.com>
Prepare to allow for hardware link stack flushing by using the
none/sw/hw type, same as the count cache state.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/security.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/kernel/security.c b/arch/powerpc/kernel/security.c
index df2a3eff950b..28f4cb062f69 100644
--- a/arch/powerpc/kernel/security.c
+++ b/arch/powerpc/kernel/security.c
@@ -27,7 +27,7 @@ enum branch_cache_flush_type {
BRANCH_CACHE_FLUSH_HW = 0x4,
};
static enum branch_cache_flush_type count_cache_flush_type = BRANCH_CACHE_FLUSH_NONE;
-static bool link_stack_flush_enabled;
+static enum branch_cache_flush_type link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
bool barrier_nospec_enabled;
static bool no_nospec;
@@ -219,7 +219,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (ccd)
seq_buf_printf(&s, "Indirect branch cache disabled");
- if (link_stack_flush_enabled)
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
seq_buf_printf(&s, ", Software link stack flush");
} else if (count_cache_flush_type != BRANCH_CACHE_FLUSH_NONE) {
@@ -228,7 +228,7 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, c
if (count_cache_flush_type == BRANCH_CACHE_FLUSH_HW)
seq_buf_printf(&s, " (hardware accelerated)");
- if (link_stack_flush_enabled)
+ if (link_stack_flush_type == BRANCH_CACHE_FLUSH_SW)
seq_buf_printf(&s, ", Software link stack flush");
} else if (btb_flush_enabled) {
@@ -447,7 +447,7 @@ static void toggle_branch_cache_flush(bool enable)
ppc_inst(PPC_INST_NOP));
#endif
pr_info("link-stack-flush: software flush disabled.\n");
- link_stack_flush_enabled = false;
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_NONE;
no_count_cache_flush();
return;
}
@@ -463,7 +463,7 @@ static void toggle_branch_cache_flush(bool enable)
#endif
pr_info("link-stack-flush: software flush enabled.\n");
- link_stack_flush_enabled = true;
+ link_stack_flush_type = BRANCH_CACHE_FLUSH_SW;
// If we just need to flush the link stack, patch an early return
if (!security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
--
2.23.0
^ permalink raw reply related
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