* Re: [PATCH v2 0/3] Power10 basic energy management
From: Nicholas Piggin @ 2020-07-13 16:58 UTC (permalink / raw)
To: ego
Cc: ravi.bangoria, mikey, pratik.r.sampat, linux-kernel,
Pratik Rajesh Sampat, paulus, linuxppc-dev
In-Reply-To: <20200713104837.GG24866@in.ibm.com>
Excerpts from Gautham R Shenoy's message of July 13, 2020 8:48 pm:
> On Mon, Jul 13, 2020 at 03:23:21PM +1000, Nicholas Piggin wrote:
>> Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
>> > Changelog v1 --> v2:
>> > 1. Save-restore DAWR and DAWRX unconditionally as they are lost in
>> > shallow idle states too
>> > 2. Rename pnv_first_spr_loss_level to pnv_first_fullstate_loss_level to
>> > correct naming terminology
>> >
>> > Pratik Rajesh Sampat (3):
>> > powerpc/powernv/idle: Exclude mfspr on HID1,4,5 on P9 and above
>> > powerpc/powernv/idle: save-restore DAWR0,DAWRX0 for P10
>> > powerpc/powernv/idle: Rename pnv_first_spr_loss_level variable
>> >
>> > arch/powerpc/platforms/powernv/idle.c | 34 +++++++++++++++++----------
>> > 1 file changed, 22 insertions(+), 12 deletions(-)
>>
>> These look okay to me, but the CPU_FTR_ARCH_300 test for
>> pnv_power9_idle_init() is actually wrong, it should be a PVR test
>> because idle is not completely architected (not even shallow stop
>> states, unfortunately).
>>
>> It doesn't look like we support POWER10 idle correctly yet, and on older
>> kernels it wouldn't work even if we fixed newer, so ideally the PVR
>> check would be backported as a fix in the front of the series.
>>
>> Sadly, we have no OPAL idle driver yet. Hopefully we will before the
>> next processor shows up :P
>
> Abhishek posted a version recently :
> https://patchwork.ozlabs.org/project/skiboot/patch/20200706043533.76539-1-huntbag@linux.vnet.ibm.com/
Yep, I saw that. Still keen to get it working, just had other priorities
in the short term. We'll need to do this OPAL v4 thing for it.
Thanks,
Nick
^ permalink raw reply
* [PATCH 12/14 v3] PCI/AER: Check the return value of pcie_capability_read_*()
From: Saheed O. Bolarinwa @ 2020-07-13 17:55 UTC (permalink / raw)
To: skhan, linux-pci, linuxppc-dev, linux-kernel-mentees,
linux-kernel
Cc: Bolarinwa Olayemi Saheed
In-Reply-To: <20200713175529.29715-1-refactormyself@gmail.com>
From: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
On failure pcie_capability_read_dword() sets it's last parameter,
val to 0.
However, with Patch 14/14, it is possible that val is set to ~0 on
failure. This would introduce a bug because (x & x) == (~0 & x).
This bug can be avoided if the return value of pcie_capability_read_word
is checked to confirm success.
Check the return value of pcie_capability_read_word() to ensure success.
Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
Signed-off-by: Bolarinwa Olayemi Saheed <refactormyself@gmail.com>
---
drivers/pci/pcie/aer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 3acf56683915..f4beb47c622c 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -800,6 +800,7 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
int aer = dev->aer_cap;
u32 status, mask;
u16 reg16;
+ int ret;
/*
* When bus id is equal to 0, it might be a bad id
@@ -828,8 +829,8 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info)
return false;
/* Check if AER is enabled */
- pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
- if (!(reg16 & PCI_EXP_AER_FLAGS))
+ ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16);
+ if (ret || !(reg16 & PCI_EXP_AER_FLAGS))
return false;
if (!aer)
--
2.18.2
^ permalink raw reply related
* Re: [PATCH v2 0/3] Power10 basic energy management
From: Nicholas Piggin @ 2020-07-13 16:50 UTC (permalink / raw)
To: benh, ego, linux-kernel, linuxppc-dev, mikey, mpe, paulus,
pratik.r.sampat, Pratik Sampat, ravi.bangoria, svaidy
In-Reply-To: <bc6494c0-9a17-2416-c6cc-15612020f497@linux.ibm.com>
Excerpts from Pratik Sampat's message of July 13, 2020 8:02 pm:
> Thank you for your comments,
>
> On 13/07/20 10:53 am, Nicholas Piggin wrote:
>> Excerpts from Pratik Rajesh Sampat's message of July 10, 2020 3:22 pm:
>>> Changelog v1 --> v2:
>>> 1. Save-restore DAWR and DAWRX unconditionally as they are lost in
>>> shallow idle states too
>>> 2. Rename pnv_first_spr_loss_level to pnv_first_fullstate_loss_level to
>>> correct naming terminology
>>>
>>> Pratik Rajesh Sampat (3):
>>> powerpc/powernv/idle: Exclude mfspr on HID1,4,5 on P9 and above
>>> powerpc/powernv/idle: save-restore DAWR0,DAWRX0 for P10
>>> powerpc/powernv/idle: Rename pnv_first_spr_loss_level variable
>>>
>>> arch/powerpc/platforms/powernv/idle.c | 34 +++++++++++++++++----------
>>> 1 file changed, 22 insertions(+), 12 deletions(-)
>> These look okay to me, but the CPU_FTR_ARCH_300 test for
>> pnv_power9_idle_init() is actually wrong, it should be a PVR test
>> because idle is not completely architected (not even shallow stop
>> states, unfortunately).
>>
>> It doesn't look like we support POWER10 idle correctly yet, and on older
>> kernels it wouldn't work even if we fixed newer, so ideally the PVR
>> check would be backported as a fix in the front of the series.
>>
>> Sadly, we have no OPAL idle driver yet. Hopefully we will before the
>> next processor shows up :P
>>
>> Thanks,
>> Nick
>
> So if I understand this correctly, in powernv/idle.c where we check for
> CPU_FTR_ARCH_300, we should rather be making a pvr_version_is(PVR_POWER9)
> check instead?
>
> Of course, the P10 PVR and its relevant checks will have to be added then too.
Yes I think so, unfortunately.
Thanks,
Nick
^ permalink raw reply
* [PATCH v6] ima: move APPRAISE_BOOTPARAM dependency on ARCH_POLICY to runtime
From: Bruno Meneguele @ 2020-07-13 16:48 UTC (permalink / raw)
To: linux-kernel, x86, linuxppc-dev, linux-s390, linux-integrity
Cc: erichte, Bruno Meneguele, nayna, stable, zohar
The IMA_APPRAISE_BOOTPARAM config allows enabling different "ima_appraise="
modes - log, fix, enforce - at run time, but not when IMA architecture
specific policies are enabled. This prevents properly labeling the
filesystem on systems where secure boot is supported, but not enabled on the
platform. Only when secure boot is actually enabled should these IMA
appraise modes be disabled.
This patch removes the compile time dependency and makes it a runtime
decision, based on the secure boot state of that platform.
Test results as follows:
-> x86-64 with secure boot enabled
[ 0.015637] Kernel command line: <...> ima_policy=appraise_tcb ima_appraise=fix
[ 0.015668] ima: Secure boot enabled: ignoring ima_appraise=fix boot parameter option
-> powerpc with secure boot disabled
[ 0.000000] Kernel command line: <...> ima_policy=appraise_tcb ima_appraise=fix
[ 0.000000] Secure boot mode disabled
-> Running the system without secure boot and with both options set:
CONFIG_IMA_APPRAISE_BOOTPARAM=y
CONFIG_IMA_ARCH_POLICY=y
Audit prompts "missing-hash" but still allow execution and, consequently,
filesystem labeling:
type=INTEGRITY_DATA msg=audit(07/09/2020 12:30:27.778:1691) : pid=4976
uid=root auid=root ses=2
subj=unconfined_u:unconfined_r:unconfined_t:s0-s0:c0.c1023 op=appraise_data
cause=missing-hash comm=bash name=/usr/bin/evmctl dev="dm-0" ino=493150
res=no
Cc: stable@vger.kernel.org
Fixes: d958083a8f64 ("x86/ima: define arch_get_ima_policy() for x86")
Signed-off-by: Bruno Meneguele <bmeneg@redhat.com>
---
v6:
- explictly print the bootparam being ignored to the user (Mimi)
v5:
- add pr_info() to inform user the ima_appraise= boot param is being
ignored due to secure boot enabled (Nayna)
- add some testing results to commit log
v4:
- instead of change arch_policy loading code, check secure boot state at
"ima_appraise=" parameter handler (Mimi)
v3:
- extend secure boot arch checker to also consider trusted boot
- enforce IMA appraisal when secure boot is effectively enabled (Nayna)
- fix ima_appraise flag assignment by or'ing it (Mimi)
v2:
- pr_info() message prefix correction
security/integrity/ima/Kconfig | 2 +-
security/integrity/ima/ima_appraise.c | 6 ++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig
index edde88dbe576..62dc11a5af01 100644
--- a/security/integrity/ima/Kconfig
+++ b/security/integrity/ima/Kconfig
@@ -232,7 +232,7 @@ config IMA_APPRAISE_REQUIRE_POLICY_SIGS
config IMA_APPRAISE_BOOTPARAM
bool "ima_appraise boot parameter"
- depends on IMA_APPRAISE && !IMA_ARCH_POLICY
+ depends on IMA_APPRAISE
default y
help
This option enables the different "ima_appraise=" modes
diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
index a9649b04b9f1..28a59508c6bd 100644
--- a/security/integrity/ima/ima_appraise.c
+++ b/security/integrity/ima/ima_appraise.c
@@ -19,6 +19,12 @@
static int __init default_appraise_setup(char *str)
{
#ifdef CONFIG_IMA_APPRAISE_BOOTPARAM
+ if (arch_ima_get_secureboot()) {
+ pr_info("Secure boot enabled: ignoring ima_appraise=%s boot parameter option",
+ str);
+ return 1;
+ }
+
if (strncmp(str, "off", 3) == 0)
ima_appraise = 0;
else if (strncmp(str, "log", 3) == 0)
--
2.26.2
^ permalink raw reply related
* Re: [RFC PATCH 7/7] lazy tlb: shoot lazies, a non-refcounting lazy tlb option
From: Nicholas Piggin @ 2020-07-13 16:48 UTC (permalink / raw)
To: Andy Lutomirski
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, X86 ML, LKML, Linux-MM,
Mathieu Desnoyers, linuxppc-dev
In-Reply-To: <CALCETrWbD=3SUOuq9P7Syb+a1DoBjjem8hq9_HCvn7wyqETkpw@mail.gmail.com>
Excerpts from Andy Lutomirski's message of July 14, 2020 1:59 am:
> On Thu, Jul 9, 2020 at 6:57 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>>
>> On big systems, the mm refcount can become highly contented when doing
>> a lot of context switching with threaded applications (particularly
>> switching between the idle thread and an application thread).
>>
>> Abandoning lazy tlb slows switching down quite a bit in the important
>> user->idle->user cases, so so instead implement a non-refcounted scheme
>> that causes __mmdrop() to IPI all CPUs in the mm_cpumask and shoot down
>> any remaining lazy ones.
>>
>> On a 16-socket 192-core POWER8 system, a context switching benchmark
>> with as many software threads as CPUs (so each switch will go in and
>> out of idle), upstream can achieve a rate of about 1 million context
>> switches per second. After this patch it goes up to 118 million.
>>
>
> I read the patch a couple of times, and I have a suggestion that could
> be nonsense. You are, effectively, using mm_cpumask() as a sort of
> refcount. You're saying "hey, this mm has no more references, but it
> still has nonempty mm_cpumask(), so let's send an IPI and shoot down
> those references too." I'm wondering whether you actually need the
> IPI. What if, instead, you actually treated mm_cpumask as a refcount
> for real? Roughly, in __mmdrop(), you would only free the page tables
> if mm_cpumask() is empty. And, in the code that removes a CPU from
> mm_cpumask(), you would check if mm_users == 0 and, if so, check if
> you just removed the last bit from mm_cpumask and potentially free the
> mm.
>
> Getting the locking right here could be a bit tricky -- you need to
> avoid two CPUs simultaneously exiting lazy TLB and thinking they
> should free the mm, and you also need to avoid an mm with mm_users
> hitting zero concurrently with the last remote CPU using it lazily
> exiting lazy TLB. Perhaps this could be resolved by having mm_count
> == 1 mean "mm_cpumask() is might contain bits and, if so, it owns the
> mm" and mm_count == 0 meaning "now it's dead" and using some careful
> cmpxchg or dec_return to make sure that only one CPU frees it.
>
> Or maybe you'd need a lock or RCU for this, but the idea would be to
> only ever take the lock after mm_users goes to zero.
I don't think it's nonsense, it could be a good way to avoid IPIs.
I haven't seen much problem here that made me too concerned about IPIs
yet, so I think the simple patch may be good enough to start with
for powerpc. I'm looking at avoiding/reducing the IPIs by combining the
unlazying with the exit TLB flush without doing anything fancy with
ref counting, but we'll see.
Thanks,
Nick
^ permalink raw reply
* Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode
From: Nicholas Piggin @ 2020-07-13 16:37 UTC (permalink / raw)
To: Andy Lutomirski, Mathieu Desnoyers
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, x86, linux-kernel,
linux-mm, linuxppc-dev
In-Reply-To: <CALCETrUHsYp0oGAiy3N-yAauPyx2nKqp1AiETgSJWc77GwO-Sg@mail.gmail.com>
Excerpts from Andy Lutomirski's message of July 14, 2020 1:48 am:
> On Mon, Jul 13, 2020 at 7:13 AM Mathieu Desnoyers
> <mathieu.desnoyers@efficios.com> wrote:
>>
>> ----- On Jul 13, 2020, at 9:47 AM, Nicholas Piggin npiggin@gmail.com wrote:
>>
>> > Excerpts from Nicholas Piggin's message of July 13, 2020 2:45 pm:
>> >> Excerpts from Andy Lutomirski's message of July 11, 2020 3:04 am:
>> >>> Also, as it stands, I can easily see in_irq() ceasing to promise to
>> >>> serialize. There are older kernels for which it does not promise to
>> >>> serialize. And I have plans to make it stop serializing in the
>> >>> nearish future.
>> >>
>> >> You mean x86's return from interrupt? Sounds fun... you'll konw where to
>> >> update the membarrier sync code, at least :)
>> >
>> > Oh, I should actually say Mathieu recently clarified a return from
>> > interrupt doesn't fundamentally need to serialize in order to support
>> > membarrier sync core.
>>
>> Clarification to your statement:
>>
>> Return from interrupt to kernel code does not need to be context serializing
>> as long as kernel serializes before returning to user-space.
>>
>> However, return from interrupt to user-space needs to be context serializing.
>>
>
> Indeed, and I figured this out on the first read through because I'm
> quite familiar with the x86 entry code. But Nick somehow missed this,
> and Nick is the one who wrote the patch.
>
> Nick, I think this helps prove my point. The code you're submitting
> may well be correct, but it's unmaintainable.
It's not. The patch I wrote for x86 is a no-op, it just moves existing
x86 hook and code that's already there to a different name.
Actually it's not quite a no-op, it't changes it to use hooks that are
actually called in the right places. Because previously it was
unmaintainable from point of view of generic mm -- it was not clear at
all that the old one should have been called in other places where the
mm goes non-lazy. Now with the exit_lazy_tlb hook, it can quite easily
be spotted where it is missing.
And x86 keeps their membarrier code in x86, and uses nice well defined
lazy tlb mm hooks.
> At the very least, this
> needs a comment explaining, from the perspective of x86, *exactly*
> what exit_lazy_tlb() is promising, why it's promising it, how it
> achieves that promise, and what code cares about it. Or we could do
> something with TIF flags and make this all less magical, although that
> will probably end up very slightly slower.
It's all documented there in existing comments plus the asm-generic
exit_lazy_tlb specification added AFAIKS.
Is the membarrier comment in finish_task_switch plus these ones not
enough?
Thanks,
Nick
^ permalink raw reply
* [PATCH 1/1 V4] : PCIE PHB reset
From: wenxiong @ 2020-07-13 14:39 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Wen Xiong, oohall, bobroff, brking, wenxiong
From: Wen Xiong <wenxiong@linux.vnet.ibm.com>
Several device drivers hit EEH(Extended Error handling) when triggering
kdump on Pseries PowerVM. This patch implemented a reset of the PHBs
in pci general code when triggering kdump. PHB reset stop all PCI
transactions from normal kernel. We have tested the patch in several
enviroments:
- direct slot adapters
- adapters under the switch
- a VF adapter in PowerVM
- a VF adapter/adapter in KVM guest.
Change History:
V4:
- Merge the code from pseries/pci.c to pseries/eeh_pseries.c
- Add 3 helper functions which are shared by eeh code and this path.
Reviewed by Michael Ellerman.
V3:
- Change the comments(Reviewed by Gustavo Romero)
V2:
- change to machine_postcore_initall(Reviewed by Oliver Halloran)
- change the error pathes(Reviewed by Sam Bobroff)
V1:
- initial version
Signed-off-by: Wen Xiong<wenxiong@linux.vnet.ibm.com>
---
arch/powerpc/platforms/pseries/eeh_pseries.c | 234 ++++++++++++++-----
1 file changed, 170 insertions(+), 64 deletions(-)
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index ace117f99d94..a3ae8d206a86 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -24,6 +24,7 @@
#include <linux/sched.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
+#include <linux/crash_dump.h>
#include <asm/eeh.h>
#include <asm/eeh_event.h>
@@ -80,6 +81,152 @@ void pseries_pcibios_bus_add_device(struct pci_dev *pdev)
eeh_probe_device(pdev);
}
+
+/**
+ * pseries_eeh_get_config_addr - Retrieve config address
+ *
+ * Retrieve the assocated config address. Actually, there're 2 RTAS
+ * function calls dedicated for the purpose. We need implement
+ * it through the new function and then the old one. Besides,
+ * you should make sure the config address is figured out from
+ * FDT node before calling the function.
+ *
+ * It's notable that zero'ed return value means invalid PE config
+ * address.
+ */
+static int pseries_eeh_get_config_addr(struct pci_controller *phb, int config_addr)
+{
+ int ret = 0;
+ int rets[3];
+
+ if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
+ /*
+ * First of all, we need to make sure there has one PE
+ * associated with the device. Otherwise, PE address is
+ * meaningless.
+ */
+ ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid), 1);
+ if (ret || (rets[0] == 0))
+ return 0;
+
+ /* Retrieve the associated PE config address */
+ ret = rtas_call(ibm_get_config_addr_info2, 4, 2, rets,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid), 0);
+ if (ret) {
+ pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
+ __func__, phb->global_number, config_addr);
+ return 0;
+ }
+
+ return rets[0];
+ }
+
+ if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
+ ret = rtas_call(ibm_get_config_addr_info, 4, 2, rets,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid), 0);
+ if (ret) {
+ pr_warn("%s: Failed to get address for PHB#%x-PE#%x\n",
+ __func__, phb->global_number, config_addr);
+ return 0;
+ }
+
+ return rets[0];
+ }
+
+ return ret;
+}
+
+/**
+ * pseries_eeh_phb_reset - Reset the specified PHB
+ * @phb: PCI controller
+ * @config_adddr: the associated config address
+ * @option: reset option
+ *
+ * Reset the specified PHB/PE
+ */
+static int pseries_eeh_phb_reset(struct pci_controller *phb, int config_addr, int option)
+{
+ int ret;
+
+ /* Reset PE through RTAS call */
+ ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid), option);
+
+ /* If fundamental-reset not supported, try hot-reset */
+ if (option == EEH_RESET_FUNDAMENTAL &&
+ ret == -8) {
+ option = EEH_RESET_HOT;
+ ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid), option);
+ }
+
+ /* We need reset hold or settlement delay */
+ if (option == EEH_RESET_FUNDAMENTAL ||
+ option == EEH_RESET_HOT)
+ msleep(EEH_PE_RST_HOLD_TIME);
+ else
+ msleep(EEH_PE_RST_SETTLE_TIME);
+
+ return ret;
+}
+
+/**
+ * pseries_eeh_phb_configure_bridge - Configure PCI bridges in the indicated PE
+ * @phb: PCI controller
+ * @config_adddr: the associated config address
+ *
+ * The function will be called to reconfigure the bridges included
+ * in the specified PE so that the mulfunctional PE would be recovered
+ * again.
+ */
+static int pseries_eeh_phb_configure_bridge(struct pci_controller *phb, int config_addr)
+{
+ int ret;
+ /* Waiting 0.2s maximum before skipping configuration */
+ int max_wait = 200;
+
+ while (max_wait > 0) {
+ ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
+ config_addr, BUID_HI(phb->buid),
+ BUID_LO(phb->buid));
+
+ if (!ret)
+ return ret;
+ if (ret < 0)
+ break;
+
+ /*
+ * If RTAS returns a delay value that's above 100ms, cut it
+ * down to 100ms in case firmware made a mistake. For more
+ * on how these delay values work see rtas_busy_delay_time
+ */
+ if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
+ ret <= RTAS_EXTENDED_DELAY_MAX)
+ ret = RTAS_EXTENDED_DELAY_MIN+2;
+
+ max_wait -= rtas_busy_delay_time(ret);
+
+ if (max_wait < 0)
+ break;
+
+ rtas_busy_delay(ret);
+ }
+
+ pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
+ __func__, phb->global_number, config_addr, ret);
+ /* PAPR defines -3 as "Parameter Error" for this function: */
+ if (ret == -3)
+ return -EINVAL;
+ else
+ return -EIO;
+}
+
/*
* Buffer for reporting slot-error-detail rtas calls. Its here
* in BSS, and not dynamically alloced, so that it ends up in
@@ -96,6 +243,10 @@ static int eeh_error_buf_size;
*/
static int pseries_eeh_init(void)
{
+ struct pci_controller *phb;
+ struct pci_dn *pdn;
+ int addr, config_addr;
+
/* figure out EEH RTAS function call tokens */
ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
@@ -148,6 +299,22 @@ static int pseries_eeh_init(void)
/* Set EEH machine dependent code */
ppc_md.pcibios_bus_add_device = pseries_pcibios_bus_add_device;
+ if (is_kdump_kernel() || reset_devices) {
+ pr_info("Issue PHB reset ...\n");
+ list_for_each_entry(phb, &hose_list, list_node) {
+ pdn = list_first_entry(&PCI_DN(phb->dn)->child_list, struct pci_dn, list);
+ addr = (pdn->busno << 16) | (pdn->devfn << 8);
+ config_addr = pseries_eeh_get_config_addr(phb, addr);
+ /* invalid PE config addr */
+ if (config_addr == 0)
+ continue;
+
+ pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_FUNDAMENTAL);
+ pseries_eeh_phb_reset(phb, config_addr, EEH_RESET_DEACTIVATE);
+ pseries_eeh_phb_configure_bridge(phb, config_addr);
+ }
+ }
+
return 0;
}
@@ -569,35 +736,13 @@ static int pseries_eeh_get_state(struct eeh_pe *pe, int *delay)
static int pseries_eeh_reset(struct eeh_pe *pe, int option)
{
int config_addr;
- int ret;
/* Figure out PE address */
config_addr = pe->config_addr;
if (pe->addr)
config_addr = pe->addr;
-
- /* Reset PE through RTAS call */
- ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
- config_addr, BUID_HI(pe->phb->buid),
- BUID_LO(pe->phb->buid), option);
-
- /* If fundamental-reset not supported, try hot-reset */
- if (option == EEH_RESET_FUNDAMENTAL &&
- ret == -8) {
- option = EEH_RESET_HOT;
- ret = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
- config_addr, BUID_HI(pe->phb->buid),
- BUID_LO(pe->phb->buid), option);
- }
-
- /* We need reset hold or settlement delay */
- if (option == EEH_RESET_FUNDAMENTAL ||
- option == EEH_RESET_HOT)
- msleep(EEH_PE_RST_HOLD_TIME);
- else
- msleep(EEH_PE_RST_SETTLE_TIME);
-
- return ret;
+
+ return pseries_eeh_phb_reset(pe->phb, config_addr, option);
}
/**
@@ -641,56 +786,17 @@ static int pseries_eeh_get_log(struct eeh_pe *pe, int severity, char *drv_log, u
* pseries_eeh_configure_bridge - Configure PCI bridges in the indicated PE
* @pe: EEH PE
*
- * The function will be called to reconfigure the bridges included
- * in the specified PE so that the mulfunctional PE would be recovered
- * again.
*/
static int pseries_eeh_configure_bridge(struct eeh_pe *pe)
{
int config_addr;
- int ret;
- /* Waiting 0.2s maximum before skipping configuration */
- int max_wait = 200;
/* Figure out the PE address */
config_addr = pe->config_addr;
if (pe->addr)
config_addr = pe->addr;
- while (max_wait > 0) {
- ret = rtas_call(ibm_configure_pe, 3, 1, NULL,
- config_addr, BUID_HI(pe->phb->buid),
- BUID_LO(pe->phb->buid));
-
- if (!ret)
- return ret;
- if (ret < 0)
- break;
-
- /*
- * If RTAS returns a delay value that's above 100ms, cut it
- * down to 100ms in case firmware made a mistake. For more
- * on how these delay values work see rtas_busy_delay_time
- */
- if (ret > RTAS_EXTENDED_DELAY_MIN+2 &&
- ret <= RTAS_EXTENDED_DELAY_MAX)
- ret = RTAS_EXTENDED_DELAY_MIN+2;
-
- max_wait -= rtas_busy_delay_time(ret);
-
- if (max_wait < 0)
- break;
-
- rtas_busy_delay(ret);
- }
-
- pr_warn("%s: Unable to configure bridge PHB#%x-PE#%x (%d)\n",
- __func__, pe->phb->global_number, pe->addr, ret);
- /* PAPR defines -3 as "Parameter Error" for this function: */
- if (ret == -3)
- return -EINVAL;
- else
- return -EIO;
+ return pseries_eeh_phb_configure_bridge(pe->phb, config_addr);
}
/**
--
2.18.1
^ permalink raw reply related
* Re: [RFC PATCH 7/7] lazy tlb: shoot lazies, a non-refcounting lazy tlb option
From: Andy Lutomirski @ 2020-07-13 15:59 UTC (permalink / raw)
To: Nicholas Piggin
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, X86 ML, LKML, Linux-MM,
Mathieu Desnoyers, linuxppc-dev
In-Reply-To: <20200710015646.2020871-8-npiggin@gmail.com>
On Thu, Jul 9, 2020 at 6:57 PM Nicholas Piggin <npiggin@gmail.com> wrote:
>
> On big systems, the mm refcount can become highly contented when doing
> a lot of context switching with threaded applications (particularly
> switching between the idle thread and an application thread).
>
> Abandoning lazy tlb slows switching down quite a bit in the important
> user->idle->user cases, so so instead implement a non-refcounted scheme
> that causes __mmdrop() to IPI all CPUs in the mm_cpumask and shoot down
> any remaining lazy ones.
>
> On a 16-socket 192-core POWER8 system, a context switching benchmark
> with as many software threads as CPUs (so each switch will go in and
> out of idle), upstream can achieve a rate of about 1 million context
> switches per second. After this patch it goes up to 118 million.
>
I read the patch a couple of times, and I have a suggestion that could
be nonsense. You are, effectively, using mm_cpumask() as a sort of
refcount. You're saying "hey, this mm has no more references, but it
still has nonempty mm_cpumask(), so let's send an IPI and shoot down
those references too." I'm wondering whether you actually need the
IPI. What if, instead, you actually treated mm_cpumask as a refcount
for real? Roughly, in __mmdrop(), you would only free the page tables
if mm_cpumask() is empty. And, in the code that removes a CPU from
mm_cpumask(), you would check if mm_users == 0 and, if so, check if
you just removed the last bit from mm_cpumask and potentially free the
mm.
Getting the locking right here could be a bit tricky -- you need to
avoid two CPUs simultaneously exiting lazy TLB and thinking they
should free the mm, and you also need to avoid an mm with mm_users
hitting zero concurrently with the last remote CPU using it lazily
exiting lazy TLB. Perhaps this could be resolved by having mm_count
== 1 mean "mm_cpumask() is might contain bits and, if so, it owns the
mm" and mm_count == 0 meaning "now it's dead" and using some careful
cmpxchg or dec_return to make sure that only one CPU frees it.
Or maybe you'd need a lock or RCU for this, but the idea would be to
only ever take the lock after mm_users goes to zero.
--Andy
^ permalink raw reply
* Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode
From: Andy Lutomirski @ 2020-07-13 15:48 UTC (permalink / raw)
To: Mathieu Desnoyers
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, x86, linux-kernel,
Nicholas Piggin, linux-mm, Andy Lutomirski, linuxppc-dev
In-Reply-To: <284592761.9860.1594649601492.JavaMail.zimbra@efficios.com>
On Mon, Jul 13, 2020 at 7:13 AM Mathieu Desnoyers
<mathieu.desnoyers@efficios.com> wrote:
>
> ----- On Jul 13, 2020, at 9:47 AM, Nicholas Piggin npiggin@gmail.com wrote:
>
> > Excerpts from Nicholas Piggin's message of July 13, 2020 2:45 pm:
> >> Excerpts from Andy Lutomirski's message of July 11, 2020 3:04 am:
> >>> Also, as it stands, I can easily see in_irq() ceasing to promise to
> >>> serialize. There are older kernels for which it does not promise to
> >>> serialize. And I have plans to make it stop serializing in the
> >>> nearish future.
> >>
> >> You mean x86's return from interrupt? Sounds fun... you'll konw where to
> >> update the membarrier sync code, at least :)
> >
> > Oh, I should actually say Mathieu recently clarified a return from
> > interrupt doesn't fundamentally need to serialize in order to support
> > membarrier sync core.
>
> Clarification to your statement:
>
> Return from interrupt to kernel code does not need to be context serializing
> as long as kernel serializes before returning to user-space.
>
> However, return from interrupt to user-space needs to be context serializing.
>
Indeed, and I figured this out on the first read through because I'm
quite familiar with the x86 entry code. But Nick somehow missed this,
and Nick is the one who wrote the patch.
Nick, I think this helps prove my point. The code you're submitting
may well be correct, but it's unmaintainable. At the very least, this
needs a comment explaining, from the perspective of x86, *exactly*
what exit_lazy_tlb() is promising, why it's promising it, how it
achieves that promise, and what code cares about it. Or we could do
something with TIF flags and make this all less magical, although that
will probably end up very slightly slower.
--Andy
^ permalink raw reply
* Re: [PATCH 00/20] Documentation: eliminate duplicated words
From: Jonathan Corbet @ 2020-07-13 15:45 UTC (permalink / raw)
To: Randy Dunlap
Cc: kvm, linux-doc, David Airlie, kgdb-bugreport, linux-fpga,
Liviu Dudau, dri-devel, Douglas Anderson, Paul Cercueil, keyrings,
Paul Mackerras, linux-i2c, Pavel Machek, Srinivas Pandruvada,
Mihail Atanassov, linux-leds, linux-s390, Daniel Thompson,
linux-scsi, Masahiro Yamada, Matthew Wilcox, Halil Pasic,
Jarkko Sakkinen, James Wang, linux-input, Mali DP Maintainers,
Derek Kiernan, linux-mips, Dragan Cvetic, Wu Hao, Tony Krowiak,
linux-kbuild, James E.J. Bottomley, Jiri Kosina, Hannes Reinecke,
linux-block, Thomas Bogendoerfer, Jacek Anaszewski, linux-mm,
Dan Williams, Andrew Morton, Mimi Zohar, Jens Axboe, Michal Marek,
Martin K. Petersen, Pierre Morel, linux-kernel, Wolfram Sang,
Daniel Vetter, Jason Wessel, Paolo Bonzini, linux-integrity,
linuxppc-dev, Mike Rapoport, Dan Murphy
In-Reply-To: <20200707180414.10467-1-rdunlap@infradead.org>
On Tue, 7 Jul 2020 11:03:54 -0700
Randy Dunlap <rdunlap@infradead.org> wrote:
> Documentation/admin-guide/mm/numaperf.rst | 2 +-
> Documentation/block/pr.rst | 2 +-
> Documentation/core-api/printk-basics.rst | 2 +-
> Documentation/dev-tools/kgdb.rst | 2 +-
> Documentation/fpga/dfl.rst | 2 +-
> Documentation/gpu/drm-uapi.rst | 2 +-
> Documentation/gpu/komeda-kms.rst | 2 +-
> Documentation/hid/intel-ish-hid.rst | 2 +-
> Documentation/i2c/upgrading-clients.rst | 2 +-
> Documentation/kbuild/kconfig-language.rst | 2 +-
> Documentation/leds/ledtrig-transient.rst | 2 +-
> Documentation/maintainer/maintainer-entry-profile.rst | 2 +-
> Documentation/mips/ingenic-tcu.rst | 2 +-
> Documentation/misc-devices/xilinx_sdfec.rst | 2 +-
> Documentation/powerpc/vas-api.rst | 2 +-
> Documentation/s390/vfio-ap.rst | 2 +-
> Documentation/scsi/advansys.rst | 2 +-
> Documentation/security/keys/trusted-encrypted.rst | 2 +-
> Documentation/virt/kvm/api.rst | 2 +-
> Documentation/vm/memory-model.rst | 2 +-
> 20 files changed, 20 insertions(+), 20 deletions(-)
I've applied this set, minus #17 that was already picked up by Martin.
Thanks,
jon
^ permalink raw reply
* Re: [RFC PATCH 00/35] Move all PCIBIOS* definitions into arch/x86
From: Arnd Bergmann @ 2020-07-13 15:08 UTC (permalink / raw)
To: Saheed O. Bolarinwa
Cc: Rich Felker, Martin K. Petersen, Linux-sh list, linux-pci,
linux-nvme, Yicong Yang, sparclinux,
Realtek linux nic maintainers, Paul Mackerras, Linux I2C,
bcm-kernel-feedback-list, Bjorn Helgaas, rfi, Toan Le,
Greg Ungerer, Marek Vasut, Rob Herring, Stefano Stabellini,
Sagi Grimberg, Yoshinori Sato, linux-scsi, Greg Kroah-Hartman,
linux-atm-general, Russell King, Ley Foon Tan, Christoph Hellwig,
Geert Uytterhoeven, Rafał Miłecki, Chas Williams,
xen-devel, Matt Turner, open list:BROADCOM NVRAM DRIVER,
linux-kernel-mentees, Kevin Hilman, Guenter Roeck, linux-hwmon,
Jean Delvare, Andrew Donnellan, Ray Jui, James E.J. Bottomley,
Linux-Renesas, Yue Wang, Jens Axboe, Jakub Kicinski, linux-m68k,
Lorenzo Pieralisi, Ivan Kokshaysky, Michael Buesch, Shuah Khan,
bjorn, open list:ARM/Amlogic Meson SoC support, Boris Ostrovsky,
Guan Xuetao, Linux ARM, Richard Henderson, Juergen Gross,
Michal Simek, Thomas Bogendoerfer, Scott Branden, Bjorn Helgaas,
Jingoo Han, Networking, Yoshihiro Shimoda, linux-wireless,
linux-kernel@vger.kernel.org, Keith Busch, Brian King,
Philipp Zabel, alpha, Frederic Barrat, Gustavo Pimentel,
linuxppc-dev, David S. Miller, Heiner Kallweit
In-Reply-To: <20200713122247.10985-1-refactormyself@gmail.com>
On Mon, Jul 13, 2020 at 3:22 PM Saheed O. Bolarinwa
<refactormyself@gmail.com> wrote:
> This goal of these series is to move the definition of *all* PCIBIOS* from
> include/linux/pci.h to arch/x86 and limit their use within there.
> All other tree specific definition will be left for intact. Maybe they can
> be renamed.
>
> PCIBIOS* is an x86 concept as defined by the PCI spec. The returned error
> codes of PCIBIOS* are positive values and this introduces some complexities
> which other archs need not incur.
I think the intention is good, but I find the series in its current
form very hard
to review, in particular the way you touch some functions three times with
trivial changes. Instead of
1) replace PCIBIOS_SUCCESSFUL with 0
2) drop pointless 0-comparison
3) reformat whitespace
I would suggest to combine the first two steps into one patch per
subsystem and drop the third step.
> PLAN:
>
> 1. [PATCH v0 1-36] Replace all PCIBIOS_SUCCESSFUL with 0
>
> 2a. Audit all functions returning PCIBIOS_* error values directly or
> indirectly and prevent possible bug coming in (2b)
>
> 2b. Make all functions returning PCIBIOS_* error values call
> pcibios_err_to_errno(). *This will change their behaviour, for good.*
>
> 3. Clone a pcibios_err_to_errno() into arch/x86/pci/pcbios.c as _v2.
> This handles the positive error codes directly and will not use any
> PCIBIOS* definitions. So calls to it have no outside dependence.
>
> 4. Make all x86 codes that needs to convert to -E* values call the
> cloned version - pcibios_err_to_errno_v2()
>
> 5. Assign PCIBIOS_* errors values directly to generic -E* errors
>
> 6. Refactor pcibios_err_to_errno() and mark it deprecated
>
> 7. Replace all calls to pcibios_err_to_errno() with the proper -E* value
> or 0.
>
> 8. Remove all PCIBIOS* definitions in include/linux/pci.h and
> pcibios_err_to_errno() too.
>
> 9. Redefine all PCIBIOS* definitions with original values inside
> arch/x86/pci/pcbios.c
>
> 10. Redefine pcibios_err_to_errno() inside arch/x86/pci/pcbios.c
>
> 11. Replace pcibios_err_to_errno_v2() calls with pcibios_err_to_errno()
>
> 12. Remove pcibios_err_to_errno_v2()
>
> Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
> Suggested-by: Yicong Yang <yangyicong@hisilicon.com>
> Signed-off-by: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
I would hope that there is a simpler procedure to get to good
code than 12 steps that rename the same things multiple times.
Maybe the work can be split up differently, with a similar end result
but fewer and easier reviewed patches. The way I'd look at the
problem, there are three main areas that can be dealt with one at
a time:
a) callers of the high-level config space accessors
pci_{write,read}_config_{byte,word,dword}, mostly in device
drivers.
b) low-level implementation of the config space accessors
through struct pci_ops
c) all other occurrences of these constants
Starting with a), my first question is whether any high-level drivers
even need to care about errors from these functions. I see 4913
callers that ignore the return code, and 576 that actually
check it, and almost none care about the specific error (as you
found as well). Unless we conclude that most PCI drivers are
wrong, could we just change the return type to 'void' and assume
they never fail for valid arguments on a valid pci_device* ?
For b), it might be nice to also change other aspects of the interface,
e.g. passing a pci_host_bridge pointer plus bus number instead of
a pci_bus pointer, or having the callback in the pci_host_bridge
structure.
> Bolarinwa Olayemi Saheed (35):
> Change PCIBIOS_SUCCESSFUL to 0
> Change PCIBIOS_SUCCESSFUL to 0
> Change PCIBIOS_SUCCESSFUL to 0
> Tidy Success/Failure checks
> Change PCIBIOS_SUCCESSFUL to 0
> Tidy Success/Failure checks
> Change PCIBIOS_SUCCESSFUL to 0
Some patches have identical subject lines including the subsystem
prefix, which you should avoid. Try to also fix the git request-pull
output to not drop that prefix here so the list makes more sense.
Arnd
^ permalink raw reply
* [RFC PATCH 00/35] Move all PCIBIOS* definitions into arch/x86
From: Saheed O. Bolarinwa @ 2020-07-13 12:22 UTC (permalink / raw)
To: helgaas
Cc: Rich Felker, Martin K. Petersen, linux-sh, linux-pci, linux-nvme,
Yicong Yang, Keith Busch, netdev, Paul Mackerras, linux-i2c,
bcm-kernel-feedback-list, sparclinux, rfi, Toan Le, Greg Ungerer,
Marek Vasut, Rob Herring, Stefano Stabellini, Sagi Grimberg,
Yoshinori Sato, linux-scsi, Greg Kroah-Hartman, linux-atm-general,
Russell King, Realtek linux nic maintainers, Christoph Hellwig,
Ley Foon Tan, Geert Uytterhoeven, Rafał Miłecki,
Chas Williams, xen-devel, Matt Turner, linux-mips,
linux-kernel-mentees, Kevin Hilman, Guenter Roeck, linux-hwmon,
Jean Delvare, Andrew Donnellan, Arnd Bergmann, Ray Jui,
James E.J. Bottomley, Yue Wang, Jens Axboe, Jakub Kicinski,
linux-m68k, Lorenzo Pieralisi, Ivan Kokshaysky, Michael Buesch,
skhan, bjorn, linux-amlogic, Boris Ostrovsky, Guan Xuetao,
linux-arm-kernel, Richard Henderson, Juergen Gross, Michal Simek,
Thomas Bogendoerfer, Scott Branden, Bjorn Helgaas, Jingoo Han,
Saheed O. Bolarinwa, Yoshihiro Shimoda, linux-wireless,
linux-kernel, linux-renesas-soc, Brian King, Philipp Zabel,
linux-alpha, Frederic Barrat, Gustavo Pimentel, linuxppc-dev,
David S. Miller, Heiner Kallweit
This goal of these series is to move the definition of *all* PCIBIOS* from
include/linux/pci.h to arch/x86 and limit their use within there.
All other tree specific definition will be left for intact. Maybe they can
be renamed.
PCIBIOS* is an x86 concept as defined by the PCI spec. The returned error
codes of PCIBIOS* are positive values and this introduces some complexities
which other archs need not incur.
PLAN:
1. [PATCH v0 1-36] Replace all PCIBIOS_SUCCESSFUL with 0
2a. Audit all functions returning PCIBIOS_* error values directly or
indirectly and prevent possible bug coming in (2b)
2b. Make all functions returning PCIBIOS_* error values call
pcibios_err_to_errno(). *This will change their behaviour, for good.*
3. Clone a pcibios_err_to_errno() into arch/x86/pci/pcbios.c as _v2.
This handles the positive error codes directly and will not use any
PCIBIOS* definitions. So calls to it have no outside dependence.
4. Make all x86 codes that needs to convert to -E* values call the
cloned version - pcibios_err_to_errno_v2()
5. Assign PCIBIOS_* errors values directly to generic -E* errors
6. Refactor pcibios_err_to_errno() and mark it deprecated
7. Replace all calls to pcibios_err_to_errno() with the proper -E* value
or 0.
8. Remove all PCIBIOS* definitions in include/linux/pci.h and
pcibios_err_to_errno() too.
9. Redefine all PCIBIOS* definitions with original values inside
arch/x86/pci/pcbios.c
10. Redefine pcibios_err_to_errno() inside arch/x86/pci/pcbios.c
11. Replace pcibios_err_to_errno_v2() calls with pcibios_err_to_errno()
12. Remove pcibios_err_to_errno_v2()
Suggested-by: Bjorn Helgaas <bjorn@helgaas.com>
Suggested-by: Yicong Yang <yangyicong@hisilicon.com>
Signed-off-by: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
Bolarinwa Olayemi Saheed (35):
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Fix Style ERROR: assignment in if condition
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
Change PCIBIOS_SUCCESSFUL to 0
Tidy Success/Failure checks
arch/alpha/kernel/core_apecs.c | 4 +--
arch/alpha/kernel/core_cia.c | 4 +--
arch/alpha/kernel/core_irongate.c | 4 +--
arch/alpha/kernel/core_lca.c | 4 +--
arch/alpha/kernel/core_marvel.c | 4 +--
arch/alpha/kernel/core_mcpcia.c | 4 +--
arch/alpha/kernel/core_polaris.c | 4 +--
arch/alpha/kernel/core_t2.c | 4 +--
arch/alpha/kernel/core_titan.c | 4 +--
arch/alpha/kernel/core_tsunami.c | 4 +--
arch/alpha/kernel/core_wildfire.c | 4 +--
arch/alpha/kernel/sys_miata.c | 2 +-
arch/arm/common/it8152.c | 4 +--
arch/arm/mach-cns3xxx/pcie.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 4 +--
arch/arm/mach-iop32x/pci.c | 6 ++--
arch/arm/mach-ixp4xx/common-pci.c | 8 ++---
arch/arm/mach-orion5x/pci.c | 4 +--
arch/arm/plat-orion/pcie.c | 8 ++---
arch/m68k/coldfire/pci.c | 8 ++---
arch/microblaze/pci/indirect_pci.c | 4 +--
arch/mips/pci/fixup-ath79.c | 2 +-
arch/mips/pci/ops-bcm63xx.c | 14 ++++----
arch/mips/pci/ops-bonito64.c | 4 +--
arch/mips/pci/ops-gt64xxx_pci0.c | 4 +--
arch/mips/pci/ops-lantiq.c | 4 +--
arch/mips/pci/ops-loongson2.c | 4 +--
arch/mips/pci/ops-mace.c | 4 +--
arch/mips/pci/ops-msc.c | 4 +--
arch/mips/pci/ops-rc32434.c | 6 ++--
arch/mips/pci/ops-sni.c | 4 +--
arch/mips/pci/ops-tx3927.c | 2 +-
arch/mips/pci/ops-tx4927.c | 2 +-
arch/mips/pci/ops-vr41xx.c | 4 +--
arch/mips/pci/pci-alchemy.c | 6 ++--
arch/mips/pci/pci-ar2315.c | 5 ++-
arch/mips/pci/pci-ar71xx.c | 4 +--
arch/mips/pci/pci-ar724x.c | 6 ++--
arch/mips/pci/pci-bcm1480.c | 4 +--
arch/mips/pci/pci-bcm1480ht.c | 4 +--
arch/mips/pci/pci-mt7620.c | 4 +--
arch/mips/pci/pci-octeon.c | 12 +++----
arch/mips/pci/pci-rt2880.c | 4 +--
arch/mips/pci/pci-rt3883.c | 4 +--
arch/mips/pci/pci-sb1250.c | 4 +--
arch/mips/pci/pci-virtio-guest.c | 4 +--
arch/mips/pci/pci-xlp.c | 4 +--
arch/mips/pci/pci-xlr.c | 4 +--
arch/mips/pci/pci-xtalk-bridge.c | 14 ++++----
arch/mips/pci/pcie-octeon.c | 4 +--
arch/mips/txx9/generic/pci.c | 5 ++-
arch/powerpc/kernel/rtas_pci.c | 4 +--
arch/powerpc/platforms/4xx/pci.c | 4 +--
arch/powerpc/platforms/52xx/efika.c | 4 +--
arch/powerpc/platforms/52xx/mpc52xx_pci.c | 4 +--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 2 +-
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 2 +-
arch/powerpc/platforms/chrp/pci.c | 8 ++---
arch/powerpc/platforms/embedded6xx/holly.c | 2 +-
.../platforms/embedded6xx/mpc7448_hpc2.c | 2 +-
arch/powerpc/platforms/fsl_uli1575.c | 2 +-
arch/powerpc/platforms/maple/pci.c | 18 +++++-----
arch/powerpc/platforms/pasemi/pci.c | 6 ++--
arch/powerpc/platforms/powermac/pci.c | 8 ++---
arch/powerpc/platforms/powernv/eeh-powernv.c | 4 +--
arch/powerpc/platforms/powernv/pci.c | 4 +--
arch/powerpc/platforms/pseries/eeh_pseries.c | 4 +--
arch/powerpc/sysdev/fsl_pci.c | 2 +-
arch/powerpc/sysdev/indirect_pci.c | 4 +--
arch/powerpc/sysdev/tsi108_pci.c | 4 +--
arch/sh/drivers/pci/common.c | 3 +-
arch/sh/drivers/pci/ops-dreamcast.c | 4 +--
arch/sh/drivers/pci/ops-sh4.c | 4 +--
arch/sh/drivers/pci/ops-sh7786.c | 8 ++---
arch/sh/drivers/pci/pci.c | 2 +-
arch/sparc/kernel/pci_common.c | 28 +++++++--------
arch/unicore32/kernel/pci.c | 4 +--
drivers/atm/iphase.c | 20 ++++++-----
drivers/atm/lanai.c | 8 ++---
drivers/bcma/driver_pci_host.c | 4 +--
drivers/hwmon/sis5595.c | 13 +++----
drivers/hwmon/via686a.c | 13 +++----
drivers/hwmon/vt8231.c | 13 +++----
drivers/i2c/busses/i2c-ali15x3.c | 5 ++-
drivers/i2c/busses/i2c-nforce2.c | 3 +-
drivers/i2c/busses/i2c-sis5595.c | 15 +++-----
drivers/misc/cxl/vphb.c | 4 +--
drivers/net/ethernet/realtek/r8169_main.c | 2 +-
drivers/nvme/host/pci.c | 2 +-
drivers/pci/access.c | 14 ++++----
drivers/pci/controller/dwc/pci-meson.c | 4 +--
.../pci/controller/dwc/pcie-designware-host.c | 2 +-
drivers/pci/controller/dwc/pcie-designware.c | 4 +--
drivers/pci/controller/dwc/pcie-hisi.c | 4 +--
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +--
.../pci/controller/mobiveil/pcie-mobiveil.c | 4 +--
drivers/pci/controller/pci-aardvark.c | 4 +--
drivers/pci/controller/pci-ftpci100.c | 4 +--
drivers/pci/controller/pci-hyperv.c | 8 ++---
drivers/pci/controller/pci-mvebu.c | 4 +--
drivers/pci/controller/pci-thunder-ecam.c | 36 +++++++++----------
drivers/pci/controller/pci-thunder-pem.c | 4 +--
drivers/pci/controller/pci-xgene.c | 5 ++-
drivers/pci/controller/pcie-altera.c | 16 ++++-----
drivers/pci/controller/pcie-iproc.c | 10 +++---
drivers/pci/controller/pcie-mediatek.c | 4 +--
drivers/pci/controller/pcie-rcar-host.c | 8 ++---
drivers/pci/controller/pcie-rockchip-host.c | 10 +++---
drivers/pci/pci-bridge-emul.c | 14 ++++----
drivers/pci/pci.c | 8 ++---
drivers/pci/pcie/bw_notification.c | 4 +--
drivers/pci/probe.c | 4 +--
drivers/pci/quirks.c | 4 +--
drivers/pci/syscall.c | 8 ++---
drivers/pci/xen-pcifront.c | 2 +-
drivers/scsi/ipr.c | 16 ++++-----
drivers/scsi/pmcraid.c | 6 ++--
drivers/ssb/driver_gige.c | 4 +--
drivers/ssb/driver_pcicore.c | 4 +--
drivers/xen/xen-pciback/conf_space.c | 2 +-
122 files changed, 347 insertions(+), 369 deletions(-)
--
2.18.2
^ permalink raw reply
* [PATCH 2/2] powerpc/kvm/cma: Improve kernel log during boot
From: Aneesh Kumar K.V @ 2020-07-13 15:07 UTC (permalink / raw)
To: linuxppc-dev, mpe; +Cc: Aneesh Kumar K.V
In-Reply-To: <20200713150749.25245-1-aneesh.kumar@linux.ibm.com>
Current kernel gives:
[ 0.000000] cma: Reserved 26224 MiB at 0x0000007959000000
[ 0.000000] hugetlb_cma: reserve 65536 MiB, up to 16384 MiB per node
[ 0.000000] cma: Reserved 16384 MiB at 0x0000001800000000
With the fix
[ 0.000000] kvm_cma_reserve: reserving 26214 MiB for global area
[ 0.000000] cma: Reserved 26224 MiB at 0x0000007959000000
[ 0.000000] hugetlb_cma: reserve 65536 MiB, up to 16384 MiB per node
[ 0.000000] cma: Reserved 16384 MiB at 0x0000001800000000
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/kvm/book3s_hv_builtin.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index 7cd3cf3d366b..073617ce83e0 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -113,7 +113,7 @@ void __init kvm_cma_reserve(void)
selected_size = (selected_size * kvm_cma_resv_ratio / 100) << PAGE_SHIFT;
if (selected_size) {
- pr_debug("%s: reserving %ld MiB for global area\n", __func__,
+ pr_info("%s: reserving %ld MiB for global area\n", __func__,
(unsigned long)selected_size / SZ_1M);
align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
cma_declare_contiguous(0, selected_size, 0, align_size,
--
2.26.2
^ permalink raw reply related
* [PATCH 1/2] powerpc/hugetlb/cma: Allocate gigantic hugetlb pages using CMA
From: Aneesh Kumar K.V @ 2020-07-13 15:07 UTC (permalink / raw)
To: linuxppc-dev, mpe; +Cc: Aneesh Kumar K.V
commit: cf11e85fc08c ("mm: hugetlb: optionally allocate gigantic hugepages using cma")
added support for allocating gigantic hugepages using CMA. This patch
enables the same for powerpc
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
---
arch/powerpc/include/asm/hugetlb.h | 7 +++++++
arch/powerpc/kernel/setup-common.c | 3 +++
arch/powerpc/mm/hugetlbpage.c | 18 ++++++++++++++++++
3 files changed, 28 insertions(+)
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index 551a9d4d3958..013165e62618 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -57,6 +57,7 @@ int huge_ptep_set_access_flags(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep,
pte_t pte, int dirty);
+void gigantic_hugetlb_cma_reserve(void) __init;
#include <asm-generic/hugetlb.h>
#else /* ! CONFIG_HUGETLB_PAGE */
@@ -71,6 +72,12 @@ static inline pte_t *hugepte_offset(hugepd_t hpd, unsigned long addr,
{
return NULL;
}
+
+
+static inline void __init gigantic_hugetlb_cma_reserve(void)
+{
+}
+
#endif /* CONFIG_HUGETLB_PAGE */
#endif /* _ASM_POWERPC_HUGETLB_H */
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index 9d3faac53295..b198b0ff25bc 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -928,6 +928,9 @@ void __init setup_arch(char **cmdline_p)
/* Reserve large chunks of memory for use by CMA for KVM. */
kvm_cma_reserve();
+ /* Reserve large chunks of memory for us by CMA for hugetlb */
+ gigantic_hugetlb_cma_reserve();
+
klp_init_thread_info(&init_task);
init_mm.start_code = (unsigned long)_stext;
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index e9bfbccd975d..26292544630f 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -684,3 +684,21 @@ void flush_dcache_icache_hugepage(struct page *page)
}
}
}
+
+void __init gigantic_hugetlb_cma_reserve(void)
+{
+ unsigned long order = 0;
+
+ if (radix_enabled())
+ order = PUD_SHIFT - PAGE_SHIFT;
+ else if (!firmware_has_feature(FW_FEATURE_LPAR) && mmu_psize_defs[MMU_PAGE_16G].shift)
+ /*
+ * For pseries we do use ibm,expected#pages for reserving 16G pages.
+ */
+ order = mmu_psize_to_shift(MMU_PAGE_16G) - PAGE_SHIFT;
+
+ if (order) {
+ VM_WARN_ON(order < MAX_ORDER);
+ hugetlb_cma_reserve(order);
+ }
+}
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v5] ima: move APPRAISE_BOOTPARAM dependency on ARCH_POLICY to runtime
From: Bruno Meneguele @ 2020-07-13 15:03 UTC (permalink / raw)
To: Mimi Zohar
Cc: linux-s390, nayna, erichte, x86, linux-kernel, stable,
linux-integrity, linuxppc-dev
In-Reply-To: <20200710192516.GC10547@glitch>
[-- Attachment #1: Type: text/plain, Size: 5872 bytes --]
On Fri, Jul 10, 2020 at 04:25:16PM -0300, Bruno Meneguele wrote:
> On Fri, Jul 10, 2020 at 02:54:48PM -0400, Mimi Zohar wrote:
> > On Fri, 2020-07-10 at 15:34 -0300, Bruno Meneguele wrote:
> > > On Fri, Jul 10, 2020 at 03:03:38PM -0300, Bruno Meneguele wrote:
> > > > On Fri, Jul 10, 2020 at 01:23:24PM -0400, Mimi Zohar wrote:
> > > > > On Thu, 2020-07-09 at 13:46 -0300, Bruno Meneguele wrote:
> > > > > > APPRAISE_BOOTPARAM has been marked as dependent on !ARCH_POLICY in compile
> > > > > > time, enforcing the appraisal whenever the kernel had the arch policy option
> > > > > > enabled.
> > > > >
> > > > > > However it breaks systems where the option is set but the system didn't
> > > > > > boot in a "secure boot" platform. In this scenario, anytime an appraisal
> > > > > > policy (i.e. ima_policy=appraisal_tcb) is used it will be forced, without
> > > > > > giving the user the opportunity to label the filesystem, before enforcing
> > > > > > integrity.
> > > > > >
> > > > > > Considering the ARCH_POLICY is only effective when secure boot is actually
> > > > > > enabled this patch remove the compile time dependency and move it to a
> > > > > > runtime decision, based on the secure boot state of that platform.
> > > > >
> > > > > Perhaps we could simplify this patch description a bit?
> > > > >
> > > > > The IMA_APPRAISE_BOOTPARAM config allows enabling different
> > > > > "ima_appraise=" modes - log, fix, enforce - at run time, but not when
> > > > > IMA architecture specific policies are enabled. This prevents
> > > > > properly labeling the filesystem on systems where secure boot is
> > > > > supported, but not enabled on the platform. Only when secure boot is
> > > > > enabled, should these IMA appraise modes be disabled.
> > > > >
> > > > > This patch removes the compile time dependency and makes it a runtime
> > > > > decision, based on the secure boot state of that platform.
> > > > >
> > > >
> > > > Sounds good to me.
> > > >
> > > > > <snip>
> > > > >
> > > > > > diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
> > > > > > index a9649b04b9f1..884de471b38a 100644
> > > > > > --- a/security/integrity/ima/ima_appraise.c
> > > > > > +++ b/security/integrity/ima/ima_appraise.c
> > > > > > @@ -19,6 +19,11 @@
> > > > > > static int __init default_appraise_setup(c
> > > > >
> > > > > > har *str)
> > > > > > {
> > > > > > #ifdef CONFIG_IMA_APPRAISE_BOOTPARAM
> > > > > > + if (arch_ima_get_secureboot()) {
> > > > > > + pr_info("appraise boot param ignored: secure boot enabled");
> > > > >
> > > > > Instead of a generic statement, is it possible to include the actual
> > > > > option being denied? Perhaps something like: "Secure boot enabled,
> > > > > ignoring %s boot command line option"
> > > > >
> > > > > Mimi
> > > > >
> > > >
> > > > Yes, sure.
> > > >
> > >
> > > Btw, would it make sense to first make sure we have a valid "str"
> > > option and not something random to print?
> > >
> > > diff --git a/security/integrity/ima/ima_appraise.c b/security/integrity/ima/ima_appraise.c
> > > index a9649b04b9f1..1f1175531d3e 100644
> > > --- a/security/integrity/ima/ima_appraise.c
> > > +++ b/security/integrity/ima/ima_appraise.c
> > > @@ -25,6 +25,16 @@ static int __init default_appraise_setup(char *str)
> > > ima_appraise = IMA_APPRAISE_LOG;
> > > else if (strncmp(str, "fix", 3) == 0)
> > > ima_appraise = IMA_APPRAISE_FIX;
> > > + else
> > > + pr_info("invalid \"%s\" appraise option");
> > > +
> > > + if (arch_ima_get_secureboot()) {
> > > + if (!is_ima_appraise_enabled()) {
> > > + pr_info("Secure boot enabled: ignoring ima_appraise=%s boot parameter option",
> > > + str);
> > > + ima_appraise = IMA_APPRAISE_ENFORCE;
> > > + }
> > > + }
> >
> > Providing feedback is probably a good idea. However, the
> > "arch_ima_get_secureboot" test can't come after setting
> > "ima_appraise."
> >
>
> Sorry, but I'm not sure if I got the reason to why it can't be done
> after: would it be basically to prevent any further processing about
> ima_appraise as a matter of security principle? Or maybe to keep the
> dependency between secureboot and bootparam truly strict?
>
> Or are there something else I'm missing?
>
I'm going to send a v6 with the pr_info() placed in the beginning
directly printing 'str', thus we can have the actual issue solved.
Then later I send another patches to handle the other cases of limiting
'str' printing and also giving the user a feedback about invalid
ima_appraise= options. So we can discuss further on that.
Thanks Mimi.
> > Mimi
> >
> > > #endif
> > > return 1;
> > > }
> > >
> > >
> > > The "else" there I think would make sense as well, at least to give the
> > > user some feedback about a possible mispelling of him (as a separate
> > > patch).
> > >
> > > And "if(!is_ima_appraise_enabled())" would avoid to print anything about
> > > "ignoring the option" to the user in case he explicitly set "enforce",
> > > which we know there isn't any real effect but is allowed and shown in
> > > kernel-parameters.txt.
> > >
> > > > Thanks!
> > > >
> > > > > > + return 1;
> > > > > > + }
> > > > > > +
> > > > > > if (strncmp(str, "off", 3) == 0)
> > > > > > ima_appraise = 0;
> > > > > > else if (strncmp(str, "log", 3) == 0)
> > > > >
> > > >
> > > > --
> > > > bmeneg
> > > > PGP Key: http://bmeneg.com/pubkey.txt
> > >
> > >
> > >
> >
>
> --
> bmeneg
> PGP Key: http://bmeneg.com/pubkey.txt
--
bmeneg
PGP Key: http://bmeneg.com/pubkey.txt
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v2] powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc
From: Madhavan Srinivasan @ 2020-07-13 14:46 UTC (permalink / raw)
To: mpe; +Cc: Anju T Sudhakar, linuxppc-dev, Madhavan Srinivasan
From: Anju T Sudhakar <anju@linux.vnet.ibm.com>
IMC trace-mode record has MSR[HV PR] bits added in the third DW.
These bits can be used to set the cpumode for the instruction pointer
captured in each sample.
Add support in kernel to use these bits to set the cpumode for
each sample.
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
Changelog v1:
- Changed check to use CPU_FTR_ARCH_31
arch/powerpc/include/asm/imc-pmu.h | 5 +++++
arch/powerpc/perf/imc-pmu.c | 29 ++++++++++++++++++++++++-----
2 files changed, 29 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h
index 4da4fcba0684..4f897993b710 100644
--- a/arch/powerpc/include/asm/imc-pmu.h
+++ b/arch/powerpc/include/asm/imc-pmu.h
@@ -99,6 +99,11 @@ struct trace_imc_data {
*/
#define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL
+/*
+ * Bit 0:1 in third DW of IMC trace record
+ * specifies the MSR[HV PR] values.
+ */
+#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62)
/*
* Device tree parser code detects IMC pmu support and
diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
index 0edcfd0b491d..a45d694a5d5d 100644
--- a/arch/powerpc/perf/imc-pmu.c
+++ b/arch/powerpc/perf/imc-pmu.c
@@ -1288,11 +1288,30 @@ static int trace_imc_prepare_sample(struct trace_imc_data *mem,
header->size = sizeof(*header) + event->header_size;
header->misc = 0;
- if (is_kernel_addr(data->ip))
- header->misc |= PERF_RECORD_MISC_KERNEL;
- else
- header->misc |= PERF_RECORD_MISC_USER;
-
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ switch (IMC_TRACE_RECORD_VAL_HVPR(mem->val)) {
+ case 0:/* when MSR HV and PR not set in the trace-record */
+ header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
+ break;
+ case 1: /* MSR HV is 0 and PR is 1 */
+ header->misc |= PERF_RECORD_MISC_GUEST_USER;
+ break;
+ case 2: /* MSR HV is 1 and PR is 0 */
+ header->misc |= PERF_RECORD_MISC_HYPERVISOR;
+ break;
+ case 3: /* MSR HV is 1 and PR is 1 */
+ header->misc |= PERF_RECORD_MISC_USER;
+ break;
+ default:
+ pr_info("IMC: Unable to set the flag based on MSR bits\n");
+ break;
+ }
+ } else {
+ if (is_kernel_addr(data->ip))
+ header->misc |= PERF_RECORD_MISC_KERNEL;
+ else
+ header->misc |= PERF_RECORD_MISC_USER;
+ }
perf_event_header__init_id(header, data, event);
return 0;
--
2.26.2
^ permalink raw reply related
* Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode
From: Mathieu Desnoyers @ 2020-07-13 14:13 UTC (permalink / raw)
To: Nicholas Piggin
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, x86, linux-kernel,
linux-mm, Andy Lutomirski, linuxppc-dev
In-Reply-To: <1594647408.wmrazhwjzb.astroid@bobo.none>
----- On Jul 13, 2020, at 9:47 AM, Nicholas Piggin npiggin@gmail.com wrote:
> Excerpts from Nicholas Piggin's message of July 13, 2020 2:45 pm:
>> Excerpts from Andy Lutomirski's message of July 11, 2020 3:04 am:
>>> Also, as it stands, I can easily see in_irq() ceasing to promise to
>>> serialize. There are older kernels for which it does not promise to
>>> serialize. And I have plans to make it stop serializing in the
>>> nearish future.
>>
>> You mean x86's return from interrupt? Sounds fun... you'll konw where to
>> update the membarrier sync code, at least :)
>
> Oh, I should actually say Mathieu recently clarified a return from
> interrupt doesn't fundamentally need to serialize in order to support
> membarrier sync core.
Clarification to your statement:
Return from interrupt to kernel code does not need to be context serializing
as long as kernel serializes before returning to user-space.
However, return from interrupt to user-space needs to be context serializing.
Thanks,
Mathieu
>
> https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-July/214171.html
>
> So you may not need to do anything more if you relaxed it.
>
> Thanks,
> Nick
--
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com
^ permalink raw reply
* Re: [RFC PATCH 4/7] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode
From: Nicholas Piggin @ 2020-07-13 13:47 UTC (permalink / raw)
To: Andy Lutomirski
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, X86 ML, LKML, Linux-MM,
Mathieu Desnoyers, linuxppc-dev
In-Reply-To: <1594613902.1wzayj0p15.astroid@bobo.none>
Excerpts from Nicholas Piggin's message of July 13, 2020 2:45 pm:
> Excerpts from Andy Lutomirski's message of July 11, 2020 3:04 am:
>> Also, as it stands, I can easily see in_irq() ceasing to promise to
>> serialize. There are older kernels for which it does not promise to
>> serialize. And I have plans to make it stop serializing in the
>> nearish future.
>
> You mean x86's return from interrupt? Sounds fun... you'll konw where to
> update the membarrier sync code, at least :)
Oh, I should actually say Mathieu recently clarified a return from
interrupt doesn't fundamentally need to serialize in order to support
membarrier sync core.
https://lists.ozlabs.org/pipermail/linuxppc-dev/2020-July/214171.html
So you may not need to do anything more if you relaxed it.
Thanks,
Nick
^ permalink raw reply
* [RFC PATCH 27/35] powerpc: Tidy Success/Failure checks
From: Saheed O. Bolarinwa @ 2020-07-13 12:22 UTC (permalink / raw)
To: helgaas, Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras
Cc: linuxppc-dev, Saheed O. Bolarinwa, skhan, linux-kernel, linux-pci,
bjorn, linux-kernel-mentees
In-Reply-To: <20200713122247.10985-1-refactormyself@gmail.com>
Remove unnecessary check for 0.
Signed-off-by: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
---
This patch depends on PATCH 26/35
arch/powerpc/platforms/powernv/eeh-powernv.c | 4 ++--
arch/powerpc/platforms/pseries/eeh_pseries.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 92f145dc9c1d..834cb6175cc4 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -318,7 +318,7 @@ static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (!edev || !edev->pcie_cap)
return 0;
- if (pnv_pci_cfg_read(pdn, pos, 4, &header) != 0)
+ if (pnv_pci_cfg_read(pdn, pos, 4, &header))
return 0;
else if (!header)
return 0;
@@ -331,7 +331,7 @@ static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (pos < 256)
break;
- if (pnv_pci_cfg_read(pdn, pos, 4, &header) != 0)
+ if (pnv_pci_cfg_read(pdn, pos, 4, &header))
break;
}
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 9c023b928f2c..aec6f76879a9 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -200,7 +200,7 @@ static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (!edev || !edev->pcie_cap)
return 0;
- if (rtas_read_config(pdn, pos, 4, &header) != 0)
+ if (rtas_read_config(pdn, pos, 4, &header))
return 0;
else if (!header)
return 0;
@@ -213,7 +213,7 @@ static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (pos < 256)
break;
- if (rtas_read_config(pdn, pos, 4, &header) != 0)
+ if (rtas_read_config(pdn, pos, 4, &header))
break;
}
--
2.18.2
^ permalink raw reply related
* [RFC PATCH 26/35] powerpc: Change PCIBIOS_SUCCESSFUL to 0
From: Saheed O. Bolarinwa @ 2020-07-13 12:22 UTC (permalink / raw)
To: helgaas, Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras
Cc: linuxppc-dev, Saheed O. Bolarinwa, skhan, linux-kernel, linux-pci,
bjorn, linux-kernel-mentees
In-Reply-To: <20200713122247.10985-1-refactormyself@gmail.com>
In reference to the PCI spec (Chapter 2), PCIBIOS* is an x86 concept.
Their scope should be limited within arch/x86.
Change all PCIBIOS_SUCCESSFUL to 0
Signed-off-by: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
---
arch/powerpc/kernel/rtas_pci.c | 4 ++--
arch/powerpc/platforms/4xx/pci.c | 4 ++--
arch/powerpc/platforms/52xx/efika.c | 4 ++--
arch/powerpc/platforms/52xx/mpc52xx_pci.c | 4 ++--
arch/powerpc/platforms/82xx/pq2.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 2 +-
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 2 +-
arch/powerpc/platforms/chrp/pci.c | 8 ++++----
arch/powerpc/platforms/embedded6xx/holly.c | 2 +-
.../platforms/embedded6xx/mpc7448_hpc2.c | 2 +-
arch/powerpc/platforms/fsl_uli1575.c | 2 +-
arch/powerpc/platforms/maple/pci.c | 18 +++++++++---------
arch/powerpc/platforms/pasemi/pci.c | 6 +++---
arch/powerpc/platforms/powermac/pci.c | 8 ++++----
arch/powerpc/platforms/powernv/eeh-powernv.c | 4 ++--
arch/powerpc/platforms/powernv/pci.c | 4 ++--
arch/powerpc/platforms/pseries/eeh_pseries.c | 4 ++--
arch/powerpc/sysdev/fsl_pci.c | 2 +-
arch/powerpc/sysdev/indirect_pci.c | 4 ++--
arch/powerpc/sysdev/tsi108_pci.c | 4 ++--
21 files changed, 46 insertions(+), 46 deletions(-)
diff --git a/arch/powerpc/kernel/rtas_pci.c b/arch/powerpc/kernel/rtas_pci.c
index 781c1869902e..18108ed9284c 100644
--- a/arch/powerpc/kernel/rtas_pci.c
+++ b/arch/powerpc/kernel/rtas_pci.c
@@ -71,7 +71,7 @@ int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
if (ret)
return PCIBIOS_DEVICE_NOT_FOUND;
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int rtas_pci_read_config(struct pci_bus *bus,
@@ -121,7 +121,7 @@ int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
if (ret)
return PCIBIOS_DEVICE_NOT_FOUND;
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int rtas_pci_write_config(struct pci_bus *bus,
diff --git a/arch/powerpc/platforms/4xx/pci.c b/arch/powerpc/platforms/4xx/pci.c
index c13d64c3b019..3e6799d987d2 100644
--- a/arch/powerpc/platforms/4xx/pci.c
+++ b/arch/powerpc/platforms/4xx/pci.c
@@ -1652,7 +1652,7 @@ static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -1696,7 +1696,7 @@ static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops ppc4xx_pciex_pci_ops =
diff --git a/arch/powerpc/platforms/52xx/efika.c b/arch/powerpc/platforms/52xx/efika.c
index 4514a6f7458a..ef2584eb2dad 100644
--- a/arch/powerpc/platforms/52xx/efika.c
+++ b/arch/powerpc/platforms/52xx/efika.c
@@ -44,7 +44,7 @@ static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
*val = ret;
- return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : 0;
}
static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -58,7 +58,7 @@ static int rtas_write_config(struct pci_bus *bus, unsigned int devfn,
rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
addr, len, val);
- return rval ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : 0;
}
static struct pci_ops rtas_pci_ops = {
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pci.c b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
index af0f79995214..b9c2d0a7077e 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pci.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pci.c
@@ -157,7 +157,7 @@ mpc52xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
out_be32(hose->cfg_addr, 0);
mb();
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int
@@ -221,7 +221,7 @@ mpc52xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
out_be32(hose->cfg_addr, 0);
mb();
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops mpc52xx_pci_ops = {
diff --git a/arch/powerpc/platforms/82xx/pq2.c b/arch/powerpc/platforms/82xx/pq2.c
index 3b5cb39a564c..c15b3b0ed118 100644
--- a/arch/powerpc/platforms/82xx/pq2.c
+++ b/arch/powerpc/platforms/82xx/pq2.c
@@ -40,7 +40,7 @@ static int pq2_pci_exclude_device(struct pci_controller *hose,
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
else
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static void __init pq2_pci_add_bridge(struct device_node *np)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 172d2b7cfeb7..66f00eb2a8be 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -76,7 +76,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
return PCIBIOS_DEVICE_NOT_FOUND;
else
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int mpc85xx_cds_restart(struct notifier_block *this,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 2157a8017aa4..f33ac8e04da6 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -118,7 +118,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
if (hose->dn == pci_with_uli)
return uli_exclude_device(hose, bus, devfn);
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index b697918b727d..36b38b28d40b 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -49,7 +49,7 @@ static int mpc86xx_exclude_device(struct pci_controller *hose,
if (hose->dn == fsl_pci_primary)
return uli_exclude_device(hose, bus, devfn);
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/platforms/chrp/pci.c b/arch/powerpc/platforms/chrp/pci.c
index b2c2bf35b76c..c8f8356607c7 100644
--- a/arch/powerpc/platforms/chrp/pci.c
+++ b/arch/powerpc/platforms/chrp/pci.c
@@ -55,7 +55,7 @@ static int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
*val = in_le32(cfg_data);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
@@ -82,7 +82,7 @@ static int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
out_le32(cfg_data, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops gg2_pci_ops =
@@ -106,7 +106,7 @@ static int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
*val = ret;
- return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : 0;
}
static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
@@ -120,7 +120,7 @@ static int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset
rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
addr, len, val);
- return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
+ return rval ? PCIBIOS_DEVICE_NOT_FOUND : 0;
}
static struct pci_ops rtas_pci_ops =
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index d8f2e2c737bb..f9fca540c52a 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -47,7 +47,7 @@ static int holly_exclude_device(struct pci_controller *hose, u_char bus,
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
else
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static void holly_remap_bridge(void)
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 15437abe1f6d..34f6a0ecdf67 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -55,7 +55,7 @@ int mpc7448_hpc2_exclude_device(struct pci_controller *hose,
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
else
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static void __init mpc7448_hpc2_setup_arch(void)
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index 044a20c1fbde..17c2cb5a8682 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -353,5 +353,5 @@ int uli_exclude_device(struct pci_controller *hose,
return PCIBIOS_DEVICE_NOT_FOUND;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index c86a66d5e998..4e49f465056d 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -142,7 +142,7 @@ static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
*val = in_le32(addr);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -173,7 +173,7 @@ static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
out_le32(addr, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops u3_agp_pci_ops =
@@ -223,7 +223,7 @@ static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
@@ -234,7 +234,7 @@ static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
- return PCIBIOS_SUCCESSFUL;
+ return 0;
switch (len) {
case 1:
@@ -248,7 +248,7 @@ static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -286,7 +286,7 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
*val = in_le32(addr);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -323,7 +323,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
out_le32(addr, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops u3_ht_pci_ops =
@@ -397,7 +397,7 @@ static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
*val = in_le32(addr);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
int offset, int len, u32 val)
@@ -428,7 +428,7 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
out_le32(addr, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops u4_pcie_pci_ops =
diff --git a/arch/powerpc/platforms/pasemi/pci.c b/arch/powerpc/platforms/pasemi/pci.c
index 8779b107d872..e558a402532a 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch/powerpc/platforms/pasemi/pci.c
@@ -166,7 +166,7 @@ static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
return PCIBIOS_BAD_REGISTER_NUMBER;
if (workaround_5945(bus, devfn, offset, len, val))
- return PCIBIOS_SUCCESSFUL;
+ return 0;
addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset);
@@ -188,7 +188,7 @@ static int pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn,
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -223,7 +223,7 @@ static int pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn,
out_le32(addr, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops pa_pxp_ops = {
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index e35eaa9cf938..bdc9a89b5181 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -307,7 +307,7 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
default:
*val = 0xfffffffful; break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
default:
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -327,7 +327,7 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
*val = swap ? in_le32(addr) : in_be32(addr);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -350,7 +350,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
case 0:
break;
case 1:
- return PCIBIOS_SUCCESSFUL;
+ return 0;
default:
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -370,7 +370,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
swap ? out_le32(addr, val) : out_be32(addr, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops u3_ht_pci_ops =
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 79409e005fcd..92f145dc9c1d 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -318,7 +318,7 @@ static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (!edev || !edev->pcie_cap)
return 0;
- if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+ if (pnv_pci_cfg_read(pdn, pos, 4, &header) != 0)
return 0;
else if (!header)
return 0;
@@ -331,7 +331,7 @@ static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (pos < 256)
break;
- if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+ if (pnv_pci_cfg_read(pdn, pos, 4, &header) != 0)
break;
}
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 091fe1cf386b..b3d5cc3e262a 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -685,7 +685,7 @@ int pnv_pci_cfg_read(struct pci_dn *pdn,
pr_devel("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
__func__, pdn->busno, pdn->devfn, where, size, *val);
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
int pnv_pci_cfg_write(struct pci_dn *pdn,
@@ -710,7 +710,7 @@ int pnv_pci_cfg_write(struct pci_dn *pdn,
return PCIBIOS_FUNC_NOT_SUPPORTED;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
#if CONFIG_EEH
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index ace117f99d94..9c023b928f2c 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -200,7 +200,7 @@ static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (!edev || !edev->pcie_cap)
return 0;
- if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+ if (rtas_read_config(pdn, pos, 4, &header) != 0)
return 0;
else if (!header)
return 0;
@@ -213,7 +213,7 @@ static int pseries_eeh_find_ecap(struct pci_dn *pdn, int cap)
if (pos < 256)
break;
- if (rtas_read_config(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
+ if (rtas_read_config(pdn, pos, 4, &header) != 0)
break;
}
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 040b9d01c079..f1118c4443f4 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -697,7 +697,7 @@ static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
return PCIBIOS_DEVICE_NOT_FOUND;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 09b36617425e..35b21276609b 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -70,7 +70,7 @@ int __indirect_read_config(struct pci_controller *hose,
*val = in_le32(cfg_data);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
@@ -148,7 +148,7 @@ int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
out_le32(cfg_data, val);
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
static struct pci_ops indirect_pci_ops =
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 49f9541954f8..586dabb4e7ea 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -78,7 +78,7 @@ tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfunc,
break;
}
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
void tsi108_clear_pci_error(u32 pci_cfg_base)
@@ -167,7 +167,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
printk("data = 0x%x\n", *val);
}
#endif
- return PCIBIOS_SUCCESSFUL;
+ return 0;
}
void tsi108_clear_pci_cfg_error(void)
--
2.18.2
^ permalink raw reply related
* [RFC PATCH 13/35] cxl: Change PCIBIOS_SUCCESSFUL to 0
From: Saheed O. Bolarinwa @ 2020-07-13 12:22 UTC (permalink / raw)
To: helgaas, Frederic Barrat, Andrew Donnellan, Arnd Bergmann,
Greg Kroah-Hartman
Cc: linuxppc-dev, Saheed O. Bolarinwa, skhan, linux-kernel, linux-pci,
bjorn, linux-kernel-mentees
In-Reply-To: <20200713122247.10985-1-refactormyself@gmail.com>
In reference to the PCI spec (Chapter 2), PCIBIOS* is an x86 concept.
There scope should be limited within arch/x86.
Change all PCIBIOS_SUCCESSFUL to 0
Signed-off-by: "Saheed O. Bolarinwa" <refactormyself@gmail.com>
---
drivers/misc/cxl/vphb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/vphb.c b/drivers/misc/cxl/vphb.c
index 1cf320e2a415..1264253cc07b 100644
--- a/drivers/misc/cxl/vphb.c
+++ b/drivers/misc/cxl/vphb.c
@@ -150,7 +150,7 @@ static int cxl_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
out:
cxl_afu_configured_put(afu);
- return rc ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
+ return rc ? PCIBIOS_DEVICE_NOT_FOUND : 0;
}
static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
@@ -184,7 +184,7 @@ static int cxl_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
out:
cxl_afu_configured_put(afu);
- return rc ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
+ return rc ? PCIBIOS_SET_FAILED : 0;
}
static struct pci_ops cxl_pcie_pci_ops =
--
2.18.2
^ permalink raw reply related
* Re: [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs
From: Michael Ellerman @ 2020-07-13 12:50 UTC (permalink / raw)
To: Athira Rajeev; +Cc: Michael Neuling, maddy, linuxppc-dev
In-Reply-To: <DF000FF6-EF09-4299-A4AD-EF76277A6EF4@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes:
>> On 08-Jul-2020, at 4:32 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
>>
>> Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes:
>> ...
>>> diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
>>> index cd6a742..5c64bd3 100644
>>> --- a/arch/powerpc/perf/core-book3s.c
>>> +++ b/arch/powerpc/perf/core-book3s.c
>>> @@ -39,10 +39,10 @@ struct cpu_hw_events {
>>> unsigned int flags[MAX_HWEVENTS];
>>> /*
>>> * The order of the MMCR array is:
>>> - * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
>>> + * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2, MMCR3
>>> * - 32-bit, MMCR0, MMCR1, MMCR2
>>> */
>>> - unsigned long mmcr[4];
>>> + unsigned long mmcr[5];
>>> struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
>>> u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
>>> u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
>> ...
>>> @@ -1310,6 +1326,10 @@ static void power_pmu_enable(struct pmu *pmu)
>>> if (!cpuhw->n_added) {
>>> mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
>>> mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
>>> +#ifdef CONFIG_PPC64
>>> + if (ppmu->flags & PPMU_ARCH_310S)
>>> + mtspr(SPRN_MMCR3, cpuhw->mmcr[4]);
>>> +#endif /* CONFIG_PPC64 */
>>> goto out_enable;
>>> }
>>>
>>> @@ -1353,6 +1373,11 @@ static void power_pmu_enable(struct pmu *pmu)
>>> if (ppmu->flags & PPMU_ARCH_207S)
>>> mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
>>>
>>> +#ifdef CONFIG_PPC64
>>> + if (ppmu->flags & PPMU_ARCH_310S)
>>> + mtspr(SPRN_MMCR3, cpuhw->mmcr[4]);
>>> +#endif /* CONFIG_PPC64 */
>>
>> I don't think you need the #ifdef CONFIG_PPC64?
>
> Hi Michael
>
> Thanks for reviewing this series.
>
> SPRN_MMCR3 is not defined for PPC32 and we hit build failure for pmac32_defconfig.
> The #ifdef CONFIG_PPC64 is to address this.
We like to avoid #ifdefs in the body of the code like that.
There's a bunch of existing #defines near the top of the file to make
32-bit work, I think you should just add another for this, so eg:
#ifdef CONFIG_PPC32
...
#define SPRN_MMCR3 0
cheers
^ permalink raw reply
* Re: [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc
From: Michael Ellerman @ 2020-07-13 12:47 UTC (permalink / raw)
To: Athira Rajeev; +Cc: mikey, maddy, linuxppc-dev
In-Reply-To: <FFC0AE06-9BF8-446C-B6D8-C4D62B61FDBE@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux.vnet.ibm.com> writes:
>> On 08-Jul-2020, at 5:34 PM, Michael Ellerman <mpe@ellerman.id.au> wrote:
>>
>> Athira Rajeev <atrajeev@linux.vnet.ibm.com <mailto:atrajeev@linux.vnet.ibm.com>> writes:
>>> From: Anju T Sudhakar <anju@linux.vnet.ibm.com>
>>>
>>> Add extended regs to sample_reg_mask in the tool side to use
>>> with `-I?` option. Perf tools side uses extended mask to display
...
>>
>>> + */
>>> + get_cpuid(buffer, sizeof(buffer));
>>> + ret = sscanf(buffer, "%u,", &version);
>>
>> This is powerpc specific code, why not just use mfspr(SPRN_PVR), rather
>> than redirecting via printf/sscanf.
>
> Hi Michael
>
> For perf tools, defines for `mfspr` , `SPRN_PVR` are in arch/powerpc/util/header.c
> So I have re-used existing utility. Otherwise, we will need to include these defines here as well
> Does that sounds good ?
They should be moved to a header in that directory that both C files can include.
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/boot: add DTB to 'targets'
From: Michael Ellerman @ 2020-07-13 12:34 UTC (permalink / raw)
To: Masahiro Yamada, linux-kbuild
Cc: Christophe Leroy, Arnd Bergmann, Masahiro Yamada, Michal Simek,
linux-kernel, Paul Mackerras, linuxppc-dev
In-Reply-To: <20200713075629.5948-1-masahiroy@kernel.org>
Masahiro Yamada <masahiroy@kernel.org> writes:
> PowerPC always re-builds DTB even if nothing has been changed.
>
> As for other architectures, arch/*/boot/dts/Makefile builds DTB by
> using the dtb-y syntax.
>
> In contrast, arch/powerpc/boot/dts/(fsl/)Makefile does nothing unless
> CONFIG_OF_ALL_DTBS is defined. Instead, arch/powerpc/boot/Makefile
> builds DTB on demand. You need to add DTB to 'targets' explicitly
> so .*.cmd files are included.
>
> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
> ---
>
> I want to apply this to kbuild tree because this is needed
> to fix the build error caused by another kbuild patch:
>
> https://lkml.org/lkml/2020/7/7/134
OK.
Acked-by: Michael Ellerman <mpe@ellerman.id.au>
cheers
> diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
> index 63d7456b9518..8792323707fd 100644
> --- a/arch/powerpc/boot/Makefile
> +++ b/arch/powerpc/boot/Makefile
> @@ -366,6 +366,8 @@ initrd-y := $(patsubst zImage%, zImage.initrd%, \
> $(patsubst treeImage%, treeImage.initrd%, $(image-y)))))
> initrd-y := $(filter-out $(image-y), $(initrd-y))
> targets += $(image-y) $(initrd-y)
> +targets += $(foreach x, dtbImage uImage cuImage simpleImage treeImage, \
> + $(patsubst $(x).%, dts/%.dtb, $(filter $(x).%, $(image-y))))
>
> $(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz
>
> --
> 2.25.1
^ permalink raw reply
* Re: [PATCH 18/20] Documentation: security/keys: eliminate duplicated word
From: Mimi Zohar @ 2020-07-13 12:24 UTC (permalink / raw)
To: Randy Dunlap, linux-kernel
Cc: kvm, linux-doc, David Airlie, kgdb-bugreport, linux-fpga,
Liviu Dudau, dri-devel, linux-mips, Paul Cercueil, keyrings,
Paul Mackerras, linux-i2c, Pavel Machek, Srinivas Pandruvada,
Mihail Atanassov, linux-leds, linux-s390, Daniel Thompson,
linux-scsi, Jonathan Corbet, Masahiro Yamada, Matthew Wilcox,
Halil Pasic, Jarkko Sakkinen, James Wang, linux-input,
Mali DP Maintainers, Derek Kiernan, Dragan Cvetic, Wu Hao,
Tony Krowiak, linux-kbuild, James E.J. Bottomley, Jiri Kosina,
Hannes Reinecke, linux-block, Thomas Bogendoerfer,
Jacek Anaszewski, linux-mm, Dan Williams, Andrew Morton,
Jens Axboe, Michal Marek, Martin K. Petersen, Pierre Morel,
Douglas Anderson, Wolfram Sang, Daniel Vetter, Jason Wessel,
Paolo Bonzini, linux-integrity, linuxppc-dev, Mike Rapoport,
Dan Murphy
In-Reply-To: <20200707180414.10467-19-rdunlap@infradead.org>
On Tue, 2020-07-07 at 11:04 -0700, Randy Dunlap wrote:
> Drop the doubled word "in".
>
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Mimi Zohar <zohar@linux.ibm.com>
^ permalink raw reply
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