* [PATCH] powerpc: Drop _nmask_and_or_msr()
From: Christophe Leroy @ 2020-08-13 10:07 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
_nmask_and_or_msr() is only used at two places to set MSR_IP.
The SYNC is unnecessary as the users are not PowerPC 601.
Can be easily writen in C.
Do it, and drop _nmask_and_or_msr()
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/misc_32.S | 13 -------------
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 3 ++-
arch/powerpc/platforms/embedded6xx/storcenter.c | 3 ++-
3 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index b24f866fef81..8d9cb5df580e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -215,19 +215,6 @@ _GLOBAL(low_choose_7447a_dfs)
#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
-/*
- * complement mask on the msr then "or" some values on.
- * _nmask_and_or_msr(nmask, value_to_or)
- */
-_GLOBAL(_nmask_and_or_msr)
- mfmsr r0 /* Get current msr */
- andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
- or r0,r0,r4 /* Or on the bits in r4 (second parm) */
- SYNC /* Some chip revs have problems here... */
- mtmsr r0 /* Update machine state */
- isync
- blr /* Done */
-
#ifdef CONFIG_40x
/*
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 15437abe1f6d..b95c3380d2b5 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -147,7 +147,8 @@ static void __noreturn mpc7448_hpc2_restart(char *cmd)
local_irq_disable();
/* Set exception prefix high - to the firmware */
- _nmask_and_or_msr(0, MSR_IP);
+ mtmsr(mfmsr() | MSR_IP);
+ isync();
for (;;) ; /* Spin until reset happens */
}
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index ed1914dd34bb..e346ddcef45e 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -101,7 +101,8 @@ static void __noreturn storcenter_restart(char *cmd)
local_irq_disable();
/* Set exception prefix high - to the firmware */
- _nmask_and_or_msr(0, MSR_IP);
+ mtmsr(mfmsr() | MSR_IP);
+ isync();
/* Wait for reset to happen */
for (;;) ;
--
2.25.0
^ permalink raw reply related
* Re: [PATCH 13/16] debug_vm_pgtable/pmd_clear: Don't use pmd/pud_clear on pte entries
From: Aneesh Kumar K.V @ 2020-08-13 8:45 UTC (permalink / raw)
To: Anshuman Khandual, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <1bb841d2-4622-b122-7176-246eb3702c9f@arm.com>
On 8/13/20 10:57 AM, Anshuman Khandual wrote:
>
>
> On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
>> pmd_clear() should not be used to clear pmd level pte entries.
>
> Could you please elaborate on this. The proposed change set does
> not match the description here.
>
pmd_clear is implemented such that we don't use that to clear a huge pte
entry. We use pmdp_huge_get_and_clear() for that. Hence we have check in
pmd_clear which add a WARN if we find a _PAGE_PTE set on the entry.
In the test we follow a hugepmd usage with a pmd_clear. We should
instead at the end of the advanced pmd test use pmdp_huge_get_and_clear().
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> ---
>> mm/debug_vm_pgtable.c | 7 ++++---
>> 1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 061c19bba7f0..529892b9be2f 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
>> @@ -191,6 +191,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
>> pmd = READ_ONCE(*pmdp);
>> WARN_ON(pmd_young(pmd));
>>
>> + /* Clear the pte entries */
>> + pmdp_huge_get_and_clear(mm, vaddr, pmdp);
>> pgtable = pgtable_trans_huge_withdraw(mm, pmdp);
>> }
>>
>> @@ -313,6 +315,8 @@ static void __init pud_advanced_tests(struct mm_struct *mm,
>> pudp_test_and_clear_young(vma, vaddr, pudp);
>> pud = READ_ONCE(*pudp);
>> WARN_ON(pud_young(pud));
>> +
>> + pudp_huge_get_and_clear(mm, vaddr, pudp);
>> }
>>
>> static void __init pud_leaf_tests(unsigned long pfn, pgprot_t prot)
>> @@ -431,8 +435,6 @@ static void __init pud_populate_tests(struct mm_struct *mm, pud_t *pudp,
>> * This entry points to next level page table page.
>> * Hence this must not qualify as pud_bad().
>> */
>> - pmd_clear(pmdp);
>> - pud_clear(pudp);
>
> Both entires are cleared before creating a fresh page table entry.
> Why that is a problem.
>
>> pud_populate(mm, pudp, pmdp);
>> pud = READ_ONCE(*pudp);
>> WARN_ON(pud_bad(pud));
>> @@ -564,7 +566,6 @@ static void __init pmd_populate_tests(struct mm_struct *mm, pmd_t *pmdp,
>> * This entry points to next level page table page.
>> * Hence this must not qualify as pmd_bad().
>> */
>> - pmd_clear(pmdp);
>
> Ditto.
>
>> pmd_populate(mm, pmdp, pgtable);
>> pmd = READ_ONCE(*pmdp);
>> WARN_ON(pmd_bad(pmd));
>>
^ permalink raw reply
* linux-next: runtime warning in Linus' tree
From: Stephen Rothwell @ 2020-08-13 6:46 UTC (permalink / raw)
To: Roman Gushchin, Andrew Morton
Cc: Linux PowerPC Mailing List, Linux Next Mailing List,
Linus Torvalds, Linux Kernel Mailing List, Johannes Weiner
[-- Attachment #1: Type: text/plain, Size: 5734 bytes --]
Hi all,
Testing Linus' tree today, my qemu runs (PowerPC
powerpc_pseries_le_defconfig) produce the following WARNING:
[ 0.021401][ T0] Mount-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[ 0.021529][ T0] Mountpoint-cache hash table entries: 8192 (order: 0, 65536 bytes, linear)
[ 0.053969][ T0] ------------[ cut here ]------------
[ 0.055220][ T0] WARNING: CPU: 0 PID: 0 at mm/memcontrol.c:5220 mem_cgroup_css_alloc+0x350/0x904
[ 0.055355][ T0] Modules linked in:
[ 0.055812][ T0] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.8.0 #5
[ 0.055976][ T0] NIP: c000000000410010 LR: c00000000040fd68 CTR: 0000000000000000
[ 0.056097][ T0] REGS: c0000000011e7ab0 TRAP: 0700 Not tainted (5.8.0)
[ 0.056162][ T0] MSR: 8000000002029033 <SF,VEC,EE,ME,IR,DR,RI,LE> CR: 24000888 XER: 00000000
[ 0.056449][ T0] CFAR: c00000000040fd80 IRQMASK: 0
[ 0.056449][ T0] GPR00: c00000000040fd68 c0000000011e7d40 c0000000011e8300 0000000000000001
[ 0.056449][ T0] GPR04: 0000000000000228 0000000000000000 0000000000000001 ffffffffffffffff
[ 0.056449][ T0] GPR08: c00000007d003208 0000000000000000 0000000000000000 c00000007d002fe8
[ 0.056449][ T0] GPR12: 0000000000000001 c0000000013d0000 0000000000000000 00000000011dd528
[ 0.056449][ T0] GPR16: 00000000011dd840 00000000011dd690 0000000000000018 0000000000000003
[ 0.056449][ T0] GPR20: 0000000000000001 c0000000010cbcf8 0000000000000003 c0000000010cd540
[ 0.056449][ T0] GPR24: c0000000010e8778 c0000000010e9080 c0000000010cbcd8 0000000000000000
[ 0.056449][ T0] GPR28: 0000000000000000 c00000007e2a1000 c0000000010cbcc8 c00000000118ea00
[ 0.057109][ T0] NIP [c000000000410010] mem_cgroup_css_alloc+0x350/0x904
[ 0.057177][ T0] LR [c00000000040fd68] mem_cgroup_css_alloc+0xa8/0x904
[ 0.057394][ T0] Call Trace:
[ 0.057534][ T0] [c0000000011e7d40] [c00000000040fd68] mem_cgroup_css_alloc+0xa8/0x904 (unreliable)
[ 0.057814][ T0] [c0000000011e7dc0] [c000000000f5b13c] cgroup_init_subsys+0xbc/0x210
[ 0.057903][ T0] [c0000000011e7e10] [c000000000f5b690] cgroup_init+0x220/0x598
[ 0.057973][ T0] [c0000000011e7ee0] [c000000000f34354] start_kernel+0x67c/0x6ec
[ 0.058047][ T0] [c0000000011e7f90] [c00000000000cb88] start_here_common+0x1c/0x614
[ 0.058241][ T0] Instruction dump:
[ 0.058420][ T0] eac10030 eae10038 eb410050 eb610058 4bffff60 60000000 60000000 60000000
[ 0.058550][ T0] 3be00100 4bfffdfc 60000000 60000000 <0fe00000> 4bfffd70 60000000 60000000
[ 0.059381][ T0] ---[ end trace cb2d79b4994ef1fe ]---
[ 0.059810][ T0] ------------[ cut here ]------------
[ 0.059872][ T0] WARNING: CPU: 0 PID: 0 at mm/memcontrol.c:5135 mem_cgroup_css_alloc+0x750/0x904
[ 0.059930][ T0] Modules linked in:
[ 0.060053][ T0] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.8.0 #5
[ 0.060113][ T0] NIP: c000000000410410 LR: c00000000040ff2c CTR: 0000000000000000
[ 0.060171][ T0] REGS: c0000000011e7ab0 TRAP: 0700 Tainted: G W (5.8.0)
[ 0.060229][ T0] MSR: 8000000002029033 <SF,VEC,EE,ME,IR,DR,RI,LE> CR: 24000880 XER: 00000000
[ 0.060332][ T0] CFAR: c00000000040fe48 IRQMASK: 0
[ 0.060332][ T0] GPR00: c00000000040ff2c c0000000011e7d40 c0000000011e8300 c00000007e234c00
[ 0.060332][ T0] GPR04: 0000000000000000 0000000000000000 c00000007e235000 0000000000000013
[ 0.060332][ T0] GPR08: 000000007ec00000 0000000000000000 0000000000000000 0000000000000001
[ 0.060332][ T0] GPR12: 0000000000000000 c0000000013d0000 0000000000000000 00000000011dd528
[ 0.060332][ T0] GPR16: 00000000011dd840 00000000011dd690 0000000000000018 0000000000000003
[ 0.060332][ T0] GPR20: c000000001223300 c000000000e95900 c00000000118ea00 c0000000012232c0
[ 0.060332][ T0] GPR24: c0000000010e8778 c0000000010e9080 0000000000400cc0 0000000000000000
[ 0.060332][ T0] GPR28: 0000000000000000 c00000007e2a1000 c00000007e234c00 0000000000000000
[ 0.060855][ T0] NIP [c000000000410410] mem_cgroup_css_alloc+0x750/0x904
[ 0.060911][ T0] LR [c00000000040ff2c] mem_cgroup_css_alloc+0x26c/0x904
[ 0.060958][ T0] Call Trace:
[ 0.061003][ T0] [c0000000011e7d40] [c00000000040ff2c] mem_cgroup_css_alloc+0x26c/0x904 (unreliable)
[ 0.061081][ T0] [c0000000011e7dc0] [c000000000f5b13c] cgroup_init_subsys+0xbc/0x210
[ 0.061165][ T0] [c0000000011e7e10] [c000000000f5b690] cgroup_init+0x220/0x598
[ 0.061233][ T0] [c0000000011e7ee0] [c000000000f34354] start_kernel+0x67c/0x6ec
[ 0.061303][ T0] [c0000000011e7f90] [c00000000000cb88] start_here_common+0x1c/0x614
[ 0.061364][ T0] Instruction dump:
[ 0.061408][ T0] ebe1fff8 7c0803a6 4e800020 60000000 60000000 3d220004 e929d230 7c3c4800
[ 0.061508][ T0] 41820190 e93c03d2 4bfffc80 60000000 <0fe00000> 4bfffa38 60000000 60000000
[ 0.061630][ T0] ---[ end trace cb2d79b4994ef1ff ]---
[ 0.096387][ T1] EEH: pSeries platform initialized
[ 0.097232][ T1] POWER8 performance monitor hardware support registered
[The line numbers in the final linux next are 5226 and 5141 due to
later patches.]
Introduced (or exposed) by commit
3e38e0aaca9e ("mm: memcg: charge memcg percpu memory to the parent cgroup")
This commit actually adds the WARN_ON, so it either adds the bug that
sets it off, or the bug already existed.
Unfotunately, the version of this patch in linux-next up tuntil today
is different. :-(
I have left this as I have no idea how to fix it :-)
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH 10/16] debug_vm_pgtable/thp: Use page table depost/withdraw with THP
From: Aneesh Kumar K.V @ 2020-08-13 6:38 UTC (permalink / raw)
To: Anshuman Khandual, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <40f2acb5-1da3-4c0a-5590-3fd12d128421@arm.com>
On 8/13/20 10:55 AM, Anshuman Khandual wrote:
> On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
>> Architectures like ppc64 use deposited page table while updating the huge pte
>> entries.
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> ---
>> mm/debug_vm_pgtable.c | 8 ++++++--
>> 1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index 644d28861ce9..48475d288df1 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
>> @@ -147,7 +147,7 @@ static void __init pmd_basic_tests(unsigned long pfn, pgprot_t prot)
>> static void __init pmd_advanced_tests(struct mm_struct *mm,
>> struct vm_area_struct *vma, pmd_t *pmdp,
>> unsigned long pfn, unsigned long vaddr,
>> - pgprot_t prot)
>> + pgprot_t prot, pgtable_t pgtable)
>> {
>> pmd_t pmd;
>>
>> @@ -158,6 +158,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
>> /* Align the address wrt HPAGE_PMD_SIZE */
>> vaddr = (vaddr & HPAGE_PMD_MASK) + HPAGE_PMD_SIZE;
>>
>> + pgtable_trans_huge_deposit(mm, pmdp, pgtable);
>> +
>> pmd = pmd_mkhuge(pfn_pmd(pfn, prot));
>> set_pmd_at(mm, vaddr, pmdp, pmd);
>> pmdp_set_wrprotect(mm, vaddr, pmdp);
>> @@ -188,6 +190,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
>> pmdp_test_and_clear_young(vma, vaddr, pmdp);
>> pmd = READ_ONCE(*pmdp);
>> WARN_ON(pmd_young(pmd));
>> +
>> + pgtable = pgtable_trans_huge_withdraw(mm, pmdp);
>> }
>>
>> static void __init pmd_leaf_tests(unsigned long pfn, pgprot_t prot)
>> @@ -1002,7 +1006,7 @@ static int __init debug_vm_pgtable(void)
>> pgd_clear_tests(mm, pgdp);
>>
>> pte_advanced_tests(mm, vma, ptep, pte_aligned, vaddr, prot);
>> - pmd_advanced_tests(mm, vma, pmdp, pmd_aligned, vaddr, prot);
>> + pmd_advanced_tests(mm, vma, pmdp, pmd_aligned, vaddr, prot, saved_ptep);
>> pud_advanced_tests(mm, vma, pudp, pud_aligned, vaddr, prot);
>> hugetlb_advanced_tests(mm, vma, ptep, pte_aligned, vaddr, prot);
>>
>>
>
> Makes sense, if it is required for THP to work correctly but needs to be tested
> across enabled platforms. Why should not the same apply for pud_advanced_tests()
> on platforms that supports PUD based THP.
>
pud doesn't have page table deposit/withdraw semantics. We use that to
support hugepage split. With pud mapping we don't split, we just drop
the hugepage and expect it to be faulted back in as regular page.
-aneesh
^ permalink raw reply
* Re: [PATCH 16/16] debug_vm_pgtable/ppc64: Add a variant of pfn_pte/pmd
From: Aneesh Kumar K.V @ 2020-08-13 6:37 UTC (permalink / raw)
To: Anshuman Khandual, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <fe7beb39-97e6-dd7c-59d4-e1a72bab3d71@arm.com>
On 8/13/20 11:00 AM, Anshuman Khandual wrote:
>
> On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
>> The tests do expect _PAGE_PTE bit set by different page table accessors.
>> This is not true for the kernel. Within the kernel, _PAGE_PTE bits are
>> usually set by set_pte_at(). To make the below tests work correctly add test
>> specific pfn_pte/pmd helpers that set _PAGE_PTE bit.
>>
>> pte_t pte = pfn_pte(pfn, prot);
>> WARN_ON(!pte_devmap(pte_mkdevmap(pte)));
>> WARN_ON(!pte_savedwrite(pte_mk_savedwrite(pte_clear_savedwrite(pte))));
>>
>> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> ---
>> mm/debug_vm_pgtable.c | 65 +++++++++++++++++++++++++++----------------
>> 1 file changed, 41 insertions(+), 24 deletions(-)
>>
>> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
>> index eea62d5e503b..153c925b5273 100644
>> --- a/mm/debug_vm_pgtable.c
>> +++ b/mm/debug_vm_pgtable.c
>> @@ -31,6 +31,23 @@
>> #include <asm/pgalloc.h>
>> #include <asm/tlbflush.h>
>>
>> +#ifdef CONFIG_PPC_BOOK3S_64
>> +static inline pte_t debug_vm_pfn_pte(unsigned long pfn, pgprot_t pgprot)
>> +{
>> + pte_t pte = pfn_pte(pfn, pgprot);
>> + return __pte(pte_val(pte) | _PAGE_PTE);
>> +
>> +}
>> +static inline pmd_t debug_vm_pfn_pmd(unsigned long pfn, pgprot_t pgprot)
>> +{
>> + pmd_t pmd = pfn_pmd(pfn, pgprot);
>> + return __pmd(pmd_val(pmd) | _PAGE_PTE);
>> +}
>> +#else
>> +#define debug_vm_pfn_pte(pfn, pgprot) pfn_pte(pfn, pgprot)
>> +#define debug_vm_pfn_pmd(pfn, pgprot) pfn_pmd(pfn, pgprot)
>> +#endif
>
> Again, no platform specific constructs please. This defeats the whole purpose of
> this test. If __PAGE_PTE is required for the helpers, then pfn_pmd/pte() could
> be modified to accommodate that. We dont see similar issues on other platforms,
> hence could you please explain why ppc64 is different here.
>
It is not platform specific. set_pte_at is the one that set the
_PAGE_PTE bit. We don't call that in the test. The test seems to make
the assumption that pfn_pte returns a proper pte which is not true.
-aneesh
^ permalink raw reply
* Re: INFO: task hung in pipe_release (2)
From: syzbot @ 2020-08-13 3:57 UTC (permalink / raw)
To: James.Bottomley, amanieu, arnd, benh, bfields, borntraeger, bp,
catalin.marinas, chris, christian, corbet, cyphar, dalias, davem,
deller, dvyukov, fenghua.yu, geert, gor, heiko.carstens, hpa, ink,
jcmvbkbc, jhogan, jlayton, kvalo, linux-alpha, linux-api,
linux-arch, linux-arm-kernel, linux-fsdevel, linux-ia64,
linux-kernel, linux-m68k, linux-mips, linux-parisc, linux-s390,
linux-sh, linux-xtensa, linux, linux, linuxppc-dev,
luis.f.correia, luto, martink, mattst88, ming.lei, ming.lei,
mingo, monstr
In-Reply-To: <00000000000084b59f05abe928ee@google.com>
syzbot has bisected this issue to:
commit fddb5d430ad9fa91b49b1d34d0202ffe2fa0e179
Author: Aleksa Sarai <cyphar@cyphar.com>
Date: Sat Jan 18 12:07:59 2020 +0000
open: introduce openat2(2) syscall
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=164e716a900000
start commit: 6ba1b005 Merge tag 'asm-generic-fixes-5.8' of git://git.ke..
git tree: upstream
final oops: https://syzkaller.appspot.com/x/report.txt?x=154e716a900000
console output: https://syzkaller.appspot.com/x/log.txt?x=114e716a900000
kernel config: https://syzkaller.appspot.com/x/.config?x=84f076779e989e69
dashboard link: https://syzkaller.appspot.com/bug?extid=61acc40a49a3e46e25ea
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=142ae224900000
Reported-by: syzbot+61acc40a49a3e46e25ea@syzkaller.appspotmail.com
Fixes: fddb5d430ad9 ("open: introduce openat2(2) syscall")
For information about bisection process see: https://goo.gl/tpsmEJ#bisection
^ permalink raw reply
* Re: [PATCH v3 2/2] powerpc/uaccess: Add pre-update addressing to __get_user_asm() and __put_user_asm()
From: Christophe Leroy @ 2020-08-13 5:56 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <20200812193712.GV6753@gate.crashing.org>
Le 12/08/2020 à 21:37, Segher Boessenkool a écrit :
> On Wed, Aug 12, 2020 at 12:25:17PM +0000, Christophe Leroy wrote:
>> Enable pre-update addressing mode in __get_user_asm() and __put_user_asm()
>>
>> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
>> ---
>> v3: new, splited out from patch 1.
>
> It still looks fine to me, you can keep my Reviewed-by: :-)
>
Ah yes thanks, forgot it when I commited it.
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Christophe
^ permalink raw reply
* Re: [PATCH 16/16] debug_vm_pgtable/ppc64: Add a variant of pfn_pte/pmd
From: Anshuman Khandual @ 2020-08-13 5:30 UTC (permalink / raw)
To: Aneesh Kumar K.V, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <20200812063358.369514-16-aneesh.kumar@linux.ibm.com>
On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
> The tests do expect _PAGE_PTE bit set by different page table accessors.
> This is not true for the kernel. Within the kernel, _PAGE_PTE bits are
> usually set by set_pte_at(). To make the below tests work correctly add test
> specific pfn_pte/pmd helpers that set _PAGE_PTE bit.
>
> pte_t pte = pfn_pte(pfn, prot);
> WARN_ON(!pte_devmap(pte_mkdevmap(pte)));
> WARN_ON(!pte_savedwrite(pte_mk_savedwrite(pte_clear_savedwrite(pte))));
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> mm/debug_vm_pgtable.c | 65 +++++++++++++++++++++++++++----------------
> 1 file changed, 41 insertions(+), 24 deletions(-)
>
> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
> index eea62d5e503b..153c925b5273 100644
> --- a/mm/debug_vm_pgtable.c
> +++ b/mm/debug_vm_pgtable.c
> @@ -31,6 +31,23 @@
> #include <asm/pgalloc.h>
> #include <asm/tlbflush.h>
>
> +#ifdef CONFIG_PPC_BOOK3S_64
> +static inline pte_t debug_vm_pfn_pte(unsigned long pfn, pgprot_t pgprot)
> +{
> + pte_t pte = pfn_pte(pfn, pgprot);
> + return __pte(pte_val(pte) | _PAGE_PTE);
> +
> +}
> +static inline pmd_t debug_vm_pfn_pmd(unsigned long pfn, pgprot_t pgprot)
> +{
> + pmd_t pmd = pfn_pmd(pfn, pgprot);
> + return __pmd(pmd_val(pmd) | _PAGE_PTE);
> +}
> +#else
> +#define debug_vm_pfn_pte(pfn, pgprot) pfn_pte(pfn, pgprot)
> +#define debug_vm_pfn_pmd(pfn, pgprot) pfn_pmd(pfn, pgprot)
> +#endif
Again, no platform specific constructs please. This defeats the whole purpose of
this test. If __PAGE_PTE is required for the helpers, then pfn_pmd/pte() could
be modified to accommodate that. We dont see similar issues on other platforms,
hence could you please explain why ppc64 is different here.
^ permalink raw reply
* Re: [PATCH 13/16] debug_vm_pgtable/pmd_clear: Don't use pmd/pud_clear on pte entries
From: Anshuman Khandual @ 2020-08-13 5:27 UTC (permalink / raw)
To: Aneesh Kumar K.V, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <20200812063358.369514-13-aneesh.kumar@linux.ibm.com>
On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
> pmd_clear() should not be used to clear pmd level pte entries.
Could you please elaborate on this. The proposed change set does
not match the description here.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> mm/debug_vm_pgtable.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
> index 061c19bba7f0..529892b9be2f 100644
> --- a/mm/debug_vm_pgtable.c
> +++ b/mm/debug_vm_pgtable.c
> @@ -191,6 +191,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
> pmd = READ_ONCE(*pmdp);
> WARN_ON(pmd_young(pmd));
>
> + /* Clear the pte entries */
> + pmdp_huge_get_and_clear(mm, vaddr, pmdp);
> pgtable = pgtable_trans_huge_withdraw(mm, pmdp);
> }
>
> @@ -313,6 +315,8 @@ static void __init pud_advanced_tests(struct mm_struct *mm,
> pudp_test_and_clear_young(vma, vaddr, pudp);
> pud = READ_ONCE(*pudp);
> WARN_ON(pud_young(pud));
> +
> + pudp_huge_get_and_clear(mm, vaddr, pudp);
> }
>
> static void __init pud_leaf_tests(unsigned long pfn, pgprot_t prot)
> @@ -431,8 +435,6 @@ static void __init pud_populate_tests(struct mm_struct *mm, pud_t *pudp,
> * This entry points to next level page table page.
> * Hence this must not qualify as pud_bad().
> */
> - pmd_clear(pmdp);
> - pud_clear(pudp);
Both entires are cleared before creating a fresh page table entry.
Why that is a problem.
> pud_populate(mm, pudp, pmdp);
> pud = READ_ONCE(*pudp);
> WARN_ON(pud_bad(pud));
> @@ -564,7 +566,6 @@ static void __init pmd_populate_tests(struct mm_struct *mm, pmd_t *pmdp,
> * This entry points to next level page table page.
> * Hence this must not qualify as pmd_bad().
> */
> - pmd_clear(pmdp);
Ditto.
> pmd_populate(mm, pmdp, pgtable);
> pmd = READ_ONCE(*pmdp);
> WARN_ON(pmd_bad(pmd));
>
^ permalink raw reply
* Re: [PATCH 10/16] debug_vm_pgtable/thp: Use page table depost/withdraw with THP
From: Anshuman Khandual @ 2020-08-13 5:25 UTC (permalink / raw)
To: Aneesh Kumar K.V, linux-mm, akpm; +Cc: linuxppc-dev
In-Reply-To: <20200812063358.369514-10-aneesh.kumar@linux.ibm.com>
On 08/12/2020 12:03 PM, Aneesh Kumar K.V wrote:
> Architectures like ppc64 use deposited page table while updating the huge pte
> entries.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> ---
> mm/debug_vm_pgtable.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/mm/debug_vm_pgtable.c b/mm/debug_vm_pgtable.c
> index 644d28861ce9..48475d288df1 100644
> --- a/mm/debug_vm_pgtable.c
> +++ b/mm/debug_vm_pgtable.c
> @@ -147,7 +147,7 @@ static void __init pmd_basic_tests(unsigned long pfn, pgprot_t prot)
> static void __init pmd_advanced_tests(struct mm_struct *mm,
> struct vm_area_struct *vma, pmd_t *pmdp,
> unsigned long pfn, unsigned long vaddr,
> - pgprot_t prot)
> + pgprot_t prot, pgtable_t pgtable)
> {
> pmd_t pmd;
>
> @@ -158,6 +158,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
> /* Align the address wrt HPAGE_PMD_SIZE */
> vaddr = (vaddr & HPAGE_PMD_MASK) + HPAGE_PMD_SIZE;
>
> + pgtable_trans_huge_deposit(mm, pmdp, pgtable);
> +
> pmd = pmd_mkhuge(pfn_pmd(pfn, prot));
> set_pmd_at(mm, vaddr, pmdp, pmd);
> pmdp_set_wrprotect(mm, vaddr, pmdp);
> @@ -188,6 +190,8 @@ static void __init pmd_advanced_tests(struct mm_struct *mm,
> pmdp_test_and_clear_young(vma, vaddr, pmdp);
> pmd = READ_ONCE(*pmdp);
> WARN_ON(pmd_young(pmd));
> +
> + pgtable = pgtable_trans_huge_withdraw(mm, pmdp);
> }
>
> static void __init pmd_leaf_tests(unsigned long pfn, pgprot_t prot)
> @@ -1002,7 +1006,7 @@ static int __init debug_vm_pgtable(void)
> pgd_clear_tests(mm, pgdp);
>
> pte_advanced_tests(mm, vma, ptep, pte_aligned, vaddr, prot);
> - pmd_advanced_tests(mm, vma, pmdp, pmd_aligned, vaddr, prot);
> + pmd_advanced_tests(mm, vma, pmdp, pmd_aligned, vaddr, prot, saved_ptep);
> pud_advanced_tests(mm, vma, pudp, pud_aligned, vaddr, prot);
> hugetlb_advanced_tests(mm, vma, ptep, pte_aligned, vaddr, prot);
>
>
Makes sense, if it is required for THP to work correctly but needs to be tested
across enabled platforms. Why should not the same apply for pud_advanced_tests()
on platforms that supports PUD based THP.
^ permalink raw reply
* [PATCH] powerpc/papr_scm: Limit the readability of 'perf_stats' sysfs attribute
From: Vaibhav Jain @ 2020-08-13 4:34 UTC (permalink / raw)
To: linuxppc-dev, linux-nvdimm
Cc: Santosh Sivaraj, Oliver O'Halloran, Aneesh Kumar K . V,
Vaibhav Jain, Dan Williams, Ira Weiny
The newly introduced 'perf_stats' attribute uses the default access
mode of 0444 letting non-root users access performance stats of an
nvdimm and potentially force the kernel into issuing large number of
expensive HCALLs. Since the information exposed by this attribute
cannot be cached hence its better to ward of access to this attribute
from users who don't need to access these performance statistics.
Hence this patch adds check in perf_stats_show() to only let users
that are 'perfmon_capable()' to read the nvdimm performance
statistics.
Fixes: 2d02bf835e573 ('powerpc/papr_scm: Fetch nvdimm performance stats from PHYP')
Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
---
arch/powerpc/platforms/pseries/papr_scm.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
index f439f0dfea7d1..36c51bf8af9a8 100644
--- a/arch/powerpc/platforms/pseries/papr_scm.c
+++ b/arch/powerpc/platforms/pseries/papr_scm.c
@@ -792,6 +792,10 @@ static ssize_t perf_stats_show(struct device *dev,
struct nvdimm *dimm = to_nvdimm(dev);
struct papr_scm_priv *p = nvdimm_provider_data(dimm);
+ /* Allow access only to perfmon capable users */
+ if (!perfmon_capable())
+ return -EACCES;
+
if (!p->stat_buffer_len)
return -ENOENT;
--
2.26.2
^ permalink raw reply related
* [PATCH 3/3] selftests/powerpc: Run tm-tmspr test for longer
From: Michael Ellerman @ 2020-08-13 1:34 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20200813013445.686464-1-mpe@ellerman.id.au>
This test creates some threads, which write to TM SPRs, and then makes
sure the registers maintain the correct values across context switches
and contention with other threads.
But currently the test finishes almost instantaneously, which reduces
the chance of it hitting an interesting condition.
So increase the number of loops, so it runs a bit longer, though still
less than 2s on a Power8.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/tm/tm-tmspr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/testing/selftests/powerpc/tm/tm-tmspr.c b/tools/testing/selftests/powerpc/tm/tm-tmspr.c
index 2ff329e2fca9..794d574db784 100644
--- a/tools/testing/selftests/powerpc/tm/tm-tmspr.c
+++ b/tools/testing/selftests/powerpc/tm/tm-tmspr.c
@@ -33,7 +33,7 @@
#include "utils.h"
#include "tm.h"
-int num_loops = 10000;
+int num_loops = 1000000;
int passed = 1;
void tfiar_tfhar(void *in)
--
2.25.1
^ permalink raw reply related
* [PATCH 2/3] selftests/powerpc: Don't use setaffinity in tm-tmspr
From: Michael Ellerman @ 2020-08-13 1:34 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20200813013445.686464-1-mpe@ellerman.id.au>
This test tries to set affinity to CPUs that don't exist, especially
if the set of online CPUs doesn't start at 0.
But there's no real reason for it to use setaffinity in the first
place, it's just trying to create lots of threads to cause contention.
So drop the setaffinity entirely.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/tm/tm-tmspr.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/tools/testing/selftests/powerpc/tm/tm-tmspr.c b/tools/testing/selftests/powerpc/tm/tm-tmspr.c
index 17becf3dcee4..2ff329e2fca9 100644
--- a/tools/testing/selftests/powerpc/tm/tm-tmspr.c
+++ b/tools/testing/selftests/powerpc/tm/tm-tmspr.c
@@ -38,14 +38,8 @@ int passed = 1;
void tfiar_tfhar(void *in)
{
- int i, cpu;
unsigned long tfhar, tfhar_rd, tfiar, tfiar_rd;
- cpu_set_t cpuset;
-
- CPU_ZERO(&cpuset);
- cpu = (unsigned long)in >> 1;
- CPU_SET(cpu, &cpuset);
- sched_setaffinity(0, sizeof(cpuset), &cpuset);
+ int i;
/* TFIAR: Last bit has to be high so userspace can read register */
tfiar = ((unsigned long)in) + 1;
--
2.25.1
^ permalink raw reply related
* [PATCH 1/3] selftests/powerpc: Fix TM tests when CPU 0 is offline
From: Michael Ellerman @ 2020-08-13 1:34 UTC (permalink / raw)
To: linuxppc-dev
Several of the TM tests fail spuriously if CPU 0 is offline, because
they blindly try to affinitise to CPU 0.
Fix them by picking any online CPU and using that instead.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
---
tools/testing/selftests/powerpc/tm/tm-poison.c | 11 +++++++----
tools/testing/selftests/powerpc/tm/tm-trap.c | 10 ++++++----
tools/testing/selftests/powerpc/tm/tm-unavailable.c | 9 ++++++---
3 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/tools/testing/selftests/powerpc/tm/tm-poison.c b/tools/testing/selftests/powerpc/tm/tm-poison.c
index 977558497c16..29e5f26af7b9 100644
--- a/tools/testing/selftests/powerpc/tm/tm-poison.c
+++ b/tools/testing/selftests/powerpc/tm/tm-poison.c
@@ -26,7 +26,7 @@
int tm_poison_test(void)
{
- int pid;
+ int cpu, pid;
cpu_set_t cpuset;
uint64_t poison = 0xdeadbeefc0dec0fe;
uint64_t unknown = 0;
@@ -35,10 +35,13 @@ int tm_poison_test(void)
SKIP_IF(!have_htm());
- /* Attach both Child and Parent to CPU 0 */
+ cpu = pick_online_cpu();
+ FAIL_IF(cpu < 0);
+
+ // Attach both Child and Parent to the same CPU
CPU_ZERO(&cpuset);
- CPU_SET(0, &cpuset);
- sched_setaffinity(0, sizeof(cpuset), &cpuset);
+ CPU_SET(cpu, &cpuset);
+ FAIL_IF(sched_setaffinity(0, sizeof(cpuset), &cpuset) != 0);
pid = fork();
if (!pid) {
diff --git a/tools/testing/selftests/powerpc/tm/tm-trap.c b/tools/testing/selftests/powerpc/tm/tm-trap.c
index 601f0c1d450d..c75960af8018 100644
--- a/tools/testing/selftests/powerpc/tm/tm-trap.c
+++ b/tools/testing/selftests/powerpc/tm/tm-trap.c
@@ -247,8 +247,7 @@ void *pong(void *not_used)
int tm_trap_test(void)
{
uint16_t k = 1;
-
- int rc;
+ int cpu, rc;
pthread_attr_t attr;
cpu_set_t cpuset;
@@ -267,9 +266,12 @@ int tm_trap_test(void)
usr1_sa.sa_sigaction = usr1_signal_handler;
sigaction(SIGUSR1, &usr1_sa, NULL);
- /* Set only CPU 0 in the mask. Both threads will be bound to cpu 0. */
+ cpu = pick_online_cpu();
+ FAIL_IF(cpu < 0);
+
+ // Set only one CPU in the mask. Both threads will be bound to that CPU.
CPU_ZERO(&cpuset);
- CPU_SET(0, &cpuset);
+ CPU_SET(cpu, &cpuset);
/* Init pthread attribute */
rc = pthread_attr_init(&attr);
diff --git a/tools/testing/selftests/powerpc/tm/tm-unavailable.c b/tools/testing/selftests/powerpc/tm/tm-unavailable.c
index 2ca2fccb0a3e..a1348a5f721a 100644
--- a/tools/testing/selftests/powerpc/tm/tm-unavailable.c
+++ b/tools/testing/selftests/powerpc/tm/tm-unavailable.c
@@ -338,16 +338,19 @@ void test_fp_vec(int fp, int vec, pthread_attr_t *attr)
int tm_unavailable_test(void)
{
- int rc, exception; /* FP = 0, VEC = 1, VSX = 2 */
+ int cpu, rc, exception; /* FP = 0, VEC = 1, VSX = 2 */
pthread_t t1;
pthread_attr_t attr;
cpu_set_t cpuset;
SKIP_IF(!have_htm());
- /* Set only CPU 0 in the mask. Both threads will be bound to CPU 0. */
+ cpu = pick_online_cpu();
+ FAIL_IF(cpu < 0);
+
+ // Set only one CPU in the mask. Both threads will be bound to that CPU.
CPU_ZERO(&cpuset);
- CPU_SET(0, &cpuset);
+ CPU_SET(cpu, &cpuset);
/* Init pthread attribute. */
rc = pthread_attr_init(&attr);
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2] powerpc/pseries: explicitly reschedule during drmem_lmb list traversal
From: Nathan Lynch @ 2020-08-13 1:07 UTC (permalink / raw)
To: Michael Ellerman, Tyrel Datwyler, linuxppc-dev; +Cc: cheloha, ldufour
In-Reply-To: <87lfij9yp6.fsf@mpe.ellerman.id.au>
Michael Ellerman <mpe@ellerman.id.au> writes:
> Tyrel Datwyler <tyreld@linux.ibm.com> writes:
>> On 8/11/20 6:20 PM, Nathan Lynch wrote:
>>>
>>> +static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb)
>>> +{
>>> + const unsigned int resched_interval = 20;
>>> +
>>> + BUG_ON(lmb < drmem_info->lmbs);
>>> + BUG_ON(lmb >= drmem_info->lmbs + drmem_info->n_lmbs);
>>
>> I think BUG_ON is a pretty big no-no these days unless there is no other option.
>
> It's complicated, but yes we would like to avoid adding them if we can.
>
> In a case like this there is no other option, *if* the check has to be
> in drmem_lmb_next().
>
> But I don't think we really need to check that there.
>
> If for some reason this was called with an *lmb pointing outside of the
> lmbs array it would confuse the cond_resched() logic, but it's not worth
> crashing the box for that IMHO.
The BUG_ONs are pretty much orthogonal to the cond_resched().
It's not apparent from the context of the change, but some users of the
for_each_drmem_lmb* macros modify elements of the drmem_info->lmbs
array. If the lmb passed to drmem_lmb_next() violates the bounds check
(say, if the callsite inappropriately modifies it within the loop), such
users are guaranteed to corrupt other objects in memory. This was my
thinking in adding the BUG_ONs, and I don't see another place to do
it.
^ permalink raw reply
* Re: [PATCH] powerpc: Fix P10 PVR revision in /proc/cpuinfo for SMT4 cores
From: Michael Neuling @ 2020-08-13 0:34 UTC (permalink / raw)
To: Michael Ellerman; +Cc: grimm, linuxppc-dev
In-Reply-To: <87sgd3zyt6.fsf@mpe.ellerman.id.au>
On Mon, 2020-08-03 at 22:41 +1000, Michael Ellerman wrote:
> Michael Neuling <mikey@neuling.org> writes:
> > On POWER10 bit 12 in the PVR indicates if the core is SMT4 or
> > SMT8. Bit 12 is set for SMT4.
> >
> > Without this patch, /proc/cpuinfo on a SMT4 DD1 POWER10 looks like
> > this:
> > cpu : POWER10, altivec supported
> > revision : 17.0 (pvr 0080 1100)
> >
> > Signed-off-by: Michael Neuling <mikey@neuling.org>
> > ---
> > arch/powerpc/kernel/setup-common.c | 1 +
> > 1 file changed, 1 insertion(+)
>
> This should have a Fixes: pointing at something so it gets backported.
Yes it should.
Mikey
^ permalink raw reply
* Re: [PATCH v2] powerpc/pseries: explicitly reschedule during drmem_lmb list traversal
From: Michael Ellerman @ 2020-08-13 0:28 UTC (permalink / raw)
To: Tyrel Datwyler, Nathan Lynch, linuxppc-dev; +Cc: cheloha, ldufour
In-Reply-To: <5e8213a6-802b-f7ca-b43b-a3de8a03d1da@linux.ibm.com>
Tyrel Datwyler <tyreld@linux.ibm.com> writes:
> On 8/11/20 6:20 PM, Nathan Lynch wrote:
>> The drmem lmb list can have hundreds of thousands of entries, and
>> unfortunately lookups take the form of linear searches. As long as
>> this is the case, traversals have the potential to monopolize the CPU
>> and provoke lockup reports, workqueue stalls, and the like unless
>> they explicitly yield.
>>
>> Rather than placing cond_resched() calls within various
>> for_each_drmem_lmb() loop blocks in the code, put it in the iteration
>> expression of the loop macro itself so users can't omit it.
>>
>> Call cond_resched() on every 20th element. Each iteration of the loop
>> in DLPAR code paths can involve around ten RTAS calls which can each
>> take up to 250us, so this ensures the check is performed at worst
>> every few milliseconds.
>>
>> Fixes: 6c6ea53725b3 ("powerpc/mm: Separate ibm, dynamic-memory data from DT format")
>> Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com>
>> ---
>> arch/powerpc/include/asm/drmem.h | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> Changes since v1:
>> * Add bounds assertions in drmem_lmb_next().
>> * Call cond_resched() in the iterator on only every 20th element
>> instead of on every iteration, to reduce overhead in tight loops.
>>
>> diff --git a/arch/powerpc/include/asm/drmem.h b/arch/powerpc/include/asm/drmem.h
>> index 17ccc6474ab6..583277e30dd2 100644
>> --- a/arch/powerpc/include/asm/drmem.h
>> +++ b/arch/powerpc/include/asm/drmem.h
>> @@ -8,6 +8,9 @@
>> #ifndef _ASM_POWERPC_LMB_H
>> #define _ASM_POWERPC_LMB_H
>>
>> +#include <linux/bug.h>
>> +#include <linux/sched.h>
>> +
>> struct drmem_lmb {
>> u64 base_addr;
>> u32 drc_index;
>> @@ -26,8 +29,21 @@ struct drmem_lmb_info {
>>
>> extern struct drmem_lmb_info *drmem_info;
>>
>> +static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb)
>> +{
>> + const unsigned int resched_interval = 20;
>> +
>> + BUG_ON(lmb < drmem_info->lmbs);
>> + BUG_ON(lmb >= drmem_info->lmbs + drmem_info->n_lmbs);
>
> I think BUG_ON is a pretty big no-no these days unless there is no other option.
It's complicated, but yes we would like to avoid adding them if we can.
In a case like this there is no other option, *if* the check has to be
in drmem_lmb_next().
But I don't think we really need to check that there.
If for some reason this was called with an *lmb pointing outside of the
lmbs array it would confuse the cond_resched() logic, but it's not worth
crashing the box for that IMHO.
cheers
^ permalink raw reply
* [RFC PATCH v1 1/4] powerpc: apm82181: create shared dtsi for APM bluestone
From: Christian Lamparter @ 2020-08-12 22:41 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
In-Reply-To: <cover.1597271958.git.chunkeey@gmail.com>
This patch adds an DTSI-File that can be used by various device-tree
files for APM82181-based devices.
Some of the nodes (like UART, PCIE, SATA) are used by the uboot and
need to stick with the naming-conventions of the old times'.
I've added comments whenever this was the case. But unfortunately,
this I've to point out that for this reason, there are some warning
messages when compiling the dtb:
> apm82181.dtsi:440.26-483.5: Warning (pci_bridge): /plb/pciex@d00000000: node name is not "pci" or "pcie"
> wd-mybooklive.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
Signed-off-By: Chris Blake <chrisrblake93@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/boot/dts/apm82181.dtsi | 485 ++++++++++++++++++++++++++++
1 file changed, 485 insertions(+)
create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
diff --git a/arch/powerpc/boot/dts/apm82181.dtsi b/arch/powerpc/boot/dts/apm82181.dtsi
new file mode 100644
index 000000000000..54a9a6fda4af
--- /dev/null
+++ b/arch/powerpc/boot/dts/apm82181.dtsi
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree template include for various Bluestone (APM82181) boards.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Author: Tirumala R Marri <tmarri@apm.com>,
+ * Christian Lamparter <chunkeey@gmail.com>,
+ * Chris Blake <chrisrblake93@gmail.com>
+ */
+
+#include <dt-bindings/dma/dw-dmac.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ dcr-parent = <&{/cpus/cpu@0}>;
+ compatible = "apm,bluestone";
+
+ aliases {
+ ethernet0 = &EMAC0; /* needed for BSP u-boot */
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ model = "PowerPC,apm82181";
+ reg = <0x00000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ timebase-frequency = <0>; /* Filled in by U-Boot */
+ i-cache-line-size = <32>;
+ d-cache-line-size = <32>;
+ i-cache-size = <32768>;
+ d-cache-size = <32768>;
+ dcr-controller;
+ dcr-access-method = "native";
+ next-level-cache = <&L2C0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
+ };
+
+ UIC0: interrupt-controller0 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <0>;
+ dcr-reg = <0x0c0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UIC1: interrupt-controller1 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <1>;
+ dcr-reg = <0x0d0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH>,
+ <0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC2: interrupt-controller2 {
+ compatible = "apm,uic-apm82181", "ibm,uic";
+ interrupt-controller;
+ cell-index = <2>;
+ dcr-reg = <0x0e0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH>,
+ <0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ UIC3: interrupt-controller3 {
+ compatible = "apm,uic-apm82181","ibm,uic";
+ interrupt-controller;
+ cell-index = <3>;
+ dcr-reg = <0x0f0 0x009>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH>,
+ <0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */
+ interrupt-parent = <&UIC0>;
+ };
+
+ OCM1: ocm@400040000 {
+ compatible = "apm,ocm-apm82181", "ibm,ocm";
+ status = "okay";
+ cell-index = <1>;
+ /* configured in U-Boot */
+ reg = <4 0x00040000 0x8000>; /* 32K */
+ };
+
+ SDR0: sdr {
+ compatible = "apm,sdr-apm82181", "ibm,sdr-460ex";
+ dcr-reg = <0x00e 0x002>;
+ };
+
+ CPR0: cpr {
+ compatible = "apm,cpr-apm82181", "ibm,cpr-460ex";
+ dcr-reg = <0x00c 0x002>;
+ };
+
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
+ dcr-reg = <0x020 0x008
+ 0x030 0x008>;
+ cache-line-size = <32>;
+ cache-size = <262144>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x0b IRQ_TYPE_EDGE_RISING>;
+ };
+
+ CPM0: cpm {
+ compatible = "ibm,cpm-apm821xx", "ibm,cpm";
+ cell-index = <0>;
+ dcr-reg = <0x160 0x003>;
+ pm-cpu = <0x02000000>;
+ pm-doze = <0x302570F0>;
+ pm-nap = <0x302570F0>;
+ pm-deepsleep = <0x302570F0>;
+ pm-iic-device = <&IIC0>;
+ pm-emac-device = <&EMAC0>;
+ unused-units = <0x00000100>;
+ idle-doze = <0x02000000>;
+ standby = <0xfeff791d>;
+ };
+
+ plb {
+ compatible = "apm,plb-apm82181", "ibm,plb-460ex", "ibm,plb4";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges; /* Filled in by U-Boot */
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ SDRAM0: sdram {
+ compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp";
+ dcr-reg = <0x010 0x002>;
+ };
+
+ RTC: rtc {
+ compatible = "ibm,rtc";
+ dcr-reg = <0x240 0x009>;
+ interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&UIC2>;
+ status = "disabled";
+ };
+
+ TRNG: trng@110000 {
+ compatible = "amcc,ppc460ex-rng", "ppc4xx-rng", "amcc, ppc4xx-trng";
+ reg = <4 0x00110000 0x100>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ PKA: pka@114000 {
+ compatible = "ppc4xx-pka", "amcc,ppc4xx-pka", "amcc, ppc4xx-pka";
+ reg = <4 0x00114000 0x4000>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x14 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ CRYPTO: crypto@180000 {
+ compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
+ reg = <4 0x00180000 0x80400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled"; /* hardware option */
+ };
+
+ MAL0: mcmal {
+ compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
+ descriptor-memory = "ocm";
+ dcr-reg = <0x180 0x062>;
+ num-tx-chans = <1>;
+ num-rx-chans = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-parent = <&UIC2>;
+ interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>,
+ <0x07 IRQ_TYPE_LEVEL_HIGH>,
+ <0x03 IRQ_TYPE_LEVEL_HIGH>,
+ <0x04 IRQ_TYPE_LEVEL_HIGH>,
+ <0x05 IRQ_TYPE_LEVEL_HIGH>,
+ <0x08 IRQ_TYPE_EDGE_FALLING>,
+ <0x09 IRQ_TYPE_EDGE_FALLING>,
+ <0x0c IRQ_TYPE_EDGE_FALLING>,
+ <0x0d IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "txeob", "rxeob", "serr",
+ "txde", "rxde",
+ "tx0coal", "tx1coal",
+ "rx0coal", "rx1coal";
+ };
+
+ POB0: opb {
+ compatible = "ibm,opb-460ex", "ibm,opb";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+
+ EBC0: ebc {
+ compatible = "ibm,ebc-460ex", "ibm,ebc";
+ dcr-reg = <0x012 0x002>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ /* ranges property is supplied by U-Boot */
+ ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;
+ interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&UIC1>;
+
+ nor_flash@0,0 {
+ compatible = "cfi-flash";
+ bank-width = <1>;
+ reg = <0x00000000 0x00000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+
+ ndfc@1,0 {
+ compatible = "ibm,ndfc";
+ reg = <00000003 00000000 00002000>;
+ ccr = <0x00001000>;
+ bank-settings = <0x80002222>;
+ status = "disabled";
+
+ nand {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+ };
+
+ UART0: serial@ef600300 {
+ /*
+ * AMCC's BSP u-boot scans for the "ns16550"
+ * compatible, without it, u-boot wouldn't
+ * set the required "clock-frequency".
+ *
+ * The hardware documentation states:
+ * "Register compatibility with 16750 register set"
+ */
+ compatible = "ns16750", "ns16550";
+ reg = <0xef600300 0x00000008>;
+ virtual-reg = <0xef600300>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ UART1: serial@ef600400 {
+ /* same "ns16750" as with UART0 */
+ compatible = "ns16750", "ns16550";
+ reg = <0xef600400 0x00000008>;
+ virtual-reg = <0xef600400>;
+ clock-frequency = <0>; /* Filled in by U-Boot */
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ IIC0: i2c@ef600700 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <0xef600700 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ IIC1: i2c@ef600800 {
+ compatible = "ibm,iic-460ex", "ibm,iic";
+ reg = <0xef600800 0x00000014>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ GPIO0: gpio@ef600b00 {
+ compatible = "ibm,ppc4xx-gpio";
+ reg = <0xef600b00 0x00000048>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ status = "disabled";
+ };
+
+ EMAC0: ethernet@ef600c00 {
+ device_type = "network";
+ compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
+ interrupt-parent = <&EMAC0>;
+ interrupts = <0 1>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH>,
+ <1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "status", "wake";
+
+ reg = <0xef600c00 0x000000c4>;
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ mal-device = <&MAL0>;
+ mal-tx-channel = <0>;
+ mal-rx-channel = <0>;
+ cell-index = <0>;
+ max-frame-size = <9000>;
+ rx-fifo-size = <16384>;
+ tx-fifo-size = <2048>;
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+ rgmii-device = <&RGMII0>;
+ rgmii-channel = <0>;
+ tah-device = <&TAH0>;
+ tah-channel = <0>;
+ has-inverted-stacr-oc;
+ has-new-stacr-staopc;
+ status = "disabled";
+ };
+
+ TAH0: emac-tah@ef601350 {
+ compatible = "ibm,tah-460ex", "ibm,tah";
+ reg = <0xef601350 0x00000030>;
+ };
+
+ RGMII0: emac-rgmii@ef601500 {
+ compatible = "ibm,rgmii-405ex", "ibm,rgmii";
+ reg = <0xef601500 0x00000008>;
+ has-mdio;
+ };
+ };
+
+ USBOTG0: usbotg@bff80000 {
+ compatible = "amcc,dwc-otg";
+ reg = <4 0xbff80000 0x10000>;
+ interrupt-parent = <&USBOTG0>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH>,
+ <1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW>,
+ <2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "usb-otg", "high-power", "dma";
+ dr_mode = "host";
+ status = "disabled";
+ };
+
+ AHBDMA0: dma@bffd0800 {
+ compatible = "snps,dma-spear1340";
+ reg = <4 0xbffd0800 0x400>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <3>;
+
+ dma-channels = <2>;
+ dma-masters = <3>;
+ block_size = <4095>;
+ data-width = <4>, <4>, <4>;
+ multi-block = <1>, <1>;
+
+ chan_allocation_order = <1>;
+ chan_priority = <1>;
+
+ snps,dma-protection-control =
+ <(DW_DMAC_HPROT1_PRIVILEGED_MODE |
+ DW_DMAC_HPROT2_BUFFERABLE)>;
+ is_memcpy;
+ };
+
+ SATA0: sata@bffd1000 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1000 0x800>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&AHBDMA0 0 0 1>;
+ dma-names = "sata-dma";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ SATA1: sata@bffd1800 {
+ compatible = "amcc,sata-460ex";
+ reg = <4 0xbffd1800 0x800>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&AHBDMA0 1 0 2>;
+ dma-names = "sata-dma";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ MSI: ppc4xx-msi@c10000000 {
+ compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+ reg = <0xc 0x10000000 0x100
+ 0xc 0x10000000 0x100>;
+ sdr-base = <0x36C>;
+ msi-data = <0x00004440>;
+ msi-mask = <0x0000ffe0>;
+ interrupts =<0 1 2 3 4 5 6 7>;
+ interrupt-parent = <&MSI>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ msi-available-ranges = <0x0 0x100>;
+ interrupt-map =
+ <0 &UIC3 0x18 IRQ_TYPE_EDGE_RISING>,
+ <1 &UIC3 0x19 IRQ_TYPE_EDGE_RISING>,
+ <2 &UIC3 0x1a IRQ_TYPE_EDGE_RISING>,
+ <3 &UIC3 0x1b IRQ_TYPE_EDGE_RISING>,
+ <4 &UIC3 0x1c IRQ_TYPE_EDGE_RISING>,
+ <5 &UIC3 0x1d IRQ_TYPE_EDGE_RISING>,
+ <6 &UIC3 0x1e IRQ_TYPE_EDGE_RISING>,
+ <7 &UIC3 0x1f IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ PCIE0: pciex@d00000000 {
+ device_type = "pci"; /* see ppc4xx_pci_find_bridge */
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
+ primary;
+ port = <0x0>; /* port number */
+ reg = <0x0000000d 0x00000000 0x20000000>, /* Config space access */
+ <0x0000000c 0x08010000 0x00001000>; /* Registers */
+ dcr-reg = <0x100 0x020>;
+ sdr-base = <0x300>;
+
+ /*
+ * Outbound ranges, one memory and one IO,
+ * later cannot be changed
+ */
+ ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000>,
+ <0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000>,
+ <0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+
+ /* Inbound 2GB range starting at 0 */
+ dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+
+ /* This drives busses 0x40 to 0x7f */
+ bus-range = <0x40 0x7f>;
+
+ /*
+ * Legacy interrupts (note the weird polarity, the bridge seems
+ * to invert PCIe legacy interrupts).
+ * We are de-swizzling here because the numbers are actually for
+ * port of the root complex virtual P2P bridge. But I want
+ * to avoid putting a node for it in the tree, so the numbers
+ * below are basically de-swizzled numbers.
+ * The real slot is on idsel 0, so the swizzling is 1:1
+ */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map =
+ <0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH>, /* swizzled int A */
+ <0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH>, /* swizzled int B */
+ <0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH>, /* swizzled int C */
+ <0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH>; /* swizzled int D */
+ status = "disabled";
+ };
+ };
+};
--
2.28.0
^ permalink raw reply related
* [RFC PATCH v1 3/4] powerpc: apm82181: add Meraki MR24 AP
From: Christian Lamparter @ 2020-08-12 22:41 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
In-Reply-To: <08dd11e8ce996a0df27dca3a9316bfc4ede0d0d0.1597271958.git.chunkeey@gmail.com>
This patch adds the device-tree definitions for Meraki MR24
Accesspoint devices.
Ready to go images and install instruction can be found @OpenWrt.
Signed-off-By: Chris Blake <chrisrblake93@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/boot/dts/meraki-mr24.dts | 237 +++++++++++++++++++++
arch/powerpc/platforms/44x/ppc44x_simple.c | 1 +
2 files changed, 238 insertions(+)
create mode 100644 arch/powerpc/boot/dts/meraki-mr24.dts
diff --git a/arch/powerpc/boot/dts/meraki-mr24.dts b/arch/powerpc/boot/dts/meraki-mr24.dts
new file mode 100644
index 000000000000..945e3e6b2585
--- /dev/null
+++ b/arch/powerpc/boot/dts/meraki-mr24.dts
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Device Tree Source for Meraki MR24 (Ikarem)
+ *
+ * Copyright (C) 2016 Chris Blake <chrisrblake93@gmail.com>
+ *
+ * Based on Cisco Meraki GPL Release r23-20150601 MR24 DTS
+ */
+
+/dts-v1/;
+
+#include "apm82181.dtsi"
+
+/ {
+ model = "Meraki MR24 Access Point";
+ compatible = "meraki,mr24";
+
+ aliases {
+ serial0 = &UART1;
+ led-boot = &status;
+ led-failsafe = &failsafe;
+ led-running = &status;
+ led-upgrade = &status;
+ };
+
+ chosen {
+ stdout-path = "/plb/opb/serial@ef600400";
+ };
+};
+
+
+&CRYPTO {
+ status = "okay";
+};
+
+&PKA {
+ status = "okay";
+};
+
+&TRNG {
+ status = "okay";
+};
+
+&EBC0 {
+ /* Ikarem has 32MB of NAND */
+ ndfc@1,0 {
+ status = "okay";
+ /* 32 MiB NAND Flash */
+ nand {
+ partition@0 {
+ label = "u-boot";
+ reg = <0x00000000 0x00150000>;
+ read-only;
+ };
+
+ partition@150000 {
+ /*
+ * The u-boot environment size is one NAND
+ * block (16KiB). u-boot allocates four NAND
+ * blocks (64KiB) in order to have spares
+ * around for bad block management
+ */
+ label = "u-boot-env";
+ reg = <0x00150000 0x00010000>;
+ read-only;
+ };
+
+ partition@160000 {
+ /*
+ * redundant u-boot environment.
+ * has to be kept it in sync with the
+ * data in "u-boot-env".
+ */
+ label = "u-boot-env-redundant";
+ reg = <0x00160000 0x00010000>;
+ read-only;
+ };
+
+ partition@170000 {
+ label = "oops";
+ reg = <0x00170000 0x00010000>;
+ };
+
+ partition@180000 {
+ label = "ubi";
+ reg = <0x00180000 0x01e80000>;
+ };
+ };
+ };
+};
+
+&UART1 {
+ status = "okay";
+};
+
+&GPIO0 {
+ status = "okay";
+};
+
+&IIC0 {
+ status = "okay";
+ /* Boot ROM is at 0x52-0x53, do not touch */
+ /* Unknown chip at 0x6e, not sure what it is */
+};
+
+&EMAC0 {
+ status = "okay";
+
+ phy-mode = "rgmii-id";
+ phy-map = <0x2>;
+ phy-address = <0x1>;
+ phy-handle = <&phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&POB0 {
+ leds {
+ compatible = "gpio-leds";
+
+ status: power-green {
+ label = "mr24:green:power";
+ gpios = <&GPIO0 18 GPIO_ACTIVE_LOW>;
+ };
+
+ failsafe: power-orange {
+ label = "mr24:orange:power";
+ gpios = <&GPIO0 19 GPIO_ACTIVE_LOW>;
+ };
+
+ lan {
+ label = "mr24:green:wan";
+ gpios = <&GPIO0 17 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-0 {
+ label = "mr24:green:wifi1";
+ gpios = <&GPIO0 23 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-1 {
+ label = "mr24:green:wifi2";
+ gpios = <&GPIO0 22 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-2 {
+ label = "mr24:green:wifi3";
+ gpios = <&GPIO0 21 GPIO_ACTIVE_LOW>;
+ };
+
+ ssi-3 {
+ label = "mr24:green:wifi4";
+ gpios = <&GPIO0 20 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ /* Label as per Meraki's "MR24 Installation Guide" */
+ label = "Factory Reset Button";
+ linux,code = <KEY_RESTART>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x15 IRQ_TYPE_EDGE_FALLING>;
+ gpios = <&GPIO0 16 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+};
+
+&PCIE0 {
+ status = "okay";
+ /*
+ * relevant lspci topology:
+ *
+ * -+-[0000:40]---00.0-[41-7f]----00.0-[42-45]--+-02.0-[43]----00.0
+ * +-03.0-[44]----00.0
+ *
+ */
+
+ bridge@64,0 {
+ reg = <0x00400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bridge@65,0 {
+ /* IDT PES3T3 PCI Express Switch */
+ compatible = "pci111d,8039";
+ reg = <0x00410000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ bridge@66,2 {
+ compatible = "pci111d,8039";
+ reg = <0x00421000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi0: wifi@67,0 {
+ /* Atheros AR9380 2.4GHz */
+ compatible = "pci168c,0030";
+ reg = <0x00430000 0 0 0 0>;
+ };
+ };
+
+ bridge@66,3 {
+ compatible = "pci111d,8039";
+ reg = <0x00421800 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi1: wifi@68,0 {
+ /* Atheros AR9380 5GHz */
+ compatible = "pci168c,0030";
+ reg = <0x00440000 0 0 0 0>;
+ };
+ };
+ };
+ };
+};
+
+&MSI {
+ status = "okay";
+};
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 1122702c804a..7d479928fd48 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -60,6 +60,7 @@ static char *board[] __initdata = {
"amcc,taishan",
"amcc,yosemite",
"mosaixtech,icon",
+ "meraki,mr24",
"wd,mybooklive",
};
--
2.28.0
^ permalink raw reply related
* [RFC PATCH v1 0/4] powerpc: apm82181: adding customer devices
From: Christian Lamparter @ 2020-08-12 22:41 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
Hello,
I've been holding on to these devices dts' for a while now.
But ever since the recent purge of the PPC405, I'm feeling
the urge to move forward.
The devices in question have been running with OpenWrt since
around 2016/2017. Back then it was linux v4.4 and required
many out-of-tree patches (for WIFI, SATA, CRYPTO...), that
since have been integrated. So, there's nothing else in the
way I think.
Now, I've looked around in the arch/powerpc for recent .dts
and device submissions to get an understanding of what is
required.
From the looks of it, it seems like every device gets a
skeleton defconfig and a CONFIG_$DEVICE symbol (Like:
CONFIG_MERAKI_MR24, CONFIG_WD_MYBOOKLIVE).
Will this be the case? Or would it make sense to further
unite the Bluestone, MR24 and MBL under a common CONFIG_APM82181
and integrate the BLUESTONE device's defconfig into it as well?
(I've stumbled accross the special machine compatible
handling of ppc in the Documentation/devicetree/usage-model.rst
already.)
Cheers,
Christian
Note:
If someone has a WD MyBook Live (DUO) and is interested in
giving it a spin with 5.8. I've made a:
"build your own Debian System" sort of script that can be
found on github: <https://github.com/chunkeey/mbl-debian>
(the only remaining patch hack is for debian's make-kpkg crossbuild)
Furthermore, the OpenWrt project currently has images for the
following apm82181 devices:
Cisco Meraki MX60(W) - Needs DSA for the AR8327
Netgear WNDAP620/WNDAP660 - (Could be next)
Netgear WNDR4700 - Needs DSA for the AR8327
Note2: I do have a stash of extensive APM82181 related documentation.
Christian Lamparter (4):
powerpc: apm82181: create shared dtsi for APM bluestone
powerpc: apm82181: add WD MyBook Live NAS
powerpc: apm82181: add Meraki MR24 AP
powerpc: apm82181: integrate bluestone.dts
arch/powerpc/boot/dts/apm82181.dtsi | 485 +++++++++++++++++++++
arch/powerpc/boot/dts/bluestone.dts | 456 +++++--------------
arch/powerpc/boot/dts/meraki-mr24.dts | 237 ++++++++++
arch/powerpc/boot/dts/wd-mybooklive.dts | 199 +++++++++
arch/powerpc/platforms/44x/ppc44x_simple.c | 4 +-
5 files changed, 1033 insertions(+), 348 deletions(-)
create mode 100644 arch/powerpc/boot/dts/apm82181.dtsi
create mode 100644 arch/powerpc/boot/dts/meraki-mr24.dts
create mode 100644 arch/powerpc/boot/dts/wd-mybooklive.dts
--
2.28.0
^ permalink raw reply
* [RFC PATCH v1 4/4] powerpc: apm82181: integrate bluestone.dts
From: Christian Lamparter @ 2020-08-12 22:41 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
In-Reply-To: <0732d462e1f727dc95898bd33cdde920ce81e2ff.1597271958.git.chunkeey@gmail.com>
This patch tries to integrate the existing bluestone.dts into the
apm82181.dtsi framework.
The original bluestone.dts produces a peculiar warning message.
> bluestone.dts:120.10-125.4: Warning (i2c_bus_reg):
> /plb/opb/i2c@ef600700/sttm@4C: I2C bus unit address format error, expected "4c"
For now, this has been kept alone.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/boot/dts/bluestone.dts | 456 +++++++---------------------
1 file changed, 109 insertions(+), 347 deletions(-)
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index cc965a1816b6..bf83bdaa8ec9 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -8,388 +8,150 @@
/dts-v1/;
+#include "apm82181.dtsi"
+
/ {
- #address-cells = <2>;
- #size-cells = <1>;
model = "apm,bluestone";
compatible = "apm,bluestone";
- dcr-parent = <&{/cpus/cpu@0}>;
aliases {
- ethernet0 = &EMAC0;
serial0 = &UART0;
serial1 = &UART1;
};
+};
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- model = "PowerPC,apm821xx";
- reg = <0x00000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- timebase-frequency = <0>; /* Filled in by U-Boot */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- dcr-controller;
- dcr-access-method = "native";
- next-level-cache = <&L2C0>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
- };
+&CRYPTO {
+ status = "okay";
+};
- UIC0: interrupt-controller0 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <0>;
- dcr-reg = <0x0c0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- };
+&PKA {
+ status = "okay";
+};
- UIC1: interrupt-controller1 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <1>;
- dcr-reg = <0x0d0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
+&TRNG {
+ status = "okay";
+};
- UIC2: interrupt-controller2 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <2>;
- dcr-reg = <0x0e0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
+&EBC0 {
+ status = "okay";
- UIC3: interrupt-controller3 {
- compatible = "ibm,uic";
- interrupt-controller;
- cell-index = <3>;
- dcr-reg = <0x0f0 0x009>;
- #address-cells = <0>;
- #size-cells = <0>;
- #interrupt-cells = <2>;
- interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
- interrupt-parent = <&UIC0>;
- };
-
- OCM: ocm@400040000 {
- compatible = "ibm,ocm";
+ nor_flash@0,0 {
status = "okay";
- cell-index = <1>;
- /* configured in U-Boot */
- reg = <4 0x00040000 0x8000>; /* 32K */
- };
-
- SDR0: sdr {
- compatible = "ibm,sdr-apm821xx";
- dcr-reg = <0x00e 0x002>;
- };
-
- CPR0: cpr {
- compatible = "ibm,cpr-apm821xx";
- dcr-reg = <0x00c 0x002>;
- };
-
- L2C0: l2c {
- compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
- dcr-reg = <0x020 0x008
- 0x030 0x008>;
- cache-line-size = <32>;
- cache-size = <262144>;
- interrupt-parent = <&UIC1>;
- interrupts = <11 1>;
- };
- plb {
- compatible = "ibm,plb4";
- #address-cells = <2>;
+ compatible = "amd,s29gl512n", "cfi-flash";
+ bank-width = <2>;
+ reg = <0x00000000 0x00000000 0x00400000>;
+ #address-cells = <1>;
#size-cells = <1>;
- ranges;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- SDRAM0: sdram {
- compatible = "ibm,sdram-apm821xx";
- dcr-reg = <0x010 0x002>;
+ partition@0 {
+ label = "kernel";
+ reg = <0x00000000 0x00180000>;
};
-
- MAL0: mcmal {
- compatible = "ibm,mcmal2";
- descriptor-memory = "ocm";
- dcr-reg = <0x180 0x062>;
- num-tx-chans = <1>;
- num-rx-chans = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-parent = <&UIC2>;
- interrupts = < /*TXEOB*/ 0x6 0x4
- /*RXEOB*/ 0x7 0x4
- /*SERR*/ 0x3 0x4
- /*TXDE*/ 0x4 0x4
- /*RXDE*/ 0x5 0x4>;
+ partition@180000 {
+ label = "env";
+ reg = <0x00180000 0x00020000>;
+ };
+ partition@1a0000 {
+ label = "u-boot";
+ reg = <0x001a0000 0x00060000>;
};
+ };
+
+ ndfc@1,0 {
+ status = "okay";
- POB0: opb {
- compatible = "ibm,opb";
+ /* 2Gb Nand Flash */
+ nand {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
- clock-frequency = <0>; /* Filled in by U-Boot */
-
- EBC0: ebc {
- compatible = "ibm,ebc";
- dcr-reg = <0x012 0x002>;
- #address-cells = <2>;
- #size-cells = <1>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- /* ranges property is supplied by U-Boot */
- ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
- interrupts = <0x6 0x4>;
- interrupt-parent = <&UIC1>;
-
- nor_flash@0,0 {
- compatible = "amd,s29gl512n", "cfi-flash";
- bank-width = <2>;
- reg = <0x00000000 0x00000000 0x00400000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "kernel";
- reg = <0x00000000 0x00180000>;
- };
- partition@180000 {
- label = "env";
- reg = <0x00180000 0x00020000>;
- };
- partition@1a0000 {
- label = "u-boot";
- reg = <0x001a0000 0x00060000>;
- };
- };
- ndfc@1,0 {
- compatible = "ibm,ndfc";
- reg = <0x00000003 0x00000000 0x00002000>;
- ccr = <0x00001000>;
- bank-settings = <0x80002222>;
- #address-cells = <1>;
- #size-cells = <1>;
- /* 2Gb Nand Flash */
- nand {
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "firmware";
- reg = <0x00000000 0x00C00000>;
- };
- partition@c00000 {
- label = "environment";
- reg = <0x00C00000 0x00B00000>;
- };
- partition@1700000 {
- label = "kernel";
- reg = <0x01700000 0x00E00000>;
- };
- partition@2500000 {
- label = "root";
- reg = <0x02500000 0x08200000>;
- };
- partition@a700000 {
- label = "device-tree";
- reg = <0x0A700000 0x00B00000>;
- };
- partition@b200000 {
- label = "config";
- reg = <0x0B200000 0x00D00000>;
- };
- partition@bf00000 {
- label = "diag";
- reg = <0x0BF00000 0x00C00000>;
- };
- partition@cb00000 {
- label = "vendor";
- reg = <0x0CB00000 0x3500000>;
- };
- };
- };
+ partition@0 {
+ label = "firmware";
+ reg = <0x00000000 0x00C00000>;
};
-
- UART0: serial@ef600300 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600300 0x00000008>;
- virtual-reg = <0xef600300>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC1>;
- interrupts = <0x1 0x4>;
+ partition@c00000 {
+ label = "environment";
+ reg = <0x00C00000 0x00B00000>;
};
-
- UART1: serial@ef600400 {
- device_type = "serial";
- compatible = "ns16550";
- reg = <0xef600400 0x00000008>;
- virtual-reg = <0xef600400>;
- clock-frequency = <0>; /* Filled in by U-Boot */
- current-speed = <0>; /* Filled in by U-Boot */
- interrupt-parent = <&UIC0>;
- interrupts = <0x1 0x4>;
+ partition@1700000 {
+ label = "kernel";
+ reg = <0x01700000 0x00E00000>;
};
-
- IIC0: i2c@ef600700 {
- compatible = "ibm,iic";
- reg = <0xef600700 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x2 0x4>;
- #address-cells = <1>;
- #size-cells = <0>;
- rtc@68 {
- compatible = "st,m41t80";
- reg = <0x68>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x9 0x8>;
- };
- sttm@4C {
- compatible = "adm,adm1032";
- reg = <0x4C>;
- interrupt-parent = <&UIC1>;
- interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
- };
+ partition@2500000 {
+ label = "root";
+ reg = <0x02500000 0x08200000>;
};
-
- IIC1: i2c@ef600800 {
- compatible = "ibm,iic";
- reg = <0xef600800 0x00000014>;
- interrupt-parent = <&UIC0>;
- interrupts = <0x3 0x4>;
+ partition@a700000 {
+ label = "device-tree";
+ reg = <0x0A700000 0x00B00000>;
};
-
- RGMII0: emac-rgmii@ef601500 {
- compatible = "ibm,rgmii";
- reg = <0xef601500 0x00000008>;
- has-mdio;
+ partition@b200000 {
+ label = "config";
+ reg = <0x0B200000 0x00D00000>;
};
-
- TAH0: emac-tah@ef601350 {
- compatible = "ibm,tah";
- reg = <0xef601350 0x00000030>;
+ partition@bf00000 {
+ label = "diag";
+ reg = <0x0BF00000 0x00C00000>;
};
-
- EMAC0: ethernet@ef600c00 {
- device_type = "network";
- compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
- interrupt-parent = <&EMAC0>;
- interrupts = <0x0 0x1>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
- /*Wake*/ 0x1 &UIC2 0x14 0x4>;
- reg = <0xef600c00 0x000000c4>;
- local-mac-address = [000000000000]; /* Filled in by U-Boot */
- mal-device = <&MAL0>;
- mal-tx-channel = <0>;
- mal-rx-channel = <0>;
- cell-index = <0>;
- max-frame-size = <9000>;
- rx-fifo-size = <16384>;
- tx-fifo-size = <2048>;
- phy-mode = "rgmii";
- phy-map = <0x00000000>;
- rgmii-device = <&RGMII0>;
- rgmii-channel = <0>;
- tah-device = <&TAH0>;
- tah-channel = <0>;
- has-inverted-stacr-oc;
- has-new-stacr-staopc;
+ partition@cb00000 {
+ label = "vendor";
+ reg = <0x0CB00000 0x3500000>;
};
};
+ };
+};
- PCIE0: pciex@d00000000 {
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
- primary;
- port = <0x0>; /* port number */
- reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
- 0x0000000c 0x08010000 0x00001000>; /* Registers */
- dcr-reg = <0x100 0x020>;
- sdr-base = <0x300>;
+&UART0 {
+ status = "okay";
+};
- /* Outbound ranges, one memory and one IO,
- * later cannot be changed
- */
- ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
- 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
- 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
+&UART1 {
+ status = "okay";
+};
- /* Inbound 2GB range starting at 0 */
- dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
+&IIC0 {
+ status = "okay";
+ rtc@68 {
+ compatible = "st,m41t80";
+ reg = <0x68>;
+ interrupt-parent = <&UIC0>;
+ interrupts = <0x9 0x8>;
+ };
+ sttm@4C {
+ compatible = "adm,adm1032";
+ reg = <0x4C>;
+ interrupt-parent = <&UIC1>;
+ interrupts = <0x1E 0x8>; /* CPU_THERNAL_L */
+ };
+};
- /* This drives busses 40 to 0x7f */
- bus-range = <0x40 0x7f>;
+&IIC1 {
+ status = "okay";
+};
- /* Legacy interrupts (note the weird polarity, the bridge seems
- * to invert PCIe legacy interrupts).
- * We are de-swizzling here because the numbers are actually for
- * port of the root complex virtual P2P bridge. But I want
- * to avoid putting a node for it in the tree, so the numbers
- * below are basically de-swizzled numbers.
- * The real slot is on idsel 0, so the swizzling is 1:1
- */
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <
- 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
- 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
- 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
- 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
- };
+&RGMII0 {
+ status = "okay";
+};
- MSI: ppc4xx-msi@C10000000 {
- compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
- reg = < 0xC 0x10000000 0x100
- 0xC 0x10000000 0x100>;
- sdr-base = <0x36C>;
- msi-data = <0x00004440>;
- msi-mask = <0x0000ffe0>;
- interrupts =<0 1 2 3 4 5 6 7>;
- interrupt-parent = <&MSI>;
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- msi-available-ranges = <0x0 0x100>;
- interrupt-map = <
- 0 &UIC3 0x18 1
- 1 &UIC3 0x19 1
- 2 &UIC3 0x1A 1
- 3 &UIC3 0x1B 1
- 4 &UIC3 0x1C 1
- 5 &UIC3 0x1D 1
- 6 &UIC3 0x1E 1
- 7 &UIC3 0x1F 1
- >;
- };
- };
+&TAH0 {
+ status = "okay";
+};
+
+&MAL0 {
+ status = "okay";
+};
+
+&EMAC0 {
+ status = "okay";
+ local-mac-address = [000000000000]; /* Filled in by U-Boot */
+ phy-mode = "rgmii";
+ phy-map = <0x00000000>;
+};
+
+&PCIE0 {
+ status = "okay";
+};
+
+&MSI {
+ status = "okay";
};
--
2.28.0
^ permalink raw reply related
* [RFC PATCH v1 2/4] powerpc: apm82181: add WD MyBook Live NAS
From: Christian Lamparter @ 2020-08-12 22:41 UTC (permalink / raw)
To: linuxppc-dev, devicetree; +Cc: Paul Mackerras, Rob Herring, Chris Blake
In-Reply-To: <15a94dddc15d29bac02439beb77fd066771c747a.1597271958.git.chunkeey@gmail.com>
This patch adds the device-tree definitions for
Western Digital MyBook Live NAS devices.
Technically, this devicetree file is shared by two, very
similar devices.
There's the My Book Live and the My Book Live Duo. WD's uboot
on the device will enable/disable the nodes for the device.
Ready to go images and install instruction can be found @OpenWrt.org
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/boot/dts/wd-mybooklive.dts | 199 +++++++++++++++++++++
arch/powerpc/platforms/44x/ppc44x_simple.c | 3 +-
2 files changed, 201 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/boot/dts/wd-mybooklive.dts
diff --git a/arch/powerpc/boot/dts/wd-mybooklive.dts b/arch/powerpc/boot/dts/wd-mybooklive.dts
new file mode 100644
index 000000000000..0871cc17bc9d
--- /dev/null
+++ b/arch/powerpc/boot/dts/wd-mybooklive.dts
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * (c) Copyright 2010 Western Digital Technologies, Inc. All Rights Reserved.
+ */
+
+/dts-v1/;
+
+#include "apm82181.dtsi"
+
+/ {
+ compatible = "wd,mybooklive";
+ model = "MyBook Live";
+
+ aliases {
+ serial0 = &UART0;
+ };
+};
+
+&POB0 {
+ ebc {
+ nor_flash@0,0 {
+ status = "okay";
+ compatible = "amd,s29gl512n", "jedec-probe", "cfi-flash", "mtd-rom";
+ bank-width = <1>;
+ reg = <0x00000000 0x00000000 0x00080000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ /* Part of bootrom - Don't use it without a jump */
+ label = "free";
+ reg = <0x00000000 0x0001e000>;
+ };
+
+ partition@1e000 {
+ label = "env";
+ reg = <0x0001e000 0x00002000>;
+ };
+
+ partition@20000 {
+ label = "uboot";
+ reg = <0x00020000 0x00050000>;
+ };
+ };
+ };
+
+ GPIO1: gpio@e0000000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0000000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ enable-button {
+ /* Defined in u-boot as: NOT_NOR
+ * "enables features other than NOR
+ * specifically, the buffer at CS2"
+ * (button).
+ *
+ * Note: This option is disabled as
+ * it prevents the system from being
+ * rebooted successfully.
+ */
+
+ gpio-hog;
+ line-name = "Enable Reset Button, disable NOR";
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-low;
+ };
+ };
+
+ GPIO2: gpio@e0100000 {
+ compatible = "wd,mbl-gpio";
+ reg-names = "dat";
+ reg = <0xe0100000 0x1>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ no-output;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ failsafe: power-red {
+ label = "mbl:red:power";
+ gpios = <&GPIO1 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "panic";
+ };
+
+ status: power-green {
+ label = "mbl:green:power";
+ gpios = <&GPIO1 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ power-blue {
+ label = "mbl:blue:power";
+ gpios = <&GPIO1 6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys-polled";
+ poll-interval = <60>; /* 3 * 20 = 60ms */
+ autorepeat;
+
+ reset-button {
+ label = "Reset button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&GPIO2 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usbpwr: usb-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power USB Core";
+ gpios = <&GPIO1 2 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ sata1pwr: sata1-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power Drive Port 1";
+ gpios = <&GPIO1 3 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on; /* needed to read OS from HDD */
+ };
+
+ sata0pwr: sata0-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "Power Drive Port 0";
+ gpios = <&GPIO1 7 GPIO_ACTIVE_LOW>;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on; /* needed to read OS from HDD */
+ };
+};
+
+&EMAC0 {
+ status = "okay";
+
+ phy-map = <0x2>;
+ phy-address = <0x1>;
+ phy-handle = <&phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&GPIO1 0 GPIO_ACTIVE_LOW>;
+
+ phy: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&CRYPTO {
+ status = "okay";
+};
+
+&PKA {
+ status = "okay";
+};
+
+&TRNG {
+ status = "okay";
+};
+
+&SATA0 {
+ status = "okay";
+
+ drive0: sata-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&SATA1 {
+ status = "okay";
+
+ drive1: sata-port@0 {
+ reg = <0>;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&UART0 {
+ status = "okay";
+};
+
+&USBOTG0 {
+ status = "okay";
+ dr_mode = "host";
+ vbus-supply = <&usbpwr>;
+};
diff --git a/arch/powerpc/platforms/44x/ppc44x_simple.c b/arch/powerpc/platforms/44x/ppc44x_simple.c
index 3dbd8ddd734a..1122702c804a 100644
--- a/arch/powerpc/platforms/44x/ppc44x_simple.c
+++ b/arch/powerpc/platforms/44x/ppc44x_simple.c
@@ -59,7 +59,8 @@ static char *board[] __initdata = {
"amcc,sequoia",
"amcc,taishan",
"amcc,yosemite",
- "mosaixtech,icon"
+ "mosaixtech,icon",
+ "wd,mybooklive",
};
static int __init ppc44x_probe(void)
--
2.28.0
^ permalink raw reply related
* Re: [PATCH v3 2/2] powerpc/uaccess: Add pre-update addressing to __get_user_asm() and __put_user_asm()
From: Segher Boessenkool @ 2020-08-12 19:37 UTC (permalink / raw)
To: Christophe Leroy; +Cc: Paul Mackerras, linuxppc-dev, linux-kernel
In-Reply-To: <13041c7df39e89ddf574ea0cdc6dedfdd9734140.1597235091.git.christophe.leroy@csgroup.eu>
On Wed, Aug 12, 2020 at 12:25:17PM +0000, Christophe Leroy wrote:
> Enable pre-update addressing mode in __get_user_asm() and __put_user_asm()
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> v3: new, splited out from patch 1.
It still looks fine to me, you can keep my Reviewed-by: :-)
Segher
^ permalink raw reply
* Re: [PATCH v2] powerpc/uaccess: Use flexible addressing with __put_user()/__get_user()
From: Segher Boessenkool @ 2020-08-12 19:30 UTC (permalink / raw)
To: Christophe Leroy; +Cc: linux-kernel, npiggin, Paul Mackerras, linuxppc-dev
In-Reply-To: <0b63e2b8-a134-9a50-2106-8ff110cf9a31@csgroup.eu>
On Wed, Aug 12, 2020 at 02:32:51PM +0200, Christophe Leroy wrote:
> Anyway, it seems that GCC doesn't make much use of the "m<>" and the
> pre-update form.
GCC does not use update form outside of inner loops much. Did you
expect anything else?
> Most of the benefit of flexible addressing seems to be
> achieved with patch 1 ie without the "m<>" constraint and update form.
Yes.
Segher
^ permalink raw reply
* Re: [PATCH v2] powerpc/pseries: explicitly reschedule during drmem_lmb list traversal
From: Tyrel Datwyler @ 2020-08-12 16:22 UTC (permalink / raw)
To: Nathan Lynch, linuxppc-dev; +Cc: cheloha, ldufour
In-Reply-To: <20200812012005.1919255-1-nathanl@linux.ibm.com>
On 8/11/20 6:20 PM, Nathan Lynch wrote:
> The drmem lmb list can have hundreds of thousands of entries, and
> unfortunately lookups take the form of linear searches. As long as
> this is the case, traversals have the potential to monopolize the CPU
> and provoke lockup reports, workqueue stalls, and the like unless
> they explicitly yield.
>
> Rather than placing cond_resched() calls within various
> for_each_drmem_lmb() loop blocks in the code, put it in the iteration
> expression of the loop macro itself so users can't omit it.
>
> Call cond_resched() on every 20th element. Each iteration of the loop
> in DLPAR code paths can involve around ten RTAS calls which can each
> take up to 250us, so this ensures the check is performed at worst
> every few milliseconds.
>
> Fixes: 6c6ea53725b3 ("powerpc/mm: Separate ibm, dynamic-memory data from DT format")
> Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com>
> ---
> arch/powerpc/include/asm/drmem.h | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> Changes since v1:
> * Add bounds assertions in drmem_lmb_next().
> * Call cond_resched() in the iterator on only every 20th element
> instead of on every iteration, to reduce overhead in tight loops.
>
> diff --git a/arch/powerpc/include/asm/drmem.h b/arch/powerpc/include/asm/drmem.h
> index 17ccc6474ab6..583277e30dd2 100644
> --- a/arch/powerpc/include/asm/drmem.h
> +++ b/arch/powerpc/include/asm/drmem.h
> @@ -8,6 +8,9 @@
> #ifndef _ASM_POWERPC_LMB_H
> #define _ASM_POWERPC_LMB_H
>
> +#include <linux/bug.h>
> +#include <linux/sched.h>
> +
> struct drmem_lmb {
> u64 base_addr;
> u32 drc_index;
> @@ -26,8 +29,21 @@ struct drmem_lmb_info {
>
> extern struct drmem_lmb_info *drmem_info;
>
> +static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb)
> +{
> + const unsigned int resched_interval = 20;
> +
> + BUG_ON(lmb < drmem_info->lmbs);
> + BUG_ON(lmb >= drmem_info->lmbs + drmem_info->n_lmbs);
I think BUG_ON is a pretty big no-no these days unless there is no other option.
-Tyrel
> +
> + if ((lmb - drmem_info->lmbs) % resched_interval == 0)
> + cond_resched();
> +
> + return ++lmb;
> +}
> +
> #define for_each_drmem_lmb_in_range(lmb, start, end) \
> - for ((lmb) = (start); (lmb) < (end); (lmb)++)
> + for ((lmb) = (start); (lmb) < (end); lmb = drmem_lmb_next(lmb))
>
> #define for_each_drmem_lmb(lmb) \
> for_each_drmem_lmb_in_range((lmb), \
>
^ permalink raw reply
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