* [PATCH 6/9] powerpc: Remove support for PowerPC 601
From: Christophe Leroy @ 2020-08-13 16:36 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <11a330af231af22874c006302a945388846f8112.1597336548.git.christophe.leroy@csgroup.eu>
PowerPC 601 has been retired.
Remove all associated specific code.
CPU_FTRS_PPC601 has CPU_FTR_COHERENT_ICACHE and CPU_FTR_COMMON.
CPU_FTR_COMMON is already present via other CPU_FTRS.
None of the remaining CPU selects CPU_FTR_COHERENT_ICACHE.
So CPU_FTRS_PPC601 can be removed from the possible features,
hence can be removed completely.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/boot/util.S | 15 +------
arch/powerpc/include/asm/cputable.h | 12 ++---
arch/powerpc/include/asm/ppc_asm.h | 3 +-
arch/powerpc/include/asm/ptrace.h | 4 --
arch/powerpc/include/asm/time.h | 2 +-
arch/powerpc/include/asm/timex.h | 3 --
arch/powerpc/kernel/btext.c | 8 +---
arch/powerpc/kernel/entry_32.S | 18 --------
arch/powerpc/kernel/head_32.S | 44 ++----------------
arch/powerpc/kernel/setup_32.c | 2 +-
arch/powerpc/kernel/traps.c | 4 --
arch/powerpc/kernel/vdso32/datapage.S | 2 -
arch/powerpc/kernel/vdso32/vdso32.lds.S | 2 -
arch/powerpc/mm/book3s32/mmu.c | 39 +++-------------
arch/powerpc/mm/ptdump/bats.c | 59 -------------------------
arch/powerpc/platforms/powermac/setup.c | 2 +-
arch/powerpc/platforms/powermac/smp.c | 4 --
17 files changed, 17 insertions(+), 206 deletions(-)
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S
index f11f0589a669..d03cdb7606dc 100644
--- a/arch/powerpc/boot/util.S
+++ b/arch/powerpc/boot/util.S
@@ -18,7 +18,7 @@
.text
-/* udelay (on non-601 processors) needs to know the period of the
+/* udelay needs to know the period of the
* timebase in nanoseconds. This used to be hardcoded to be 60ns
* (period of 66MHz/4). Now a variable is used that is initialized to
* 60 for backward compatibility, but it can be overridden as necessary
@@ -37,19 +37,6 @@ timebase_period_ns:
*/
.globl udelay
udelay:
- mfspr r4,SPRN_PVR
- srwi r4,r4,16
- cmpwi 0,r4,1 /* 601 ? */
- bne .Ludelay_not_601
-00: li r0,86 /* Instructions / microsecond? */
- mtctr r0
-10: addi r0,r0,0 /* NOP */
- bdnz 10b
- subic. r3,r3,1
- bne 00b
- blr
-
-.Ludelay_not_601:
mulli r4,r3,1000 /* nanoseconds */
/* Change r4 to be the number of ticks using:
* (nanoseconds + (timebase_period_ns - 1 )) / timebase_period_ns
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index fdddb822d564..76ce0ffd8af0 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -294,8 +294,6 @@ static inline void cpu_feature_keys_init(void) { }
#define CPU_FTR_MAYBE_CAN_NAP 0
#endif
-#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \
- CPU_FTR_COHERENT_ICACHE)
#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
@@ -511,10 +509,8 @@ static inline void cpu_feature_keys_init(void) { }
#else
enum {
CPU_FTRS_POSSIBLE =
-#ifdef CONFIG_PPC_BOOK3S_601
- CPU_FTRS_PPC601 |
-#elif defined(CONFIG_PPC_BOOK3S_32)
- CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
+#ifdef CONFIG_PPC_BOOK3S_32
+ CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
@@ -589,9 +585,7 @@ enum {
#else
enum {
CPU_FTRS_ALWAYS =
-#ifdef CONFIG_PPC_BOOK3S_601
- CPU_FTRS_PPC601 &
-#elif defined(CONFIG_PPC_BOOK3S_32)
+#ifdef CONFIG_PPC_BOOK3S_32
CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 67a421b81a50..511786f0e40d 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -401,8 +401,7 @@ END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
#define MFTBU(dest) mfspr dest, SPRN_TBRU
#endif
-/* tlbsync is not implemented on 601 */
-#if !defined(CONFIG_SMP) || defined(CONFIG_PPC_BOOK3S_601)
+#ifndef CONFIG_SMP
#define TLBSYNC
#else
#define TLBSYNC tlbsync; sync
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index 155a197c0aa1..e2c778c176a3 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -243,11 +243,7 @@ static inline void set_trap_norestart(struct pt_regs *regs)
}
#define arch_has_single_step() (1)
-#ifndef CONFIG_PPC_BOOK3S_601
#define arch_has_block_step() (true)
-#else
-#define arch_has_block_step() (false)
-#endif
#define ARCH_HAS_USER_SINGLE_STEP_REPORT
/*
diff --git a/arch/powerpc/include/asm/time.h b/arch/powerpc/include/asm/time.h
index cb326720a8a1..ce065589192a 100644
--- a/arch/powerpc/include/asm/time.h
+++ b/arch/powerpc/include/asm/time.h
@@ -39,7 +39,7 @@ struct div_result {
};
/* Accessor functions for the timebase (RTC on 601) registers. */
-#define __USE_RTC() (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
+#define __USE_RTC() (0)
#ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h
index 6047402b0a4d..95988870a57b 100644
--- a/arch/powerpc/include/asm/timex.h
+++ b/arch/powerpc/include/asm/timex.h
@@ -17,9 +17,6 @@ typedef unsigned long cycles_t;
static inline cycles_t get_cycles(void)
{
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
- return 0;
-
return mftb();
}
diff --git a/arch/powerpc/kernel/btext.c b/arch/powerpc/kernel/btext.c
index 02300edc6989..b609fb39dba8 100644
--- a/arch/powerpc/kernel/btext.c
+++ b/arch/powerpc/kernel/btext.c
@@ -95,18 +95,12 @@ void __init btext_prepare_BAT(void)
boot_text_mapped = 0;
return;
}
- if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
+ {
/* 603, 604, G3, G4, ... */
lowbits = addr & ~0xFF000000UL;
addr &= 0xFF000000UL;
disp_BAT[0] = vaddr | (BL_16M<<2) | 2;
disp_BAT[1] = addr | (_PAGE_NO_CACHE | _PAGE_GUARDED | BPP_RW);
- } else {
- /* 601 */
- lowbits = addr & ~0xFF800000UL;
- addr &= 0xFF800000UL;
- disp_BAT[0] = vaddr | (_PAGE_NO_CACHE | PP_RWXX) | 4;
- disp_BAT[1] = addr | BL_8M | 0x40;
}
logicalDisplayBase = (void *) (vaddr + lowbits);
}
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index f25ea188ecd3..8cdc8bcde703 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -811,19 +811,11 @@ _ASM_NOKPROBE_SYMBOL(fast_exception_return)
1: lis r3,exc_exit_restart_end@ha
addi r3,r3,exc_exit_restart_end@l
cmplw r12,r3
-#ifdef CONFIG_PPC_BOOK3S_601
- bge 2b
-#else
bge 3f
-#endif
lis r4,exc_exit_restart@ha
addi r4,r4,exc_exit_restart@l
cmplw r12,r4
-#ifdef CONFIG_PPC_BOOK3S_601
- blt 2b
-#else
blt 3f
-#endif
lis r3,fee_restarts@ha
tophys(r3,r3)
lwz r5,fee_restarts@l(r3)
@@ -840,7 +832,6 @@ fee_restarts:
/* aargh, a nonrecoverable interrupt, panic */
/* aargh, we don't know which trap this is */
-/* but the 601 doesn't implement the RI bit, so assume it's OK */
3:
li r10,-1
stw r10,_TRAP(r11)
@@ -1302,19 +1293,11 @@ nonrecoverable:
lis r10,exc_exit_restart_end@ha
addi r10,r10,exc_exit_restart_end@l
cmplw r12,r10
-#ifdef CONFIG_PPC_BOOK3S_601
- bgelr
-#else
bge 3f
-#endif
lis r11,exc_exit_restart@ha
addi r11,r11,exc_exit_restart@l
cmplw r12,r11
-#ifdef CONFIG_PPC_BOOK3S_601
- bltlr
-#else
blt 3f
-#endif
lis r10,ee_restarts@ha
lwz r12,ee_restarts@l(r10)
addi r12,r12,1
@@ -1322,7 +1305,6 @@ nonrecoverable:
mr r12,r11 /* restart at exc_exit_restart */
blr
3: /* OK, we can't recover, kill this process */
- /* but the 601 doesn't implement the RI bit, so assume it's OK */
lwz r3,_TRAP(r1)
andi. r0,r3,1
beq 5f
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 0865e2152d22..a7be9b76ff84 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -34,16 +34,6 @@
#include "head_32.h"
-/* 601 only have IBAT */
-#ifdef CONFIG_PPC_BOOK3S_601
-#define LOAD_BAT(n, reg, RA, RB) \
- li RA,0; \
- mtspr SPRN_IBAT##n##U,RA; \
- lwz RA,(n*16)+0(reg); \
- lwz RB,(n*16)+4(reg); \
- mtspr SPRN_IBAT##n##U,RA; \
- mtspr SPRN_IBAT##n##L,RB
-#else
#define LOAD_BAT(n, reg, RA, RB) \
/* see the comment for clear_bats() -- Cort */ \
li RA,0; \
@@ -57,7 +47,6 @@
lwz RB,(n*16)+12(reg); \
mtspr SPRN_DBAT##n##U,RA; \
mtspr SPRN_DBAT##n##L,RB
-#endif
__HEAD
.stabs "arch/powerpc/kernel/",N_SO,0,0,0f
@@ -438,7 +427,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
SystemCall:
SYSCALL_ENTRY 0xc00
-/* Single step - not used on 601 */
EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
@@ -980,8 +968,7 @@ load_up_mmu:
lwz r6,_SDR1@l(r6)
mtspr SPRN_SDR1,r6
-/* Load the BAT registers with the values set up by MMU_init.
- MMU_init takes care of whether we're on a 601 or not. */
+/* Load the BAT registers with the values set up by MMU_init. */
lis r3,BATS@ha
addi r3,r3,BATS@l
tophys(r3,r3)
@@ -1158,7 +1145,6 @@ EXPORT_SYMBOL(switch_mmu_context)
clear_bats:
li r10,0
-#ifndef CONFIG_PPC_BOOK3S_601
mtspr SPRN_DBAT0U,r10
mtspr SPRN_DBAT0L,r10
mtspr SPRN_DBAT1U,r10
@@ -1167,7 +1153,6 @@ clear_bats:
mtspr SPRN_DBAT2L,r10
mtspr SPRN_DBAT3U,r10
mtspr SPRN_DBAT3L,r10
-#endif
mtspr SPRN_IBAT0U,r10
mtspr SPRN_IBAT0L,r10
mtspr SPRN_IBAT1U,r10
@@ -1258,26 +1243,9 @@ mmu_off:
sync
RFI
-/*
- * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
- * (we keep one for debugging) and on others, we use one 256M BAT.
- */
+/* We use one BAT to map up to 256M of RAM at _PAGE_OFFSET */
initial_bats:
lis r11,PAGE_OFFSET@h
-#ifdef CONFIG_PPC_BOOK3S_601
- ori r11,r11,4 /* set up BAT registers for 601 */
- li r8,0x7f /* valid, block length = 8MB */
- mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */
- mtspr SPRN_IBAT0L,r8 /* lower BAT register */
- addis r11,r11,0x800000@h
- addis r8,r8,0x800000@h
- mtspr SPRN_IBAT1U,r11
- mtspr SPRN_IBAT1L,r8
- addis r11,r11,0x800000@h
- addis r8,r8,0x800000@h
- mtspr SPRN_IBAT2U,r11
- mtspr SPRN_IBAT2L,r8
-#else
tophys(r8,r11)
#ifdef CONFIG_SMP
ori r8,r8,0x12 /* R/W access, M=1 */
@@ -1286,11 +1254,10 @@ initial_bats:
#endif /* CONFIG_SMP */
ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
- mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */
+ mtspr SPRN_DBAT0L,r8 /* N.B. 6xx have valid */
mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
mtspr SPRN_IBAT0L,r8
mtspr SPRN_IBAT0U,r11
-#endif
isync
blr
@@ -1308,13 +1275,8 @@ setup_disp_bat:
beqlr
lwz r11,0(r8)
lwz r8,4(r8)
-#ifndef CONFIG_PPC_BOOK3S_601
mtspr SPRN_DBAT3L,r8
mtspr SPRN_DBAT3U,r11
-#else
- mtspr SPRN_IBAT3L,r8
- mtspr SPRN_IBAT3U,r11
-#endif
blr
#endif /* CONFIG_BOOTX_TEXT */
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 1823706ae076..057d6b8e9bb0 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -223,6 +223,6 @@ __init void initialize_cache_info(void)
dcache_bsize = cur_cpu_spec->dcache_bsize;
icache_bsize = cur_cpu_spec->icache_bsize;
ucache_bsize = 0;
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601) || IS_ENABLED(CONFIG_E200))
+ if (IS_ENABLED(CONFIG_E200))
ucache_bsize = icache_bsize = dcache_bsize;
}
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d1ebe152f210..c5f39f13e96e 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -529,9 +529,6 @@ void system_reset_exception(struct pt_regs *regs)
* Check if the NIP corresponds to the address of a sync
* instruction for which there is an entry in the exception
* table.
- * Note that the 601 only takes a machine check on TEA
- * (transfer error ack) signal assertion, and does not
- * set any of the top 16 bits of SRR1.
* -- paulus.
*/
static inline int check_io_access(struct pt_regs *regs)
@@ -796,7 +793,6 @@ int machine_check_generic(struct pt_regs *regs)
case 0x80000:
pr_cont("Machine check signal\n");
break;
- case 0: /* for 601 */
case 0x40000:
case 0x140000: /* 7450 MSS error and TEA */
pr_cont("Transfer error ack signal\n");
diff --git a/arch/powerpc/kernel/vdso32/datapage.S b/arch/powerpc/kernel/vdso32/datapage.S
index 217bb630f8f9..1d23e2771dba 100644
--- a/arch/powerpc/kernel/vdso32/datapage.S
+++ b/arch/powerpc/kernel/vdso32/datapage.S
@@ -47,7 +47,6 @@ V_FUNCTION_END(__kernel_get_syscall_map)
*
* returns the timebase frequency in HZ
*/
-#ifndef CONFIG_PPC_BOOK3S_601
V_FUNCTION_BEGIN(__kernel_get_tbfreq)
.cfi_startproc
mflr r12
@@ -60,4 +59,3 @@ V_FUNCTION_BEGIN(__kernel_get_tbfreq)
blr
.cfi_endproc
V_FUNCTION_END(__kernel_get_tbfreq)
-#endif
diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S
index 4c985467a668..bf1c28741c7e 100644
--- a/arch/powerpc/kernel/vdso32/vdso32.lds.S
+++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S
@@ -145,13 +145,11 @@ VERSION
__kernel_datapage_offset;
__kernel_get_syscall_map;
-#ifndef CONFIG_PPC_BOOK3S_601
__kernel_gettimeofday;
__kernel_clock_gettime;
__kernel_clock_getres;
__kernel_time;
__kernel_get_tbfreq;
-#endif
__kernel_sync_dicache;
__kernel_sync_dicache_p5;
__kernel_sigtramp32;
diff --git a/arch/powerpc/mm/book3s32/mmu.c b/arch/powerpc/mm/book3s32/mmu.c
index c0162911f6cb..f42b718ea971 100644
--- a/arch/powerpc/mm/book3s32/mmu.c
+++ b/arch/powerpc/mm/book3s32/mmu.c
@@ -74,14 +74,7 @@ static int find_free_bat(void)
{
int b;
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601)) {
- for (b = 0; b < 4; b++) {
- struct ppc_bat *bat = BATS[b];
-
- if (!(bat[0].batl & 0x40))
- return b;
- }
- } else {
+ {
int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
for (b = 0; b < n; b++) {
@@ -97,7 +90,7 @@ static int find_free_bat(void)
/*
* This function calculates the size of the larger block usable to map the
* beginning of an area based on the start address and size of that area:
- * - max block size is 8M on 601 and 256 on other 6xx.
+ * - max block size is 256 on 6xx.
* - base address must be aligned to the block size. So the maximum block size
* is identified by the lowest bit set to 1 in the base address (for instance
* if base is 0x16000000, max size is 0x02000000).
@@ -106,7 +99,7 @@ static int find_free_bat(void)
*/
static unsigned int block_size(unsigned long base, unsigned long top)
{
- unsigned int max_size = IS_ENABLED(CONFIG_PPC_BOOK3S_601) ? SZ_8M : SZ_256M;
+ unsigned int max_size = SZ_256M;
unsigned int base_shift = (ffs(base) - 1) & 31;
unsigned int block_shift = (fls(top - base) - 1) & 31;
@@ -117,7 +110,6 @@ static unsigned int block_size(unsigned long base, unsigned long top)
* Set up one of the IBAT (block address translation) register pairs.
* The parameters are not checked; in particular size must be a power
* of 2 between 128k and 256M.
- * Only for 603+ ...
*/
static void setibat(int index, unsigned long virt, phys_addr_t phys,
unsigned int size, pgprot_t prot)
@@ -207,9 +199,6 @@ void mmu_mark_initmem_nx(void)
unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
unsigned long size;
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
- return;
-
for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) {
size = block_size(base, top);
setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
@@ -246,9 +235,6 @@ void mmu_mark_rodata_ro(void)
int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
int i;
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
- return;
-
for (i = 0; i < nb; i++) {
struct ppc_bat *bat = BATS[i];
@@ -287,8 +273,7 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys,
flags &= ~_PAGE_COHERENT;
bl = (size >> 17) - 1;
- if (!IS_ENABLED(CONFIG_PPC_BOOK3S_601)) {
- /* 603, 604, etc. */
+ {
/* Do DBAT first */
wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
| _PAGE_COHERENT | _PAGE_GUARDED);
@@ -305,16 +290,6 @@ void __init setbat(int index, unsigned long virt, phys_addr_t phys,
bat[0] = bat[1];
else
bat[0].batu = bat[0].batl = 0;
- } else {
- /* 601 cpu */
- if (bl > BL_8M)
- bl = BL_8M;
- wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
- | _PAGE_COHERENT);
- wimgxpp |= (flags & _PAGE_RW)?
- ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
- bat->batu = virt | wimgxpp | 4; /* Ks=0, Ku=1 */
- bat->batl = phys | bl | 0x40; /* V=1 */
}
bat_addrs[index].start = virt;
@@ -467,11 +442,7 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
*/
BUG_ON(first_memblock_base != 0);
- /* 601 can only access 16MB at the moment */
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
- memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
- else /* Anything else has 256M mapped */
- memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));
+ memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M));
}
void __init print_system_hash_info(void)
diff --git a/arch/powerpc/mm/ptdump/bats.c b/arch/powerpc/mm/ptdump/bats.c
index e29b338d499f..c4c628b03cf8 100644
--- a/arch/powerpc/mm/ptdump/bats.c
+++ b/arch/powerpc/mm/ptdump/bats.c
@@ -12,62 +12,6 @@
#include "ptdump.h"
-static char *pp_601(int k, int pp)
-{
- if (pp == 0)
- return k ? " " : "rwx";
- if (pp == 1)
- return k ? "r x" : "rwx";
- if (pp == 2)
- return "rwx";
- return "r x";
-}
-
-static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper)
-{
- u32 blpi = upper & 0xfffe0000;
- u32 k = (upper >> 2) & 3;
- u32 pp = upper & 3;
- phys_addr_t pbn = PHYS_BAT_ADDR(lower);
- u32 bsm = lower & 0x3ff;
- u32 size = (bsm + 1) << 17;
-
- seq_printf(m, "%d: ", idx);
- if (!(lower & 0x40)) {
- seq_puts(m, " -\n");
- return;
- }
-
- seq_printf(m, "0x%08x-0x%08x ", blpi, blpi + size - 1);
-#ifdef CONFIG_PHYS_64BIT
- seq_printf(m, "0x%016llx ", pbn);
-#else
- seq_printf(m, "0x%08x ", pbn);
-#endif
- pt_dump_size(m, size);
-
- seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp));
-
- seq_puts(m, lower & _PAGE_WRITETHRU ? "w " : " ");
- seq_puts(m, lower & _PAGE_NO_CACHE ? "i " : " ");
- seq_puts(m, lower & _PAGE_COHERENT ? "m " : " ");
- seq_puts(m, "\n");
-}
-
-#define BAT_SHOW_601(_m, _n, _l, _u) bat_show_601(_m, _n, mfspr(_l), mfspr(_u))
-
-static int bats_show_601(struct seq_file *m, void *v)
-{
- seq_puts(m, "---[ Block Address Translation ]---\n");
-
- BAT_SHOW_601(m, 0, SPRN_IBAT0L, SPRN_IBAT0U);
- BAT_SHOW_601(m, 1, SPRN_IBAT1L, SPRN_IBAT1U);
- BAT_SHOW_601(m, 2, SPRN_IBAT2L, SPRN_IBAT2U);
- BAT_SHOW_601(m, 3, SPRN_IBAT3L, SPRN_IBAT3U);
-
- return 0;
-}
-
static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool is_d)
{
u32 bepi = upper & 0xfffe0000;
@@ -146,9 +90,6 @@ static int bats_show_603(struct seq_file *m, void *v)
static int bats_open(struct inode *inode, struct file *file)
{
- if (IS_ENABLED(CONFIG_PPC_BOOK3S_601))
- return single_open(file, bats_show_601, NULL);
-
return single_open(file, bats_show_603, NULL);
}
diff --git a/arch/powerpc/platforms/powermac/setup.c b/arch/powerpc/platforms/powermac/setup.c
index f002b0fa69b8..2e2cc0c75d87 100644
--- a/arch/powerpc/platforms/powermac/setup.c
+++ b/arch/powerpc/platforms/powermac/setup.c
@@ -284,7 +284,7 @@ static void __init pmac_setup_arch(void)
/* 604, G3, G4 etc. */
loops_per_jiffy = *fp / HZ;
else
- /* 601, 603, etc. */
+ /* 603, etc. */
loops_per_jiffy = *fp / (2 * HZ);
of_node_put(cpu);
break;
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index eb23264910e1..02f79396a284 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -270,10 +270,6 @@ static void __init smp_psurge_probe(void)
int i, ncpus;
struct device_node *dn;
- /* We don't do SMP on the PPC601 -- paulus */
- if (PVR_VER(mfspr(SPRN_PVR)) == 1)
- return;
-
/*
* The powersurge cpu board can be used in the generation
* of powermacs that have a socket for an upgradeable cpu card,
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] arch/powerpc: use simple i2c probe function
From: Luca Ceresoli @ 2020-08-13 13:14 UTC (permalink / raw)
To: Stephen Kitt, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Scott Wood, linuxppc-dev
Cc: linux-i2c, linux-kernel
In-Reply-To: <20200807152713.381588-1-steve@sk2.org>
Hi,
On 07/08/20 17:27, Stephen Kitt wrote:
> The i2c probe functions here don't use the id information provided in
> their second argument, so the single-parameter i2c probe function
> ("probe_new") can be used instead.
>
> This avoids scanning the identifier tables during probes.
>
> Signed-off-by: Stephen Kitt <steve@sk2.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
--
Luca
^ permalink raw reply
* Re: [PATCH] sfc_ef100: Fix build failure on powerpc
From: Edward Cree @ 2020-08-13 14:55 UTC (permalink / raw)
To: Christophe Leroy, Solarflare linux maintainers, Martin Habets,
David S. Miller, Jakub Kicinski
Cc: netdev, linuxppc-dev, linux-kernel
In-Reply-To: <44e26ec6a1bc01b5b138c29b623c83d5846718b2.1597329390.git.christophe.leroy@csgroup.eu>
On 13/08/2020 15:39, Christophe Leroy wrote:
> ppc6xx_defconfig fails building sfc.ko module, complaining
> about the lack of _umoddi3 symbol.
>
> This is due to the following test
>
> if (EFX_MIN_DMAQ_SIZE % reader->value) {
>
> Because reader->value is u64.
Already fixed in net.git by 41077c990266 ("sfc: fix ef100 design-param checking").
But thanks anyway.
^ permalink raw reply
* Re: [RFC PATCH 1/2] powerpc/numa: Introduce logical numa id
From: Nathan Lynch @ 2020-08-13 22:53 UTC (permalink / raw)
To: Aneesh Kumar K.V; +Cc: linuxppc-dev, Srikar Dronamraju
In-Reply-To: <87eeof4q87.fsf@linux.ibm.com>
Hi Aneesh,
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
> "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
>> On 8/8/20 2:15 AM, Nathan Lynch wrote:
>>> "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
>>>> On 8/7/20 9:54 AM, Nathan Lynch wrote:
>>>>> "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
>>>>>> diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
>>>>>> index e437a9ac4956..6c659aada55b 100644
>>>>>> --- a/arch/powerpc/mm/numa.c
>>>>>> +++ b/arch/powerpc/mm/numa.c
>>>>>> @@ -221,25 +221,51 @@ static void initialize_distance_lookup_table(int nid,
>>>>>> }
>>>>>> }
>>>>>>
>>>>>> +static u32 nid_map[MAX_NUMNODES] = {[0 ... MAX_NUMNODES - 1] = NUMA_NO_NODE};
>>>>>
>>>>> It's odd to me to use MAX_NUMNODES for this array when it's going to be
>>>>> indexed not by Linux's logical node IDs but by the platform-provided
>>>>> domain number, which has no relation to MAX_NUMNODES.
>>>>
>>>>
>>>> I didn't want to dynamically allocate this. We could fetch
>>>> "ibm,max-associativity-domains" to find the size for that. The current
>>>> code do assume firmware group id to not exceed MAX_NUMNODES. Hence kept
>>>> the array size to be MAX_NUMNODEs. I do agree that it is confusing. May
>>>> be we can do #define MAX_AFFINITY_DOMAIN MAX_NUMNODES?
>>>
>>> Well, consider:
>>>
>>> - ibm,max-associativity-domains can change at runtime with LPM. This
>>> doesn't happen in practice yet, but we should probably start thinking
>>> about how to support that.
>>> - The domain numbering isn't clearly specified to have any particular
>>> properties such as beginning at zero or a contiguous range.
>>>
>>> While the current code likely contains assumptions contrary to these
>>> points, a change such as this is an opportunity to think about whether
>>> those assumptions can be reduced or removed. In particular I think it
>>> would be good to gracefully degrade when the number of NUMA affinity
>>> domains can exceed MAX_NUMNODES. Using the platform-supplied domain
>>> numbers to directly index Linux data structures will make that
>>> impossible.
>>>
>>> So, maybe genradix or even xarray wouldn't actually be overengineering
>>> here.
>>>
>>
>> One of the challenges with such a data structure is that we initialize
>> the nid_map before the slab is available. This means a memblock based
>> allocation and we would end up implementing such a sparse data structure
>> ourselves here.
Yes, good point.
>> As you mentioned above, since we know that hypervisor as of now limits
>> the max affinity domain id below ibm,max-associativity-domains we are
>> good with an array-like nid_map we have here. This keeps the code simpler.
>>
>> This will also allow us to switch to a more sparse data structure as you
>> requested here in the future because the main change that is pushed in
>> this series is the usage of firmare_group_id_to_nid(). The details of
>> the data structure we use to keep track of that mapping are pretty much
>> internal to that function.
>
> How about this? This makes it not a direct index. But it do limit the
> search to max numa node on the system.
>
> static int domain_id_map[MAX_NUMNODES] = {[0 ... MAX_NUMNODES - 1] = -1 };
>
> static int __affinity_domain_to_nid(int domain_id, int max_nid)
> {
> int i;
>
> for (i = 0; i < max_nid; i++) {
> if (domain_id_map[i] == domain_id)
> return i;
> }
> return NUMA_NO_NODE;
> }
OK, this indexes the array by Linux's node id, good. I was wondering if
I could persuade you do flip it around like this :-)
Walking through the code below:
> int affinity_domain_to_nid(struct affinity_domain *domain)
> {
> int nid, domain_id;
> static int last_nid = 0;
> static DEFINE_SPINLOCK(node_id_lock);
>
> domain_id = domain->id;
> /*
> * For PowerNV we don't change the node id. This helps to avoid
> * confusion w.r.t the expected node ids. On pseries, node numbers
> * are virtualized. Hence do logical node id for pseries.
> */
> if (!firmware_has_feature(FW_FEATURE_LPAR))
> return domain_id;
>
> if (domain_id == -1 || last_nid == MAX_NUMNODES)
> return NUMA_NO_NODE;
>
> nid = __affinity_domain_to_nid(domain_id, last_nid);
So this is pseries fast path. Attempt to look up the Linux node for the
given domain, where last_nid is the highest-numbered node in use so
far. If the result is in [0..last_nid] we're done.
>
> if (nid == NUMA_NO_NODE) {
> spin_lock(&node_id_lock);
If the lookup fails enter the critical section. As we discussed offline,
this is a precaution for potentially parallel device probing.
> /* recheck with lock held */
> nid = __affinity_domain_to_nid(domain_id, last_nid);
Attempt the same lookup again. If the result is in [0..last_nid],
another thread has just initialized the mapping for this domain and
we're done.
> if (nid == NUMA_NO_NODE) {
> nid = last_nid++;
> domain_id_map[nid] = domain_id;
> }
If the lookup fails again, "allocate" the next unused Linux node
number. Otherwise use the result returned by the second call to
__affinity_domain_to_nid().
> spin_unlock(&node_id_lock);
> }
>
> return nid;
> }
Generally I agree with this approach. I don't quite get the locking. I
understand there could be a need for a lockless fast path, but as
written I don't think last_nid is appropriately protected - two
slow-path threads could cause an increment to be "lost" since last_nid
is loaded before taking the lock.
^ permalink raw reply
* Re: [PATCH] powerpc/papr_scm: Limit the readability of 'perf_stats' sysfs attribute
From: Michael Ellerman @ 2020-08-14 1:29 UTC (permalink / raw)
To: Aneesh Kumar K.V, Vaibhav Jain, linuxppc-dev, linux-nvdimm
Cc: Oliver O'Halloran, Dan Williams, Ira Weiny, Santosh Sivaraj
In-Reply-To: <13e82e40-35c7-266c-2ec0-5fcdcb5fb27f@linux.ibm.com>
"Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> writes:
> On 8/13/20 10:04 AM, Vaibhav Jain wrote:
>> The newly introduced 'perf_stats' attribute uses the default access
>> mode of 0444 letting non-root users access performance stats of an
>> nvdimm and potentially force the kernel into issuing large number of
>> expensive HCALLs. Since the information exposed by this attribute
>> cannot be cached hence its better to ward of access to this attribute
>> from users who don't need to access these performance statistics.
>>
>> Hence this patch adds check in perf_stats_show() to only let users
>> that are 'perfmon_capable()' to read the nvdimm performance
>> statistics.
>>
>> Fixes: 2d02bf835e573 ('powerpc/papr_scm: Fetch nvdimm performance stats from PHYP')
>> Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
>> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
>> ---
>> arch/powerpc/platforms/pseries/papr_scm.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/powerpc/platforms/pseries/papr_scm.c b/arch/powerpc/platforms/pseries/papr_scm.c
>> index f439f0dfea7d1..36c51bf8af9a8 100644
>> --- a/arch/powerpc/platforms/pseries/papr_scm.c
>> +++ b/arch/powerpc/platforms/pseries/papr_scm.c
>> @@ -792,6 +792,10 @@ static ssize_t perf_stats_show(struct device *dev,
>> struct nvdimm *dimm = to_nvdimm(dev);
>> struct papr_scm_priv *p = nvdimm_provider_data(dimm);
>>
>> + /* Allow access only to perfmon capable users */
>> + if (!perfmon_capable())
>> + return -EACCES;
>> +
>
> An access check is usually done in open(). This is the read callback IIUC.
Yes. Otherwise an unprivileged user can open the file, and then trick a
suid program into reading from it.
cheers
^ permalink raw reply
* fsl_espi errors on v5.7.15
From: Chris Packham @ 2020-08-14 2:48 UTC (permalink / raw)
To: broonie@kernel.org, mpe@ellerman.id.au, benh@kernel.crashing.org,
paulus@samba.org, Heiner Kallweit,
tiago.brusamarello@datacom.ind.br
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org
Hi,
I'm seeing a problem with accessing spi-nor after upgrading a T2081
based system to linux v5.7.15
For this board u-boot and the u-boot environment live on spi-nor.
When I use fw_setenv from userspace I get the following kernel logs
# fw_setenv foo=1
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
...
If I run fw_printenv (before getting it into a bad state) it is able to
display the content of the boards u-boot environment.
If been unsuccessful in producing a setup for bisecting the issue. I do
know the issue doesn't occur on the old 4.4.x based kernel but that's
probably not much help.
Any pointers on what the issue (and/or solution) might be.
Thanks,
Chris
^ permalink raw reply
* Re: BUG: unable to handle kernel paging request in fl_dump_key
From: syzbot @ 2020-08-14 2:53 UTC (permalink / raw)
To: benh, dalias, davem, jhogan, jhs, jiri, jiri, kuba, linux-kernel,
linux-kselftest, linux-mips, linux-sh, linuxppc-dev, mpe, netdev,
paul.burton, paulus, ralf, shuah, syzkaller-bugs, xiyou.wangcong,
ysato
In-Reply-To: <000000000000735f5205a5b02279@google.com>
syzbot has bisected this issue to:
commit a51486266c3ba8e035a47fa96df67f274fe0c7d0
Author: Jiri Pirko <jiri@mellanox.com>
Date: Sat Jun 15 09:03:49 2019 +0000
net: sched: remove NET_CLS_IND config option
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=17463509900000
start commit: 1ca0fafd tcp: md5: allow changing MD5 keys in all socket s..
git tree: net
final oops: https://syzkaller.appspot.com/x/report.txt?x=14c63509900000
console output: https://syzkaller.appspot.com/x/log.txt?x=10c63509900000
kernel config: https://syzkaller.appspot.com/x/.config?x=bf3aec367b9ab569
dashboard link: https://syzkaller.appspot.com/bug?extid=9c1be56e9317b795e874
syz repro: https://syzkaller.appspot.com/x/repro.syz?x=1062a40b100000
Reported-by: syzbot+9c1be56e9317b795e874@syzkaller.appspotmail.com
Fixes: a51486266c3b ("net: sched: remove NET_CLS_IND config option")
For information about bisection process see: https://goo.gl/tpsmEJ#bisection
^ permalink raw reply
* [PATCH] powerpc: Add POWER10 raw mode cputable entry
From: Madhavan Srinivasan @ 2020-08-14 3:59 UTC (permalink / raw)
To: mpe; +Cc: Madhavan Srinivasan, linuxppc-dev
Add a raw mode cputable entry for POWER10. Copies most of the fields
from commit a3ea40d5c736 ("powerpc: Add POWER10 architected mode")
except for oprofile_cpu_type, machine_check_early, pvr_mask and pvr_mask
filed. On bare metal systems we use DT CPU features, which doesn't need a
cputable entry. But in VMs we still rely on the raw cputable entry to
set the correct values for the PMU related fields.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
arch/powerpc/kernel/cputable.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b4066354f0730..1e052f53e5dca 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -541,6 +541,25 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check_early = __machine_check_early_realmode_p9,
.platform = "power9",
},
+ { /* Power10 */
+ .pvr_mask = 0xffff0000,
+ .pvr_value = 0x00800000,
+ .cpu_name = "POWER10 (raw)",
+ .cpu_features = CPU_FTRS_POWER10,
+ .cpu_user_features = COMMON_USER_POWER10,
+ .cpu_user_features2 = COMMON_USER2_POWER10,
+ .mmu_features = MMU_FTRS_POWER10,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .num_pmcs = 6,
+ .pmc_type = PPC_PMC_IBM,
+ .oprofile_cpu_type = "ppc64/power10",
+ .oprofile_type = PPC_OPROFILE_INVALID,
+ .cpu_setup = __setup_cpu_power10,
+ .cpu_restore = __restore_cpu_power10,
+ .machine_check_early = __machine_check_early_realmode_p10,
+ .platform = "power10",
+ },
{ /* Cell Broadband Engine */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
--
2.26.2
^ permalink raw reply related
* [PATCH] kernel/watchdog: fix warning -Wunused-variable for watchdog_allowed_mask in ppc64
From: Balamuruhan S @ 2020-08-14 4:39 UTC (permalink / raw)
To: mpe; +Cc: ravi.bangoria, naveen.n.rao, linuxppc-dev, sandipan,
Balamuruhan S
In ppc64 config if `CONFIG_SOFTLOCKUP_DETECTOR` is not set then it
warns for unused declaration of `watchdog_allowed_mask` while building,
move the declaration inside ifdef later in the code.
```
kernel/watchdog.c:47:23: warning: ‘watchdog_allowed_mask’ defined but not used [-Wunused-variable]
static struct cpumask watchdog_allowed_mask __read_mostly;
```
Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
---
kernel/watchdog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 5abb5b22ad13..33c9b8a3d51b 100644
--- a/kernel/watchdog.c
+++ b/kernel/watchdog.c
@@ -44,7 +44,6 @@ int __read_mostly soft_watchdog_user_enabled = 1;
int __read_mostly watchdog_thresh = 10;
static int __read_mostly nmi_watchdog_available;
-static struct cpumask watchdog_allowed_mask __read_mostly;
struct cpumask watchdog_cpumask __read_mostly;
unsigned long *watchdog_cpumask_bits = cpumask_bits(&watchdog_cpumask);
@@ -166,6 +165,7 @@ int __read_mostly sysctl_softlockup_all_cpu_backtrace;
unsigned int __read_mostly softlockup_panic =
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE;
+static struct cpumask watchdog_allowed_mask __read_mostly;
static bool softlockup_initialized __read_mostly;
static u64 __read_mostly sample_period;
base-commit: a3a28c4451dff698d0c7ef5a3e80423aa5774e2b
--
2.24.1
^ permalink raw reply related
* Re: [PATCH v3] powerpc/pseries: explicitly reschedule during drmem_lmb list traversal
From: Christophe Leroy @ 2020-08-14 5:00 UTC (permalink / raw)
To: Nathan Lynch, linuxppc-dev; +Cc: cheloha, ldufour, tyreld
In-Reply-To: <20200813151131.2070161-1-nathanl@linux.ibm.com>
Le 13/08/2020 à 17:11, Nathan Lynch a écrit :
> The drmem lmb list can have hundreds of thousands of entries, and
> unfortunately lookups take the form of linear searches. As long as
> this is the case, traversals have the potential to monopolize the CPU
> and provoke lockup reports, workqueue stalls, and the like unless
> they explicitly yield.
>
> Rather than placing cond_resched() calls within various
> for_each_drmem_lmb() loop blocks in the code, put it in the iteration
> expression of the loop macro itself so users can't omit it.
>
> Introduce a drmem_lmb_next() iteration helper function which calls
> cond_resched() at a regular interval during array traversal. Each
> iteration of the loop in DLPAR code paths can involve around ten RTAS
> calls which can each take up to 250us, so this ensures the check is
> performed at worst every few milliseconds.
>
> Fixes: 6c6ea53725b3 ("powerpc/mm: Separate ibm, dynamic-memory data from DT format")
> Signed-off-by: Nathan Lynch <nathanl@linux.ibm.com>
Looks a lot better to me than v2.
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
>
> Notes:
> Changes since v2:
> * Make drmem_lmb_next() more general.
> * Adjust reschedule interval for better code generation.
> * Add commentary to drmem_lmb_next() to explain the cond_resched()
> call.
> * Remove bounds assertions.
>
> Changes since v1:
> * Add bounds assertions in drmem_lmb_next().
> * Call cond_resched() in the iterator on only every 20th element
> instead of on every iteration, to reduce overhead in tight loops.
>
> arch/powerpc/include/asm/drmem.h | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/include/asm/drmem.h b/arch/powerpc/include/asm/drmem.h
> index 17ccc6474ab6..6fb928605ed1 100644
> --- a/arch/powerpc/include/asm/drmem.h
> +++ b/arch/powerpc/include/asm/drmem.h
> @@ -8,6 +8,8 @@
> #ifndef _ASM_POWERPC_LMB_H
> #define _ASM_POWERPC_LMB_H
>
> +#include <linux/sched.h>
> +
> struct drmem_lmb {
> u64 base_addr;
> u32 drc_index;
> @@ -26,8 +28,22 @@ struct drmem_lmb_info {
>
> extern struct drmem_lmb_info *drmem_info;
>
> +static inline struct drmem_lmb *drmem_lmb_next(struct drmem_lmb *lmb,
> + const struct drmem_lmb *start)
> +{
> + /*
> + * DLPAR code paths can take several milliseconds per element
> + * when interacting with firmware. Ensure that we don't
> + * unfairly monopolize the CPU.
> + */
> + if (((++lmb - start) % 16) == 0)
> + cond_resched();
> +
> + return lmb;
> +}
> +
> #define for_each_drmem_lmb_in_range(lmb, start, end) \
> - for ((lmb) = (start); (lmb) < (end); (lmb)++)
> + for ((lmb) = (start); (lmb) < (end); lmb = drmem_lmb_next(lmb, start))
>
> #define for_each_drmem_lmb(lmb) \
> for_each_drmem_lmb_in_range((lmb), \
>
^ permalink raw reply
* [PATCH v2] powerpc: Remove flush_instruction_cache() on 8xx
From: Christophe Leroy @ 2020-08-14 5:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, hch
Cc: linuxppc-dev, linux-kernel
flush_instruction_cache() is never used on 8xx, remove it.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2: Becomes a standalone patch independant of the series dismantling the ASM flush_instruction_cache()
---
arch/powerpc/mm/nohash/8xx.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c
index d2b37146ae6c..231ca95f9ffb 100644
--- a/arch/powerpc/mm/nohash/8xx.c
+++ b/arch/powerpc/mm/nohash/8xx.c
@@ -244,13 +244,6 @@ void set_context(unsigned long id, pgd_t *pgd)
mb();
}
-void flush_instruction_cache(void)
-{
- isync();
- mtspr(SPRN_IC_CST, IDC_INVALL);
- isync();
-}
-
#ifdef CONFIG_PPC_KUEP
void __init setup_kuep(bool disabled)
{
--
2.25.0
^ permalink raw reply related
* Re: [PATCH 1/5] powerpc: Remove flush_instruction_cache for book3s/32
From: Christophe Leroy @ 2020-08-14 5:52 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: linuxppc-dev, Paul Mackerras, linux-kernel
In-Reply-To: <20200813121403.GB16237@infradead.org>
Le 13/08/2020 à 14:14, Christoph Hellwig a écrit :
> On Thu, Aug 13, 2020 at 01:13:08PM +0100, Christoph Hellwig wrote:
>> On Thu, Aug 13, 2020 at 10:12:00AM +0000, Christophe Leroy wrote:
>>> -#ifndef CONFIG_PPC_8xx
>>> +#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32)
>>> _GLOBAL(flush_instruction_cache)
>>> #if defined(CONFIG_4xx)
>>> lis r3, KERNELBASE@h
>>> @@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache)
>>> mfspr r3,SPRN_L1CSR1
>>> ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
>>> mtspr SPRN_L1CSR1,r3
>>> -#elif defined(CONFIG_PPC_BOOK3S_601)
>>> - blr /* for 601, do nothing */
>>> -#else
>>> - /* 603/604 processor - use invalidate-all bit in HID0 */
>>> - mfspr r3,SPRN_HID0
>>> - ori r3,r3,HID0_ICFI
>>> - mtspr SPRN_HID0,r3
>>> #endif /* CONFIG_4xx */
>>> isync
>>> blr
>>> EXPORT_SYMBOL(flush_instruction_cache)
>>> -#endif /* CONFIG_PPC_8xx */
>>> +#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */
>>
>> What about untangling this into entirely separate versions instead
>> of the ifdef mess? Also the export does not seem to be needed at all.
>
> Ok, I see that you do that later, sorry.
>
In v2, I drop the untangling patch, because the series completely
dismantles flush_instruction_cache() so there is no need for an
ephemeral untanggled version of it.
Christophe
^ permalink raw reply
* [PATCH v2 3/4] powerpc: Rewrite 4xx flush_cache_instruction() in C
From: Christophe Leroy @ 2020-08-14 5:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, hch
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <50098f49877cea0f46730a9df82dcabf84160e4b.1597384512.git.christophe.leroy@csgroup.eu>
Nothing prevents flush_cache_instruction() from being writen in C.
Do it to improve readability and maintainability.
This function is very small and isn't called from assembly,
make it static inline in asm/cacheflush.h
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2: Written as a static inline instead of adding a new C file for this function alone.
---
arch/powerpc/include/asm/cacheflush.h | 8 ++++++++
arch/powerpc/kernel/misc_32.S | 7 +------
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 481877879fec..138e46d8c04e 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -98,7 +98,15 @@ static inline void invalidate_dcache_range(unsigned long start,
mb(); /* sync */
}
+#ifdef CONFIG_4xx
+static inline void flush_instruction_cache(void)
+{
+ iccci((void *)KERNELBASE);
+ isync();
+}
+#else
void flush_instruction_cache(void);
+#endif
#include <asm-generic/cacheflush.h>
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 5c074c2ff5b5..1bda207459a8 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -272,12 +272,8 @@ _ASM_NOKPROBE_SYMBOL(real_writeb)
/*
* Flush instruction cache.
*/
-#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32)
+#ifdef CONFIG_FSL_BOOKE
_GLOBAL(flush_instruction_cache)
-#if defined(CONFIG_4xx)
- lis r3, KERNELBASE@h
- iccci 0,r3
-#elif defined(CONFIG_FSL_BOOKE)
#ifdef CONFIG_E200
mfspr r3,SPRN_L1CSR0
ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
@@ -289,7 +285,6 @@ _GLOBAL(flush_instruction_cache)
mfspr r3,SPRN_L1CSR1
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
mtspr SPRN_L1CSR1,r3
-#endif /* CONFIG_4xx */
isync
blr
EXPORT_SYMBOL(flush_instruction_cache)
--
2.25.0
^ permalink raw reply related
* [PATCH v2 1/4] powerpc: Remove flush_instruction_cache for book3s/32
From: Christophe Leroy @ 2020-08-14 5:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, hch
Cc: linuxppc-dev, linux-kernel
The only callers of flush_instruction_cache() are:
arch/powerpc/kernel/swsusp_booke.S: bl flush_instruction_cache
arch/powerpc/mm/nohash/40x.c: flush_instruction_cache();
arch/powerpc/mm/nohash/44x.c: flush_instruction_cache();
arch/powerpc/mm/nohash/fsl_booke.c: flush_instruction_cache();
arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache();
arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache();
This function is not used by book3s/32, drop it.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/misc_32.S | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index b24f866fef81..5c074c2ff5b5 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -271,9 +271,8 @@ _ASM_NOKPROBE_SYMBOL(real_writeb)
/*
* Flush instruction cache.
- * This is a no-op on the 601.
*/
-#ifndef CONFIG_PPC_8xx
+#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32)
_GLOBAL(flush_instruction_cache)
#if defined(CONFIG_4xx)
lis r3, KERNELBASE@h
@@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache)
mfspr r3,SPRN_L1CSR1
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
mtspr SPRN_L1CSR1,r3
-#elif defined(CONFIG_PPC_BOOK3S_601)
- blr /* for 601, do nothing */
-#else
- /* 603/604 processor - use invalidate-all bit in HID0 */
- mfspr r3,SPRN_HID0
- ori r3,r3,HID0_ICFI
- mtspr SPRN_HID0,r3
#endif /* CONFIG_4xx */
isync
blr
EXPORT_SYMBOL(flush_instruction_cache)
-#endif /* CONFIG_PPC_8xx */
+#endif
/*
* Copy a whole page. We use the dcbz instruction on the destination
--
2.25.0
^ permalink raw reply related
* [PATCH v2 2/4] powerpc: Move flush_instruction_cache() prototype in asm/cacheflush.h
From: Christophe Leroy @ 2020-08-14 5:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, hch
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <50098f49877cea0f46730a9df82dcabf84160e4b.1597384512.git.christophe.leroy@csgroup.eu>
flush_instruction_cache() belongs to the cache flushing function
family.
Move its prototype in asm/cacheflush.h
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2: new
---
arch/powerpc/include/asm/cacheflush.h | 2 ++
arch/powerpc/include/asm/processor.h | 1 -
arch/powerpc/platforms/44x/machine_check.c | 1 +
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index 54764c6e922d..481877879fec 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -98,6 +98,8 @@ static inline void invalidate_dcache_range(unsigned long start,
mb(); /* sync */
}
+void flush_instruction_cache(void);
+
#include <asm-generic/cacheflush.h>
#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index ed0d633ab5aa..d828813e35de 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -435,7 +435,6 @@ extern void power7_idle_type(unsigned long type);
extern void power9_idle_type(unsigned long stop_psscr_val,
unsigned long stop_psscr_mask);
-extern void flush_instruction_cache(void);
extern void hard_reset_now(void);
extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
diff --git a/arch/powerpc/platforms/44x/machine_check.c b/arch/powerpc/platforms/44x/machine_check.c
index 90ad6ac529d2..a5c898bb9bab 100644
--- a/arch/powerpc/platforms/44x/machine_check.c
+++ b/arch/powerpc/platforms/44x/machine_check.c
@@ -7,6 +7,7 @@
#include <linux/ptrace.h>
#include <asm/reg.h>
+#include <asm/cacheflush.h>
int machine_check_440A(struct pt_regs *regs)
{
--
2.25.0
^ permalink raw reply related
* [PATCH v2 4/4] powerpc: Rewrite FSL_BOOKE flush_cache_instruction() in C
From: Christophe Leroy @ 2020-08-14 5:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman, hch
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <50098f49877cea0f46730a9df82dcabf84160e4b.1597384512.git.christophe.leroy@csgroup.eu>
Nothing prevents flush_cache_instruction() from being writen in C.
Do it to improve readability and maintainability.
This function is only use by low level callers, it is not
intended to be used by module. Don't export it.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
arch/powerpc/kernel/misc_32.S | 22 ----------------------
arch/powerpc/mm/nohash/fsl_booke.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 22 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 1bda207459a8..87717966f5cd 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -268,28 +268,6 @@ _ASM_NOKPROBE_SYMBOL(real_writeb)
#endif /* CONFIG_40x */
-
-/*
- * Flush instruction cache.
- */
-#ifdef CONFIG_FSL_BOOKE
-_GLOBAL(flush_instruction_cache)
-#ifdef CONFIG_E200
- mfspr r3,SPRN_L1CSR0
- ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
- /* msync; isync recommended here */
- mtspr SPRN_L1CSR0,r3
- isync
- blr
-#endif
- mfspr r3,SPRN_L1CSR1
- ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
- mtspr SPRN_L1CSR1,r3
- isync
- blr
-EXPORT_SYMBOL(flush_instruction_cache)
-#endif
-
/*
* Copy a whole page. We use the dcbz instruction on the destination
* to reduce memory traffic (it eliminates the unnecessary reads of
diff --git a/arch/powerpc/mm/nohash/fsl_booke.c b/arch/powerpc/mm/nohash/fsl_booke.c
index 0c294827d6e5..36bda962d3b3 100644
--- a/arch/powerpc/mm/nohash/fsl_booke.c
+++ b/arch/powerpc/mm/nohash/fsl_booke.c
@@ -219,6 +219,22 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
}
+void flush_instruction_cache(void)
+{
+ unsigned long tmp;
+
+ if (IS_ENABLED(CONFIG_E200)) {
+ tmp = mfspr(SPRN_L1CSR0);
+ tmp |= L1CSR0_CFI | L1CSR0_CLFC;
+ mtspr(SPRN_L1CSR0, tmp);
+ } else {
+ tmp = mfspr(SPRN_L1CSR1);
+ tmp |= L1CSR1_ICFI | L1CSR1_ICLFR;
+ mtspr(SPRN_L1CSR1, tmp);
+ }
+ isync();
+}
+
/*
* MMU_init_hw does the chip-specific initialization of the MMU hardware.
*/
--
2.25.0
^ permalink raw reply related
* Re: fsl_espi errors on v5.7.15
From: Heiner Kallweit @ 2020-08-14 6:19 UTC (permalink / raw)
To: Chris Packham, broonie@kernel.org, mpe@ellerman.id.au,
benh@kernel.crashing.org, paulus@samba.org,
tiago.brusamarello@datacom.ind.br
Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-spi@vger.kernel.org
In-Reply-To: <3f48e5fb-33c9-8046-0f80-236eed163c16@alliedtelesis.co.nz>
On 14.08.2020 04:48, Chris Packham wrote:
> Hi,
>
> I'm seeing a problem with accessing spi-nor after upgrading a T2081
> based system to linux v5.7.15
>
> For this board u-boot and the u-boot environment live on spi-nor.
>
> When I use fw_setenv from userspace I get the following kernel logs
>
> # fw_setenv foo=1
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but SPIE_DON isn't set!
> fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
> fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
> fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
> fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
> fsl_espi ffe110000.spi: Transfer done but rx/tx fifo's aren't empty!
> fsl_espi ffe110000.spi: SPIE_RXCNT = 1, SPIE_TXCNT = 32
> ...
>
This error reporting doesn't exist yet in 4.4. So you may have an issue
under 4.4 too, it's just not reported.
Did you verify that under 4.4 fw_setenv actually has an effect?
> If I run fw_printenv (before getting it into a bad state) it is able to
> display the content of the boards u-boot environment.
>
This might indicate an issue with spi being locked. I've seen related
questions, just use the search engine of your choice and check for
fw_setenv and locked.
> If been unsuccessful in producing a setup for bisecting the issue. I do
> know the issue doesn't occur on the old 4.4.x based kernel but that's
> probably not much help.
>
> Any pointers on what the issue (and/or solution) might be.
>
> Thanks,
> Chris
>
Heiner
^ permalink raw reply
* Re: [PATCH] powerpc: Add POWER10 raw mode cputable entry
From: kernel test robot @ 2020-08-14 6:27 UTC (permalink / raw)
To: Madhavan Srinivasan, mpe; +Cc: linuxppc-dev, Madhavan Srinivasan, kbuild-all
In-Reply-To: <20200814035903.3179314-1-maddy@linux.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 19980 bytes --]
Hi Madhavan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on v5.8 next-20200814]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Madhavan-Srinivasan/powerpc-Add-POWER10-raw-mode-cputable-entry/20200814-120142
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-defconfig (attached as .config)
compiler: powerpc64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> arch/powerpc/kernel/cputable.c:561:26: error: '__machine_check_early_realmode_p10' undeclared here (not in a function); did you mean '__machine_check_early_realmode_p9'?
561 | .machine_check_early = __machine_check_early_realmode_p10,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| __machine_check_early_realmode_p9
vim +561 arch/powerpc/kernel/cputable.c
136
137 static struct cpu_spec __initdata cpu_specs[] = {
138 #ifdef CONFIG_PPC_BOOK3S_64
139 { /* PPC970 */
140 .pvr_mask = 0xffff0000,
141 .pvr_value = 0x00390000,
142 .cpu_name = "PPC970",
143 .cpu_features = CPU_FTRS_PPC970,
144 .cpu_user_features = COMMON_USER_POWER4 |
145 PPC_FEATURE_HAS_ALTIVEC_COMP,
146 .mmu_features = MMU_FTRS_PPC970,
147 .icache_bsize = 128,
148 .dcache_bsize = 128,
149 .num_pmcs = 8,
150 .pmc_type = PPC_PMC_IBM,
151 .cpu_setup = __setup_cpu_ppc970,
152 .cpu_restore = __restore_cpu_ppc970,
153 .oprofile_cpu_type = "ppc64/970",
154 .oprofile_type = PPC_OPROFILE_POWER4,
155 .platform = "ppc970",
156 },
157 { /* PPC970FX */
158 .pvr_mask = 0xffff0000,
159 .pvr_value = 0x003c0000,
160 .cpu_name = "PPC970FX",
161 .cpu_features = CPU_FTRS_PPC970,
162 .cpu_user_features = COMMON_USER_POWER4 |
163 PPC_FEATURE_HAS_ALTIVEC_COMP,
164 .mmu_features = MMU_FTRS_PPC970,
165 .icache_bsize = 128,
166 .dcache_bsize = 128,
167 .num_pmcs = 8,
168 .pmc_type = PPC_PMC_IBM,
169 .cpu_setup = __setup_cpu_ppc970,
170 .cpu_restore = __restore_cpu_ppc970,
171 .oprofile_cpu_type = "ppc64/970",
172 .oprofile_type = PPC_OPROFILE_POWER4,
173 .platform = "ppc970",
174 },
175 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
176 .pvr_mask = 0xffffffff,
177 .pvr_value = 0x00440100,
178 .cpu_name = "PPC970MP",
179 .cpu_features = CPU_FTRS_PPC970,
180 .cpu_user_features = COMMON_USER_POWER4 |
181 PPC_FEATURE_HAS_ALTIVEC_COMP,
182 .mmu_features = MMU_FTRS_PPC970,
183 .icache_bsize = 128,
184 .dcache_bsize = 128,
185 .num_pmcs = 8,
186 .pmc_type = PPC_PMC_IBM,
187 .cpu_setup = __setup_cpu_ppc970,
188 .cpu_restore = __restore_cpu_ppc970,
189 .oprofile_cpu_type = "ppc64/970MP",
190 .oprofile_type = PPC_OPROFILE_POWER4,
191 .platform = "ppc970",
192 },
193 { /* PPC970MP */
194 .pvr_mask = 0xffff0000,
195 .pvr_value = 0x00440000,
196 .cpu_name = "PPC970MP",
197 .cpu_features = CPU_FTRS_PPC970,
198 .cpu_user_features = COMMON_USER_POWER4 |
199 PPC_FEATURE_HAS_ALTIVEC_COMP,
200 .mmu_features = MMU_FTRS_PPC970,
201 .icache_bsize = 128,
202 .dcache_bsize = 128,
203 .num_pmcs = 8,
204 .pmc_type = PPC_PMC_IBM,
205 .cpu_setup = __setup_cpu_ppc970MP,
206 .cpu_restore = __restore_cpu_ppc970,
207 .oprofile_cpu_type = "ppc64/970MP",
208 .oprofile_type = PPC_OPROFILE_POWER4,
209 .platform = "ppc970",
210 },
211 { /* PPC970GX */
212 .pvr_mask = 0xffff0000,
213 .pvr_value = 0x00450000,
214 .cpu_name = "PPC970GX",
215 .cpu_features = CPU_FTRS_PPC970,
216 .cpu_user_features = COMMON_USER_POWER4 |
217 PPC_FEATURE_HAS_ALTIVEC_COMP,
218 .mmu_features = MMU_FTRS_PPC970,
219 .icache_bsize = 128,
220 .dcache_bsize = 128,
221 .num_pmcs = 8,
222 .pmc_type = PPC_PMC_IBM,
223 .cpu_setup = __setup_cpu_ppc970,
224 .oprofile_cpu_type = "ppc64/970",
225 .oprofile_type = PPC_OPROFILE_POWER4,
226 .platform = "ppc970",
227 },
228 { /* Power5 GR */
229 .pvr_mask = 0xffff0000,
230 .pvr_value = 0x003a0000,
231 .cpu_name = "POWER5 (gr)",
232 .cpu_features = CPU_FTRS_POWER5,
233 .cpu_user_features = COMMON_USER_POWER5,
234 .mmu_features = MMU_FTRS_POWER5,
235 .icache_bsize = 128,
236 .dcache_bsize = 128,
237 .num_pmcs = 6,
238 .pmc_type = PPC_PMC_IBM,
239 .oprofile_cpu_type = "ppc64/power5",
240 .oprofile_type = PPC_OPROFILE_POWER4,
241 /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
242 * and above but only works on POWER5 and above
243 */
244 .oprofile_mmcra_sihv = MMCRA_SIHV,
245 .oprofile_mmcra_sipr = MMCRA_SIPR,
246 .platform = "power5",
247 },
248 { /* Power5++ */
249 .pvr_mask = 0xffffff00,
250 .pvr_value = 0x003b0300,
251 .cpu_name = "POWER5+ (gs)",
252 .cpu_features = CPU_FTRS_POWER5,
253 .cpu_user_features = COMMON_USER_POWER5_PLUS,
254 .mmu_features = MMU_FTRS_POWER5,
255 .icache_bsize = 128,
256 .dcache_bsize = 128,
257 .num_pmcs = 6,
258 .oprofile_cpu_type = "ppc64/power5++",
259 .oprofile_type = PPC_OPROFILE_POWER4,
260 .oprofile_mmcra_sihv = MMCRA_SIHV,
261 .oprofile_mmcra_sipr = MMCRA_SIPR,
262 .platform = "power5+",
263 },
264 { /* Power5 GS */
265 .pvr_mask = 0xffff0000,
266 .pvr_value = 0x003b0000,
267 .cpu_name = "POWER5+ (gs)",
268 .cpu_features = CPU_FTRS_POWER5,
269 .cpu_user_features = COMMON_USER_POWER5_PLUS,
270 .mmu_features = MMU_FTRS_POWER5,
271 .icache_bsize = 128,
272 .dcache_bsize = 128,
273 .num_pmcs = 6,
274 .pmc_type = PPC_PMC_IBM,
275 .oprofile_cpu_type = "ppc64/power5+",
276 .oprofile_type = PPC_OPROFILE_POWER4,
277 .oprofile_mmcra_sihv = MMCRA_SIHV,
278 .oprofile_mmcra_sipr = MMCRA_SIPR,
279 .platform = "power5+",
280 },
281 { /* POWER6 in P5+ mode; 2.04-compliant processor */
282 .pvr_mask = 0xffffffff,
283 .pvr_value = 0x0f000001,
284 .cpu_name = "POWER5+",
285 .cpu_features = CPU_FTRS_POWER5,
286 .cpu_user_features = COMMON_USER_POWER5_PLUS,
287 .mmu_features = MMU_FTRS_POWER5,
288 .icache_bsize = 128,
289 .dcache_bsize = 128,
290 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
291 .oprofile_type = PPC_OPROFILE_POWER4,
292 .platform = "power5+",
293 },
294 { /* Power6 */
295 .pvr_mask = 0xffff0000,
296 .pvr_value = 0x003e0000,
297 .cpu_name = "POWER6 (raw)",
298 .cpu_features = CPU_FTRS_POWER6,
299 .cpu_user_features = COMMON_USER_POWER6 |
300 PPC_FEATURE_POWER6_EXT,
301 .mmu_features = MMU_FTRS_POWER6,
302 .icache_bsize = 128,
303 .dcache_bsize = 128,
304 .num_pmcs = 6,
305 .pmc_type = PPC_PMC_IBM,
306 .oprofile_cpu_type = "ppc64/power6",
307 .oprofile_type = PPC_OPROFILE_POWER4,
308 .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
309 .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
310 .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
311 POWER6_MMCRA_OTHER,
312 .platform = "power6x",
313 },
314 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
315 .pvr_mask = 0xffffffff,
316 .pvr_value = 0x0f000002,
317 .cpu_name = "POWER6 (architected)",
318 .cpu_features = CPU_FTRS_POWER6,
319 .cpu_user_features = COMMON_USER_POWER6,
320 .mmu_features = MMU_FTRS_POWER6,
321 .icache_bsize = 128,
322 .dcache_bsize = 128,
323 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
324 .oprofile_type = PPC_OPROFILE_POWER4,
325 .platform = "power6",
326 },
327 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
328 .pvr_mask = 0xffffffff,
329 .pvr_value = 0x0f000003,
330 .cpu_name = "POWER7 (architected)",
331 .cpu_features = CPU_FTRS_POWER7,
332 .cpu_user_features = COMMON_USER_POWER7,
333 .cpu_user_features2 = COMMON_USER2_POWER7,
334 .mmu_features = MMU_FTRS_POWER7,
335 .icache_bsize = 128,
336 .dcache_bsize = 128,
337 .oprofile_type = PPC_OPROFILE_POWER4,
338 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
339 .cpu_setup = __setup_cpu_power7,
340 .cpu_restore = __restore_cpu_power7,
341 .machine_check_early = __machine_check_early_realmode_p7,
342 .platform = "power7",
343 },
344 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
345 .pvr_mask = 0xffffffff,
346 .pvr_value = 0x0f000004,
347 .cpu_name = "POWER8 (architected)",
348 .cpu_features = CPU_FTRS_POWER8,
349 .cpu_user_features = COMMON_USER_POWER8,
350 .cpu_user_features2 = COMMON_USER2_POWER8,
351 .mmu_features = MMU_FTRS_POWER8,
352 .icache_bsize = 128,
353 .dcache_bsize = 128,
354 .oprofile_type = PPC_OPROFILE_INVALID,
355 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
356 .cpu_setup = __setup_cpu_power8,
357 .cpu_restore = __restore_cpu_power8,
358 .machine_check_early = __machine_check_early_realmode_p8,
359 .platform = "power8",
360 },
361 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
362 .pvr_mask = 0xffffffff,
363 .pvr_value = 0x0f000005,
364 .cpu_name = "POWER9 (architected)",
365 .cpu_features = CPU_FTRS_POWER9,
366 .cpu_user_features = COMMON_USER_POWER9,
367 .cpu_user_features2 = COMMON_USER2_POWER9,
368 .mmu_features = MMU_FTRS_POWER9,
369 .icache_bsize = 128,
370 .dcache_bsize = 128,
371 .oprofile_type = PPC_OPROFILE_INVALID,
372 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
373 .cpu_setup = __setup_cpu_power9,
374 .cpu_restore = __restore_cpu_power9,
375 .platform = "power9",
376 },
377 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
378 .pvr_mask = 0xffffffff,
379 .pvr_value = 0x0f000006,
380 .cpu_name = "POWER10 (architected)",
381 .cpu_features = CPU_FTRS_POWER10,
382 .cpu_user_features = COMMON_USER_POWER10,
383 .cpu_user_features2 = COMMON_USER2_POWER10,
384 .mmu_features = MMU_FTRS_POWER10,
385 .icache_bsize = 128,
386 .dcache_bsize = 128,
387 .oprofile_type = PPC_OPROFILE_INVALID,
388 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
389 .cpu_setup = __setup_cpu_power10,
390 .cpu_restore = __restore_cpu_power10,
391 .platform = "power10",
392 },
393 { /* Power7 */
394 .pvr_mask = 0xffff0000,
395 .pvr_value = 0x003f0000,
396 .cpu_name = "POWER7 (raw)",
397 .cpu_features = CPU_FTRS_POWER7,
398 .cpu_user_features = COMMON_USER_POWER7,
399 .cpu_user_features2 = COMMON_USER2_POWER7,
400 .mmu_features = MMU_FTRS_POWER7,
401 .icache_bsize = 128,
402 .dcache_bsize = 128,
403 .num_pmcs = 6,
404 .pmc_type = PPC_PMC_IBM,
405 .oprofile_cpu_type = "ppc64/power7",
406 .oprofile_type = PPC_OPROFILE_POWER4,
407 .cpu_setup = __setup_cpu_power7,
408 .cpu_restore = __restore_cpu_power7,
409 .machine_check_early = __machine_check_early_realmode_p7,
410 .platform = "power7",
411 },
412 { /* Power7+ */
413 .pvr_mask = 0xffff0000,
414 .pvr_value = 0x004A0000,
415 .cpu_name = "POWER7+ (raw)",
416 .cpu_features = CPU_FTRS_POWER7,
417 .cpu_user_features = COMMON_USER_POWER7,
418 .cpu_user_features2 = COMMON_USER2_POWER7,
419 .mmu_features = MMU_FTRS_POWER7,
420 .icache_bsize = 128,
421 .dcache_bsize = 128,
422 .num_pmcs = 6,
423 .pmc_type = PPC_PMC_IBM,
424 .oprofile_cpu_type = "ppc64/power7",
425 .oprofile_type = PPC_OPROFILE_POWER4,
426 .cpu_setup = __setup_cpu_power7,
427 .cpu_restore = __restore_cpu_power7,
428 .machine_check_early = __machine_check_early_realmode_p7,
429 .platform = "power7+",
430 },
431 { /* Power8E */
432 .pvr_mask = 0xffff0000,
433 .pvr_value = 0x004b0000,
434 .cpu_name = "POWER8E (raw)",
435 .cpu_features = CPU_FTRS_POWER8E,
436 .cpu_user_features = COMMON_USER_POWER8,
437 .cpu_user_features2 = COMMON_USER2_POWER8,
438 .mmu_features = MMU_FTRS_POWER8,
439 .icache_bsize = 128,
440 .dcache_bsize = 128,
441 .num_pmcs = 6,
442 .pmc_type = PPC_PMC_IBM,
443 .oprofile_cpu_type = "ppc64/power8",
444 .oprofile_type = PPC_OPROFILE_INVALID,
445 .cpu_setup = __setup_cpu_power8,
446 .cpu_restore = __restore_cpu_power8,
447 .machine_check_early = __machine_check_early_realmode_p8,
448 .platform = "power8",
449 },
450 { /* Power8NVL */
451 .pvr_mask = 0xffff0000,
452 .pvr_value = 0x004c0000,
453 .cpu_name = "POWER8NVL (raw)",
454 .cpu_features = CPU_FTRS_POWER8,
455 .cpu_user_features = COMMON_USER_POWER8,
456 .cpu_user_features2 = COMMON_USER2_POWER8,
457 .mmu_features = MMU_FTRS_POWER8,
458 .icache_bsize = 128,
459 .dcache_bsize = 128,
460 .num_pmcs = 6,
461 .pmc_type = PPC_PMC_IBM,
462 .oprofile_cpu_type = "ppc64/power8",
463 .oprofile_type = PPC_OPROFILE_INVALID,
464 .cpu_setup = __setup_cpu_power8,
465 .cpu_restore = __restore_cpu_power8,
466 .machine_check_early = __machine_check_early_realmode_p8,
467 .platform = "power8",
468 },
469 { /* Power8 */
470 .pvr_mask = 0xffff0000,
471 .pvr_value = 0x004d0000,
472 .cpu_name = "POWER8 (raw)",
473 .cpu_features = CPU_FTRS_POWER8,
474 .cpu_user_features = COMMON_USER_POWER8,
475 .cpu_user_features2 = COMMON_USER2_POWER8,
476 .mmu_features = MMU_FTRS_POWER8,
477 .icache_bsize = 128,
478 .dcache_bsize = 128,
479 .num_pmcs = 6,
480 .pmc_type = PPC_PMC_IBM,
481 .oprofile_cpu_type = "ppc64/power8",
482 .oprofile_type = PPC_OPROFILE_INVALID,
483 .cpu_setup = __setup_cpu_power8,
484 .cpu_restore = __restore_cpu_power8,
485 .machine_check_early = __machine_check_early_realmode_p8,
486 .platform = "power8",
487 },
488 { /* Power9 DD2.0 */
489 .pvr_mask = 0xffffefff,
490 .pvr_value = 0x004e0200,
491 .cpu_name = "POWER9 (raw)",
492 .cpu_features = CPU_FTRS_POWER9_DD2_0,
493 .cpu_user_features = COMMON_USER_POWER9,
494 .cpu_user_features2 = COMMON_USER2_POWER9,
495 .mmu_features = MMU_FTRS_POWER9,
496 .icache_bsize = 128,
497 .dcache_bsize = 128,
498 .num_pmcs = 6,
499 .pmc_type = PPC_PMC_IBM,
500 .oprofile_cpu_type = "ppc64/power9",
501 .oprofile_type = PPC_OPROFILE_INVALID,
502 .cpu_setup = __setup_cpu_power9,
503 .cpu_restore = __restore_cpu_power9,
504 .machine_check_early = __machine_check_early_realmode_p9,
505 .platform = "power9",
506 },
507 { /* Power9 DD 2.1 */
508 .pvr_mask = 0xffffefff,
509 .pvr_value = 0x004e0201,
510 .cpu_name = "POWER9 (raw)",
511 .cpu_features = CPU_FTRS_POWER9_DD2_1,
512 .cpu_user_features = COMMON_USER_POWER9,
513 .cpu_user_features2 = COMMON_USER2_POWER9,
514 .mmu_features = MMU_FTRS_POWER9,
515 .icache_bsize = 128,
516 .dcache_bsize = 128,
517 .num_pmcs = 6,
518 .pmc_type = PPC_PMC_IBM,
519 .oprofile_cpu_type = "ppc64/power9",
520 .oprofile_type = PPC_OPROFILE_INVALID,
521 .cpu_setup = __setup_cpu_power9,
522 .cpu_restore = __restore_cpu_power9,
523 .machine_check_early = __machine_check_early_realmode_p9,
524 .platform = "power9",
525 },
526 { /* Power9 DD2.2 or later */
527 .pvr_mask = 0xffff0000,
528 .pvr_value = 0x004e0000,
529 .cpu_name = "POWER9 (raw)",
530 .cpu_features = CPU_FTRS_POWER9_DD2_2,
531 .cpu_user_features = COMMON_USER_POWER9,
532 .cpu_user_features2 = COMMON_USER2_POWER9,
533 .mmu_features = MMU_FTRS_POWER9,
534 .icache_bsize = 128,
535 .dcache_bsize = 128,
536 .num_pmcs = 6,
537 .pmc_type = PPC_PMC_IBM,
538 .oprofile_cpu_type = "ppc64/power9",
539 .oprofile_type = PPC_OPROFILE_INVALID,
540 .cpu_setup = __setup_cpu_power9,
541 .cpu_restore = __restore_cpu_power9,
542 .machine_check_early = __machine_check_early_realmode_p9,
543 .platform = "power9",
544 },
545 { /* Power10 */
546 .pvr_mask = 0xffff0000,
547 .pvr_value = 0x00800000,
548 .cpu_name = "POWER10 (raw)",
549 .cpu_features = CPU_FTRS_POWER10,
550 .cpu_user_features = COMMON_USER_POWER10,
551 .cpu_user_features2 = COMMON_USER2_POWER10,
552 .mmu_features = MMU_FTRS_POWER10,
553 .icache_bsize = 128,
554 .dcache_bsize = 128,
555 .num_pmcs = 6,
556 .pmc_type = PPC_PMC_IBM,
557 .oprofile_cpu_type = "ppc64/power10",
558 .oprofile_type = PPC_OPROFILE_INVALID,
559 .cpu_setup = __setup_cpu_power10,
560 .cpu_restore = __restore_cpu_power10,
> 561 .machine_check_early = __machine_check_early_realmode_p10,
562 .platform = "power10",
563 },
564 { /* Cell Broadband Engine */
565 .pvr_mask = 0xffff0000,
566 .pvr_value = 0x00700000,
567 .cpu_name = "Cell Broadband Engine",
568 .cpu_features = CPU_FTRS_CELL,
569 .cpu_user_features = COMMON_USER_PPC64 |
570 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
571 PPC_FEATURE_SMT,
572 .mmu_features = MMU_FTRS_CELL,
573 .icache_bsize = 128,
574 .dcache_bsize = 128,
575 .num_pmcs = 4,
576 .pmc_type = PPC_PMC_IBM,
577 .oprofile_cpu_type = "ppc64/cell-be",
578 .oprofile_type = PPC_OPROFILE_CELL,
579 .platform = "ppc-cell-be",
580 },
581 { /* PA Semi PA6T */
582 .pvr_mask = 0x7fff0000,
583 .pvr_value = 0x00900000,
584 .cpu_name = "PA6T",
585 .cpu_features = CPU_FTRS_PA6T,
586 .cpu_user_features = COMMON_USER_PA6T,
587 .mmu_features = MMU_FTRS_PA6T,
588 .icache_bsize = 64,
589 .dcache_bsize = 64,
590 .num_pmcs = 6,
591 .pmc_type = PPC_PMC_PA6T,
592 .cpu_setup = __setup_cpu_pa6t,
593 .cpu_restore = __restore_cpu_pa6t,
594 .oprofile_cpu_type = "ppc64/pa6t",
595 .oprofile_type = PPC_OPROFILE_PA6T,
596 .platform = "pa6t",
597 },
598 { /* default match */
599 .pvr_mask = 0x00000000,
600 .pvr_value = 0x00000000,
601 .cpu_name = "POWER5 (compatible)",
602 .cpu_features = CPU_FTRS_COMPATIBLE,
603 .cpu_user_features = COMMON_USER_PPC64,
604 .mmu_features = MMU_FTRS_POWER,
605 .icache_bsize = 128,
606 .dcache_bsize = 128,
607 .num_pmcs = 6,
608 .pmc_type = PPC_PMC_IBM,
609 .platform = "power5",
610 }
611 #endif /* CONFIG_PPC_BOOK3S_64 */
612
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 26274 bytes --]
^ permalink raw reply
* [PATCH v2] powerpc: Drop _nmask_and_or_msr()
From: Christophe Leroy @ 2020-08-14 6:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras, Michael Ellerman
Cc: linuxppc-dev, linux-kernel
_nmask_and_or_msr() is only used at two places to set MSR_IP.
The SYNC is unnecessary as the users are not PowerPC 601.
Can be easily writen in C.
Do it, and drop _nmask_and_or_msr()
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
---
v2: Removed the prototype in asm/processor.h
---
arch/powerpc/include/asm/processor.h | 1 -
arch/powerpc/kernel/misc_32.S | 13 -------------
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c | 3 ++-
arch/powerpc/platforms/embedded6xx/storcenter.c | 3 ++-
4 files changed, 4 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index ed0d633ab5aa..5f6b3ee84dd1 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -441,7 +441,6 @@ extern void poweroff_now(void);
extern int fix_alignment(struct pt_regs *);
extern void cvt_fd(float *from, double *to);
extern void cvt_df(double *from, float *to);
-extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
#ifdef CONFIG_PPC64
/*
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index b24f866fef81..8d9cb5df580e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -215,19 +215,6 @@ _GLOBAL(low_choose_7447a_dfs)
#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
-/*
- * complement mask on the msr then "or" some values on.
- * _nmask_and_or_msr(nmask, value_to_or)
- */
-_GLOBAL(_nmask_and_or_msr)
- mfmsr r0 /* Get current msr */
- andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
- or r0,r0,r4 /* Or on the bits in r4 (second parm) */
- SYNC /* Some chip revs have problems here... */
- mtmsr r0 /* Update machine state */
- isync
- blr /* Done */
-
#ifdef CONFIG_40x
/*
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 15437abe1f6d..b95c3380d2b5 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -147,7 +147,8 @@ static void __noreturn mpc7448_hpc2_restart(char *cmd)
local_irq_disable();
/* Set exception prefix high - to the firmware */
- _nmask_and_or_msr(0, MSR_IP);
+ mtmsr(mfmsr() | MSR_IP);
+ isync();
for (;;) ; /* Spin until reset happens */
}
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c
index ed1914dd34bb..e346ddcef45e 100644
--- a/arch/powerpc/platforms/embedded6xx/storcenter.c
+++ b/arch/powerpc/platforms/embedded6xx/storcenter.c
@@ -101,7 +101,8 @@ static void __noreturn storcenter_restart(char *cmd)
local_irq_disable();
/* Set exception prefix high - to the firmware */
- _nmask_and_or_msr(0, MSR_IP);
+ mtmsr(mfmsr() | MSR_IP);
+ isync();
/* Wait for reset to happen */
for (;;) ;
--
2.25.0
^ permalink raw reply related
* Re: [PATCH] powerpc: Add POWER10 raw mode cputable entry
From: Madhavan Srinivasan @ 2020-08-14 7:20 UTC (permalink / raw)
To: kernel test robot, mpe; +Cc: linuxppc-dev, kbuild-all
In-Reply-To: <202008141438.ZTQh1pcI%lkp@intel.com>
On 8/14/20 11:57 AM, kernel test robot wrote:
> Hi Madhavan,
>
> Thank you for the patch! Yet something to improve:
>
> [auto build test ERROR on powerpc/next]
> [also build test ERROR on v5.8 next-20200814]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
>
> url: https://github.com/0day-ci/linux/commits/Madhavan-Srinivasan/powerpc-Add-POWER10-raw-mode-cputable-entry/20200814-120142
> base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
> config: powerpc-defconfig (attached as .config)
> compiler: powerpc64-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
>>> arch/powerpc/kernel/cputable.c:561:26: error: '__machine_check_early_realmode_p10' undeclared here (not in a function); did you mean '__machine_check_early_realmode_p9'?
> 561 | .machine_check_early = __machine_check_early_realmode_p10,
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> | __machine_check_early_realmode_p9
Yes, i did hit this in my compile check and i added the below line,
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b4066354f073..b22216db5c71 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -75,6 +75,7 @@ extern void __restore_cpu_power10(void);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p10(struct pt_regs *regs);
#endif /* CONFIG_PPC64 */
#if defined(CONFIG_E500)
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec*
spec);
but my bad, i sent the one i internally reviewed which did not have it.
I will send again. Sorry
Maddy
> vim +561 arch/powerpc/kernel/cputable.c
>
> 136
> 137 static struct cpu_spec __initdata cpu_specs[] = {
> 138 #ifdef CONFIG_PPC_BOOK3S_64
> 139 { /* PPC970 */
> 140 .pvr_mask = 0xffff0000,
> 141 .pvr_value = 0x00390000,
> 142 .cpu_name = "PPC970",
> 143 .cpu_features = CPU_FTRS_PPC970,
> 144 .cpu_user_features = COMMON_USER_POWER4 |
> 145 PPC_FEATURE_HAS_ALTIVEC_COMP,
> 146 .mmu_features = MMU_FTRS_PPC970,
> 147 .icache_bsize = 128,
> 148 .dcache_bsize = 128,
> 149 .num_pmcs = 8,
> 150 .pmc_type = PPC_PMC_IBM,
> 151 .cpu_setup = __setup_cpu_ppc970,
> 152 .cpu_restore = __restore_cpu_ppc970,
> 153 .oprofile_cpu_type = "ppc64/970",
> 154 .oprofile_type = PPC_OPROFILE_POWER4,
> 155 .platform = "ppc970",
> 156 },
> 157 { /* PPC970FX */
> 158 .pvr_mask = 0xffff0000,
> 159 .pvr_value = 0x003c0000,
> 160 .cpu_name = "PPC970FX",
> 161 .cpu_features = CPU_FTRS_PPC970,
> 162 .cpu_user_features = COMMON_USER_POWER4 |
> 163 PPC_FEATURE_HAS_ALTIVEC_COMP,
> 164 .mmu_features = MMU_FTRS_PPC970,
> 165 .icache_bsize = 128,
> 166 .dcache_bsize = 128,
> 167 .num_pmcs = 8,
> 168 .pmc_type = PPC_PMC_IBM,
> 169 .cpu_setup = __setup_cpu_ppc970,
> 170 .cpu_restore = __restore_cpu_ppc970,
> 171 .oprofile_cpu_type = "ppc64/970",
> 172 .oprofile_type = PPC_OPROFILE_POWER4,
> 173 .platform = "ppc970",
> 174 },
> 175 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
> 176 .pvr_mask = 0xffffffff,
> 177 .pvr_value = 0x00440100,
> 178 .cpu_name = "PPC970MP",
> 179 .cpu_features = CPU_FTRS_PPC970,
> 180 .cpu_user_features = COMMON_USER_POWER4 |
> 181 PPC_FEATURE_HAS_ALTIVEC_COMP,
> 182 .mmu_features = MMU_FTRS_PPC970,
> 183 .icache_bsize = 128,
> 184 .dcache_bsize = 128,
> 185 .num_pmcs = 8,
> 186 .pmc_type = PPC_PMC_IBM,
> 187 .cpu_setup = __setup_cpu_ppc970,
> 188 .cpu_restore = __restore_cpu_ppc970,
> 189 .oprofile_cpu_type = "ppc64/970MP",
> 190 .oprofile_type = PPC_OPROFILE_POWER4,
> 191 .platform = "ppc970",
> 192 },
> 193 { /* PPC970MP */
> 194 .pvr_mask = 0xffff0000,
> 195 .pvr_value = 0x00440000,
> 196 .cpu_name = "PPC970MP",
> 197 .cpu_features = CPU_FTRS_PPC970,
> 198 .cpu_user_features = COMMON_USER_POWER4 |
> 199 PPC_FEATURE_HAS_ALTIVEC_COMP,
> 200 .mmu_features = MMU_FTRS_PPC970,
> 201 .icache_bsize = 128,
> 202 .dcache_bsize = 128,
> 203 .num_pmcs = 8,
> 204 .pmc_type = PPC_PMC_IBM,
> 205 .cpu_setup = __setup_cpu_ppc970MP,
> 206 .cpu_restore = __restore_cpu_ppc970,
> 207 .oprofile_cpu_type = "ppc64/970MP",
> 208 .oprofile_type = PPC_OPROFILE_POWER4,
> 209 .platform = "ppc970",
> 210 },
> 211 { /* PPC970GX */
> 212 .pvr_mask = 0xffff0000,
> 213 .pvr_value = 0x00450000,
> 214 .cpu_name = "PPC970GX",
> 215 .cpu_features = CPU_FTRS_PPC970,
> 216 .cpu_user_features = COMMON_USER_POWER4 |
> 217 PPC_FEATURE_HAS_ALTIVEC_COMP,
> 218 .mmu_features = MMU_FTRS_PPC970,
> 219 .icache_bsize = 128,
> 220 .dcache_bsize = 128,
> 221 .num_pmcs = 8,
> 222 .pmc_type = PPC_PMC_IBM,
> 223 .cpu_setup = __setup_cpu_ppc970,
> 224 .oprofile_cpu_type = "ppc64/970",
> 225 .oprofile_type = PPC_OPROFILE_POWER4,
> 226 .platform = "ppc970",
> 227 },
> 228 { /* Power5 GR */
> 229 .pvr_mask = 0xffff0000,
> 230 .pvr_value = 0x003a0000,
> 231 .cpu_name = "POWER5 (gr)",
> 232 .cpu_features = CPU_FTRS_POWER5,
> 233 .cpu_user_features = COMMON_USER_POWER5,
> 234 .mmu_features = MMU_FTRS_POWER5,
> 235 .icache_bsize = 128,
> 236 .dcache_bsize = 128,
> 237 .num_pmcs = 6,
> 238 .pmc_type = PPC_PMC_IBM,
> 239 .oprofile_cpu_type = "ppc64/power5",
> 240 .oprofile_type = PPC_OPROFILE_POWER4,
> 241 /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
> 242 * and above but only works on POWER5 and above
> 243 */
> 244 .oprofile_mmcra_sihv = MMCRA_SIHV,
> 245 .oprofile_mmcra_sipr = MMCRA_SIPR,
> 246 .platform = "power5",
> 247 },
> 248 { /* Power5++ */
> 249 .pvr_mask = 0xffffff00,
> 250 .pvr_value = 0x003b0300,
> 251 .cpu_name = "POWER5+ (gs)",
> 252 .cpu_features = CPU_FTRS_POWER5,
> 253 .cpu_user_features = COMMON_USER_POWER5_PLUS,
> 254 .mmu_features = MMU_FTRS_POWER5,
> 255 .icache_bsize = 128,
> 256 .dcache_bsize = 128,
> 257 .num_pmcs = 6,
> 258 .oprofile_cpu_type = "ppc64/power5++",
> 259 .oprofile_type = PPC_OPROFILE_POWER4,
> 260 .oprofile_mmcra_sihv = MMCRA_SIHV,
> 261 .oprofile_mmcra_sipr = MMCRA_SIPR,
> 262 .platform = "power5+",
> 263 },
> 264 { /* Power5 GS */
> 265 .pvr_mask = 0xffff0000,
> 266 .pvr_value = 0x003b0000,
> 267 .cpu_name = "POWER5+ (gs)",
> 268 .cpu_features = CPU_FTRS_POWER5,
> 269 .cpu_user_features = COMMON_USER_POWER5_PLUS,
> 270 .mmu_features = MMU_FTRS_POWER5,
> 271 .icache_bsize = 128,
> 272 .dcache_bsize = 128,
> 273 .num_pmcs = 6,
> 274 .pmc_type = PPC_PMC_IBM,
> 275 .oprofile_cpu_type = "ppc64/power5+",
> 276 .oprofile_type = PPC_OPROFILE_POWER4,
> 277 .oprofile_mmcra_sihv = MMCRA_SIHV,
> 278 .oprofile_mmcra_sipr = MMCRA_SIPR,
> 279 .platform = "power5+",
> 280 },
> 281 { /* POWER6 in P5+ mode; 2.04-compliant processor */
> 282 .pvr_mask = 0xffffffff,
> 283 .pvr_value = 0x0f000001,
> 284 .cpu_name = "POWER5+",
> 285 .cpu_features = CPU_FTRS_POWER5,
> 286 .cpu_user_features = COMMON_USER_POWER5_PLUS,
> 287 .mmu_features = MMU_FTRS_POWER5,
> 288 .icache_bsize = 128,
> 289 .dcache_bsize = 128,
> 290 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 291 .oprofile_type = PPC_OPROFILE_POWER4,
> 292 .platform = "power5+",
> 293 },
> 294 { /* Power6 */
> 295 .pvr_mask = 0xffff0000,
> 296 .pvr_value = 0x003e0000,
> 297 .cpu_name = "POWER6 (raw)",
> 298 .cpu_features = CPU_FTRS_POWER6,
> 299 .cpu_user_features = COMMON_USER_POWER6 |
> 300 PPC_FEATURE_POWER6_EXT,
> 301 .mmu_features = MMU_FTRS_POWER6,
> 302 .icache_bsize = 128,
> 303 .dcache_bsize = 128,
> 304 .num_pmcs = 6,
> 305 .pmc_type = PPC_PMC_IBM,
> 306 .oprofile_cpu_type = "ppc64/power6",
> 307 .oprofile_type = PPC_OPROFILE_POWER4,
> 308 .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
> 309 .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
> 310 .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
> 311 POWER6_MMCRA_OTHER,
> 312 .platform = "power6x",
> 313 },
> 314 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
> 315 .pvr_mask = 0xffffffff,
> 316 .pvr_value = 0x0f000002,
> 317 .cpu_name = "POWER6 (architected)",
> 318 .cpu_features = CPU_FTRS_POWER6,
> 319 .cpu_user_features = COMMON_USER_POWER6,
> 320 .mmu_features = MMU_FTRS_POWER6,
> 321 .icache_bsize = 128,
> 322 .dcache_bsize = 128,
> 323 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 324 .oprofile_type = PPC_OPROFILE_POWER4,
> 325 .platform = "power6",
> 326 },
> 327 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
> 328 .pvr_mask = 0xffffffff,
> 329 .pvr_value = 0x0f000003,
> 330 .cpu_name = "POWER7 (architected)",
> 331 .cpu_features = CPU_FTRS_POWER7,
> 332 .cpu_user_features = COMMON_USER_POWER7,
> 333 .cpu_user_features2 = COMMON_USER2_POWER7,
> 334 .mmu_features = MMU_FTRS_POWER7,
> 335 .icache_bsize = 128,
> 336 .dcache_bsize = 128,
> 337 .oprofile_type = PPC_OPROFILE_POWER4,
> 338 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 339 .cpu_setup = __setup_cpu_power7,
> 340 .cpu_restore = __restore_cpu_power7,
> 341 .machine_check_early = __machine_check_early_realmode_p7,
> 342 .platform = "power7",
> 343 },
> 344 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
> 345 .pvr_mask = 0xffffffff,
> 346 .pvr_value = 0x0f000004,
> 347 .cpu_name = "POWER8 (architected)",
> 348 .cpu_features = CPU_FTRS_POWER8,
> 349 .cpu_user_features = COMMON_USER_POWER8,
> 350 .cpu_user_features2 = COMMON_USER2_POWER8,
> 351 .mmu_features = MMU_FTRS_POWER8,
> 352 .icache_bsize = 128,
> 353 .dcache_bsize = 128,
> 354 .oprofile_type = PPC_OPROFILE_INVALID,
> 355 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 356 .cpu_setup = __setup_cpu_power8,
> 357 .cpu_restore = __restore_cpu_power8,
> 358 .machine_check_early = __machine_check_early_realmode_p8,
> 359 .platform = "power8",
> 360 },
> 361 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
> 362 .pvr_mask = 0xffffffff,
> 363 .pvr_value = 0x0f000005,
> 364 .cpu_name = "POWER9 (architected)",
> 365 .cpu_features = CPU_FTRS_POWER9,
> 366 .cpu_user_features = COMMON_USER_POWER9,
> 367 .cpu_user_features2 = COMMON_USER2_POWER9,
> 368 .mmu_features = MMU_FTRS_POWER9,
> 369 .icache_bsize = 128,
> 370 .dcache_bsize = 128,
> 371 .oprofile_type = PPC_OPROFILE_INVALID,
> 372 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 373 .cpu_setup = __setup_cpu_power9,
> 374 .cpu_restore = __restore_cpu_power9,
> 375 .platform = "power9",
> 376 },
> 377 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
> 378 .pvr_mask = 0xffffffff,
> 379 .pvr_value = 0x0f000006,
> 380 .cpu_name = "POWER10 (architected)",
> 381 .cpu_features = CPU_FTRS_POWER10,
> 382 .cpu_user_features = COMMON_USER_POWER10,
> 383 .cpu_user_features2 = COMMON_USER2_POWER10,
> 384 .mmu_features = MMU_FTRS_POWER10,
> 385 .icache_bsize = 128,
> 386 .dcache_bsize = 128,
> 387 .oprofile_type = PPC_OPROFILE_INVALID,
> 388 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
> 389 .cpu_setup = __setup_cpu_power10,
> 390 .cpu_restore = __restore_cpu_power10,
> 391 .platform = "power10",
> 392 },
> 393 { /* Power7 */
> 394 .pvr_mask = 0xffff0000,
> 395 .pvr_value = 0x003f0000,
> 396 .cpu_name = "POWER7 (raw)",
> 397 .cpu_features = CPU_FTRS_POWER7,
> 398 .cpu_user_features = COMMON_USER_POWER7,
> 399 .cpu_user_features2 = COMMON_USER2_POWER7,
> 400 .mmu_features = MMU_FTRS_POWER7,
> 401 .icache_bsize = 128,
> 402 .dcache_bsize = 128,
> 403 .num_pmcs = 6,
> 404 .pmc_type = PPC_PMC_IBM,
> 405 .oprofile_cpu_type = "ppc64/power7",
> 406 .oprofile_type = PPC_OPROFILE_POWER4,
> 407 .cpu_setup = __setup_cpu_power7,
> 408 .cpu_restore = __restore_cpu_power7,
> 409 .machine_check_early = __machine_check_early_realmode_p7,
> 410 .platform = "power7",
> 411 },
> 412 { /* Power7+ */
> 413 .pvr_mask = 0xffff0000,
> 414 .pvr_value = 0x004A0000,
> 415 .cpu_name = "POWER7+ (raw)",
> 416 .cpu_features = CPU_FTRS_POWER7,
> 417 .cpu_user_features = COMMON_USER_POWER7,
> 418 .cpu_user_features2 = COMMON_USER2_POWER7,
> 419 .mmu_features = MMU_FTRS_POWER7,
> 420 .icache_bsize = 128,
> 421 .dcache_bsize = 128,
> 422 .num_pmcs = 6,
> 423 .pmc_type = PPC_PMC_IBM,
> 424 .oprofile_cpu_type = "ppc64/power7",
> 425 .oprofile_type = PPC_OPROFILE_POWER4,
> 426 .cpu_setup = __setup_cpu_power7,
> 427 .cpu_restore = __restore_cpu_power7,
> 428 .machine_check_early = __machine_check_early_realmode_p7,
> 429 .platform = "power7+",
> 430 },
> 431 { /* Power8E */
> 432 .pvr_mask = 0xffff0000,
> 433 .pvr_value = 0x004b0000,
> 434 .cpu_name = "POWER8E (raw)",
> 435 .cpu_features = CPU_FTRS_POWER8E,
> 436 .cpu_user_features = COMMON_USER_POWER8,
> 437 .cpu_user_features2 = COMMON_USER2_POWER8,
> 438 .mmu_features = MMU_FTRS_POWER8,
> 439 .icache_bsize = 128,
> 440 .dcache_bsize = 128,
> 441 .num_pmcs = 6,
> 442 .pmc_type = PPC_PMC_IBM,
> 443 .oprofile_cpu_type = "ppc64/power8",
> 444 .oprofile_type = PPC_OPROFILE_INVALID,
> 445 .cpu_setup = __setup_cpu_power8,
> 446 .cpu_restore = __restore_cpu_power8,
> 447 .machine_check_early = __machine_check_early_realmode_p8,
> 448 .platform = "power8",
> 449 },
> 450 { /* Power8NVL */
> 451 .pvr_mask = 0xffff0000,
> 452 .pvr_value = 0x004c0000,
> 453 .cpu_name = "POWER8NVL (raw)",
> 454 .cpu_features = CPU_FTRS_POWER8,
> 455 .cpu_user_features = COMMON_USER_POWER8,
> 456 .cpu_user_features2 = COMMON_USER2_POWER8,
> 457 .mmu_features = MMU_FTRS_POWER8,
> 458 .icache_bsize = 128,
> 459 .dcache_bsize = 128,
> 460 .num_pmcs = 6,
> 461 .pmc_type = PPC_PMC_IBM,
> 462 .oprofile_cpu_type = "ppc64/power8",
> 463 .oprofile_type = PPC_OPROFILE_INVALID,
> 464 .cpu_setup = __setup_cpu_power8,
> 465 .cpu_restore = __restore_cpu_power8,
> 466 .machine_check_early = __machine_check_early_realmode_p8,
> 467 .platform = "power8",
> 468 },
> 469 { /* Power8 */
> 470 .pvr_mask = 0xffff0000,
> 471 .pvr_value = 0x004d0000,
> 472 .cpu_name = "POWER8 (raw)",
> 473 .cpu_features = CPU_FTRS_POWER8,
> 474 .cpu_user_features = COMMON_USER_POWER8,
> 475 .cpu_user_features2 = COMMON_USER2_POWER8,
> 476 .mmu_features = MMU_FTRS_POWER8,
> 477 .icache_bsize = 128,
> 478 .dcache_bsize = 128,
> 479 .num_pmcs = 6,
> 480 .pmc_type = PPC_PMC_IBM,
> 481 .oprofile_cpu_type = "ppc64/power8",
> 482 .oprofile_type = PPC_OPROFILE_INVALID,
> 483 .cpu_setup = __setup_cpu_power8,
> 484 .cpu_restore = __restore_cpu_power8,
> 485 .machine_check_early = __machine_check_early_realmode_p8,
> 486 .platform = "power8",
> 487 },
> 488 { /* Power9 DD2.0 */
> 489 .pvr_mask = 0xffffefff,
> 490 .pvr_value = 0x004e0200,
> 491 .cpu_name = "POWER9 (raw)",
> 492 .cpu_features = CPU_FTRS_POWER9_DD2_0,
> 493 .cpu_user_features = COMMON_USER_POWER9,
> 494 .cpu_user_features2 = COMMON_USER2_POWER9,
> 495 .mmu_features = MMU_FTRS_POWER9,
> 496 .icache_bsize = 128,
> 497 .dcache_bsize = 128,
> 498 .num_pmcs = 6,
> 499 .pmc_type = PPC_PMC_IBM,
> 500 .oprofile_cpu_type = "ppc64/power9",
> 501 .oprofile_type = PPC_OPROFILE_INVALID,
> 502 .cpu_setup = __setup_cpu_power9,
> 503 .cpu_restore = __restore_cpu_power9,
> 504 .machine_check_early = __machine_check_early_realmode_p9,
> 505 .platform = "power9",
> 506 },
> 507 { /* Power9 DD 2.1 */
> 508 .pvr_mask = 0xffffefff,
> 509 .pvr_value = 0x004e0201,
> 510 .cpu_name = "POWER9 (raw)",
> 511 .cpu_features = CPU_FTRS_POWER9_DD2_1,
> 512 .cpu_user_features = COMMON_USER_POWER9,
> 513 .cpu_user_features2 = COMMON_USER2_POWER9,
> 514 .mmu_features = MMU_FTRS_POWER9,
> 515 .icache_bsize = 128,
> 516 .dcache_bsize = 128,
> 517 .num_pmcs = 6,
> 518 .pmc_type = PPC_PMC_IBM,
> 519 .oprofile_cpu_type = "ppc64/power9",
> 520 .oprofile_type = PPC_OPROFILE_INVALID,
> 521 .cpu_setup = __setup_cpu_power9,
> 522 .cpu_restore = __restore_cpu_power9,
> 523 .machine_check_early = __machine_check_early_realmode_p9,
> 524 .platform = "power9",
> 525 },
> 526 { /* Power9 DD2.2 or later */
> 527 .pvr_mask = 0xffff0000,
> 528 .pvr_value = 0x004e0000,
> 529 .cpu_name = "POWER9 (raw)",
> 530 .cpu_features = CPU_FTRS_POWER9_DD2_2,
> 531 .cpu_user_features = COMMON_USER_POWER9,
> 532 .cpu_user_features2 = COMMON_USER2_POWER9,
> 533 .mmu_features = MMU_FTRS_POWER9,
> 534 .icache_bsize = 128,
> 535 .dcache_bsize = 128,
> 536 .num_pmcs = 6,
> 537 .pmc_type = PPC_PMC_IBM,
> 538 .oprofile_cpu_type = "ppc64/power9",
> 539 .oprofile_type = PPC_OPROFILE_INVALID,
> 540 .cpu_setup = __setup_cpu_power9,
> 541 .cpu_restore = __restore_cpu_power9,
> 542 .machine_check_early = __machine_check_early_realmode_p9,
> 543 .platform = "power9",
> 544 },
> 545 { /* Power10 */
> 546 .pvr_mask = 0xffff0000,
> 547 .pvr_value = 0x00800000,
> 548 .cpu_name = "POWER10 (raw)",
> 549 .cpu_features = CPU_FTRS_POWER10,
> 550 .cpu_user_features = COMMON_USER_POWER10,
> 551 .cpu_user_features2 = COMMON_USER2_POWER10,
> 552 .mmu_features = MMU_FTRS_POWER10,
> 553 .icache_bsize = 128,
> 554 .dcache_bsize = 128,
> 555 .num_pmcs = 6,
> 556 .pmc_type = PPC_PMC_IBM,
> 557 .oprofile_cpu_type = "ppc64/power10",
> 558 .oprofile_type = PPC_OPROFILE_INVALID,
> 559 .cpu_setup = __setup_cpu_power10,
> 560 .cpu_restore = __restore_cpu_power10,
> > 561 .machine_check_early = __machine_check_early_realmode_p10,
> 562 .platform = "power10",
> 563 },
> 564 { /* Cell Broadband Engine */
> 565 .pvr_mask = 0xffff0000,
> 566 .pvr_value = 0x00700000,
> 567 .cpu_name = "Cell Broadband Engine",
> 568 .cpu_features = CPU_FTRS_CELL,
> 569 .cpu_user_features = COMMON_USER_PPC64 |
> 570 PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
> 571 PPC_FEATURE_SMT,
> 572 .mmu_features = MMU_FTRS_CELL,
> 573 .icache_bsize = 128,
> 574 .dcache_bsize = 128,
> 575 .num_pmcs = 4,
> 576 .pmc_type = PPC_PMC_IBM,
> 577 .oprofile_cpu_type = "ppc64/cell-be",
> 578 .oprofile_type = PPC_OPROFILE_CELL,
> 579 .platform = "ppc-cell-be",
> 580 },
> 581 { /* PA Semi PA6T */
> 582 .pvr_mask = 0x7fff0000,
> 583 .pvr_value = 0x00900000,
> 584 .cpu_name = "PA6T",
> 585 .cpu_features = CPU_FTRS_PA6T,
> 586 .cpu_user_features = COMMON_USER_PA6T,
> 587 .mmu_features = MMU_FTRS_PA6T,
> 588 .icache_bsize = 64,
> 589 .dcache_bsize = 64,
> 590 .num_pmcs = 6,
> 591 .pmc_type = PPC_PMC_PA6T,
> 592 .cpu_setup = __setup_cpu_pa6t,
> 593 .cpu_restore = __restore_cpu_pa6t,
> 594 .oprofile_cpu_type = "ppc64/pa6t",
> 595 .oprofile_type = PPC_OPROFILE_PA6T,
> 596 .platform = "pa6t",
> 597 },
> 598 { /* default match */
> 599 .pvr_mask = 0x00000000,
> 600 .pvr_value = 0x00000000,
> 601 .cpu_name = "POWER5 (compatible)",
> 602 .cpu_features = CPU_FTRS_COMPATIBLE,
> 603 .cpu_user_features = COMMON_USER_PPC64,
> 604 .mmu_features = MMU_FTRS_POWER,
> 605 .icache_bsize = 128,
> 606 .dcache_bsize = 128,
> 607 .num_pmcs = 6,
> 608 .pmc_type = PPC_PMC_IBM,
> 609 .platform = "power5",
> 610 }
> 611 #endif /* CONFIG_PPC_BOOK3S_64 */
> 612
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply related
* [PATCH v2] powerpc: Add POWER10 raw mode cputable entry
From: Madhavan Srinivasan @ 2020-08-14 7:45 UTC (permalink / raw)
To: mpe; +Cc: Madhavan Srinivasan, linuxppc-dev
Add a raw mode cputable entry for POWER10. Copies most of the fields
from commit a3ea40d5c736 ("powerpc: Add POWER10 architected mode")
except for oprofile_cpu_type, machine_check_early, pvr_mask and pvr_mask
fields. On bare metal systems we use DT CPU features, which doesn't need a
cputable entry. But in VMs we still rely on the raw cputable entry to
set the correct values for the PMU related fields.
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
---
Changelog v1:
- Fixed function undeclared compiler error.
arch/powerpc/kernel/cputable.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index b4066354f0730..bb0c7f43a8283 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -75,6 +75,7 @@ extern void __restore_cpu_power10(void);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
+extern long __machine_check_early_realmode_p10(struct pt_regs *regs);
#endif /* CONFIG_PPC64 */
#if defined(CONFIG_E500)
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
@@ -541,6 +542,25 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check_early = __machine_check_early_realmode_p9,
.platform = "power9",
},
+ { /* Power10 */
+ .pvr_mask = 0xffff0000,
+ .pvr_value = 0x00800000,
+ .cpu_name = "POWER10 (raw)",
+ .cpu_features = CPU_FTRS_POWER10,
+ .cpu_user_features = COMMON_USER_POWER10,
+ .cpu_user_features2 = COMMON_USER2_POWER10,
+ .mmu_features = MMU_FTRS_POWER10,
+ .icache_bsize = 128,
+ .dcache_bsize = 128,
+ .num_pmcs = 6,
+ .pmc_type = PPC_PMC_IBM,
+ .oprofile_cpu_type = "ppc64/power10",
+ .oprofile_type = PPC_OPROFILE_INVALID,
+ .cpu_setup = __setup_cpu_power10,
+ .cpu_restore = __restore_cpu_power10,
+ .machine_check_early = __machine_check_early_realmode_p10,
+ .platform = "power10",
+ },
{ /* Cell Broadband Engine */
.pvr_mask = 0xffff0000,
.pvr_value = 0x00700000,
--
2.26.2
^ permalink raw reply related
* [PATCH net 1/5] ibmvnic: print caller in several error messages
From: Lijun Pan @ 2020-08-14 7:59 UTC (permalink / raw)
To: netdev; +Cc: Lijun Pan, linuxppc-dev
In-Reply-To: <20200814075921.88745-1-ljp@linux.ibm.com>
The error messages in the changed functions are exactly the same.
In order to differentiate them and make debugging easier,
we print the function names in the error messages.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
drivers/net/ethernet/ibm/ibmvnic.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index 5afb3c9c52d2..aba1cd9862ac 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -1864,7 +1864,7 @@ static int do_change_param_reset(struct ibmvnic_adapter *adapter,
if (rc) {
netdev_err(adapter->netdev,
- "Couldn't initialize crq. rc=%d\n", rc);
+ "%s: Couldn't initialize crq. rc=%d\n", __func__, rc);
return rc;
}
@@ -2089,7 +2089,7 @@ static int do_hard_reset(struct ibmvnic_adapter *adapter,
rc = init_crq_queue(adapter);
if (rc) {
netdev_err(adapter->netdev,
- "Couldn't initialize crq. rc=%d\n", rc);
+ "%s: Couldn't initialize crq. rc=%d\n", __func__, rc);
return rc;
}
@@ -2912,7 +2912,7 @@ static struct ibmvnic_sub_crq_queue *init_sub_crq_queue(struct ibmvnic_adapter
rc = ibmvnic_reset_crq(adapter);
if (rc == H_CLOSED) {
- dev_warn(dev, "Partner adapter not ready, waiting.\n");
+ dev_warn(dev, "%s: Partner adapter not ready, waiting.\n", __func__);
} else if (rc) {
dev_warn(dev, "Error %d registering sub-crq\n", rc);
goto reg_failed;
@@ -4865,7 +4865,7 @@ static int ibmvnic_reset_crq(struct ibmvnic_adapter *adapter)
if (rc == H_CLOSED)
/* Adapter is good, but other end is not ready */
- dev_warn(dev, "Partner adapter not ready\n");
+ dev_warn(dev, "%s: Partner adapter not ready\n", __func__);
else if (rc != 0)
dev_warn(dev, "Couldn't register crq (rc=%d)\n", rc);
@@ -4926,7 +4926,7 @@ static int init_crq_queue(struct ibmvnic_adapter *adapter)
retrc = rc;
if (rc == H_CLOSED) {
- dev_warn(dev, "Partner adapter not ready\n");
+ dev_warn(dev, "%s: Partner adapter not ready\n", __func__);
} else if (rc) {
dev_warn(dev, "Error %d opening adapter\n", rc);
goto reg_crq_failed;
@@ -5129,8 +5129,8 @@ static int ibmvnic_probe(struct vio_dev *dev, const struct vio_device_id *id)
do {
rc = init_crq_queue(adapter);
if (rc) {
- dev_err(&dev->dev, "Couldn't initialize crq. rc=%d\n",
- rc);
+ dev_err(&dev->dev, "%s: Couldn't initialize crq. rc=%d\n",
+ __func__, rc);
goto ibmvnic_init_fail;
}
--
2.23.0
^ permalink raw reply related
* [PATCH net 3/5] ibmvnic: improve ibmvnic_init and ibmvnic_reset_init
From: Lijun Pan @ 2020-08-14 7:59 UTC (permalink / raw)
To: netdev; +Cc: Lijun Pan, linuxppc-dev
In-Reply-To: <20200814075921.88745-1-ljp@linux.ibm.com>
When H_SEND_CRQ command returns with H_CLOSED, it means the
server's CRQ is not ready yet. Instead of resetting immediately,
we wait for the server to launch passive init.
ibmvnic_init() and ibmvnic_reset_init() should also return the
error code from ibmvnic_send_crq_init() call.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
drivers/net/ethernet/ibm/ibmvnic.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index 50e86e65961e..e366fd42a8c4 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -3568,8 +3568,7 @@ static int ibmvnic_send_crq(struct ibmvnic_adapter *adapter,
if (rc) {
if (rc == H_CLOSED) {
dev_warn(dev, "CRQ Queue closed\n");
- if (test_bit(0, &adapter->resetting))
- ibmvnic_reset(adapter, VNIC_RESET_FATAL);
+ /* do not reset, report the fail, wait for passive init from server */
}
dev_warn(dev, "Send error (rc=%d)\n", rc);
@@ -4985,7 +4984,12 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter)
reinit_completion(&adapter->init_done);
adapter->init_done_rc = 0;
- ibmvnic_send_crq_init(adapter);
+ rc = ibmvnic_send_crq_init(adapter);
+ if (rc) {
+ dev_err(dev, "%s: Send crq init failed with error %d\n", __func__, rc);
+ return rc;
+ }
+
if (!wait_for_completion_timeout(&adapter->init_done, timeout)) {
dev_err(dev, "Initialization sequence timed out\n");
return -1;
@@ -5039,7 +5043,12 @@ static int ibmvnic_init(struct ibmvnic_adapter *adapter)
adapter->from_passive_init = false;
adapter->init_done_rc = 0;
- ibmvnic_send_crq_init(adapter);
+ rc = ibmvnic_send_crq_init(adapter);
+ if (rc) {
+ dev_err(dev, "%s: Send crq init failed with error %d\n", __func__, rc);
+ return rc;
+ }
+
if (!wait_for_completion_timeout(&adapter->init_done, timeout)) {
dev_err(dev, "Initialization sequence timed out\n");
return -1;
--
2.23.0
^ permalink raw reply related
* [PATCH net 2/5] ibmvnic: compare adapter->init_done_rc with more readable ibmvnic_rc_codes
From: Lijun Pan @ 2020-08-14 7:59 UTC (permalink / raw)
To: netdev; +Cc: Lijun Pan, linuxppc-dev
In-Reply-To: <20200814075921.88745-1-ljp@linux.ibm.com>
Instead of comparing (adapter->init_done_rc == 1), let it
be (adapter->init_done_rc == PARTIALSUCCESS).
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
drivers/net/ethernet/ibm/ibmvnic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index aba1cd9862ac..50e86e65961e 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -974,7 +974,7 @@ static int set_link_state(struct ibmvnic_adapter *adapter, u8 link_state)
return -1;
}
- if (adapter->init_done_rc == 1) {
+ if (adapter->init_done_rc == PARTIALSUCCESS) {
/* Partuial success, delay and re-send */
mdelay(1000);
resend = true;
--
2.23.0
^ permalink raw reply related
* [PATCH net 4/5] ibmvnic: remove never executed if statement
From: Lijun Pan @ 2020-08-14 7:59 UTC (permalink / raw)
To: netdev; +Cc: Lijun Pan, linuxppc-dev
In-Reply-To: <20200814075921.88745-1-ljp@linux.ibm.com>
At the beginning of the function, from_passive_init is set false by
"adapter->from_passive_init = false;",
hence the if statement will never run.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
drivers/net/ethernet/ibm/ibmvnic.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
index e366fd42a8c4..280358dce8ba 100644
--- a/drivers/net/ethernet/ibm/ibmvnic.c
+++ b/drivers/net/ethernet/ibm/ibmvnic.c
@@ -5000,12 +5000,6 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter)
return adapter->init_done_rc;
}
- if (adapter->from_passive_init) {
- adapter->state = VNIC_OPEN;
- adapter->from_passive_init = false;
- return -1;
- }
-
if (test_bit(0, &adapter->resetting) && !adapter->wait_for_reset &&
adapter->reset_reason != VNIC_RESET_MOBILITY) {
if (adapter->req_rx_queues != old_num_rx_queues ||
@@ -5059,12 +5053,6 @@ static int ibmvnic_init(struct ibmvnic_adapter *adapter)
return adapter->init_done_rc;
}
- if (adapter->from_passive_init) {
- adapter->state = VNIC_OPEN;
- adapter->from_passive_init = false;
- return -1;
- }
-
rc = init_sub_crqs(adapter);
if (rc) {
dev_err(dev, "Initialization of sub crqs failed\n");
--
2.23.0
^ permalink raw reply related
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