* Re: [PATCH v3] powerpc/numa: Restrict possible nodes based on platform
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Srikar Dronamraju
Cc: Nathan Lynch, Tyrel Datwyler, linuxppc-dev, Bharata B Rao
In-Reply-To: <20200817055257.110873-1-srikar@linux.vnet.ibm.com>
On Mon, 17 Aug 2020 11:22:57 +0530, Srikar Dronamraju wrote:
> As per draft LoPAPR (Revision 2.9_pre7), section B.5.3 "Run Time Abstaction
> Services (RTAS) Node at
> https://openpowerfoundation.org/wp-content/uploads/2020/07/LoPAR-20200611.pdf,
> there are 2 device tree property ibm,max-associativity-domains (which
> defines the maximum number of domains that the firmware i.e PowerVM can
> support) and ibm,current-associativity-domains (which defines the maximum
> number of domains that the platform can support). Value of
> ibm,max-associativity-domains property is always greater than or equal to
> ibm,current-associativity-domains property. If the said property is not
> available, use ibm,max-associativity-domain as fallback. In this yet to be
> released LoPAPR, ibm,current-associativity-domains is mentioned in page 833
> / B.5.3 which is covered under under "Appendix B. System Binding" section
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/numa: Restrict possible nodes based on platform
https://git.kernel.org/powerpc/c/67df77845c181166d4bc324cbb0382f7e81c7631
cheers
^ permalink raw reply
* Re: [PATCH v2 1/2] sched/topology: Allow archs to override cpu_smt_mask
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Srikar Dronamraju
Cc: Ingo Molnar, Gautham R Shenoy, Michael Neuling, Vincent Guittot,
Peter Zijlstra, linuxppc-dev, LKML, Valentin Schneider,
Mel Gorman, Dietmar Eggemann
In-Reply-To: <20200807074517.27957-1-srikar@linux.vnet.ibm.com>
On Fri, 7 Aug 2020 13:15:16 +0530, Srikar Dronamraju wrote:
> cpu_smt_mask tracks topology_sibling_cpumask. This would be good for
> most architectures. One of the users of cpu_smt_mask(), would be to
> identify idle-cores. On Power9, a pair of SMT4 cores can be presented by
> the firmware as a SMT8 core for backward compatibility reasons.
>
> Powerpc allows LPARs to be live migrated from Power8 to Power9. Do note
> Power8 had only SMT8 cores. Existing software which has been
> developed/configured for Power8 would expect to see SMT8 core.
> Maintaining the illusion of SMT8 core is a requirement to make that
> work.
>
> [...]
Applied to powerpc/next.
[1/2] sched/topology: Allow archs to override cpu_smt_mask
https://git.kernel.org/powerpc/c/3babbe447d76ac2919ec4d0eb3b0adfb22f5b03c
[2/2] powerpc/topology: Override cpu_smt_mask
https://git.kernel.org/powerpc/c/f3232321db58480804f80d59aeb651a5c859a200
cheers
^ permalink raw reply
* Re: [PATCH v6 0/8] powerpc/watchpoint: Bug fixes plus new feature flag
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Ravi Bangoria, christophe.leroy, mpe
Cc: mikey, jniethe5, pedromfc, linux-kernel, paulus, rogealve,
naveen.n.rao, linuxppc-dev
In-Reply-To: <20200902042945.129369-1-ravi.bangoria@linux.ibm.com>
On Wed, 2 Sep 2020 09:59:37 +0530, Ravi Bangoria wrote:
> Patch #1 fixes issue for quardword instruction on p10 predecessors.
> Patch #2 fixes issue for vector instructions.
> Patch #3 fixes a bug about watchpoint not firing when created with
> ptrace PPC_PTRACE_SETHWDEBUG and CONFIG_HAVE_HW_BREAKPOINT=N.
> The fix uses HW_BRK_TYPE_PRIV_ALL for ptrace user which, I
> guess, should be fine because we don't leak any kernel
> addresses and PRIV_ALL will also help to cover scenarios when
> kernel accesses user memory.
> Patch #4,#5 fixes infinite exception bug, again the bug happens only
> with CONFIG_HAVE_HW_BREAKPOINT=N.
> Patch #6 fixes two places where we are missing to set hw_len.
> Patch #7 introduce new feature bit PPC_DEBUG_FEATURE_DATA_BP_ARCH_31
> which will be set when running on ISA 3.1 compliant machine.
> Patch #8 finally adds selftest to test scenarios fixed by patch#2,#3
> and also moves MODE_EXACT tests outside of BP_RANGE condition.
>
> [...]
Applied to powerpc/next.
[1/8] powerpc/watchpoint: Fix quadword instruction handling on p10 predecessors
https://git.kernel.org/powerpc/c/4759c11ed20454b7b36db4ec15f7d5aa1519af4a
[2/8] powerpc/watchpoint: Fix handling of vector instructions
https://git.kernel.org/powerpc/c/4441eb02333a9b46a0d919aa7a6d3b137b5f2562
[3/8] powerpc/watchpoint/ptrace: Fix SETHWDEBUG when CONFIG_HAVE_HW_BREAKPOINT=N
https://git.kernel.org/powerpc/c/9b6b7c680cc20971444d9f836e49fc98848bcd0a
[4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c
https://git.kernel.org/powerpc/c/edc8dd99b29e4d705c45e2a3a6c01b096ee056db
[5/8] powerpc/watchpoint: Fix exception handling for CONFIG_HAVE_HW_BREAKPOINT=N
https://git.kernel.org/powerpc/c/5b905d77987de065bdd3a2906816b5f143df087b
[6/8] powerpc/watchpoint: Add hw_len wherever missing
https://git.kernel.org/powerpc/c/58da5984d2ea6d95f3f9d9e8dd9f7e1b0dddfb3c
[7/8] powerpc/watchpoint/ptrace: Introduce PPC_DEBUG_FEATURE_DATA_BP_ARCH_31
https://git.kernel.org/powerpc/c/fa725cc53d353110f39a9e5b9f60d6acb2c7ff49
[8/8] selftests/powerpc: Tests for kernel accessing user memory
https://git.kernel.org/powerpc/c/ac234524056da4e0c081f682da3ea25cdaab737a
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/powernv/idle: add a basic stop 0-3 driver for POWER10
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Nicholas Piggin, linuxppc-dev
Cc: Gautham R . Shenoy, Michael Neuling, Ryan P Grimm,
Pratik Rajesh Sampat
In-Reply-To: <20200819094700.493399-1-npiggin@gmail.com>
On Wed, 19 Aug 2020 19:47:00 +1000, Nicholas Piggin wrote:
> This driver does not restore stop > 3 state, so it limits itself
> to states which do not lose full state or TB.
>
> The POWER10 SPRs are sufficiently different from P9 that it seems
> easier to split out the P10 code. The POWER10 deep sleep code
> (e.g., the BHRB restore) has been taken out, but it can be re-added
> when stop > 3 support is added.
Applied to powerpc/next.
[1/1] powerpc/powernv/idle: add a basic stop 0-3 driver for POWER10
https://git.kernel.org/powerpc/c/ffd2961bb41f797eb00b58e019b707555197275e
cheers
^ permalink raw reply
* Re: [PATCH 0/5] powerpc/tau: TAU driver fixes
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Finn Thain
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <cover.1599260540.git.fthain@telegraphics.com.au>
On Sat, 05 Sep 2020 09:02:20 +1000, Finn Thain wrote:
> This patch series fixes various bugs in the Thermal Assist Unit driver.
> It was tested on 266 MHz and 292 MHz PowerBook G3 laptops.
>
>
> Finn Thain (5):
> powerpc/tau: Use appropriate temperature sample interval
> powerpc/tau: Convert from timer to workqueue
> powerpc/tau: Remove duplicated set_thresholds() call
> powerpc/tau: Check processor type before enabling TAU interrupt
> powerpc/tau: Disable TAU between measurements
>
> [...]
Applied to powerpc/next.
[1/5] powerpc/tau: Use appropriate temperature sample interval
https://git.kernel.org/powerpc/c/66943005cc41f48e4d05614e8f76c0ca1812f0fd
[2/5] powerpc/tau: Convert from timer to workqueue
https://git.kernel.org/powerpc/c/b1c6a0a10bfaf36ec82fde6f621da72407fa60a1
[3/5] powerpc/tau: Remove duplicated set_thresholds() call
https://git.kernel.org/powerpc/c/420ab2bc7544d978a5d0762ee736412fe9c796ab
[4/5] powerpc/tau: Check processor type before enabling TAU interrupt
https://git.kernel.org/powerpc/c/5e3119e15fed5b9a9a7e528665ff098a4a8dbdbc
[5/5] powerpc/tau: Disable TAU between measurements
https://git.kernel.org/powerpc/c/e63d6fb5637e92725cf143559672a34b706bca4f
cheers
^ permalink raw reply
* Re: [PATCH -next] macintosh: windfarm: use for_each_child_of_node() macro
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Qinglang Miao; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20200914061411.3356-1-miaoqinglang@huawei.com>
On Mon, 14 Sep 2020 14:14:11 +0800, Qinglang Miao wrote:
> Use for_each_child_of_node() macro instead of open coding it.
Applied to powerpc/next.
[1/1] macintosh: windfarm: use for_each_child_of_node() macro
https://git.kernel.org/powerpc/c/8f7e57e8e29c4fc788811dd4db96126272b8df91
cheers
^ permalink raw reply
* Re: [PATCH v2] powerpc/pci: unmap legacy INTx interrupts when a PHB is removed
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Cédric Le Goater
Cc: Alexey Kardashevskiy, Oliver O'Halloran, linuxppc-dev
In-Reply-To: <20200807101854.844619-1-clg@kaod.org>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 793 bytes --]
On Fri, 7 Aug 2020 12:18:54 +0200, Cédric Le Goater wrote:
> When a passthrough IO adapter is removed from a pseries machine using
> hash MMU and the XIVE interrupt mode, the POWER hypervisor expects the
> guest OS to clear all page table entries related to the adapter. If
> some are still present, the RTAS call which isolates the PCI slot
> returns error 9001 "valid outstanding translations" and the removal of
> the IO adapter fails. This is because when the PHBs are scanned, Linux
> maps automatically the INTx interrupts in the Linux interrupt number
> space but these are never removed.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/pci: unmap legacy INTx interrupts when a PHB is removed
https://git.kernel.org/powerpc/c/3a3181e16fbde752007759f8759d25e0ff1fc425
cheers
^ permalink raw reply
* Re: [PATCH v2] powerpc/powermac: Fix low_sleep_handler with KUAP and KUEP
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <21b05f7298c1b18f73e6e5b4cd5005aafa24b6da.1599820109.git.christophe.leroy@csgroup.eu>
On Fri, 11 Sep 2020 10:29:15 +0000 (UTC), Christophe Leroy wrote:
> low_sleep_handler() has an hardcoded restore of segment registers
> that doesn't take KUAP and KUEP into account.
>
> Use head_32's load_segment_registers() routine instead.
Applied to powerpc/next.
[1/1] powerpc/powermac: Fix low_sleep_handler with KUAP and KUEP
https://git.kernel.org/powerpc/c/2c637d2df4ee4830e9d3eb2bd5412250522ce96e
cheers
^ permalink raw reply
* Re: [PATCH v1] powerpc/process: Tag an #endif to help locate the matching #ifdef.
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <3612a8f8aaca16de3fc414a7e66293319d6e213c.1597643147.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:46:45 +0000 (UTC), Christophe Leroy wrote:
> That #endif is more than 100 lines after the matching #ifdef,
> and there are several #ifdef/#else/#endif inbetween.
>
> Tag it as /* CONFIG_PPC_BOOK3S_64 */ to help locate the
> matching #ifdef.
Applied to powerpc/next.
[1/1] powerpc/process: Tag an #endif to help locate the matching #ifdef.
https://git.kernel.org/powerpc/c/60d62bfd24efce1a595d259100b8a4e7a489e834
cheers
^ permalink raw reply
* Re: [PATCH v1] powerpc/process: Replace #ifdef CONFIG_KALLSYMS by IS_ENABLED()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <2d89732a9062b2cf2651728804e4b8f6c9b9358e.1597643164.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:46:44 +0000 (UTC), Christophe Leroy wrote:
> The #ifdef CONFIG_KALLSYMS encloses some printk which can
> compile in all cases.
>
> Replace by IS_ENABLED().
Applied to powerpc/next.
[1/1] powerpc/process: Replace #ifdef CONFIG_KALLSYMS by IS_ENABLED()
https://git.kernel.org/powerpc/c/8f020c7ca300fd60374f0347814c92ea513c24da
cheers
^ permalink raw reply
* Re: [PATCH v1] powerpc/process: Replace an #ifdef CONFIG_PPC_BOOK3S_64 by IS_ENABLED()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <d31506ca9bac9def68cf7424eded63fdc4fb6660.1597643167.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:46:42 +0000 (UTC), Christophe Leroy wrote:
> This #ifdef CONFIG_PPC_BOOK3S_64 calls preload_new_slb_context()
> when radix is not enabled.
>
> radix_enabled() is always defined, and the prototype for
> preload_new_slb_context() is always present, so the #ifdef
> is unneeded.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/process: Replace an #ifdef CONFIG_PPC_BOOK3S_64 by IS_ENABLED()
https://git.kernel.org/powerpc/c/bfac2799301c19d81122af04a8a3ad5ecae3737e
cheers
^ permalink raw reply
* Re: [PATCH v1] powerpc/process: Replace an #ifdef CONFIG_PPC_47x by IS_ENABLED()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <ac8da0e3baa91dda805e1e492fd65aecd90c1fb5.1597643156.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:46:41 +0000 (UTC), Christophe Leroy wrote:
> isync() is always defined, no need for an #ifdef.
>
> Replace it by IS_ENABLED(CONFIG_PPC_47x).
Applied to powerpc/next.
[1/1] powerpc/process: Replace an #ifdef CONFIG_PPC_47x by IS_ENABLED()
https://git.kernel.org/powerpc/c/04d476bfbb06426fef2985c8e53578bb04596a6f
cheers
^ permalink raw reply
* Re: [PATCH v1] powerpc/process: Replace an #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) by IS_ENABLED()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <a1b6ef3d657c8f249193442f56868fc358ea5b6c.1597643160.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:46:43 +0000 (UTC), Christophe Leroy wrote:
> The #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) encloses some
> printk which can be compiled in all cases.
>
> Replace by IS_ENABLED().
Applied to powerpc/next.
[1/1] powerpc/process: Replace an #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) by IS_ENABLED()
https://git.kernel.org/powerpc/c/2ec42996f5b12826466300a755413577b6913206
cheers
^ permalink raw reply
* Re: [PATCH v1 1/4] powerpc/process: Remove useless #ifdef CONFIG_VSX
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <0eb61cf0dc66d781d47deb2228498cd61d03a754.1597643221.git.christophe.leroy@csgroup.eu>
On Mon, 17 Aug 2020 05:47:55 +0000 (UTC), Christophe Leroy wrote:
> cpu_has_feature(CPU_FTR_VSX) returns false when CONFIG_VSX is
> not set.
>
> There is no need to enclose the test in an #ifdef CONFIG_VSX.
> Remove it.
Applied to powerpc/next.
[1/4] powerpc/process: Remove useless #ifdef CONFIG_VSX
https://git.kernel.org/powerpc/c/80739c2bd29133715d6828e333649a55095f4747
[2/4] powerpc/process: Remove useless #ifdef CONFIG_ALTIVEC
https://git.kernel.org/powerpc/c/e3667ee427e224f9951eb3940a97477285548134
[3/4] powerpc/process: Remove useless #ifdef CONFIG_SPE
https://git.kernel.org/powerpc/c/532ed1900d37a47c821718a0d8d28eb05b2c4d28
[4/4] powerpc/process: Remove useless #ifdef CONFIG_PPC_FPU
https://git.kernel.org/powerpc/c/c83c192a6fbb1d4db4144c40296ed059f5eca384
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/uaccess: Add pre-update addressing to __put_user_asm_goto()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <346f65d677adb11865f7762c25a1ca3c64404ba5.1599216023.git.christophe.leroy@csgroup.eu>
On Fri, 4 Sep 2020 10:46:47 +0000 (UTC), Christophe Leroy wrote:
> Enable pre-update addressing mode in __put_user_asm_goto()
Applied to powerpc/next.
[1/1] powerpc/uaccess: Add pre-update addressing to __put_user_asm_goto()
https://git.kernel.org/powerpc/c/fcf1f26895a4f14618b0dc04e0801b123c55e4a3
cheers
^ permalink raw reply
* Re: [PATCH] powerpc/kasan: Fix CONFIG_KASAN_VMALLOC for 8xx
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <8ae4554357da4882612644a74387ae05525b2aaa.1599800716.git.christophe.leroy@csgroup.eu>
On Fri, 11 Sep 2020 05:05:38 +0000 (UTC), Christophe Leroy wrote:
> Before the commit identified below, pages tables allocation was
> performed after the allocation of final shadow area for linear memory.
> But that commit switched the order, leading to page tables being
> already allocated at the time 8xx kasan_init_shadow_8M() is called.
> Due to this, kasan_init_shadow_8M() doesn't map the needed
> shadow entries because there are already page tables.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/kasan: Fix CONFIG_KASAN_VMALLOC for 8xx
https://git.kernel.org/powerpc/c/4c42dc5c69a8f24c467a6c997909d2f1d4efdc7f
cheers
^ permalink raw reply
* Re: [PATCH] powerpc: Fix random segfault when freeing hugetlb range
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <f0cb2a5477cd87d1eaadb128042e20aeb2bc2859.1598860677.git.christophe.leroy@csgroup.eu>
On Mon, 31 Aug 2020 07:58:19 +0000 (UTC), Christophe Leroy wrote:
> The following random segfault is observed from time to time with
> map_hugetlb selftest:
>
> root@localhost:~# ./map_hugetlb 1 19
> 524288 kB hugepages
> Mapping 1 Mbytes
> Segmentation fault
>
> [...]
Applied to powerpc/next.
[1/1] powerpc: Fix random segfault when freeing hugetlb range
https://git.kernel.org/powerpc/c/542db12a9c42d1ce70c45091765e02f74c129f43
cheers
^ permalink raw reply
* Re: [PATCH 1/3] powerpc/uaccess: Switch __put_user_size_allowed() to __put_user_asm_goto()
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <94ba5a5138f99522e1562dbcdb38d31aa790dc89.1599216721.git.christophe.leroy@csgroup.eu>
On Fri, 4 Sep 2020 11:01:30 +0000 (UTC), Christophe Leroy wrote:
> __put_user_asm_goto() provides more flexibility to GCC and avoids using
> a local variable to tell if the write succeeded or not.
> GCC can then avoid implementing a cmp in the fast path.
>
> See the difference for a small function like the PPC64 version of
> save_general_regs() in arch/powerpc/kernel/signal_32.c:
>
> [...]
Applied to powerpc/next.
[1/3] powerpc/uaccess: Switch __put_user_size_allowed() to __put_user_asm_goto()
https://git.kernel.org/powerpc/c/ee0a49a6870ea75e25b4d4984c1bb6b3b7c65f2b
[2/3] powerpc/uaccess: Switch __patch_instruction() to __put_user_asm_goto()
https://git.kernel.org/powerpc/c/e64ac41ab0c510b3f85199a585eb886cad92fb19
[3/3] powerpc/uaccess: Remove __put_user_asm() and __put_user_asm2()
https://git.kernel.org/powerpc/c/7fdf966bed155b214f4f1f9b67825a40b2e9b998
cheers
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/8xx: Refactor calculation of number of entries per PTE in page tables
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <f6ea2483c2c389567b007945948f704d18cfaeea.1598862623.git.christophe.leroy@csgroup.eu>
On Mon, 31 Aug 2020 08:30:43 +0000 (UTC), Christophe Leroy wrote:
> On 8xx, the number of entries occupied by a PTE in the page tables
> depends on the size of the page. At the time being, this calculation
> is done in two places: in pte_update() and in set_huge_pte_at()
>
> Refactor this calculation into a helper called
> number_of_cells_per_pte(). For the time being, the val param is
> unused. It will be used by following patch.
>
> [...]
Applied to powerpc/next.
[1/2] powerpc/8xx: Refactor calculation of number of entries per PTE in page tables
https://git.kernel.org/powerpc/c/175a99991511fed16108dcb823f0af8e72325a1f
[2/2] powerpc/8xx: Support 16k hugepages with 4k pages
https://git.kernel.org/powerpc/c/e47168f3d1b14af5281cf50c59561d59d28201f9
cheers
^ permalink raw reply
* Re: [PATCH 1/2] powerpc/32: Fix vmap stack - Do not activate MMU before reading task struct
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Christophe Leroy
Cc: linuxppc-dev, linux-kernel
In-Reply-To: <a027d447022a006c9c4958ac734128e577a3c5c1.1599486108.git.christophe.leroy@csgroup.eu>
On Mon, 7 Sep 2020 13:42:09 +0000 (UTC), Christophe Leroy wrote:
> We need r1 to be properly set before activating MMU, so
> reading task_struct->stack must be done with MMU off.
>
> This means we need an additional register to play with MSR
> bits while r11 now points to the stack. For that, move r10
> back to CR (As is already done for hash MMU) and use r10.
>
> [...]
Applied to powerpc/next.
[1/2] powerpc/32: Fix vmap stack - Do not activate MMU before reading task struct
https://git.kernel.org/powerpc/c/c118c7303ad528be8ff2aea8cd1ee15452c763f0
[2/2] powerpc/32: Fix vmap stack - Properly set r1 before activating MMU
https://git.kernel.org/powerpc/c/da7bb43ab9da39bcfed0d146ce94e1f0cbae4ca0
cheers
^ permalink raw reply
* Re: [PATCH v3] powerpc/pseries/svm: Allocate SWIOTLB buffer anywhere in memory
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Thiago Jung Bauermann, iommu
Cc: Konrad Rzeszutek Wilk, Ram Pai, Robin Murphy, linux-kernel,
Satheesh Rajendran, linuxppc-dev, Christoph Hellwig
In-Reply-To: <20200818221126.391073-1-bauerman@linux.ibm.com>
On Tue, 18 Aug 2020 19:11:26 -0300, Thiago Jung Bauermann wrote:
> POWER secure guests (i.e., guests which use the Protection Execution
> Facility) need to use SWIOTLB to be able to do I/O with the hypervisor, but
> they don't need the SWIOTLB memory to be in low addresses since the
> hypervisor doesn't have any addressing limitation.
>
> This solves a SWIOTLB initialization problem we are seeing in secure guests
> with 128 GB of RAM: they are configured with 4 GB of crashkernel reserved
> memory, which leaves no space for SWIOTLB in low addresses.
>
> [...]
Applied to powerpc/next.
[1/1] powerpc/pseries/svm: Allocate SWIOTLB buffer anywhere in memory
https://git.kernel.org/powerpc/c/eae9eec476d13fad9af6da1f44a054ee02b7b161
cheers
^ permalink raw reply
* Re: [PATCH v2 1/4] powerpc/percpu: Update percpu bootmem allocator
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Aneesh Kumar K.V, linuxppc-dev, mpe; +Cc: cam
In-Reply-To: <20200608070904.387440-1-aneesh.kumar@linux.ibm.com>
On Mon, 8 Jun 2020 12:39:01 +0530, Aneesh Kumar K.V wrote:
> This update the ppc64 version to be closer to x86/sparc.
Applied to powerpc/next.
[1/4] powerpc/percpu: Update percpu bootmem allocator
https://git.kernel.org/powerpc/c/2a32abac8860aa1c3a1fc99973ce67179575b36c
[2/4] powerpc/64/mm: implement page mapping percpu first chunk allocator
https://git.kernel.org/powerpc/c/eb553f16973ade990d05946af9ae191394712c8a
[3/4] powerpc/book3s64/hash/4k: Support large linear mapping range with 4K
https://git.kernel.org/powerpc/c/7746406baa3bc9e23fdd7b7da2f04d86e25ab837
[4/4] powerpc/mm/book3s: Split radix and hash MAX_PHYSMEM limit
https://git.kernel.org/powerpc/c/b32d5d7e920a364287f6206af2d20179978a617d
cheers
^ permalink raw reply
* Re: [PATCH] powerepc/book3s64/hash: Align start/end address correctly with bolt mapping
From: Michael Ellerman @ 2020-09-17 11:27 UTC (permalink / raw)
To: Aneesh Kumar K.V, linuxppc-dev, mpe
In-Reply-To: <20200907072539.67310-1-aneesh.kumar@linux.ibm.com>
On Mon, 7 Sep 2020 12:55:39 +0530, Aneesh Kumar K.V wrote:
> This ensures we don't do a partial mapping of memory. With nvdimm, when
> creating namespaces with size not aligned to 16MB, the kernel ends up partially
> mapping the pages. This can result in kernel adding multiple hash page table
> entries for the same range. A new namespace will result in
> create_section_mapping() with start and end overlapping an already existing
> bolted hash page table entry.
>
> [...]
Applied to powerpc/next.
[1/1] powerepc/book3s64/hash: Align start/end address correctly with bolt mapping
https://git.kernel.org/powerpc/c/79b123cdf9cf0d4a1620baa8c611962626323a08
cheers
^ permalink raw reply
* Re: [PATCH v2 0/3] ASoC: fsl_sai: update the register list
From: Fabio Estevam @ 2020-09-17 9:40 UTC (permalink / raw)
To: Shengjiu Wang
Cc: Linux-ALSA, Timur Tabi, Xiubo Li, Liam Girdwood, Takashi Iwai,
Jaroslav Kysela, Nicolin Chen, Mark Brown, linuxppc-dev,
linux-kernel
In-Reply-To: <1600323079-5317-1-git-send-email-shengjiu.wang@nxp.com>
Hi Shengjiu,
On Thu, Sep 17, 2020 at 3:18 AM Shengjiu Wang <shengjiu.wang@nxp.com> wrote:
>
> As sai ip is upgraded, so update sai register list.
>
> Shengjiu Wang (3):
> ASoC: fsl_sai: Add new added registers and new bit definition
> ASoC: fsl_sai: Add fsl_sai_check_version function
> ASoC: fsl_sai: Set MCLK input or output direction
>
> changes in v2:
> - update commit message for first commit
> - Add acked-by Nicolin
For the whole series:
Reviewed-by: Fabio Estevam <festevam@gmail.com>
^ permalink raw reply
* [PATCH v2 2/2] powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C
From: Jordan Niethe @ 2020-09-17 9:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: oohall, npiggin, Jordan Niethe
In-Reply-To: <20200917091716.4631-1-jniethe5@gmail.com>
The only thing keeping the cpu_setup() and cpu_restore() functions used
in the cputable entries for Power7, Power8, Power9 and Power10 in
assembly was cpu_restore() being called before there was a stack in
generic_secondary_smp_init(). Commit ("powerpc/64: Set up a kernel stack
for secondaries before cpu_restore()") means that it is now possible to
use C.
Rewrite the functions in C so they are a little bit easier to read. This
is not changing their functionality.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
---
arch/powerpc/include/asm/cpu_setup_power.h | 12 +
arch/powerpc/kernel/cpu_setup_power.S | 252 -------------------
arch/powerpc/kernel/cpu_setup_power.c | 269 +++++++++++++++++++++
arch/powerpc/kernel/cputable.c | 9 +-
4 files changed, 282 insertions(+), 260 deletions(-)
create mode 100644 arch/powerpc/include/asm/cpu_setup_power.h
delete mode 100644 arch/powerpc/kernel/cpu_setup_power.S
create mode 100644 arch/powerpc/kernel/cpu_setup_power.c
diff --git a/arch/powerpc/include/asm/cpu_setup_power.h b/arch/powerpc/include/asm/cpu_setup_power.h
new file mode 100644
index 000000000000..24be9131f803
--- /dev/null
+++ b/arch/powerpc/include/asm/cpu_setup_power.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2020 IBM Corporation
+ */
+void __setup_cpu_power7(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power7(void);
+void __setup_cpu_power8(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power8(void);
+void __setup_cpu_power9(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power9(void);
+void __setup_cpu_power10(unsigned long offset, struct cpu_spec *spec);
+void __restore_cpu_power10(void);
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
deleted file mode 100644
index 704e8b9501ee..000000000000
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ /dev/null
@@ -1,252 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * This file contains low level CPU setup functions.
- * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
- */
-
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/cache.h>
-#include <asm/book3s/64/mmu-hash.h>
-
-/* Entry: r3 = crap, r4 = ptr to cputable entry
- *
- * Note that we can be called twice for pseudo-PVRs
- */
-_GLOBAL(__setup_cpu_power7)
- mflr r11
- bl __init_hvmode_206
- mtlr r11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
- bl __init_LPCR_ISA206
- mtlr r11
- blr
-
-_GLOBAL(__restore_cpu_power7)
- mflr r11
- mfmsr r3
- rldicl. r0,r3,4,63
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
- bl __init_LPCR_ISA206
- mtlr r11
- blr
-
-_GLOBAL(__setup_cpu_power8)
- mflr r11
- bl __init_FSCR
- bl __init_PMU
- bl __init_PMU_ISA207
- bl __init_hvmode_206
- mtlr r11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- ori r3, r3, LPCR_PECEDH
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA206
- bl __init_HFSCR
- bl __init_PMU_HV
- bl __init_PMU_HV_ISA207
- mtlr r11
- blr
-
-_GLOBAL(__restore_cpu_power8)
- mflr r11
- bl __init_FSCR
- bl __init_PMU
- bl __init_PMU_ISA207
- mfmsr r3
- rldicl. r0,r3,4,63
- mtlr r11
- beqlr
- li r0,0
- mtspr SPRN_LPID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- ori r3, r3, LPCR_PECEDH
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA206
- bl __init_HFSCR
- bl __init_PMU_HV
- bl __init_PMU_HV_ISA207
- mtlr r11
- blr
-
-_GLOBAL(__setup_cpu_power10)
- mflr r11
- bl __init_FSCR_power10
- bl __init_PMU
- bl __init_PMU_ISA31
- b 1f
-
-_GLOBAL(__setup_cpu_power9)
- mflr r11
- bl __init_FSCR_power9
- bl __init_PMU
-1: bl __init_hvmode_206
- mtlr r11
- beqlr
- li r0,0
- mtspr SPRN_PSSCR,r0
- mtspr SPRN_LPID,r0
- mtspr SPRN_PID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
- or r3, r3, r4
- LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
- andc r3, r3, r4
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA300
- bl __init_HFSCR
- bl __init_PMU_HV
- mtlr r11
- blr
-
-_GLOBAL(__restore_cpu_power10)
- mflr r11
- bl __init_FSCR_power10
- bl __init_PMU
- bl __init_PMU_ISA31
- b 1f
-
-_GLOBAL(__restore_cpu_power9)
- mflr r11
- bl __init_FSCR_power9
- bl __init_PMU
-1: mfmsr r3
- rldicl. r0,r3,4,63
- mtlr r11
- beqlr
- li r0,0
- mtspr SPRN_PSSCR,r0
- mtspr SPRN_LPID,r0
- mtspr SPRN_PID,r0
- LOAD_REG_IMMEDIATE(r0, PCR_MASK)
- mtspr SPRN_PCR,r0
- mfspr r3,SPRN_LPCR
- LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
- or r3, r3, r4
- LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
- andc r3, r3, r4
- li r4,0 /* LPES = 0 */
- bl __init_LPCR_ISA300
- bl __init_HFSCR
- bl __init_PMU_HV
- mtlr r11
- blr
-
-__init_hvmode_206:
- /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
- mfmsr r3
- rldicl. r0,r3,4,63
- bnelr
- ld r5,CPU_SPEC_FEATURES(r4)
- LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
- andc r5,r5,r6
- std r5,CPU_SPEC_FEATURES(r4)
- blr
-
-__init_LPCR_ISA206:
- /* Setup a sane LPCR:
- * Called with initial LPCR in R3 and desired LPES 2-bit value in R4
- *
- * LPES = 0b01 (HSRR0/1 used for 0x500)
- * PECE = 0b111
- * DPFD = 4
- * HDICE = 0
- * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
- * VRMASD = 0b10000 (L=1, LP=00)
- *
- * Other bits untouched for now
- */
- li r5,0x10
- rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
-
- /* POWER9 has no VRMASD */
-__init_LPCR_ISA300:
- rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
- ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
- li r5,4
- rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
- clrrdi r3,r3,1 /* clear HDICE */
- li r5,4
- rldimi r3,r5, LPCR_VC_SH, 0
- mtspr SPRN_LPCR,r3
- isync
- blr
-
-__init_FSCR_power10:
- mfspr r3, SPRN_FSCR
- ori r3, r3, FSCR_PREFIX
- mtspr SPRN_FSCR, r3
- // fall through
-
-__init_FSCR_power9:
- mfspr r3, SPRN_FSCR
- ori r3, r3, FSCR_SCV
- mtspr SPRN_FSCR, r3
- // fall through
-
-__init_FSCR:
- mfspr r3,SPRN_FSCR
- ori r3,r3,FSCR_TAR|FSCR_EBB
- mtspr SPRN_FSCR,r3
- blr
-
-__init_HFSCR:
- mfspr r3,SPRN_HFSCR
- ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
- HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
- mtspr SPRN_HFSCR,r3
- blr
-
-__init_PMU_HV:
- li r5,0
- mtspr SPRN_MMCRC,r5
- blr
-
-__init_PMU_HV_ISA207:
- li r5,0
- mtspr SPRN_MMCRH,r5
- blr
-
-__init_PMU:
- li r5,0
- mtspr SPRN_MMCRA,r5
- mtspr SPRN_MMCR0,r5
- mtspr SPRN_MMCR1,r5
- mtspr SPRN_MMCR2,r5
- blr
-
-__init_PMU_ISA207:
- li r5,0
- mtspr SPRN_MMCRS,r5
- blr
-
-__init_PMU_ISA31:
- li r5,0
- mtspr SPRN_MMCR3,r5
- LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
- mtspr SPRN_MMCRA,r5
- blr
diff --git a/arch/powerpc/kernel/cpu_setup_power.c b/arch/powerpc/kernel/cpu_setup_power.c
new file mode 100644
index 000000000000..cf5201b0579d
--- /dev/null
+++ b/arch/powerpc/kernel/cpu_setup_power.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 IBM Corporation
+ * This file contains low level CPU setup functions.
+ * Originally written in assembly by
+ * Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ */
+#include <asm/reg.h>
+#include <asm/synch.h>
+#include <linux/bitops.h>
+#include <asm/cputable.h>
+#include <asm/cpu_setup_power.h>
+
+/* Disable CPU_FTR_HVMODE and return false if MSR:HV is not set */
+static bool init_hvmode_206(struct cpu_spec *t)
+{
+ u64 msr;
+
+ msr = mfmsr();
+ if (msr & MSR_HV)
+ return true;
+
+ t->cpu_features &= ~(CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST);
+ return false;
+}
+
+static void init_LPCR_ISA300(u64 lpcr, u64 lpes)
+{
+ /* POWER9 has no VRMASD */
+ lpcr |= (lpes << LPCR_LPES_SH) & LPCR_LPES;
+ lpcr |= LPCR_PECE0|LPCR_PECE1|LPCR_PECE2;
+ lpcr |= (4ull << LPCR_DPFD_SH) & LPCR_DPFD;
+ lpcr &= ~LPCR_HDICE; /* clear HDICE */
+ lpcr |= (4ull << LPCR_VC_SH);
+ mtspr(SPRN_LPCR, lpcr);
+ isync();
+}
+
+/*
+ * Setup a sane LPCR:
+ * Called with initial LPCR and desired LPES 2-bit value
+ *
+ * LPES = 0b01 (HSRR0/1 used for 0x500)
+ * PECE = 0b111
+ * DPFD = 4
+ * HDICE = 0
+ * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
+ * VRMASD = 0b10000 (L=1, LP=00)
+ *
+ * Other bits untouched for now
+ */
+static void init_LPCR_ISA206(u64 lpcr, u64 lpes)
+{
+ lpcr |= (0x10ull << LPCR_VRMASD_SH) & LPCR_VRMASD;
+ init_LPCR_ISA300(lpcr, lpes);
+}
+
+static void init_FSCR(void)
+{
+ u64 fscr;
+
+ fscr = mfspr(SPRN_FSCR);
+ fscr |= FSCR_TAR|FSCR_EBB;
+ mtspr(SPRN_FSCR, fscr);
+}
+
+static void init_FSCR_power9(void)
+{
+ u64 fscr;
+
+ fscr = mfspr(SPRN_FSCR);
+ fscr |= FSCR_SCV;
+ mtspr(SPRN_FSCR, fscr);
+ init_FSCR();
+}
+
+static void init_FSCR_power10(void)
+{
+ u64 fscr;
+
+ fscr = mfspr(SPRN_FSCR);
+ fscr |= FSCR_PREFIX;
+ mtspr(SPRN_FSCR, fscr);
+ init_FSCR_power9();
+}
+
+static void init_HFSCR(void)
+{
+ u64 hfscr;
+
+ hfscr = mfspr(SPRN_HFSCR);
+ hfscr |= HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|HFSCR_DSCR|\
+ HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP;
+ mtspr(SPRN_HFSCR, hfscr);
+}
+
+static void init_PMU_HV(void)
+{
+ mtspr(SPRN_MMCRC, 0);
+}
+
+static void init_PMU_HV_ISA207(void)
+{
+ mtspr(SPRN_MMCRH, 0);
+}
+
+static void init_PMU(void)
+{
+ mtspr(SPRN_MMCRA, 0);
+ mtspr(SPRN_MMCR0, 0);
+ mtspr(SPRN_MMCR1, 0);
+ mtspr(SPRN_MMCR2, 0);
+}
+
+static void init_PMU_ISA207(void)
+{
+ mtspr(SPRN_MMCRS, 0);
+}
+
+static void init_PMU_ISA31(void)
+{
+ mtspr(SPRN_MMCR3, 0);
+ mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
+}
+
+/*
+ * Note that we can be called twice of pseudo-PVRs.
+ * The parameter offset is not used.
+ */
+
+void __setup_cpu_power7(unsigned long offset, struct cpu_spec *t)
+{
+ if (!init_hvmode_206(t))
+ return;
+
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
+}
+
+void __restore_cpu_power7(void)
+{
+ u64 msr;
+
+ msr = mfmsr();
+ if (!(msr & MSR_HV))
+ return;
+
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH);
+}
+
+void __setup_cpu_power8(unsigned long offset, struct cpu_spec *t)
+{
+ init_FSCR();
+ init_PMU();
+ init_PMU_ISA207();
+
+ if (!init_hvmode_206(t))
+ return;
+
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
+ init_HFSCR();
+ init_PMU_HV();
+ init_PMU_HV_ISA207();
+}
+
+void __restore_cpu_power8(void)
+{
+ u64 msr;
+
+ init_FSCR();
+ init_PMU();
+ init_PMU_ISA207();
+
+ msr = mfmsr();
+ if (!(msr & MSR_HV))
+ return;
+
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */
+ init_HFSCR();
+ init_PMU_HV();
+ init_PMU_HV_ISA207();
+}
+
+void __setup_cpu_power9(unsigned long offset, struct cpu_spec *t)
+{
+ init_FSCR_power9();
+ init_PMU();
+
+ if (!init_hvmode_206(t))
+ return;
+
+ mtspr(SPRN_PSSCR, 0);
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
+ LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
+ init_HFSCR();
+ init_PMU_HV();
+}
+
+void __restore_cpu_power9(void)
+{
+ u64 msr;
+
+ init_FSCR_power9();
+ init_PMU();
+
+ msr = mfmsr();
+ if (!(msr & MSR_HV))
+ return;
+
+ mtspr(SPRN_PSSCR, 0);
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
+ LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
+ init_HFSCR();
+ init_PMU_HV();
+}
+
+void __setup_cpu_power10(unsigned long offset, struct cpu_spec *t)
+{
+ init_FSCR_power10();
+ init_PMU();
+ init_PMU_ISA31();
+
+ if (!init_hvmode_206(t))
+ return;
+
+ mtspr(SPRN_PSSCR, 0);
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
+ LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
+ init_HFSCR();
+ init_PMU_HV();
+}
+
+void __restore_cpu_power10(void)
+{
+ u64 msr;
+
+ init_FSCR_power10();
+ init_PMU();
+ init_PMU_ISA31();
+
+ msr = mfmsr();
+ if (!(msr & MSR_HV))
+ return;
+
+ mtspr(SPRN_PSSCR, 0);
+ mtspr(SPRN_LPID, 0);
+ mtspr(SPRN_PID, 0);
+ mtspr(SPRN_PCR, PCR_MASK);
+ init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\
+ LPCR_HVICE | LPCR_HEIC) & ~(LPCR_UPRT | LPCR_HR), 0);
+ init_HFSCR();
+ init_PMU_HV();
+}
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 3d406a9626e8..bce545280056 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -59,19 +59,12 @@ extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
#endif /* CONFIG_PPC32 */
#ifdef CONFIG_PPC64
+#include <asm/cpu_setup_power.h>
extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
extern void __setup_cpu_pa6t(unsigned long offset, struct cpu_spec* spec);
extern void __restore_cpu_pa6t(void);
extern void __restore_cpu_ppc970(void);
-extern void __setup_cpu_power7(unsigned long offset, struct cpu_spec* spec);
-extern void __restore_cpu_power7(void);
-extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
-extern void __restore_cpu_power8(void);
-extern void __setup_cpu_power9(unsigned long offset, struct cpu_spec* spec);
-extern void __restore_cpu_power9(void);
-extern void __setup_cpu_power10(unsigned long offset, struct cpu_spec* spec);
-extern void __restore_cpu_power10(void);
extern long __machine_check_early_realmode_p7(struct pt_regs *regs);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
--
2.17.1
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