* Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
From: Matthew Wilcox @ 2020-11-16 16:32 UTC (permalink / raw)
To: Dave Hansen
Cc: mark.rutland, Peter Zijlstra, catalin.marinas, eranian,
sparclinux, will, mingo, kan.liang, linux-arch, ak, aneesh.kumar,
alexander.shishkin, jolsa, npiggin, acme, Kirill A. Shutemov,
linux-kernel, linuxppc-dev, davem, kirill.shutemov
In-Reply-To: <eeec67f6-ea05-1115-f249-b6cdcf2c5e2c@intel.com>
On Mon, Nov 16, 2020 at 08:28:23AM -0800, Dave Hansen wrote:
> On 11/16/20 7:54 AM, Matthew Wilcox wrote:
> > It gets even more complicated with CPUs with multiple levels of TLB
> > which support different TLB entry sizes. My CPU reports:
> >
> > TLB info
> > Instruction TLB: 2M/4M pages, fully associative, 8 entries
> > Instruction TLB: 4K pages, 8-way associative, 64 entries
> > Data TLB: 1GB pages, 4-way set associative, 4 entries
> > Data TLB: 4KB pages, 4-way associative, 64 entries
> > Shared L2 TLB: 4KB/2MB pages, 6-way associative, 1536 entries
>
> It's even "worse" on recent AMD systems. Those will coalesce multiple
> adjacent PTEs into a single TLB entry. I think Alphas did something
> like this back in the day with an opt-in.
I debated mentioning that ;-) We can detect in software whether that's
_possible_, but we can't detect whether it's *done* it. I heard it
sometimes takes several faults on the 4kB entries for the CPU to decide
that it's beneficial to use a 32kB TLB entry. But this is all rumour.
> Anyway, the changelog should probably replace:
>
> > This enables PERF_SAMPLE_{DATA,CODE}_PAGE_SIZE to report accurate TLB
> > page sizes.
>
> with something more like:
>
> This enables PERF_SAMPLE_{DATA,CODE}_PAGE_SIZE to report accurate page
> table mapping sizes.
>
> That's really the best we can do from software without digging into
> microarchitecture-specific events.
I mean this is perf. Digging into microarch specific events is what it
does ;-)
^ permalink raw reply
* Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
From: Dave Hansen @ 2020-11-16 16:36 UTC (permalink / raw)
To: Matthew Wilcox
Cc: mark.rutland, Peter Zijlstra, catalin.marinas, eranian,
sparclinux, will, mingo, kan.liang, linux-arch, ak, aneesh.kumar,
alexander.shishkin, jolsa, npiggin, acme, Kirill A. Shutemov,
linux-kernel, linuxppc-dev, davem, kirill.shutemov
In-Reply-To: <20201116163213.GG29991@casper.infradead.org>
On 11/16/20 8:32 AM, Matthew Wilcox wrote:
>>
>> That's really the best we can do from software without digging into
>> microarchitecture-specific events.
> I mean this is perf. Digging into microarch specific events is what it
> does ;-)
Yeah, totally.
But, if we see a bunch of 4k TLB hit events, it's still handy to know
that those 4k TLB hits originated from a 2M page table entry. This
series just makes sure that perf has the data about the page table
mapping sizes regardless of what the microarchitecture does with it.
I'm just saying we need to make the descriptions in this perf feature
specifically about the page tables, not the TLB.
^ permalink raw reply
* Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
From: Peter Zijlstra @ 2020-11-16 16:55 UTC (permalink / raw)
To: Dave Hansen
Cc: mark.rutland, alexander.shishkin, catalin.marinas, eranian,
sparclinux, will, mingo, kan.liang, linux-arch, ak, aneesh.kumar,
Matthew Wilcox, jolsa, npiggin, acme, Kirill A. Shutemov,
linux-kernel, linuxppc-dev, davem, kirill.shutemov
In-Reply-To: <eeec67f6-ea05-1115-f249-b6cdcf2c5e2c@intel.com>
On Mon, Nov 16, 2020 at 08:28:23AM -0800, Dave Hansen wrote:
> On 11/16/20 7:54 AM, Matthew Wilcox wrote:
> > It gets even more complicated with CPUs with multiple levels of TLB
> > which support different TLB entry sizes. My CPU reports:
> >
> > TLB info
> > Instruction TLB: 2M/4M pages, fully associative, 8 entries
> > Instruction TLB: 4K pages, 8-way associative, 64 entries
> > Data TLB: 1GB pages, 4-way set associative, 4 entries
> > Data TLB: 4KB pages, 4-way associative, 64 entries
> > Shared L2 TLB: 4KB/2MB pages, 6-way associative, 1536 entries
>
> It's even "worse" on recent AMD systems. Those will coalesce multiple
> adjacent PTEs into a single TLB entry. I think Alphas did something
> like this back in the day with an opt-in.
>
> Anyway, the changelog should probably replace:
ARM64 does too.
> > This enables PERF_SAMPLE_{DATA,CODE}_PAGE_SIZE to report accurate TLB
> > page sizes.
>
> with something more like:
>
> This enables PERF_SAMPLE_{DATA,CODE}_PAGE_SIZE to report accurate page
> table mapping sizes.
Sure.
^ permalink raw reply
* Re: [PATCH 0/5] perf/mm: Fix PERF_SAMPLE_*_PAGE_SIZE
From: Peter Zijlstra @ 2020-11-16 16:57 UTC (permalink / raw)
To: Dave Hansen
Cc: mark.rutland, alexander.shishkin, catalin.marinas, eranian,
sparclinux, will, mingo, kan.liang, linux-arch, ak, aneesh.kumar,
Matthew Wilcox, jolsa, npiggin, acme, Kirill A. Shutemov,
linux-kernel, linuxppc-dev, davem, kirill.shutemov
In-Reply-To: <3f2239fe-367a-16de-fcb5-543d39f34c22@intel.com>
On Mon, Nov 16, 2020 at 08:36:36AM -0800, Dave Hansen wrote:
> On 11/16/20 8:32 AM, Matthew Wilcox wrote:
> >>
> >> That's really the best we can do from software without digging into
> >> microarchitecture-specific events.
> > I mean this is perf. Digging into microarch specific events is what it
> > does ;-)
>
> Yeah, totally.
Sure, but the automatic promotion/demotion of TLB sizes is not visible
if you don't know what you startd out with.
> But, if we see a bunch of 4k TLB hit events, it's still handy to know
> that those 4k TLB hits originated from a 2M page table entry. This
> series just makes sure that perf has the data about the page table
> mapping sizes regardless of what the microarchitecture does with it.
This.
^ permalink raw reply
* Re: [PATCH] ocxl: Mmio invalidation support
From: Frederic Barrat @ 2020-11-16 17:51 UTC (permalink / raw)
To: Christophe Lombard, linuxppc-dev, fbarrat, Andrew Donnellan
In-Reply-To: <20201113153333.290505-1-clombard@linux.vnet.ibm.com>
On 13/11/2020 16:33, Christophe Lombard wrote:
> OpenCAPI 4.0/5.0 with TLBI/SLBI Snooping, is not used due to performance
> problems caused by the PAU having to process all incoming TLBI/SLBI
> commands which will cause them to back up on the PowerBus.
>
> When the Address Translation Mode requires TLB and SLB Invalidate
> operations to be initiated using MMIO registers, a set of registers like
> the following is used:
> • XTS MMIO ATSD0 LPARID register
> • XTS MMIO ATSD0 AVA register
> • XTS MMIO ATSD0 launch register, write access initiates a shoot down
> • XTS MMIO ATSD0 status register
>
> The MMIO based mechanism also blocks the NPU/PAU from snooping TLBIE
> commands from the PowerBus.
>
> The Shootdown commands (ATSD) will be generated using MMIO registers
> in the NPU/PAU and sent to the device.
>
> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
> ---
> arch/powerpc/include/asm/pnv-ocxl.h | 2 +
> arch/powerpc/platforms/powernv/ocxl.c | 19 +++
> drivers/misc/ocxl/link.c | 180 ++++++++++++++++++++++----
> drivers/misc/ocxl/ocxl_internal.h | 46 ++++++-
> drivers/misc/ocxl/trace.h | 125 ++++++++++++++++++
> 5 files changed, 348 insertions(+), 24 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h
> index d37ededca3ee..4a23abcc347b 100644
> --- a/arch/powerpc/include/asm/pnv-ocxl.h
> +++ b/arch/powerpc/include/asm/pnv-ocxl.h
> @@ -28,4 +28,6 @@ int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **p
> void pnv_ocxl_spa_release(void *platform_data);
> int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
>
> +extern int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
> + uint64_t lpcr);
"extern" is useless
> #endif /* _ASM_PNV_OCXL_H */
> diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c
> index ecdad219d704..100546ea635f 100644
> --- a/arch/powerpc/platforms/powernv/ocxl.c
> +++ b/arch/powerpc/platforms/powernv/ocxl.c
> @@ -483,3 +483,22 @@ int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle)
> return rc;
> }
> EXPORT_SYMBOL_GPL(pnv_ocxl_spa_remove_pe_from_cache);
> +
> +int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
> + uint64_t lpcr)
> +{
> + struct pci_controller *hose = pci_bus_to_host(dev->bus);
> + struct pnv_phb *phb = hose->private_data;
> + u32 bdfn;
> + int rc;
> +
> + bdfn = (dev->bus->number << 8) | dev->devfn;
I was told a bit too late that pci_dev_id() exists, so we should
probably use from now on.
> + rc = opal_npu_map_lpar(phb->opal_id, bdfn, lparid, lpcr);
> + if (rc) {
> + dev_err(&dev->dev, "Error mapping device to LPAR: %d\n", rc);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(pnv_ocxl_map_lpar);
> diff --git a/drivers/misc/ocxl/link.c b/drivers/misc/ocxl/link.c
> index fd73d3bc0eb6..9b5b77d40734 100644
> --- a/drivers/misc/ocxl/link.c
> +++ b/drivers/misc/ocxl/link.c
Overall, there are many changes in that file and it would help the
review if it could be broken up in a set of smaller patches.
> @@ -4,6 +4,8 @@
> #include <linux/mutex.h>
> #include <linux/mm_types.h>
> #include <linux/mmu_context.h>
> +#include <linux/mm.h>
> +#include <linux/mmu_notifier.h>
> #include <asm/copro.h>
> #include <asm/pnv-ocxl.h>
> #include <asm/xive.h>
> @@ -33,6 +35,31 @@
>
> #define SPA_PE_VALID 0x80000000
>
> +struct spa;
> +
> +/*
> + * A opencapi link can be used be by several PCI functions. We have
> + * one link per device slot.
> + *
> + * A linked list of opencapi links should suffice, as there's a
> + * limited number of opencapi slots on a system and lookup is only
> + * done when the device is probed
> + */
> +struct ocxl_link {
> + struct list_head list;
> + struct kref ref;
> + int domain;
> + int bus;
> + int dev;
> + u64 mmio_atsd; /* ATSD physical address */
> + void __iomem *base; /* ATSD register virtual address */
> + spinlock_t atsd_lock; // to serialize shootdowns
> + atomic_t irq_available;
> + struct spa *spa;
> + void *platform_data;
> +};
> +static struct list_head links_list = LIST_HEAD_INIT(links_list);
> +static DEFINE_MUTEX(links_list_lock);
>
> struct pe_data {
> struct mm_struct *mm;
> @@ -41,6 +68,8 @@ struct pe_data {
> /* opaque pointer to be passed to the above callback */
> void *xsl_err_data;
> struct rcu_head rcu;
> + struct ocxl_link *link;
> + struct mmu_notifier mmu_notifier;
> };
>
> struct spa {
> @@ -69,27 +98,6 @@ struct spa {
> } xsl_fault;
> };
>
> -/*
> - * A opencapi link can be used be by several PCI functions. We have
> - * one link per device slot.
> - *
> - * A linked list of opencapi links should suffice, as there's a
> - * limited number of opencapi slots on a system and lookup is only
> - * done when the device is probed
> - */
> -struct ocxl_link {
> - struct list_head list;
> - struct kref ref;
> - int domain;
> - int bus;
> - int dev;
> - atomic_t irq_available;
> - struct spa *spa;
> - void *platform_data;
> -};
> -static struct list_head links_list = LIST_HEAD_INIT(links_list);
> -static DEFINE_MUTEX(links_list_lock);
> -
> enum xsl_response {
> CONTINUE,
> ADDRESS_ERROR,
> @@ -126,6 +134,8 @@ static void ack_irq(struct spa *spa, enum xsl_response r)
> }
> }
>
> +static const struct mmu_notifier_ops ocxl_mmu_notifier_ops;
> +
> static void xsl_fault_handler_bh(struct work_struct *fault_work)
> {
> vm_fault_t flt = 0;
> @@ -376,6 +386,7 @@ static void free_spa(struct ocxl_link *link)
>
> static int alloc_link(struct pci_dev *dev, int PE_mask, struct ocxl_link **out_link)
> {
> + struct pci_controller *hose = pci_bus_to_host(dev->bus);
> struct ocxl_link *link;
> int rc;
>
> @@ -403,6 +414,22 @@ static int alloc_link(struct pci_dev *dev, int PE_mask, struct ocxl_link **out_l
> if (rc)
> goto err_xsl_irq;
>
> + /* Since OpenCAPI 5.0, Address Translation Mode requires TLB
> + * and SLB Invalidate operations to be initiated using MMIO
> + * registers
> + */
> + if (of_property_read_u64_index(hose->dn, "ibm,mmio-atsd",
> + 0, &link->mmio_atsd)) {
> + dev_info(&dev->dev, "No available ATSD found\n");
> + }
> + if (link->mmio_atsd) {
> + link->base = ioremap(link->mmio_atsd, 24);
> + if (!link->base)
> + dev_warn(&dev->dev, "ioremap failed - mmio_atsd: %#llx\n", link->mmio_atsd);
> + else
> + pnv_ocxl_map_lpar(dev, mfspr(SPRN_LPID), 0);
> + }
To stay coherent with how we've done things like interrupts, the
device tree parsing and ioremap() for the shootdown page should be
done in a platform-specific file (powernv)
Also, could we get a more descriptive name than link->base?
> +
> *out_link = link;
> return 0;
>
> @@ -464,12 +491,101 @@ void ocxl_link_release(struct pci_dev *dev, void *link_handle)
> {
> struct ocxl_link *link = (struct ocxl_link *) link_handle;
>
> + if (link->base) {
> + iounmap(link->base);
> + link->base = NULL;
> + }
What's allocated in alloc_link(), i.e. the shootdown page, should be
released in release_xsl() and not in ocxl_link_release() (it's too
early in case of several functions).
> mutex_lock(&links_list_lock);
> kref_put(&link->ref, release_xsl);
> mutex_unlock(&links_list_lock);
> }
> EXPORT_SYMBOL_GPL(ocxl_link_release);
>
> +static void tlb_invalidate(struct ocxl_link *link,
> + unsigned long pid,
> + unsigned long addr)
> +{
> + unsigned long timeout = jiffies + (HZ * OCXL_ATSD_TIMEOUT);
> + uint64_t val;
> + int pend;
> +
> + if (!link->base)
> + return;
> +
> + spin_lock(&link->atsd_lock);
Looks like atsd_lock is not initialized.
> + if (addr) {
> + /* load Abbreviated Virtual Address register with
> + * the necessary value
> + */
> + val = SETFIELD(XTS_ATSD_AVA_AVA, 0ull, addr >> (63-51));
> + out_be64(link->base + XTS_ATSD_AVA, val);
> + eieio();
That eieio() needs a comment.
> + trace_ocxl_mmu_notifier_mmio_atsd_ava(val, pid);
> + }
> +
> + /* Write access initiates a shoot down to initiate the
> + * TLB Invalidate command
> + */
> + val = XTS_ATSD_LNCH_R;
All that code should be in a platform-specific file.
> + if (addr) {
> + val = SETFIELD(XTS_ATSD_LNCH_RIC, val, 0b00);
> + val = SETFIELD(XTS_ATSD_LNCH_IS, val, 0b00);
> + } else {
> + val = SETFIELD(XTS_ATSD_LNCH_RIC, val, 0b10);
> + val = SETFIELD(XTS_ATSD_LNCH_IS, val, 0b01);
> + val |= XTS_ATSD_LNCH_OCAPI_SINGLETON;
> + }
> + val |= XTS_ATSD_LNCH_PRS;
> + val = SETFIELD(XTS_ATSD_LNCH_AP, val, 0b101);
> + val = SETFIELD(XTS_ATSD_LNCH_PID, val, pid);
> + out_be64(link->base + XTS_ATSD_LNCH, val);
> + trace_ocxl_mmu_notifier_mmio_atsd_lnch(val, addr, pid);
> +
> + /* Poll the ATSD status register to determine when the
> + * TLB Invalidate has been completed.
> + */
> + val = in_be64(link->base + XTS_ATSD_STAT);
> + pend = val >> 63;
> + trace_ocxl_mmu_notifier_mmio_atsd_stat(val, addr, pid);
> +
> + while (pend) {
> + if (time_after_eq(jiffies, timeout)) {
> + pr_err("%s - Timeout while reading XTS MMIO ATSD status register (val=%#llx, pidr=0x%lx)\n",
> + __func__, val, pid);
> + spin_unlock(&link->atsd_lock);
> + return;
> + }
> + cpu_relax();
> + val = in_be64(link->base + XTS_ATSD_STAT);
> + pend = val >> 63;
> + }
> + spin_unlock(&link->atsd_lock);
> + trace_ocxl_mmu_notifier_mmio_atsd_stat(val, addr, pid);
> +}
> +
> +static void invalidate_range_end(struct mmu_notifier *mn,
> + const struct mmu_notifier_range *range)
> +{
> + struct pe_data *pe_data = container_of(mn, struct pe_data, mmu_notifier);
> + struct ocxl_link *link = pe_data->link;
> + struct mm_struct *mm = mn->mm;
> + unsigned long addr, pid, page_size = PAGE_SIZE;
> +
> + pid = mm->context.id;
> + trace_ocxl_mmu_notifier_range(range->start, range->end, pid);
> +
> + for (addr = range->start; addr < range->end; addr += page_size)
> + tlb_invalidate(link, pid, addr);
> +}
> +
> +static const struct mmu_notifier_ops ocxl_mmu_notifier_ops = {
> + /* invalidate_range_end() is called when all pages in the
> + * range have been unmapped and the pages have been freed by
> + * the VM
> + */
> + .invalidate_range_end = invalidate_range_end,
> +};
> +
See comments in mmu_notifier.h. Looks like we shouldn't be using
invalidate_range_end(), it's too late
Did we test abrupt death of the host process? Do we need to also use
.release()?
> static u64 calculate_cfg_state(bool kernel)
> {
> u64 state;
> @@ -517,7 +633,7 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
> goto unlock;
> }
>
> - pe_data = kmalloc(sizeof(*pe_data), GFP_KERNEL);
> + pe_data = kzalloc(sizeof(*pe_data), GFP_KERNEL);
> if (!pe_data) {
> rc = -ENOMEM;
> goto unlock;
> @@ -526,9 +642,13 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
> pe_data->mm = mm;
> pe_data->xsl_err_cb = xsl_err_cb;
> pe_data->xsl_err_data = xsl_err_data;
> + pe_data->link = link;
> + pe_data->mmu_notifier.ops = &ocxl_mmu_notifier_ops;
>
> memset(pe, 0, sizeof(struct ocxl_process_element));
> pe->config_state = cpu_to_be64(calculate_cfg_state(pidr == 0));
> + pe->pasid = cpu_to_be32(pasid << (31 - 19));
> + pe->bdf = cpu_to_be32(1 << (31 - 15));
why do we hard-code bdf 1?
> pe->lpid = cpu_to_be32(mfspr(SPRN_LPID));
> pe->pid = cpu_to_be32(pidr);
> pe->tid = cpu_to_be32(tidr);
> @@ -540,8 +660,17 @@ int ocxl_link_add_pe(void *link_handle, int pasid, u32 pidr, u32 tidr,
> * by the nest MMU. If we have a kernel context, TLBIs are
> * already global.
> */
> - if (mm)
> + if (mm) {
> mm_context_add_copro(mm);
> + if (link->base) {
> + /* Use MMIO registers for the TLB and SLB
> + * Invalidate operations.
> + */
> + trace_init_mmu_notifier(pasid, mm->context.id);
> + mmu_notifier_register(&pe_data->mmu_notifier, mm);
> + }
> + }
> +
> /*
> * Barrier is to make sure PE is visible in the SPA before it
> * is used by the device. It also helps with the global TLBI
> @@ -672,6 +801,11 @@ int ocxl_link_remove_pe(void *link_handle, int pasid)
> WARN(1, "Couldn't find pe data when removing PE\n");
> } else {
> if (pe_data->mm) {
> + if (link->base) {
> + trace_release_mmu_notifier(pasid, pe_data->mm->context.id);
> + mmu_notifier_unregister(&pe_data->mmu_notifier, pe_data->mm);
> + tlb_invalidate(link, pe_data->mm->context.id, 0ull);
> + }
> mm_context_remove_copro(pe_data->mm);
> mmdrop(pe_data->mm);
> }
> diff --git a/drivers/misc/ocxl/ocxl_internal.h b/drivers/misc/ocxl/ocxl_internal.h
> index 0bad0a123af6..35d8be3cd270 100644
> --- a/drivers/misc/ocxl/ocxl_internal.h
> +++ b/drivers/misc/ocxl/ocxl_internal.h
> @@ -8,6 +8,48 @@
> #include <linux/list.h>
> #include <misc/ocxl.h>
>
> +/* Find left shift from first set bit in mask */
> +#define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
> +
> +/* Set field fname of oval to fval
> + * NOTE: oval isn't modified, the combined result is returned
> + */
> +#define SETFIELD(m, v, val) \
> + (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
> +
> +#define OCXL_ATSD_TIMEOUT 1
> +
> +/* 5.9.3.3 TLB Management Instructions - PowerISA tags workbook */
> +#define XTS_ATSD_LNCH 0x00
> +#define XTS_ATSD_LNCH_R PPC_BIT(0) /* Radix Invalidate */
> +#define XTS_ATSD_LNCH_RIC PPC_BITMASK(1,2) /* Radix Invalidation Control
> + * 0b00 Just invalidate TLB.
> + * 0b01 Invalidate just Page Walk Cache.
> + * 0b10 Invalidate TLB, Page Walk Cache, and any
> + * caching of Partition and Process Table Entries.
> + */
> +#define XTS_ATSD_LNCH_LP PPC_BITMASK(3, 10) /* Number and Page Size of translations to be invalidated (HPT only ?) */
> +#define XTS_ATSD_LNCH_IS PPC_BITMASK(11, 12) /* Invalidation Criteria
> + * 0b00 Invalidate just the target VA.
> + * 0b01 Invalidate matching PID.
> + */
> +#define XTS_ATSD_LNCH_PRS PPC_BIT(13) /* 0b1: Process Scope, 0b0: Partition Scope */
> +#define XTS_ATSD_LNCH_B PPC_BIT(14) /* Invalidation Flag */
> +#define XTS_ATSD_LNCH_AP PPC_BITMASK(15, 17) /* Actual Page Size to be invalidated
> + * 000 4KB
> + * 101 64KB
> + * 001 2MB
> + * 010 1GB
> + */
> +#define XTS_ATSD_LNCH_L PPC_BIT(18) /* Defines the large page select (L=0b0 for 4KB pages, L=0b1 for large pages) */
> +#define XTS_ATSD_LNCH_PID PPC_BITMASK(19, 38) /* Process ID */
> +#define XTS_ATSD_LNCH_F PPC_BIT(39) /* NoFlush – Assumed to be 0b0 */
> +#define XTS_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40)
> +#define XTS_ATSD_LNCH_OCAPI_SINGLETON PPC_BIT(41)
> +#define XTS_ATSD_AVA 0x08
> +#define XTS_ATSD_AVA_AVA PPC_BITMASK(0, 51) /* au lieu de 35*/
> +#define XTS_ATSD_STAT 0x10
> +
> #define MAX_IRQ_PER_LINK 2000
> #define MAX_IRQ_PER_CONTEXT MAX_IRQ_PER_LINK
>
> @@ -84,7 +126,9 @@ struct ocxl_context {
>
> struct ocxl_process_element {
> __be64 config_state;
> - __be32 reserved1[11];
> + __be32 pasid;
> + __be32 bdf;
> + __be32 reserved1[9];
> __be32 lpid;
> __be32 tid;
> __be32 pid;
> diff --git a/drivers/misc/ocxl/trace.h b/drivers/misc/ocxl/trace.h
> index 17e21cb2addd..6171069d071a 100644
> --- a/drivers/misc/ocxl/trace.h
> +++ b/drivers/misc/ocxl/trace.h
I haven't looked at this yet. It should probably be in a separate patch.
Fred
> @@ -8,6 +8,131 @@
>
> #include <linux/tracepoint.h>
>
> +
> +TRACE_EVENT(ocxl_mmu_notifier_range,
> + TP_PROTO(unsigned long start, unsigned long end, unsigned long pidr),
> + TP_ARGS(start, end, pidr),
> +
> + TP_STRUCT__entry(
> + __field(unsigned long, start)
> + __field(unsigned long, end)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->start = start;
> + __entry->end = end;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("start=0x%lx end=0x%lx pidr=0x%lx",
> + __entry->start,
> + __entry->end,
> + __entry->pidr
> + )
> +);
> +
> +TRACE_EVENT(ocxl_mmu_notifier_mmio_atsd_ava,
> + TP_PROTO(u64 val, unsigned long pidr),
> + TP_ARGS(val, pidr),
> +
> + TP_STRUCT__entry(
> + __field(u64, val)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->val = val;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("ATSD AVA: 0x%llx pidr=0x%lx",
> + __entry->val, __entry->pidr
> + )
> +);
> +
> +TRACE_EVENT(ocxl_mmu_notifier_mmio_atsd_lnch,
> + TP_PROTO(u64 val, unsigned long addr, unsigned long pidr),
> + TP_ARGS(val, addr, pidr),
> +
> + TP_STRUCT__entry(
> + __field(u64, val)
> + __field(unsigned long, addr)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->val = val;
> + __entry->addr = addr;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("ATSD LNCH: 0x%llx addr=0x%lx pidr=0x%lx",
> + __entry->val, __entry->addr, __entry->pidr
> + )
> +);
> +
> +TRACE_EVENT(ocxl_mmu_notifier_mmio_atsd_stat,
> + TP_PROTO(u64 val, unsigned long addr, unsigned long pidr),
> + TP_ARGS(val, addr, pidr),
> +
> + TP_STRUCT__entry(
> + __field(u64, val)
> + __field(unsigned long, addr)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->val = val;
> + __entry->addr = addr;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("ATSD STAT: 0x%llx addr=0x%lx pidr=0x%lx",
> + __entry->val, __entry->addr, __entry->pidr
> + )
> +);
> +
> +TRACE_EVENT(init_mmu_notifier,
> + TP_PROTO(int pasid, unsigned long pidr),
> + TP_ARGS(pasid, pidr),
> +
> + TP_STRUCT__entry(
> + __field(int, pasid)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->pasid = pasid;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("pasid=%d, pidr=0x%lx",
> + __entry->pasid,
> + __entry->pidr
> + )
> +);
> +
> +TRACE_EVENT(release_mmu_notifier,
> + TP_PROTO(int pasid, unsigned long pidr),
> + TP_ARGS(pasid, pidr),
> +
> + TP_STRUCT__entry(
> + __field(int, pasid)
> + __field(unsigned long, pidr)
> + ),
> +
> + TP_fast_assign(
> + __entry->pasid = pasid;
> + __entry->pidr = pidr;
> + ),
> +
> + TP_printk("pasid=%d, pidr=0x%lx",
> + __entry->pasid,
> + __entry->pidr
> + )
> +);
> +
> DECLARE_EVENT_CLASS(ocxl_context,
> TP_PROTO(pid_t pid, void *spa, int pasid, u32 pidr, u32 tidr),
> TP_ARGS(pid, spa, pasid, pidr, tidr),
>
^ permalink raw reply
* Re: [PATCH net-next 02/12] ibmvnic: Introduce indirect subordinate Command Response Queue buffer
From: Thomas Falcon @ 2020-11-16 18:18 UTC (permalink / raw)
To: Jakub Kicinski
Cc: cforno12, netdev, ljp, ricklind, dnbanerg, drt, brking, sukadev,
linuxppc-dev
In-Reply-To: <20201114153501.66072756@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
On 11/14/20 5:35 PM, Jakub Kicinski wrote:
> On Thu, 12 Nov 2020 13:09:57 -0600 Thomas Falcon wrote:
>> This patch introduces the infrastructure to send batched subordinate
>> Command Response Queue descriptors, which are used by the ibmvnic
>> driver to send TX frame and RX buffer descriptors.
>>
>> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
>> @@ -2957,6 +2963,19 @@ static struct ibmvnic_sub_crq_queue *init_sub_crq_queue(struct ibmvnic_adapter
>>
>> scrq->adapter = adapter;
>> scrq->size = 4 * PAGE_SIZE / sizeof(*scrq->msgs);
>> + scrq->ind_buf.index = 0;
>> +
>> + scrq->ind_buf.indir_arr =
>> + dma_alloc_coherent(dev,
>> + IBMVNIC_IND_ARR_SZ,
>> + &scrq->ind_buf.indir_dma,
>> + GFP_KERNEL);
>> +
>> + if (!scrq->ind_buf.indir_arr) {
>> + dev_err(dev, "Couldn't allocate indirect scrq buffer\n");
> This warning/error is not necessary, memory allocation will trigger an
> OOM message already.
Thanks, I can fix that in a v2.
>
>> + goto reg_failed;
> Don't you have to do something like
>
> rc = plpar_hcall_norets(H_FREE_SUB_CRQ,
> adapter->vdev->unit_address,
> scrq->crq_num);
>
> ?
Yes, you're right, I will include that in a v2 also.
>> + }
>> +
>> spin_lock_init(&scrq->lock);
>>
^ permalink raw reply
* Re: [PATCH net-next 01/12] ibmvnic: Ensure that subCRQ entry reads are ordered
From: Thomas Falcon @ 2020-11-16 18:28 UTC (permalink / raw)
To: Jakub Kicinski
Cc: cforno12, netdev, ljp, ricklind, dnbanerg, drt, brking, sukadev,
linuxppc-dev
In-Reply-To: <20201114153524.1a32241f@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
On 11/14/20 5:35 PM, Jakub Kicinski wrote:
> On Thu, 12 Nov 2020 13:09:56 -0600 Thomas Falcon wrote:
>> Ensure that received Subordinate Command-Response Queue
>> entries are properly read in order by the driver.
>>
>> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
> Are you sure this is not a bug fix?
Yes, I guess it does look like a bug fix. I can omit this in v2 and
submit this as a stand-alone patch to net?
^ permalink raw reply
* Re: [PATCH net-next 01/12] ibmvnic: Ensure that subCRQ entry reads are ordered
From: Jakub Kicinski @ 2020-11-16 18:30 UTC (permalink / raw)
To: Thomas Falcon
Cc: cforno12, netdev, ljp, ricklind, dnbanerg, drt, brking, sukadev,
linuxppc-dev
In-Reply-To: <b0cd74bb-8f05-a201-080c-e325ae4a27b2@linux.ibm.com>
On Mon, 16 Nov 2020 12:28:05 -0600 Thomas Falcon wrote:
> On 11/14/20 5:35 PM, Jakub Kicinski wrote:
> > On Thu, 12 Nov 2020 13:09:56 -0600 Thomas Falcon wrote:
> >> Ensure that received Subordinate Command-Response Queue
> >> entries are properly read in order by the driver.
> >>
> >> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
> > Are you sure this is not a bug fix?
> Yes, I guess it does look like a bug fix. I can omit this in v2 and
> submit this as a stand-alone patch to net?
Yup, that's the preferred way. Thanks!
^ permalink raw reply
* Re: [PATCH net-next 04/12] ibmvnic: Introduce xmit_more support using batched subCRQ hcalls
From: Thomas Falcon @ 2020-11-16 18:40 UTC (permalink / raw)
To: Jakub Kicinski
Cc: cforno12, netdev, ljp, ricklind, dnbanerg, drt, brking, sukadev,
linuxppc-dev
In-Reply-To: <20201114154632.55e87b1c@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
On 11/14/20 5:46 PM, Jakub Kicinski wrote:
> On Thu, 12 Nov 2020 13:09:59 -0600 Thomas Falcon wrote:
>> Include support for the xmit_more feature utilizing the
>> H_SEND_SUB_CRQ_INDIRECT hypervisor call which allows the sending
>> of multiple subordinate Command Response Queue descriptors in one
>> hypervisor call via a DMA-mapped buffer. This update reduces hypervisor
>> calls and thus hypervisor call overhead per TX descriptor.
>>
>> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
> The common bug with xmit_more is not flushing the already queued
> notifications when there is a drop. Any time you drop a skb you need
> to check it's not an skb that was the end of an xmit_more train and
> if so flush notifications (or just always flush on error).
>
> Looking at the driver e.g. this starting goto:
>
> if (ibmvnic_xmit_workarounds(skb, netdev)) {
> tx_dropped++;
> tx_send_failed++;
> ret = NETDEV_TX_OK;
> goto out;
> }
>
> Does not seem to hit any flush on its way out AFAICS.
Hi, I included those updates in a later patch to ease review but see now
that that was a mistake. I will merge those bits back into this patch
and resubmit.
Thanks!
^ permalink raw reply
* Re: [PATCH 3/5] perf/core: Fix arch_perf_get_page_size()
From: Liang, Kan @ 2020-11-16 13:11 UTC (permalink / raw)
To: Peter Zijlstra, mingo, acme, mark.rutland, alexander.shishkin,
jolsa, eranian
Cc: linux-arch, ak, catalin.marinas, linuxppc-dev, willy,
linux-kernel, dave.hansen, npiggin, aneesh.kumar, sparclinux,
will, davem, kirill.shutemov
In-Reply-To: <20201113113426.526012343@infradead.org>
On 11/13/2020 6:19 AM, Peter Zijlstra wrote:
> The (new) page-table walker in arch_perf_get_page_size() is broken in
> various ways. Specifically while it is used in a locless manner, it
> doesn't depend on CONFIG_HAVE_FAST_GUP nor uses the proper _lockless
> offset methods, nor is careful to only read each entry only once.
>
> Also the hugetlb support is broken due to calling pte_page() without
> first checking pte_special().
>
> Rewrite the whole thing to be a proper lockless page-table walker and
> employ the new pXX_leaf_size() pgtable functions to determine the TLB
> size without looking at the page-frames.
>
> Fixes: 51b646b2d9f8 ("perf,mm: Handle non-page-table-aligned hugetlbfs")
> Fixes: 8d97e71811aa ("perf/core: Add PERF_SAMPLE_DATA_PAGE_SIZE")
The issue
(https://lkml.kernel.org/r/8e88ba79-7c40-ea32-a7ed-bdc4fc04b2af@linux.intel.com)
has been fixed by this patch set.
Tested-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> ---
> arch/arm64/include/asm/pgtable.h | 3 +
> arch/sparc/include/asm/pgtable_64.h | 13 ++++
> arch/sparc/mm/hugetlbpage.c | 19 ++++--
> include/linux/pgtable.h | 16 +++++
> kernel/events/core.c | 102 +++++++++++++-----------------------
> 5 files changed, 82 insertions(+), 71 deletions(-)
>
> --- a/kernel/events/core.c
> +++ b/kernel/events/core.c
> @@ -7001,90 +7001,62 @@ static u64 perf_virt_to_phys(u64 virt)
> return phys_addr;
> }
>
> -#ifdef CONFIG_MMU
> -
> /*
> - * Return the MMU page size of a given virtual address.
> - *
> - * This generic implementation handles page-table aligned huge pages, as well
> - * as non-page-table aligned hugetlbfs compound pages.
> - *
> - * If an architecture supports and uses non-page-table aligned pages in their
> - * kernel mapping it will need to provide it's own implementation of this
> - * function.
> + * Return the MMU/TLB page size of a given virtual address.
> */
> -__weak u64 arch_perf_get_page_size(struct mm_struct *mm, unsigned long addr)
> +static u64 perf_get_tlb_page_size(struct mm_struct *mm, unsigned long addr)
> {
> - struct page *page;
> - pgd_t *pgd;
> - p4d_t *p4d;
> - pud_t *pud;
> - pmd_t *pmd;
> - pte_t *pte;
> + u64 size = 0;
>
> - pgd = pgd_offset(mm, addr);
> - if (pgd_none(*pgd))
> - return 0;
> +#ifdef CONFIG_HAVE_FAST_GUP
> + pgd_t *pgdp, pgd;
> + p4d_t *p4dp, p4d;
> + pud_t *pudp, pud;
> + pmd_t *pmdp, pmd;
> + pte_t *ptep, pte;
>
> - p4d = p4d_offset(pgd, addr);
> - if (!p4d_present(*p4d))
> + pgdp = pgd_offset(mm, addr);
> + pgd = READ_ONCE(*pgdp);
> + if (pgd_none(pgd))
> return 0;
>
> - if (p4d_leaf(*p4d))
> - return 1ULL << P4D_SHIFT;
> + if (pgd_leaf(pgd))
> + return pgd_leaf_size(pgd);
>
> - pud = pud_offset(p4d, addr);
> - if (!pud_present(*pud))
> + p4dp = p4d_offset_lockless(pgdp, pgd, addr);
> + p4d = READ_ONCE(*p4dp);
> + if (!p4d_present(p4d))
> return 0;
>
> - if (pud_leaf(*pud)) {
> -#ifdef pud_page
> - page = pud_page(*pud);
> - if (PageHuge(page))
> - return page_size(compound_head(page));
> -#endif
> - return 1ULL << PUD_SHIFT;
> - }
> + if (p4d_leaf(p4d))
> + return p4d_leaf_size(p4d);
>
> - pmd = pmd_offset(pud, addr);
> - if (!pmd_present(*pmd))
> + pudp = pud_offset_lockless(p4dp, p4d, addr);
> + pud = READ_ONCE(*pudp);
> + if (!pud_present(pud))
> return 0;
>
> - if (pmd_leaf(*pmd)) {
> -#ifdef pmd_page
> - page = pmd_page(*pmd);
> - if (PageHuge(page))
> - return page_size(compound_head(page));
> -#endif
> - return 1ULL << PMD_SHIFT;
> - }
> + if (pud_leaf(pud))
> + return pud_leaf_size(pud);
>
> - pte = pte_offset_map(pmd, addr);
> - if (!pte_present(*pte)) {
> - pte_unmap(pte);
> + pmdp = pmd_offset_lockless(pudp, pud, addr);
> + pmd = READ_ONCE(*pmdp);
> + if (!pmd_present(pmd))
> return 0;
> - }
>
> - page = pte_page(*pte);
> - if (PageHuge(page)) {
> - u64 size = page_size(compound_head(page));
> - pte_unmap(pte);
> - return size;
> - }
> -
> - pte_unmap(pte);
> - return PAGE_SIZE;
> -}
> + if (pmd_leaf(pmd))
> + return pmd_leaf_size(pmd);
>
> -#else
> + ptep = pte_offset_map(&pmd, addr);
> + pte = ptep_get_lockless(ptep);
> + if (pte_present(pte))
> + size = pte_leaf_size(pte);
> + pte_unmap(ptep);
> +#endif /* CONFIG_HAVE_FAST_GUP */
>
> -static u64 arch_perf_get_page_size(struct mm_struct *mm, unsigned long addr)
> -{
> - return 0;
> + return size;
> }
>
> -#endif
> -
> static u64 perf_get_page_size(unsigned long addr)
> {
> struct mm_struct *mm;
> @@ -7109,7 +7081,7 @@ static u64 perf_get_page_size(unsigned l
> mm = &init_mm;
> }
>
> - size = arch_perf_get_page_size(mm, addr);
> + size = perf_get_tlb_page_size(mm, addr);
>
> local_irq_restore(flags);
>
>
>
^ permalink raw reply
* Re: [PATCH] powerpc: Drop -me200 addition to build flags
From: Scott Wood @ 2020-11-16 20:26 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: natechancellor, ndesaulniers, linux-kernel
In-Reply-To: <20201116120913.165317-1-mpe@ellerman.id.au>
On Mon, 2020-11-16 at 23:09 +1100, Michael Ellerman wrote:
> Currently a build with CONFIG_E200=y will fail with:
>
> Error: invalid switch -me200
> Error: unrecognized option -me200
>
> Upstream binutils has never supported an -me200 option. Presumably it
> was supported at some point by either a fork or Freescale internal
> binutils.
>
> We can't support code that we can't even build test, so drop the
> addition of -me200 to the build flags, so we can at least build with
> CONFIG_E200=y.
>
> Reported-by: Németh Márton <nm127@freemail.hu>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
> ---
>
> More discussion:
> https://lore.kernel.org/lkml/202011131146.g8dPLQDD-lkp@intel.com
> ---
> arch/powerpc/Makefile | 1 -
> 1 file changed, 1 deletion(-)
Acked-by: Scott Wood <oss@buserror.net>
I'd go further and remove E200 code entirely, unless someone with the hardware
can claim that it actually works. There doesn't appear to be any actual
platform support for an e200-based system. It seems to be a long-abandoned
work in progress.
-Scott
^ permalink raw reply
* Re: Error: invalid switch -me200
From: Scott Wood @ 2020-11-16 20:27 UTC (permalink / raw)
To: Segher Boessenkool, Fāng-ruì Sòng
Cc: Arnd Bergmann, kbuild-all, kernel test robot, Brian Cain,
Alan Modra, Linus Torvalds, Masahiro Yamada, Nick Desaulniers,
LKML, clang-built-linux, Nathan Chancellor, linuxppc-dev
In-Reply-To: <20201114005015.GZ2672@gate.crashing.org>
On Fri, 2020-11-13 at 18:50 -0600, Segher Boessenkool wrote:
> On Fri, Nov 13, 2020 at 04:37:38PM -0800, Fāng-ruì Sòng wrote:
> > On Fri, Nov 13, 2020 at 4:23 PM Segher Boessenkool
> > <segher@kernel.crashing.org> wrote:
> > > On Fri, Nov 13, 2020 at 12:14:18PM -0800, Nick Desaulniers wrote:
> > > > > > > Error: invalid switch -me200
> > > > > > > Error: unrecognized option -me200
> > > > > >
> > > > > > 251 cpu-as-$(CONFIG_E200) += -Wa,-me200
> > > > > >
> > > > > > Are those all broken configs, or is Kconfig messed up such that
> > > > > > randconfig can select these when it should not?
> > > > >
> > > > > Hmmm, looks like this flag does not exist in mainline binutils?
> > > > > There is
> > > > > a thread in 2010 about this that Segher commented on:
> > > > >
> > > > >
https://lore.kernel.org/linuxppc-dev/9859E645-954D-4D07-8003-FFCD2391AB6E@kernel.crashing.org/
> > > > >
> > > > > Guess this config should be eliminated?
> > >
> > > The help text for this config options says that e200 is used in 55xx,
> > > and there *is* an -me5500 GAS flag (which probably does this same
> > > thing, too). But is any of this tested, or useful, or wanted?
> > >
> > > Maybe Christophe knows, cc:ed.
> >
> > CC Alan Modra, a binutils global maintainer.
> >
> > Alan, can the few -Wa,-m* options deleted from arch/powerpc/Makefile ?
>
> All the others work fine (and are needed afaics), it is only -me200 that
> doesn't exist (in mainline binutils). Perhaps -me5500 will work for it
> instead.
According to Wikipedia e200 is from mpc55xx (for which I don't see any
platform support having ever been added). e5500 is completely different (64-
bit version of e500mc).
-Scott
^ permalink raw reply
* Re: Error: invalid switch -me200
From: Segher Boessenkool @ 2020-11-16 20:47 UTC (permalink / raw)
To: Scott Wood
Cc: Arnd Bergmann, kbuild-all, kernel test robot, Brian Cain,
Alan Modra, Linus Torvalds, Masahiro Yamada, Nick Desaulniers,
LKML, clang-built-linux, Fāng-ruì Sòng,
Nathan Chancellor, linuxppc-dev
In-Reply-To: <e19e3a9f47c988b30a19316ee3de2b588e20a641.camel@buserror.net>
On Mon, Nov 16, 2020 at 02:27:12PM -0600, Scott Wood wrote:
> On Fri, 2020-11-13 at 18:50 -0600, Segher Boessenkool wrote:
> > All the others work fine (and are needed afaics), it is only -me200 that
> > doesn't exist (in mainline binutils). Perhaps -me5500 will work for it
> > instead.
>
> According to Wikipedia e200 is from mpc55xx (for which I don't see any
> platform support having ever been added). e5500 is completely different (64-
> bit version of e500mc).
Ah yes, confusing processor numbers :-( That explains, sorry.
Segher
^ permalink raw reply
* Re: [PATCH] powerpc: Drop -me200 addition to build flags
From: Nick Desaulniers @ 2020-11-16 23:34 UTC (permalink / raw)
To: Michael Ellerman; +Cc: LKML, oss, linuxppc-dev, Nathan Chancellor
In-Reply-To: <20201116120913.165317-1-mpe@ellerman.id.au>
On Mon, Nov 16, 2020 at 4:09 AM Michael Ellerman <mpe@ellerman.id.au> wrote:
>
> Currently a build with CONFIG_E200=y will fail with:
>
> Error: invalid switch -me200
> Error: unrecognized option -me200
>
> Upstream binutils has never supported an -me200 option. Presumably it
> was supported at some point by either a fork or Freescale internal
> binutils.
>
> We can't support code that we can't even build test, so drop the
> addition of -me200 to the build flags, so we can at least build with
> CONFIG_E200=y.
>
> Reported-by: Németh Márton <nm127@freemail.hu>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Thanks for the patch; this should make randconfig builds not pick this
non-buildable config.
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
> ---
>
> More discussion: https://lore.kernel.org/lkml/202011131146.g8dPLQDD-lkp@intel.com
> ---
> arch/powerpc/Makefile | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
> index a4d56f0a41d9..16b8336f91dd 100644
> --- a/arch/powerpc/Makefile
> +++ b/arch/powerpc/Makefile
> @@ -248,7 +248,6 @@ KBUILD_CFLAGS += $(call cc-option,-mno-string)
> cpu-as-$(CONFIG_40x) += -Wa,-m405
> cpu-as-$(CONFIG_44x) += -Wa,-m440
> cpu-as-$(CONFIG_ALTIVEC) += $(call as-option,-Wa$(comma)-maltivec)
> -cpu-as-$(CONFIG_E200) += -Wa,-me200
> cpu-as-$(CONFIG_E500) += -Wa,-me500
>
> # When using '-many -mpower4' gas will first try and find a matching power4
> --
> 2.25.1
>
--
Thanks,
~Nick Desaulniers
^ permalink raw reply
* Re: Error: invalid switch -me200
From: Alan Modra @ 2020-11-16 23:59 UTC (permalink / raw)
To: Segher Boessenkool
Cc: Arnd Bergmann, kbuild-all, Brian Cain,
Fāng-ruì Sòng, Masahiro Yamada, linuxppc-dev,
Nick Desaulniers, LKML, clang-built-linux, Nathan Chancellor,
Linus Torvalds, kernel test robot
In-Reply-To: <20201114005015.GZ2672@gate.crashing.org>
On Fri, Nov 13, 2020 at 06:50:15PM -0600, Segher Boessenkool wrote:
> On Fri, Nov 13, 2020 at 04:37:38PM -0800, Fāng-ruì Sòng wrote:
> > On Fri, Nov 13, 2020 at 4:23 PM Segher Boessenkool
> > <segher@kernel.crashing.org> wrote:
> > > On Fri, Nov 13, 2020 at 12:14:18PM -0800, Nick Desaulniers wrote:
> > > > > > > Error: invalid switch -me200
> > > > > > > Error: unrecognized option -me200
> > > > > >
> > > > > > 251 cpu-as-$(CONFIG_E200) += -Wa,-me200
> > > > > >
> > > > > > Are those all broken configs, or is Kconfig messed up such that
> > > > > > randconfig can select these when it should not?
> > > > >
> > > > > Hmmm, looks like this flag does not exist in mainline binutils? There is
> > > > > a thread in 2010 about this that Segher commented on:
> > > > >
> > > > > https://lore.kernel.org/linuxppc-dev/9859E645-954D-4D07-8003-FFCD2391AB6E@kernel.crashing.org/
> > > > >
> > > > > Guess this config should be eliminated?
> > >
> > > The help text for this config options says that e200 is used in 55xx,
> > > and there *is* an -me5500 GAS flag (which probably does this same
> > > thing, too). But is any of this tested, or useful, or wanted?
> > >
> > > Maybe Christophe knows, cc:ed.
> >
> > CC Alan Modra, a binutils global maintainer.
> >
> > Alan, can the few -Wa,-m* options deleted from arch/powerpc/Makefile ?
>
> All the others work fine (and are needed afaics), it is only -me200 that
> doesn't exist (in mainline binutils).
Right, and a quick check says it never existed. There is e200z4,
added to binutils with dfdaec14b0d, 2016-08-01, but the kernel -me200
was added in 2005. I suspect the toolchain support only existed
inside Freescale and pushing it upstream was too difficult.
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply
* Re: [PATCH] powerpc/powernv/memtrace: Fake non-memblock aligned sized traces
From: Jordan Niethe @ 2020-11-17 0:03 UTC (permalink / raw)
To: Michael Ellerman; +Cc: Michael Neuling, linuxppc-dev
In-Reply-To: <87blfx4iho.fsf@mpe.ellerman.id.au>
On Mon, Nov 16, 2020 at 11:02 PM Michael Ellerman <mpe@ellerman.id.au> wrote:
>
> Jordan Niethe <jniethe5@gmail.com> writes:
> > The hardware trace macros which use the memory provided by memtrace are
> > able to use trace sizes as small as 16MB. Only memblock aligned values
> > can be removed from each NUMA node by writing that value to
> > memtrace/enable in debugfs. This means setting up, say, a 16MB trace is
> > not possible. To allow such a trace size, instead align whatever value
> > is written to memtrace/enable to the memblock size for the purpose of
> > removing it from each NUMA node but report the written value from
> > memtrace/enable and memtrace/x/size in debugfs.
>
> Why does it matter if the size that's removed is larger than the size
> that was requested?
>
> Is it about constraining the size of the trace? If so that seems like it
> should be the job of the tracing tools, not the kernel.
Yeah about constraining the size, I'll just do it in the trace tools.
>
> cheers
^ permalink raw reply
* Re: [PATCH] ocxl: Mmio invalidation support
From: Andrew Donnellan @ 2020-11-17 0:41 UTC (permalink / raw)
To: Christophe Lombard, linuxppc-dev, fbarrat
In-Reply-To: <20201113153333.290505-1-clombard@linux.vnet.ibm.com>
On 14/11/20 2:33 am, Christophe Lombard wrote:
> OpenCAPI 4.0/5.0 with TLBI/SLBI Snooping, is not used due to performance
> problems caused by the PAU having to process all incoming TLBI/SLBI
> commands which will cause them to back up on the PowerBus.
>
> When the Address Translation Mode requires TLB and SLB Invalidate
> operations to be initiated using MMIO registers, a set of registers like
> the following is used:
> • XTS MMIO ATSD0 LPARID register
> • XTS MMIO ATSD0 AVA register
> • XTS MMIO ATSD0 launch register, write access initiates a shoot down
> • XTS MMIO ATSD0 status register
>
> The MMIO based mechanism also blocks the NPU/PAU from snooping TLBIE
> commands from the PowerBus.
>
> The Shootdown commands (ATSD) will be generated using MMIO registers
> in the NPU/PAU and sent to the device.
>
> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
snowpatch has reported some minor checkpatch issues:
https://openpower.xyz/job/snowpatch/job/snowpatch-linux-checkpatch/16267//artifact/linux/checkpatch.log
--
Andrew Donnellan OzLabs, ADL Canberra
ajd@linux.ibm.com IBM Australia Limited
^ permalink raw reply
* Re: [PATCH 1/2] kbuild: Hoist '--orphan-handling' into Kconfig
From: Nick Desaulniers @ 2020-11-17 1:41 UTC (permalink / raw)
To: Nathan Chancellor
Cc: Michal Marek, Kees Cook, Linux Kbuild mailing list,
Catalin Marinas, Masahiro Yamada,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Russell King,
LKML, linuxppc-dev, Arvind Sankar, Ingo Molnar, Borislav Petkov,
clang-built-linux, Thomas Gleixner, Will Deacon, Linux ARM
In-Reply-To: <20201113195553.1487659-1-natechancellor@gmail.com>
On Fri, Nov 13, 2020 at 11:56 AM Nathan Chancellor
<natechancellor@gmail.com> wrote:
>
> Currently, '--orphan-handling=warn' is spread out across four different
> architectures in their respective Makefiles, which makes it a little
> unruly to deal with in case it needs to be disabled for a specific
> linker version (in this case, ld.lld 10.0.1).
Hi Nathan,
This patch fails to apply for me via b4 on next-20201116 due to a
conflict in arch/Kconfig:1028. Would you mind sending a rebased V2?
--
Thanks,
~Nick Desaulniers
^ permalink raw reply
* Re: [PATCH 1/2] kbuild: Hoist '--orphan-handling' into Kconfig
From: Nathan Chancellor @ 2020-11-17 1:54 UTC (permalink / raw)
To: Nick Desaulniers
Cc: Michal Marek, Kees Cook, Linux Kbuild mailing list,
Catalin Marinas, Masahiro Yamada,
maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT), Russell King,
LKML, linuxppc-dev, Arvind Sankar, Ingo Molnar, Borislav Petkov,
clang-built-linux, Thomas Gleixner, Will Deacon, Linux ARM
In-Reply-To: <CAKwvOdnf5WKJrLnwM9dDDniP0eG5gnFSMB0rapqWLUAZbVJZvQ@mail.gmail.com>
On Mon, Nov 16, 2020 at 05:41:58PM -0800, Nick Desaulniers wrote:
> On Fri, Nov 13, 2020 at 11:56 AM Nathan Chancellor
> <natechancellor@gmail.com> wrote:
> >
> > Currently, '--orphan-handling=warn' is spread out across four different
> > architectures in their respective Makefiles, which makes it a little
> > unruly to deal with in case it needs to be disabled for a specific
> > linker version (in this case, ld.lld 10.0.1).
>
> Hi Nathan,
> This patch fails to apply for me via b4 on next-20201116 due to a
> conflict in arch/Kconfig:1028. Would you mind sending a rebased V2?
Hi Nick,
This series is intended to go into v5.10 so rebasing it against -next
defeats that; please test it against v5.10-rc4, where it still applies
cleanly. The conflicts will be handled by other entities (Stephen Rothwell
and Linus).
If you want to test it against -next, 'git am -3' will allow you to
easily handle the conflict.
Cheers,
Nathan
^ permalink raw reply
* Re: [PATCH 1/3] powerpc: boot: include compiler_attributes.h
From: Nathan Chancellor @ 2020-11-17 3:01 UTC (permalink / raw)
To: Nick Desaulniers
Cc: clang-built-linux, Gustavo A . R . Silva, linux-kernel,
Miguel Ojeda, Paul Mackerras, linuxppc-dev
In-Reply-To: <20201116043532.4032932-2-ndesaulniers@google.com>
On Sun, Nov 15, 2020 at 08:35:30PM -0800, Nick Desaulniers wrote:
> The kernel uses `-include` to include include/linux/compiler_types.h
> into all translation units (see scripts/Makefile.lib), which #includes
> compiler_attributes.h.
>
> arch/powerpc/boot/ uses different compiler flags from the rest of the
> kernel. As such, it doesn't contain the definitions from these headers,
> and redefines a few that it needs.
>
> For the purpose of enabling -Wimplicit-fallthrough for ppc, include
> compiler_types.h via `-include`.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/236
> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
> ---
> We could just `#include "include/linux/compiler_types.h"` in the few .c
> sources used from lib/ (there are proper header guards in
> compiler_types.h).
>
> It was also noted in 6a9dc5fd6170 that we could -D__KERNEL__ and
> -include compiler_types.h like the main kernel does, though testing that
> produces a whole sea of warnings to cleanup. This approach is minimally
> invasive.
>
> arch/powerpc/boot/Makefile | 1 +
> arch/powerpc/boot/decompress.c | 1 -
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
> index f8ce6d2dde7b..1659963a8f1d 100644
> --- a/arch/powerpc/boot/Makefile
> +++ b/arch/powerpc/boot/Makefile
> @@ -31,6 +31,7 @@ endif
> BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
> -fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \
> -pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
> + -include $(srctree)/include/linux/compiler_attributes.h \
> $(LINUXINCLUDE)
>
> ifdef CONFIG_PPC64_BOOT_WRAPPER
> diff --git a/arch/powerpc/boot/decompress.c b/arch/powerpc/boot/decompress.c
> index 8bf39ef7d2df..6098b879ac97 100644
> --- a/arch/powerpc/boot/decompress.c
> +++ b/arch/powerpc/boot/decompress.c
> @@ -21,7 +21,6 @@
>
> #define STATIC static
> #define INIT
> -#define __always_inline inline
>
> /*
> * The build process will copy the required zlib source files and headers
> --
> 2.29.2.299.gdc1121823c-goog
>
^ permalink raw reply
* Re: [PATCH 2/3] Revert "lib: Revert use of fallthrough pseudo-keyword in lib/"
From: Nathan Chancellor @ 2020-11-17 3:02 UTC (permalink / raw)
To: Nick Desaulniers
Cc: clang-built-linux, Gustavo A . R . Silva, linux-kernel,
Miguel Ojeda, Paul Mackerras, linuxppc-dev
In-Reply-To: <20201116043532.4032932-3-ndesaulniers@google.com>
On Sun, Nov 15, 2020 at 08:35:31PM -0800, Nick Desaulniers wrote:
> This reverts commit 6a9dc5fd6170 ("lib: Revert use of fallthrough
> pseudo-keyword in lib/")
>
> Now that we can build arch/powerpc/boot/ free of -Wimplicit-fallthrough,
> re-enable these fixes for lib/.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/236
> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
> ---
> lib/asn1_decoder.c | 4 ++--
> lib/assoc_array.c | 2 +-
> lib/bootconfig.c | 4 ++--
> lib/cmdline.c | 10 +++++-----
> lib/dim/net_dim.c | 2 +-
> lib/dim/rdma_dim.c | 4 ++--
> lib/glob.c | 2 +-
> lib/siphash.c | 36 ++++++++++++++++++------------------
> lib/ts_fsm.c | 2 +-
> lib/vsprintf.c | 14 +++++++-------
> lib/xz/xz_dec_lzma2.c | 4 ++--
> lib/xz/xz_dec_stream.c | 16 ++++++++--------
> lib/zstd/bitstream.h | 10 +++++-----
> lib/zstd/compress.c | 2 +-
> lib/zstd/decompress.c | 12 ++++++------
> lib/zstd/huf_compress.c | 4 ++--
> 16 files changed, 64 insertions(+), 64 deletions(-)
>
> diff --git a/lib/asn1_decoder.c b/lib/asn1_decoder.c
> index 58f72b25f8e9..13da529e2e72 100644
> --- a/lib/asn1_decoder.c
> +++ b/lib/asn1_decoder.c
> @@ -381,7 +381,7 @@ int asn1_ber_decoder(const struct asn1_decoder *decoder,
> case ASN1_OP_END_SET_ACT:
> if (unlikely(!(flags & FLAG_MATCHED)))
> goto tag_mismatch;
> - /* fall through */
> + fallthrough;
>
> case ASN1_OP_END_SEQ:
> case ASN1_OP_END_SET_OF:
> @@ -448,7 +448,7 @@ int asn1_ber_decoder(const struct asn1_decoder *decoder,
> pc += asn1_op_lengths[op];
> goto next_op;
> }
> - /* fall through */
> + fallthrough;
>
> case ASN1_OP_ACT:
> ret = actions[machine[pc + 1]](context, hdr, tag, data + tdp, len);
> diff --git a/lib/assoc_array.c b/lib/assoc_array.c
> index 6f4bcf524554..04c98799c3ba 100644
> --- a/lib/assoc_array.c
> +++ b/lib/assoc_array.c
> @@ -1113,7 +1113,7 @@ struct assoc_array_edit *assoc_array_delete(struct assoc_array *array,
> index_key))
> goto found_leaf;
> }
> - /* fall through */
> + fallthrough;
> case assoc_array_walk_tree_empty:
> case assoc_array_walk_found_wrong_shortcut:
> default:
> diff --git a/lib/bootconfig.c b/lib/bootconfig.c
> index 649ed44f199c..9f8c70a98fcf 100644
> --- a/lib/bootconfig.c
> +++ b/lib/bootconfig.c
> @@ -827,7 +827,7 @@ int __init xbc_init(char *buf, const char **emsg, int *epos)
> q - 2);
> break;
> }
> - /* fall through */
> + fallthrough;
> case '=':
> ret = xbc_parse_kv(&p, q, c);
> break;
> @@ -836,7 +836,7 @@ int __init xbc_init(char *buf, const char **emsg, int *epos)
> break;
> case '#':
> q = skip_comment(q);
> - /* fall through */
> + fallthrough;
> case ';':
> case '\n':
> ret = xbc_parse_key(&p, q);
> diff --git a/lib/cmdline.c b/lib/cmdline.c
> index 9e186234edc0..46f2cb4ce6d1 100644
> --- a/lib/cmdline.c
> +++ b/lib/cmdline.c
> @@ -144,23 +144,23 @@ unsigned long long memparse(const char *ptr, char **retptr)
> case 'E':
> case 'e':
> ret <<= 10;
> - /* fall through */
> + fallthrough;
> case 'P':
> case 'p':
> ret <<= 10;
> - /* fall through */
> + fallthrough;
> case 'T':
> case 't':
> ret <<= 10;
> - /* fall through */
> + fallthrough;
> case 'G':
> case 'g':
> ret <<= 10;
> - /* fall through */
> + fallthrough;
> case 'M':
> case 'm':
> ret <<= 10;
> - /* fall through */
> + fallthrough;
> case 'K':
> case 'k':
> ret <<= 10;
> diff --git a/lib/dim/net_dim.c b/lib/dim/net_dim.c
> index a4db51c21266..06811d866775 100644
> --- a/lib/dim/net_dim.c
> +++ b/lib/dim/net_dim.c
> @@ -233,7 +233,7 @@ void net_dim(struct dim *dim, struct dim_sample end_sample)
> schedule_work(&dim->work);
> break;
> }
> - /* fall through */
> + fallthrough;
> case DIM_START_MEASURE:
> dim_update_sample(end_sample.event_ctr, end_sample.pkt_ctr,
> end_sample.byte_ctr, &dim->start_sample);
> diff --git a/lib/dim/rdma_dim.c b/lib/dim/rdma_dim.c
> index f7e26c7b4749..15462d54758d 100644
> --- a/lib/dim/rdma_dim.c
> +++ b/lib/dim/rdma_dim.c
> @@ -59,7 +59,7 @@ static bool rdma_dim_decision(struct dim_stats *curr_stats, struct dim *dim)
> break;
> case DIM_STATS_WORSE:
> dim_turn(dim);
> - /* fall through */
> + fallthrough;
> case DIM_STATS_BETTER:
> step_res = rdma_dim_step(dim);
> if (step_res == DIM_ON_EDGE)
> @@ -94,7 +94,7 @@ void rdma_dim(struct dim *dim, u64 completions)
> schedule_work(&dim->work);
> break;
> }
> - /* fall through */
> + fallthrough;
> case DIM_START_MEASURE:
> dim->state = DIM_MEASURE_IN_PROGRESS;
> dim_update_sample_with_comps(curr_sample->event_ctr, 0, 0,
> diff --git a/lib/glob.c b/lib/glob.c
> index 52e3ed7e4a9b..85ecbda45cd8 100644
> --- a/lib/glob.c
> +++ b/lib/glob.c
> @@ -102,7 +102,7 @@ bool __pure glob_match(char const *pat, char const *str)
> break;
> case '\\':
> d = *pat++;
> - /* fall through */
> + fallthrough;
> default: /* Literal character */
> literal:
> if (c == d) {
> diff --git a/lib/siphash.c b/lib/siphash.c
> index c47bb6ff2149..a90112ee72a1 100644
> --- a/lib/siphash.c
> +++ b/lib/siphash.c
> @@ -68,11 +68,11 @@ u64 __siphash_aligned(const void *data, size_t len, const siphash_key_t *key)
> bytemask_from_count(left)));
> #else
> switch (left) {
> - case 7: b |= ((u64)end[6]) << 48; /* fall through */
> - case 6: b |= ((u64)end[5]) << 40; /* fall through */
> - case 5: b |= ((u64)end[4]) << 32; /* fall through */
> + case 7: b |= ((u64)end[6]) << 48; fallthrough;
> + case 6: b |= ((u64)end[5]) << 40; fallthrough;
> + case 5: b |= ((u64)end[4]) << 32; fallthrough;
> case 4: b |= le32_to_cpup(data); break;
> - case 3: b |= ((u64)end[2]) << 16; /* fall through */
> + case 3: b |= ((u64)end[2]) << 16; fallthrough;
> case 2: b |= le16_to_cpup(data); break;
> case 1: b |= end[0];
> }
> @@ -101,11 +101,11 @@ u64 __siphash_unaligned(const void *data, size_t len, const siphash_key_t *key)
> bytemask_from_count(left)));
> #else
> switch (left) {
> - case 7: b |= ((u64)end[6]) << 48; /* fall through */
> - case 6: b |= ((u64)end[5]) << 40; /* fall through */
> - case 5: b |= ((u64)end[4]) << 32; /* fall through */
> + case 7: b |= ((u64)end[6]) << 48; fallthrough;
> + case 6: b |= ((u64)end[5]) << 40; fallthrough;
> + case 5: b |= ((u64)end[4]) << 32; fallthrough;
> case 4: b |= get_unaligned_le32(end); break;
> - case 3: b |= ((u64)end[2]) << 16; /* fall through */
> + case 3: b |= ((u64)end[2]) << 16; fallthrough;
> case 2: b |= get_unaligned_le16(end); break;
> case 1: b |= end[0];
> }
> @@ -268,11 +268,11 @@ u32 __hsiphash_aligned(const void *data, size_t len, const hsiphash_key_t *key)
> bytemask_from_count(left)));
> #else
> switch (left) {
> - case 7: b |= ((u64)end[6]) << 48; /* fall through */
> - case 6: b |= ((u64)end[5]) << 40; /* fall through */
> - case 5: b |= ((u64)end[4]) << 32; /* fall through */
> + case 7: b |= ((u64)end[6]) << 48; fallthrough;
> + case 6: b |= ((u64)end[5]) << 40; fallthrough;
> + case 5: b |= ((u64)end[4]) << 32; fallthrough;
> case 4: b |= le32_to_cpup(data); break;
> - case 3: b |= ((u64)end[2]) << 16; /* fall through */
> + case 3: b |= ((u64)end[2]) << 16; fallthrough;
> case 2: b |= le16_to_cpup(data); break;
> case 1: b |= end[0];
> }
> @@ -301,11 +301,11 @@ u32 __hsiphash_unaligned(const void *data, size_t len,
> bytemask_from_count(left)));
> #else
> switch (left) {
> - case 7: b |= ((u64)end[6]) << 48; /* fall through */
> - case 6: b |= ((u64)end[5]) << 40; /* fall through */
> - case 5: b |= ((u64)end[4]) << 32; /* fall through */
> + case 7: b |= ((u64)end[6]) << 48; fallthrough;
> + case 6: b |= ((u64)end[5]) << 40; fallthrough;
> + case 5: b |= ((u64)end[4]) << 32; fallthrough;
> case 4: b |= get_unaligned_le32(end); break;
> - case 3: b |= ((u64)end[2]) << 16; /* fall through */
> + case 3: b |= ((u64)end[2]) << 16; fallthrough;
> case 2: b |= get_unaligned_le16(end); break;
> case 1: b |= end[0];
> }
> @@ -431,7 +431,7 @@ u32 __hsiphash_aligned(const void *data, size_t len, const hsiphash_key_t *key)
> v0 ^= m;
> }
> switch (left) {
> - case 3: b |= ((u32)end[2]) << 16; /* fall through */
> + case 3: b |= ((u32)end[2]) << 16; fallthrough;
> case 2: b |= le16_to_cpup(data); break;
> case 1: b |= end[0];
> }
> @@ -454,7 +454,7 @@ u32 __hsiphash_unaligned(const void *data, size_t len,
> v0 ^= m;
> }
> switch (left) {
> - case 3: b |= ((u32)end[2]) << 16; /* fall through */
> + case 3: b |= ((u32)end[2]) << 16; fallthrough;
> case 2: b |= get_unaligned_le16(end); break;
> case 1: b |= end[0];
> }
> diff --git a/lib/ts_fsm.c b/lib/ts_fsm.c
> index ab749ec10ab5..64fd9015ad80 100644
> --- a/lib/ts_fsm.c
> +++ b/lib/ts_fsm.c
> @@ -193,7 +193,7 @@ static unsigned int fsm_find(struct ts_config *conf, struct ts_state *state)
> TOKEN_MISMATCH();
>
> block_idx++;
> - /* fall through */
> + fallthrough;
>
> case TS_FSM_ANY:
> if (next == NULL)
> diff --git a/lib/vsprintf.c b/lib/vsprintf.c
> index 14c9a6af1b23..d3c5c16f391c 100644
> --- a/lib/vsprintf.c
> +++ b/lib/vsprintf.c
> @@ -1265,7 +1265,7 @@ char *mac_address_string(char *buf, char *end, u8 *addr,
>
> case 'R':
> reversed = true;
> - /* fall through */
> + fallthrough;
>
> default:
> separator = ':';
> @@ -1682,7 +1682,7 @@ char *uuid_string(char *buf, char *end, const u8 *addr,
> switch (*(++fmt)) {
> case 'L':
> uc = true;
> - /* fall through */
> + fallthrough;
> case 'l':
> index = guid_index;
> break;
> @@ -2219,7 +2219,7 @@ char *pointer(const char *fmt, char *buf, char *end, void *ptr,
> case 'S':
> case 's':
> ptr = dereference_symbol_descriptor(ptr);
> - /* fall through */
> + fallthrough;
> case 'B':
> return symbol_string(buf, end, ptr, spec, fmt);
> case 'R':
> @@ -2450,7 +2450,7 @@ int format_decode(const char *fmt, struct printf_spec *spec)
>
> case 'x':
> spec->flags |= SMALL;
> - /* fall through */
> + fallthrough;
>
> case 'X':
> spec->base = 16;
> @@ -2468,7 +2468,7 @@ int format_decode(const char *fmt, struct printf_spec *spec)
> * utility, treat it as any other invalid or
> * unsupported format specifier.
> */
> - /* fall through */
> + fallthrough;
>
> default:
> WARN_ONCE(1, "Please remove unsupported %%%c in format string\n", *fmt);
> @@ -3411,10 +3411,10 @@ int vsscanf(const char *buf, const char *fmt, va_list args)
> break;
> case 'i':
> base = 0;
> - /* fall through */
> + fallthrough;
> case 'd':
> is_sign = true;
> - /* fall through */
> + fallthrough;
> case 'u':
> break;
> case '%':
> diff --git a/lib/xz/xz_dec_lzma2.c b/lib/xz/xz_dec_lzma2.c
> index 65a1aad8c223..ca2603abee08 100644
> --- a/lib/xz/xz_dec_lzma2.c
> +++ b/lib/xz/xz_dec_lzma2.c
> @@ -1043,7 +1043,7 @@ XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s,
>
> s->lzma2.sequence = SEQ_LZMA_PREPARE;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_LZMA_PREPARE:
> if (s->lzma2.compressed < RC_INIT_BYTES)
> @@ -1055,7 +1055,7 @@ XZ_EXTERN enum xz_ret xz_dec_lzma2_run(struct xz_dec_lzma2 *s,
> s->lzma2.compressed -= RC_INIT_BYTES;
> s->lzma2.sequence = SEQ_LZMA_RUN;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_LZMA_RUN:
> /*
> diff --git a/lib/xz/xz_dec_stream.c b/lib/xz/xz_dec_stream.c
> index 32ab2a08b7cb..fea86deaaa01 100644
> --- a/lib/xz/xz_dec_stream.c
> +++ b/lib/xz/xz_dec_stream.c
> @@ -583,7 +583,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
> if (ret != XZ_OK)
> return ret;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_BLOCK_START:
> /* We need one byte of input to continue. */
> @@ -608,7 +608,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
> s->temp.pos = 0;
> s->sequence = SEQ_BLOCK_HEADER;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_BLOCK_HEADER:
> if (!fill_temp(s, b))
> @@ -620,7 +620,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
>
> s->sequence = SEQ_BLOCK_UNCOMPRESS;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_BLOCK_UNCOMPRESS:
> ret = dec_block(s, b);
> @@ -629,7 +629,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
>
> s->sequence = SEQ_BLOCK_PADDING;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_BLOCK_PADDING:
> /*
> @@ -651,7 +651,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
>
> s->sequence = SEQ_BLOCK_CHECK;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_BLOCK_CHECK:
> if (s->check_type == XZ_CHECK_CRC32) {
> @@ -675,7 +675,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
>
> s->sequence = SEQ_INDEX_PADDING;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_INDEX_PADDING:
> while ((s->index.size + (b->in_pos - s->in_start))
> @@ -699,7 +699,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
>
> s->sequence = SEQ_INDEX_CRC32;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_INDEX_CRC32:
> ret = crc32_validate(s, b);
> @@ -709,7 +709,7 @@ static enum xz_ret dec_main(struct xz_dec *s, struct xz_buf *b)
> s->temp.size = STREAM_HEADER_SIZE;
> s->sequence = SEQ_STREAM_FOOTER;
>
> - /* fall through */
> + fallthrough;
>
> case SEQ_STREAM_FOOTER:
> if (!fill_temp(s, b))
> diff --git a/lib/zstd/bitstream.h b/lib/zstd/bitstream.h
> index 3a49784d5c61..7c65c66e41fd 100644
> --- a/lib/zstd/bitstream.h
> +++ b/lib/zstd/bitstream.h
> @@ -259,15 +259,15 @@ ZSTD_STATIC size_t BIT_initDStream(BIT_DStream_t *bitD, const void *srcBuffer, s
> bitD->bitContainer = *(const BYTE *)(bitD->start);
> switch (srcSize) {
> case 7: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[6]) << (sizeof(bitD->bitContainer) * 8 - 16);
> - /* fall through */
> + fallthrough;
> case 6: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[5]) << (sizeof(bitD->bitContainer) * 8 - 24);
> - /* fall through */
> + fallthrough;
> case 5: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[4]) << (sizeof(bitD->bitContainer) * 8 - 32);
> - /* fall through */
> + fallthrough;
> case 4: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[3]) << 24;
> - /* fall through */
> + fallthrough;
> case 3: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[2]) << 16;
> - /* fall through */
> + fallthrough;
> case 2: bitD->bitContainer += (size_t)(((const BYTE *)(srcBuffer))[1]) << 8;
> default:;
> }
> diff --git a/lib/zstd/compress.c b/lib/zstd/compress.c
> index 5e0b67003e55..b080264ed3ad 100644
> --- a/lib/zstd/compress.c
> +++ b/lib/zstd/compress.c
> @@ -3182,7 +3182,7 @@ static size_t ZSTD_compressStream_generic(ZSTD_CStream *zcs, void *dst, size_t *
> zcs->outBuffFlushedSize = 0;
> zcs->stage = zcss_flush; /* pass-through to flush stage */
> }
> - /* fall through */
> + fallthrough;
>
> case zcss_flush: {
> size_t const toFlush = zcs->outBuffContentSize - zcs->outBuffFlushedSize;
> diff --git a/lib/zstd/decompress.c b/lib/zstd/decompress.c
> index db6761ea4deb..66cd487a326a 100644
> --- a/lib/zstd/decompress.c
> +++ b/lib/zstd/decompress.c
> @@ -442,7 +442,7 @@ size_t ZSTD_decodeLiteralsBlock(ZSTD_DCtx *dctx, const void *src, size_t srcSize
> case set_repeat:
> if (dctx->litEntropy == 0)
> return ERROR(dictionary_corrupted);
> - /* fall through */
> + fallthrough;
> case set_compressed:
> if (srcSize < 5)
> return ERROR(corruption_detected); /* srcSize >= MIN_CBLOCK_SIZE == 3; here we need up to 5 for case 3 */
> @@ -1768,7 +1768,7 @@ size_t ZSTD_decompressContinue(ZSTD_DCtx *dctx, void *dst, size_t dstCapacity, c
> return 0;
> }
> dctx->expected = 0; /* not necessary to copy more */
> - /* fall through */
> + fallthrough;
>
> case ZSTDds_decodeFrameHeader:
> memcpy(dctx->headerBuffer + ZSTD_frameHeaderSize_prefix, src, dctx->expected);
> @@ -2309,7 +2309,7 @@ size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inB
> switch (zds->stage) {
> case zdss_init:
> ZSTD_resetDStream(zds); /* transparent reset on starting decoding a new frame */
> - /* fall through */
> + fallthrough;
>
> case zdss_loadHeader: {
> size_t const hSize = ZSTD_getFrameParams(&zds->fParams, zds->headerBuffer, zds->lhSize);
> @@ -2376,7 +2376,7 @@ size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inB
> }
> zds->stage = zdss_read;
> }
> - /* fall through */
> + fallthrough;
>
> case zdss_read: {
> size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx);
> @@ -2405,7 +2405,7 @@ size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inB
> zds->stage = zdss_load;
> /* pass-through */
> }
> - /* fall through */
> + fallthrough;
>
> case zdss_load: {
> size_t const neededInSize = ZSTD_nextSrcSizeToDecompress(zds->dctx);
> @@ -2438,7 +2438,7 @@ size_t ZSTD_decompressStream(ZSTD_DStream *zds, ZSTD_outBuffer *output, ZSTD_inB
> /* pass-through */
> }
> }
> - /* fall through */
> + fallthrough;
>
> case zdss_flush: {
> size_t const toFlushSize = zds->outEnd - zds->outStart;
> diff --git a/lib/zstd/huf_compress.c b/lib/zstd/huf_compress.c
> index e727812d12aa..08b4ae80aed4 100644
> --- a/lib/zstd/huf_compress.c
> +++ b/lib/zstd/huf_compress.c
> @@ -556,9 +556,9 @@ size_t HUF_compress1X_usingCTable(void *dst, size_t dstSize, const void *src, si
> n = srcSize & ~3; /* join to mod 4 */
> switch (srcSize & 3) {
> case 3: HUF_encodeSymbol(&bitC, ip[n + 2], CTable); HUF_FLUSHBITS_2(&bitC);
> - /* fall through */
> + fallthrough;
> case 2: HUF_encodeSymbol(&bitC, ip[n + 1], CTable); HUF_FLUSHBITS_1(&bitC);
> - /* fall through */
> + fallthrough;
> case 1: HUF_encodeSymbol(&bitC, ip[n + 0], CTable); HUF_FLUSHBITS(&bitC);
> case 0:
> default:;
> --
> 2.29.2.299.gdc1121823c-goog
>
^ permalink raw reply
* Re: [PATCH 3/3] powerpc: fix -Wimplicit-fallthrough
From: Nathan Chancellor @ 2020-11-17 3:02 UTC (permalink / raw)
To: Nick Desaulniers
Cc: clang-built-linux, Gustavo A . R . Silva, linux-kernel,
Miguel Ojeda, Paul Mackerras, linuxppc-dev
In-Reply-To: <20201116043532.4032932-4-ndesaulniers@google.com>
On Sun, Nov 15, 2020 at 08:35:32PM -0800, Nick Desaulniers wrote:
> The "fallthrough" pseudo-keyword was added as a portable way to denote
> intentional fallthrough. Clang will still warn on cases where there is a
> fallthrough to an immediate break. Add explicit breaks for those cases.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/236
> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
> ---
> arch/powerpc/kernel/prom_init.c | 1 +
> arch/powerpc/kernel/uprobes.c | 1 +
> arch/powerpc/perf/imc-pmu.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
> index 38ae5933d917..e9d4eb6144e1 100644
> --- a/arch/powerpc/kernel/prom_init.c
> +++ b/arch/powerpc/kernel/prom_init.c
> @@ -355,6 +355,7 @@ static int __init prom_strtobool(const char *s, bool *res)
> default:
> break;
> }
> + break;
> default:
> break;
> }
> diff --git a/arch/powerpc/kernel/uprobes.c b/arch/powerpc/kernel/uprobes.c
> index d200e7df7167..e8a63713e655 100644
> --- a/arch/powerpc/kernel/uprobes.c
> +++ b/arch/powerpc/kernel/uprobes.c
> @@ -141,6 +141,7 @@ int arch_uprobe_exception_notify(struct notifier_block *self,
> case DIE_SSTEP:
> if (uprobe_post_sstep_notifier(regs))
> return NOTIFY_STOP;
> + break;
> default:
> break;
> }
> diff --git a/arch/powerpc/perf/imc-pmu.c b/arch/powerpc/perf/imc-pmu.c
> index 7b25548ec42b..e106909ff9c3 100644
> --- a/arch/powerpc/perf/imc-pmu.c
> +++ b/arch/powerpc/perf/imc-pmu.c
> @@ -1500,6 +1500,7 @@ static int update_pmu_ops(struct imc_pmu *pmu)
> pmu->pmu.stop = trace_imc_event_stop;
> pmu->pmu.read = trace_imc_event_read;
> pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
> + break;
> default:
> break;
> }
> --
> 2.29.2.299.gdc1121823c-goog
>
^ permalink raw reply
* Re: [PATCH] powerpc/powernv/sriov: fix unsigned int win compared to less than zero
From: Michael Ellerman @ 2020-11-17 3:07 UTC (permalink / raw)
To: Andrew Donnellan, xiakaixu1987, fbarrat, benh, paulus
Cc: Kaixu Xia, linuxppc-dev, linux-kernel
In-Reply-To: <40b8ba6f-4916-55c2-a1f0-b7daa3c2e201@linux.ibm.com>
Andrew Donnellan <ajd@linux.ibm.com> writes:
> On 10/11/20 10:19 pm, xiakaixu1987@gmail.com wrote:
>> From: Kaixu Xia <kaixuxia@tencent.com>
>>
>> Fix coccicheck warning:
>>
>> ./arch/powerpc/platforms/powernv/pci-sriov.c:443:7-10: WARNING: Unsigned expression compared with zero: win < 0
>> ./arch/powerpc/platforms/powernv/pci-sriov.c:462:7-10: WARNING: Unsigned expression compared with zero: win < 0
>>
>> Reported-by: Tosk Robot <tencent_os_robot@tencent.com>
>> Signed-off-by: Kaixu Xia <kaixuxia@tencent.com>
>
> This seems like the right fix, the value assigned to win can indeed be
> -1 so it should be signed. Thanks for sending the patch.
>
> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
I'll add:
Fixes: 39efc03e3ee8 ("powerpc/powernv/sriov: Move M64 BAR allocation into a helper")
Which I think is the culprit as it changed:
if (win >= phb->ioda.m64_bar_idx + 1)
to:
if (win < 0)
cheers
^ permalink raw reply
* Re: [PATCH 1/6] ibmvfc: byte swap login_buf.resp values in attribute show functions
From: Martin K. Petersen @ 2020-11-17 3:22 UTC (permalink / raw)
To: Tyrel Datwyler
Cc: james.bottomley, martin.petersen, linux-scsi, linux-kernel,
Christoph Hellwig, brking, linuxppc-dev
In-Reply-To: <7df9d768-e008-a849-5fbd-78d6bd0536fa@linux.ibm.com>
Tyrel,
> The checkpatch script only warns at 100 char lines these days. To be
> fair though I did have two lines go over that limit by a couple
> characters, there are a couple commit log typos, and I had an if
> keyword with no space after before the opening parenthesis. So, I'll
> happily re-spin.
Please tweak the little things that need fixing and resubmit.
> However, for my info going forward is the SCSI subsystem sticking to
> 80 char lines as a hard limit?
As far as I'm concerned the 80 char limit is mainly about ensuring that
the code is structured in a sensible way. Typesetting best practices
also suggest that longer lines are harder to read. So while I generally
don't strictly enforce the 80 char limit for drivers, I do push back if
I feel that readability could be improved by breaking the line or
restructuring the code.
Use your best judgment to optimize for readability.
Thanks!
--
Martin K. Petersen Oracle Linux Engineering
^ permalink raw reply
* [PATCH] powerpc: fix create_section_mapping compile warning
From: Dan Williams @ 2020-11-17 3:31 UTC (permalink / raw)
To: akpm; +Cc: kernel test robot, linux-mm, Paul Mackerras, linuxppc-dev
0day robot reports that a recent rework of how
memory_add_physaddr_to_nid() and phys_to_target_node() are declared
resulted in the following new compilation warning:
arch/powerpc/mm/mem.c:91:12: warning: no previous prototype for 'create_section_mapping' [-Wmissing-prototypes]
91 | int __weak create_section_mapping(unsigned long start, unsigned long end,
| ^~~~~~~~~~~~~~~~~~~~~~
...fix this by moving the declaration of create_section_mapping()
outside of the CONFIG_NEED_MULTIPLE_NODES ifdef guard, and include an
explicit include of asm/mmzone.h in mem.c. An include of linux/mmzone.h
is not sufficient.
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
arch/powerpc/include/asm/mmzone.h | 7 +++++--
arch/powerpc/mm/mem.c | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/mmzone.h b/arch/powerpc/include/asm/mmzone.h
index 177fd18caf83..6cda76b57c5d 100644
--- a/arch/powerpc/include/asm/mmzone.h
+++ b/arch/powerpc/include/asm/mmzone.h
@@ -33,8 +33,6 @@ extern struct pglist_data *node_data[];
extern int numa_cpu_lookup_table[];
extern cpumask_var_t node_to_cpumask_map[];
#ifdef CONFIG_MEMORY_HOTPLUG
-extern int create_section_mapping(unsigned long start, unsigned long end,
- int nid, pgprot_t prot);
extern unsigned long max_pfn;
u64 memory_hotplug_max(void);
#else
@@ -48,5 +46,10 @@ u64 memory_hotplug_max(void);
#define __HAVE_ARCH_RESERVED_KERNEL_PAGES
#endif
+#ifdef CONFIG_MEMORY_HOTPLUG
+extern int create_section_mapping(unsigned long start, unsigned long end,
+ int nid, pgprot_t prot);
+#endif
+
#endif /* __KERNEL__ */
#endif /* _ASM_MMZONE_H_ */
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 01ec2a252f09..3fc325bebe4d 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -50,6 +50,7 @@
#include <asm/rtas.h>
#include <asm/kasan.h>
#include <asm/svm.h>
+#include <asm/mmzone.h>
#include <mm/mmu_decl.h>
^ permalink raw reply related
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