* [PATCH] ASoC: fsl_sai: Correct the clock source for mclk0
From: Shengjiu Wang @ 2020-11-19 2:29 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, perex, tiwai,
alsa-devel
Cc: linuxppc-dev, linux-kernel
On VF610, mclk0 = bus_clk;
On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
On i.MX7ULP, mclk0 = bus_clk;
On i.MX8QM/8QXP, mclk0 = bus_clk;
On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
So add variable mclk0_mclk1_match in fsl_sai_soc_data to
distinguish these platforms.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 11 ++++++++++-
sound/soc/fsl/fsl_sai.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 3e5c1eaccd5e..479fd27ace35 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1040,7 +1040,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
sai->bus_clk = NULL;
}
- sai->mclk_clk[0] = sai->bus_clk;
for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
sprintf(tmp, "mclk%d", i);
sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
@@ -1051,6 +1050,11 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ if (sai->soc_data->mclk0_mclk1_match)
+ sai->mclk_clk[0] = sai->mclk_clk[1];
+ else
+ sai->mclk_clk[0] = sai->bus_clk;
+
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
@@ -1165,6 +1169,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.use_edma = false,
.fifo_depth = 32,
.reg_offset = 0,
+ .mclk0_mclk1_match = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
@@ -1172,6 +1177,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.use_edma = false,
.fifo_depth = 32,
.reg_offset = 0,
+ .mclk0_mclk1_match = true,
};
static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
@@ -1179,6 +1185,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
.use_edma = false,
.fifo_depth = 16,
.reg_offset = 8,
+ .mclk0_mclk1_match = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
@@ -1186,6 +1193,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
.use_edma = false,
.fifo_depth = 128,
.reg_offset = 8,
+ .mclk0_mclk1_match = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
@@ -1193,6 +1201,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
.use_edma = true,
.fifo_depth = 64,
.reg_offset = 0,
+ .mclk0_mclk1_match = false,
};
static const struct of_device_id fsl_sai_ids[] = {
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 4bbcd0dbe8f1..390a9ca3b531 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -219,6 +219,7 @@
struct fsl_sai_soc_data {
bool use_imx_pcm;
bool use_edma;
+ bool mclk0_mclk1_match;
unsigned int fifo_depth;
unsigned int reg_offset;
};
--
2.27.0
^ permalink raw reply related
* Re: [PATCH] ASoC: fsl_sai: Correct the clock source for mclk0
From: Nicolin Chen @ 2020-11-19 5:01 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, linuxppc-dev, tiwai, perex, broonie,
festevam, linux-kernel
In-Reply-To: <1605752956-17397-1-git-send-email-shengjiu.wang@nxp.com>
On Thu, Nov 19, 2020 at 10:29:16AM +0800, Shengjiu Wang wrote:
> On VF610, mclk0 = bus_clk;
> On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
> On i.MX7ULP, mclk0 = bus_clk;
> On i.MX8QM/8QXP, mclk0 = bus_clk;
> On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
>
> So add variable mclk0_mclk1_match in fsl_sai_soc_data To
Not in favor of "mclk0_mclk1_match" as it doesn't sound explicit
to me. Instead, "mclk0_is_bus_clk" or "mclk0_is_mclk1" might be
better. Or in case that you foresee some other implementation:
enum {
MCLK0_IS_BUS_CLK,
MCLK0_IS_MCLK1,
};
static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
+ .mclk0_alias = MCLK0_IS_BUS_CLK,
};
^ permalink raw reply
* Re: [PATCH] ASoC: fsl_sai: Correct the clock source for mclk0
From: Shengjiu Wang @ 2020-11-19 5:28 UTC (permalink / raw)
To: Nicolin Chen
Cc: alsa-devel, Timur Tabi, Xiubo Li, Fabio Estevam, Shengjiu Wang,
Takashi Iwai, linux-kernel, Mark Brown, linuxppc-dev
In-Reply-To: <20201119050120.GA7124@Asurada-Nvidia>
On Thu, Nov 19, 2020 at 1:02 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Thu, Nov 19, 2020 at 10:29:16AM +0800, Shengjiu Wang wrote:
> > On VF610, mclk0 = bus_clk;
> > On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
> > On i.MX7ULP, mclk0 = bus_clk;
> > On i.MX8QM/8QXP, mclk0 = bus_clk;
> > On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
> >
> > So add variable mclk0_mclk1_match in fsl_sai_soc_data To
>
> Not in favor of "mclk0_mclk1_match" as it doesn't sound explicit
> to me. Instead, "mclk0_is_bus_clk" or "mclk0_is_mclk1" might be
> better. Or in case that you foresee some other implementation:
>
> enum {
> MCLK0_IS_BUS_CLK,
> MCLK0_IS_MCLK1,
> };
>
> static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
> + .mclk0_alias = MCLK0_IS_BUS_CLK,
> };
No problem.
But I just find this patch doesn't consider the mqs case.
MCLK0 can't be used for mqs, it needs MCLK1, even
the MCLK0 is same as MCLK1, MCLK1 need to be
selected for mqs case.
Is there a decent way for this case?
best regards
wang shengjiu
^ permalink raw reply
* [PATCH 2/2] powerpc: sstep: Fix store and update instructions
From: Sandipan Das @ 2020-11-19 5:41 UTC (permalink / raw)
To: mpe; +Cc: ravi.bangoria, jniethe5, paulus, naveen.n.rao, linuxppc-dev, dja
In-Reply-To: <20201119054139.244083-1-sandipan@linux.ibm.com>
The Power ISA says that the fixed-point store and update
instructions must not use R0 for the base address (RA).
In this case, the instruction is invalid. This applies
to the following instructions.
* Store Byte with Update (stbu)
* Store Byte with Update Indexed (stbux)
* Store Halfword with Update (sthu)
* Store Halfword with Update Indexed (sthux)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Doubleword with Update (stdu)
* Store Doubleword with Update Indexed (stdux)
To remove any inconsistencies, this adds an additional check
for the aforementioned instructions to make sure that they
are treated as unknown by the emulation infrastructure when
RA = 0. The kernel will then fallback to executing the
instruction on hardware.
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---
arch/powerpc/lib/sstep.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 25a5436be6c6..1c20c14f8757 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2226,17 +2226,23 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 149: /* stdx */
case 181: /* stdux */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 8);
break;
#endif
case 151: /* stwx */
case 183: /* stwux */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 4);
break;
case 215: /* stbx */
case 247: /* stbux */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 1);
break;
@@ -2265,6 +2271,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 407: /* sthx */
case 439: /* sthux */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 2);
break;
@@ -2568,12 +2576,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 36: /* stw */
case 37: /* stwu */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 4);
op->ea = dform_ea(word, regs);
break;
case 38: /* stb */
case 39: /* stbu */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 1);
op->ea = dform_ea(word, regs);
break;
@@ -2596,6 +2608,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 44: /* sth */
case 45: /* sthu */
+ if (u && ra == 0)
+ return -1;
op->type = MKOP(STORE, u, 2);
op->ea = dform_ea(word, regs);
break;
@@ -2746,6 +2760,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
op->type = MKOP(STORE, 0, 8);
break;
case 1: /* stdu */
+ if (ra == 0)
+ return -1;
op->type = MKOP(STORE, UPDATE, 8);
break;
case 2: /* stq */
--
2.25.1
^ permalink raw reply related
* [PATCH 1/2] powerpc: sstep: Fix load and update instructions
From: Sandipan Das @ 2020-11-19 5:41 UTC (permalink / raw)
To: mpe; +Cc: ravi.bangoria, jniethe5, paulus, naveen.n.rao, linuxppc-dev, dja
The Power ISA says that the fixed-point load and update
instructions must neither use R0 for the base address (RA)
nor have the destination (RT) and the base address (RA) as
the same register. In these cases, the instruction is
invalid. This applies to the following instructions.
* Load Byte and Zero with Update (lbzu)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Halfword and Zero with Update (lhzu)
* Load Halfword and Zero with Update Indexed (lhzux)
* Load Halfword Algebraic with Update (lhau)
* Load Halfword Algebraic with Update Indexed (lhaux)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic with Update Indexed (lwaux)
* Load Doubleword with Update (ldu)
* Load Doubleword with Update Indexed (ldux)
However, the following behaviour is observed using some
invalid opcodes where RA = RT.
An userspace program using an invalid instruction word like
0xe9ce0001, i.e. "ldu r14, 0(r14)", runs and exits without
getting terminated abruptly. The instruction performs the
load operation but does not write the effective address to
the base address register. Attaching an uprobe at that
instruction's address results in emulation which writes the
effective address to the base register. Thus, the final value
of the base address register is different.
To remove any inconsistencies, this adds an additional check
for the aforementioned instructions to make sure that they
are treated as unknown by the emulation infrastructure when
RA = 0 or RA = RT. The kernel will then fallback to executing
the instruction on hardware.
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---
arch/powerpc/lib/sstep.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 855457ed09b5..25a5436be6c6 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -2157,11 +2157,15 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 23: /* lwzx */
case 55: /* lwzux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 4);
break;
case 87: /* lbzx */
case 119: /* lbzux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 1);
break;
@@ -2215,6 +2219,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
#ifdef __powerpc64__
case 21: /* ldx */
case 53: /* ldux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 8);
break;
@@ -2236,18 +2242,24 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 279: /* lhzx */
case 311: /* lhzux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 2);
break;
#ifdef __powerpc64__
case 341: /* lwax */
case 373: /* lwaux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, SIGNEXT | u, 4);
break;
#endif
case 343: /* lhax */
case 375: /* lhaux */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, SIGNEXT | u, 2);
break;
@@ -2540,12 +2552,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 32: /* lwz */
case 33: /* lwzu */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 4);
op->ea = dform_ea(word, regs);
break;
case 34: /* lbz */
case 35: /* lbzu */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 1);
op->ea = dform_ea(word, regs);
break;
@@ -2564,12 +2580,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
case 40: /* lhz */
case 41: /* lhzu */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, u, 2);
op->ea = dform_ea(word, regs);
break;
case 42: /* lha */
case 43: /* lhau */
+ if (u && (ra == 0 || ra == rd))
+ return -1;
op->type = MKOP(LOAD, SIGNEXT | u, 2);
op->ea = dform_ea(word, regs);
break;
@@ -2659,6 +2679,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
op->type = MKOP(LOAD, 0, 8);
break;
case 1: /* ldu */
+ if (ra == 0 || ra == rd)
+ return -1;
op->type = MKOP(LOAD, UPDATE, 8);
break;
case 2: /* lwa */
--
2.25.1
^ permalink raw reply related
* Re: [PATCH] ASoC: fsl_sai: Correct the clock source for mclk0
From: Nicolin Chen @ 2020-11-19 5:53 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Timur Tabi, Xiubo Li, Fabio Estevam, Shengjiu Wang,
Takashi Iwai, linux-kernel, Mark Brown, linuxppc-dev
In-Reply-To: <CAA+D8AOuaeZCnvY0h2stzkiMnNCe7zvK_D4M2irT7y7NC+iZFg@mail.gmail.com>
On Thu, Nov 19, 2020 at 01:28:32PM +0800, Shengjiu Wang wrote:
> On Thu, Nov 19, 2020 at 1:02 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> >
> > On Thu, Nov 19, 2020 at 10:29:16AM +0800, Shengjiu Wang wrote:
> > > On VF610, mclk0 = bus_clk;
> > > On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
> > > On i.MX7ULP, mclk0 = bus_clk;
> > > On i.MX8QM/8QXP, mclk0 = bus_clk;
> > > On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
> > >
> > > So add variable mclk0_mclk1_match in fsl_sai_soc_data To
> >
> > Not in favor of "mclk0_mclk1_match" as it doesn't sound explicit
> > to me. Instead, "mclk0_is_bus_clk" or "mclk0_is_mclk1" might be
> > better. Or in case that you foresee some other implementation:
> >
> > enum {
> > MCLK0_IS_BUS_CLK,
> > MCLK0_IS_MCLK1,
> > };
> >
> > static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
> > + .mclk0_alias = MCLK0_IS_BUS_CLK,
> > };
>
> No problem.
>
> But I just find this patch doesn't consider the mqs case.
> MCLK0 can't be used for mqs, it needs MCLK1, even
> the MCLK0 is same as MCLK1, MCLK1 need to be
> selected for mqs case.
>
> Is there a decent way for this case?
Is there any use case that we have to use MCLK0 instead of MCLK1
on SoCs where MCLK0=MCLK1? If no, how about skip MCLK0 at all in
the for-loop at fsl_sai_set_bclk?
/*
* There is no point in polling MCLK0 if it is identical to MCLK1.
* And given that MQS use case has to use MCLK1 though two clocks
* are the same, we simply skip MCLK0 and start to find from MCLK1.
*/
id = mclk0_is_mclk1 ? 1 : 0;
for (; id < FSL_SAI_MCLK_MAX; id++) {
^ permalink raw reply
* Re: [PATCH] ASoC: fsl_sai: Correct the clock source for mclk0
From: Shengjiu Wang @ 2020-11-19 6:04 UTC (permalink / raw)
To: Nicolin Chen
Cc: alsa-devel, Timur Tabi, Xiubo Li, Fabio Estevam, Shengjiu Wang,
Takashi Iwai, linux-kernel, Mark Brown, linuxppc-dev
In-Reply-To: <20201119055340.GA1666@Asurada-Nvidia>
On Thu, Nov 19, 2020 at 1:54 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
>
> On Thu, Nov 19, 2020 at 01:28:32PM +0800, Shengjiu Wang wrote:
> > On Thu, Nov 19, 2020 at 1:02 PM Nicolin Chen <nicoleotsuka@gmail.com> wrote:
> > >
> > > On Thu, Nov 19, 2020 at 10:29:16AM +0800, Shengjiu Wang wrote:
> > > > On VF610, mclk0 = bus_clk;
> > > > On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
> > > > On i.MX7ULP, mclk0 = bus_clk;
> > > > On i.MX8QM/8QXP, mclk0 = bus_clk;
> > > > On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
> > > >
> > > > So add variable mclk0_mclk1_match in fsl_sai_soc_data To
> > >
> > > Not in favor of "mclk0_mclk1_match" as it doesn't sound explicit
> > > to me. Instead, "mclk0_is_bus_clk" or "mclk0_is_mclk1" might be
> > > better. Or in case that you foresee some other implementation:
> > >
> > > enum {
> > > MCLK0_IS_BUS_CLK,
> > > MCLK0_IS_MCLK1,
> > > };
> > >
> > > static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
> > > + .mclk0_alias = MCLK0_IS_BUS_CLK,
> > > };
> >
> > No problem.
> >
> > But I just find this patch doesn't consider the mqs case.
> > MCLK0 can't be used for mqs, it needs MCLK1, even
> > the MCLK0 is same as MCLK1, MCLK1 need to be
> > selected for mqs case.
> >
> > Is there a decent way for this case?
>
> Is there any use case that we have to use MCLK0 instead of MCLK1
> on SoCs where MCLK0=MCLK1? If no, how about skip MCLK0 at all in
> the for-loop at fsl_sai_set_bclk?
>
> /*
> * There is no point in polling MCLK0 if it is identical to MCLK1.
> * And given that MQS use case has to use MCLK1 though two clocks
> * are the same, we simply skip MCLK0 and start to find from MCLK1.
> */
> id = mclk0_is_mclk1 ? 1 : 0;
>
> for (; id < FSL_SAI_MCLK_MAX; id++) {
Ok, thanks, will update the patch.
best regards
wang shengjiu
^ permalink raw reply
* [PATCH v2] ASoC: fsl_sai: Correct the clock source for mclk0
From: Shengjiu Wang @ 2020-11-19 6:40 UTC (permalink / raw)
To: timur, nicoleotsuka, Xiubo.Lee, festevam, broonie, perex, tiwai,
alsa-devel
Cc: linuxppc-dev, linux-kernel
On VF610, mclk0 = bus_clk;
On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
On i.MX7ULP, mclk0 = bus_clk;
On i.MX8QM/8QXP, mclk0 = bus_clk;
On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
So add variable mclk0_is_mclk1 in fsl_sai_soc_data to
distinguish these platforms.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
---
changes in v2:
- rename mclk0_mclk1_match to mclk0_is_mclk1
- skip MCLK0 when it is same as MCLK1 on master clock scanning
sound/soc/fsl/fsl_sai.c | 20 ++++++++++++++++++--
sound/soc/fsl/fsl_sai.h | 1 +
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 3e5c1eaccd5e..f3d3d20d35d7 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -359,7 +359,14 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
if (sai->is_slave_mode)
return 0;
- for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
+ /*
+ * There is no point in polling MCLK0 if it is identical to MCLK1.
+ * And given that MQS use case has to use MCLK1 though two clocks
+ * are the same, we simply skip MCLK0 and start to find from MCLK1.
+ */
+ id = sai->soc_data->mclk0_is_mclk1 ? 1 : 0;
+
+ for (; id < FSL_SAI_MCLK_MAX; id++) {
clk_rate = clk_get_rate(sai->mclk_clk[id]);
if (!clk_rate)
continue;
@@ -1040,7 +1047,6 @@ static int fsl_sai_probe(struct platform_device *pdev)
sai->bus_clk = NULL;
}
- sai->mclk_clk[0] = sai->bus_clk;
for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
sprintf(tmp, "mclk%d", i);
sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
@@ -1051,6 +1057,11 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ if (sai->soc_data->mclk0_is_mclk1)
+ sai->mclk_clk[0] = sai->mclk_clk[1];
+ else
+ sai->mclk_clk[0] = sai->bus_clk;
+
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
@@ -1165,6 +1176,7 @@ static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.use_edma = false,
.fifo_depth = 32,
.reg_offset = 0,
+ .mclk0_is_mclk1 = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
@@ -1172,6 +1184,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.use_edma = false,
.fifo_depth = 32,
.reg_offset = 0,
+ .mclk0_is_mclk1 = true,
};
static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
@@ -1179,6 +1192,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
.use_edma = false,
.fifo_depth = 16,
.reg_offset = 8,
+ .mclk0_is_mclk1 = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
@@ -1186,6 +1200,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
.use_edma = false,
.fifo_depth = 128,
.reg_offset = 8,
+ .mclk0_is_mclk1 = false,
};
static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
@@ -1193,6 +1208,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
.use_edma = true,
.fifo_depth = 64,
.reg_offset = 0,
+ .mclk0_is_mclk1 = false,
};
static const struct of_device_id fsl_sai_ids[] = {
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 4bbcd0dbe8f1..ff2619f1b214 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -219,6 +219,7 @@
struct fsl_sai_soc_data {
bool use_imx_pcm;
bool use_edma;
+ bool mclk0_is_mclk1;
unsigned int fifo_depth;
unsigned int reg_offset;
};
--
2.27.0
^ permalink raw reply related
* Re: [PATCH v2] ASoC: fsl_sai: Correct the clock source for mclk0
From: Nicolin Chen @ 2020-11-19 6:51 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, timur, Xiubo.Lee, linuxppc-dev, tiwai, perex, broonie,
festevam, linux-kernel
In-Reply-To: <1605768038-4582-1-git-send-email-shengjiu.wang@nxp.com>
On Thu, Nov 19, 2020 at 02:40:38PM +0800, Shengjiu Wang wrote:
> On VF610, mclk0 = bus_clk;
> On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1;
> On i.MX7ULP, mclk0 = bus_clk;
> On i.MX8QM/8QXP, mclk0 = bus_clk;
> On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk;
>
> So add variable mclk0_is_mclk1 in fsl_sai_soc_data to
> distinguish these platforms.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
^ permalink raw reply
* [PATCH] media: fsl-viu: Use proper check for presence of {out, in}_be32()
From: Geert Uytterhoeven @ 2020-11-19 8:01 UTC (permalink / raw)
To: Michael Ellerman, Benjamin Herrenschmidt, Paul Mackerras,
Mauro Carvalho Chehab, Fabio Estevam
Cc: kernel test robot, Arnd Bergmann, linux-kernel,
Geert Uytterhoeven, Hans Verkuil, linuxppc-dev, linux-media
When compile-testing on m68k/randconfig:
drivers/media/platform/fsl-viu.c: In function 'viu_start_dma':
drivers/media/platform/fsl-viu.c:253:2: error: implicit declaration of function 'out_be32' [-Werror=implicit-function-declaration]
drivers/media/platform/fsl-viu.c: In function 'viu_stop_dma':
drivers/media/platform/fsl-viu.c:266:15: error: implicit declaration of function 'in_be32' [-Werror=implicit-function-declaration]
Fix this by replacing the checks for PowerPC, Microblaze, and m68k by
checks for the presence of {out,in}_be32().
As PowerPC implements the be32 accessors using inline functions instead
of macros, identity definitions are added for all accessors to make the
above checks work.
Fixes: 29d750686331a1a9 ("media: fsl-viu: allow building it with COMPILE_TEST")
Fixes: 17621758e53f0e6b ("media: fsl-viu: Do not redefine out_be32()/in_be32() for CONFIG_M68K")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Hans Verkuil <hans.verkuil@cisco.com>
---
Compile-tested on m68k, microblaze, and powerpc.
Assembler output before/after compared for powerpc.
v2:
- Add Reviewed-by,
- s/definions/definitions/,
- Update for commits 6898dd580a045341 ("media: media/platform:
fsl-viu.c: fix build for MICROBLAZE") and 17621758e53f0e6b ("media:
fsl-viu: Do not redefine out_be32()/in_be32() for CONFIG_M68K"),
which added checks for Microblaze and m68k (the latter is not
sufficient, cfr. the report from the kernel test robot).
v1: https://lore.kernel.org/lkml/1528451328-21316-1-git-send-email-geert@linux-m68k.org/
---
arch/powerpc/include/asm/io.h | 14 ++++++++++++++
drivers/media/platform/fsl-viu.c | 4 +++-
2 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 58635960403c058b..fcb250db110d8e2b 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -194,6 +194,20 @@ static inline void out_be64(volatile u64 __iomem *addr, u64 val)
#endif
#endif /* __powerpc64__ */
+#define in_be16 in_be16
+#define in_be32 in_be32
+#define in_be64 in_be64
+#define in_le16 in_le16
+#define in_le32 in_le32
+#define in_le64 in_le64
+
+#define out_be16 out_be16
+#define out_be32 out_be32
+#define out_be64 out_be64
+#define out_le16 out_le16
+#define out_le32 out_le32
+#define out_le64 out_le64
+
/*
* Low level IO stream instructions are defined out of line for now
*/
diff --git a/drivers/media/platform/fsl-viu.c b/drivers/media/platform/fsl-viu.c
index 4f2a0f992905b4b3..d8a6dd4ffbad56d6 100644
--- a/drivers/media/platform/fsl-viu.c
+++ b/drivers/media/platform/fsl-viu.c
@@ -32,8 +32,10 @@
#define VIU_VERSION "0.5.1"
/* Allow building this driver with COMPILE_TEST */
-#if !defined(CONFIG_PPC) && !defined(CONFIG_MICROBLAZE) && !defined(CONFIG_M68K)
+#ifndef out_be32
#define out_be32(v, a) iowrite32be(a, (void __iomem *)v)
+#endif
+#ifndef in_be32
#define in_be32(a) ioread32be((void __iomem *)a)
#endif
--
2.25.1
^ permalink raw reply related
* [PATCH for 4.4] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set
From: Christophe Leroy @ 2020-11-19 8:47 UTC (permalink / raw)
To: gregkh, stable; +Cc: linuxppc-dev, linux-kernel
[This is backport for 4.4 of 29daf869cbab69088fe1755d9dd224e99ba78b56]
The kernel expects pte_young() to work regardless of CONFIG_SWAP.
Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.
This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.
Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.
Fixes: d069cb4373fe ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497c384 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d90a9f ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc3e8a ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
---
arch/powerpc/kernel/head_8xx.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 01e274e6907b..3d7512e72900 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -361,11 +361,9 @@ InstructionTLBMiss:
/* Load the MI_TWC with the attributes for this "segment." */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
li r11, RPN_PATTERN
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20-23 and 28 must be clear.
@@ -436,11 +434,9 @@ DataStoreTLBMiss:
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
--
2.25.0
^ permalink raw reply related
* [PATCH for 4.19] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set
From: Christophe Leroy @ 2020-11-19 8:47 UTC (permalink / raw)
To: gregkh, stable; +Cc: linuxppc-dev, linux-kernel
[This is backport for 4.19 of 29daf869cbab69088fe1755d9dd224e99ba78b56]
The kernel expects pte_young() to work regardless of CONFIG_SWAP.
Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.
This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.
Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.
Fixes: d069cb4373fe ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497c384 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d90a9f ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc3e8a ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
---
arch/powerpc/kernel/head_8xx.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9fd2ff28b8ff..dc99258f2e8c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -356,11 +356,9 @@ _ENTRY(ITLBMiss_cmp)
/* Load the MI_TWC with the attributes for this "segment." */
mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-7, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
li r11, RPN_PATTERN | 0x200
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20 and 23 must be clear.
@@ -482,11 +480,9 @@ _ENTRY(DTLBMiss_jmp)
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-7, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
--
2.25.0
^ permalink raw reply related
* [PATCH for 4.14] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set
From: Christophe Leroy @ 2020-11-19 8:47 UTC (permalink / raw)
To: gregkh, stable; +Cc: linuxppc-dev, linux-kernel
[This is backport for 4.14 of 29daf869cbab69088fe1755d9dd224e99ba78b56]
The kernel expects pte_young() to work regardless of CONFIG_SWAP.
Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.
This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.
Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.
Fixes: d069cb4373fe ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497c384 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d90a9f ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc3e8a ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
---
arch/powerpc/kernel/head_8xx.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 2d0d89e2cb9a..43884af0e35c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -398,11 +398,9 @@ _ENTRY(ITLBMiss_cmp)
#if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
rlwimi r10, r11, 1, MI_SPS16K
#endif
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
li r11, RPN_PATTERN
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20-23 and 28 must be clear.
@@ -528,11 +526,9 @@ _ENTRY(DTLBMiss_jmp)
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
--
2.25.0
^ permalink raw reply related
* [PATCH for 4.9] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set
From: Christophe Leroy @ 2020-11-19 8:47 UTC (permalink / raw)
To: gregkh, stable; +Cc: linuxppc-dev, linux-kernel
[This is backport for 4.9 of 29daf869cbab69088fe1755d9dd224e99ba78b56]
The kernel expects pte_young() to work regardless of CONFIG_SWAP.
Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.
This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.
Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.
Fixes: d069cb4373fe ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497c384 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d90a9f ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc3e8a ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
---
arch/powerpc/kernel/head_8xx.S | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 2274be535dda..3801b32b1642 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -359,11 +359,9 @@ InstructionTLBMiss:
/* Load the MI_TWC with the attributes for this "segment." */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
li r11, RPN_PATTERN
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20-23 and 28 must be clear.
@@ -443,11 +441,9 @@ _ENTRY(DTLBMiss_jmp)
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-11, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
* Software indicator bits 24, 25, 26, and 27 must be
--
2.25.0
^ permalink raw reply related
* [PATCH for 5.4] powerpc/8xx: Always fault when _PAGE_ACCESSED is not set
From: Christophe Leroy @ 2020-11-19 8:47 UTC (permalink / raw)
To: gregkh, stable; +Cc: linuxppc-dev, linux-kernel
[This is backport for 5.4 of 29daf869cbab69088fe1755d9dd224e99ba78b56]
The kernel expects pte_young() to work regardless of CONFIG_SWAP.
Make sure a minor fault is taken to set _PAGE_ACCESSED when it
is not already set, regardless of the selection of CONFIG_SWAP.
This adds at least 3 instructions to the TLB miss exception
handlers fast path. Following patch will reduce this overhead.
Also update the rotation instruction to the correct number of bits
to reflect all changes done to _PAGE_ACCESSED over time.
Fixes: d069cb4373fe ("powerpc/8xx: Don't touch ACCESSED when no SWAP.")
Fixes: 5f356497c384 ("powerpc/8xx: remove unused _PAGE_WRITETHRU")
Fixes: e0a8e0d90a9f ("powerpc/8xx: Handle PAGE_USER via APG bits")
Fixes: 5b2753fc3e8a ("powerpc/8xx: Implementation of PAGE_EXEC")
Fixes: a891c43b97d3 ("powerpc/8xx: Prepare handlers for _PAGE_HUGE for 512k pages.")
Cc: stable@vger.kernel.org
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/af834e8a0f1fa97bfae65664950f0984a70c4750.1602492856.git.christophe.leroy@csgroup.eu
---
arch/powerpc/kernel/head_8xx.S | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 98d8b6832fcb..f6428b90a6c7 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -229,9 +229,7 @@ SystemCall:
InstructionTLBMiss:
mtspr SPRN_SPRG_SCRATCH0, r10
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
mtspr SPRN_SPRG_SCRATCH1, r11
-#endif
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
@@ -278,11 +276,9 @@ InstructionTLBMiss:
#ifdef ITLB_MISS_KERNEL
mtcr r11
#endif
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-7, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 20 and 23 must be clear.
* Software indicator bits 22, 24, 25, 26, and 27 must be
@@ -296,9 +292,7 @@ InstructionTLBMiss:
/* Restore registers */
0: mfspr r10, SPRN_SPRG_SCRATCH0
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
mfspr r11, SPRN_SPRG_SCRATCH1
-#endif
rfi
patch_site 0b, patch__itlbmiss_exit_1
@@ -308,9 +302,7 @@ InstructionTLBMiss:
addi r10, r10, 1
stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
mfspr r10, SPRN_SPRG_SCRATCH0
-#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
mfspr r11, SPRN_SPRG_SCRATCH1
-#endif
rfi
#endif
@@ -394,11 +386,9 @@ DataStoreTLBMiss:
* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
* r10 = (r10 & ~PRESENT) | r11;
*/
-#ifdef CONFIG_SWAP
- rlwinm r11, r10, 32-5, _PAGE_PRESENT
+ rlwinm r11, r10, 32-7, _PAGE_PRESENT
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
-#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 24, 25, 26, and 27 must be
* set. All other Linux PTE bits control the behavior
--
2.25.0
^ permalink raw reply related
* Re: [PATCH net-next v2 1/9] ibmvnic: Introduce indirect subordinate Command Response Queue buffer
From: ljp @ 2020-11-19 9:34 UTC (permalink / raw)
To: Thomas Falcon
Cc: cforno12, netdev, ricklind, dnbanerg, drt, brking, kuba, sukadev,
linuxppc-dev
In-Reply-To: <1605748345-32062-2-git-send-email-tlfalcon@linux.ibm.com>
On 2020-11-18 19:12, Thomas Falcon wrote:
> This patch introduces the infrastructure to send batched subordinate
> Command Response Queue descriptors, which are used by the ibmvnic
> driver to send TX frame and RX buffer descriptors.
>
> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
Acked-by: Lijun Pan <ljp@linux.ibm.com>
^ permalink raw reply
* Re: [PATCH net-next v2 5/9] ibmvnic: Remove send_subcrq function
From: ljp @ 2020-11-19 9:37 UTC (permalink / raw)
To: Thomas Falcon
Cc: cforno12, netdev, ricklind, dnbanerg, Linuxppc-dev, drt, brking,
kuba, sukadev, linuxppc-dev
In-Reply-To: <1605748345-32062-6-git-send-email-tlfalcon@linux.ibm.com>
On 2020-11-18 19:12, Thomas Falcon wrote:
> It is not longer used, so remove it.
>
> Signed-off-by: Thomas Falcon <tlfalcon@linux.ibm.com>
Acked-by: Lijun Pan <ljp@linux.ibm.com>
^ permalink raw reply
* Re: [PATCH net-next v2 9/9] ibmvnic: Do not replenish RX buffers after every polling loop
From: ljp @ 2020-11-19 9:43 UTC (permalink / raw)
To: Thomas Falcon
Cc: cforno12, netdev, ricklind, dnbanerg, Linuxppc-dev, drt, brking,
kuba, sukadev, linuxppc-dev
In-Reply-To: <1605748345-32062-10-git-send-email-tlfalcon@linux.ibm.com>
On 2020-11-18 19:12, Thomas Falcon wrote:
> From: "Dwip N. Banerjee" <dnbanerg@us.ibm.com>
>
> Reduce the amount of time spent replenishing RX buffers by
> only doing so once available buffers has fallen under a certain
> threshold, in this case half of the total number of buffers, or
> if the polling loop exits before the packets processed is less
> than its budget.
>
> Signed-off-by: Dwip N. Banerjee <dnbanerg@us.ibm.com>
> ---
> drivers/net/ethernet/ibm/ibmvnic.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/ibm/ibmvnic.c
> b/drivers/net/ethernet/ibm/ibmvnic.c
> index 96df6d8fa277..9fe43ab0496d 100644
> --- a/drivers/net/ethernet/ibm/ibmvnic.c
> +++ b/drivers/net/ethernet/ibm/ibmvnic.c
> @@ -2537,7 +2537,10 @@ static int ibmvnic_poll(struct napi_struct
> *napi, int budget)
> frames_processed++;
> }
>
> - if (adapter->state != VNIC_CLOSING)
> + if (adapter->state != VNIC_CLOSING &&
> + ((atomic_read(&adapter->rx_pool[scrq_num].available) <
> + adapter->req_rx_add_entries_per_subcrq / 2) ||
> + frames_processed < budget))
1/2 seems a simple and good algorithm.
Explaining why "frames_process < budget" is necessary in the commit
message
or source code also helps.
> replenish_rx_pool(adapter, &adapter->rx_pool[scrq_num]);
> if (frames_processed < budget) {
> if (napi_complete_done(napi, frames_processed)) {
^ permalink raw reply
* Re: [PATCH net-next v2 8/9] ibmvnic: Use netdev_alloc_skb instead of alloc_skb to replenish RX buffers
From: ljp @ 2020-11-19 9:47 UTC (permalink / raw)
To: Thomas Falcon
Cc: cforno12, netdev, ricklind, dnbanerg, Linuxppc-dev, drt, brking,
kuba, sukadev, linuxppc-dev
In-Reply-To: <1605748345-32062-9-git-send-email-tlfalcon@linux.ibm.com>
On 2020-11-18 19:12, Thomas Falcon wrote:
> From: "Dwip N. Banerjee" <dnbanerg@us.ibm.com>
>
> Take advantage of the additional optimizations in netdev_alloc_skb when
> allocating socket buffers to be used for packet reception.
>
> Signed-off-by: Dwip N. Banerjee <dnbanerg@us.ibm.com>
Acked-by: Lijun Pan <ljp@linux.ibm.com>
^ permalink raw reply
* Re: [PATCH v2 00/16] PCI: dwc: Another round of clean-ups
From: Lorenzo Pieralisi @ 2020-11-19 11:01 UTC (permalink / raw)
To: Rob Herring
Cc: Kunihiko Hayashi, Neil Armstrong, linux-pci, Binghui Wang,
Bjorn Andersson, linux-tegra, Thierry Reding, linux-arm-kernel,
Thomas Petazzoni, Jonathan Chocron, Shawn Guo,
Kishon Vijay Abraham I, Fabio Estevam, Jerome Brunet,
Jesper Nilsson, Lorenzo Pieralisi, Kevin Hilman, Pratyush Anand,
Krzysztof Kozlowski, Jonathan Hunter, Murali Karicheri,
NXP Linux Team, Xiaowei Song, Marek Szyprowski, Masahiro Yamada,
Richard Zhu, Martin Blumenstingl, linux-arm-msm, Sascha Hauer,
Yue Wang, linux-samsung-soc, Bjorn Helgaas, linux-amlogic,
linux-omap, Mingkai Hu, linux-arm-kernel, Roy Zang, Minghuan Lian,
Jingoo Han, Andy Gross, Vidya Sagar, Stanimir Varbanov,
Kukjin Kim, Pengutronix Kernel Team, Gustavo Pimentel,
linuxppc-dev, Lucas Stach
In-Reply-To: <20201105211159.1814485-1-robh@kernel.org>
On Thu, 5 Nov 2020 15:11:43 -0600, Rob Herring wrote:
> Here's another batch of DWC PCI host refactoring. This series primarily
> moves more of the MSI, link up, and resource handling to the core
> code. Beyond a couple of minor fixes, new in this version is runtime
> detection of iATU regions instead of using DT properties.
>
> No doubt I've probably broken something. Please test. I've run this thru
> kernelci and checked boards with DWC PCI which currently is just
> Layerscape boards (hint: add boards and/or enable PCI). A git branch is
> here[1].
>
> [...]
Applied to pci/dwc, thanks!
[01/16] PCI: dwc: Support multiple ATU memory regions
https://git.kernel.org/lpieralisi/pci/c/9f9e59a480
[02/16] PCI: dwc/intel-gw: Move ATU offset out of driver match data
https://git.kernel.org/lpieralisi/pci/c/1d567aac46
[03/16] PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
https://git.kernel.org/lpieralisi/pci/c/a0fd361db8
[04/16] PCI: dwc/intel-gw: Remove some unneeded function wrappers
https://git.kernel.org/lpieralisi/pci/c/1cc9a55999
[05/16] PCI: dwc: Ensure all outbound ATU windows are reset
https://git.kernel.org/lpieralisi/pci/c/458ad06c4c
[06/16] PCI: dwc/dra7xx: Use the common MSI irq_chip
https://git.kernel.org/lpieralisi/pci/c/7f170d35f5
[07/16] PCI: dwc: Drop the .set_num_vectors() host op
https://git.kernel.org/lpieralisi/pci/c/331e9bcead
[08/16] PCI: dwc: Move MSI interrupt setup into DWC common code
https://git.kernel.org/lpieralisi/pci/c/5bcb1757e6
[09/16] PCI: dwc: Rework MSI initialization
https://git.kernel.org/lpieralisi/pci/c/f78f02638a
[10/16] PCI: dwc: Move link handling into common code
https://git.kernel.org/lpieralisi/pci/c/886a9c1347
[11/16] PCI: dwc: Move dw_pcie_msi_init() into core
https://git.kernel.org/lpieralisi/pci/c/59fbab1ae4
[12/16] PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
https://git.kernel.org/lpieralisi/pci/c/b9ac0f9dc8
[13/16] PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
https://git.kernel.org/lpieralisi/pci/c/60f5b73fa0
[14/16] Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
https://git.kernel.org/lpieralisi/pci/c/fcde397422
[15/16] PCI: dwc: Move inbound and outbound windows to common struct
https://git.kernel.org/lpieralisi/pci/c/9ca17af552
[16/16] PCI: dwc: Detect number of iATU windows
https://git.kernel.org/lpieralisi/pci/c/281f1f99cf
Thanks,
Lorenzo
^ permalink raw reply
* CONFIG_PPC_VAS depends on 64k pages...?
From: Will Springer @ 2020-11-19 10:58 UTC (permalink / raw)
To: linuxppc-dev; +Cc: daniel
I learned about the POWER9 gzip accelerator a few months ago when the
support hit upstream Linux 5.8. However, for some reason the Kconfig
dictates that VAS depends on a 64k page size, which is problematic as I
run Void Linux, which uses a 4k-page kernel.
Some early poking by others indicated there wasn't an obvious page size
dependency in the code, and suggested I try modifying the config to switch
it on. I did so, but was stopped by a minor complaint of an "unexpected DT
configuration" by the VAS code. I wasn't equipped to figure out exactly what
this meant, even after finding the offending condition, so after writing a
very drawn-out forum post asking for help, I dropped the subject.
Fast forward to today, when I was reminded of the whole thing again, and
decided to debug a bit further. Apparently the VAS platform device
(derived from the DT node) has 5 resources on my 4k kernel, instead of 4
(which evidently works for others who have had success on 64k kernels). I
have no idea what this means in practice (I don't know how to introspect
it), but after making a tiny patch[1], everything came up smoothly and I
was doing blazing-fast gzip (de)compression in no time.
Everything seems to work fine on 4k pages. So, what's up? Are there
pitfalls lurking around that I've yet to stumble over? More reasonably,
I'm curious as to why the feature supposedly depends on 64k pages, or if
there's anything else I should be concerned about.
I do have to say I'm quite satisfied with the results of the NX
accelerator, though. Being able to shuffle data to a RaptorCS box over gigE
and get compressed data back faster than most software gzip could ever
hope to achieve is no small feat, let alone the instantaneous results locally.
:)
Cheers,
Will Springer [she/her]
[1]: https://github.com/Skirmisher/void-packages/blob/vas-4k-pages/srcpkgs/linux5.9/patches/ppc-vas-on-4k.patch
^ permalink raw reply
* Re: CONFIG_PPC_VAS depends on 64k pages...?
From: Christophe Leroy @ 2020-11-19 14:43 UTC (permalink / raw)
To: Will Springer, linuxppc-dev, Sukadev Bhattiprolu; +Cc: daniel
In-Reply-To: <7171078.EvYhyI6sBW@sheen>
Hi,
Le 19/11/2020 à 11:58, Will Springer a écrit :
> I learned about the POWER9 gzip accelerator a few months ago when the
> support hit upstream Linux 5.8. However, for some reason the Kconfig
> dictates that VAS depends on a 64k page size, which is problematic as I
> run Void Linux, which uses a 4k-page kernel.
>
> Some early poking by others indicated there wasn't an obvious page size
> dependency in the code, and suggested I try modifying the config to switch
> it on. I did so, but was stopped by a minor complaint of an "unexpected DT
> configuration" by the VAS code. I wasn't equipped to figure out exactly what
> this meant, even after finding the offending condition, so after writing a
> very drawn-out forum post asking for help, I dropped the subject.
>
> Fast forward to today, when I was reminded of the whole thing again, and
> decided to debug a bit further. Apparently the VAS platform device
> (derived from the DT node) has 5 resources on my 4k kernel, instead of 4
> (which evidently works for others who have had success on 64k kernels). I
> have no idea what this means in practice (I don't know how to introspect
> it), but after making a tiny patch[1], everything came up smoothly and I
> was doing blazing-fast gzip (de)compression in no time.
>
> Everything seems to work fine on 4k pages. So, what's up? Are there
> pitfalls lurking around that I've yet to stumble over? More reasonably,
> I'm curious as to why the feature supposedly depends on 64k pages, or if
> there's anything else I should be concerned about.
>
Maybe ask Sukadev who did the implementation and is maintaining it ?
> I do have to say I'm quite satisfied with the results of the NX
> accelerator, though. Being able to shuffle data to a RaptorCS box over gigE
> and get compressed data back faster than most software gzip could ever
> hope to achieve is no small feat, let alone the instantaneous results locally.
> :)
>
> Cheers,
> Will Springer [she/her]
>
> [1]: https://github.com/Skirmisher/void-packages/blob/vas-4k-pages/srcpkgs/linux5.9/patches/ppc-vas-on-4k.patch
>
Christophe
^ permalink raw reply
* [PATCH v3 0/2] powerpc/ptrace: Hard wire PT_SOFTE value to 1 in gpr_get() too
From: Oleg Nesterov @ 2020-11-19 16:01 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Madhavan Srinivasan, Michael Ellerman,
Paul Mackerras
Cc: Christophe Leroy, Aneesh Kumar K.V, linux-kernel, Nicholas Piggin,
Jan Kratochvil, Al Viro, linuxppc-dev
Can we finally fix this problem? ;)
My previous attempt was ignored, see
https://lore.kernel.org/lkml/20190917121256.GA8659@redhat.com/
Now that gpr_get() was changed to use membuf API we can make a simpler fix.
Sorry, uncompiled/untested, I don't have a ppc machine.
Oleg.
arch/powerpc/kernel/ptrace/ptrace-tm.c | 21 ++++++++++++---------
arch/powerpc/kernel/ptrace/ptrace-view.c | 21 ++++++++++++---------
include/linux/regset.h | 12 ++++++++++++
3 files changed, 36 insertions(+), 18 deletions(-)
^ permalink raw reply
* [PATCH v3 1/2] powerpc/ptrace: simplify gpr_get/tm_cgpr_get
From: Oleg Nesterov @ 2020-11-19 16:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Madhavan Srinivasan, Michael Ellerman,
Paul Mackerras
Cc: Christophe Leroy, Aneesh Kumar K.V, linux-kernel, Nicholas Piggin,
Jan Kratochvil, Al Viro, linuxppc-dev
In-Reply-To: <20201119160154.GA5183@redhat.com>
gpr_get() does membuf_write() twice to override pt_regs->msr in between.
We can call membuf_write() once and change ->msr in the kernel buffer,
this simplifies the code and the next fix.
The patch adds a new simple helper, membuf_at(offs), it returns the new
membuf which can be safely used after membuf_write().
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
---
arch/powerpc/kernel/ptrace/ptrace-tm.c | 13 +++++--------
arch/powerpc/kernel/ptrace/ptrace-view.c | 13 +++++--------
include/linux/regset.h | 12 ++++++++++++
3 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-tm.c b/arch/powerpc/kernel/ptrace/ptrace-tm.c
index 54f2d076206f..f8fcbd85d4cb 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-tm.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-tm.c
@@ -86,6 +86,8 @@ int tm_cgpr_active(struct task_struct *target, const struct user_regset *regset)
int tm_cgpr_get(struct task_struct *target, const struct user_regset *regset,
struct membuf to)
{
+ struct membuf to_msr = membuf_at(&to, offsetof(struct pt_regs, msr));
+
if (!cpu_has_feature(CPU_FTR_TM))
return -ENODEV;
@@ -97,17 +99,12 @@ int tm_cgpr_get(struct task_struct *target, const struct user_regset *regset,
flush_altivec_to_thread(target);
membuf_write(&to, &target->thread.ckpt_regs,
- offsetof(struct pt_regs, msr));
- membuf_store(&to, get_user_ckpt_msr(target));
+ sizeof(struct user_pt_regs));
- BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
- offsetof(struct pt_regs, msr) + sizeof(long));
+ membuf_store(&to_msr, get_user_ckpt_msr(target));
- membuf_write(&to, &target->thread.ckpt_regs.orig_gpr3,
- sizeof(struct user_pt_regs) -
- offsetof(struct pt_regs, orig_gpr3));
return membuf_zero(&to, ELF_NGREG * sizeof(unsigned long) -
- sizeof(struct user_pt_regs));
+ sizeof(struct user_pt_regs));
}
/*
diff --git a/arch/powerpc/kernel/ptrace/ptrace-view.c b/arch/powerpc/kernel/ptrace/ptrace-view.c
index 7e6478e7ed07..39686ede40b3 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-view.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-view.c
@@ -217,6 +217,7 @@ int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
static int gpr_get(struct task_struct *target, const struct user_regset *regset,
struct membuf to)
{
+ struct membuf to_msr = membuf_at(&to, offsetof(struct pt_regs, msr));
int i;
if (target->thread.regs == NULL)
@@ -228,17 +229,13 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset,
target->thread.regs->gpr[i] = NV_REG_POISON;
}
- membuf_write(&to, target->thread.regs, offsetof(struct pt_regs, msr));
- membuf_store(&to, get_user_msr(target));
+ membuf_write(&to, target->thread.regs,
+ sizeof(struct user_pt_regs));
- BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
- offsetof(struct pt_regs, msr) + sizeof(long));
+ membuf_store(&to_msr, get_user_msr(target));
- membuf_write(&to, &target->thread.regs->orig_gpr3,
- sizeof(struct user_pt_regs) -
- offsetof(struct pt_regs, orig_gpr3));
return membuf_zero(&to, ELF_NGREG * sizeof(unsigned long) -
- sizeof(struct user_pt_regs));
+ sizeof(struct user_pt_regs));
}
static int gpr_set(struct task_struct *target, const struct user_regset *regset,
diff --git a/include/linux/regset.h b/include/linux/regset.h
index c3403f328257..a00765f0e8cf 100644
--- a/include/linux/regset.h
+++ b/include/linux/regset.h
@@ -46,6 +46,18 @@ static inline int membuf_write(struct membuf *s, const void *v, size_t size)
return s->left;
}
+static inline struct membuf membuf_at(const struct membuf *s, size_t offs)
+{
+ struct membuf n = *s;
+
+ if (offs > n.left)
+ offs = n.left;
+ n.p += offs;
+ n.left -= offs;
+
+ return n;
+}
+
/* current s->p must be aligned for v; v must be a scalar */
#define membuf_store(s, v) \
({ \
--
2.25.1.362.g51ebf55
^ permalink raw reply related
* [PATCH v3 2/2] powerpc/ptrace: Hard wire PT_SOFTE value to 1 in gpr_get() too
From: Oleg Nesterov @ 2020-11-19 16:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Madhavan Srinivasan, Michael Ellerman,
Paul Mackerras
Cc: Christophe Leroy, Aneesh Kumar K.V, linux-kernel, Nicholas Piggin,
Jan Kratochvil, Al Viro, linuxppc-dev
In-Reply-To: <20201119160154.GA5183@redhat.com>
The commit a8a4b03ab95f ("powerpc: Hard wire PT_SOFTE value to 1 in
ptrace & signals") changed ptrace_get_reg(PT_SOFTE) to report 0x1,
but PTRACE_GETREGS still copies pt_regs->softe as is.
This is not consistent and this breaks the user-regs-peekpoke test
from https://sourceware.org/systemtap/wiki/utrace/tests/
Reported-by: Jan Kratochvil <jan.kratochvil@redhat.com>
Signed-off-by: Oleg Nesterov <oleg@redhat.com>
---
arch/powerpc/kernel/ptrace/ptrace-tm.c | 8 +++++++-
arch/powerpc/kernel/ptrace/ptrace-view.c | 8 +++++++-
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/ptrace/ptrace-tm.c b/arch/powerpc/kernel/ptrace/ptrace-tm.c
index f8fcbd85d4cb..d0d339f86e61 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-tm.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-tm.c
@@ -87,6 +87,10 @@ int tm_cgpr_get(struct task_struct *target, const struct user_regset *regset,
struct membuf to)
{
struct membuf to_msr = membuf_at(&to, offsetof(struct pt_regs, msr));
+#ifdef CONFIG_PPC64
+ struct membuf to_softe = membuf_at(&to,
+ offsetof(struct pt_regs, softe));
+#endif
if (!cpu_has_feature(CPU_FTR_TM))
return -ENODEV;
@@ -102,7 +106,9 @@ int tm_cgpr_get(struct task_struct *target, const struct user_regset *regset,
sizeof(struct user_pt_regs));
membuf_store(&to_msr, get_user_ckpt_msr(target));
-
+#ifdef CONFIG_PPC64
+ membuf_store(&to_softe, 0x1ul);
+#endif
return membuf_zero(&to, ELF_NGREG * sizeof(unsigned long) -
sizeof(struct user_pt_regs));
}
diff --git a/arch/powerpc/kernel/ptrace/ptrace-view.c b/arch/powerpc/kernel/ptrace/ptrace-view.c
index 39686ede40b3..f554ccfcbfae 100644
--- a/arch/powerpc/kernel/ptrace/ptrace-view.c
+++ b/arch/powerpc/kernel/ptrace/ptrace-view.c
@@ -218,6 +218,10 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset,
struct membuf to)
{
struct membuf to_msr = membuf_at(&to, offsetof(struct pt_regs, msr));
+#ifdef CONFIG_PPC64
+ struct membuf to_softe = membuf_at(&to,
+ offsetof(struct pt_regs, softe));
+#endif
int i;
if (target->thread.regs == NULL)
@@ -233,7 +237,9 @@ static int gpr_get(struct task_struct *target, const struct user_regset *regset,
sizeof(struct user_pt_regs));
membuf_store(&to_msr, get_user_msr(target));
-
+#ifdef CONFIG_PPC64
+ membuf_store(&to_softe, 0x1ul);
+#endif
return membuf_zero(&to, ELF_NGREG * sizeof(unsigned long) -
sizeof(struct user_pt_regs));
}
--
2.25.1.362.g51ebf55
^ permalink raw reply related
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