* [PATCH v2 12/13] powerpc/xive: Improve error reporting of OPAL calls
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
Introduce a vp_err() macro to standardize error reporting.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/native.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index e91519c42463..05a800a3104e 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -122,6 +122,8 @@ static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
return rc == 0 ? 0 : -ENXIO;
}
+#define vp_err(vp, fmt, ...) pr_err("VP[0x%x]: " fmt, vp, ##__VA_ARGS__)
+
/* This can be called multiple time to change a queue configuration */
int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
__be32 *qpage, u32 order, bool can_escalate)
@@ -149,7 +151,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
&esc_irq_be,
NULL);
if (rc) {
- pr_err("Error %lld getting queue info prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc);
rc = -EIO;
goto fail;
}
@@ -172,7 +174,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
msleep(OPAL_BUSY_DELAY_MS);
}
if (rc) {
- pr_err("Error %lld setting queue for prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc);
rc = -EIO;
} else {
/*
@@ -199,7 +201,7 @@ static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
msleep(OPAL_BUSY_DELAY_MS);
}
if (rc)
- pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
+ vp_err(vp_id, "Failed to disable queue %d : %lld\n", prio, rc);
}
void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
@@ -698,6 +700,8 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation)
break;
msleep(OPAL_BUSY_DELAY_MS);
}
+ if (rc)
+ vp_err(vp_id, "Failed to enable VP : %lld\n", rc);
return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_enable_vp);
@@ -712,6 +716,8 @@ int xive_native_disable_vp(u32 vp_id)
break;
msleep(OPAL_BUSY_DELAY_MS);
}
+ if (rc)
+ vp_err(vp_id, "Failed to disable VP : %lld\n", rc);
return rc ? -EIO : 0;
}
EXPORT_SYMBOL_GPL(xive_native_disable_vp);
@@ -723,8 +729,10 @@ int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
s64 rc;
rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
- if (rc)
+ if (rc) {
+ vp_err(vp_id, "Failed to get VP info : %lld\n", rc);
return -EIO;
+ }
*out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
*out_chip_id = be32_to_cpu(vp_chip_id_be);
@@ -755,8 +763,7 @@ int xive_native_get_queue_info(u32 vp_id, u32 prio,
rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
&qeoi_page, &escalate_irq, &qflags);
if (rc) {
- pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to get queue %d info : %lld\n", prio, rc);
return -EIO;
}
@@ -784,8 +791,7 @@ int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
&opal_qindex);
if (rc) {
- pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to get queue %d state : %lld\n", prio, rc);
return -EIO;
}
@@ -804,8 +810,7 @@ int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
if (rc) {
- pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
- vp_id, prio, rc);
+ vp_err(vp_id, "failed to set queue %d state : %lld\n", prio, rc);
return -EIO;
}
@@ -827,8 +832,7 @@ int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
rc = opal_xive_get_vp_state(vp_id, &state);
if (rc) {
- pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
- vp_id, rc);
+ vp_err(vp_id, "failed to get vp state : %lld\n", rc);
return -EIO;
}
--
2.26.2
^ permalink raw reply related
* [PATCH v2 03/13] powerpc/xive: Introduce XIVE_IPI_HW_IRQ
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
The XIVE driver deals with CPU IPIs in a peculiar way. Each CPU has
its own XIVE IPI interrupt allocated at the HW level, for PowerNV, or
at the hypervisor level for pSeries. In practice, these interrupts are
not always used. pSeries/PowerVM prefers local doorbells for local
threads since they are faster. On PowerNV, global doorbells are also
preferred for the same reason.
The mapping in the Linux is reduced to a single interrupt using HW
interrupt number 0 and a custom irq_chip to handle EOI. This can cause
performance issues in some benchmark (ipistorm) on multichip systems.
Clarify the use of the 0 value, it will help in improving multichip
support.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/xive-internal.h | 2 ++
arch/powerpc/sysdev/xive/common.c | 10 +++++-----
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h
index b7b901da2168..d701af7fb48c 100644
--- a/arch/powerpc/sysdev/xive/xive-internal.h
+++ b/arch/powerpc/sysdev/xive/xive-internal.h
@@ -5,6 +5,8 @@
#ifndef __XIVE_INTERNAL_H
#define __XIVE_INTERNAL_H
+#define XIVE_IPI_HW_IRQ 0 /* interrupt source # for IPIs */
+
/*
* A "disabled" interrupt should never fire, to catch problems
* we set its logical number to this
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 65af34ac1fa2..ee375daf8114 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -1142,7 +1142,7 @@ static void __init xive_request_ipi(void)
return;
/* Initialize it */
- virq = irq_create_mapping(xive_irq_domain, 0);
+ virq = irq_create_mapping(xive_irq_domain, XIVE_IPI_HW_IRQ);
xive_ipi_irq = virq;
WARN_ON(request_irq(virq, xive_muxed_ipi_action,
@@ -1242,7 +1242,7 @@ static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
#ifdef CONFIG_SMP
/* IPIs are special and come up with HW number 0 */
- if (hw == 0) {
+ if (hw == XIVE_IPI_HW_IRQ) {
/*
* IPIs are marked per-cpu. We use separate HW interrupts under
* the hood but associated with the same "linux" interrupt
@@ -1271,7 +1271,7 @@ static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
if (!data)
return;
hw_irq = (unsigned int)irqd_to_hwirq(data);
- if (hw_irq)
+ if (hw_irq != XIVE_IPI_HW_IRQ)
xive_irq_free_data(virq);
}
@@ -1421,7 +1421,7 @@ static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
* Ignore anything that isn't a XIVE irq and ignore
* IPIs, so can just be dropped.
*/
- if (d->domain != xive_irq_domain || hw_irq == 0)
+ if (d->domain != xive_irq_domain || hw_irq == XIVE_IPI_HW_IRQ)
continue;
/*
@@ -1655,7 +1655,7 @@ static int xive_core_debug_show(struct seq_file *m, void *private)
hw_irq = (unsigned int)irqd_to_hwirq(d);
/* IPIs are special (HW number 0) */
- if (hw_irq)
+ if (hw_irq != XIVE_IPI_HW_IRQ)
xive_debug_show_irq(m, hw_irq, d);
}
return 0;
--
2.26.2
^ permalink raw reply related
* [PATCH v2 00/13] powerpc/xive: misc cleanups
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
Hello,
The most important change is the removal of support of OPAL flags
required for P9 DD1. It provides a good cleanup of some complex
routines.
Thanks,
C.
Changes since v1:
- dropped the change on the allocation of the pages donated to the
XIVE IC. Needs a retest on a specific system.
- Took into account Greg's comments on flag removal.
Cédric Le Goater (13):
KVM: PPC: Book3S HV: XIVE: Show detailed configuration in debug output
powerpc/xive: Rename XIVE_IRQ_NO_EOI to show its a flag
powerpc/xive: Introduce XIVE_IPI_HW_IRQ
powerpc/xive: Use cpu_to_node() instead of ibm,chip-id property
powerpc/xive: Add a name to the IRQ domain
powerpc/xive: Add a debug_show handler to the XIVE irq_domain
powerpc: Increase NR_IRQS range to support more KVM guests
powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG
powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_MASK_FW
powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW
powerpc/xive: Simplify xive_do_source_eoi()
powerpc/xive: Improve error reporting of OPAL calls
KVM: PPC: Book3S HV: XIVE: Add a comment regarding VP numbering
arch/powerpc/include/asm/opal-api.h | 6 +-
arch/powerpc/include/asm/xive.h | 8 +-
arch/powerpc/kvm/book3s_xive.h | 13 ++
arch/powerpc/sysdev/xive/xive-internal.h | 7 +-
arch/powerpc/kvm/book3s_xive.c | 134 +++++++-------
arch/powerpc/kvm/book3s_xive_native.c | 24 ++-
arch/powerpc/kvm/book3s_xive_template.c | 5 -
arch/powerpc/sysdev/xive/common.c | 214 +++++++++++------------
arch/powerpc/sysdev/xive/native.c | 46 ++---
arch/powerpc/sysdev/xive/spapr.c | 8 +-
arch/powerpc/Kconfig | 2 +-
11 files changed, 234 insertions(+), 233 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH v2 10/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
This flag was used to support the P9 DD1 and we have stopped
supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Also, remove eoi handler which is now unused.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/opal-api.h | 2 +-
arch/powerpc/include/asm/xive.h | 2 +-
arch/powerpc/sysdev/xive/xive-internal.h | 1 -
arch/powerpc/kvm/book3s_xive_template.c | 2 --
arch/powerpc/sysdev/xive/common.c | 14 +-------------
arch/powerpc/sysdev/xive/native.c | 12 ------------
arch/powerpc/sysdev/xive/spapr.c | 6 ------
7 files changed, 3 insertions(+), 36 deletions(-)
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 0455b679c050..0b63ba7d5917 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -1093,7 +1093,7 @@ enum {
OPAL_XIVE_IRQ_LSI = 0x00000004,
OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* P9 DD1.0 workaround */
- OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
+ OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, /* P9 DD1.0 workaround */
};
/* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 8d5b0dcc253c..9a312b975ca8 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -62,7 +62,7 @@ struct xive_irq_data {
#define XIVE_IRQ_FLAG_LSI 0x02
/* #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 */ /* P9 DD1.0 workaround */
/* #define XIVE_IRQ_FLAG_MASK_FW 0x08 */ /* P9 DD1.0 workaround */
-#define XIVE_IRQ_FLAG_EOI_FW 0x10
+/* #define XIVE_IRQ_FLAG_EOI_FW 0x10 */ /* P9 DD1.0 workaround */
#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
/* Special flag set by KVM for excalation interrupts */
diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h
index c07fadb9d264..9cf57c722faa 100644
--- a/arch/powerpc/sysdev/xive/xive-internal.h
+++ b/arch/powerpc/sysdev/xive/xive-internal.h
@@ -52,7 +52,6 @@ struct xive_ops {
void (*shutdown)(void);
void (*update_pending)(struct xive_cpu *xc);
- void (*eoi)(u32 hw_irq);
void (*sync_source)(u32 hw_irq);
u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
#ifdef CONFIG_SMP
diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
index ece36e024a8f..b0015e05d99a 100644
--- a/arch/powerpc/kvm/book3s_xive_template.c
+++ b/arch/powerpc/kvm/book3s_xive_template.c
@@ -74,8 +74,6 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd)
/* If the XIVE supports the new "store EOI facility, use it */
if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
__x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);
- else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW)
- opal_int_eoi(hw_irq);
else if (xd->flags & XIVE_IRQ_FLAG_LSI) {
/*
* For LSIs the HW EOI cycle is used rather than PQ bits,
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index b240eb698920..ed9bc49f45a7 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -354,18 +354,7 @@ static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
/* If the XIVE supports the new "store EOI facility, use it */
if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
- else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
- /*
- * The FW told us to call it. This happens for some
- * interrupt sources that need additional HW whacking
- * beyond the ESB manipulation. For example LPC interrupts
- * on P9 DD1.0 needed a latch to be clared in the LPC bridge
- * itself. The Firmware will take care of it.
- */
- if (WARN_ON_ONCE(!xive_ops->eoi))
- return;
- xive_ops->eoi(hw_irq);
- } else {
+ else {
u8 eoi_val;
/*
@@ -1267,7 +1256,6 @@ static const struct {
} xive_irq_flags[] = {
{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
{ XIVE_IRQ_FLAG_LSI, "LSI" },
- { XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
{ XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
};
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index 6c04ac1f3a1f..e91519c42463 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
if (opal_flags & OPAL_XIVE_IRQ_LSI)
data->flags |= XIVE_IRQ_FLAG_LSI;
- if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
- data->flags |= XIVE_IRQ_FLAG_EOI_FW;
data->eoi_page = be64_to_cpu(eoi_page);
data->trig_page = be64_to_cpu(trig_page);
data->esb_shift = be32_to_cpu(esb_shift);
@@ -380,15 +378,6 @@ static void xive_native_update_pending(struct xive_cpu *xc)
}
}
-static void xive_native_eoi(u32 hw_irq)
-{
- /*
- * Not normally used except if specific interrupts need
- * a workaround on EOI.
- */
- opal_int_eoi(hw_irq);
-}
-
static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
{
s64 rc;
@@ -471,7 +460,6 @@ static const struct xive_ops xive_native_ops = {
.match = xive_native_match,
.shutdown = xive_native_shutdown,
.update_pending = xive_native_update_pending,
- .eoi = xive_native_eoi,
.setup_cpu = xive_native_setup_cpu,
.teardown_cpu = xive_native_teardown_cpu,
.sync_source = xive_native_sync_source,
diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
index 6610e5149d5a..01ccc0786ada 100644
--- a/arch/powerpc/sysdev/xive/spapr.c
+++ b/arch/powerpc/sysdev/xive/spapr.c
@@ -628,11 +628,6 @@ static void xive_spapr_update_pending(struct xive_cpu *xc)
}
}
-static void xive_spapr_eoi(u32 hw_irq)
-{
- /* Not used */;
-}
-
static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
{
/* Only some debug on the TIMA settings */
@@ -677,7 +672,6 @@ static const struct xive_ops xive_spapr_ops = {
.match = xive_spapr_match,
.shutdown = xive_spapr_shutdown,
.update_pending = xive_spapr_update_pending,
- .eoi = xive_spapr_eoi,
.setup_cpu = xive_spapr_setup_cpu,
.teardown_cpu = xive_spapr_teardown_cpu,
.sync_source = xive_spapr_sync_source,
--
2.26.2
^ permalink raw reply related
* [PATCH v2 06/13] powerpc/xive: Add a debug_show handler to the XIVE irq_domain
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
Full state of the Linux interrupt descriptors can be dumped under
debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
the XIVE interrupt controller.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/sysdev/xive/common.c | 58 +++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 7314b87d0b45..348445ffa0af 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -1303,11 +1303,69 @@ static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
return xive_ops->match(node);
}
+#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
+static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
+
+static const struct {
+ u64 mask;
+ char *name;
+} xive_irq_flags[] = {
+ { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
+ { XIVE_IRQ_FLAG_LSI, "LSI" },
+ { XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
+ { XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
+ { XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
+ { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
+ { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
+};
+
+static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
+ struct irq_data *irqd, int ind)
+{
+ struct xive_irq_data *xd;
+ u64 val;
+ int i;
+
+ /* No IRQ domain level information. To be done */
+ if (!irqd)
+ return;
+
+ if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
+ return;
+
+ seq_printf(m, "%*sXIVE:\n", ind, "");
+ ind++;
+
+ xd = irq_data_get_irq_handler_data(irqd);
+ if (!xd) {
+ seq_printf(m, "%*snot assigned\n", ind, "");
+ return;
+ }
+
+ val = xive_esb_read(xd, XIVE_ESB_GET);
+ seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
+ seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
+ xd->saved_p ? "saved" : "");
+ seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
+ seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
+ seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
+ seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
+ seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
+ for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
+ if (xd->flags & xive_irq_flags[i].mask)
+ seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
+ }
+}
+#endif
+
static const struct irq_domain_ops xive_irq_domain_ops = {
.match = xive_irq_domain_match,
.map = xive_irq_domain_map,
.unmap = xive_irq_domain_unmap,
.xlate = xive_irq_domain_xlate,
+#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
+ .debug_show = xive_irq_domain_debug_show,
+#endif
};
static void __init xive_init_host(struct device_node *np)
--
2.26.2
^ permalink raw reply related
* [PATCH v2 09/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_MASK_FW
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/opal-api.h | 2 +-
arch/powerpc/include/asm/xive.h | 2 +-
arch/powerpc/kvm/book3s_xive.c | 54 +++++------------------------
arch/powerpc/sysdev/xive/common.c | 40 +--------------------
arch/powerpc/sysdev/xive/native.c | 2 --
5 files changed, 11 insertions(+), 89 deletions(-)
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 48ee604ca39a..0455b679c050 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -1092,7 +1092,7 @@ enum {
OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
OPAL_XIVE_IRQ_LSI = 0x00000004,
OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
- OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
+ OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* P9 DD1.0 workaround */
OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
};
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index b3c039d0bb6e..8d5b0dcc253c 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -61,7 +61,7 @@ struct xive_irq_data {
#define XIVE_IRQ_FLAG_STORE_EOI 0x01
#define XIVE_IRQ_FLAG_LSI 0x02
/* #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 */ /* P9 DD1.0 workaround */
-#define XIVE_IRQ_FLAG_MASK_FW 0x08
+/* #define XIVE_IRQ_FLAG_MASK_FW 0x08 */ /* P9 DD1.0 workaround */
#define XIVE_IRQ_FLAG_EOI_FW 0x10
#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index fae1c2e8da29..30dfeac731c6 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -419,37 +419,16 @@ static u8 xive_lock_and_mask(struct kvmppc_xive *xive,
/* Get the right irq */
kvmppc_xive_select_irq(state, &hw_num, &xd);
+ /* Set PQ to 10, return old P and old Q and remember them */
+ val = xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_10);
+ state->old_p = !!(val & 2);
+ state->old_q = !!(val & 1);
+
/*
- * If the interrupt is marked as needing masking via
- * firmware, we do it here. Firmware masking however
- * is "lossy", it won't return the old p and q bits
- * and won't set the interrupt to a state where it will
- * record queued ones. If this is an issue we should do
- * lazy masking instead.
- *
- * For now, we work around this in unmask by forcing
- * an interrupt whenever we unmask a non-LSI via FW
- * (if ever).
+ * Synchronize hardware to sensure the queues are updated when
+ * masking
*/
- if (xd->flags & OPAL_XIVE_IRQ_MASK_VIA_FW) {
- xive_native_configure_irq(hw_num,
- kvmppc_xive_vp(xive, state->act_server),
- MASKED, state->number);
- /* set old_p so we can track if an H_EOI was done */
- state->old_p = true;
- state->old_q = false;
- } else {
- /* Set PQ to 10, return old P and old Q and remember them */
- val = xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_10);
- state->old_p = !!(val & 2);
- state->old_q = !!(val & 1);
-
- /*
- * Synchronize hardware to sensure the queues are updated
- * when masking
- */
- xive_native_sync_source(hw_num);
- }
+ xive_native_sync_source(hw_num);
return old_prio;
}
@@ -483,23 +462,6 @@ static void xive_finish_unmask(struct kvmppc_xive *xive,
/* Get the right irq */
kvmppc_xive_select_irq(state, &hw_num, &xd);
- /*
- * See comment in xive_lock_and_mask() concerning masking
- * via firmware.
- */
- if (xd->flags & OPAL_XIVE_IRQ_MASK_VIA_FW) {
- xive_native_configure_irq(hw_num,
- kvmppc_xive_vp(xive, state->act_server),
- state->act_priority, state->number);
- /* If an EOI is needed, do it here */
- if (!state->old_p)
- xive_vm_source_eoi(hw_num, xd);
- /* If this is not an LSI, force a trigger */
- if (!(xd->flags & OPAL_XIVE_IRQ_LSI))
- xive_irq_trigger(xd);
- goto bail;
- }
-
/* Old Q set, set PQ to 11 */
if (state->old_q)
xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_11);
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 7b6e3149f1ea..b240eb698920 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -424,9 +424,7 @@ static void xive_irq_eoi(struct irq_data *d)
}
/*
- * Helper used to mask and unmask an interrupt source. This
- * is only called for normal interrupts that do not require
- * masking/unmasking via firmware.
+ * Helper used to mask and unmask an interrupt source.
*/
static void xive_do_source_set_mask(struct xive_irq_data *xd,
bool mask)
@@ -673,20 +671,6 @@ static void xive_irq_unmask(struct irq_data *d)
pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
- /*
- * This is a workaround for PCI LSI problems on P9, for
- * these, we call FW to set the mask. The problems might
- * be fixed by P9 DD2.0, if that is the case, firmware
- * will no longer set that flag.
- */
- if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
- unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
- xive_ops->configure_irq(hw_irq,
- get_hard_smp_processor_id(xd->target),
- xive_irq_priority, d->irq);
- return;
- }
-
xive_do_source_set_mask(xd, false);
}
@@ -696,20 +680,6 @@ static void xive_irq_mask(struct irq_data *d)
pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
- /*
- * This is a workaround for PCI LSI problems on P9, for
- * these, we call OPAL to set the mask. The problems might
- * be fixed by P9 DD2.0, if that is the case, firmware
- * will no longer set that flag.
- */
- if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
- unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
- xive_ops->configure_irq(hw_irq,
- get_hard_smp_processor_id(xd->target),
- 0xff, d->irq);
- return;
- }
-
xive_do_source_set_mask(xd, true);
}
@@ -852,13 +822,6 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
int rc;
u8 pq;
- /*
- * We only support this on interrupts that do not require
- * firmware calls for masking and unmasking
- */
- if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
- return -EIO;
-
/*
* This is called by KVM with state non-NULL for enabling
* pass-through or NULL for disabling it
@@ -1304,7 +1267,6 @@ static const struct {
} xive_irq_flags[] = {
{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
{ XIVE_IRQ_FLAG_LSI, "LSI" },
- { XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
{ XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
{ XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index f501b1640068..6c04ac1f3a1f 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
if (opal_flags & OPAL_XIVE_IRQ_LSI)
data->flags |= XIVE_IRQ_FLAG_LSI;
- if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
- data->flags |= XIVE_IRQ_FLAG_MASK_FW;
if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
data->flags |= XIVE_IRQ_FLAG_EOI_FW;
data->eoi_page = be64_to_cpu(eoi_page);
--
2.26.2
^ permalink raw reply related
* [PATCH v2 13/13] KVM: PPC: Book3S HV: XIVE: Add a comment regarding VP numbering
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
When the XIVE resources are allocated at the HW level, the VP
structures describing the vCPUs of a guest are distributed among
the chips to optimize the PowerBUS usage. For best performance, the
guest vCPUs can be pinned to match the VP structure distribution.
Currently, the VP identifiers are deduced from the vCPU id using
the kvmppc_pack_vcpu_id() routine which is not incorrect but not
optimal either. It VSMT is used, the result is not continuous and
the constraints on HW resources described above can not be met.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/kvm/book3s_xive.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_xive.h b/arch/powerpc/kvm/book3s_xive.h
index d5d4fee7ac94..86c24a4ad809 100644
--- a/arch/powerpc/kvm/book3s_xive.h
+++ b/arch/powerpc/kvm/book3s_xive.h
@@ -218,6 +218,17 @@ static inline struct kvmppc_xive_src_block *kvmppc_xive_find_source(struct kvmpp
return xive->src_blocks[bid];
}
+/*
+ * When the XIVE resources are allocated at the HW level, the VP
+ * structures describing the vCPUs of a guest are distributed among
+ * the chips to optimize the PowerBUS usage. For best performance, the
+ * guest vCPUs can be pinned to match the VP structure distribution.
+ *
+ * Currently, the VP identifiers are deduced from the vCPU id using
+ * the kvmppc_pack_vcpu_id() routine which is not incorrect but not
+ * optimal either. It VSMT is used, the result is not continuous and
+ * the constraints on HW resources described above can not be met.
+ */
static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server)
{
return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
--
2.26.2
^ permalink raw reply related
* [PATCH v2 08/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_SHIFT_BUG
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
This flag was used to support the PHB4 LSIs on P9 DD1 and we have
stopped supporting this CPU when DD2 came out. See skiboot commit:
https://github.com/open-power/skiboot/commit/0b0d15e3c170
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/opal-api.h | 2 +-
arch/powerpc/include/asm/xive.h | 2 +-
arch/powerpc/kvm/book3s_xive_native.c | 3 ---
arch/powerpc/kvm/book3s_xive_template.c | 3 ---
arch/powerpc/sysdev/xive/common.c | 9 ---------
arch/powerpc/sysdev/xive/native.c | 2 --
6 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 1dffa3cb16ba..48ee604ca39a 100644
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -1091,7 +1091,7 @@ enum {
OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
OPAL_XIVE_IRQ_LSI = 0x00000004,
- OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
+ OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
};
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index d332dd9a18de..b3c039d0bb6e 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -60,7 +60,7 @@ struct xive_irq_data {
};
#define XIVE_IRQ_FLAG_STORE_EOI 0x01
#define XIVE_IRQ_FLAG_LSI 0x02
-#define XIVE_IRQ_FLAG_SHIFT_BUG 0x04
+/* #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 */ /* P9 DD1.0 workaround */
#define XIVE_IRQ_FLAG_MASK_FW 0x08
#define XIVE_IRQ_FLAG_EOI_FW 0x10
#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
diff --git a/arch/powerpc/kvm/book3s_xive_native.c b/arch/powerpc/kvm/book3s_xive_native.c
index 9b395381179d..170d1d04e1d1 100644
--- a/arch/powerpc/kvm/book3s_xive_native.c
+++ b/arch/powerpc/kvm/book3s_xive_native.c
@@ -37,9 +37,6 @@ static u8 xive_vm_esb_load(struct xive_irq_data *xd, u32 offset)
* ordering.
*/
- if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
- offset |= offset << 4;
-
val = in_be64(xd->eoi_mmio + offset);
return (u8)val;
}
diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
index 4ad3c0279458..ece36e024a8f 100644
--- a/arch/powerpc/kvm/book3s_xive_template.c
+++ b/arch/powerpc/kvm/book3s_xive_template.c
@@ -61,9 +61,6 @@ static u8 GLUE(X_PFX,esb_load)(struct xive_irq_data *xd, u32 offset)
if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
offset |= XIVE_ESB_LD_ST_MO;
- if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
- offset |= offset << 4;
-
val =__x_readq(__x_eoi_page(xd) + offset);
#ifdef __LITTLE_ENDIAN__
val >>= 64-8;
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index 348445ffa0af..7b6e3149f1ea 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -200,10 +200,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
offset |= XIVE_ESB_LD_ST_MO;
- /* Handle HW errata */
- if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
- offset |= offset << 4;
-
if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
else
@@ -214,10 +210,6 @@ static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
{
- /* Handle HW errata */
- if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
- offset |= offset << 4;
-
if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
else
@@ -1312,7 +1304,6 @@ static const struct {
} xive_irq_flags[] = {
{ XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
{ XIVE_IRQ_FLAG_LSI, "LSI" },
- { XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
{ XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
{ XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
{ XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
index c3182ec9ed65..f501b1640068 100644
--- a/arch/powerpc/sysdev/xive/native.c
+++ b/arch/powerpc/sysdev/xive/native.c
@@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
if (opal_flags & OPAL_XIVE_IRQ_LSI)
data->flags |= XIVE_IRQ_FLAG_LSI;
- if (opal_flags & OPAL_XIVE_IRQ_SHIFT_BUG)
- data->flags |= XIVE_IRQ_FLAG_SHIFT_BUG;
if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
data->flags |= XIVE_IRQ_FLAG_MASK_FW;
if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
--
2.26.2
^ permalink raw reply related
* [PATCH v2 07/13] powerpc: Increase NR_IRQS range to support more KVM guests
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
PowerNV systems can handle up to 4K guests and 1M interrupt numbers
per chip. Increase the range of allowed interrupts to support a larger
number of guests.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 5181872f9452..c250fbd430d1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -66,7 +66,7 @@ config NEED_PER_CPU_PAGE_FIRST_CHUNK
config NR_IRQS
int "Number of virtual interrupt numbers"
- range 32 32768
+ range 32 1048576
default "512"
help
This defines the number of virtual interrupt numbers the kernel
--
2.26.2
^ permalink raw reply related
* [PATCH v2 02/13] powerpc/xive: Rename XIVE_IRQ_NO_EOI to show its a flag
From: Cédric Le Goater @ 2020-12-10 17:14 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-1-clg@kaod.org>
This is a simple cleanup to identify easily all flags of the XIVE
interrupt structure. The interrupts flagged with XIVE_IRQ_FLAG_NO_EOI
are the escalations used to wake up vCPUs in KVM. They are handled
very differently from the rest.
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
arch/powerpc/include/asm/xive.h | 2 +-
arch/powerpc/kvm/book3s_xive.c | 4 ++--
arch/powerpc/sysdev/xive/common.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
index 309b4d65b74f..d332dd9a18de 100644
--- a/arch/powerpc/include/asm/xive.h
+++ b/arch/powerpc/include/asm/xive.h
@@ -66,7 +66,7 @@ struct xive_irq_data {
#define XIVE_IRQ_FLAG_H_INT_ESB 0x20
/* Special flag set by KVM for excalation interrupts */
-#define XIVE_IRQ_NO_EOI 0x80
+#define XIVE_IRQ_FLAG_NO_EOI 0x80
#define XIVE_INVALID_CHIP_ID -1
diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
index 18a6b75a3bfd..fae1c2e8da29 100644
--- a/arch/powerpc/kvm/book3s_xive.c
+++ b/arch/powerpc/kvm/book3s_xive.c
@@ -219,7 +219,7 @@ int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
/* In single escalation mode, we grab the ESB MMIO of the
* interrupt and mask it. Also populate the VCPU v/raddr
* of the ESB page for use by asm entry/exit code. Finally
- * set the XIVE_IRQ_NO_EOI flag which will prevent the
+ * set the XIVE_IRQ_FLAG_NO_EOI flag which will prevent the
* core code from performing an EOI on the escalation
* interrupt, thus leaving it effectively masked after
* it fires once.
@@ -231,7 +231,7 @@ int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_01);
vcpu->arch.xive_esc_raddr = xd->eoi_page;
vcpu->arch.xive_esc_vaddr = (__force u64)xd->eoi_mmio;
- xd->flags |= XIVE_IRQ_NO_EOI;
+ xd->flags |= XIVE_IRQ_FLAG_NO_EOI;
}
return 0;
diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
index a80440af491a..65af34ac1fa2 100644
--- a/arch/powerpc/sysdev/xive/common.c
+++ b/arch/powerpc/sysdev/xive/common.c
@@ -416,7 +416,7 @@ static void xive_irq_eoi(struct irq_data *d)
* been passed-through to a KVM guest
*/
if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
- !(xd->flags & XIVE_IRQ_NO_EOI))
+ !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
xive_do_source_eoi(irqd_to_hwirq(d), xd);
else
xd->stale_p = true;
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Bjorn Helgaas @ 2020-12-10 17:38 UTC (permalink / raw)
To: Vladimir Oltean
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209202904.2juzokqhleusgsts@skbuf>
On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> > Hopefully my mail client won't mess up the output that much.
>
> I can reproduce on my LS1028A as well. The following fixes the bug for
> me. I did not follow the discussion and see if it is helpful for others.
> I don't understand how the bug came to be. There might be more to it
> than what I'm seeing. If it's just what I'm seeing, then the patch was
> pretty broken to begin with.
I squashed the fix below into a pci/ecam branch for v5.11, thanks!
> -----------------------------[cut here]-----------------------------
> From b184da4088c9d39d25fee2486941cdf77688a409 Mon Sep 17 00:00:00 2001
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> Date: Wed, 9 Dec 2020 22:17:32 +0200
> Subject: [PATCH] PCI: fix invalid window size for the ECAM config space
>
> The blamed commit forgot that pci_ecam_create() calculates the size of
> the window for the ECAM's config space based on the spacing between two
> buses. The drivers whose .bus_shift from struct pci_ecam_ops was changed
> to zero in this commit are now using this invalid value for bus_shift
> in calculating the window size.
>
> Before (broken):
> pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x1
> After (fixed/restored):
> pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x100000
>
> Fixes: f3c07cf6924e ("PCI: Unify ECAM constants in native PCI Express drivers")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/pci/ecam.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
> index 59f91d434859..9fda0d49bc93 100644
> --- a/drivers/pci/ecam.c
> +++ b/drivers/pci/ecam.c
> @@ -28,11 +28,19 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
> struct resource *cfgres, struct resource *busr,
> const struct pci_ecam_ops *ops)
> {
> + unsigned int bus_shift = ops->bus_shift;
> struct pci_config_window *cfg;
> unsigned int bus_range, bus_range_max, bsz;
> struct resource *conflict;
> int i, err;
>
> + /*
> + * struct pci_ecam_ops may omit specifying bus_shift
> + * if it is as per spec
> + */
> + if (!bus_shift)
> + bus_shift = PCIE_ECAM_BUS_SHIFT;
> +
> if (busr->start > busr->end)
> return ERR_PTR(-EINVAL);
>
> @@ -46,14 +54,14 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
> cfg->busr.end = busr->end;
> cfg->busr.flags = IORESOURCE_BUS;
> bus_range = resource_size(&cfg->busr);
> - bus_range_max = resource_size(cfgres) >> ops->bus_shift;
> + bus_range_max = resource_size(cfgres) >> bus_shift;
> if (bus_range > bus_range_max) {
> bus_range = bus_range_max;
> cfg->busr.end = busr->start + bus_range - 1;
> dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
> cfgres, &cfg->busr, busr);
> }
> - bsz = 1 << ops->bus_shift;
> + bsz = 1 << bus_shift;
>
> cfg->res.start = cfgres->start;
> cfg->res.end = cfgres->end;
> -----------------------------[cut here]-----------------------------
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Michael Walle @ 2020-12-10 19:58 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
rrichter, Vladimir Oltean, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201210173809.GA37355@bjorn-Precision-5520>
Am 2020-12-10 18:38, schrieb Bjorn Helgaas:
> On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
>> On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
>> > Hopefully my mail client won't mess up the output that much.
>>
>> I can reproduce on my LS1028A as well. The following fixes the bug for
>> me. I did not follow the discussion and see if it is helpful for
>> others.
>> I don't understand how the bug came to be. There might be more to it
>> than what I'm seeing. If it's just what I'm seeing, then the patch was
>> pretty broken to begin with.
>
> I squashed the fix below into a pci/ecam branch for v5.11, thanks!
FWIW
Tested-by: Michael Walle <michael@walle.cc>
-michael
^ permalink raw reply
* Re: linux-next: build warning after merge of the akpm tree
From: Stephen Rothwell @ 2020-12-10 21:17 UTC (permalink / raw)
To: Michael Ellerman
Cc: Kees Cook, Mathieu Malaterre, Linux Kernel Mailing List,
Nicholas Piggin, Linux Next Mailing List, Andrew Morton, PowerPC
In-Reply-To: <87im9aseam.fsf@mpe.ellerman.id.au>
[-- Attachment #1: Type: text/plain, Size: 719 bytes --]
Hi Michael,
On Thu, 10 Dec 2020 11:19:45 +1100 Michael Ellerman <mpe@ellerman.id.au> wrote:
>
> Stephen Rothwell <sfr@canb.auug.org.au> writes:
> >
> > On Wed, 09 Dec 2020 15:44:35 +1100 Michael Ellerman <mpe@ellerman.id.au> wrote:
> >>
> >> They should really be in DATA_DATA or similar shouldn't they?
> >
> > No other architecture appears t need them ...
>
> Any arch with orphan-handling=warn should see them I thought?
I did an x86_64 allyesconfig build (same compiler (more or less) and
same source) and it produces none of these sections. The only
difference in UBSAN CONFIG_ options was that CONFIG_UBSAN_UNREACHABLE
is not set in the x86_64 build.
--
Cheers,
Stephen Rothwell
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply
* Re: [PATCH v2 07/13] powerpc: Increase NR_IRQS range to support more KVM guests
From: Michael Ellerman @ 2020-12-10 23:51 UTC (permalink / raw)
To: Cédric Le Goater, linuxppc-dev; +Cc: Greg Kurz, Cédric Le Goater
In-Reply-To: <20201210171450.1933725-8-clg@kaod.org>
Cédric Le Goater <clg@kaod.org> writes:
> PowerNV systems can handle up to 4K guests and 1M interrupt numbers
> per chip. Increase the range of allowed interrupts to support a larger
> number of guests.
>
> Reviewed-by: Greg Kurz <groug@kaod.org>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/powerpc/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
> index 5181872f9452..c250fbd430d1 100644
> --- a/arch/powerpc/Kconfig
> +++ b/arch/powerpc/Kconfig
> @@ -66,7 +66,7 @@ config NEED_PER_CPU_PAGE_FIRST_CHUNK
>
> config NR_IRQS
> int "Number of virtual interrupt numbers"
> - range 32 32768
> + range 32 1048576
> default "512"
> help
> This defines the number of virtual interrupt numbers the kernel
We should really do what other arches do, and size this appropriately
based on the config, rather than asking users to guess what size they
need.
But I guess I'll take this for now, and we can do something fancier
later.
cheers
^ permalink raw reply
* Re: [PATCH 2/8] x86: use exit_lazy_tlb rather than membarrier_mm_sync_core_before_usermode
From: Andy Lutomirski @ 2020-12-11 0:11 UTC (permalink / raw)
To: Nicholas Piggin
Cc: linux-arch, Arnd Bergmann, Peter Zijlstra, X86 ML, LKML, Linux-MM,
Mathieu Desnoyers, Andy Lutomirski, linuxppc-dev
In-Reply-To: <1607224014.8xeujbleij.astroid@bobo.none>
> On Dec 5, 2020, at 7:59 PM, Nicholas Piggin <npiggin@gmail.com> wrote:
>
> I'm still going to persue shoot-lazies for the merge window. As you
> see it's about a dozen lines and a if (IS_ENABLED(... in core code.
> Your change is common code, but a significant complexity (which
> affects all archs) so needs a lot more review and testing at this
> point.
I don't think it's ready for this merge window. I read the early
patches again, and I think they make the membarrier code worse, not
better. I'm not fundamentally opposed to the shoot-lazies concept,
but it needs more thought and it needs a cleaner foundation.
^ permalink raw reply
* [GIT PULL] Please pull powerpc/linux.git powerpc-5.10-6 tag
From: Michael Ellerman @ 2020-12-11 0:25 UTC (permalink / raw)
To: Linus Torvalds; +Cc: linuxppc-dev, linux-kernel
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256
Hi Linus,
Please pull one final powerpc fix for 5.10:
The following changes since commit a1ee28117077c3bf24e5ab6324c835eaab629c45:
powerpc/64s/powernv: Fix memory corruption when saving SLB entries on MCE (2020-12-02 23:16:40 +1100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.10-6
for you to fetch changes up to 5eedf9fe8db23313df104576845cec5f481b9b60:
powerpc/mm: Fix KUAP warning by providing copy_from_kernel_nofault_allowed() (2020-12-08 10:22:09 +1100)
- ------------------------------------------------------------------
powerpc fixes for 5.10 #6
One commit to implement copy_from_kernel_nofault_allowed(), otherwise
copy_from_kernel_nofault() can trigger warnings when accessing bad addresses in
some configurations.
Thanks to:
Christophe Leroy, Qian Cai.
- ------------------------------------------------------------------
Christophe Leroy (1):
powerpc/mm: Fix KUAP warning by providing copy_from_kernel_nofault_allowed()
arch/powerpc/mm/Makefile | 2 +-
arch/powerpc/mm/maccess.c | 9 +++++++++
2 files changed, 10 insertions(+), 1 deletion(-)
create mode 100644 arch/powerpc/mm/maccess.c
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^ permalink raw reply
* Re: [GIT PULL] Please pull powerpc/linux.git powerpc-5.10-6 tag
From: pr-tracker-bot @ 2020-12-11 0:40 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Linus Torvalds, linux-kernel
In-Reply-To: <878sa5rxx4.fsf@mpe.ellerman.id.au>
The pull request you sent on Fri, 11 Dec 2020 11:25:43 +1100:
> https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git tags/powerpc-5.10-6
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/47003b9971cc7c38737f21e07034502ca35ab7af
Thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/prtracker.html
^ permalink raw reply
* Re: [PATCH v1 1/2] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE (nested case only)
From: David Gibson @ 2020-12-11 1:16 UTC (permalink / raw)
To: Bharata B Rao; +Cc: aneesh.kumar, npiggin, kvm-ppc, linuxppc-dev
In-Reply-To: <20201210042418.GA775394@in.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 2218 bytes --]
On Thu, Dec 10, 2020 at 09:54:18AM +0530, Bharata B Rao wrote:
> On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> > On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> > > Implements H_RPT_INVALIDATE hcall and supports only nested case
> > > currently.
> > >
> > > A KVM capability KVM_CAP_RPT_INVALIDATE is added to indicate the
> > > support for this hcall.
> >
> > I have a couple of questions about this patch:
> >
> > 1. Is this something that is useful today, or is it something that may
> > become useful in the future depending on future product plans? In
> > other words, what advantage is there to forcing L2 guests to use this
> > hcall instead of doing tlbie themselves?
>
> H_RPT_INVALIDATE will replace the use of the existing H_TLB_INVALIDATE
> for nested partition scoped invalidations. Implementations that want to
> off-load invalidations to the host (when GTSE=0) would have to bother
> about only one hcall (H_RPT_INVALIDATE)
>
> >
> > 2. Why does it need to be added to the default-enabled hcall list?
> >
> > There is a concern that if this is enabled by default we could get the
> > situation where a guest using it gets migrated to a host that doesn't
> > support it, which would be bad. That is the reason that all new
> > things like this are disabled by default and only enabled by userspace
> > (i.e. QEMU) in situations where we can enforce that it is available on
> > all hosts to which the VM might be migrated.
>
> As you suggested privately, I am thinking of falling back to
> H_TLB_INVALIDATE in case where this new hcall fails due to not being
> present. That should address the migration case that you mention
> above. With that and leaving the new hcall enabled by default
> is good okay?
No. Assuming that guests will have some fallback is not how the qemu
migration compatibility model works. If we specify an old machine
type, we need to provide the same environment that the older host
would have.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [powerpc:merge] BUILD SUCCESS 244569c777ca638b08c75db88fe035bdec52ef80
From: kernel test robot @ 2020-12-11 1:44 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git merge
branch HEAD: 244569c777ca638b08c75db88fe035bdec52ef80 Automatic merge of 'next' into merge (2020-12-10 00:34)
elapsed time: 2140m
configs tested: 223
configs skipped: 3
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
sh kfr2r09_defconfig
x86_64 alldefconfig
arm am200epdkit_defconfig
arm colibri_pxa270_defconfig
arm lpd270_defconfig
arm omap2plus_defconfig
mips db1xxx_defconfig
powerpc cm5200_defconfig
mips maltaup_defconfig
powerpc skiroot_defconfig
arm zx_defconfig
arm palmz72_defconfig
arm u300_defconfig
powerpc cell_defconfig
m68k m5475evb_defconfig
m68k m5407c3_defconfig
sh titan_defconfig
powerpc canyonlands_defconfig
mips ci20_defconfig
xtensa nommu_kc705_defconfig
sh se7722_defconfig
s390 allyesconfig
arm ep93xx_defconfig
powerpc wii_defconfig
xtensa cadence_csp_defconfig
mips ip28_defconfig
sh r7780mp_defconfig
powerpc lite5200b_defconfig
mips ip32_defconfig
sh migor_defconfig
sh kfr2r09-romimage_defconfig
um i386_defconfig
arc hsdk_defconfig
mips maltaup_xpa_defconfig
arm zeus_defconfig
sh se7343_defconfig
mips vocore2_defconfig
arm orion5x_defconfig
powerpc mpc836x_mds_defconfig
nds32 allnoconfig
ia64 generic_defconfig
arm xcep_defconfig
powerpc mpc83xx_defconfig
sh shx3_defconfig
arm neponset_defconfig
m68k mvme16x_defconfig
mips omega2p_defconfig
arm eseries_pxa_defconfig
arm tct_hammer_defconfig
powerpc mvme5100_defconfig
powerpc acadia_defconfig
arm imote2_defconfig
mips gcw0_defconfig
sh se7724_defconfig
arc nsimosci_hs_smp_defconfig
arm viper_defconfig
powerpc asp8347_defconfig
arm simpad_defconfig
arm socfpga_defconfig
alpha alldefconfig
arm vexpress_defconfig
powerpc makalu_defconfig
powerpc ps3_defconfig
sh se7705_defconfig
sh sh7763rdp_defconfig
sparc64 alldefconfig
h8300 defconfig
sh rsk7201_defconfig
arm vt8500_v6_v7_defconfig
mips maltasmvp_eva_defconfig
sh edosk7760_defconfig
arm imx_v6_v7_defconfig
powerpc mpc85xx_cds_defconfig
mips loongson1c_defconfig
powerpc storcenter_defconfig
arm footbridge_defconfig
arm iop32x_defconfig
mips tb0219_defconfig
mips cu1000-neo_defconfig
powerpc rainier_defconfig
m68k apollo_defconfig
arm pcm027_defconfig
mips ath25_defconfig
powerpc mpc834x_mds_defconfig
arm oxnas_v6_defconfig
s390 defconfig
sh microdev_defconfig
arm u8500_defconfig
powerpc icon_defconfig
arm spear6xx_defconfig
arm s3c6400_defconfig
mips ar7_defconfig
arm versatile_defconfig
m68k alldefconfig
sh r7785rp_defconfig
sh secureedge5410_defconfig
ia64 tiger_defconfig
arm mini2440_defconfig
sh ul2_defconfig
sh se7751_defconfig
arm mmp2_defconfig
powerpc holly_defconfig
arm h5000_defconfig
mips bcm63xx_defconfig
c6x defconfig
mips allyesconfig
mips rb532_defconfig
mips bcm47xx_defconfig
powerpc tqm8541_defconfig
arm cerfcube_defconfig
arm multi_v4t_defconfig
sh urquell_defconfig
sh sdk7786_defconfig
powerpc ppc64e_defconfig
sh sh7785lcr_32bit_defconfig
riscv nommu_k210_defconfig
powerpc mpc8540_ads_defconfig
arm tegra_defconfig
powerpc pmac32_defconfig
mips ath79_defconfig
arm shannon_defconfig
sh j2_defconfig
m68k m5249evb_defconfig
sh rts7751r2dplus_defconfig
sh rts7751r2d1_defconfig
mips bigsur_defconfig
mips xway_defconfig
mips cobalt_defconfig
mips nlm_xlp_defconfig
mips rm200_defconfig
arm mxs_defconfig
riscv alldefconfig
powerpc arches_defconfig
m68k m5272c3_defconfig
powerpc mpc837x_rdb_defconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
c6x allyesconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
parisc allyesconfig
i386 allyesconfig
sparc allyesconfig
sparc defconfig
i386 tinyconfig
i386 defconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a004-20201209
i386 randconfig-a005-20201209
i386 randconfig-a001-20201209
i386 randconfig-a002-20201209
i386 randconfig-a006-20201209
i386 randconfig-a003-20201209
i386 randconfig-a001-20201210
i386 randconfig-a004-20201210
i386 randconfig-a003-20201210
i386 randconfig-a002-20201210
i386 randconfig-a005-20201210
i386 randconfig-a006-20201210
x86_64 randconfig-a016-20201209
x86_64 randconfig-a012-20201209
x86_64 randconfig-a013-20201209
x86_64 randconfig-a014-20201209
x86_64 randconfig-a015-20201209
x86_64 randconfig-a011-20201209
i386 randconfig-a013-20201209
i386 randconfig-a014-20201209
i386 randconfig-a011-20201209
i386 randconfig-a015-20201209
i386 randconfig-a012-20201209
i386 randconfig-a016-20201209
i386 randconfig-a014-20201210
i386 randconfig-a013-20201210
i386 randconfig-a012-20201210
i386 randconfig-a011-20201210
i386 randconfig-a016-20201210
i386 randconfig-a015-20201210
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
x86_64 rhel
x86_64 allyesconfig
x86_64 rhel-7.6-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 kexec
clang tested configs:
x86_64 randconfig-a004-20201209
x86_64 randconfig-a006-20201209
x86_64 randconfig-a005-20201209
x86_64 randconfig-a001-20201209
x86_64 randconfig-a002-20201209
x86_64 randconfig-a003-20201209
x86_64 randconfig-a003-20201210
x86_64 randconfig-a006-20201210
x86_64 randconfig-a002-20201210
x86_64 randconfig-a005-20201210
x86_64 randconfig-a004-20201210
x86_64 randconfig-a001-20201210
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [powerpc:next] BUILD SUCCESS 0be47634db0baa9e91c7e635e7e73355d6a5cf43
From: kernel test robot @ 2020-12-11 1:51 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
branch HEAD: 0be47634db0baa9e91c7e635e7e73355d6a5cf43 powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
elapsed time: 726m
configs tested: 174
configs skipped: 2
The following configs have been built successfully.
More configs may be tested in the coming days.
gcc tested configs:
arm defconfig
arm64 allyesconfig
arm64 defconfig
arm allyesconfig
arm allmodconfig
arm omap2plus_defconfig
mips db1xxx_defconfig
powerpc cm5200_defconfig
mips maltaup_defconfig
powerpc skiroot_defconfig
mips ip28_defconfig
mips ci20_defconfig
sh kfr2r09-romimage_defconfig
um i386_defconfig
arc hsdk_defconfig
mips maltaup_xpa_defconfig
arm ep93xx_defconfig
arm zeus_defconfig
sh se7343_defconfig
sh migor_defconfig
mips vocore2_defconfig
arm orion5x_defconfig
powerpc mpc836x_mds_defconfig
arm eseries_pxa_defconfig
arm tct_hammer_defconfig
powerpc mvme5100_defconfig
powerpc acadia_defconfig
sh shx3_defconfig
arm imote2_defconfig
mips malta_kvm_guest_defconfig
sh sdk7780_defconfig
powerpc mpc8560_ads_defconfig
arm lubbock_defconfig
arm tango4_defconfig
mips gcw0_defconfig
powerpc asp8347_defconfig
arm simpad_defconfig
powerpc ps3_defconfig
sh se7705_defconfig
sh sh7763rdp_defconfig
sparc64 alldefconfig
h8300 defconfig
sh rsk7201_defconfig
mips loongson1c_defconfig
powerpc storcenter_defconfig
arm footbridge_defconfig
arm iop32x_defconfig
mips rs90_defconfig
arm collie_defconfig
openrisc or1ksim_defconfig
mips bcm63xx_defconfig
alpha alldefconfig
sh microdev_defconfig
arm u8500_defconfig
powerpc icon_defconfig
arm spear6xx_defconfig
arm s3c6400_defconfig
mips ar7_defconfig
arm versatile_defconfig
m68k alldefconfig
sh r7785rp_defconfig
sh secureedge5410_defconfig
ia64 tiger_defconfig
arm mini2440_defconfig
sh ul2_defconfig
c6x defconfig
mips allyesconfig
mips rb532_defconfig
mips bcm47xx_defconfig
sh urquell_defconfig
sh sdk7786_defconfig
powerpc ppc64e_defconfig
arm palmz72_defconfig
sh sh7785lcr_32bit_defconfig
arm shannon_defconfig
sh j2_defconfig
m68k m5249evb_defconfig
sh rts7751r2dplus_defconfig
powerpc mpc834x_itx_defconfig
sh alldefconfig
powerpc ppc40x_defconfig
mips rm200_defconfig
arm mxs_defconfig
riscv alldefconfig
powerpc arches_defconfig
m68k m5272c3_defconfig
powerpc mpc837x_rdb_defconfig
ia64 allmodconfig
ia64 defconfig
ia64 allyesconfig
m68k allmodconfig
m68k defconfig
m68k allyesconfig
nios2 defconfig
arc allyesconfig
nds32 allnoconfig
c6x allyesconfig
nds32 defconfig
nios2 allyesconfig
csky defconfig
alpha defconfig
alpha allyesconfig
xtensa allyesconfig
h8300 allyesconfig
arc defconfig
sh allmodconfig
parisc defconfig
s390 allyesconfig
parisc allyesconfig
s390 defconfig
i386 allyesconfig
sparc defconfig
i386 tinyconfig
i386 defconfig
sparc allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
powerpc allnoconfig
i386 randconfig-a004-20201209
i386 randconfig-a005-20201209
i386 randconfig-a001-20201209
i386 randconfig-a002-20201209
i386 randconfig-a006-20201209
i386 randconfig-a003-20201209
i386 randconfig-a001-20201210
i386 randconfig-a004-20201210
i386 randconfig-a003-20201210
i386 randconfig-a002-20201210
i386 randconfig-a005-20201210
i386 randconfig-a006-20201210
x86_64 randconfig-a016-20201209
x86_64 randconfig-a012-20201209
x86_64 randconfig-a013-20201209
x86_64 randconfig-a014-20201209
x86_64 randconfig-a015-20201209
x86_64 randconfig-a011-20201209
i386 randconfig-a013-20201209
i386 randconfig-a014-20201209
i386 randconfig-a011-20201209
i386 randconfig-a015-20201209
i386 randconfig-a012-20201209
i386 randconfig-a016-20201209
i386 randconfig-a014-20201210
i386 randconfig-a013-20201210
i386 randconfig-a012-20201210
i386 randconfig-a011-20201210
i386 randconfig-a016-20201210
i386 randconfig-a015-20201210
riscv nommu_k210_defconfig
riscv allyesconfig
riscv nommu_virt_defconfig
riscv allnoconfig
riscv defconfig
riscv rv32_defconfig
riscv allmodconfig
x86_64 rhel
x86_64 allyesconfig
x86_64 rhel-7.6-kselftests
x86_64 defconfig
x86_64 rhel-8.3
x86_64 kexec
clang tested configs:
x86_64 randconfig-a004-20201209
x86_64 randconfig-a006-20201209
x86_64 randconfig-a005-20201209
x86_64 randconfig-a001-20201209
x86_64 randconfig-a002-20201209
x86_64 randconfig-a003-20201209
x86_64 randconfig-a003-20201210
x86_64 randconfig-a006-20201210
x86_64 randconfig-a002-20201210
x86_64 randconfig-a005-20201210
x86_64 randconfig-a004-20201210
x86_64 randconfig-a001-20201210
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* [PATCH] powerpc/powernv: Rate limit opal-elog read failure message
From: Andrew Donnellan @ 2020-12-11 2:11 UTC (permalink / raw)
To: linuxppc-dev; +Cc: aneesh.kumar, mahesh, hegdevasant
Sometimes we can't read an error log from OPAL, and we print an error
message accordingly. But the OPAL userspace tools seem to like retrying a
lot, in which case we flood the kernel log with a lot of messages.
Change pr_err() to pr_err_ratelimited() to help with this.
Signed-off-by: Andrew Donnellan <ajd@linux.ibm.com>
---
arch/powerpc/platforms/powernv/opal-elog.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/opal-elog.c b/arch/powerpc/platforms/powernv/opal-elog.c
index 37b380eef41a..5821b0fa8614 100644
--- a/arch/powerpc/platforms/powernv/opal-elog.c
+++ b/arch/powerpc/platforms/powernv/opal-elog.c
@@ -171,8 +171,8 @@ static ssize_t raw_attr_read(struct file *filep, struct kobject *kobj,
opal_rc = opal_read_elog(__pa(elog->buffer),
elog->size, elog->id);
if (opal_rc != OPAL_SUCCESS) {
- pr_err("ELOG: log read failed for log-id=%llx\n",
- elog->id);
+ pr_err_ratelimited("ELOG: log read failed for log-id=%llx\n",
+ elog->id);
kfree(elog->buffer);
elog->buffer = NULL;
return -EIO;
--
2.20.1
^ permalink raw reply related
* Re: [PATCH v1 1/2] KVM: PPC: Book3S HV: Add support for H_RPT_INVALIDATE (nested case only)
From: Paul Mackerras @ 2020-12-11 5:27 UTC (permalink / raw)
To: David Gibson; +Cc: npiggin, Bharata B Rao, kvm-ppc, aneesh.kumar, linuxppc-dev
In-Reply-To: <20201211011639.GD4874@yekko.fritz.box>
On Fri, Dec 11, 2020 at 12:16:39PM +1100, David Gibson wrote:
> On Thu, Dec 10, 2020 at 09:54:18AM +0530, Bharata B Rao wrote:
> > On Wed, Dec 09, 2020 at 03:15:42PM +1100, Paul Mackerras wrote:
> > > On Mon, Oct 19, 2020 at 04:56:41PM +0530, Bharata B Rao wrote:
> > > > Implements H_RPT_INVALIDATE hcall and supports only nested case
> > > > currently.
> > > >
> > > > A KVM capability KVM_CAP_RPT_INVALIDATE is added to indicate the
> > > > support for this hcall.
> > >
> > > I have a couple of questions about this patch:
> > >
> > > 1. Is this something that is useful today, or is it something that may
> > > become useful in the future depending on future product plans? In
> > > other words, what advantage is there to forcing L2 guests to use this
> > > hcall instead of doing tlbie themselves?
> >
> > H_RPT_INVALIDATE will replace the use of the existing H_TLB_INVALIDATE
> > for nested partition scoped invalidations. Implementations that want to
> > off-load invalidations to the host (when GTSE=0) would have to bother
> > about only one hcall (H_RPT_INVALIDATE)
> >
> > >
> > > 2. Why does it need to be added to the default-enabled hcall list?
> > >
> > > There is a concern that if this is enabled by default we could get the
> > > situation where a guest using it gets migrated to a host that doesn't
> > > support it, which would be bad. That is the reason that all new
> > > things like this are disabled by default and only enabled by userspace
> > > (i.e. QEMU) in situations where we can enforce that it is available on
> > > all hosts to which the VM might be migrated.
> >
> > As you suggested privately, I am thinking of falling back to
> > H_TLB_INVALIDATE in case where this new hcall fails due to not being
> > present. That should address the migration case that you mention
> > above. With that and leaving the new hcall enabled by default
> > is good okay?
>
> No. Assuming that guests will have some fallback is not how the qemu
> migration compatibility model works. If we specify an old machine
> type, we need to provide the same environment that the older host
> would have.
I misunderstood what this patchset is about when I first looked at
it. H_RPT_INVALIDATE has two separate functions; one is to do
process-scoped invalidations for a guest when LPCR[GTSE] = 0 (i.e.,
when the guest is not permitted to do tlbie itself), and the other is
to do partition-scoped invalidations that an L1 hypervisor needs to do
on behalf of an L2 guest. The second function is a replacement and
standardization of the existing H_TLB_INVALIDATE which was introduced
with the nested virtualization code (using a hypercall number from the
platform-specific range).
This patchset only implements the second function, not the first. The
first function remains unimplemented in KVM at present.
Given that QEMU will need changes for a guest to be able to exploit
H_RPT_INVALIDATE (at a minimum, adding a device tree property), it
doesn't seem onerous for QEMU to have to enable the hcall with
KVM_CAP_PPC_ENABLE_HCALL. I think that the control on whether the
hcall is handled in KVM along with the control on nested hypervisor
function provides adequate control for QEMU without needing a writable
capability. The read-only capability to say whether the hcall exists
does seem useful.
Given all that, I'm veering towards taking Bharata's patchset pretty
much as-is, minus the addition of H_RPT_INVALIDATE to the
default-enabled set.
Paul.
^ permalink raw reply
* Re: [PATCH v2 07/13] powerpc: Increase NR_IRQS range to support more KVM guests
From: Cédric Le Goater @ 2020-12-11 8:14 UTC (permalink / raw)
To: Michael Ellerman, linuxppc-dev; +Cc: Greg Kurz
In-Reply-To: <87czzhrzhk.fsf@mpe.ellerman.id.au>
On 12/11/20 12:51 AM, Michael Ellerman wrote:
> Cédric Le Goater <clg@kaod.org> writes:
>> PowerNV systems can handle up to 4K guests and 1M interrupt numbers
>> per chip. Increase the range of allowed interrupts to support a larger
>> number of guests.
>>
>> Reviewed-by: Greg Kurz <groug@kaod.org>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> arch/powerpc/Kconfig | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
>> index 5181872f9452..c250fbd430d1 100644
>> --- a/arch/powerpc/Kconfig
>> +++ b/arch/powerpc/Kconfig
>> @@ -66,7 +66,7 @@ config NEED_PER_CPU_PAGE_FIRST_CHUNK
>>
>> config NR_IRQS
>> int "Number of virtual interrupt numbers"
>> - range 32 32768
>> + range 32 1048576
>> default "512"
>> help
>> This defines the number of virtual interrupt numbers the kernel
>
> We should really do what other arches do, and size this appropriately
> based on the config, rather than asking users to guess what size they
> need.
>
> But I guess I'll take this for now, and we can do something fancier
> later.
I was thinking on adding a property to OPAL to size the HW interrupt
number space. Is that it ? That would be good because it's increasing
from 20bits on P9 to 24bits on P10.
I am checking other arches.
Thanks,
C.
^ permalink raw reply
* [PATCH] net: fs_enet: remove casting dma_alloc_coherent
From: Xu Wang @ 2020-12-11 8:48 UTC (permalink / raw)
To: pantelis.antoniou, davem, kuba, linuxppc-dev; +Cc: linux-kernel
Remove casting the values returned by dma_alloc_coherent.
Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
---
drivers/net/ethernet/freescale/fs_enet/mac-fcc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c b/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
index b47490be872c..17f757c0bb85 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mac-fcc.c
@@ -147,7 +147,7 @@ static int allocate_bd(struct net_device *dev)
struct fs_enet_private *fep = netdev_priv(dev);
const struct fs_platform_info *fpi = fep->fpi;
- fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev,
+ fep->ring_base = dma_alloc_coherent(fep->dev,
(fpi->tx_ring + fpi->rx_ring) *
sizeof(cbd_t), &fep->ring_mem_addr,
GFP_KERNEL);
--
2.17.1
^ permalink raw reply related
* [PATCH] net: ethernet: fs-enet: remove casting dma_alloc_coherent
From: Xu Wang @ 2020-12-11 8:52 UTC (permalink / raw)
To: pantelis.antoniou, davem, kuba, linuxppc-dev; +Cc: linux-kernel
Remove casting the values returned by dma_alloc_coherent.
Signed-off-by: Xu Wang <vulab@iscas.ac.cn>
---
drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
index 99fe2c210d0f..3ae345676e50 100644
--- a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
+++ b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c
@@ -131,7 +131,7 @@ static int allocate_bd(struct net_device *dev)
struct fs_enet_private *fep = netdev_priv(dev);
const struct fs_platform_info *fpi = fep->fpi;
- fep->ring_base = (void __force __iomem *)dma_alloc_coherent(fep->dev,
+ fep->ring_base = dma_alloc_coherent(fep->dev,
(fpi->tx_ring + fpi->rx_ring) *
sizeof(cbd_t), &fep->ring_mem_addr,
GFP_KERNEL);
--
2.17.1
^ permalink raw reply related
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